TC74ACT640FT

TC51WHM516AXBN65,70 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAM DESCRIPTION The TC51WHM516AXBN is a 33,554,432-bit pseudo static random access memory(PSRAM) organized as 2,097,152 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high density, high speed and low power. The device operates single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports deep power-down mode, realizing low-power standby. FEATURES • • • • • • • Organized as 2,097,152 words by 16 bits Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: Page read operation by 8 words Logic compatible with SRAM R/W ( WE ) pin Standby current Standby 70 µA Deep power-down standby 5 µA • Access Times: TC51WHM516AXBN 65 Access Time CE1 Access Time 70 70 ns 70 ns 25 ns 30 ns 65 ns 65 ns 25 ns 30 ns OE Access Time Page Access Time • Package: P-TFBGA48-0607-0.75AZ (Weight: g typ.) PIN ASSIGNMENT (TOP VIEW) 1 A B C D E F G H 2 OE UB I/O11 I/O12 I/O13 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O2 I/O4 I/O5 I/O6 6 CE2 I/O1 I/O3 VDD VSS I/O7 I/O8 A20 PIN NAMES A0 to A20 A0 to A2 Address Inputs Page Address Inputs LB I/O9 I/O10 VSS VDD I/O1 to I/O16 Data Inputs/Outputs CE1 Chip Enable Input Chip select Input Write Enable Input Output Enable Input Data Byte Control Inputs Power Ground No Connection CE2 WE OE I/O15 I/O14 I/O16 A18 A19 A8 WE A11 LB , UB VDD GND NC (FBGA48) 2002-08-22 1/11 TC51WHM516AXBN65,70 BLOCK DIAGRAM CE A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 DATA INPUT BUFFER VDD GND MEMORY CELL ARRAY 4,096 × 512 × 16 (33,554,432) ROW ADDRESS BUFFER ROW ADDRESS DECODER SENSE AMP DATA OUTPUT BUFFER CE I/O9 to I/O16 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z DATA INPUT BUFFER COLUMN ADDRESS DECODER REFRESH ADDRESS COUNTER REFRESH CONTROL COLUMN ADDRESS BUFFER CONTROL SIGNAL A0 A1 A2 A3 A4 A5 A6 A7 A8 GENERATOR WE OE UB LB CE1 CE CE2 OPERATION MODE MODE Read(Word) Read(Lower Byte) Read(Upper Byte) Write(Word) Write(Lower Byte) Write(Upper Byte) Outputs Disabled Standby Deep Power-down Standby Notes: L = Low-level Input(VIL), CE1 CE2 H H H H H H H H L OE WE H H H L L L H X X LB L L H L L H X X X UB Add X X X X X X X X X I/O1 to I/O8 DOUT DOUT High-Z DIN DIN Invalid High-Z High-Z High-Z DATA OUTPUT BUFFER POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDSD L L L L L L L H H L L L X X X H X X L H L L H L X X X H = High-level Input(VIH), X = VIH or VIL, High-Z = High-impedance 2002-08-22 2/11 TC51WHM516AXBN65,70 ABSOLUTE MAXIMUM RATINGS (See Note 1) SYMBOL VDD VIN VOUT Topr. Tstrg. Tsolder PD IOUT Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Soldering Temperature (10 s) Power Dissipation Short Circuit Output Current RATING VALUE −1.0 to 3.6 −1.0 to 3.6 −1.0 to 3.6 −25 to 85 −55 to 150 260 0.6 50 UNIT V V V °C °C °C W mA DC RECOMMENDED OPERATING CONDITIONS (Ta = −25°C to 85°C) SYMBOL VDD VIH VIL PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage MIN 2.6 2.0 −0.3* TYP. 2.75   MAX 3.3 VDD + 0.3* 0.4 V UNIT * : VIH(Max) VDD+1.0 V with 10 ns pulse width VIL(Min) -1.0 V with 10 ns pulse width DC CHARACTERISTICS (Ta = −25°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 3 to 4) SYMBOL IIL ILO VOH VOL IDDO1 IDDO2 IDDS IDDSD PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current TEST CONDITION VIN = 0 V to VDD Output disable, VOUT = 0 V to VDD IOH = − 0.5 mA IOL = 1.0 mA CE1 = VIL CE2 = VIH, IOUT = 0 mA CE1 = VIL, CE2 = VIH, Page add. cycling, IOUT = 0 mA MIN −1.0 −1.0 2.0  tRC = min tPC = min     TYP.         MAX +1.0 +1.0  0.4 40 UNIT µA µA V V mA Page Access Operating Current Standby Current(MOS) Deep Power-down Standby Current 25 70 5 mA µA µA CE1 = VDD − 0.2 V, CE2 = VDD − 0.2 V CE2 = 0.2 V CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance TEST CONDITION VIN = GND VOUT = GND MAX 10 10 UNIT pF pF Note: This parameter is sampled periodically and is not 100% tested. 2002-08-22 3/11 TC51WHM516AXBN65,70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −25°C to 85°C, VDD = 2.6 to 3.3 V) (See Note 5 to 11) SYMBOL PARAMETER MIN tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tPM tPC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP Read Cycle Time Address Access Time Chip Enable ( CE1 ) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time Page Mode Time Page Mode Cycle Time Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1 CE2 Hold from Power On 65     10 0 0    10 65 30  10 65 50 65 60 60 0 0  0 30 0 0 300 10 0 30 65 MAX 10000 65 65 25 25    20 20 20  10000  30  10000       20         MIN 70     10 0 0    10 70 30  10 70 50 70 60 60 0 0  0 30 0 0 300 10 0 30 TC51WHM516AXBN 70 MAX 10000 70 70 25 25    20 20 20  10000  30  10000       20         ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms ns µs UNIT AC TEST CONDITIONS PARAMETER Output load Input pulse level Timing measurements Reference level t R, t F CONDITION 30 pF + 1 TTL Gate VDD − 0.2 V, 0.2 V VDD × 0.5 VDD× 0.5 5 ns 2002-08-22 4/11 TC51WHM516AXBN65,70 TIMING DIAGRAMS READ CYCLE tRC Address A0 to A20 tACC tCO CE1 tOH CE2 tOE OE Fix-H tOD tODO WE tBA UB , LB tBE DOUT I/O1 to I/O16 tOEE Hi-Z tCOE INDETERMINATE tBD VALID DATA OUT Hi-Z PAGE READ CYCLE (8 words access) tPM Address A0 to A2 Address A3 to A20 tRC tPC tPC tPC CE1 CE2 OE Fix-H WE UB , LB tBA tOEE DOUT I/O1 to I/O16 tBE Hi-Z tCOE tCO tACC tOE tAOH DOUT tAA DOUT tAA tAOH DOUT tAOH tBD tOH DOUT tOD Hi-Z tAA tODO * Maximum 8 words 2002-08-22 5/11 TC51WHM516AXBN65,70 WRITE CYCLE 1 ( WE CONTROLLED) (See Note 8) tWC Address A0 to A20 tAS WE tAW tWP tWR tCW CE1 tWR tCH CE2 tBW UB , LB tWR tODW DOUT I/O1 to I/O16 DIN I/O1 to I/O16 (See Note 10) Hi-Z tDS (See Note 9) tOEW (See Note 11) tDH (See Note 9) VALID DATA IN WRITE CYCLE 2 ( CE CONTROLLED) (See Note 8) tWC Address A0 to A20 tAS WE tAW tWP tWR tCW CE1 tWR tCH CE2 tBW UB , LB tWR tBE DOUT I/O1 to I/O16 Hi-Z tCOE tODW Hi-Z tDS tDH DIN I/O1 to I/O16 (See Note 9) VALID DATA IN 2002-08-22 6/11 TC51WHM516AXBN65,70 WRITE CYCLE 3 ( UB , LB CONTROLLED) (See Note 8) tWC Address A0 to A20 tAW tAS WE tWP tWR tCW CE1 tCH CE2 tCW tBW UB , LB tBE DOUT I/O1 to I/O16 Hi-Z tCOE tODW Hi-Z tDS tDH DIN I/O1 to I/O16 (See Note 9) VALID DATA IN 2002-08-22 7/11 TC51WHM516AXBN65,70 Deep Power-down Timing CE1 tDPD CE2 tCS tCH Power-on Timing VDD VDD min CE1 tCHC CE2 tCHP tCH Provisions of Address Skew Read In case, multiple invalid address cycles shorter than tRCmin sustain over 10µs in a active status, as least one valid address cycle over tRCmin must be needed during 10µs. over 10µs CE1 WE Address tRCmin Write In case, multiple invalid address cycles shorter than tWCmin sustain over 10µs in a active status, as least one valid address cycle over tWCmin with tWPmin must be needed during 10µs. over 10µs CE1 tWPmin WE Address tWCmin 2002-08-22 8/11 TC51WHM516AXBN65,70 Notes: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Stresses greater than listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are reference to GND. IDDO depends on the cycle time. IDDO depends on output loading. Specified values are defined with the output open condition. AC measurements are assumed tR, tF = 5 ns. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. Data cannot be retained at deep power-down stand-by mode. If OE is high during the write cycle, the outputs will remain at high impedance. During the output state of I/O signals, input signals of reverse polarity must not be applied. If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedance. If CE1 or LB / UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedance. 2002-08-22 9/11 TC51WHM516AXBN65,70 PACKAGE DIMENSIONS P-TFBGA48-0607-0.75AZ 0.2 S A Unit:mm 0.2 S B 7.0 4 0.15 0.1 S S 0.28 0.05 0.375 6.0 0.1 S 0.43 0.05 B A B C D E F G H φ0.08 M S AB 1.2 max 1.125 A 1 2 3 4 5 0.375 (5.25) 0.75 0.875 Weight: g (typ) 0.75 6 (3.75) 2002-08-22 10/11 TC51WHM516AXBN65,70 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2002-08-22 11/11