TC74HC4538AFT

TC74HC4538AP/AF/AFN/AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC4538AP,TC74HC4538AF,TC74HC4538AFN,TC74HC4538AFT Dual Retriggerable Monostable Multivibrator The TC74HC4538A is a high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There are two trigger inputs, A input (positive edge input), and B input (negative edge input). These inputs are valid for a slow rise/fall time signal (tr = tf = 1 s) as they are schmitt trigger inputs. After triggering, the output stays in a MONOSTABLE state for the time period determined by the external resistor and capacitor (RX, CX). A low level at CD input breaks this STABLE STATE. In the MONOSTABLE state, if a new trigger is applied, it makes the MONOSTABLE period longer (retrigger mode). Limitations for CX and RX are as follows: External capacitor CX ........... No limitation External resistor RX .............. VCC = 2.0 V more than 5 kΩ VCC ≥ 3.0 V more than 1 kΩ All inputs are equipped with protection circuits against static discharge or transient excess voltage. Note: The JEDEC SOP (FN) is not available in Japan. TC74HC4538AP TC74HC4538AF Features (Note) • • TC74HC4538AFN High speed: tpd = 25 ns (typ.) at VCC = 5 V Low power dissipation Stand by state: ICC = 4 μA (max) at Ta = 25°C Active state: ICC = 300 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 10 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 4 mA (min) ∼ Balanced propagation delays: tpLH − tpHL Wide operating voltage range: VCC (opr) = 2 V to 6 V Pin and function compatible with 4538B Note: In the case of using only one circuit, CD should be tied to GND, T1·T2·Q· Q should be tied to OPEN, the other inputs should be tied to VCC or GND. TC74HC4538AFT • • • • • • Weight DIP16-P-300-2.54A SOP16-P-300.1.27A SOL16-P-150-1.27 TSSOP16-P-0044-0.65A : 1.00 g (typ.) : 0.18 (typ.) : 0.13 g (typ.) : 0.06 g (typ. 1 2007-10-01 TC74HC4538AP/AF/AFN/AFT Pin Assignment IEC Logic Symbol (4) (5) (3) (1) (2) (12) (11) (13) (15) (14) & (6) R CX RX/CX & R CX RX/CX (7) 1Q 1T1 1T2 1 2 3 4 5 6 7 8 (top view) 16 15 14 13 12 11 10 9 VCC 2T1 2T2 2CD 1A 1B 1CD 1CD 1A 1T1 1T2 2A 2B 2CD 1Q 1B 1Q 2A 2B (10) (9) 2Q 2Q 1Q GND 2Q 2Q 2T1 2T2 Truth Table Inputs A B CD Outputs Q Q Note Output Enable H X H L X X L X H H H H L L H L L H H Inhibit Inhibit Output Enable Reset X: Don’t care 2 2007-10-01 TC74HC4538AP/AF/AFN/AFT Block Diagram (Note 1)(Note 2) DX CX 1 T1 A B 4 5 7 3 CD DX VCC CX RX 15 6 T1 Q A B Q 13 CD 2 T2 RX VCC 14 T2 10 Q 12 11 9 Q Note 1: CX, RX, DX are external. Capacitor, resistor, and diode, respectively. Note 2: External clamping diode, DX The external capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied. Supply voltage is turned off and CX is discharged mainly through the internal (parasitic) diode. If CX is sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC by rush current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the rush current is automatically limited and damage to the IC is avoided. The maximum value of forward current through the parasitic diode is ±20 mA. In the case of a large CX, the limitation of fall time of the supply voltage is determined as follows: tf ≥ (VCC − 0.7) CX/20 mA (tf is the time from the voltage supply turning off to the level of supply voltage reaching 0.4 VCC.) In the care of a system that does not satisfy the above condition, an external clamping diode is needed to protect the IC from rush current. 3 2007-10-01 TC74HC4538AP/AF/AFN/AFT System Diagram VCC VrefL QP C1 C2 VrefH T2 QN T1 VCC DRQ A B CK F/F Q Q Q CD Timing Chart trr VIH A B VIL VIH VIL T2 CD VCC VrefH VrefL GND VIH VIL VOH Q VOL VOH Q twOUT twOUT twOUT + trr VOL 4 2007-10-01 TC74HC4538AP/AF/AFN/AFT Functional Description (1) Stand-by state The external capacitor is fully charge to VCC in the stand-by state. That means, before triggering, QP and QN transistors which are connected to the T2 node are in the off state. Two comparators that relate to the timing of the output pulse, and two reference voltage supplies stop their operation. The total supply current is only leakage current. Trigger operation Trigger operation is effective in either of the following two cases. One is the condition where the A input is low, and the B input has a falling signal. The other, where the B input is high, and the A input has a rising signal. After trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The external capacitor discharges through QN. The voltage level at the T2 node drops. If the T2 voltage level falls to the internal reference voltage VrefL, the output of C1 becomes low. The flip-flop is then reset and QN turns off. At that moment C1 stops but C2 continues operating. After QN turns off, the voltage at T2 start rising at a rate determined by the time constant of external capacitor CX and resistor RX. After the triggering, output Q becomes high, following some delay time of the internal F/F and gates. It stays high even if the voltage of T2 changes from falling to rising. When T2 reaches the internal reference voltage VrefH, the output of C2 becomes low, the output Q goes low and C2 stops its operation. That means, after triggering, when the voltage level of T2 reaches VrefH, the IC returns to its MONOSTABLE state. In the case of large value of CX and RX, and ignoring the discharge time of the capacitor and internal delays of the IC, the width of the output pulse, (twOUT), is as follows: twOUT = 0.70·CX·RX Retrigger operation When another new trigger is applied to input A or B while in the MONOSTABLE state, it is effective only if the IC is charging CX. The voltage level of T2 then falls to VrefL level again. Therefore the Q output stays high if the next trigger comes in before the time period set by CX and RX. If the 2nd trigger is very close to previous trigger, such as application during the discharge cycle, the nd trigger will not be effective. 2 The minimum time for effective 2nd trigger, trr (min), depends on VCC and CX. Reset operation In normal operation, CD input is held high. If CD is low, a trigger has no effect because the Q output is held low and the trigger control F/F is reset. Also QP turns on and CX is charged rapidly to VCC. This means if CD input is set low, the IC goes into a wait state. (2) (3) (4) 5 2007-10-01 TC74HC4538AP/AF/AFN/AFT Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating −0.5 to 7 −0.5 to VCC + 0.5 −0.5 to VCC + 0.5 ±20 ±20 ±25 ±50 500 (DIP) (Note 2)/180 (SOP/TSSOP) −65 to 150 Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40°C to 65°C. From Ta = 65°C to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. Operating Ranges (Note 1) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time ( CD only) External capacitor External resistor Symbol VCC VIN VOUT Topr Rating 2 to 6 0 to VCC 0 to VCC −40 to 85 0 to 1000 (VCC = 2.0 V) tr, tf 0 to 500 (VCC = 4.5 V) 0 to 400 (VCC = 6.5 V) CX RX No limitation (Note 2) ≥ 5 k (Note 5) (VCC = 2.0 V) ≥ 1 k (Note 5) (VCC ≥ 3.0 V) F Ω ns Unit V V V °C Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 2: The maximum allowable values of CX and RX are a function of leakage of capacitor CX, the leakage of TC74HC4538A, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ. 6 2007-10-01 TC74HC4538AP/AF/AFN/AFT Electrical Characteristics DC Characteristics Test Condition Characteristics Symbol VCC (V) 2.0 High-level input voltage VIH ― 4.5 6.0 2.0 Low-level input voltage VIL ― 4.5 6.0 2.0 High-level output voltage (Q, Q ) VIN = VIH or VIL IOH = −20 μA 4.5 6.0 IOH = −4 mA IOH = −5.2 mA 4.5 6.0 2.0 Low-level output voltage (Q, Q ) VIN = VIH or VIL IOL = 20 μA 4.5 6.0 IOL = 4 mA IOL = 5.2 mA Input leakage current T2 terminal input leakage current Quiescent supply current Active-state supply current (Note) IIN IIN ICC VIN = VCC or GND VIN = VCC or GND VIN = VCC or GND VIN = VCC or GND T2 ext = 0.5 VCC 4.5 6.0 6.0 6.0 6.0 2.0 4.5 6.0 Min 1.50 3.15 4.20 ― ― ― 1.9 4.4 5.9 4.18 5.68 ― ― ― ― ― ― ― ― ― ― ― Ta = 25°C Typ. ― ― ― ― ― ― 2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18 ― ― ― 40 200 300 Max ― ― ― 0.50 1.35 1.80 ― ― ― ― ― 0.1 0.1 0.1 0.26 0.26 ±0.1 ±0.5 4.0 120 300 600 Ta = −40 to 85°C Min 1.50 3.15 4.20 ― ― ― 1.9 4.4 5.9 4.13 5.63 ― ― ― ― ― ― ― ― ― ― ― Max ― ― ― 0.50 1.35 1.80 ― ― ― ― ― 0.1 0.1 0.1 0.33 0.33 ±1.0 ±5.0 40.0 160 400 800 μA μA μA μA V V V V Unit VOH VOL ICC Note: Per circuit 7 2007-10-01 TC74HC4538AP/AF/AFN/AFT Timing Requirements (input: tr = tf = 6 ns) Characteristics Symbol Test Condition VCC (V) Minimum pulse width (A, B ) tw (L) tw (H) 2.0 ― 4.5 6.0 2.0 tw (L) ― 4.5 6.0 2.0 Minimum clear removal time trem ― 4.5 6.0 RX = 1 kΩ CX = 100 pF Minimum retrigger time trr RX = 1 kΩ CX = 0.01 μF 2.0 4.5 6.0 2.0 4.5 6.0 Ta = 25°C Typ. ― ― ― ― ― ― ― ― ― 380 92 72 6.0 1.4 1.2 Limit 75 15 13 75 15 13 15 5 5 ― ― ― ― ― ― Ta = −40 to 85°C Limit 95 19 16 95 19 16 15 5 5 ― ― ― ― ― ― μs ns ns ns ns Unit Minimum clear width ( CD ) AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns) Characteristics Output transition time Propagation delay time (A, B -Q, Q ) Propagation delay time ( CD -Q, Q ) Symbol tTLH tTHL tpLH tpHL tpLH tpHL Test Condition ― Min ― Typ. 6 Max 12 Unit ns ― ― 25 44 ns ― ― 21 34 ns 8 2007-10-01 TC74HC4538AP/AF/AFN/AFT AC Characteristics (CL = 50 pF, input: tr = tf = 6 ns) Characteristics Symbol Test Condition VCC (V) tTLH tTHL 2.0 ― 4.5 6.0 2.0 ― 4.5 6.0 2.0 ― 4.5 6.0 CX = 0 F RX = 5 kΩ (VCC = 2 V) RX = 1 kΩ (VCC = 4.5 V, 6 V) Output pulse width twOUT CX = 0.01 μF RX = 10 kΩ 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 ― ― (Note) ― Min ― ― ― ― ― ― ― ― ― ― ― ― 70 69 69 0.67 0.67 0.67 ― ― ― Ta = 25°C Typ. 30 8 7 120 30 25 100 25 20 540 180 150 83 77 77 0.75 0.73 0.73 ±1 5 70 Max 75 15 13 250 50 43 195 39 33 1200 250 200 96 85 85 0.83 0.77 0.77 ― 10 ― Ta = −40 to 85°C Min ― ― ― ― ― ― ― ― ― ― ― ― 70 69 69 0.67 0.67 0.67 ― ― ― Max 95 19 16 315 63 54 245 49 42 1500 320 260 96 85 85 0.83 0.77 0.77 ― 10 ― % pF pF ms μs ns ns ns ns Unit Output transition time Propagation delay time (A, B -Q, Q ) Propagation delay time ( CD -Q, Q ) tpLH tpHL tpLH tpHL CX = 0.1 μF RX = 10 kΩ Output pulse width error between circuits (in same package) Input capacitance Power dissipation capacitance CIN CPD ΔtwOUT Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC’·Duty/100 + ICC/2 (per circuit) (ICC’: active supply current) (duty: %) 9 2007-10-01 TC74HC4538AP/AF/AFN/AFT Output Pulse Width Constant K – Supply Voltage (typical) (external resistor (RX) = 10 kΩ: twOUT = K·CX·RX) Output pulse width constant K 0.9 0.8 CX = 0.01 μF CX = 0.1 μF 0.7 CX = 1 μF 2 3 4 5 6 Supply voltage VCC (V) twOUT – CX Characteristics (typical) VCC = 4.5 V CL = 50 pF RX = 1 MΩ 10 3 trr – VCC Characteristics (typical) Ta = 25°C Minimum retrigger time trr (μs) 10 CX = 0.01 μF 1 CX = 1000 pF 0.1 CX = 100 pF Output pulse width twOUT (μs) RX = 100 kΩ 102 RX = 10 kΩ 10 RX = 1 kΩ 0 1 2 3 4 5 6 Supply voltage 1 VCC (V) 10−1 102 103 104 External capacitor CX (pF) 10 2007-10-01 TC74HC4538AP/AF/AFN/AFT Package Dimensions Weight: 1.00 g (typ.) 11 2007-10-01 TC74HC4538AP/AF/AFN/AFT Package Dimensions Weight: 0.18 g (typ.) 12 2007-10-01 TC74HC4538AP/AF/AFN/AFT Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.13 g (typ.) 13 2007-10-01 TC74HC4538AP/AF/AFN/AFT Package Dimensions Weight: 0.06 g (typ.) 14 2007-10-01 TC74HC4538AP/AF/AFN/AFT RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN GENERAL • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 15 2007-10-01