TC74HCT646AP_07

TC74HCT646AP TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT646AP Octal Bus Transceiver/Register (3-state) The TC74HCT646A is high speed CMOS OCTAL BUS TRANSCEIVER/REGISTERs fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Its inputs are compatible with TTL, NMOS, and CMOS output voltage levels. This device is bus transceiver with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the internal registers. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Weight: 1.50 g (typ.) Features (Note 1)(Note 2) • • • • • • • High speed: fmax = 60 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 μA (max) at Ta = 25°C Compatible with TTL output: VIH = 2.0 V (min) VIL = 0.8 V (max) Output drive capability: 15 LSTTL loads Symmetrical output impedance: |IOH| = IOL = 6 mA (min) ∼ Balanced propagation delays: tpLH − tpHL Pin and function compatible with 74LS646 Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result. Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull down resistors. Pin Assignment 1 2007-10-01 TC74HCT646AP IEC Logic Symbol Truth Table G DIR CAB X H X (Note) CBA X (Note) SAB X SBA X A Inputs Z X Inputs L X L H L X L H X L H Outputs X L L H X X (Note) L L H Qn L H B Inputs Z X Outputs L H L H Qn L H Inputs L H L H X L H The data on the B bus are displayed on the A bus, and are stored into the B storage flip-flops on the rising edge of CBA. The data in the B storage flip-flops are displayed on the A bus. The data on the B bus are stored into the B storage flip-flops on the rising edge of CBA, and the stored data propagate directly onto the A bus. The data on the B bus are displayed on the A bus. The data on the A bus are displayed on the B bus, and are stored into the A storage flip-flops on the rising edge of CAB. The data in the A storage flip-flops are displayed on the B bus. The data on the A bus are stored into the A storage flip-flops on the rising edge of CAB, and the stored data propagate directly onto the B bus. The data on the A bus are displayed on the B bus. Function The output functions of A and B busses are disabled. Both A and B busses are used as inputs to the internal flip-flops. Data on the bus will be stored on the rising edge of the clock. X X X (Note) X (Note) X L H X (Note) (Note) X (Note) X (Note) X (Note) X X (Note) H X H X L L (Note) X (Note) X (Note) X H X H X: Don’t care Qn: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs. Z: High impedance Note: The clock are not internally gated with either G or DIR. Therefore, data on the A and/or B busses may be clocked into the storage flip-flops at any time. 2 2007-10-01 TC74HCT646AP Timing Chart System Diagram 3 2007-10-01 TC74HCT646AP Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating −0.5~7.0 −0.5~VCC + 0.5 −0.5~VCC + 0.5 ±20 ±20 ±35 ±75 500 (DIP) −65~150 (Note 2) Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. Operating Ranges (Note) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr tr, tf Rating 4.5~5.5 0~VCC 0~VCC −40~85 0~500 Unit V V V °C ns Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 4 2007-10-01 TC74HCT646AP Electrical Characteristics DC Characteristics Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage 3-state output off state current Input leakage current Quiescent supply current Symbol Test Condition VCC (V) ⎯ ⎯ IOH = −20 μA VIN = VIH or VIL I OH = −6 mA IOL = 20 μA VIN = VIH or VIL I = 6 mA OL VIN = VIH or VIL VOUT = VCC or GND VIN = VCC or GND VIN = VCC or GND Per input: VIN = 0.5 V or 2.4 V Other input: VCC or GND 4.5~5.5 4.5~5.5 4.5 4.5 4.5 4.5 5.5 5.5 5.5 5.5 Min 2.0 ⎯ 4.4 4.18 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Ta = 25°C Typ. ⎯ ⎯ 4.5 4.31 0.0 0.17 ⎯ ⎯ ⎯ ⎯ Max ⎯ 0.8 ⎯ ⎯ 0.1 0.26 ±0.5 ±0.1 4.0 2.0 Ta = −40~85°C Min 2.0 ⎯ 4.4 4.13 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max ⎯ 0.8 ⎯ ⎯ 0.1 0.33 ±5.0 ±1.0 40.0 2.9 Unit VIH VIL VOH V V V VOL V IOZ IIN ICC IC μA μA μA mA Timing Requirements (input: tr = tf = 6 ns) Characteristics Symbol Test Condition VCC (V) Minimum pulse width (CK) Minimum set-up time tW (L) tW (H) ts ⎯ 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 Ta = 25°C Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Limit 15 14 10 9 5 5 31 37 Ta = −40 ~85°C Limit 19 17 13 12 5 5 25 30 ns Unit ⎯ ns Minimum hold time th ⎯ ns Clock frequency f ⎯ MHz 5 2007-10-01 TC74HCT646AP AC Characteristics (input: tr = tf = 6 ns) Characteristics Symbol tTLH tTHL tpLH tpHL Test Condition CL (pF) VCC (V) ⎯ 50 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 31 37 ⎯ ⎯ ⎯ ⎯ Ta = 25°C Typ. 7 6 20 17 25 22 29 26 34 31 24 21 29 26 26 23 31 28 26 23 55 61 5 13 40 Max 12 11 30 27 38 34 44 40 52 47 34 31 42 38 38 34 46 41 35 32 ⎯ ⎯ 10 ⎯ ⎯ Ta = −40~85°C Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 25 30 ⎯ ⎯ ⎯ Max 15 14 38 34 48 43 55 50 65 59 43 39 53 46 48 43 58 52 44 40 ⎯ ⎯ 10 ⎯ ⎯ ns ns ns ns ns Unit Output transition time ns Propagation delay time (BUS-bus) 50 ⎯ 150 Propagation delay time (CAB, CBA-bus) tpLH tpHL 50 ⎯ 150 Propagation delay time (SAB, SBA-bus) tpLH tpHL 50 ⎯ 150 Output enable time (DIR, G -bus) tpZL tpZH 50 RL = 1 kΩ 150 Output disable time (DIR, G -bus) Maximum clock frequency Input capacitance Output capacitance Power dissipation capacitance tpLZ tpHZ fmax CIN CI/O CPD (Note) RL = 1 kΩ ⎯ 50 50 MHz pF pF pF DIR, G , SAB, SBA, CAB, CBA An, Bn Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC/8 (per bit) 6 2007-10-01 TC74HCT646AP Package Dimensions Weight: 1.50 g (typ.) 7 2007-10-01 TC74HCT646AP RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN GENERAL • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 8 2007-10-01