TC74VHC4053AFK(E,K

TC74VHC4051,4052,4053AF/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC4051AF, TC74VHC4051AFK TC74VHC4052AF, TC74VHC4052AFK TC74VHC4053AF, TC74VHC4053AFK TC74VHC4051AF/AFK 8-Channel Analog Multiplexer/Demultiplexer TC74VHC4052AF/AFK Dual 4-Channel Analog Multiplexer/Demultiplexer TC74V4053AF/AFK Triple 2-Channel Analog Multiplexer/Demultiplexer TC74VHC4051AF, TC74VHC4052AF, TC74VHC4053AF The TC74VHC4051A/4052A/4053A are high-speed, low-voltage drive analog multiplexer/demultiplexers using silicon gate CMOS technology. TC74VHC4051AFK, TC74VHC4052AFK, In 3 V and 5 V systems these can achieve high-speed operation with the TC74VHC4053AFK low power dissipation that is a feature of CMOS. The TC74VHC4051A/4052A/4053A offer analog/digital signal selection as well as mixed signals. The 4051A has an 8-channel configuration, the 4052A has an 4-channel × 2 configuration, and the 4053A has a 2-channel × 3 configuration. The switches for each channel are turned ON by the control pin digital signals. All control inputs are equipped with a newly developed input protection circuit that avoids the need for a diode on the plus side (forward side from the input to the VCC). As a result, for example, 5.5 V signals can be permitted on the inputs even when the power supply voltage to the circuits SOP16-P-300-1.27A : 0.18 g ( typ.) is off. As a result of this input power protection, the VSSOP16-P-0030-0.50 : 0.02 g ( typ.) TC74VHC4051A/4052A/4053A can be used in a variety of applications, including in the system which has two power supplies, and in battery backup circuits. Features  Low ON-resistance: Ron = 45 Ω (typ.) (VCC = 3 V)  Low power dissipation: ICC = 2.0 μA (max) (Ta = 25°C)  Input level: Ron = 24 Ω (typ.) (VCC = 4.5 V) VIL = 0.8 V (max) (VCC = 3 V) VIH = 2.0 V (min) (VCC = 3 V)  Power down protection is provided on all control inputs Start of commercial production 2007-01 © 2019 Toshiba Electronic Devices & Storage Corporation 1 2019-01-31 TC74VHC4051,4052,4053AF/FK Pin Assignment (top view) TC74VHC4051A TC74VHC4052A 4 1 16 VCC 0Y 1 16 VCC 6 2 15 2 2Y 2 15 2X COM 3 14 1 Y-COM 3 14 1X 7 4 13 0 3Y 4 13 X-COM 5 5 12 3 1Y 5 12 0X INH 6 11 A INH 6 11 3X GND 7 10 B GND 7 10 A GND 8 9 GND 8 9 C B TC74VHC4053A 1Y 1 16 VCC 0Y 2 15 Y-COM 1Z 3 14 X-COM Z-COM 4 13 1X 0Z 5 12 0X INH 6 11 A GND 7 10 B GND 8 9 C Truth Table “ON” Channel Control Inputs Inhibit C* B A VHC4051A VHC4052A VHC4053A L L L L 0 0X, 0Y 0X, 0Y, 0Z L L L H 1 1X, 1Y 1X, 0Y, 0Z L L H L 2 2X, 2Y 0X, 1Y, 0Z L L H H 3 3X, 3Y 1X, 1Y, 0Z L H L L 4  0X, 0Y, 1Z L H L H 5  1X, 0Y, 1Z L H H L 6  0X, 1Y, 1Z L H H H 7  1X, 1Y, 1Z H X X X None None None X: Don't care, *: Except VHC4052A © 2019 Toshiba Electronic Devices & Storage Corporation 2 2019-01-31 TC74VHC4051,4052,4053AF/FK System Diagram TC74VHC4051A COM C I/O O/I 0 1 A 2 3 B 4 5 C 6 C I/O INH O/I 7 TC74VHC4052A X-COM C I/O O/I 0X 1X A 2X 3X B 0Y 1Y 2Y C INH I/O O/I 3Y Y-COM TC74VHC4053A Y-COM X-COM A C I/O O/I 0X 1X B 0Y 1Y C 0Z C I/O INH © 2019 Toshiba Electronic Devices & Storage Corporation 3 O/I 1Z Z-COM 2019-01-31 TC74VHC4051,4052,4053AF/FK Absolute Maximum Ratings (Note) Characteristics Symbol Rating Unit Power supply voltage VCC 0.5 to 7.0 V Control input voltage VIN 0.5 to 7.0 V Switch I/O voltage VI/O  0.5 to VCC  0.5 V Input diode current IIK 20 mA IIOK 25 mA IT 25 mA DC VCC or ground current ICC 50 mA Power dissipation PD 180 mW Storage temperature Tstg 65 to 150 °C I/O diode current Switch through current Note : Exceeding any of the absolute maximum ratings, even briefly, may lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Operating Ranges (Note) Characteristics Symbol Rating Unit Power supply voltage VCC 2 to 5.5 V Input voltage VIN 0 to 5.5 V Switch I/O voltage VI/O 0 to VCC V Operating temperature Topr 40 to 85 °C 0 to 200 (VCC  2.5  0.2 V) Input rise and fall time dt/dv 0 to 100 (VCC  3.3  0.3 V) ns/V 0 to 20 (VCC  5  0.5 V) Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused control inputs must be tied to either VCC or GND. © 2019 Toshiba Electronic Devices & Storage Corporation 4 2019-01-31 TC74VHC4051,4052,4053AF/FK Electrical Characteristics DC Electrical Characteristics Ta  25°C Characteristics High-level Symbol Unit VCC (V) Min Typ. Max Min Max 2.0 1.5   1.5  3.0 2.0   2.0  4.5 3.15   3.15  5.5 3.85   3.85  2.0   0.5  0.5 3.0   0.8  0.8 4.5   1.35  1.35 5.5   1.65  1.65 VIN  VIL or VIH VI/O  VCC to GND II/O  2 mA 2.3  200    3.0  45 86  108 4.5  24 37  46 VIN  VIL or VIH VI/O  VCC or GND II/O  2 mA 2.3  28 73  84 3.0  22 38  44 4.5  17 27  31 VIN  VIL or VIH VI/O  VCC to GND II/O  2 mA 2.3  10 25  35 3.0  5 15  20 4.5  5 13  18  VIH Input voltage Low-level ON resistance Difference of ON resistance between switches  VIL RON RON Ta  40 to 85°C Test Condition V   Input/Output leakage current (switch OFF) IOFF VOS  VCC or GND VIS  GND to VCC VIN = VIL or VIH 5.5   0.1  .0 A Input/Output leakage current (switch ON, output open) II/O VOS  VCC or GND VIN  VIL or VIH 5.5   0.1  .0 A Control input current IIN VIN  VCC or GND 5.5   0.1  1.0 A Quiescent supply current ICC VIN  VCC or GND 5.5   2.0  20.0 A © 2019 Toshiba Electronic Devices & Storage Corporation 5 2019-01-31 TC74VHC4051,4052,4053AF/FK AC Electrical Characteristics (Input: tr  tf  3 ns) Ta  25°C Characteristics Symbol Unit CL  15 pF RL  1 k Phase difference between input and output I/O CL  50 pF RL  1 k CL  15 pF RL  1 k Output enable time CL  15 pF RL  1 k Figure 1 Figure 1 tpLZ tpHZ CL  50 pF RL  1 k Control input capacitance Figure 1 tpZL tpZH CL  50 pF RL  1 k Output disable time CIN Figure 1 All types VCC (V) Min Typ. Max Min Max 2.50.2  1.2 10  16 3.30.3  0.8 6  10 5.00.5  0.3 4  7 2.50.2  2.6 12  18 3.30.3  1.5 9  12 5.00.5  0.6 6  8 2.50.2  3.3 15  20 3.30.3  2.3 11  15 5.00.5  1.6 7  10 2.50.2  4.2 25  32 3.30.3  3.0 18  22 5.00.5  2.1 12  16 2.50.2  6 15  23 3.30.3  4.5 11  15 5.00.5  3.2 7  10 2.50.2  9.6 25  32 3.30.3  7.2 18  22 5.00.5  5.1 12  16   2   10 pF    pF    pF    pF    pF 4051A COMMON terminal capacitance SWITCH terminal capacitance CIS COS 4052A  Figure 2  8.2 4051A 5.7  Figure 2  Power dissipation capacitance CPD 4052A ns 0.5  Figure 2  0.5 0.5 4051A 15 Figure 2  (Note) 4053A Note: 5.6 4053A 4052A ns 5.6 4051A CIOS 13.1 4053A 4052A ns 23.4 4053A Feedthrough capacitance Ta  40 to 85°C Test Condition  24 12 CPD is defined as the value of the internal equivalent capacitance of IC which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr)  CPD･VCC･fIN  ICC © 2019 Toshiba Electronic Devices & Storage Corporation 6 2019-01-31 TC74VHC4051,4052,4053AF/FK Analog Switch Characteristics (Ta  25°C) (Note) Characteristics Test Condition Typ. Unit VCC (V) Sine Wave Distortion (T.H.D) RL  10 kCL  50 pF, fIN  1 kHz VIN  2.0 Vp-p 3.0 0.1 VIN  4.0 Vp-p 4.5 0.03 % 4051A Frequency response (switch ON) VIN is centered at (VCC/2). Adjust input for 0dBm. Increase fIN frequency until dB meter reads 3dB. RL  50 , CL  10 pF,sine wave Figure 3 4052A 150 3.0 4053A 240 4051A 180 4052A 4.5 4053A Feed through attenuation (switch OFF) VIN is centered at (VCC/2). Adjust input for 0dBm. RL  600 , CL  50 pF, fIN  1 MHz, sine wave Figure 4 RL  50 , CL  10 pF, fIN  1 MHz, sine wave Crosstalk (control input to signal output) RL  600 , CL  50 pF, fIN  1 MHz, square wave (tr  tf  6 ns) Figure 5 Crosstalk (between any switches) VIN is centered at (VCC/2). Adjust input for 0dBm. RL  600 , CL  50 pF, fIN  1 MHz, sine wave Figure 6 Note: 200 MHz 230 280 3.0 -45 4.5 -45 3.0 -65 4.5 -65 3.0 60 4.5 100 3.0 -45 4.5 -45 dB mV dB These characteristics are determined by design of devices. Switch pin Common pin © 2019 Toshiba Electronic Devices & Storage Corporation 7 2019-01-31 TC74VHC4051,4052,4053AF/FK AC Test Circuit 3 ns VCC 3 ns VCC 90% VC C 10% GND VCC I/O O/I 1 k VO/I (S1  VCC, S2  GND) S2 50 pF from P.G 50% S1 GND 90% 50% tpZH tpHZ VO/I (S1  GND, S2  VCC) VOL VOH 50% 10% tpZL Figure 1 VOH VOL tpLZ tpLZ, tpHZ, tpZL, tpZH CIOS VCC C VCC O/I COS I/O (Common pin) CIS (Switch pin) GND Figure 2 CIOS, CIS, COS VCC VCC 1/2VCC O/I GND Figure 3 50  I/O VIN 10 pF C Frequency Response (switch on) VCC C VCC I/O O/I Figure 4 © 2019 Toshiba Electronic Devices & Storage Corporation RL GND CL 1/2VCC RL VIN Feedthrough 8 2019-01-31 TC74VHC4051,4052,4053AF/FK VCC C VCC 600  I/O O/I GND 1/2VCC C Figure 5 50 pF from P.G 600  VCC GND 1/2VCC Cross Talk (control input to output signal) VCC VCC C 600  I/O O/I GND 1/2VCC Figure 6 50 pF O/I 50 pF I/O 600  600  1/2VCC VCC 600  C VIN 1/2VCC Cross Talk (between any two switches) © 2019 Toshiba Electronic Devices & Storage Corporation 9 2019-01-31 TC74VHC4051,4052,4053AF/FK Package Dimensions Weight: 0.18 g (typ.) © 2019 Toshiba Electronic Devices & Storage Corporation 10 2019-01-31 TC74VHC4051,4052,4053AF/FK Package Dimensions Weight: 0.02 g (typ.) © 2019 Toshiba Electronic Devices & Storage Corporation 11 2019-01-31 TC74VHC4051,4052,4053AF/FK RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. 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