TC74VHC9164FK(EL,K

TC74VHC9164FK(EL,K

  • 厂商:

    TOSHIBA(东芝)

  • 封装:

    VSSOP16P_4.25X3MM

  • 描述:

    IC LOGIC 8-BIT SHIFT REGISTER (P-IN/S-OUT, S-IN/P-OUT 2.0 to 5.5V US16 (VSSOP16)

  • 详情介绍
  • 数据手册
  • 价格&库存
TC74VHC9164FK(EL,K 数据手册
TC74VHC9164FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC9164FK 8-Bit Shift Register (Parallel-IN/ Serial-OUT, Serial -IN/ Parallel -OUT) The TC74VHC9164 is an ultra-high-speed 8-Bit Shift Register fabricated using silicon-gate CMOS technology. The TC74VHC9164 combines low power consumption of CMOS with Schottky TTL speeds. The TC74VHC9164 has parallel data inputs/outputs, a serial input and a serial output. It converts parallel data into serial data or vice versa. When P/S CONT is Low, Q/D1 to Q/D8 are configured as parallel data outputs. At this time, the SI input is serially loaded on the rising edges of CK and unloaded from the Q/D1 to Q/D8 outputs in parallel. When CLR/ LOAD input is Low, all flip-flops are asynchronously reset, irrespective of the CK state. When P/S CONT is High, Q/D1 to Q/D8 are configured as parallel data inputs. At this time, when CLR/ LOAD is Low, Q/D1 to Q/D8 latch data in parallel asynchronously from the CK input. All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHC9164 is capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity. Additionally, all the inputs have a newly developed protection circuit without a diode returned to VCC. This enables the inputs to be tolerant of up to 5.5 volts even when power supply is down. The input power-down protection capability makes the TC74VHC9164 ideal for a wide range of applications, such as interfacing between different voltages, voltage translation from 5 V to 3 V and battery back-up circuits. TC74VHC9164FK Weight VSSOP16-P-0030-0.50 : 0.02 g (typ.) Features  High speed: fmax  149 MHz (typ.) at VCC  5 V  Low power dissipation: ICC  4 A (max) at Ta  25°C  Power down protection is provided on all inputs.  Balanced propagation delays: tpLH  tpHL  Wide operating voltage range: VCC (opr)  2 to 5.5 V Start of commercial production 2011-03 © 2018 Toshiba Electronic Devices & Storage Corporation 1 2018-06-22 TC74VHC9164FK Pin Assignment P/S CONT 1 16 VCC 2 15 Q8C SI 3 14 Q8’ CK 4 13 Q/D8 Q/D1 5 12 Q/D7 Q/D2 6 11 Q/D6 Q/D3 7 10 Q/D5 GND 8 9 Q/D4 (top view) t Truth Table Parallel Outputs/Inputs Inputs Function P/S CONT CLR/ LOAD SI CK L X X X Q/D1 to Q/D8 are configured as parallel outputs. L L X X Shift register is cleared. L H L L H H First stage of S.R. becomes “H”. Other stages store the data of previous stage, respectively. L H X The shift register remains unchanged. The Q8C output keeps the value of the previous flip-flop. H X X X Q/D1 to Q/D8 are configured as parallel inputs. H L X X Q/D1 to Q/D8 are latched into the shift register. H H L H H H H H X Q/D1········Q/D8 Output- state Parallel Outputs Input- state Parallel Inputs First stage of S.R. becomes “L”. Other stages store the data of previous stage, respectively. First stage of S.R. becomes “L”. Other stages store the data of previous stage, respectively. First stage of S.R. becomes “H”. Other stages store the data of previous stage, respectively. The shift register remains unchanged. The Q8C output keeps the value of the previous flip-flop. X: Don’t care © 2018 Toshiba Electronic Devices & Storage Corporation 2 2018-06-22 TC74VHC9164FK System Diagram Q/D1 5 P/S CONT 1 SI 3 CK Q/D2 6 Q/D3 7 Q/D4 9 Q/D5 10 Q/D6 11 Q/D8 13 C PD D Q C PD D Q C PD D Q C PD D Q C PD D Q C PD D Q C PD D Q C PD D Q CK S/L CK S/L CK S/L CK S/L CK S/L CK S/L CK S/L CK S/L こ 4 CLR/LOAD Q/D7 12 14 D Q 15 Q8’ Q8C CK R 2 Timing Chart P/S CONT CK SI Q/D1 H Q/D2 L Q/D3 L Q/D4 H Q/D5 L Q/D6 H Q/D7 L Q/D8 H Output Q8’ H Output Q8C Parallel Outputs/ Inputs DON”T CARE UNTIL CLR/LOAD GOES “L” L H CLR H L L H H L L H L L L H H LOAD Parallel Outputs © 2018 Toshiba Electronic Devices & Storage Corporation Parallel Inputs 3 2018-06-22 TC74VHC9164FK Absolute Maximum Ratings (Note1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to 7.0 V DC output voltage VOUT −0.5 to VCC + 0.5 V DC bus I/O voltage (Q/D1 to Q/D8) VI/O Input diode current IIK −20 mA Output diode current IOK ±20 mA DC output current IOUT ±25 mA DC VCC/ground current ICC ±75 mA Power dissipation PD 180 mW Storage temperature Tstg −65 to 150 °C −0.5 to 7.0 (Note2) −0.5 to VCC + 0.5 (Note3) V Note1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note2 Output in off-state Note3 High or low state. IOUT absolute maximum rating must be observed. Operating Ranges (Note1) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to 5.5 V VOUT 0 to VCC V Output voltage DC bus I/O voltage (Q/D1 to Q/D8) VI/O Operating temperature Topr 0 to 5.5 (Note2) 0 to VCC (Note3) −40 to 85 V °C Note1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note2 Output in off-state Note3 High or low state. © 2018 Toshiba Electronic Devices & Storage Corporation 4 2018-06-22 TC74VHC9164FK Electrical Characteristics DC Characteristics Characteristics Positive threshold voltage Negative threshold voltage Hysteresis voltage Test Condition Symbol VP VCC (V) Min Typ Max Min Max 3.0 ― ― 2.20 ― 2.20 4.5 ― ― 3.15 ― 3.15 5.5 ― ― 3.85 ― 3.85 3.0 0.90 ― ― 0.90 ― 4.5 1.35 ― ― 1.35 ― 5.5 1.65 ― ― 1.65 ― 3.0 0.30 ― 1.20 0.30 1.20 4.5 0.40 ― 1.40 0.40 1.40 5.5 0.50 ― 1.60 0.50 1.60 2.0 1.9 2.0 ― 1.9 ― 3.0 2.9 3.0 ― 2.9 ― 4.5 4.4 4.5 ― 4.4 ― IOH = −4 mA 3.0 2.58 ― ― 2.48 ― IOH = −8 mA 4.5 3.94 ― ― 3.80 ― 2.0 ― 0.0 0.1 ― 0.1 3.0 ― 0.0 0.1 ― 0.1 4.5 ― 0.0 0.1 ― 0.1 IOL = 4 mA 3.0 ― ― 0.36 ― 0.44 IOL = 8 mA 4.5 ― ― 0.36 ― 0.44 ― VN ― VH ― IOH = −50 μA High-level output voltage Low-level output voltage VOH VOL VIN = VIH or VIL VIN = VIH or VIL Ta = −40 to 85°C Ta = 25°C IOL = 50 μA Unit V V V V V 3-state output off-state current (Q/D1 to Q/D8) IOZ VIN = VIH or VIL VI/O=5.5 V or GND 0 to 5.5 ― ― ±0.25 ― ±2.5 μA Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ― ― 4.0 ― 40.0 μA © 2018 Toshiba Electronic Devices & Storage Corporation 5 2018-06-22 TC74VHC9164FK Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Test Condition Ta = 25°C Ta = −40 to 85°C VCC (V) Typ. Limit Limit Unit Minimum pulse width (CK) tw (L) tw (H) ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 7.0 5.0 8.0 6.0 ns Minimum pulse width ( CLR / LOAD ) tw (L) ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 6.0 5.0 7.0 6.0 ns Minimum set-up time (Q/D1 to Q/D8 – CLR / LOAD ) ts ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 6.0 5.0 7.0 6.0 ns Minimum set-up time (SI-CK) ts ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 6.0 5.0 7.0 5.0 ns Minimum hold time (Q/D1 to Q/D8 – CLR / LOAD ) th ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 1.0 1.0 1.0 1.0 ns Minimum hold time (SI-CK) th ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 1.0 1.5 1.0 1.5 ns trem ― 3.3 ± 0.3 5.0 ± 0.5 ― ― 5.0 3.0 5.0 3.0 ns Minimum removal time ( CLR / LOAD -CK) © 2018 Toshiba Electronic Devices & Storage Corporation 6 2018-06-22 TC74VHC9164FK AC Characteristics (input: tr = tf = 3 ns) Characteristics Propagation delay time (CK – Q/D1 to Q/D8) Propagation delay time (CK – Q8’,Q8C) Propagation delay time ( CLR / LOAD –Q/D1 to Q/D8) Propagation delay time ( CLR / LOAD -Q8’,Q8C) Propagation delay time (Q/D8-Q8’) 3-state output enable time (P/S CONT – Q/D1 to Q/D8) 3-state output disable time (P/S CONT – Q/D1 to Q/D8) Test Condition Symbol tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpLH tpHL tpZL tpZH tpLZ tpHZ VCC (V) fmax Min Typ. Max Min Max 15 ― 9.3 14.7 1.0 16.7 50 ― 12.1 19.0 1.0 21.6 15 ― 6.7 9.7 1.0 11.1 50 ― 9.1 13.1 1.0 14.9 15 ― 9.0 14.4 1.0 16.4 50 ― 11.8 18.6 1.0 21.2 15 ― 6.4 9.4 1.0 10.7 50 ― 8.7 12.7 1.0 14.5 15 ― 7.9 11.7 1.0 13.4 50 ― 10.2 15.1 1.0 17.2 15 ― 6.2 8.4 1.0 9.6 50 ― 8.0 11.1 1.0 12.6 15 ― 8.0 11.8 1.0 13.5 50 ― 10.3 15.3 1.0 17.5 15 ― 6.2 8.5 1.0 9.7 50 ― 8.1 11.2 1.0 12.8 15 ― 9.5 15.2 1.0 17.3 50 ― 11.8 18.9 1.0 21.6 15 ― 6.7 9.6 1.0 10.9 50 ― 8.4 12.2 1.0 13.9 15 ― 6.7 10.4 1.0 11.9 50 ― 9.9 15.4 1.0 17.6 15 ― 5.0 7.3 1.0 8.3 50 ― 7.6 11.0 1.0 12.5 3.3 ± 0.3 50 ― 10.1 12.8 1.0 13.7 5.0 ± 0.5 50 ― 7.8 9.8 1.0 10.6 15 68 107 ― 59 ― 50 52 82 ― 46 ― 15 103 149 ― 90 ― 50 76 109 ― 67 ― ― 4 10 ― 10 pF Q/D1 - Q/D8 ― 8 ― ― ― pF P/S CONT=L (Parallel Outputs) ― 102 ― ― ― P/S CONT=H (Parallel Inputs) ― 34 ― ― ― 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 ― 5.0 ± 0.5 3.3 ± 0.3 RL=1kΩ 5.0 ± 0.5 RL=1kΩ ― 5.0 ± 0.5 Input capacitance CIN bus Input capacitance CI/O Power dissipation capacitance (Note) CPD Unit CL (pF) 3.3 ± 0.3 Maximum clock frequency Ta = −40 to 85°C Ta = 25°C ― ns ns ns ns ns ns ns MHz pF Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC © 2018 Toshiba Electronic Devices & Storage Corporation 7 2018-06-22 TC74VHC9164FK Noise Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol Ta = 25°C VCC (V) Typ. Max Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 5.0 0.6 1.0 V Quiet output minimum dynamic VOL VOLV CL = 50 pF 5.0 -0.5 −1.0 V Minimum high level dynamic input voltage VIHD CL = 50 pF 5.0 ― 3.5 V Maximum low level dynamic input voltage VILD CL = 50 pF 5.0 ― 1.5 V © 2018 Toshiba Electronic Devices & Storage Corporation 8 2018-06-22 TC74VHC9164FK Package Dimensions Weight: 0.02 g (typ.) © 2018 Toshiba Electronic Devices & Storage Corporation 9 2018-06-22 TC74VHC9164FK RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”.  TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.  This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.  Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.  PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). 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Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.  Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. © 2018 Toshiba Electronic Devices & Storage Corporation 10 2018-06-22
TC74VHC9164FK(EL,K
1. 物料型号:TC74VHC9164FK,由东芝公司生产。

2. 器件简介:TC74VHC9164FK是一款高速CMOS 4位串行移位寄存器,具有三态输出功能,适用于高速数据传输。

3. 引脚分配:该器件具有16个引脚,包括数据输入、时钟输入、输出使能、串行输入/输出以及电源和地线。

4. 参数特性:工作电压范围为2.0V至5.5V,工作温度范围为-40℃至+85℃。

5. 功能详解:TC74VHC9164FK能够实现数据的串行输入和并行输出,支持高速数据传输。

6. 应用信息:常用于数字电路设计中的数据存储和传输,尤其是在需要高速数据交换的应用中。

7. 封装信息:采用TSSOP-16封装。
TC74VHC9164FK(EL,K 价格&库存

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