TC74VHCT374AFT

TC74VHCT374AF/AFT/AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT374AF,TC74VHCT374AFT,TC74VHCT374AFK Octal D-Type Flip Flop with 3-State Output The TC74VHCT374A is an advanced high speed CMOS OCTAL FLIP-FLOP with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CK) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc. Note: Output in off-state TC74VHCT374AFK TC74VHCT374AF TC74VHCT374AFT Features • • • • • • • High speed: fmax = 140 MHz (typ.) at VCC = 5 V Low power dissipation: ICC = 4 μA (max) at Ta = 25°C Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min) Power down protection is provided on all inputs and outputs. ∼ Balanced propagation delays: tpLH − tpHL Low noise: VOLP = 1.6 V (max) Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 374 type. Weight SOP20-P-300-1.27A TSSOP20-P-0044-0.65A VSSOP20-P-0030-0.50 : 0.22 g (typ.) : 0.08 g (typ.) : 0.03 g (typ.) 1 2007-10-01 TC74VHCT374AF/AFT/AFK Pin Assignment IEC Logic Symbol (1) (11) (3) (4) (7) (8) (13) (14) (17) (18) OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 (top view) VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CK OE CK D0 D1 D2 D3 D4 D5 D6 D7 EN C1 1D (2) (5) (6) (9) (12) (15) (16) (19) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 10 Truth Table Inputs OE CK X D X X L H Output Z Qn L H H L L L X: Don’t care Z: High impedance Qn: No change System Diagram D0 3 D 4 D D1 7 D D2 8 D D3 13 D D4 14 D D5 17 D D6 18 D D7 CK 11 CK Q CK Q CK Q CK Q CK Q CK Q CK Q CK Q OE 1 2 Q0 5 Q1 6 Q2 9 Q3 12 Q4 15 Q5 16 Q6 19 Q7 2 2007-10-01 TC74VHCT374AF/AFT/AFK Absolute Maximum Ratings (Note 1) Characteristics Supply voltage range DC input voltage DC output voltage Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature Symbol VCC VIN VOUT IIK IOK IOUT ICC PD Tstg Rating −0.5 to 7.0 −0.5 to 7.0 −0.5 to 7.0 −0.5 to VCC + 0.5 −20 ±20 ±25 ±75 180 −65 to 150 (Note 4) (Note 2) (Note 3) Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: Output in off-state Note 3: High or low state. IOUT absolute maximum rating must be observed. Note 4: VOUT < GND, VOUT > VCC Operating Ranges (Note 1) Characteristics Supply voltage Input voltage Output voltage Operating temperature Input rise and fall time Symbol VCC VIN VOUT Topr dt/dv Rating 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC −40 to 85 0 to 20 (Note 2) (Note 3) Unit V V V °C ns/V Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 2: VCC = 0 V Note 3: High or low state 3 2007-10-01 TC74VHCT374AF/AFT/AFK Electrical Characteristics DC Characteristics Characteristics High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage 3-state output off-state current Input leakage current Quiescent supply current Output leakage current Symbol Test Condition VCC (V) VIH VIL VOH ― ― VIN IOH = −50 μA = VIH or IOH = −8 mA VIL VIN IOL = 50 μA = VIH or IOL = 8 mA VIL VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5 V or GND VIN = VCC or GND Per input: VIN = 3.4 V Other input: VCC or GND VOUT = 5.5 V 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 Min 2.0 ― 4.40 3.94 ― ― ― Ta = 25°C Typ. ― ― 4.50 ― 0.0 ― ― Max ― 0.8 ― ― 0.10 0.36 ±0.25 Ta = −40 to 85°C Min 2.0 ― 4.40 3.80 ― ― ― Max ― 0.8 ― ― 0.10 0.44 ±2.50 μA V V V Unit VOL V IOZ IIN ICC ICCT IOPD 0 to 5.5 5.5 5.5 0 ― ― ― ― ― ― ― ― ±0.1 4.0 1.35 0.5 ― ― ― ― ±1.0 40.0 1.50 5.0 μA μA mA μA Timing Requirements (input: tr = tf = 3 ns) Characteristics Symbol Test Condition VCC (V) Minimum pulse width (CK) Minimum set-up time Minimum hold time tw (H) tw (L) ts th ― ― ― 5.0 ± 0.5 5.0 ± 0.5 5.0 ± 0.5 Ta = 25°C Typ. ― ― ― Limit 6.5 2.5 2.5 Ta = −40 to 85°C Limit 8.5 2.5 2.5 ns ns ns Unit 4 2007-10-01 TC74VHCT374AF/AFT/AFK AC Characteristics (input: tr = tf = 3 ns) Characteristics Propagation delay time (CK-Q) 3-state output enable time 3-state output disable time Maximum clock frequency Output to output skew Input capacitance Output capacitance Power dissipation capacitance Symbol Test Condition VCC (V) tpLH tpHL tpZL tpZH tpLZ tpHZ fmax tosLH tosHL CIN COUT CPD ― 5.0 ± 0.5 50 RL = 1 kΩ 5.0 ± 0.5 15 50 50 15 50 50 ― ― ― ― 90 85 ― ― ― (Note 2) ― 5.6 6.5 7.3 7.0 140 130 ― 4 9 25 10.4 10.2 11.2 11.2 ― ― 1.0 10 ― ― 1.0 1.0 1.0 1.0 80 95 ― ― ― ― 11.5 11.5 12.5 12.0 ― ― 1.0 10 ― ― ns CL (pF) 15 Min ― Ta = 25°C Typ. 4.1 Max 9.4 Ta = −40 to 85°C Min 1.0 Max 10.5 ns Unit RL = 1 kΩ 5.0 ± 0.5 ns ― 5.0 ± 0.5 MHz (Note 1) 5.0 ± 0.5 ― ― ns pF pF pF Note 1: Parameter guaranteed by design. tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn| Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC/8 (per F/F) And the total CPD when n pcs. of latch operate can be gained by the following equation: CPD (total) = 14 + 11·n Noise Characteristics (input: tr = tf = 3 ns) Characteristics Quiet output maximum dynamic VOL Quiet output minimum dynamic VOL Minimum high level dynamic input voltage Maximum low level dynamic input voltage Symbol VOLP VOLV VIHD VILD CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Test Condition VCC (V) 5.0 5.0 5.0 5.0 Ta = 25°C Typ. 1.1 −1.1 ― ― Max 1.5 −1.5 2.0 0.8 Unit V V V V 5 2007-10-01 TC74VHCT374AF/AFT/AFK Package Dimensions Weight: 0.22 g (typ.) 6 2007-10-01 TC74VHCT374AF/AFT/AFK Package Dimensions Weight: 0.08 g (typ.) 7 2007-10-01 TC74VHCT374AF/AFT/AFK Package Dimensions Weight: 0.03 g (typ.) 8 2007-10-01 TC74VHCT374AF/AFT/AFK RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 20070701-EN GENERAL • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Unintended Usage of TOSHIBA products listed in his document shall be made at the customer’s own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 9 2007-10-01