TC74VHCV373FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCV373FK
Octal Schmitt D-Type Latch with 3-State Output
The TC74VHCV373FK is an advanced high speed CMOS OCTAL LATCH
with 3-STATE OUTPUT fabricated with silicon gate CMOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining the CMOS low power dissipation.
This 8-bit D-type latch is controlled by a latch enable input (LE) and an output
enable input ( OE ).
When the OE input is high, the eight outputs are in a high impedance state.
Input pin have hysteresis between the positive-going and negative-going
thresholds. Thus the TC74VHCV373FK are capable of squaring up
transitions of slowly changing input signals and provides an improved noise
immunity.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to
the input and output (Note) pins without regard to the supply voltage. These
structure prevents device destruction due to mismatched supply and
input/output voltages such as battery back up, hot board insertion, etc.
Note:
TC74VHCV373FK
Weight
VSSOP20-P-0030-0.50
: 0.03 g ( typ.)
Output in off-state
Features
High speed: tpd = 5.4 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
Wide operating voltage range: VCC (opr) = 1.8 V to 5.5 V
Ouput current: |IOH|/IOL = 16 mA (min) (VCC = 4.5 V)
Available in VSSOP (US)
Power-down protection provided on all inputs and outputs
Pin and function compatible with the 74 series
(74AC/VHC/HC/F/ALS/LS etc.) 373 typ
Start of commercial production
2010-01
© 2019
Toshiba Electronic Devices & Storage Corporation
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TC74VHCV373FK
Pin Assignment
1
20
VCC
Q0
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
GND 10
11
LE
(top view)
Truth Table
Inputs
Output
OE
LE
D
H
X
X
Z
L
L
X
Qn
L
H
L
L
L
H
H
H
X: Don’t care
Z: High impedance
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
D0
D1
3
LE
11
D2
4
D3
7
D4
8
D5
13
D6
17
14
D7
18
D
D
D
D
D
D
D
D
L Q
L Q
L Q
L Q
L Q
L Q
L Q
L Q
1
OE
2
Q0
5
Q1
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Toshiba Electronic Devices & Storage Corporation
6
9
Q2
Q3
2
12
Q4
15
Q5
16
Q6
19
Q7
2019-01-31
TC74VHCV373FK
Absolute Maximum Ratings (Note1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
VCC
−0.5 to 7.0
V
DC input voltage
VIN
−0.5 to 7.0
V
DC output voltage
VOUT
Input diode current
IIK
−50
Output diode current
IOK
±50
DC output current
IOUT
±50
mA
Power dissipation
PD
180
mW
ICC/IGND
±100
mA
Tstg
−65 to 150
°C
DC VCC/ground current
Storage temperature
−0.5 to 7.0
(Note 2)
−0.5 to VCC + 0.5
(Note 3)
V
mA
(Note 4)
mA
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even
destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant
change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating
conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the
operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
Note 2: Output in off-state
Note 3: High or low state. IOUT absolute maximum rating must be observed.
Note 4: VOUT < GND, VOUT > VCC
Operating Ranges (Note1)
Characteristics
Symbol
Rating
Unit
Power supply voltage
VCC
1.8 to 5.5
V
Input voltage
VIN
Output voltage
0 to 5.5
VOUT
V
0 to 5.5
(Note 2)
0 to VCC
(Note 3)
V
Operating temperature
Topr
−40 to 85
°C
Input rise and fall time
dt/dv
0 to 20 (VCC = 3.3 ± 0.3 V)
0 to 1 (VCC = 5 ± 0.5 V)
ms/V
Note 1: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Note 2: Output in off-state
Note 3: High or low state.
© 2019
Toshiba Electronic Devices & Storage Corporation
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TC74VHCV373FK
Electrical Characteristics
DC Characteristics
Characteristics
Positive threshold voltage
Negative threshold voltage
Hysteresis voltage
High-level output voltage
Low-level output voltage
Test Condition
Symbol
VP
VN
VH
VOH
VOL
3-state output off-state
current
IOZ
Power-off leakage current
IOFF
VIN
= VIH or VIL
VIN
= VIH or VIL
Ta =
−40 to 85°C
Ta = 25°C
Unit
VCC (V)
Min
Typ.
Max
Min
Max
―
1.8
2.3
3.0
4.5
5.5
―
―
―
―
―
―
―
―
―
―
1.65
1.85
2.20
3.15
3.85
―
―
―
―
―
1.65
1.85
2.20
3.15
3.85
―
1.8
2.3
3.0
4.5
5.5
0.15
0.45
0.90
1.35
1.65
―
―
―
―
―
―
―
―
―
―
0.15
0.45
0.90
1.35
1.65
―
―
―
―
―
―
1.8
2.3
3.0
4.5
5.5
0.15
0.20
0.30
0.40
0.50
―
―
―
―
―
1.05
1.10
1.20
1.40
1.60
0.15
0.20
0.30
0.40
0.50
1.05
1.10
1.20
1.40
1.60
IOH = −50 μA
1.8
3.0
4.5
1.7
2.9
4.4
1.8
3.0
4.5
―
―
―
1.7
2.9
4.4
―
―
―
IOH = −8 mA
IOH = −16 mA
3.0
4.5
2.58
3.94
―
―
―
―
2.48
3.80
―
―
IOL = 50 μA
1.8
3.0
4.5
―
―
―
0.0
0.0
0.0
0.1
0.1
0.1
―
―
―
0.1
0.1
0.1
IOL = 8 mA
IOL = 16 mA
3.0
4.5
―
―
―
―
0.36
0.44
―
―
0.44
0.55
1.8 to 5.5
―
―
±0.5
―
±5.0
μA
0
―
―
0.5
―
5.0
μA
VIN = VIH or VIL
VOUT = 0 to 5.5V
VIN/VOUT = 5.5 V
V
V
V
Input leakage current
IIN
VIN = 5.5 V or GND
0 to 5.5
―
―
±0.1
―
±1.0
μA
Quiescent supply current
ICC
VIN = VCC or GND
5.5
―
―
2.0
―
20.0
μA
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Toshiba Electronic Devices & Storage Corporation
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2019-01-31
TC74VHCV373FK
Timing Requirements (input: tr = tf = 3 ns)
Characteristics
Symbol
Test Condition
Ta = 25°C
Ta =
−40 to
85°C
VCC (V)
Typ.
Limit
Limit
Unit
Minimum pulse width
(LE)
tw (H)
―
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
―
―
―
6.0
5.0
5.0
6.5
5.0
5.0
ns
Minimum set-up time
ts
―
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
―
―
―
4.5
4.0
4.0
5.0
4.0
4.0
ns
Minimum hold time
th
―
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
―
―
―
1.5
1.0
1.0
1.5
1.0
1.0
ns
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TC74VHCV373FK
AC Electrical Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
VCC (V)
CL (pF)
Min
Typ.
Max
Min
Max
15
―
10.7
15.7
1.0
19.0
50
―
13.5
19.3
1.0
22.0
15
―
7.4
11.0
1.0
13.0
50
―
9.5
14.5
1.0
16.5
15
―
5.4
7.2
1.0
8.5
50
―
7.1
9.2
1.0
10.5
15
―
13.0
17.7
1.0
20.1
50
―
15.5
21.1
1.0
24.1
15
―
8.8
12.9
1.0
14.8
50
―
10.8
15.5
1.0
17.7
15
―
6.2
7.2
1.0
8.5
50
―
8.0
9.3
1.0
10.6
15
―
9.4
15.8
1.0
19.0
50
―
12.3
18.8
1.0
22.0
15
―
6.5
11.4
1.0
13.5
50
―
8.7
14.9
1.0
17.0
15
―
4.5
8.1
1.0
9.5
50
―
6.2
10.1
1.0
11.5
2.5 ± 0.2
50
―
14.5
17.4
1.0
19.0
3.3 ± 0.3
50
―
10.9
13.2
1.0
15.0
5.0 ± 0.5
50
―
8.0
9.2
1.0
10.5
2.5 ± 0.2
50
―
―
1.5
―
1.5
3.3 ± 0.3
50
―
―
1.5
―
1.5
5.0 ± 0.5
50
―
―
1.0
―
1.0
2.5 ± 0.2
Propagation delay
time
(LE-Q)
tpLH
tpHL
―
3.3 ± 0.3
5.0 ± 0.5
2.5 ± 0.2
Propagation delay
time
(D-Q)
tpLH
tpHL
―
3.3 ± 0.3
5.0 ± 0.5
2.5 ± 0.2
3-state output enable
time
tpZL
tpZH
RL = 1 kΩ
3.3 ± 0.3
5.0 ± 0.5
3-state output disable
time
Output to output skew
Input capacitance
Output capacitance
Power dissipation
capacitance
tpLZ
tpHZ
RL = 1 kΩ
tosLH
tosHL
(Note 1)
Ta =
−40 to 85°C
Ta = 25°C
Unit
ns
ns
ns
ns
ns
CIN
―
―
4
10
―
10
pF
COUT
―
―
6
―
―
―
pF
―
21
―
―
―
pF
CPD
(Note 2)
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current
consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/8 (per latch)
And the total CPD when n pcs. of Latch operate can be gained by the following equation:
CPD (total) = 11 + 10·n
© 2019
Toshiba Electronic Devices & Storage Corporation
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2019-01-31
TC74VHCV373FK
Noise Characteristics (input: tr = tf = 3 ns)
Characteristics
Test Condition
Symbol
Ta = 25°C
VCC (V)
Typ.
Max
Unit
Quiet output maximum dynamic VOL
VOLP
CL = 50 pF
3.3
5.0
0.3
0.7
―
―
V
Quiet output minimum dynamic VOL
VOLV
CL = 50 pF
3.3
5.0
−0.1
−0.4
―
―
V
Minimum high level dynamic input voltage
VIHD
CL = 50 pF
5.0
―
3.5
V
Maximum low level dynamic input voltage
VILD
CL = 50 pF
5.0
―
1.5
V
© 2019
Toshiba Electronic Devices & Storage Corporation
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TC74VHCV373FK
Package Dimensions
Weight: 0.03 g (typ.)
© 2019
Toshiba Electronic Devices & Storage Corporation
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TC74VHCV373FK
RESTRICTIONS ON PRODUCT USE
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Hardware, software and systems described in this document are collectively referred to as “Product”.
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written permission, reproduction is permissible only if reproduction is without alteration/omission.
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complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the
Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information,
including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and
conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product
will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited
to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the
applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any
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2019-01-31