TC90101FG

TC90101FG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic ＴＣ９０１０１ＦＧ Y/C separation & Video Decoder TC90101FG is a 1chip LSI of multi 3line comb and multi color decoder. TC90101FG has 10bit ADC and 2channels 8bit ADC for analog Video signal interface and also include Y/C separation, color decode, and signal processing circuit. The output interface of TC90101FG is a selectable for ITUR-601 & 656. Featurｓ • Multi color system • Input I/F： CVBS, Y/C, YcbCr(1H & 525p/625p) • Multi 3 line comb (SECAM: BPF) • Component signal frequency detection (525i/525p/625i/625p) • AGC circuit • Output format : 656/601 • Picture improvement Ｙ： Vertical enhance/LTI/Contrast/Setup adjust C： TOF/ACC/Color decode/color gain/CTI/offset adjust • Noise level detection/ID1(525I & 525p) data slice/ CCD data slice/WSS data slice/ Macrovision detection • I2C bus control • Read data superposition on ITUR-656 output • Package： LQFP 100 （0.5mm pitch） • Power supply： 3.3 V， 2.5V，1.5V LQFP100-P-1414-0.5C Weight：0.65g(Typ) Version (note1)These devices are easy to be damaged by high voltage or electric fields. In regards to this, please handle with care. 4.2 ● TOSHIBA is continually working to improve the quality and the reliability of its product. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Feb./2005 1 TC90101FG １．Block Diagram HD/VD D/A Clamp Sync Sep. Timing ×8 Clock Gene. reference clock 42M X'tal SW S/N detection macrovision CCD slice ID1 WSS SW Y CVBS 27 M 10bit ADC AGC SW C Cb MPX 27M 8bit ADC 27M → 4fsc 3line comb Vertical enhance LTI contrast adust delay adjust ＡＣＣ color decord ＴＩＮＴ adjust Color adjust ITU-R656 encodｅ 656/601 Format Cr 27M 8bit ADC IIC-BUS SW SCL SDA ２．Pin Layout 出力I/F Output I/F 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 YCLAMPP1 VSSIO2 YCLAMPP2 VDDIO2 VBI READY ODDEVEN UVFLAG 7 6 BIASYAD 7 7 VRTYAD 7 8 YIN 7 9 VSSYAD 8 0 VRMYAD 8 1 CVBS IN 1.5 3.3 1.5 TESTM6 TESTM5 5 0 VDDIO1 4 9 CKOUT 4 8 YOUT0 4 7 YOUT1 4 6 VSSIO1 4 5 YOUT2 4 4 YOUT3 4 3 DVSS3 4 2 YOUT4 4 1 YOUT5 4 0 DVDD3 3 9 YOUT6 3 8 YOUT7 3 7 YOUT8 3 6 YOUT9 3 5 DVSS2 3 4 COUT8 COUT3 COUT2 COUT9 DVDD4 COUT1 COUT7 VDOUT HDOUT COUT6 DVSS5 DVDD5 COUT5 COUT4 DVSS4 3.3 2.5 ｱﾅﾛｸﾞ入力I/F 8 2 VDDYAD 8 3 VRBYAD 8 4 BIASCAD 8 5 VRTCAD 8 6 CIN 8 7 VSSCAD 8 8 Cb IN 8 9 VDDCAD 9 0 VRBCAD 9 1 BIASRAD 9 2 VRTRAD 9 3 VSSRAD 9 4 Cr IN 9 5 VDDRAD 9 6 VRBRAD 9 7 VDDDA 9 8 DAOUT 9 9 VSSDA Analog Input I/F TC90101FG Top view 1.5 2.5 COUT0 CGP 出力I/F I/F Output 1.5 CSYNC IN 2.5 33 DVDD2 3 2 TESTM4 3 1 TESTM3 3 0 TESTM2 2 9 2.5 2.5 VREFDA VDDPLL VCOFIL VSSPLL PLLIN TESTM1 2 8 SCL 2 7 VDDIO3 BUSSEL VSSXO TDIO9 TDIO8 TDIO6 TDIO5 DVDD1 TDIO2 VDDXO XOIN TDIO7 TDIO4 TDIO3 DVSS1 TDIO1 XOOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 X8PLL 42M XO Feb./2005 TDIO0 TDCLK RESET NCO DAC 100 BIASDA 3.3 1.5 3.3 SDA 2 6 2 TC90101FG ３．Terminals discription Piｎ No Piｎ Name Function （ ）：Condition at normal operation Durable ｖoltage (V) 2.5 2.5 2.5 2.5 0 3.3 3.3 3.3 0 3.3 3.3 3.3 3.3 3.3 1.5 3.3 3.3 3.3 0 3.3 3.3 3.3 3.3 3.3 3.3 5 5 3.3 3.3 3.3 3.3 1.5 5 0 3.3 3.3 3.3 3.3 1.5 3.3 3.3 0 3.3 3.3 0 3.3 3.3 3.3 3.3 3.3 I/O Circuit (Analog or Digital) DC at Analog signal normal Amplitude Oparation （Vp-p） （Ｖ） 1.5 2.5 1.25 1.2 0 3.3 0 1.5 0 3.3 3.3 0 0 0 0 1.5 0 0 1.5 0 0 3.3 0 0.5∼ VDDPLL*0.8 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VREFDA VDDPLL PLLIN VCOFIL VSSPLL VDDXO XOIN XOOUT VSSXO TDIO9 TDIO8 TDIO7 TDIO6 TDIO5 DVDD1 TDIO4 TDIO3 TDIO2 DVSS1 TDIO1 TDIO0 TDCLK VDDIO3 BUSSEL RESET SDA SCL TESTM1 TESTM2 TESTM3 TESTM4 DVDD2 CSYNCIN DVSS2 YOUT9 YOUT8 YOUT7 YOUT6 DVDD3 YOUT5 YOUT4 DVSS3 YOUT3 YOUT2 VSSIO1 YOUT1 YOUT0 CKOUT VDDIO1 TESTM5 The reference voltage terminal of DAC Power supply for X8 PLL circuit Input terminal of X8 PLL circuit Filter terminal for X8 PLL circuit GND for X8 PLL circuit Power supply for X’ tal OSC circuit X’ tal OSC circuit input terminal X’ tal OSC circuit output terminal GND for X’ tal OSC circuit Bypass VDD IN Bypass GND VDD IN OUT GND I/O I/O I/O I/O I/O VDD I/O I/O I/O GND I/O I/O IN VDD IN IN I/O IN IN IN IN IN VDD IN GND OUT OUT OUT OUT VDD OUT OUT GND OUT OUT GND OUT OUT OUT VDD IN Analog Terminal for Test mode （Normaly Open） Power supply for Logic circuit Terminal for Test mode （Normaly Open） GND for Logic circuit Terminal for Test mode （Normaly Open） Power supply for I/O IICBUS slave address selection(L:B0､Hi:B2) Reset terminal (Low :Reset Hi :normal) ＩＩＣ ＳＤＡ terminal (5V input possible） ＩＩＣ ＳＣＬ terminal (5V input possible) Terminal for Test mode （Normaly connect to GND） Power supply for Logic circuit External composite Sync signal input （In case not use external CSYNC, conect to ＧＮＤ） GND for Logic circuit Digital video port output 9 （MSB） （656/ 601 mode：YCbCr, 601：Y） Digital video port output 8 Digital video port output 7 Digital video port output 6 Power supply for Logic circuit Digital video port output 5 Digital video port output 4 GND for Logic circuit Digital video port output 3 Digital video port output 2 GND for I/O Digital video port output 1 (In case 8bit output mode : fixed to Low) Digital video port output 0 (In case 8bit output mode : fixed to Low) System Clock output terminal for digital video signal output. 656 : 27MHz 601 : 13.5MHz Power supply for I/O Terminal for Test mode（Normaly connect to GND） Digital Feb./2005 3 TC90101FG Piｎ No Piｎ Name Function （ ）：Condition at normal operation Durable ｖoltage (V) 3.3 3.3 I/O Circuit (Analog or Digital) DC at Analog signal normal Amplitude Oparation （Vp-p） （Ｖ） 0 - 51 52 TESTM6 COUT0 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 COUT1 DVDD4 COUT2 COUT3 DVSS4 COUT4 COUT5 VDDIO2 COUT6 COUT7 VSSIO2 COUT8 COUT9 DVDD5 UVFLAG HDOUT DVSS5 VDOUT ODD/EVEN VBIREADY CGP YCLAMPP1 YCLAMPP2 BIASYAD VRTYAD YIN VSSYAD VRMYAD CVBSIN VDDYAD VRBYAD BIASCAD VRTCAD CIN VSSCAD CbIN VDDCAD VRBCAD BIASRAD VRTRAD VSSRAD CrIN VDDRAD VRBRAD VDDDA DAOUT Terminal for Test mode（Normaly connect to GND） ＣbＣr digital video signal output (LSB） （656：COUT0-9 are fixed Low 601：CbCr） （In case 16bit mode: This terminal is fixed Low) ＣbＣr digital video signal output (2 nd LSB） （In case 16bit mode: This terminal is fixed Low) Power supply for Logic circuit ＣbＣr digital video signal output 2 ＣbＣr digital video signal output 3 GND for Logic circuit ＣbＣr digital video signal output 4 ＣbＣr digital video signal output 5 Power supply for I/O ＣbＣr digital video signal output 6 ＣbＣr digital video signal output 7 GND for I/O ＣbＣr digital video signal output 8 ＣbＣr digital video signal output 9 (MSB) Power supply for Logic circuit Reference timing pulse for multiplexed Cb/Cr signal Horizontal reference timing pulse GND for Logic circuit Vertical reference timing pulse Field index output Reference timing pulse of IIC read for VBI data slice Function (Hi level at 23 line and 286 line) Clamp gate timing pulse Clamp signal output for CVBSIN Clamp signal output for YIN Bias terminal for internal 10bit ADC Reference top voltage terminal for internal 10bit ADC Analog Y signal input terminal (10bit ADC) GND for internal 10bit ADC The reference middle voltage terminal for Internal 10bit ADC Analog CVBS signal input terminal (10bit ADC) Power supply for internal 10bit ADC Reference bottom voltage terminal for internal 10bit ADC Bias terminal for internal 8bit C/Cb-ADC Reference top voltage terminal for internal 8bit C/Cb-ADC Analog C signal input terminal (8bit ADC) GND for internal 8bit C/Cb-ADC Analog Cb signal input terminal (8bit ADC) Power supply for internal 8bit C/Cb-ADC Reference bottom voltage terminal for 8bit C/Cb-ADC Bias terminal for internal 8bit Cｒ-ADC Reference top voltage terminal for 8bit Cr-ADC GND for internal 8bit Cr-ADC Analog Cb signal input terminal (8bit ADC) Power supply for internal 8bit Cr-ADC Reference bottom voltage terminal 8bit Cr-ADC Power supply for internal DAC of NCO Output terminal of DAC of NCO GND for internal DAC of NCO Bias terminal for internal DAC IN OUT 3.3 1.5 3.3 3.3 0 3.3 3.3 3.3 3.3 3.3 0 3.3 3.3 1.5 3.3 3.3 0 3.3 3.3 3.3 3.3 3.3 3.3 2.5 2.5 2.5 0 2.5 2.5 2.5 2.5 2.5 2.5 2.5 0 2.5 2.5 2.5 2.5 2.5 0 2.5 2.5 2.5 2.5 2.5 0 2.5 OUT VDD OUT OUT GND OUT OUT VDD OUT OUT GND OUT OUT VDD OUT OUT GND OUT OUT OUT OUT OUT OUT Bypass Bypass IN GND Bypass IN VDD Bypass Bypass Bypass IN GND IN VDD Bypass Bypass Bypass GND IN VDD Bypass VDD OUT GND Bypass 1.5 0 3.3 0 1.5 0 0.8 1.75 0 1.25 2.5 0.75 0.8 1.75 1.25 0 2.5 0.75 0.8 1.75 0 2.5 0.75 2.5 2 0 0.9 VDDYADx0.4 VDDYADx0.4 VDDCADx0.4 VDDCADx0.4 VDDRADx0.4 VDDDA-VDDD A*0.6 - Digital Analog 99 VSSDA 100 BIASDA (Note) Please place the capacitor at near the terminal. Please take care Surge for the IIC I/F terminals. Feb./2005 4 TC90101FG ４．Functional Description 4.1 General Description TC90101FG is a Video decoder device for multi color system (525i. 625i). TC90101FG also has a through mode and sync processing for 525p & 625p component signal. 1.TC90101FG has input interface for CVBS，S-Video, YＣbＣr. For RGB signal it needs some external circuit as below. CVBS LPF SCART G Ｂ R RGB → YCbCr AMP/LPF AMP/LPF AMP/LPF Y Ｃb Ｃr TC90101FG CGP 2. Automatic clamp control circuit. 3. Multi 3line comb filter. 4. Multi color decoder and sync processing. 5. Color system detection circuit. (Selectable auto detection and manual setting.) Result of color system dtection can be read via IIC. 6. Frequncy detection circuit for 525i/525p/625i/625p for component signal. 7. AGC circuit circuit at after stage of ADC. 8. Picture processing circuit for CVBS, S-Video, 525i/625I component signal. 9. Selectable ITUR-601, ITUR-656 output interface. 10. VBI data slice function (525i ID-1/525p ID-1/ CCD/ WSS). It can be read via IIC. 11. Macrovision detection circuit. 12. Noise level detection circuit. 13. Superposition function for IIC read data on ITUR-656 ouitput. 4.2 Fanctional Discription 1. Clock System TC90101FG has a digital VCO circuit which uses 42MHz free run X’tal OSC. Digital VCO circuit generates 27MHz fH clock for input stage, 4fsc clock for internal comb block And 13.5MHz for output stage. 2.0 Input interface Input signal CVBS Y(S-Video & Component ) C(S-Video & Component ) Cb Cr Pin name CVBS IN YIN CIN Cb IN Cr IN Terminal 81 78 86 88 94 2.1 Selection input signal Input signal can be set via INSEL at sub address 00hex. INSEL : 00 : CVBS 01: S-Video 10: YCbCr 11: SCART( ** ) ( * ) : it’s not available to input RGB signal dilectlly. It’s needs RGB to YCbCr conversion circuit at the before stage of TC90101FG. In this mode CVBS must be inputted to CVBIN for sync processing, noise dtection and VBI data slice. Feb./2005 5 TC90101FG 2.2 Input signal amplitude TC90101FG has a 10bit ADC for CVBS & Y signal and 2ch 8bit ADC for C & Cb/Cr. The Dynamic range of ADC is desgned as AVDD *0.4 (Normally 1Vpp at AVDD = 2.5V). The recomemdation amplitude of the input signal : 0.7Vpp at 140IRE (CVBS/Y) . refer to fig-1. * in case of AGC ON, recommendation input signal amplitude is 0.6Vpp (140IRE). (AGC control range is from - 6dB to +3dB.) 1023 100 80 60 40 20 0 -20 -40 51 0 256 0.7Vp-p AVDD×0.4V 767 Fig-1. Amlitude of CVBS input 255 〈IRE〉 20 0 -20 153 128 0.2Vp-p 103 0 Fig-2. Amlitude of C input 255 217 128 0.7Vp-p 39 0 Fig-3. Amlitude of base band C signal input Feb./2005 6 TC90101FG The amplitude of input signal for 10bit ADC is 0.7Vp-p as 140IRE. in case of C signal for S-video. The amplitude of input signal for C ADC is 0.2Vp-p as 40IRE. (Refer to Fig-2.) The amplitude of input signal for Cb/Cr is 0.7Vp-p as 100% level. (Refer to Fig-3.) (VDD = 2.5V) Input signal vs output signal level Input signal Input signal amplitude： Ouput signal level（LSB） Vp-p（※） CVBS 16-235(pedestal to white 100%) （8bit mode） 0.7Vp-p（500mVp-p） 16-235(pedestal to white 100%) （8bit mode） Ｙ 0.7Vp-p（500mVp-p） C 16-240（8bit mode） 0.2Vp-p（Burst） Cb 0.7Vp-p (100% color) 16-240（8bit mode） Cr 0.7Vp-p (100% color) 16-240（8bit mode） ※ Input signal amplitude： For CVBS and Y, it means 100% level (140IRE). (500mVp-p: pedestal to white 100%.) Cb/Cr, it means 100% color bar Signal. Notice: Ｔｈｅｓｅ amplitude of output signal have done by initial value of IIC registers related with gain. 3. Clamping The clam control circuit controls the corect clamping for input signals. TC90101FG has a feed back clamp for H-Sync portion of CVBS/Y input signal to clamp 256LSB(10bit unit). It is selectable to use the 2 types of the feed back clamp (internal circuit or external circuit) via IIC bus. (FBCLMPEX at sub address 03 hex.) In case use external, the clamp signal from YCLAMP1,YCLAMP2(pin 74,75) to be connected with input Terminals. (refer to application circuit.) For C signal, it is biased to 128 LSB. For Cb and Cr signal, it is used keed clamping control to 128 LSB. Input mode CVBS S- Video/ YCbCr CVBS+ YCbCr (1H) Input signal CVBS Y C Cb/Cr CVBS Y Cb/Cr Pin number 81 78 86 88/94 81 78 88/94 ADC 10bit 10bit 8bit 8bit 8bit 10bit 8bit(ＭＰＸ) Feed back clamp − Keed clamp Sync chip clamp Feed back clamp Keed clamp Clamping function Comment Time constant is selectable for internalClamping mode via BUS FBCLMOD atSub address 32hex. Biased to 128LSB 4. TV system detection for CVBS and S- Video input TC90101FG has 4 types of detection mode and it is selectable via AUTDET at sub address 00hex. AUTODET 00 01 10 Mode Manual setting EU South America Fsc detection 4.4336MHz 3.57954MHz 3.57954MHz 3.5756MHz 3.5820MHz 4.4336MHz 3.57954MHz 3.5756MHz 3.5820MHz Commemt TV system is set via TV0 – TV3 at sub address 00hex. Priority : 4.43MHz PAL→ NTSC→ SECAM (it’s not available to detect 3.58MHz PAL signal.) Priority : 3.58MHz PAL→ 3.58MHz NTSC (it’s not available to detect 4.43MHz fsc signal.) 11 Full multi Priority : PAL→ NTSC→ SECAM There is not priority for 50Hz/60Hz(Vertical frequency) detection. VD output (pin 70) is controled via VD.DET at sub address 23hex. [00] : free run. [01] : fixed mode when it detects no signal (The frequency of VDOUT is depends on TVM2.) [10] : Fixed Frequency at Manual setting mode. [11] : VDOUT is depends on TVM2 at all of TV system detection mode. Feb./2005 7 TC90101FG 5. H/V Sync processing TC90101FG has H/V sync separation circuit and regenrates HD/VD pulse. The phase and width of HD/VD pulse are controled via THRHV at sub address 22hex. [0] : 656 format. [1] : Syncronized with input signal. 6. D2 signal (525p/525p component) processing TC90101FG has D1 and D2 detection circuit and Sync processing for D2 signal. D2 signal is converted as 4:2:2 digital signal by internal ADC. (Sampling rate of Y ADC is 27MHz.) ID-1 data slice for 525p is available but It’s not available to use picture implrovement function and Noise level detection, (The sliced data of ID-1 can be read via IIC.) 7. T.O.F (Take Off filter) TC90101FG has Take Off filiter which is in front of color decoder. Characteristic of T.O.F is set via TOF at sub address 0C hex. [000] : Off [001] : type 1- [111] : type 7 (Type 1 : BPF.) 8. Y process a) Vertical enhancement : adjustable coring, gain, and non-linear performance b) LTI function The performance of this function is controlled via Iregisters at 04 and 05 hex. f0 : 3.3MHz / 2.2MHz Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE Gain : Off / 1/8 / 1/4 / 1/2 c) Sharpness The performance of this function is controlled via Iregisters at 02 and 03 hex. f0 : 4.2MHz / 3.3MHz Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE Gain : -1/4 - Off - 1/2 LTI Sharpness/ Noise canceｌ ＋ ｆ0/Gain/Coring ｆ0/Gain/Coring d) Noise canceller The performance of this function is controlled via Iregisters at 04 hex. f0 : 4.2MHz / 3.3MHz ( It uses same register with f0 of sharpness control.) Coring : 0.8IRE/1.6IRE/3.2IRE/6.4IRE Gain : -1/4 - Off - 1/2 e) Contrast Control range : ×(1/2) - ×2.4 f) Brightness it’s effective at the periode of picture signal portion. Control range : -128LSB - 128LSB ( 10bit unit) 9. C process a) ACC control : A reference level is set up by register ACC LEVEL. b) Killer control : sensitivity of killer is set via [BUS KILLV] at sub address 37 hex. In case Killer detection, comb filter for Y becomes off. c) HUE control : Hue control is available for CVBS and C signal of NTSC system. Hue bias : 0 --- +45degree Hue range : -45 degree --- +43.6degree d) Sub color gain control Amplitude of Cb and Cr signals are controlled via IIC. Control range is –6dB --- +2.8dB Feb./2005 8 TC90101FG e) CTI function f0 is selectable (1.7MHz/ 3.3MHz). Coring level is selectable (0.4IRE/ 0.8IRE/ 1.6IRE/ 3.2IRE). Gain is selectable (OFF/ x1/8 / x1/4 / x1/2). f) Offset control of the period of picture area The DC level of the Cb and Cr signals are controlled via IIC independently. Control range : -8LSB ---- +7LSB (10bit unit) 10. Output format Output format (data format/clock/phase) is controlled via IIC Bus. Y：The Pedestal level is 16LSB at 8bit output format and 64LSB at 10bit output format. C：The signal level is 128LSB except for picture periode at 8bit output mode. (10bit mode: 512LSB) The output format (656/601) is set via FORMATO (01h,D3) and the Dynamic range is set via OUTBITS(01h､D2) Picture periode of Y output can be controlled by CLP (20h,D0). CLP = [1] : the signal of under 16LSB (8bit mode) is sliced at 16LSB. (standard mode.) CLP = [0] : It’s available to output the signal of under 16LSB. Normaly it must be set [1]. Output Terminals YOUT [0-9] (note) COUT [0-9] (note) Bit 10 10 Cｂ/Cｒ（CLK：13.5MHz） Reference timing pulse for Cb/Cr UVFLAG 1 (13.5/2)MHｚ Polarity : Cr = High(Initial value) 1 864fH/1728fH：625line source 13.5MHz/27MHz(/54M CKOUT (note) 858fH/1716fH：525line source Hz) Polarity : Reversal(Initial value) HDOUT 1 Re-generated HD ｆH VDOUT 1 Re- generated VD ｆV ODDEVEN 1 Field indication ｆV VBIREADY 1 Flag after VBI data slicing ｆＶ Note : YOUT, COUT, CKOUT has Hi impeadance mode. (01h,D1) a) 525ｉ/60Hz CVBS input mode Data rate 13.5MHz/27MHz (601/656) 6.75MHz Comment Y/YCｂCr（601/656） ＣＶＢＳ ５２５   １    ２     ３     ４    ５     ６    ７    ８     ９     １０   …    １９     ２０ ＨＤＯＵＴ Sync Through 同期ｽﾙｰ Mode ＶＤＯＵＴ ＯＤＤ/ＥＶＥＮ ＶＤＯＵＴ ＯＤＤ/ＥＶＥＮ FIELD 1 FIELD 1 ﾓｰﾄﾞ 656 656 準拠 Mode ﾓｰﾄﾞ （1ｓｔ Field） Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656： Field１： Line 4 EAV Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 1 EAV、 Ｆｉｎｉｓｈ→ Line 10 EAV VBI READY： High level output → from Line 23 SAV to Line 24 EAV Feb./2005 9 TC90101FG （2nd Field） ＣＶＢＳ ２６３ ２６４ ２６５ ２６６ ２６７ ２６８ ２６９ ２７０ ２７１ ２７２ ２７３ … ２８２ ＨＤＯＵＴ ＶＤＯＵＴ Sync Through 同期ｽﾙｰ Mode ﾓｰﾄﾞ ＯＤＤ/ＥＶＥＮ 656 656 準拠 Mode ﾓｰﾄﾞ FIELD 2 ＶＤＯＵＴ ＯＤＤ/ＥＶＥＮ FIELD 2 Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656： Field 2： Line 266 EAV Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 264 EAV、 Ｆｉｎｉｓｈ→ Line 273 EAV VBI READY： High level output → from Line 286 SAV to Line 287 EAV b) 625ｉ/50Hz CVBS input mode （1ｓｔ, 3rd Field） ＣＶＢＳ ６２１ ６２２ ６２３ ６２４ ６２５ １ ２ ３ ４ ５ ６ … ２２ ２３ ＨＤＯＵＴ ＶＤＯＵＴ Sync Through ﾞ Mode ＯＤＤ/ＥＶＥＮ FIELD 1 ﾞ 656 Mode ＶＤＯＵＴ ＯＤＤ/ＥＶＥＮ FIELD 1 Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656： Field１： Line 1 EAV Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 624 EAV、 Ｆｉｎｉｓｈ→ Line 23 EAV VBI READY： High level output → from Line 64 SAV to Line 65 EAV Feb./2005 10 TC90101FG （2nd ,4th Field） ＣＶＢＳ ３０９   ３１０   ３１１  ３１２   ３１３   ３１４   ３１５  ３１６   ３１７  ３１８   ３１９    …    ３３５  ３３６ ＨＤＯＵＴ 同期ｽﾙｰ Sync Through Mode ﾓｰﾄﾞ ＶＤＯＵＴ ＯＤＤ/ＥＶＥＮ FIELD 2 Mode 656 準拠 ＶＤＯＵＴ ﾓｰﾄﾞ 656 ＯＤＤ/ＥＶＥＮ FIELD 2 Selectable Sync through mode and 656 mode via THRHV at sub address 22hex. 656： Field 2： Line 313 EAV Ｆｉｅｌｄ Ｂｌａｎｋｉｎｇ ； Ｓｔａｒｔ→ Line 311 EAV、 Ｆｉｎｉｓｈ→ Line 336 EAV VBI READY： High level output → from Line 377 SAV to Line 378 EAV The pulse width of HD/VD output at Sync through mode 525i 625i HD pulse width 4.74μｓ (128 cycle (unit: 27MHz clock) VD pulse width ３Ｈ 2.5H Notice： 656 output mode The width of HD pulse is same as the period of between EAV and SAV. In case of input non standard signal, it may not be above value. Feb./2005 11 TC90101FG 11. Feature function a) S/N detection (noise level detection) Noise level detection is performed in the vertical blanking period. The result of noise level detection is stored to IIC read register and it is performed at every field. The related write registers are as follows. EN NOISEV S (sub address 1B hex) : Setup of start line for noise detection. EN NOISEV W (sub address 1A hex) : Setup of the numbers of lines for noise detection . EN NOISEH S (sub address 1A hex) : Setup of start position for noise detection at selected line. EN NOISEH W(sub address 1A hex) : Setup of the period for noise detection at selected line. Reference position 5.3μs EN NOISEH S EN NOISEH W b-1) Video ID (ID-1) data slice function for NTSC 525i signal (CVBS/S-video/Component) ID-1 data slicing is performed at line 20 and 283 in the vertical blanking period. The sliced data is stored to IIC read register and it is performed at every field. b-2) Video ID (ID-1) data slice function for NTSC 525p signal (Component) ID-1 data slicing is performed at line 41 in the vertical blanking period for NTSC 525p signal. The sliced data is stored to IIC read register and it is performed at every vertical blanking periode. c) CCD data slice function for US area(NTSC 525i signal (CVBS)) CCD data slicing is performed at line 21 and 284 in the vertical blanking period. The sliced data is stored to IIC read register and it is performed at every field. CRI detection, start bit detection and sliced data can be read via IIC bus. d) WSS data slice function for EU area (PAL 625i signal (CVBS)) WSS data slicing is performed at line 23 and 336 in the vertical blanking period. The sliced data is stored to IIC read register and it is performed at every field. RUN-IN detection, start ｃｏｄｅ detection and sliced data can be read via IIC bus. e) Macrovision detection TC90101FG can detect a pseudo sync, AGC pulse and color stripe. The result of Macrovision detection can be read via IIC bus. ｆ） AGC function TC90101FG has an AGC function for CVBS and Y signal (S-video). The related write registers are as follows. PAGCON (sub address 2B hex) : Setup for PEAK AGC function. PKLIM (sub address 2B hex) : Setup for limit level for PEAK AGC function. SAGCON (sub address 2B hex) : Setup for SYNC AGC function. (Through mode : Both registers (PAGCON & SAGCON) must be set [0]. ) Feb./2005 12 TC90101FG 12. Insertion of IIC read data for output TC90101FG has IIC read data insert mode for ITU-656 out put format. It’s also available for ITU-601 mode. These functions are based on ARIB STD-B6. Selection of the line for IIC read data insertion is set via register at sub address 25hex and 26hex . ①25H D7：Insertion ON / OFF control for Horisontal blanking periode. ②25H D6：Insertion ON / OFF control for Vertical blanking periode. ③25H D5：Selection of insertion for ITU-601 mode ④25H D4-D0：Line selection of insertion for Horizontal blanking periode. ⑤26H D7-D4：Line selection of insertion for Vertical blanking periode. TC90101FG uses “the 2nd form of ARIB " ADF DID SDID DC UDW CS ADF DID SDID DC UDW CS ：Auxiliary signal flag word （Fixation） 3 word ：For discernment （set by register） ：For discernment 2nd data（set by register） ：Data count code（the numbers of UDW word） ：User data word （main data） ：Check sum (DID∼UDW) ●ＡＤＦ ADF uses fixed value. 1) at the 10bit mode 000h 3FFh 3FFh 2) at the 8 bit mode 00h FFh FFh ●ＤＩＤ DID has 4bit control registers （26H：D3-D0）. 1) For 10bit mode. D9(MSB) D8 D7(MSB) 0 D8 D[7:0]の偶数パリティビット D6 0 D5 0 D7 0 D4 0 D6 1 D5 0 D3 DID3 D4 0 D3 DID3 D2 DID2 D2 DID2 D1 0 D1 DID1 D0(LSB) DID0 D0(LSB) 0定 2) For 8bit mode. （Notice） DID[3:2]＝00 is not available when use 8bit mode. ●SDID SDID has 4bit control registers （27H）. 1) For 10bit mode. D9(MSB) D8 D7(MSB) SDID7 D8 D[7:0]の偶数パリティビット D7 SDID7 D6 SDID6 D5 SDID5 D4 SDID4 D3 SDID3 D2 SDID2 D1 SDID1 D0(LSB) SDID0 2) For 8bit mode. D6 SDID6 D5 SDID5 D4 SDID4 D3 SDID3 D2 SDID2 D1 0 D0(LSB) 0 （Notice） DID[7:2]＝0000 00 is not available when use 8bit mode. ●ＤＣ DC uses Fixed value. 1) For 10bit mode. D9(MSB) 0 D7(MSB) 0 D8 1 D6 1 D7 0 D5 0 D6 0 D4 0 D5 1 D3 1 D4 0 D2 0 D3 0 D1 0 D2 0 D0(LSB) 0 D1 0 D0(LSB) 0 2) For 8bit mode. Feb./2005 13 TC90101FG ●ＵＷＤ ＜I2C Read Bus → ６５６ insertion specification.＞ In case of 1byte Read register (RD[7:0]), it is superposed as below ・Read register 1 byte. RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 ・６５６ insertion： 1st word. D7 0 D6 1 D5 RD7 D4 RD6 D3 RD5 D2 RD4 D1 0 D0 0 D(-1) D(-2) 0,0 (10bit mode) ・６５６ insertion： 2nd word D7 0 D6 0 D5 RD3 D4 RD2 D3 RD1 D2 RD0 D1 1 D0 0 D(-1) D(-2) 0,0 (10bit mode) ●ＣＳ Check sum means total value of ＤＩＤ to ＵＷＤ as below. １）10bit mode It calculates total value of the 9bits low ranks of DID, SDID, DC and all of UDW. MSB(D9) means D8 of calculated valu. (it ignores the over flow.) D9 D8 D8 D7 D6 D5 D4 D3 D2 D1 D0 Total value of the 9bits low ranks of DID, SDID, DC and all of UDW. (it ignores the over flow.) ２）８ｂｉｔ mode It calculates total value of the 7bits low ranks of DID, SDID, DC and all of UDW. MSB(D7) means D6 of calculated valu. (it ignores the over flow.) D7 D6 D6 D5 D4 D3 D2 D1 D0 Total value of the 9bits low ranks of DID, SDID, DC and all of UDW.(it ignores the over flow.) Feb./2005 14 TC90101FG 4. IIC BUS TC90101FG has two slave address (B2 hexand B0hex). A slave address is chosen by BUSSEL Terminal which is pin 24. (BUSSEL=L：B0hex , BUSSEL=H：B2hex）。 R/ W A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 0 X X ・Data transmission format S Slave Address 7bit MSB MSB 0A Sub Address 8bit MSB A Data 8bit AP S: Start condition P: Stop condition A: Acknowledgement (1) Start condition, Stop condition (2) Bit transmission SDA SDA SCL S Start conditions P Stop conditions SCL SDA is not changed. SDA is changed. (3) Acknowledgement SDA from Master High impedance High impedance SCL from Master S Start conditions 1 8 9 Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Feb./2005 15 TC90101FG IIC BUS Sub 00H MAP D5 D4 D3 D2 D1 D0 AUTODET TVM3 TVM2 TVM1 TVM0 Color system detection mode FSC selection FV selection PAL selection SECAM selection 00：Manual （00h-D5･･D2 : Active） 0：3.58MHz 0：60Hz 0：Not PAL 0：Not SECAM 01：EU mode 1：4.43MHz １：50Hz 1：PAL 1：SECAM 10：South America 0000：NT358 0100：NT50 1000：NT443 1100：don't use 11：Full detection mode 0001：don't use 0101：don't use 1001：SEC60 1101：SECAM 0010：PAL-M 0110：PAL-N 1010：PAL60 1110：PAL 0011：don't use 0111：don't use 1011：don't use 1111：don't use SELCK YCS Mode FORMATO OUTBITS HIZMODE ADPWD Frequency of CKOUT(pin48) selection 3LYCS selection Fixed to [0] setting of output Stand by mode 0：3line 10：54MHz 00：13.5MHz 0：Rec601 0：8bit 0：Normal 0：ADC-OFF 1:BPF 11：13.5MHz 01：27MHz 1：Rec656 1：10bit 1：Open 1：Normal V ENH GAIN V ENH MAX POINT V ENH SLICE LEVEL FENH PRENH V Enhance Gain V Enhance Non-linear Ｖ Enhance Coring Sharpness fo Pre Enhance 00：OFF 10：×1/4 00： 6IRE 10：13IRE 00：ＯＦＦ 10：1.6IRE 0：4.2MHz 0:OFF 01：×1/8 11：×1/2 01： 9IRE 11：16IRE 01：0.8IRE 11：2.3IRE 1：3.3MHｚ 1:ON SHARPNESS GAIN SHARPNESS SLICE LEVEL FBCLAMP FBCLMPEX Sharpness Gain Adjustment Shrpness coring F/B CLAMP FB CLAMP mode 1000:(don't use) 1100:-3/16 0000:1/16 0100:5/16 0：Auto mode 0: External 1001:(don't use) 1101:-2/16 0001:2/16 0101:6/16 00：0.8IRE 10：3.2IRE 1：Always ON 1: Internal 1010:(don't use) 1110:-1/16 0010:3/16 0110:7/16 01：1.6IRE 11：6.4IRE 1011:-4/16 1111:OFF 0011:4/16 0111:8/16 NOISE CANCEL GAIN SET DELAY FLTI FCTI Gain Adjustment Cb and Cr Delay Adjustment LTI fo CTI fo 0000：-296ns ∼ 1000：Center ∼ 1111：259ｎｓ（37ns unit） 00：OFF 10：×1/2 0：3.3MHz 0：1.7MHz 01：×1/4 11：×1 1：2.2MHｚ 1：3.4MHz CTI GAIN CTI SLICE LEVEL LTI GAIN LTI SLICE LEVEL ＬＴＩ Gain Adjustment ＬＴＩ Coring CＴＩ Gain CＴＩ Coring 00：OFF 10：×1/4 00：0.8IRE 10：3.2IRE 00：OFF 10：×1/2 00：0.4IRE 10：1.6IRE 01：×1/8 11：×1/2 01：1.6IRE 11：6.4IRE 01：×1/4 11：×3/4 01：0.8IRE 11：3.2IRE CONTRAST Contrast Adjustment 00h：ｘ１/2 ∼ 40h：ｘ1 ∼ FFh：ｘ2.4 BRIGHTNESS Brightness Control 10000000：-128LSB ∼  00000000：0LSB ∼ 01111111：+128LSB（１０ｂｉｔ） CR OUTPUT GAIN CB OUTPUT GAIN Ｃｒ Gain Adjustment Ｃｂ Gain Adjustment 1000：×1/2 ∼ 0000：×１ ∼ 0111：×1.4 1000：×1/2 ∼ 0000：×１ ∼ 0111：×1.4 CR OUTPUT OFFSET CB OUTPUT OFFSET Ｃｒ Output Offset Adjustment Ｃｂ Output Offset Adjustment 1000：-8LSB ∼ 0000：０ ∼ 0111：+7LSB （１０ｂｉｔ） 1000：-8LSB ∼ 0000：０ ∼ 0111：+7LSB （１０ｂｉｔ） HUE FP_FIL filter for Feed HUE adjustment ( for NTSC signal) back 1000000：−４５° ∼ 0000000：０° ∼ 0111111：＋４３．６° ０：OFF １：ON HUE BIAS CLPFOF DCLAMP_VMASK HUE bias adjustment (Adjustment for the demodulation phase of R-Y ( NTSC only) C Trap (burst ) V mask of digital 000000：０° ∼ 111111：＋４５° (for degital clamp) clamp 0：OFF 0：OFF １：ON 1：ON Y INPUT OFFSET ＴＯＦ BUS_DCOMTRP2 DCOMB out Offset adjustment for clamp Y input Take off filter selection C Trap 000：OFF , 001：BPF, 1000：-31mV ∼ 0000：0mV ∼ 0111：+27mV 0：OFF 010：MIN ∼ 111：MAX 1：ON D6 INSEL Input signal selection 00：CVBS 01：Y/C（S-Video） 10：YCbCr（D1or D2 Component） 11：CVBS+ＹCbCr(for SCART） D7 INIT:03H 01H INIT:33H 02H INIT:34H 03H INIT:F0H 04H INIT:08H 05H INIT:00H 06H INIT:40H 07H INIT:00H 08H INIT:00H 09H INIT:00H 0AH INIT:01H 0BH INIT:03H 0CH INIT:00H 0DH INIT:00H 0EH Y ClampPulse_F Phase adjustment of digital clamp for Y 000：1.19μｓ ∼ 111：3.26μｓ CR INPUT OFFSET Offset adjustment for Cr input 1000：-31mV ∼ 0000：0mV ∼ 0111：+27mV Y ClampPulse_W Adjustment of Clamp widthfor Y digital clamp 000：0.9μｓ ∼ 111：2.96μｓ INIT:00H 0FH INIT:00H DIGITAL Y CLAMP Time constant of Y digital clamp 00：OFF 10：mediam 01：small 11：large CB INPUT OFFSET Offset adjustment for Cb input 1000：-31mV ∼ 0000：0mV ∼ 0111：+27mV * : Every blank register must be set “0”. Feb./2005 16 TC90101FG Sub 10H INIT:00H 11H D5 D4 D3 D2 D1 D0 CICLMPP_S CICLMPP_W Adjustment of input clamp phase for analog Cb/Cr Adjustment of input clamp width for analog Cb/Cr 1000：-1.185μｓ ∼ 0000：±０ ∼ 0111：+1.04μｓ 1000：-1.185μｓ ∼ 0000：±０ ∼ 0111：+1.04μｓ C ClampPulse_F C ClampPulse_W DIGITAL C CLAMP Adjustment of digital clamp phase for Cb/Cr Adjustment of digital clamp width for Cb/Cr Time constant of Cb/Cr digital clamp 000：1.19μｓ ∼ 111：3.26μｓ 000：0.9μｓ ∼ 111：2.96μｓ 00：OFF 10：mediam 01：small 11：large COLOR KILLER LEVEL ACC LEVEL CONFIX Adjustment the sensitivity of the killer detection Adjustment ＡＣＣ reference level Killer function 000：Max ∼ 111：Ｍｉｎ 0000：Ｍｉｎ ∼ 1111：Ｍａｘ 〔Initial：1000〕 0：normal 1：killer off DOT DIST CGAIN COMB+ 1LINE DOT COM443N Reduse dot ( Horizontal) ＳＥＣＡＭ用 Ｙ trap performance Comb selection for 443NTSC 000：ＯＦＦ ∼ １１１：×0.875（Intial：011） 00：OFF 10：ｘ0.17 0：OFF 0：OFF 01：ｘ0.16 11：ｘ0.18 1：ON 1：ON 0:1H Comb 1:2H Comb SYNC TIP CLAMP１ EXTERNAL SYNC SEPA LVL VSEPLVL VLMT HHKIL Mode selection for external sync Sync tip clamp mode for CVBS Sync sepa. Level V sepa mode V sepa limit AFC V mask 00：OFF(internal) 10：CsyncL 0:30% 00：ON 10：AUTO１ 0： 1/8 0：OFF 01：CsyncH 11：VsyncH 1:40% 01：OFF 11：AUTO２ 0：5/16 1： 1/16 1：ON 1：1/2 SHCTRL MUTE C MUTE Adjustment Horizontal phase reference picture mute Cb/Cr out mute 100000：-4.74μｓ ∼ 000000：±０μｓ ∼ 011111：+4.46μｓ（1/6.75MHzｽﾃｯﾌﾟ） 0：OFF 0：OFF 1：ON 1：ON HDAMP1 HD GAIN1 Time constant 1 fpr H PLL(Phase difference: big) Loop gain 1 for H PLL(Phase difference: big) 000：large ∼ 111：small 00000：small ∼ 11111：large HDAMP2 HDGAIN2 Loop gain 1 for H PLL(Phase difference: middle) Time constant 2 fpr H PLL(Phase difference: middle) 000：large ∼ 111：small 00000：small ∼ 11111：large HDAMP3 HDGAIN3 Loop gain 1 for H PLL(Phase difference: small) Time constant 3 fpr H PLL(Phase difference: small) 000：large ∼ 111：small 00000：small ∼ 11111：large HGCON12 HGCON21 Threshold level at the phase diffrence large to middle Threshold level at the phase diffrence middle to big 0000:OFF ∼ 1111:High 0000:OFF ∼ 1111:High EN_NOISEH_S EN_NOISEH_W EN_NOISEV_W Adjustment the width for noise detection Adjustment start phase for noise detection Noise detection line numbers 000：32.2uS ∼ 100：36.9uS ∼ 111：40.5uS 000：9.4uS ∼ 100：14.1uS ∼ 111：17.7uS 00：1H 10：3H 01：2H 11：4H VSRACH EN_NOISEV_S FLOCK Adjustment start line for noise detection fsc lock period HPLL Gain at lock 000：0H ∼ １11：+15H 0：1/2 00：3V 01：4V 60Hz：line ７ is as 0H 1：no change 10：5V 11：6V 50Hz：line ４ is as ０Ｈ HDPH VDPH Adjustment horizontal phase for digital output Adjustment Vertical phase for digital output 1000：-1.185uS ∼ 0000：0uS ∼ 1111：+1.04uS 0000：0H ∼ 1111：+15H EN_PIXH_S EN_PIXH_W Adjustment start phase of horizontal signal processing Adjustment width of horizontal signal processing 1000：-1.185μｓ ∼ 0000：cemter ∼ 0111：+1.04μｓ 1000：-1.185μｓ ∼ 0000：center∼ 0111：+1.04μｓ COMB KILL EN_PIXV_S EN_PIXV_A Adjustment start phase of vertical signal processing 000：OFF 011：1∼23H 110：1∼26H 0000：line 10 ∼ 1111： line 25 0：Manual 001：１∼21H 100：1∼24H 111：Auto 1：Auto 010：1∼22H 101：1∼25H (60:22H,50:23H) HBLK_S HBLK_W Adjustment start phase of horizontal BLK Adjustment width of horizontal BLK 1000：-2.37μｓ ∼ 0000：±０ ∼ 0111：+2.27μｓ 1000：-2.37μｓ ∼ 0000：±０ ∼ 0111：+2.27μｓ D7 D6 INIT:00H 12H INIT:08H 13H INIT:5BH 14H INIT:1CH 15H INIT:00H 16H INIT:4EH 17H INIT:85H 18H INIT:A6H 19H INIT:48H 1AH INIT:90H 1BH INIT:00H 1CH INIT:00H 1DH INIT:00H 1EH INIT:07H 1FH INIT:00H * : Every blank register must be set “0”. Feb./2005 17 TC90101FG S ub 20H INIT:00H 21H D5 D4 D3 D2 D1 D0 BFP_S VBIVAD[2:0] CLP Adjustment start phase of burst gate Adjustment the pase of VBI data slice 16LSB limit 0000：center ∼ 1111：+4.44μs 100:-4H∼000:center ∼111:3H 0：OFF （ 0.296 μs ste p） 1：ON VPHS HDST BYFOFF BCFOFF Adjustment start phase of V at THRHV=1 Delay adjustment of HDOUT BSRY filter BSRC filter 110：384W 011：192W 000：0W 10：40w 00：32w 111：don't use 100：256W 001：64W 11：44w 01：36w 0：ON 0：ON (1W:27MHz) 101：320W 010：128W (1W:27MHz) 1：OFF 1：OFF PHPOLE PVPOLE PFPOLE THRHV INVCK SEL_BLK YOLEVEL HDOUT polarity VDOUT polarity Field polarity H,V-OUT through CKOUT polarity V.BLK processing 1/1.71875 Y output amplitude 0：active 0：active 0：active 0: 656 0：active 0：normal 0：1.71875 1：ne gative 1：ne gative 1： t hrou gh 1：ne gative 1： t hrou gh 1：1.0 1：ne gative EXVDF VD_DET RBCHG FIELD_DET Adjustment Ext VD phase Control VDOUT Cb/Cr phase Field Det. 0：normal 00：Free run at no -sig. 000：center 011：+5.96us 110：-3.97us 01:Fixed mode 50/60 （ on TVM2） 0：AUTO 001：+1.99us 100：-7.94us 111：-1.99us 1：chan ge 10：Fixed mode at MANUAL mode 1：Fixed Low 010：+3.97us 101：-5.96us 11：Fixed mode for MANUAL mode & no sig at AUTO mode D7 D6 INIT:03H 22H INIT:18H 23H INIT:00H 24H INIT:80H 25H INIT:00H 26H INIT:00H 27H INIT:00H 28H FLDTMSEL SEL_RDATA VCTOLE VCRESET AFC_Cont Adjustment horizontal phase for field detection Start phase of IIC read registers V count V count reset AFC control 000：-5.7μｓ 011：-13.2μｓ 110：-20.9μｓ 001：-8.2μｓ 100：-15.7μｓ 111：-23.2μｓ 0:-H/8 ∼ +H/4 0：OFF 0：OFF 00：CDEC 01：CCD 010：-10.7μｓ 101：-18.4μｓ 1:±H/8 1：ON 1：ON 10：ID1 11：WSS AXD_HSEL[4:0] AXD_HON AXD_VON AXD_SSEL Line number for incert data data insert of H data insert of V data incert NTSC : 21/284 line + AXD_HSEL for 601 format PAL時 : 24/337 line + AXD_HSEL 0：OFF 0：OFF 0：incert to CbCr 1：ON 1：ON 1：incert to Ｙ AXD_VSEL[3:0] DID[3:0] Line number for incert data to field BLK For DID code NTSC :  1line+AXD_VSEL PAL : 1line+AXD_VSEL SDID[7:0] For DID code CSONTIM CSOFTIM strp_idg_wd[1] strp_idg_wd[0] strp_idg_lv[1] strp_idg_lv[0] Ａｄｊｕｓｔｍｅｎｔ histerisis for Adjustment mask periode Sensitivity of Ａｄｊｕｓｔｍｅｎｔ histerisis for Color stripe detect ON for color stripe detection color stripe detection Color stripe detect ON 00: Low ∼ 11: High 00:OFF 10:2.0s 00:OFF 10:1.0s 00:10clk 10:20clk 01:1.0s 11:3.0s 01:0.5s 11:1.4s 01:15clk 11:30clk PSLICEL CPSON BUS_CSDETSEL AGCWID PSEWID PSEMOD Slice level for pseudo H sync Pseudo H sync Color syripe Adjustment AGC A djustment Pseudo detection detection periode periodeof H detect detection 0:OFF 0:2.3∼3.2μS(D1) 0:1.3∼2.7μS(D1) 00:20% 01:25% 1:ON 1: 2.0∼3.5μS(D1) 1: 1.0∼3.0μS(D1) 0:OFF 10:40% 11:60% 0:1.1∼1.7μS(D2) 0:0.9∼1.3μS(D2) 1:ON 1: 1.0∼1.8μS(D2) 1: 0.8∼1.4μS(D2) ASLICEL AGCHYS PALPFON PASEL AGCMOD Adjustment of histerisis time LPF for AGC AGC AGC pulse A djustment of slice level for AGC puls e for AGC pulse detection pulse & pseudo Hsync detection detection H sync detection 0:OFF 0: after AGC 0:OFF 00:60% 01:70% 00:OFF 01:0.4s 1:ON 1:befor AGC 1:ON 10:80% 11:90% 10:0.7s 11:1.0s PSLP PKLIM PATTK PAGCON AGCLPFON Peak AGC limit level Adjustment Peak AGC Atack time Sesitivity for Peak detection fsc Tra p Filter Peak AGC 00: fast∼11：slow 00：big∼11: small 0：OFF 00：105% 10：115% 0：OFF 1：ON 01：110% 11：120% 1：ON 01：1/4 11：1/8 SATTK SSLP SAGCON Adjustment Sync AGC Atack time Adjustment Sync AGC recovery time Sync AGC 00: fast∼11：slow 00: fast∼11：slow 0：OFF 1：ON CCDMOD CSLICEL CLPFON CSLICES IRTIMS CSTMOD Phase for ID1 sensitivity of CCD Field selection for CCD data slice Adjustment fixed slice level LPF for CCD CCD slice detection start bit function mode 0：OFF 0：Auto slice 00：416LSB 01：496LSB 0:±0.6μs 0：big 00：ODD 01：EVEN 1：ON 1：fixed slice level 10：296LSB 11：336LSB 1:±1.2μｓ 1：small 10：Both Field 11：Both Field ISLICEL IPHASES ILPFON ISLICES IRWIDON IEDGES LPF for ID1 Adjustment fixed slice level for ID1 Det. for amplitude Phase adjustment Adjustment the sampling pase ID1data slice data slice of ID1signal forID1det. for ID1 function mode 0：OFF 0：Auto slice 00：480LSB 01：592LSB 0:80LSB 0：Adaptive mode 0：0 1：-1 1：ON 1：fixed slice level 10：312LSB 11：368LSB 1:OFF 1：Fixed mode 2：+2 3：+1 WSLICEL WSSMOD WLPFON WSLICES WNGROFF WSTMOD LPF for WSS1 WSS data Adjustment of the slice level WSS SC Field selection for data slice slice mode for WSSdata det. Mode WSS data slice 0：OFF 0：Adaptive 00：512LSB 01：640LSB 0：sensive 00：ODD 01：EVEN 1：ON 1：Fixed mode 10：320LSB 11：384LSB 1：Slow 10：Both Field 11：Both Field INIT:00H 29H INIT:3AH 2AH INIT:DAH 2BH INIT:1AH 2CH INIT:0FH ２DH INIT:80H 2EH INIT:80H 2FH INIT:88H * : Every blank register must be set “0”. Feb./2005 18 TC90101FG D7 30H D5 CCDDLY Phase adjustment for CCD data slice 0000:min ∼ 1000:center ∼ 1111:max 1STEP = 128fh WSSDLY Phase adjustment for WSS data slice 0000:min ∼ 1000:center ∼ 1111:max 1STEP = 128fh PROG D1/D2 detection INIT:80H 33H 0：Manual 1：Auto det. MGAINSL Manual Gain set for GCA 0：OFF 1：ON Manual set 0：D1 1：D2 BUS_FBCLMOD Time constant of theInternal feed back clamping 00：Reference 10：Small 01：Large 11：Mid MGAIN Adjustment for GCA Gain D6 D4 D3 D1 ID1DLY Phase adjustment for ID1 data slice 0000:min ∼ 1000:center ∼ 1111:max 1STEP = 128fh YADFILON FILON１ 13.5M trap IIR FILTER for ADC selection 0：OFF 0:FIL1 1：ON 1:FIL2 D2 D0 INIT:88H 31H INIT:84H 32H CDECEV1[4] fsc pull in performance 0:Nornal 1:Wide FILON0 IIR FILTER ON/OFF 0:OFF 1:ON INIT:00H 34H INIT:00H 35H CGP_S Adjustment start phase of output pulse of CGP 1000：-1.185μｓ ∼ 0000：±０ ∼ 0111：+1.04μｓ 0000：Sync center + 3.7μs DET4VAL Threshold level for DET. 443 ［1000:MIN 0000:CEN 0111:MAX] CGP_W Adjustment pulse width of CGP 1000：-1.185μｓ ∼ 0000：±０ ∼ 0111：+1.04μｓ 0000：center ( 2μs) SYNC TIP CLAMP２ VDMSKCHG Clamp control 00：ON 10：AUTO１ 0 1 01：OFF 11：AUTO２ INIT:07H 36H CGPOUTM CGP OUT control BUS_DCOMTRP1 DCOMB OUT C Trap 0：OFF 1：ON BUS_YNCLV Y NOISE LIM 0:4LSB 1:8LSB BUS_BFD2 BGCTR BUS_ENPIXOFF Mute 0：ON 1：OFF BUS_CNCON C NOISE 0:OFF 1:ON INIT:00H 37H 0:auto 1:forced ON BUS_YNCCK Y NOISE INIT:00H BUS_YNCGA Y NOISE GAIN 0:×1/2 1:×1 BUS_YNCON Y NOISE 0:OFF 1:ON BUS_CKILLLV CKILL Gain 0:Center 1:+3dB BUS_CNCLV C NOISE LIM 0:4LSB 1:8LSB BUS_CNCGA C NOISE GAIN 0:×1/2 1:×1 * : Every blank register must be set “0”. Feb./2005 19 TC90101FG IIC BUS Read Data Sub D7 DET50 Field Frequency 0:60Hz 1:50Hz DET443 4.43MHz det. 0:non 1:Det. NOISE_OUT7 D6 NOSIG Signal det. 0:Signal det. 1:no signal PALDET PAL det. 0:non 1:Det. NOISE_OUT6 D5 NOVP V-Sync Sep 0:V sig det 1:no V sig SECAMDET SECAM det. 0:non 1:Det. NOISE_OUT5 D4 D3 D2 FIELD UNLOCK H/VSTD Field indication HPLL for inpit sig H-V std. det. 0:ODD 0:LOCK 0:std. 1:EVEN 1:UNLOCK 1:non-std. FSC_SEL CKILL fsc detection Killer det. 00:3.579545MHz 01:3.575611MHz 0:Color 10:3.582056MHz 11:4.433MHz 1:White&black NOISE_OUT4 NOISE_OUT3 NOISE_OUT2 S/N detection 0000_0000:Strong signal → 1111_1111:Weak signal D1 D0 progressive D1/D2 det. 0:D1 1:D2 FSCLOCK fsc lock det. 0:unlock 1:lock NOISE_OUT0 A-1 0 A-2 0 NOISE_OUT1 A-3 (MSB) H_Cont［7］ A-4 H_Cont［6］ 10000000：Min COLSTYPE Color stripe 0：TYPE2 1:TYPE3 IIR CCD[6] Start bit det. 0：NG 1：OK IIR CCD[14] H_Cont［5］ H_Cont［4］ H_Cont［3］ H_Cont［2］ information of H counter numbers for 1V periode 00000000：Typ 01111111：Max COLSDET Color stripe det. 0:non 1:det. IIR CCD[5] Color_ S_DET Psuedo Sync det. 0:non 1:det. IIR CCD[4] AGC DET AGC Pulse det. 0:non 0 1:det. IIR CCD[3] IIR CCD[2] CCD sliced data H_Cont［1］ (LSB) H_Cont［0］ A-5 0固定 IIR CCD[7] CCD CRI det. ０：under 3ck １：upper then 3ck IIR CCD[15] 0 IIR CCD[1] 0 IIR CCD[0] B-1 (LSB) IIR CCD[13] IIR CCD[12] IIR CCD[11] CCD sliced data IIR CCD[10] IIR CCD[9] IIR CCD[8] B-2 IIR CCD[23] IIR CCD[22] CCD sliced data B-3 IIR CCD[31] B-4 (MSB) IIR ID1[7] Reference sig. det. 0:NG 1:OK IIR ID1[15] IIR ID1[6] CRC code det. 0:NG 1:OK IIR ID1[14] IIR ID1[5] IIR ID1[4] WORD０(sliced data) (LSB) IIR ID1[13] IIR ID1[3] IIR ID1[2] IIR ID1[1] WORD１(sliced data) (LSB) IIR ID1[0] (MSB) IIR CCD[30] IIR CCD[21] Field information ０：ODD １：EVEN IIR CCD[29] IIR CCD[20] IIR CCD[19] IIR CCD[18] Numbers of CRI IIR CCD[17] IIR CCD[16] 0 (MSB) IIR CCD[28] IIR CCD[27] information of CCD slice level IIR CCD[26] (LSB) IIR CCD[25] IIR CCD[24] C-1 IIR ID1[12] IIR ID1[11] WORD2(sliced data) IIR ID1[10] IIR ID1[9] IIR ID1[8] C-2 IIR ID1[23] C-3 IIR ID1[31] C-4 (MSB) IIR_WSS[7] RUN-IN det. 0:NG 1:OK IIR WSS[15] IIR_WSS[6] START CODE det. 0:NG 1:OK IIR_WSS[14] IIR_WSS[5] IIR_WSS[4] IIR_WSS[3] IIR_WSS[2] WSS(sliced data) IIR_WSS[1] (LSB) IIR WSS[0] IIR ID1[30] IIR ID1[29] IIR ID1[28] IIR ID1[27] information of ID1 slice level IIR ID1[26] IIR ID1[22] IIR ID1[21] IIR ID1[20] ＣＲＣＣ(sliced data) IIR ID1[19] IIR ID1[18] IIR ID1[17] 0 IIR ID1[25] IIR ID1[16] Field information 0:ODD 1:EVEN IIR ID1[24] D-1 (LSB) IIR_WSS[13] IIR_WSS[12] IIR_WSS[11] WSS(sliced data) IIR_WSS[10] IIR_WSS[9] IIR_WSS[8] D-2 IIR_WSS[23] Bi phase det. 0:NG 1:OK IIR_WSS[22] Field information 0:ODD 1:EVEN IIR_WSS[21] IIR_WSS[20] IIR_WSS[19] IIR_WSS[18] information of WSS slice level IIR_WSS[17] (MSB) IIR WSS[16] D-3 (MSB) SEL_RDATA 00h 01h 10h 11h IIC read data sequence ＡＢＣＤ ＢＣＡＤ ＣＡＢＤ ＤＡＢＣ (LSB) Feb./2005 20 TC90101FG ●Additional information about IIC registers. BUS address Function Contents 00H：D7-D6 Input signal selection. An input signal is chosen. 00H：D5-D2 Select TVM. The TV-system is fixed forcibly. It uses when it is worked in the manual. 00H：D1-D0 Color system detection Setup Color system detection mode. mode. Manual / Europeian / South American / Full auto detection. 01H：D7 Setup for YCS. 3-lineComb or BPF is chosen. 0: 3-line-Comb 1: B.P.F 01H：D5-D4 Select clock Setup for an output clock frequency. Select “601：13.5MHz” or “656：27MHz”. 01H：D3 Select OUTPUT FORMAT Setup for an output format (601or656). 01H：D2 Select OUTBITS Setup for an output bits range (8bit or 10bit). Digital-Output Control Each digital output terminals are controlled. 01H：D1 0：Active 1：OPEN (Because it becomes Hi Impedance, coexistence with other IC's is possible.） 01H：D0 ADC-Power Control The control of the power supply for ADC. 0：The power supply of ADC is turned off. 1：Normal (It usually uses by this setup.) 02H：D7-D6 Set V Enhance Gain Gain (off, 1/8, 1/4 and 1/2) is set up. 02H：D5-D4 Set V Enhance nonSetup the characteristic of V-enhance gain for non- correlation liner point. Component. Choose it from 4 point 02H：D3-D2 Set V Enhance coring Choose Coring(No response level). 02H：D1 Set “f0” of sharpness Set f0 of Sharpness. It works with f0 of Noise-canceler as well together. 02H：D0 Select Pre-Enhance Pre-Enhance makes it control the part Edgy of Sharpness. 03H：D7-D4 Adjustment Sharpness Control the Gain of Sharpness. Gain. 1011：-1/4 ∼ 1111：OFF ∼ 0111：8/16 1000, 1001 and 1010 can't be used. 03H：D3-D2 Set Sharpness-coring Choose Coring(No response level). -Level. Set the Feed-Back CLAMP. 03H：D1 Set the Feed-Back 0: Auto. It becomes a diode clamp when TC90101FG detects a CLAMP non-signal. 1：Feed-Back Clamp is active. Select Internal-Feed-Back or External-Feed-Back. 03H：D0 Change the Feed-Back 0: External mode (Pin74, 75 outputs clamp signal). CLAMP 1: Internal mode (Pin74, 75 : Open). The time-constant for internal feedback clamp is set via BUS_FBCLMOD at sub address 32 hex. 04H：D7-D6 Set Noise canceler Set the Gain of NOISE-CANCEL. Gain 04H：D5 Set LTI f0 Set the f0 of LTI. 04H：D4 Set CTI f0 Set the f0 of CTI. 04H：D3-D0 Cb & Cr delay adjust. Fine tune for delay of Cb & Cr. Step is 37[ns] between -296ns∼259ns. But step is 74[ns] at YCbCr input mode. 05H：D7-D6 LTI Gain adjustment It set the Gain of LTI. 05H：D5-D4 LTI coring Level It set the Coring(No response level) of LTI. Use after you confirm a picture. 05H：D3-D2 CTI Gain adjustment It set the Gain of CTI. 05H：D1-D0 CTI coring Level It set the Coring(No response level) of CTI. Feb./2005 21 TC90101FG BUS address Function 06H：D7-D0 Contrast Adjustment 07H：D7-D0 08H：D7-D4 08H：D3-D0 09H：D7-D4 09H：D3-D0 0AH：D7-D1 0AH：D0 0BH：D7-D2 0BH：D1 0BH：D0 0CH：D7-D4 0CH：D3 0CH：D2-D0 0EH：D7-D5 OEH：D4-D2 0EH：D1-D0 0FH：D7-D4 OFH：D3-D0 10H：D7-D4 Contents It set the Contrast. (Reference value: [01000000]) Variability is ×0.5∼×2.4. （When use big value and inputs big amplitude signal, It takes place over range of internal circuit.) Brightness Adjustment It set the Brightness. Variability is -128LSB ∼ +128LSB. Cr Gain Adjustment It set Gain of Cr. (Refrence value:[0000]) Variability is ×0.5∼×1.4. （When use big value and inputs big amplitude signal, It takes place over range of internal circuit.) Cb Gain Adjustment It set Gain of Cb. (Refrence value:[0000]) Variability is ×0.5∼×1.4. （When use big value and inputs big amplitude signal, It takes place over range of internal circuit.) Cr Output OFFSET adjust. Fine tune for offset of the Cr at output stage. Cb Output OFFSET adjust. Fine tune for offset of the Cr at output stage. HUE adjustment HUE adjustment at the NTSC input mode. Variable is -45°-+43.6 °. Filter for feed-back Setup BPF for feed-back-clamp. [1]:ON [0]:OFF Normaly It must be set [1]. HUE Bias adjustment Fine tune HUE-Bias at the NTSC input mode. Variable is 0°∼+45°. C Trap for dirital clamp. It is C-Trap for Digital-clamp of Y. [1]:ON [0]:OFF Use [1] at the digital-clamp-mode. V-mask of digital clamp Setup of the digital clamping at V-Blk period. [1]: Clamp OFF [0]: Clamp ON. It usually uses on [1]. Offset adjustment for Offset adjustment for Y signal at Analog-input. clamp Y-input Use with 0[mV] when you use with digita-clamp. C-trap of D-COMB Setup C-trap for Y at Digital-COMB-block. [1]: ON [0]: OFF. This setup can reduce Cross-color and beat. Take off Filter select Setup Take-off-Filter. Take-off-Filter is put in front of Decoder. 000：OFF、001： BPF、010∼111：TOF（TOF1∼TOF6） When BPF is set up, it can't get the effect of TOF. Phase adjustment of Digital-clamp is put by input-Y-signal Digital-clamp for Y. Adjustment of the phase of Digital-clamp-pulse for Y. Reference value:[011].The variable is about 0.3[μs] step. Adjustment of clampAdjustment of the width of Digital-clamp-pulse for Y. width for Y-digital Reference value: [011].Variable is about 0.3[μs] step. -clamp Time constant of YIt can select ON/OFF of Digital-clamp-Y. And adjustment of Digital-clamp time constant of Digital-clamp-Y. Offset adjustment for Adjust the offset of the Cr at input by YCbCr signal. Cr-Input Use with 0[mv] at the time of Digital-clamp. Variable is -31[mV] ∼ +27[mV]. Offset adjustment for Adjust the offset of the Cb at input by YCbCr signal. Cb-Input Use [0000] at the Digital-clamp mode. Variable is -31[mV] ∼ +27[mV]. Adjustment of input Adjust the clamp-phase of Cb/Cr at YCbCr signals. clamp phase for Cb/Cr It usually uses on BUS:[0000]. 22 Feb./2005 TC90101FG BUS address Function 10H：D3-D0 Adjustment of input clamp width for Cb/Cr 11H：D7-D5 Adjustment of digital -clamp-Pulse-phase for C/Cb/Cr 11H：D4-D2 Adjustment of digital Clamp-pulse-width for C/Cb/Cr 11H：D1-D0 Time constant of CDigital-clamp 12H：D7 Setup killer function 12H：D6-D4 12H：D3-D0 13H：D7-D6 13H：D5 Level of color-killer ACC reference Level Reduce H-dot Setup Comb+ 13H：D4 13H：D3 13H：D2-D0 1 LINE DOT 443NTSC Comb control SECAM Y trap setup Contents Adjust the clamp pulse width of Cb/Cr at YCbCr signals. It usually uses on BUS:[0000]. Adjust the digital-clamp-phase for C/Cb/Cr. (S-Video/YCbCr inputs.) It usually uses on BUS:[011]. Fine tune the digital-clamp-pulse-width for C/Cb/Cr. (S-Video/YCbCr inputs.) It usually uses on BUS:[011]. This is adjustment of time constant of Digital-clamp-C. It can set ON/OFF and three-kinds. Setup color killer function. [0]: Active (normal) [1]: Killer become OFF always. Level of color-killer-ON is set up. [000]:killer sensitivity is max.[111]: killer sensitivity is minimum. Reference-level of ACC(auto color control) is set up. Level by ACC becomes smallest when it is set up in 000. Setup of dot-reducer at the horizontal edge. When it is turned on, dot of the part of H is reduced. It has an effect as below for PAL system. When the horizontal lines of the front and the rear have color and edge element,and the horizontal line of center has no color, it drops Y signal level for calculated result. Therefore it occurs dots of black in spite of white and gray picture.When COMB+ is on, it can decrease this noise. It usually uses ON, when PAL signal. Setup of 1LINE-DOT-improver in the YCS block. [1]:ON [0]:OFF It can reduce the dot,when only 1-line has a color signal. Comb control in 443NTSC is changed. [1]:2H comb [0]:1H comb Cross-color will reduce when 2H-Comb is selected. Setup Y-trap performance for SECAM. TC90101FG SECAM Trap Frequency Response 10 0 TC 90103FG S E C A M T ra p F re q ue n c y R e sp o n se -10 B B B B B B B B U U U U U U U U S S S S S S S S = = = = = = = = 0 1 2 3 4 5 6 7 Gain [ dB ] -20 -30 -40 -50 -60 0 1 2 3 4 5 F re q u e n c y [ MHz ] 6 7 8 9 10 Feb./2005 23 TC90101FG BUS address Function 14H：D7-D6 Selection for external-sync 14H：D5 14H：D4-D3 Sync Separation level Sync-tip-clamp-mode for CVBS 14H：D2 Setup for V-sepa 14H：D1 V-sepa limit 14H：D0 Setup of Half-H-killer 15H：D7-D2 Horizontal phase reference Picture MUTE Cb and Cr MUTE Time constant 1 for HPLL (Phase difference:big) Loop Gain 1 for HPLL (Phase difference:big) Time constant 2 for HPLL (Phase difference:middle) 15H：D1 15H：D0 16H：D7-D5 16H：D4-D0 17H：D7-D5 17H：D4-D0 Loop Gain 2 for HPLL (Phase difference:middle) 18H：D7-D5 Time constant 3 for HPLL (Phase difference:small) 18H：D4-D0 Loop Gain 3 for HPLL (Phase difference:small) Contents It select the input signal of Composite-SYNC-in of Pin-33. [00]: OFF(Internal) Pin33 must be connect to GND. [01]: External composite Sync mode (polarity: High) [10]: External composite Sync mode (polarity: Low) [11]: External V-Sync mode (polarity: High) Level of Sync-sepa is set up. Initial value is [0]:30%. It set the control of clamp. [00]: Sync tip clamp ON [01]: Sync tip clamp OFF [10]: AUTO1(Sync-tip-clamping becomes activity, When it detect non-signal or pedestal has a big difference. [11]: AUTO2 (Sync-tip-clamping becomes activity, When it detect non-signal. Setup for V-sepa 0: Type 1 1: Type 2 (Type 2 is more effective than Type1.) Limit of V-sepa is set up. V-sepa becomes easy, when it is set up in 1/16. But,Usually use with 0(1/8）. It count Half-H at the V period. [0]: OFF (Initial value) [1]: ON (It is effective for top-curl problem of non-standard signal.(VCR trick mode etc･･) Reference-Horizontal-counter of internal is set up. This register is reference timing for all of internal function. Usually, it uses with 0[µs]. [0]: Normal [1]: Picture Mute ON [0]: Normal [1]: Color signal Mute ON It is time-constant of PLL. It becomes active when the phase difference has big value. Reference value: [010] It is Loop-Gain of PLL. It becomes active when the phase difference has big value. Reference value: [01110] It is time-constant of PLL. It becomes active when the phase difference has middle value. Reference value: [100] It is Loop-Gain of PLL. It becomes active when the phase difference has middle value. Reference value: [01101] It is time-constant of PLL. It becomes active when the phase difference has small value. (it means under stable.) Reference value: [101] It is Loop-Gain of PLL. It becomes active when the phase difference has small value. Reference value: [00110] Feb./2005 24 TC90101FG BUS address Function 19H：D7-D4 Threshold level at the phase difference big to middle 19H：D3-D0 Threshold level at the phase difference middle to big 1AH：D7-D5 Start phase for noise detection 1AH：D4-D2 Width for noise detection 1AH：D1-D0 1BH：D7-D4 1BH：D2 1BH：D1-D0 1CH：D7-D4 1CH：D3-D0 1DH：D7-D4 1DH：D3-D0 1EH：D7-D4 1EH：D3 1EH：D2-D0 1FH：D7-D4 1FH：D3-D0 20H：D7-D4 Contents Threshold level that Phase-diffrent changes from Big to middle is set up. Recommendation value: [0100] Threshold level that Phase-diffrent changes from middle to Big is set up. Recommendation value: [01000] The horizontal-start-phase of the detection of Noise is set up. “Point of 5.3µs from sync” is center. The horizontal-width of the detection of Noise is set up. The amount of noise-detection changes by Width. When width is widened, detection sensitivity rises. The number of horizontal It is the numbers of lines which Noise is detected in. lines which Noise is The number of line's can be set up from 1H to 4H. detected in Start line for Noise The vertical start line of the Noise detection is set up. detection 60Hz：7-lines as 0H.It is set up in 1 line unit. 50Hz：4-lines as 0H.It is set up in 1 line unit. HPLL-Lock-Gain The fsc Lock-Gain is set up. Usually used with 1/2. fsc lock period Lock-period of fsc is set up. Search-time becomes long, when it is set up ∼6V. But, it is easy to pull in. Horizontal phase for The position of EAV&SAV is set up. digital format Usually, it uses with initial-value:0[us]. Vertical phase for V-phase of VD is set up when "H/V OUT through". digital format Variability of V-phase is the 1H unit. Start phase of The horizontal start phase of the picture-processing-period is Horizontal signal set up. The picture-processing is set up with COMBKILL processing (1EH D2∼D0). Width of Horizontal The horizontal width of the picture-processing-period is signal processing set up. The start reference is a horizontal start phase. Make adjustment after start-setup. Start phase of vertical The vertical start line of the picture-processing-period is set signal processing up.It becomes MUTE to the setup from the vertical start line. The setup of the vertical AUTO or MANUAL is selected. picture processing MANUAL : It becomes the value that it is set up with 1EH(D7-D4). AUTO: 60Hz= from 10th line / 50Hz= from 23th line Picture-processing is started from each line. Setup of COMBKILL period The period of COMBKILL is set up. This period doesn't do picture processing. AUTO:60Hz=1∼22H、50Hz=1∼23H But, it is a mask period to 21H by the Y/C input of 60Hz and the YCbCr input of 60Hz. Start phase of The start phase of H-BLANK-PULSE is set up. Horizontal BLK Usually, it uses with initial-value:0[us]. Width of Horizontal BLK The width of H-BLANK-PULSE is set up. Usually, it uses with initial-value:0[us]. Start phase of burst gate The start phase of BURST-GATE-PULSE is set up. Feb./2005 25 TC90101FG BUS address Function 20H：D3-D1 Set line of VBI data slice 20H：D0 21H：D7-D5 21H：D4-D3 21H：D1 21H：D0 22H：D7 22H：D6 22H：D5 22H：D4 16LSB limit Start phase of V at THR-V Delay adjustment of HD-OUT BSRY filter BSRC filter HD-OUT of polarity VD-OUT of polarity Polatity of Field H/V-OUT through 22H：D3 22H：D2 Polarity of CKOUT V.BLK processing 22H：D1 23H：D6 Y output Amplitude Cb/Cr phase 23H：D5-D4 50/60Hz VD cotrol 23H：D3 23H：D2-D0 24H：D7-D5 Field Det on non-signal Ext VD phase Horizontal phase for field detection V count Contents The line of VBI-data-slice is set up. Usually used with center. When it uses at the outside synchronism, it uses for the adjustment, when the phase of the outside VD-pulse and the input signal are shifted. VBI and Macrovision detection line move at the same time, too. It limit less than 16LSB at the Digital output. Use by ON, when you use with 601/656 output. The phase of VD is set up. Bus:111 can't be set up. When Thru of V, Set the delay of HD-Pulse.The variability is 32W∼44W (1W=27MHz). It usually uses on ON. It usually uses on ON. The polarity of the HD output is chosen. The polarity of the VD output is chosen. The polarity of the Field output is chosen. H/V-OUT in 601 output is chosen. 656：H/V-pulse equal to 656. Through：H/V-pulse equal to the input signal. The polarity of the CKOUT is chosen. Processing of V-Blanking is chosen. It usually uses on O:NORMAL. The period of blanking in NORMAL are Y=16LSB (8bit) and C=128LSB (8bit). Through is for the test. The amplitude of the Digital output is changed. It usually uses on O:1.71875. “1” is for the test. The output of Cb and Cr can change. 0：Digital Format Normal 1：change VD output is controlled. (It becomes effective when it is set up in 601 output.） 00：Free run 01：It is fixed on 50 or 60 on non-signal. Frequency to fix depends on TVM2. 10：When Video-system is MANUAL control, a setup is always fixed on TVM2. 11：It is always fixed on TVM2 at MANUAL. It is fixed on TVM2 at non-signals. The detection of Field is set up on non-signals. It is A phase in the external-VD-input. Variable is -7.94[μs] ∼ 5.96[μs]. It is H-phase of Field-detection. It is the phase margin. Use with Bus:100. It is the allowable range of V-counter. It can set margin of "V-Sep phase and H-counter". It usually uses on 0. It is the specifications of reset of V-counter. When ON, It can reduce field-miss-detection. It usually uses on ON. 26 24H：D4 24H：D3 V count reset Feb./2005 TC90101FG BUS address Function 24H：D2 AFC leak control 24H：D1-D0 The order of read Data 25H：D7 Data insert of H 25H：D6 Data insert of V 25H：D5 25H：D4-D0 26H：D7-D4 26H：D3-D0 27H：D7-D0 28H：D7-6 Data insert for 601 Line number for insert Data. Line number for insert Data in field blank. For DID code For DID code Histerisis for color stripe detection Histerisis for color stripe detection Mask period for color stripe detection Sensitivity for color stripe detection Color stripe detection AGC detection periode Pulse width of Pseudo sync Pseudo H sync detection Slice level for pseudo H sync LPF for AGC pulse & pseudo H sync detection Route change of AGC pulse & pseudo H sync AGC Pulse detection Slice level for AGC pulse Histerisis time for AGC pulse detection Peak AGC ON/OFF Limit level of Peak AGC fsc Trap Filter Peak AGC attack time 28H：D5-D4 28H：D3-D2 28H：D1-D0 29H：D7 29H：D5 29H：D4 29H：D2 29H：D1-D0 2AH：D7 2AH：D6 2AH：D4 2AH：D3-D2 2AH：D1-D0 2BH：D7 2BH：D6-D5 2BH：D4 2BH：D3-D2 Contents It is Leak-control in the AFC circuit. It usually uses on OFF. It can change order that Read-data. 00: ABCD A：Detection、B：CCD、C：ID1、D：WSS BUS：01=BCAD、BUS：10=CABD、BUS：11=DABC It insert Read-data to the H period of the output. Data is inserted after EAV at 656. Data is inserted same place with 656 at 601. It insert Read-data to the V period of the output. Data is inserted after EAV at 656. Data is inserted same place with 656 at 601. Data can insert on either of Y or CbCr at 601 output. Data cannot insert both line. Set line which Read-Data insert. It can set each 1-line for 1bit. Set line(in Field-Blanking) which Read-Data insert. It can set each 1-line for 1bit. This setup is DID code. This setup is DID code. It is Histerisis of the Color-stripe-detection. If takes the long time, detection-time increase. But, miss-detection decreases. It is Histerisis of the Color stripe detection-OFF. If takes the long time, detection-OFF-time increase. But, miss-detection decreases. It is the detection period of color-stripe. It is judged in more than the setup period. It is the detection sensitivity of color-stripe. It is judged in more than the setup. It set ON/OFF of color stripe detection. It is the Pulse width of the AGC detection. It is the Pulse width of the pseudo-sync pulse. It set ON/OFF of pseudo H sync detection. It set slice level of pseudo H sync. It set ON/OFF of LPF for AGC pulse & pseudo H sync detection It is Route of “AGC pulse & pseudo H sync”. Switching of Route is before and after the AGC circuit. It set ON/OFF of AGC Pulse detection. It set slice level of AGC pulse. It set histerisis-time of AGC pulse detection. It It It It set set set set ON/OFF of peak AGC. Limit level of Peak AGC. ON/OFF of fsc Trap Filter. Peak AGC attack time. Feb./2005 27 TC90101FG BUS address Function 2BH：D1-D0 An integral coefficient of Peak AGC detection 2CH：D7 Sync AGC 2CH：D3-D2 Sync AGC attack time 2CH：D1-D0 Peak/Sync AGC recovery time 2DH：D7 LPF for CCD 2DH：D6 CCD slice function mode 2DH：D5 2DH：D3 2DH：D2 2DH：D1-D0 2EH：D7 2EH：D6 2EH：D5-D4 2EH：D3 2EH：D2 CCD slice level Phase width of ID1 detection CCD Start bit detection Select CCD field LPF for ID1 ID1 data slice function ID1 slice level Detection for amplitude of ID1 signal Phase of ID1 detection Contents It is the integral-coefficient of Peak AGC detection. It set ON/OFF of Sync AGC. It set Sync AGC attack time. It set recovery time of Peak AGC and Sync AGC. It set ON/OFF of LPF for CCD. It set mode of CCD slice function. Level changes by the input amplitude,when Auto mode. It set CCD slice level. It is effective when 2DH:D6 is set a fix. It set phase width of ID1 detection. It is the detection sensitivity of the start bit of CCD. It set field that detect CCD. It set ON/OFF of LPF(Input stage of ID1-detection circuit) It set ID1 data slice function. When Auto slice,slice level changes by the input amplitude. It set ID1 slice level. It is effective when 2EH:D6. It is the reference amplitude of the detection. When it is off, Amplitude detection becomes AUTO. It is the reference phase of the ID1 detection. When Adaptive , it can search in the range of ±1.1μs at the D1. It is the phase of the detection of ID1. "1" changes in 0.12µs unit at D1, 0.28µs unit at D2. It usually uses on "0". It set ON/OFF of LPF(Input stage of WSS-detection circuit) It set WSS data slice function. When Adaptive slice,slice level changes by the input amplitude. It set WSS slice level. It is effective when 2FH:D6. It set detection sensitivity of start-code of WSS. It set field that detect WSS. It is Delay-adjust of LINE-timing for the CCD detection. It uses when detection start deviates in weak electric density It is Delay-adjust of LINE-timing for the ID1 detection. It uses when detection start deviates in weak electric density It is Delay-adjust of LINE-timing for the WSS detection. It uses when detection start deviates in weak electric density It set sensitivity of Pulled-in of fsc. High: Sensitivity is up. It set ON/OFF of 13.5MHz Trap at ADC. It usually uses on "ON". Characteristic selecting of C-filter of SECAM. It set ON/OFF of C-filter of SECAM. A color beat can be reduced. It usually uses on "Always ON" in SECAM. 28 2EH：D1-D0 Sampling phase of ID1 2FH：D7 2FH：D6 LPF for WSS1 WSS data slice function 2FH：D5-D4 2FH：D2 2FH：D1-D0 30H：D7-D4 30H：D3-D0 31H：D7-D4 31H：D3 31H：D2 31H：D1 31H：D0 WSS slice level WSS SC Det mode Select WSS field Adjust line timing of CCD Adjust line timing of ID1 Adjust line timing of WSS fsc pull in 13.5MHz trap IIR Filter selection IIR Filter ON/OFF Feb./2005 TC90101FG BUS address Function 32H：D7 D1/D2 Det 32H：D6 32H：D5-D4 33H：D7 D1/D2 Manual set Internal feed-backclamp Manual Gain AGC Contents It is the distinction of D1/D2. It is effective 32H:D6 when manual set. Internal control is fixed with D1orD2. When clamp set internal, it can set time constant. 33H：D6-D0 34H：D7-D4 34H：D3-D0 35H：D7-D4 35H：D1-D0 36H：D7 36H：D6 36H：D0 37H：D7 37H：D6 37H：D5 37H：D4 37H：D3 37H：D2 37H：D1 37H：D0 It set ON/OFF of Peak-AGC Gain. It is effective when it is ON. It gives priority to Manual when this bit is ON. Therefore, it can't get the effect of AGC. Manual Gain It is effective when 33H(D7). Gain becomes a fix. CGP start phase It set start phase of CGP(Output of Terminal-73). Width of CGP It set width of CGP(Output of Terminal-73). Threshold for DET.443 It set threshold for DET.443. It is easy to distinguish when a MAX side is chosen. Sync-tip-clamp-mode for It is the control of limit-clamp to add under the input signal Y-input at Y input. Four kinds of switchings are possible. ON:Always,limitter-clamp to add to Low-level of input is ON. OFF:Always,limitter-clamp to add to Low-level of input is off. AUTO1：It is ON in the no-signal and 'When Pedestal-Level deviated greatly.' AUTO2：It is ON on no-signal. CGP OUT control It set action of CGP. AUTO: It is output only when an input signal is set 11(D7 and D6 on 00H). Forced on: It is output to all the input. C Trap of DCOMB It is ON, when you want reduce Cross-color and beat. Mute The Blanking period becomes mute. Y Noise It set f0 of Y-Noise-Canceler. It usually uses on "0". Y Noise Lim It set Limitter of Y-Noise-Canceler. Y Noise Gain It set Gain of Y-Noise-Canceler. Y Noise canceler It set ON/OFF of Y-Noise-Canceler. CKILL Gain It set the condition of CKILL Gain. When it is set up in +6dB, Level which color disappears to grows big. It uses ”0” when weak electric density. C Noise lim It set Limitter of C-Noise-Canceler. C Noise Gain It set Gain of C-Noise-Canceler. C Noise canceler It set ON/OFF of C-Noise-Canceler. Feb./2005 29 TC90101FG MAXIMUN RATINGS（Vss=0V, Ta=25℃） Each item of the maximum rating shows the marginal value of this product. Since a product is sometimes damaged when rating is exceeded also one item or for a moment again, be sure to use it within rating. ＣＨＡＲＡＣＴＥＲＩＳＴＩＣ SYNBOL ＲＡＴＩＮＧ UNIT Power Supply Voltage1（1.5V System） VDD１ -0.3 ∼ VSS+2.0 Ｖ Power Supply Voltage2（2.5V System） VDD２ -0.3 ∼ VSS+3.5 Ｖ Power Supply Voltage3（3.3V System） VDD３ -0.3 ∼ VSS+3.9 Ｖ VIN -0.3 ∼ VDDIO +0.3 Ｖ Input Voltage SDA/SCL(Note1) -0.3 ∼ VSS + 5.5 Ｖ A IN -0.3 ∼ VDDAD+0.3 Ｖ Potential difference between power supply terminals VDG1（Note2） 0.3 Ｖ （1.5V System） Potential difference between power supply terminals VDG2（Note2） 0.3 Ｖ （2.5V System） Potential difference between power supply terminals VDG3（Note2） 0.3 Ｖ （3.3V System） Potential difference between power supply terminals VDG4（Note2） 0.3 Ｖ （1.5V System＞2.5V System） Potential difference between power supply terminals VDG5（Note2） 0.3 Ｖ （2.5V System ＞3.3V System） Power Dissipation ＰＤ(Note3) 1900 ｍW Storage Temperature Ｔｓｔｇ -40 ∼ 125 ℃ (Note1) SDA，SCL： 5V tolerance. (Note2) 1.5V system power supply terminal is made into the same voltage, 2.5V system power supply terminal is made into the same voltage, and 3.3V system power supply terminal is made into the same voltage. The maximum potential difference should not exceed rating for all power supply terminals then. (Note3) Derated above Ta=25℃ in the proportion of 19mW/℃. Operation conditions（Vss=0V） Cannot guarantee operation of TC90A92F, when the recommendation power supply voltage range (1.40V-1.65V, 2.3V-2.7V, 3.0V-3.6V) is exceeded. Once, when it returns from the over range, it differs from a front condition. ＣＨＡＲＡＣＴＥＲＩＳＴＩＣ Supply Voltage for digital block Supply Voltage for I/O block Supply Voltage for XO block Supply Voltage for PLL block Supply Voltage for Analog block Ambient operating temperature Terminal No. 15,32,39,54,66 23,49,60 6 2 82,89,95,97 SYNBOL DVDD1-5 VDDIO1-3 VDDXO VDDPLL VDDAD/VDDDA Ｔopr MIN 1.40 3.0 3.0 2.3 2.3 -10 TYP 1.5 3.3 3.3 2.5 2.5 − MAX 1.65 3.6 3.6 2.7 2.7 75 UNIT V V V V V ℃ Feb./2005 30 TC90101FG The condition of power (VDD=3.3V, 2.5V, 1.5V) rising and falling (1)Power Supply rising These contents are the important items which influence the reliability guarantee of the IC. It is necessary to satisfy the following condition. (1) P ow er rising condition 3.3V (pow er range : 3.0 ∼ 3.6V ) m ore than 3.0V *note1 V D D =3.3V m ore than 0.4V 2.5V (pow er range : 2.3 ∼ 2.7V ) m ore than 2.3V * note1 V D D =2.5V m ore than 0.4V 1.5V (pow er range : 1.4 ∼ 1.65V ) *note1 V D D =1.5V m ore than 0.4V It needs to rise less than 40m s from starting to rise the pow er of 2.5V . (reset release) T erm inal 30 ： R E S E T A fter all pow ers rising, it is necessary to keep resetting m ore than 0.5m s. A nd it m ust not keep the reset conditions m ore than one m inute. IIC -B us IN Term inal31 ： S D A Term inal 32 ： S C L A fter reset release, it is necessary to be m ore than 100ns for IIC B U S control starting. m ore than 1.4V *note1 S uch the pow er term inal are em bedded the protective diode . It m ust not send a penetration electric current. C ondition: P ow er level of 3.3V line ≧ P ow er level of 2.5V line ≧ P ow er level of 1.5V line W hen the pow er level of 1.5V line is m ore than 0.4V , 3.3V line and 2.5V line m ust reach the level of pow er m ore than 0.4V . A nd w hen the pow er level of 2.5V line is m ore than 0.4V, 3.3V line m ust reach the level of pow er m ore than 0.4V . 3.3V pow er term inal 2.5V pow er term inal 1.5V pow er term inal (2) P ow er falling condition It is necessary to fall the pow er of 1.5V line before 3.3V line and 2.5V line are fallen, and to fall the pow er of 2.5V line before 3.3V line is fallen. It m ust not send a penetration electric current too . Feb./2005 31 TC90101FG ELECTRICAL CHARACTERRISTICS (1) DC CHARACTERRISTICS （Ta=25℃,VDD1=1.50±0.1V,VDD2=2.50±0.2V,VDD3=3.30±0.3V) ITEM Power Supply Current Terminal No. 15,32,39,54,66 Symbol IDD1 Min. Typ. Max. 30 80 15 VDD3x0.8 45 105 30 70 135 60 VDD3 Unit mA 2,82,89,95,97 IDD2 mA 6,23,49,60 IDD3 mA Input Voltage 10,11,12,13,14,16,17, 18,20,21,22,24,25,28, 29,30,31,50,51 26,27,33 10,11,12,13,14,16,17, 18,20,21,22,24,25,28, 29,30,31,50,51 26,27,33 VIH V Note Sum total current of 1.5V system power supply terminal NTSC:Y/C IN, Color Bar Signal Sum total current of 2.5V system power supply terminal NTSC:Y/C IN, Color Bar Signal Sum total current of 3.3V system power supply terminal Changes with the loads of I/O. I/O input terminal of 3.3V system I/O input terminal of 5.0V system I/O input terminal of 3.3V system I/O input terminal of 5.0V system 5.0V Pull up use I/O input terminal of 5.0V system 3.3V Pull up use 3 I/O input terminal of 3.3V system I/O input terminal of 5.0V system I/O input terminal of 3.3V system I/O input terminal of 5.0V system I/O output terminal of 3.3V system Load of 4mA outflow VIL VSS VDD3x0.2 V VDD3x0.2 0.3 Input Current 10,11,12,13,14,16,17, 18,20,21,22,24,25,28, 29,30,31,50,51 26,27,33 10,11,12,13,14,16,17, 18,20,21,22,24,25,28, 29,30,31,50,51 26,27,33 IIH -10 10 μA IIL -10 10 μA Output Voltage 35,36,37,38,40,41,43, 44,46,47,48,52,53,55, 56,58,59,61,62,64,65, 67,68,70,71,72,73,74, 75 35,36,37,38,40,41,43, 44,46,47,48,52,53,55, 56,58,59,61,62,64,65, 67,68,70,71,72,73,74, 75 26 VOH VDD3-0.6 VDD3 V VOL VSS 0.4 V I/O output terminal of 3.3V system Load of 4mA inflow I/O output terminal of 5.0V system Load of 4mA inflow Notice : The specifications of VIL is difference in the Pull-up voltage. When it specially uses for 3.3V with pull-up, do the design which is less than 0.3V securely. Feb./2005 32 TC90101FG (2) AC CHARACTERRISTICS （Ta=25℃,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V) ITEM Symbol Min. Typ. Max. Unit Note AD input level for Y AD input level for C ADC differentiation error ADC integration error Output impedance VYIN VCIN DLEa ILEa Zy 160 0.7 0.5 ±4 ±4 200 0.8 0.8 240 Vp-p White 100% Signal Vp-p Cb/Cr input LSB LSB Ω (3) PLL CHARACTERRISTICS （Ta=25℃,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V) ITEM Symbol Min. Typ. Max. Unit Note Drawing-in frequency range ΔfckN -50 Operation input amplitude Vck 0.3 0.5 50 2.0 kHz Clock Amplitude:0.5Vp-p Vp-p Standard clock frequency input Feb./2005 33 TC90101FG Application ② 1.5V 3.3V 1.5V 0.01μ 0.01μ 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 0.01μ 18k 18k YCLAMPP1 VSSIO2 COUT6 VDDIO2 YCLAMPP2 UVFLAG VBI READY ODDEVEN 0.01μ LPF 0.01μ NP 0.47μ ① LPF 0.01μ NP 0.47μ 2.5V 0.01μ 0.01μ LPF 0.01μ 0.01μ ① NP 0.47μ 2.5V 0.01μ 0.01μ 0.01μ LPF ① NP 0.47μ 2.5V 0.01μ 2.5V 1.5k 4p 1.2k 0.01μ 0.01μ 0.01μ 22μ 0.1μ 0.1μ BUF 0.1μ BUF BUF 0.1μ BUF BUF 7 6 BIASYAD 7 7 VRTYAD 7 8 YIN 7 9 VSSYAD 8 0 VRMYAD 8 1 CVBS IN 8 2 VDDYAD 8 3 VRBYAD 8 4 BIASCAD 8 5 VRTCAD 8 6 CIN 8 7 VSSCAD 8 8 Cb IN 8 9 VDDCAD 9 0 VRBCAD 9 1 BIASRAD 9 2 VRTRAD 9 3 VSSRAD 9 4 Cr IN 9 5 VDDRAD 9 6 VRBRAD 9 7 VDDDA 9 8 DAOUT 9 9 VSSDA 100 1.5 3.3 1.5 TESTM6 TESTM5 5 0 VDDIO1 4 9 CKOUT 4 8 DVSS4 COUT7 HDOUT COUT9 COUT5 COUT4 COUT2 DVDD4 COUT1 COUT8 VDOUT DVSS5 DVDD5 COUT3 COUT0 CGP ② 0.01μ 3.3V 3.3 2.5 YOUT0 4 7 YOUT1 4 6 VSSIO1 4 5 YOUT2 4 4 YOUT3 4 3 DVSS3 4 2 YOUT4 4 1 YOUT5 4 0 DVDD3 3 9 YOUT6 3 8 YOUT7 3 7 YOUT8 3 6 YOUT9 3 5 DVSS2 3 4 ② 0.01μ 1.5V ② TC90101FG Top view 1.5 ② LPF 2.5 1.5 CSYNC IN 2.5 33 0.01μ DVDD2 3 2 TESTM4 3 1 TESTM3 3 0 TESTM2 2 9 TESTM1 2 8 SCL 2 7 1.5V 2.5 2.5 VREFDA VCOFIL VDDPLL VSSPLL PLLIN BIASDA 3.3 TDIO8 TDIO6 TDIO5 TDIO9 DVDD1 XOOUT TDIO7 TDIO4 VDDXO XOIN VSSXO 1.5 TDIO2 TDIO3 DVSS1 TDIO1 3.3 VDDIO3 BUSSEL RESET TDIO0 TDCLK SDA 2 6 4.7k 4.7k 5V可 ①ｱﾅﾛｸﾞGN ①Analog D GND ②ﾃﾞｼﾞﾀﾙGN D ②Digital GND 両GN D間はﾋﾞｰｽﾞｺｱ等で 分離する事 1 ① 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 0.1μ 1500p 270k 0.01μ 42M 0.01μ 1.5V 1.5μ 0.01μ 22μ 2.5V ① 22p 10μ 18p ② 3.3V ② 1000p 3.3V ② Feb./2005 34 TC90101FG ● PACKAGE OUTLINE LQFP100-P-1414-0.50C UNIT:mm Weight：0.65g（center） Feb./2005 35 TC90101FG About soloderability, following conditions were confirmed. ● Solderability (1) Use of Sn-63Pb solder Bath ・solder bath temperature=230℃ ・dipping time=5seconds ・the number of times=once ・use of R-type flex (2)Use of Sn-3.0Ag-0.5Cu solder Bath ・solder bath temperature=245℃ ・dipping time=5seconds ・the number of time=once ・use of R-type flex RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 030619EBA • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. Feb./2005 36