TC9329AFAG

TC9329AFAG/AFCG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9329AFAG, TC9329AFCG Portable Audio DTS Controller (DTS-21) The TC9329AFAG/AFCG is a single-chip DTS microcontroller for portable audio incorporating a 230-MHz prescaler, PLL, and LCD driver. In addition to a 20-bit IF counter, 6-bit A/D converter, serial interface, and buzzer function, the device supports an interrupt function, 8-bit timer/counter, and 8-bit pulse counter. The LCD driver features built-in 1/4 duty, 1/2 bias and a 3-V voltage boosting circuit, implementing stable LCD. The power supply voltage ranges from 0.9 to 1.8 V. Because of its low current consumption (CPU: 80 µA (max)), the device is suitable for use in digital tuning systems in portable equipment such as headphone stereos. TC9329AFAG TC9329AFCG Features CMOS DTS microcontroller LSI with built-in 230 MHz prescaler, PLL, and LCD driver • Operating voltage: VDD = 0.9~1.8 V (typ.: 1.5 V) • Current dissipation: CPU in operation: IDD = 40 µA typ. PLL in operation: IDD = 6 mA typ. (VHF mode) • Operating temperature range: Ta = −10~60°C Weight • Program memory (ROM): 16 bits × 4096 steps LQFP64-P-1010-0.50E : 0.32 g ( typ.) • Data memory (RAM): 4 bits × 256 words TQFP64-P-1010-0.50C : 0.26 g ( typ.) • Instruction execution time: With crystal oscillator: 40 µs With CR oscillator: 6 µs (at 1 MHz, VDD = 1.1~1.8 V) • Crystal oscillator frequency: 75 kHz • Stack level: 8 • General-purpose IF counter: 20 bit (CMOS input supported) • A/D converter: 6 bits × 4-channels • LCD driver: 1/4 duty, 1/2 bias, 72 segments (max) • I/O port: CMOS I/O ports: 12 N-channel open drain I/O ports: 16 (max) Output-only port: 1 Input-only ports: 3 (max) • Timer/counter: 8 bits (as timer clock: INTR1/INTR2; instruction cycle: 1 kHz selectable) • Pulse counter: 8-bit up/down counter (input via INTR2 pin) Buzzer: 8 settings, 0.625~3 kHz; 4 built-in modes consisting of continuous, single-shot, 10 Hz intermittent, or 10 Hz intermittent at 1 Hz intervals. • • Interrupts: 2 external, 2 internal (serial interface, 8-bit timer) Package: QFP-64 (0.5-mm/0.65-mm pitch, 1.4-mm thickness) Note: Handle with care to prevent devices from deteriorating due to electrostatic discharge. • 1 2006-03-02 TC9329AFAG/AFCG Pin Assignment (top view) HOLD (INTR2/PCTRin) IFin1 (INTR1) P5-2 (ADin3) P5-1 (ADin2) P5-0 (ADin1) P3-3 (SCK) IFin2 (IN2) P3-2 (SO) P3-1 (SI) DO (OT) OSCin 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P5-3 (ADin4) P2-0 P2-1 P2-2 P2-3 (PSC) RESET XOUT XIN GND VDB C1 C2 VEE C3 C4 VLCD 49 50 51 TEST 32 31 30 GND P3-0 VDD Vreg A/D SIO PLL MUTE P4-3 P4-2 P4-1 P4-0 (BUZR) VDD P1-3 P1-2 P1-1 P1-0 P9-3 (S18) P9-2 (S17) P9-1 (S16) P9-0 (S15) P8-3 (S14) P8-2 (S13) N-channel open drain I/O ports (8) CMOS I/O ports (4) CMOS I/O ports (4) 52 53 54 55 Oscillation circuit SVFP64/TQFP64 (0.5 mm pitch) CMOS I/O ports (4) 29 28 27 26 25 24 23 22 Doubler circuit N-channel open drain/ CMOS I/O ports (8) 21 20 19 18 LCD driver (1/4 duty, 1/2 bias: 72 segments max) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 56 57 58 59 60 61 62 63 64 S1 (OT5) S2 (OT6) S3 (OT7) S4 (OT8) COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) S5 (OT9) S6 (OT10) S7 (OT11) S8 (OT12) S9 (OT13) S10 (OT14) P8-0 (S11) P8-1 (S12) 2 2006-03-02 TC9329AFAG/AFCG Block Diagram Peripheral XOUT XIN CRosc CPU P1-3 Port1 P1-0 G-Reg. R/W Buf. PSC P2-3 (PSC) Port2 P2-0 X’tal OSC Vreg Vreg (1.5 V) DO2 (OT) Phase Comp. RAM (4 × 256 word) ALU P4-3 Port4 P4-0 (BUZR) OSCin PLL BUZR IFin1 (INTR1) IFin2 (IN2) IF Counter Up/Down Counter Data Reg (16 bit) CRosc CR OSC Timer ROM Interrupt Cont. INTR2 (16 × 4096 Step) Instruction Decoder MUTE MUTE P8-3 (S18) Port9 P9-0 (S15) P8-3 (S14) Port8 Serial Interface LCD Driver Port3 Program Counter Reset VLCD Stack Reg. (8 Level) Vreg VDB VDD P8-0 (S11) P3-3 (SCK) P3-2 (SO) P3-1 (SI) P3-0 VLCD HOLD (INTR2) TEST RESET VDD GND VDB A/D Conv. Doubler C1 C2 P5-3 (ADin4) P5-2 (ADin3) P5-1 (ADin2) P5-0 (ADin1) LCD Driver/Output Port VLCD Port5 VEE (1.5 V) VEE C3 Doubler C4 VLCD COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4) VLCD S1 (OT5) S2 (OT6) S6 (OT10) S7 (OT11) S8 (OT12) S9 (OT13) 3 S10 (OT14) 2006-03-02 TC9329AFAG/AFCG Description of Pin Function Pin No. Symbol Pin Name Function and Operation Outputs common signals to LCD panels. Through a matrix with pins S1 to S18, a maximum of 72 segments can be displayed. Three levels, VLCD, VEE (1/2 VLCD ), and GND, are output at 62.5 Hz every 2 ms. VEE is output after system reset and CLOCK STOP are released, and a common signal is output after the DISP OFF bit is set to “0”. These pins can be programmed as output ports (Note 1). Segment signal output terminals for LCD panel. Together with COM1 to COM4, a matrix is formed that can display a maximum of 72 segments. VEE is output after system reset and CLOCK STOP are released, and a common signal is output after the DISP OFF bit is set to “0”. All pins from S1 to S10 can be programmed as output ports (Note 1), and all pins from S11 to S18 as I/O ports, in units of pins. When the pins function as output ports, VLCD pin potential and GND potential are output to them. When the pins function as I/O ports, drain output is N-ch open. Because power is supplied from VLCD for the I/O ports, up to VLCD voltage (3 V) can be applied. P8-0/S13~ 15~22 P9-3/S18 LCD segment An instruction increments the data ports output/ I/O port 8, 9 (OT1 to OT14) by 1 every time data are accessed. Therefore the ports can be used for external memory address signals, facilitating data access. Note: After system reset, the output port pins are set to LCD output, the I/O port pins to I/O port input. Remarks 1 COM1/OT1 VLCD VEE 2 COM2/OT2 LCD common output/Output port 3 COM3/OT3 4 COM4/OT4 VLCD S1/OT5~ 5~14 S10/OT14 LCD segment output/Output port VLCD VDD Input instruction The input and output of these 4-bit I/O ports can be programmed in 1-bit units. These pins can be programmed to be pulled up or down. Thus, they can be used as key input pins. By altering the input of I/O ports set to input, the CLOCK STOP mode or the WAIT mode can be released, and the MUTE bit of the MUTE pin can be set to “1”. VDD VDD 23~26 P1-0~P1-3 I/O port 1 RIN1 VDD Note 1: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore disconnect the voltage boosting capacitor and connect the VLCD pin to the VDD pin. 4 2006-03-02 TC9329AFAG/AFCG Pin No. Symbol Pin Name Function and Operation Remarks 50~52 P2-0~P2-2 I/O port 2 VLCD The input and output of these 4-bit I/O ports can be programmed in 1-bit units. The P2-3 pin is also used as a PLL prescaler PSC signal output pin. A PLL can be configured using an external prescaler. In such a case, set the pin to I/O port output. VDD Input instruction 53 P2-3/PSC I/O port 2 /Prescaler /PSC output 4-bit I/O ports, allowing input and output to be programmed in 1-bit units. The I/O ports are N-ch open drain. Up to 3.6 V can be input. Even at low voltage, N-ch high output current (2 mA typ.) can be obtained. These pins also function as serial interface circuit (SIO) input/output pins. P3-0 I/O port 3 There are two types of serial interface circuit: SIO1 allows 4 or 8-bit input/output and SIO2 allows 26-bit serial data input. SIO1 inputs data of SI pin serially with the edge of the clock of SCK pin, and outputs it to SO pin. Internal (SCK = 37.5 kHz), external, or rising/falling shift can be selected as the clock (SCK) for serial operation. The SO pin can be switched to serial input (SI), facilitating LSI control and communication between controllers. Setting “1” in the SIO2 bit sets the SCK pin to the SIO2 clock input and the SI/SO pin to SIO2 data input. A synchronization circuit is built-in for SIO2. When SIO interrupts are enabled, an interrupt is generated after SIO execution or by SIO2 operating clock input and the program jumps to address 4. All SIO inputs use built-in Schmitt circuits. SIO and all controls are programmable. 4-bit I/O ports, allowing input and output to be programmed in 1-bit units. 28 P4-0/BUZR I/O port 4 /Buzzer output The P4-0 pin is also used for buzzer output. The buzzer output can select 8 kinds of 0.625 to 3-kHz frequencies with 4 modes: continuous output, single-shot output, 10 Hz intermittent output, and 10 Hz intermittent at 1 Hz intervals output. SIO, buzzer, and all associated controls can be programmed. P3-1/SI /Serial data input Input instruction (P3-0) 42~45 P3-2/SO /Serial data output P3-3/SCK /Serial clock I/O Input instruction + SIOon (P3-1~P3-3) VDD 29~31 P4-1~P4-3 I/O port 4 Input instruction 5 2006-03-02 TC9329AFAG/AFCG Pin No. Symbol Pin Name Function and Operation 4-bit I/O ports, allowing input and output to be programmed in 1-bit units. Pins P5-0 to P5-3 can also be used for analog input to the built-in 6 bit, 4-channel AD converter. The conversion time of the built-in AD converter using the successive I/O port 5 comparison method is 280 µs. The /AD analog voltage necessary pin can be programmed to input AD analog input in 1-bit units. Up to the doubled voltage VDB (VDD × 2) can be input as the AD input voltage. I/O ports are N-ch open drain output. Up to the VDB v oltage can be applied to the AD input pins. The AD converter and all associated controls are performed via sortware. 1-bit output port, normally used for muting control signal output. This pin can set the internal MUTE bit to “1” according to change in the input of I/O port 1 and HOLD . The MUTE bit output logic can be changed. Remarks 46~49 P5-0/ADin1~ P5-3/ADin4 To AD converter VDD Input instruction VDD 32 MUTE Muting output port The internal CR oscillator clock can be output depending on the contents of the test port. Input pin used for controlling TEST mode. Test mode control input “H” (high) level indicates TEST mode, while “L” (low) indicates normal operation. The pin is normally used at low level or in NC (no connection) state. (A pull-down resistor is built in.) RIN2 VDD 33 TEST 6 2006-03-02 TC9329AFAG/AFCG Pin No. Symbol Pin Name Function and Operation Input pin for request/release hold mode. Normally, this pin is used to input radio mode selection signals or battery detection signals. Hold mode includes CLOCK STOP mode (stops crystal oscillation) and WAIT mode (halts CPU). Setting is implemented with the CKSTP instruction or the WAIT instruction. To request Clock Stop mode, either L-level detection on the HOLD pin or forced execution can be programmed. The mode is released by H-level detection on the HOLD pin or input change, respectively. Executing the CKSTP instruction stops the clock generator and the CPU, resulting in entry to memory backup state. In memory backup state, current dissipation becomes low (1 µA or less) and the display output/CMOS output ports automatically become L level and N-ch open drain output is set toOff. Regardless of this input state, Wait mode is executed in order to lower power dissipation. Either operation of the crystal oscillator only or CPU suspension can be programmed. For operation of the crystal oscillator only, all displays are at L level and other pins are in hold state. For CPU suspension, the CPU stops and all others retain their states. Wait mode is released by changing HOLD input. The P34 pin is also used for external interrupt input. When interrupts are enabled and a 13.3 to 26.7-µA pulse or longer is input to the pin, interrupt INTR1/2 is generated and the program jumps to address 1/2. Input logic or rising/falling edge can be selected for each input interrupt. The internal 8-bit timer clock input can be selected as input to the pins. When the count value reaches the specified value, an interrupt is generated (address 4). The pin is also used for input of an 8-bit pulse counter. Input rising/falling or upcount/downcount can be selected for the counter. Remarks VDD Hold mode control input HOLD 34 /INTR2 /PCTRin /External interrupt input /Plus count input 7 2006-03-02 TC9329AFAG/AFCG Pin No. Symbol Pin Name Function and Operation IF signal input pin for the IF counter to count the IF signals of the FM and AM bands and to detect the automatic stop position. The input frequency is between 0.3 to 12 MHz. A built-in input amp. and C coupling allow operation at low-level input. The IF counter is a 20-bit counter with optional gate times of 1, 4, 16 and 64 ms. 20 bits of data can be readily stored in memory. In Manual mode, gate On/Off or CR oscillator clock frequency count can be performed using an instruction. The input pin can be programmed for use as an input port (IN port). In this case, the pins are CMOS input. They can count input clocks using the IF counter. IFin1 also functions as an external interrupt input pin. When interrupts are enabled and a 13.3 to 26.7-µA pulse or longer is input to IFin1, an interrupt is generated and the program jumps to address 1. Input logic or rising/falling edge can be selected for the input interrupt. The internal 8-bit timer clock input can be selected as input to the pin. When the count value reaches the specified value, an interrupt is generated (address 4). Note: When a pin is set to IF input, the input is at high impedance in PLL Off mode or if the pins are not used for input. Pins to which power is applied. Normally, VDD = 0.9~1.8 V is applied. 27, 39 VDD In backup state (at execution of the CKSTP instruction), current dissipation drops (1 µA or less) and the power supply voltage can be reduced to 0.75 V. Note: To operate the power on reset, the power supply should start up in 10~100 ms. VDD Remarks 35 36 IFin1/INTR1 IFin2/IN2 IF signal 1 input /External interrupt input RfIN2 VDD IF signal 2 input /Input port Power-supply pins 37, 57 GND GND 8 2006-03-02 TC9329AFAG/AFCG Pin No. Symbol Pin Name Function and Operation For FM input, mode can be switched between 1/2 + Pulse Swallow VHF and FM mode. For AM input, mode can be switched between Pulse Swallow (HF) and Direct Dividing (LF) mode. Normally, local oscillation output (Voltage-Controlled Oscillator: VCO output) of 80 to 230 MHz is input in VHF mode; 60 to 130 MHz in FM mode; 1 to 30 MHz in HF mode; 0.5 to 8 MHz in LF mode. A PLL can be configured using an external prescaler. In such a case, set the pin to LF, and connect the prescaler divider output to the OSCin input pin and the PSC input to the P2-3 (PSC) output pin. With an input amp incorporated, capacitive-coupling, small-amplitude operation is supported. Note: The input is at high impedance in PLL Off mode. PLL phase comparator output pins. Tristate output. When the program counter divider output is higher than the reference frequency, H level is output; when lower, L level; and when they match, high impedance. For the phase comparator power supply, a 1.5-V constant voltage supply (Vreg pin) is used. Even if the power supply voltage drops, a stable PLL can be configured. The DO/OT pin can be programmed to high impedance or as an output port (OT). Note: For tristate output, the H-level output uses a constant voltage supply. When H-level output current is required, Toshiba recommend using an external power supply. Phase comparator constant voltage supply. When the phase comparator output is tristate output, a constant voltage supply of 1.5 V (typ.) is output to the pin. For this output, connect a stabilizing capacitor (0.47 µF typ.). Constant voltage On/Off can be programmed. Because half the voltage potential can be switched to AD converter A/D input, it can be used to detect how much battery remains. At PLL operation, the constant voltage is used for H level phase comparator output. Thus, when H level output current is required, Toshiba recommend using an external power supply. Externally apply 1.8 to 3.6 V to the pin. Input pin for system reset signals. 54 RESET Reset input RESET takes place at low level; at high level, the program starts from address “0”. Remarks RfIN1 VDD 38 OSCin local oscillation signal input Vreg 40 DO/OT Phase comparator output/output port 41 Vreg Phase comparator constant voltage supply Vreg 9 2006-03-02 TC9329AFAG/AFCG Pin No. Symbol Pin Name Function and Operation Crystal oscillator pins. 55 XOUT A reference 75 kHz crystal resonator is connected to the XIN and XOUT pins. The oscillator stops oscillating during CKSTP instruction execution. Crystal oscillator pin The VXT pin is the power supply for the crystal oscillator. A stabilizing capacitor (0.47 µF typ.) is connected. Usually, the clock of a crystal oscillator is used for the clock for peripheral equipment. Through programming, the built-in VCO can be changed to CPU and CPU only operation can be accelerated. Voltage doubler boosting output pins. The VDB pin doubles the VDD pin voltage using the voltage doubler boosting capacitor between C1 and C2. The doubled voltage is used for the AD converter and constant voltage circuit (Vreg, VEE) power supply. The VEE pin supplies a constant voltage of 1.5 V from the VDB voltage. The voltage is doubled (to 3 V) using the voltage doubler boosting capacitor between C3 and C4. The doubled voltage is then supplied to the VLCD pin. The VEE potential and the VLCD potential are used to drive the LCD. Connect a stabilizing capacitor between the VDB pin and GND (0.1 µF, 10 µF typ.), and between the VLCD pin and GND (0.1 µF typ.). Connect a voltage doubler boosting capacitor (0.1 µF typ.) between C1 and C2, and between C3 and C4. (Note) VLCD XOUT ROUT RfXT VDD XIN Remarks 56 XIN 58 59 60 61 62 63 VDB C1 C2 VEE C3 C4 Voltage doubler boosting output pins 64 VLCD Note: When the LCD pin is set as an output port, the “H” level output is the doubled voltage VLCD. Therefore disconnect the voltage boosting capacitor and connect the VLCD pin to the VDD pin. 10 2006-03-02 TC9329AFAG/AFCG Description of Operations ○ CPU The CPU consists of a program counter, a stack register, an ALU, a program memory, a data memory, a G-register, a data register, a DAL address register, a carry F/F, a judgment circuit, and an interruption circuit. 1. Program Counter (PC) The program counter consists of a 14-bit binary up-counter and addresses the program memory (ROM). The counter is cleared when the system is reset and the programs start from the 0 address. Under normal conditions, the counter is increased in increments of one whenever an instruction is executed, but the address specified in the instruction operand is loaded when a JUMP instruction or CALL instruction is executed. Also, when an instruction that is equipped with the skip function (AIS, SLTI, TMT, RNS instructions, etc.) is executed, and the result of this includes a skip condition, the program counter is increased in increments of two and the subsequent instruction is skipped. Furthermore, if interruption is received, the vector address corresponding to each interruption is loaded. Note: Addresses 0000H-0FFFH are reserved for the program memory. For this reason, access to addresses outside this range is prohibited. Contens of Program Counter (PC) PC13 PC12 PC11 PC10 JUMP ADDR1 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Instruction Operand of instruction (ADDR1) JUMP ADDR2 Power on reset RESET by reset pin DAL (DA) (DAL bit = 1) RN, RNS, RNI At the time of an interruption reception Power on reset RESET by reset pin 0 0 0 Operand of instruction (ADDR2) Operand of instruction (ADDR3) DAL address register (DA) Contents of general register (r) 0 0 0 0 0 Contents of stack register Vector address of each interruption 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Priority 1 2 3 4 Interruption Factor INTR1 pin INTR2 pin Serial inter face Timer counter Vector Address 0001H 0002H 0003H 0004H 2. Stack Register A register consisting of 8 × 14 bits which stores the contents of the program counter +1 (the return address) when a sub-routine call instruction is executed. The contents of the stack register are loaded into the program counter when the return instruction (RN, RNS, RNI instruction) is executed. There are eight stack levels available and nesting occurs with both levels. 11 2006-03-02 TC9329AFAG/AFCG 3. ALU ALU is equipped with binary 4-bit parallel add/subtract functions, logical operation, comparison and multiple bit judgment functions. This CPU is not equipped with an accumulator, and all operations are handled directly within the data memory. 4. Program Memory (ROM) The program memory consists of 16 bits × 4096 steps and is used for storing programs. The usable address range consists of 4096 steps between address 0000H ~ 0FFFH. The program memory is divided into 4096 separate steps and consists of page 0 ~ 3. The JUMP instruction and CALL instruction can be freely used throughout all 4096 steps. In case of setting DAL bit (it arranges on I/O map) “0” (DAL ADDR3, (r) command), the program memory address 0000H ~ 03FFH (page 0) are used as data area and setting DAL bit “1” (DAL (DA) command), the program memory address 0000H to 0FFFH (page 0 ~ 3) are used as data area. The 16 bit contents of this can be loaded into the data register by executing the DAL instruction. Note: An address outside of the program lop must be set when establishing a data area within the program memory. ROM 16 bit 0000H 0000H JUMP address at initialization Page 0 (1 k step) 0400H Page 1 JUMP instruction specification area CALL instruction specification area 0002H 0003H 0004H Interruption vector address *1 0001H INTR1 INTR2 Serial interface 8 bit timer 0800H Page 2 0C00H Page 3 0FFFH *2 *1: *2: DAL bit = DAL access area at setting “0” DAL bit = DAL access area at setting “1” Note: DAL bit is arranged on I/O map. DAL instruction area 12 2006-03-02 TC9329AFAG/AFCG 5. Data Memory (RAM) The data memory consists of 4 bit × 256 words and is used for storing data. These 256 words are expressed in row addresses (4 bits) and column addresses (4 bits). 192 words (row address = address 004H ~ 00FH) within the data memory are addressed indirectly by the G-register. Owing to this, it is necessary to specify the row address with the G-register before the data in this area can be processed. The address 00H ~ 0FH within the data memory are known as general registers, and these can be used simply by specifying the relevant column address (4 bit). These sixteen general registers can be used for operations and transfers with the data memory, and may also be used as normal data memories. Note: The column address (4 bit) that specifies the general register is the register number of the general register. Note: All row address (addresses 0H ~ FH) can be specified indirectly with the G-register. Note: The data memory is 256 words and 2 bits of the 6-bit higher ranks of G-register row address are used “0” (00H ~ 0FH address). Note: By using LD and ST instructionss, it can be addressed directly in 256 words (row address = 00H ~ 0FH) in a data memory. COLMUN ADDRESS: DC 0 12 3 4 5 67 89ABCDEF General register (one from among addresses 00H ~ 0fH) ROW ADDRESS: DR * 0 1 2 3 4 5 6 7 8 9 A B C D E F Indirect specification of row addresses (4H ~ FH) with the G-register * The indirect specification of row address = 0H ~ FH is also possible LD and ST instructions allow low addresses (0H ~ FH) to be directly 13 2006-03-02 TC9329AFAG/AFCG 6. G-Register (G-REG) The G-register is a 4 bits register used for addressing the row addresses (DR = 4H ~ FH addresses) of the data memory’s 192 words. The contents of this register are validated when the MVGD instruction or MVGS instruction are executed, and not affected through the execution of any other instructions. This register is used as one of the ports, and the contents are set when the OUT1 instruction from among the I/O instructions is executed. The 6-bit contents can be directly set by execution of STIG instruction. (→Refer to the Register Port section.) 7. Data Register (DATA REG) The data register consists of 1 16 bits and stores 16 bits of optional address data. This register is used as one of the ports, and the contents are loaded into the data memory in units of 4 bits when an IN1 instruction from among the I/O instructions is executed. ( Refer to the Register Port section.) Moreover, this register supports writing from the data memory and is used for evacuation/return processing of the data at the time of interruption. 8. DAL Address Register (DA) The data register consists of 1 × 14 bits. If a DAL instruction is executed when the DAL bit is set to “1”, 16 bits of the data of the free addresses in the program memory specified by this DAL address register are loaded. By the setting (DATA) → DA bit to “1”, the contents of data register (DATA REG) can be transmitted to DAL address register (DA). This register and a control bit are treated as a port, and are accessed by IN3/OUT3 instruction of an input-and-output instruction. (→ Refer to section in Register port item) 9. Carry F/F (Ca Flag) This is set when either Carry or Borrow are issued in the result of calculation instruction execution and is reset if neither of these are issued. The contents of carry F/F can only be amended through the execution addition, subtraction, CLT, CLTC instructions and are not affected by the execution of any other instruction. The carry F/F can be accessed by the IN1/OUT1 instruction of an input-and-output instruction. For this reason, an input-and-output command performs the evacuation and the return at the time of interruption between data memories. (→ Refer to the Register Port section.) 10. Judgment Circuit (J) This circuit judges the skip conditions when an instruction equipped with the skip function is executed. The program counter is increased in increments of two when the skip conditions are satisfied, and the subsequent instruction is skipped. There are 15 instructions equipped with a wide variety of skip functions available. (→ Refer to the items marked with a “*” symbol in the Table Instruction Functions and Operational Instructions) 11. Interruption Circuit An interruption circuit branches to each vector address by the demand from circumference hardware, and performs each interruption processing. (→Refer to the interruption function section.) 14 2006-03-02 TC9329AFAG/AFCG 12. Instruction Set Table A total of 57 instruction sets are available, and all of these are single-word instructions. These instructions are expressed with 6-bit instruction codes. High order 2 bit Low order 4 bit 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 0 1 2 3 4 5 6 7 8 9 A B C D E AI AIC SI SIB ORIM ANIM XORIM MVIM AD AC SU SB ORR ANDR XORR 00 0 M, I M, I M, I M, I M, I M, I M, I M, I r, M r, M ST r, M r, M r, M r, M r, M CLT CLTC MVGD r, M r, M r, M M*, r LD r, M* JUMP ADDR1 TMTR TMFR SEQ SNE 01 1 r, M r, M r, M r, M 10 2 SLTI SGEI SEQI SNEI TMTN TMT TMFN TMF IN1 IN2 IN3 OUT1 OUT2 OUT3 DAL SHRC RORC STIG CAL ADDR2 1111 F MVSR M1, M2 MVGS M, r SKP, SKPN RN, RNS WAIT CKSTP XCH DI, EI, RNI NOOP M P 11 3 M, I M, I M, I M, I M, N M, N M, N M, N M, C M, C M, C M, C M, C M, C ADDR3, r M M I* 15 2006-03-02 TC9329AFAG/AFCG 13. Table of Instruction Functions and Operational Instructions (Description of the symbols used in the table) M : Data memory address. Generally one of the addresses from among addresses 00H to 3FH in the data memory. M* : Data memory address (256 words) One of the addresses from among addresses 000H to 0FFH in the data memory. (Effective only at the time of ST and LD instruction execution) r : General register One of the addresses from among addresses 00H to 00FH in the data memory. PC : Program Counter (14 bits) STACK : Stack register (14 bits) G : G-register (6 bits) DATA : Data register (16 bits) I : Immediate data (4 bits) I* : Immediate data (6 bits, effective only at the time of STIG instruction execution) N : Bit position (4 bits) : ALL “0” C : Port code No. (4 bits) CN : Port code No. (4 bits) RN : General register No. (4 bits) ADDR1 : Program memory address (14 bits) ADDR2 : Program memory address within page 0 to 3 (12 bits) ADDR3 : High order 6 bits of the program memory address within page 0. DA : DAL address register (14 bits, effective only DAL instruction at the time of DAL bits is set to “1”) Ca : Carry CY : Carry flag P : Wait condition b : Borrow IN1~IN3 : The ports used during the execution of instructions IN1 to IN3 OUT1~OUT3 : The ports used during the execution of instructions OUT1 to OUT3 () : Contents of the register or data memory []C : Contents of the port indicating code No. C (4 bits) [] : Contents of the data memory indicating the contents of the register or data memory []P : Contents of the program memory (16 bits) IC : Instruction code (6 bits) * : Commands equipped with the skip function DC : Data memory column address (4 bits) DR : Data memory row address (2 bits) DR* : Data memory row address (4 bits, effective only at the time of ST and LD instruction execution) (M) b0~(M) b3 : Bits data of the contents of a data memory (1 bit) 16 2006-03-02 TC9329AFAG/AFCG Instruc -tion Group AI Mnemonic Skip Function Machine Language (16 bits) Function Description Operation Description IC (6 bits) 000000 000001 001000 A (2 bits) DR DR DR B (4 bits) DC DC DC C (4 bits) I I RN M, I M, I r, M Addition Instructions Add immediate data to memory M ← (M) + I AIC AD Add immediate data M ← (M) + I + ca to memory with carry Add memory to general register Add memory to general register with carry Subtract immediate data from memory Subtract immediate data from memory with borrow Subtract memory from general register Subtract memory from general register with borrow r ← (r) + (M) r ← (r) + (M) + ca M ← (M) − I M ← (M) − I − b r ← (r) − (M) r ← (r) − (M) − b AC r, M 001001 DR DC RN Subtraction Instructions SI M, I 000010 DR DC I SIB M, I 000011 DR DC I SU r, M 001010 DR DC RN SB r, M 001011 DR DC RN SLTI M, I * Skip if memory is less than immediate data Skip if (M) < I 110000 DR DC I SGEI M, I * Skip if memory is greater than or equal Skip if (M) > I = to immediate data Skip if memory is equal to immediate data Skip if (M) = I 110001 DR DC I SEQI M, I * 110010 DR DC I Comparison Instructions SNEI M, I * Skip if memory is not equal to immediate Skip if (M) ≠ I data Skip if general register is equal to memory Skip if general register is not equal to memory Skip if (r) = (M) 110011 DR DC I SEQ r, M * 010010 DR DC RN SNE r, M * Skip if (r) ≠ (M) 010011 DR DC RN CLT r, M Set carry flag if general register is (CY) ← 1 if (r) < (M) or less than memory, or (CY) ← 0 if (r) > (M) = reset if not Set carry flag if general register is less than memory with carry or reset if not (CY) ← 1 if (r) < (M) + (ca) or (CY) ← 0 if (r) > (M) + (Ca) = 011100 DR DC RN CLTC r, M 011101 DR DC RN 17 2006-03-02 TC9329AFAG/AFCG Instruc -tion Group LD ST Mnemonic Skip Function Machine Language (16 bits) Function Description Operation Description IC (6 bits) 0101 0110 001111 000111 A (2 bits) DR* (4 bits) DR* (4 bits) DR DR B (4 bits) DC DC DC1 DC C (4 bits) RN RN DC2 I r, M* M*, r Load memory to general register Store memory to general register r ← (M*) M* ← (r) MVSR M1, M2 Move memory to (DR, DC1) ← (DR, DC2) memory in same row Move immediate data M←I to memory Move memory to destination memory [(G), (r)] ← (M) referring to G-register and general register Move source memory referring to G-register and (M) ← [(G), (r)] general register to memory (Note) Move immediate data G ← I* to G-register Input IN1 port data to M ← [IN1] C memory Output contents of memory to OUT1 port [OUT1] C ← (M) Transfer Instructions MVIM M, I MVGD r, M 011110 DR DC RN MVGS M, r 011111 DR DC RN STIG IN1 I* M, C 111111 111000 DR I* DC 0010 CN OUT1 M, C 111011 DR DC CN I/O Instructions IN2 M, C Input IN2 port data to M ← [IN2] C memory Output contents of memory to OUT2 port [OUT2] C ← (M) 111001 DR DC CN OUT2 M, C 111100 DR DC CN IN3 M, C Input IN3 port data to M ← [IN3] C memory Output contents of memory to OUT3 port Logical OR of general register and memory Logical AND of general register and memory Logical OR of memory and immediate data Logical AND of memory and immediate data [OUT3] C ← (M) 111010 DR DC CN OUT3 M, C 111101 DR DC CN ORR r, M r ← (r) ∨ (M) 001100 DR DC RN Logical Poeration Instructions ANDR r, M r ← (r) ∧ (M) 001101 DR DC RN ORIM M, I M ← (M) ∨ I 000100 DR DC I ANIM M, I M ← (M) ∧ I 000101 DR DC I XORIM M, I Logical exclusive OR of memory and M ← (M) ∀ I immediate data Logical exclusive OR of general register r ← (r) ∀ (M) and memory 000110 DR DC I XORR r, M 001110 DR DC RN Note: The execution time for the MVGS instruction is two machine cycles. 18 2006-03-02 TC9329AFAG/AFCG Instruc -tion Group Mnemonic Skip Function Machine Language (16 bits) Function Description Operation Description IC (6 bits) A (2 bits) B (4 bits) C (4 bits) TMTR r, M * Test general register bits by memory bits, then skip if all bits specified are true Test general register bits by memory bits, then skip if all bits specified are false Test memory bits, then skip if all bits specified are true Skip if r [N (M)] = all “1” 010000 DR DC RN TMFR r, M * Skip if r [N (M)] = all “0” 010001 DR DC RN Bit Judgement Instruction TMT M, N * Skip if M (N) = all “1” 110101 DR DC N TMF M, N * Test memory bits, then not skip if all bits Skip if M (N) = all “0” specified are false Test memory bits, then not skip if all bits Skip if M (N) = not all “1” specified are true Test memory bits, then not skip if all bits Skip if M (N) = not all “0” specified are false Skip if carry flag is true Skip if carry flag is false Call subroutine Return to main routine Return to main routine and skip unconditionally Skip if (CY) = 1 Skip if (CY) = 0 STACK ← (PC) + 1 and PC ← ADDR2 PC ← (STACK) PC ← (STACK) and skip 110111 DR DC N TMTN M, N * 110100 DR DC N TMFN M, N * 110110 DR DC N SKP SKPN CAL ADDR2 * * 111111 111111 1011 111111 00 01 ⎯ ⎯ 0011 0011 ADDR2 (12 bits) 10 SUB = Routne Instructions RN ⎯ ⎯ 0011 RNS 111111 11 0011 JUMP Instructions JUMP ADDR1 Jump to address specified PC ← ADDR1 10 ADDR1 (14 bits) DI Reset IMF Set IMF (Note) IMF ← 0 (Note) IMF ← 1 111111 111111 111111 00 01 11 ⎯ ⎯ ⎯ 0111 0111 0111 Intruption Instruction EI RNI Return to main PC ← (STACK) routine and set IMF (Note) IMF ← 1 Note: The IMF bit is an interruption master permission flag and is arranged on I/O map. (→ Refer to the interruption function section.) 19 2006-03-02 TC9329AFAG/AFCG Instruc -tion Group Mnemonic Skip Function Function Description Shift memory bits to right direction with carry Rotate memory bits to right direction with carry Exchange memory bits mutually Operation Description 0 → (M) b3 → (M) b2 → (M) b1 → (M) b0→ (CY) (M) b3 → (M) b2 → (M) b1→ (M) b0 → (CY) (M) b3 ↔ (M) b0, (M) b2 ↔ (M) b1 Machine Language (16 bits) IC (6 bits) 111111 A (2 bits) DR B (4 bits) DC C (4 bits) 0000 SHRC M RORC M 111111 DR DC 0001 XCH M 111111 DR DC 0110 Other Instructions DAL ADDR3, r IF DAL bit = 0 then load program in page 0 to DATA register IF DAL bit = 1 then DATA ← [ADDR3 + (r)] p load program in page 0 memory referring to DAL address register to DATA register (Note) At P = “0” H, the condition is CPU waiting (soft wait mode) At P = “1” H, expect for clock generator, all function is waiting (hard wait mode) Clock generator stop No operation 111110 ADDR3 (6 bits) RN WAIT P Wait at condition P 111111 P ⎯ 0100 CKSTP NOOP Stop clock generator to MODE condition 111111 111111 ⎯ ⎯ ⎯ ⎯ 0101 1111 ⎯ Note: The four low order bits of the program memory’s 10-bit address specified with the DAL instruction are addressed indirectly with the contents of the general registerer. Note: The excution time for the DALinstruction is two machine cycles. Note: DALbitsand DAL address register (DA) are arrenged on the I/O map. (→ Refer to the Register Port section) Note: When “1” is set to DAL bit and the DAL instruction is executed, all the operand part becomes invalid and the reference addresses are used for the DAL address register. 20 2006-03-02 TC9329AFAG/AFCG I/O Map (IN1 (M, C), IN2 (M, C), IN3 (M, C), OUT1 (M, C), OUT2 (M, C), OUT3 (M, C)) I/O φL1 OUT1 Code Y1 HF PW0 1 P0 2 P4 P5 P6 P7 edge P1 P2 P16 AD SEL0 AD SEL1 AD SEL2 STA -0 -1 I/O port 3 -2 -3 F0 F1 IF data 2 F2 F3 AD4 AD5 BUSY 0 -0 -1 I/O port 3 -2 -3 PW1 Y2 Y4 Y8 FM PD0 K1 PD2 PD3 -0 -1 I/O port 2 -2 -3 BUSY MANUAL OVER Y1 Y2 φL2 OUT2 Y4 Y8 Y1 Y2 I/O port 1 φL3 OUT3 Y4 Y8 Y1 Y2 IF monitor 0 AD0 AD1 A/D data AD2 AD3 -0 -1 I/O port 2 -2 -3 φK1 IN1 Y4 Y8 Y1 Y2 A/D data φK2 IN2 Y4 Y8 Y1 Y2 I/O port 1 φK3 IN3 Y4 Y8 Power control 0 I/O port 1 pull-down Programmable counter 1 A/D control IF data 1 Programmable counter 2 Serial interface control 1 SCK - INV SCK - I/O SIO-ON -0 -1 I/O port 4 -2 -3 F4 F5 IF data 3 F6 F7 Serial interface monitor 0 -0 -1 I/O port 4 -2 -3 Programmable counter 3 3 P8 4 P12 5 R0 6 R1 R2 P13 Reference select P14 P15 Programmable counter Serial interface control 2 P11 STA P9 P10 SO - I/ O 8/ 4 bit SIO Select -0 -1 I/O port 5 -2 -3 F8 F9 IF data 4 F10 F11 BUSY COUNT SIO F/F -0 -1 I/O port 5 -2 -3 Programmable counter 4 SO0 Serial interface output data 1 SO1 SO2 SO3 -0 -1 Serial interface input data 1 F14 F15 SI0 SI1 SI2 SI3 -0 -1 -2 -3 F12 F13 IF data 5 -2 -3 Serial interface output data 2 SO4 SO5 SO6 CKSTP mode SO7 Test port 2 #4 I/O port 8 F16 F17 Serial interface input data 2 F18 F19 SI4 SI5 Timer 2 Hz F/F 10 Hz 0 100 Hz 0 0 I/O port 8 0 -0 Interrupt permission flag HOLD EF1 EF2 EF3 EF4 -0 -1 -1 I/O port 9 -2 -3 -2 -3 SI6 SI7 P16 IF counter control 1 Timer reset IF1/2 7 PW IF1/INTR1 IF2/IN2 2 Hz F/F Clock IF counter control 2 Interrupt control G1 POL1 (INTR1) POL2 (INTR2) IE * HOLD -0 -1 I/O port 9 FE4 (Timer) MUTE -0 HOLD PLL off control -1 IF counter Split (DATA) → DA -2 Prescaller IN OT Count Up -3 PSC ENA F/F port 1 Pull-up -2 -3 INTR1 INTR2 0 Interrupt master flag IMF STA/ STP 8 MUTE MANIAL G0 MUTE control Interrupt permission flag HOLD EF1 (INTR1) FE2 (INTR2) FE3 (SIO) MUTE control I/O Unlock detection ENA POL I/O-1 9 UNLOCK Detection RESET A BF0 B BM0 C CA Flag BM1 * POL DO2 control Interrupt latch reset M1 ILR1 (INTR1) ILR2 (INTR2) ILR3 (SIO) ILR4 (Timer) Input port (INTR1) IN2 IL1 Interrupt latch IL2 IL3 IL4 DAL CT0 CT1 CT2 CT3 DAL address CT7 DA0 DA1 DA2 DA3 0 0 0 PN M0 BUZZR output control 1 BF1 BF2 BEN Timer counter Interrupt detection data1 DAL ID0 ID1 ID2 ID3 Timer counter data 1 BUZZR output control 2 BUZR ON * Timer counter Interrupt detection data2 POL * DAL address DA0 DA1 DA2 DA3 CA flag 0 0 0 CT4 Timer counter data 2 CT5 CT6 ID4 ID5 ID6 ID7 Timer counter control CK0 CK1 GT CR d0 Data register 1 d1 d2 d3 G register 1 d7 G0 G1 G2 G3 S1 Data select S2 S3 S4 d4 d0 Data register 1 d1 d2 d3 G register 1 D G0 E G4 F #0 #1 #2 #3 COM1 G5 Test port 1 * * Data select G3 SEL1 SEL2 SEL4 SEL8 d4 Data register 2 d5 d6 Data register 2 d5 d6 d7 G1 G2 G register 2 Segment data 1/ General purpose output data COM1/OT COM2/OT COM3/OT COM4/OT d8 Data register 3 d9 d10 d11 G4 G register 2 G5 0 0 d8 Data register 3 d9 d10 d11 Segment data2/ Segment IO control COM2 COM3 COM4 d12 Data register 4 d13 d14 d15 d12 Data register 4 d13 d14 d15 Refer to next page 21 2006-03-02 TC9329AFAG/AFCG φKL2D Data Select S1 S2 S4 S8 φL2D I/O φL2E φL2F φL3B φK3B OUT2 Y1 Y2 Y4 Y8 Y1 Y2 OUT2 Y4 S13 COM4 /OT4 COM1 COM2 S14 COM4 /OT8 COM1 COM2 S15 COM4 /OT12 COM1 COM2 S16 COM4 COM1 COM2 S17 COM3 COM4 COM1 COM2 S18 COM3 COM4 COM1 COM2 COM3 COM4 CTR RESET COM3 COM4 DOWN COM3 COM4 DA12 COM3 COM4 DA8 COM3 COM4 DA4 COM3 COM4 DA0 Y8 Y1 Y2 OUT3 Y4 Y8 Y1 Y2 IN3 Y4 Y8 S1/OT1~OT4 0 COM1 /OT1 COM2 /OT2 COM3 /OT3 DAL address 1 DA1 DA2 DA3 DA0 DAL address 1 DA1 DA2 DA3 S2/OT5~OT8 1 COM1 /OT5 COM2 /OT6 COM3 /OT7 DAL address 2 DA5 DA6 DA7 DA4 DAL address 2 DA5 DA6 DA7 S3/OT9~OT12 2 COM1 /OT9 COM2 /OT10 COM3 /OT11 DAL address 3 DA9 DA10 DA11 DA8 DAL address 3 DA9 DA10 DA11 S4/OT13~OT14 3 COM1 /OT13 COM2 /OT14 S5 4 COM1 5 COM1 6 COM1 7 COM1 8 COM1 9 COM1 A COM1 B COM1 C COM2 COM3 COM4 COM2 S12 COM3 COM4 -0 -1 COM2 S11 COM3 COM4 -0 -1 COM2 S10 COM3 COM4 -0 -1 COM2 S9 COM3 COM4 S15 S16 COM2 S8 COM3 COM4 S11 S12 COM2 S7 COM2 S6 COM3 DAL address 4 DA13 * * DAL address 4 DA12 DA13 0 0 Pulse counter control POL * * Pulse counter data PC0 PC1 PC2 PC3 Pulse counter control OVER RESET OSC control S14 IFin CPU Select OSC on Freq Select OVER * * Pulse counter data PC4 PC5 PC6 PC7 Segment/IO select S13 Pulse counter data 0 0 0 Segment/IO select S17 S18 OSC0 SIO2 data select OSC data OSC1 OSC2 * SIO2 decode data OSC3 DEC0 DEC1 DEC2 DEC3 I/O control 1 -2 -3 SIO2 information data 1 INF0 INF1 INF2 INF3 I/O control 2 -2 -3 Vreg ON -2 -3 * * * SIO2 information data 2 INF4 INF5 INF6 INF7 I/O control 4 SIO2 information data 3 INF8 INF9 INF110 INF11 SIO2 information data 4 INF12 0: Offset data 1: Check data INF13 INF14 INF15 SIO2 offset/Check data 1 OFS0 /CHK0 OFS4 /CHK4 OFS1 /CHK1 OFS5 /CHK5 OFS2 /CHK2 OFS6 /CHK6 OFS3 /CHK3 OFS7 /CHK7 SIO2 offset/Check data 2 D SIO2 offset/Check data 3 E OFS8 /CHK8 LCD control F DISP OFF LCD OFF OTB-UP * OFS9 /CHK9 0 0 22 2006-03-02 TC9329AFAG/AFCG ○ I/O map All of the ports within the device are expressed with a matrix of six I/O instructions (OUT 1 ~ 3 instructions and IN 1 ~ 3 instructions) and a 4-bit code number. The allocation of these ports is shown on the following page in the form of an I/O map. The ports used in the execution of the various I/O instructions on the horizontal axis of the I/O map are allocated to the port code numbers indicated on the vertical axis. The G-register, data register and DAL bits are also used as ports. The OUT1 ~ 3 instructions are specified as output ports and the IN 1 ~ 3 instructions are specified as input ports. Note: The ports indicated by the angled lines on the I/O map do not actually exist within the device. The contents of other ports and data memories are not affected when data is output to a non-existent output port with the execution of the output instruction. The data loaded from data memories when a non-existent input port has been specified with the execution of an input instruction becomes “1”. Note: The outout ports marked with an asterisk (*) on the I/O map are not used. Data output to these ports assume the don’t care status. Note: The Y1 contents of the ports expressed in 4 bits correspond to the data memory’s low order bits and the Y8 contents correspond to the high order bits. The ports specified with the six I/O instructions and code No. C are coded in the following manner: φ [K/L] mn (o) Contents of the selection port (indirectly specified data, 0-F [HEX]) I/O instruction’s operand CN (0~F [HEX]) The six I/O instructions are coded with the digits 1 to 3 I/O Instruction m OUT1 1 OUT2 2 OUT3 3 IN1 1 IN2 2 IN3 3 Indicates the input/output port K: Input port (IN1~IN3 instruction) L: Output port (OUT1~OUT3 instruciton) (Example) The setting for the G-register is allocated to code “D” and “E” in the OUT1 instruction. The encoded expression at this time becomes “φL1D”and “φL1E”. 23 2006-03-02 TC9329AFAG/AFCG ○ Clock Generator The clock generator generates the standard clock used as the standard of the system clock supplied to a core-based CPU and circumference hardware. Through the program, it is possible to switch between an external crystal oscillation circuit and the built-in CR oscillation circuit as the CPU operation clock. 1. Crystal Oscillation Circuit 75 kHz crystal resonator is connected to the device’s crystal resonator terminal (XN, XOUT) as indicated below. During normal operation, the oscillation signal is supplied to the clock generator, the reference frequency divider and other elements, and generates the various CPU timing signals and reference frequency. (XOUT) 54 R X’tal = 75 kHz 55 (XIN) 56 (GND) 57 CO X'tal CI Note: It is necessary to use a crystal resonator with a low CI value and favorable start-up characteristics. Be sure to adjust and set the external resistance and capacitor constant to the crystal resonator actually used. 2. CR VCO Through the use of the built-in CR VCO, it is possible to raise the CPU processing speed. This will be utilized for high-speed processing in the required system. The OSCon bit controls the ON/OFF operation of the CR oscillation circuit; and if this bit is set to “1”, the CR VCO starts operating. If the setting of the CPU Select bits is “0”, the CPU operates on the 75 kHz for the crystal oscillator clock; if the setting is “1”, the CPU operates on the CR VCO clock. The oscillation frequency of CR VCO (fCR) is 1 MHz (typ.); and a clock that divides this frequency by 1/2 or 1/4 can be used as the CPU operation clock. The CR VCO frequency serves as a system that can control the resistance of the CR VCO through the program so that factors, such as power supply voltage and the variations in the built-in capacitor and resistance can be changed. For this reason, it is possible to calculate the CR oscillation frequency using the IF counter. If used for the CPU clock, the frequency of the CR VCO is changed to the CPU operation clock after the CR VCO resistance is controlled and adjusted to the set-up frequency and the CR oscillation frequency is calculated using the IF counter. Moreover, the frequency changes with the change in power supply voltage from −15% to +10% of the set value, VDD = 1.5 V (i.e., from VDD = 1.1 V to VDD = 1.8 V). If a setting frequency with an accuracy greater than this range is required, be sure always to adjust the CR VCO frequency using the IF counter. The frequency setting range of CR VCO can be freely set up in the range 0.8 to 1.2 MHz. The resistance of the CR VCO, which has a standard value of 36 kΩ (1 MHz), can be programmed to 16 levels, from 20 kΩ to 50 kΩ (in 2 kΩ steps) and the value set using the data of 3 bits of OSC0-OSC3. The Freq Select bit sets the division value of the CR oscillation frequency. The frequency is fCR/2 if this bit is set to “0”, and fCR/4 if the bit is set to “1”. When the frequency is set to fCR = 1 MHz, the instruction executing time is compared with the 40 µs for when the crystal oscillator clock is used. The instruction execution time is accelerated to 3/500 kHz = 6 µs for 1/2 division mode, and to 3/250 kHz = 12 µs for 1/4 division mode. Although the processing speed of the CPU is accelerated, other timing functions (such as that for the Timer, etc.) operate on the crystal oscillation frequency. The Ifin bit is a control bit for changing the CR oscillation frequency clock to the IF counter. If “0” is set, the IF counter starts calculating the IF (etc.); if “1” is set, the CR VCO frequency can be selected as the clock input of the IF counter. To calculate the CR VCO frequency, it is necessary to set the Prescaler IN bit to “1”. (→ Refer to IF counter item.) Moreover, the CR oscillation frequency clock can be output from the MUTE terminal, and used for external IC clocks and monitoring of the CR oscillation clock monitor. If the Test port 1 (φL1F) is set to “5H”, the CR VCO clock outputs from MUTE terminal. The setup and control of the frequency of the CR VCO is set using an OUT3 instruction for which [CN = 6~7H] has been specified in the operand 24 2006-03-02 TC9329AFAG/AFCG Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 φL2D SEL1 Data select Y1 Y2 Y4 Y8 φL3B 6 IFin OSC control CPU Freq select OSC on select Change of CR oscillation dividing frequency Control for CR VCO operation ..... 0: fCR/2 1: fCR/4 0: CR VCO stop 1: CR VCO operation 0: Used for crystal resonator frequency clock 1: Used for inside oscillation frequency clock 0: IF input operation mode 1: Internal oscillate frequency calculation mode Selection of CPU clock ................ Connection control to IF counter of CR oscillation clock Y1 Y2 Y4 Y8 φL3B 7 OSC data OSC0 OSC1 OSC2 OSC3 Selection of the internal resistance of CR VCO OSC0 OSC1 OSC2 OSC3 0 0 0 0 Resistance (Typ.) 20 kΩ (2 kΩ interval) 36 kΩ (2 kΩ interval) 50 kΩ Oscillation Frequency (Typ.) fCR = 1.8 MHz ↓ 1 ↓ 0 ↓ 0 ↓ 0 ↓ fCR = 1.0 MHz ↓ 1 ↓ 1 ↓ 1 ↓ 1 ↓ fCR = 0.64 MHz Note: The oscillation frequency is the frequency of a standard product and this frequency varies with the power supply voltage and the product. The frequency range in which settings be made is from 0.8~ 1.2 MHz. 3. Composition of a Clock Generator (Circumference hardware operation clock) 75 kHz CPU timing clock XOUT 55 XIN 56 CPU Select Crystal oscillation circuit CPU Timing generator OSC0~OSC3 CR oscillation circuit 1/2 1/2 To IF counter and MUTE terminal Freq Select OSCon 25 2006-03-02 TC9329AFAG/AFCG ○ System Reset The device’s system will be reset when the RESET terminal is subject to the “L” level. The program will start from 0 address after about 100 ms of stand-by time have elapsed following system reset. Note: The LCD common output and the segment output will be fixed at their “L” level during system reset and during the subsequent stand-by period. Note: It is necessary to initialize through the program any of the internal ports shown in the above-mentioned I/O map that were not initialized after system reset. The mark on the I/O map after system reset indicates a port or bit set to “0” after system reset, while the mark indicates a port or bit set to “1”. A port or bit with no mark is unfixed.. I/O φL2F OUT2 I/O φL1 OUT1 φL2D Y1 Y2 Y4 Y8 Code Y1 Y2 Reference select Y4 Y8 Programmable counter I/O control 1 8 -0 -1 -2 -3 5 R0 R1 R2 P16 After system reset, this port is set to “0”. After system reset, this port is set to “1”. After system reset, this bit is unfixed. (Note) VDD terminal (Note) RESET terminal GND Crystal oscillator stops during the reset from a reset terminal. CPU Stand-by operation (about100 ms) XOUT terminal Stand-by (about 100 ms) Reset CPU operation Stand-by (about100 ms) Internal reset signal CPU operation Note: If there is a possibility that the power supply voltage will drop to 0.9 V or less, set to clock stop mode or activate the reset operation. 26 2006-03-02 TC9329AFAG/AFCG ○ Back-up Mode By executing the CKSTP instruction or WAIT instruction, three kinds of back-up mode can be activated. 1. Clock Stop Mode Clock stop mode is a function that suspends system operations and maintains the internal status immediately prior to suspension at a low level of current consumption (under 1 µA). Crystal oscillations suspended simultaneously and CMOS output ports and output terminals for LCD display purposes are automatically set at “L” level, and N-channel open-drain terminals are set to off status (high impedances) automatically. The supply voltage can be reduced to 0.75 V with clock stop mode. Suspension is activated at the CKSTP instruction execution address when the CKSTP instruction is executed. The next address is executed after approximately 100 ms of stand-by time when clock stop mode is cancelled. (1) Clock stop mode setting There are two types of mode setting for clock stop mode. The required setting is selected with the CKSTP MODE bit. This bit is accessed with the OUT2 instruction for which [CN = 6H] has been specified in the operand. Y1 Y2 Y4 CKSTP mode 0: MODE-0 1: MODE-1 Y8 φL26 ① MODE-0 Wtih this mode set, the clock stop mode is assumed if the CKSTP instruction is executed when the HOLD terminal is at “L” level. The same operations as the NOOP instruction will be assumed if the CKSTP instruction is executed when the HOLD terminal is at “H” level. MODE-1 With this mode set, the clock stop mode is assumed when the CKSTP instruction is executed regardless of the HOLD terminal level. ② Note: The PLL will assume off status during execution of the CKSTPinstruction. Note: Before the execution of the clock stop instruction, be sure to access the HOLD input terminal and I/O port 1 input port and rest the 2 HzF/F. Without execution of this instruction, it may not be possible to enter clock mode even if clock mode is executed. (2) Canceling clock stop mode ① MODE-0 Clock stop mode is cancelled when specified in this mode by changing the “H” level of the HOLD terminal or the input status of the I/O port (P1-0~3) specified in the input port. MODE-1 Clock stop mode is cancelled when specified in this mode by changing the HOLD terminal or the input status of the I/O port (P1-0~3) specified in the input port. ② 27 2006-03-02 TC9329AFAG/AFCG (3) Clock stop mode timing MODE-0 ① High impedance XOUT terminal CPU operation CKSTP instruction NOOP operation CKSTP instruction execution NOOP operation Clock stop Stand-by (about 100 ms) CPU operation (The clock stop mode is assumed if the CKSTP instruction is executed when the HOLD input is at “L” level.) ② MODE-1 HOLD terminal High impedance XOUT terminal CPU operation CKSTP instruction CKSTP instruction execution CKSTP instruction execution Clock stop Stand-by (about 100 ms) CPU operation Clock stop (The clock stop mode is assumed whenever the CKSTP instruction is executed.) (4) Example of a circuit (example of a MODE-0 circuit) 0.1 µF VDD 27 VDD 39 POWER VDD 27 VDD 39 POWER 470 µF 0.1 µF 0.1 µF 4700 µF 0.1 µF 1 kΩ HOLD 34 1 MΩ HOLD 34 1 MΩ Example of battery back-up circuit 1 kΩ Example of a condenser back-up circuit 28 2006-03-02 TC9329AFAG/AFCG 2. Wait Mode Wait mode suspends system operations, maintains the internal status immediately prior to suspension and reduces current consumption. There are two types of wait mode: SOFT WAIT mode and HARD WAIT mode. Operations are suspended at the address where the WAIT instruction was executed when the wait mode is activated. The next address is executed immediately after the wait mode is cancelled without entry to stand-by status. (1) SOFT WAIT mode Only the CPU operations within the device are suspended on execution of a WAIT instruction in which [P = 0H] has been specified in the operand. The crystal resonator and other elements will continue to operate normally at this time. The SOFT WAIT mode is efficient in reducing current consumption during clock operations when used in programs that include clock functions. Note: Current consumption will differ in accordance with execution time of CPU operation. (2) HARD WAIT mode The operations of all elements, with the exception of the crystal resonator, can be suspended by the execution of a WAIT instruction in which [P = 1H] has been specified in the operand. This enables even greater levels of current consumption reduction than the SOFT WAIT mode. It suspends the CPU operation. Note: The output port is maintained during HARD WAIT mode. All LCD display output terminals are fixed at “L” level and the voltage doubler circuit (VDB), LCD voltage regulator ciicuit (VEE) and LCD voltage doubler circuit (VLCD) operate. (3) Wait mode setting The wait status is assumed whenever the WAIT instruction is executed. Note: The PLL OFF status will be assumed during the wait mode. (4) Wait mode cancellation conditions Wait mode is cancelled when the following conditions are satisfied: ① When the input status of the HOLD terminal changes. ② When the input status of the I/O port specified in the input port (P1-0~3) changes. ③ When the 2 Hz Timer F/F is set as “1” (only with the SOFT WAIT mode) 3. HOLD Input Port Y1 Y2 Y4 Y8 0 Y1 Y2 Y4 Y8 φK17 HOLD (INTR1) (INTR2) φL39 HOLD PLL OFF control 0: Input “L” level 1: Input “H” level 0: Do not control of PLL OFF with a HOLD terminal 1: PLL OFF mode with “L” level of HOLD terminal The HOLD terminal can be used as an input port. This bit loads into the data memory data input using the IN1 instruction for which [CN = 7H] has been specified in the operand. It is necessary to access this port prior to the execution of the CKSTP instruction when clock stop mode or wait mode is set. Note that, without accessing this port it may not be possible to enter clock stop mode even if this instruction is executed. While HOLD PLL off control bit is set to “1”, PLL off mode result if HOLD terminal input goes to “L” level. Therefore setting to PLL off-mode can be done quickly during battery replacement. The bit is accessed with the OUT3 instruction for which [CN = 9H] has been specified in the operand. PLL off mode becomes active even if all reference ports are “1”. (→ Refer to the reference frequency divider item) Note: The HOLD input terminal is used as an INTR2 terminal. The same as data is output at the HOLD and INTR2 input ports. 29 2006-03-02 TC9329AFAG/AFCG ○ Interrupt Function The peripheral hardware that can use the Interrupt function has an INTR1 terminal, INTR2 terminal, Timer counter, and Serial interface. If this peripheral hardware fulfills the conditions, the interrupt request signal from the peripheral hardware is output, and the interrupt request is issued. On being received, each interrupt branches to a vector address determined by the interrupt factor, and the processing routine for the interrupt begins. Pretreatment and post-processing are necessary in the interrupt routine, before and after the normal Interrupt processing, to restore the same state that was in effect at the time the interrupt occurred. It is necessary to perform shunting and return of the register and indestructible data memory used by ALU to the data memory for Interrupt use.. When interrupt processing ends, the program is restored using the Return command for the Interrupt function. The INTR1 and INTR2 terminals are serve as IFin1 and HOLD terminals. 1. Interrupt Control Circuit The Interrupt Control Circuit consists of an interrupt permission flag, an interrupt latch, and an interrupt priority circuit block. This control performs setup and control through the OUT2/IN2 instructions. (1) Interrupt enable flag The interrupt enable flag has a master permission flag and individual permission flags corresponding to each interrupt factor. An individual enable flag sets the interrupt prohibition/permission according to the interrupt factor. A master enable flag is a flag for prohibiting or permitting all Interrupts. If these enable registers are set to “1”, permission takes effect; if they are set to “0”, prohibition takes effect.. An individual enable flag is accessed through the OUT2/IN2 instructions for which [CN 8H] has been specified in the operand. A master enable flag can perform permission/prohibition by execution of an EI/DI instruction. Interrupt is prohibited by execution of a DI command, and enabled by execution of an EI command. At this time, interrupt is enabled during execution of the EI command and DI command in the program. If an interrupt request is received, the master enable flag is reset to “0” and all interrupts are prohibited. On execution of the interrupt return command, the flag is set to “1”. A master enable flag is read into the data memory using an IN2 command for which [CN = 7H] has been specified. Y1 Y2 EF2 Y4 EF3 Y8 EF4 φLK28 EF1 An individual enable flag EF1･･･INTR1 terminal EF2･･･INTR2 terminal EF3･･･Serial interface EF4･･･8 bits timer counter “0”･･･Prohibition “1”･･･Enable Y1 Y2 0 Y4 0 Y8 0 φK27 IMF Master enable flag Reset to “0” on receipt of interrupt or execution of DI command. Set to “1” on execution of the Interrupt Return or EI commands. 30 2006-03-02 TC9329AFAG/AFCG (2) Interrupt latch If an Interrupt request generates, the interrupt latch is set to “1”. If Interrupt is enabled, the CPU will be requested to receive the Interrupt, and the process will branch to the Interrupt routine. If the Interrupt is received at this time, the Interrupt latch is reset by data “0” automatically. Interrupt latch data can read by the program and the existence or nonexistence of an Interrupt occurrence can be determined on an individual basis. In accordance with the Interrupt request, the Interrupt latch that was set to “1” is reset to “0”; in this way, it is possible to cancel or initialize the Interrupt request. Y1 Y2 ILR2 Y4 ILR3 Y8 ILR4 φL29 ILR1 Interrupt latch reset If set to “1”, interrupt latch is reset to “0”. Y8 IL4 0: No Interrupt 1: Interrupt existence On occurrence of Interrupt request, set to “1”; on receipt of Interrupt, reset to “0”. Y1 Y2 IL2 Y4 IL3 φK29 IL1 Interrupt latch data IL1･･･INTR1 terminal IL2･･･INTR2 terminal IL3･･･Serial interface IL4･･･8-bits timer counter (3) Interrupt priority circuit block Interrupt priority circuit is a circuit that determines the order in which Interrupts are processed if Interrupts occur simultaneously or if two or more Interrupts have been permitted.. Vector addresses for the interrupt routine are also generated in this block. Priority 1 2 3 4 Interrupt Factor INTR1 terminal INTR2 terminal Serial interface Timer counter Vector Address 0001H 0002H 0003H 0004H 31 2006-03-02 TC9329AFAG/AFCG 2. Interrupt Reception Processing The interrupt request is retained until the interrupt is received or the interrupt latch is reset to “0” by system reset operation or by the program. The interrupt reception operation is as shown below. ① If the interrupt conditions are fulfilled, each item of peripheral hardware outputs each interrupt request signal and sets the Interrupt latch to “1”. ② The Interrupt latch of the interrupt factor received resets to “0” if the interrupt enable flag corresponding to each interrupt factor and the master enable flag are set to “1”. ③ The interrupt master enable flag resets to “0” and interrupt is prohibited. ④ The contents of a stack pointer are made -1. ⑤ The contents of the program counter (PC) are shunted to the stack register. In this case, the contents of the program change to the next address after the point at which the interrupt was received, or the next address after the point at which the interrupt was permitted. ⑥ The contents of the vector address corresponding to the received interrupt are transferred to the program counter. ⑦ The contents of the vector address are executed. Steps ①~⑥ are executed within one instruction cycle. This instruction cycle is called the “Interrupt Cycle” Note: The stack pointer is a pointer for which an 8-level stack register is specified. Interrupt enable period Instruction EI Instruc -tion Set “1” to individual enable flag Interrup -tion cycle IMF (Master enable flag) Interrupt signal Interrupt signal IL (Interrupt latch) EF (Individual enable flag) One instruction cycle Interrupt enable period Interrupt processing routine Interrupt reception Interrupt holed period EI instruction Set “1” to individual enable flag Interrupt cycle Instruction IMF (Master enable flag) Interrupt signal Interrupt signal IL (Interrupt latch) EF (Individual enable flag) Interrupt reservation period Interrupt processing routine Interrupt reception 32 2006-03-02 TC9329AFAG/AFCG 3. Return Processing from Interrupt Processing Routine A special command, the RNI instruction, is used to return to the processing state that was in effect before the interrupt was received. With execution of the RNI instruction, the following processing is executed step-by-step automatically. ① The contents of the address stack, specified by the stack pointer, are returned to the program counter. ② Set the Interrupt Master Enable Flag to “1” to activate the enable state. ③ +1 is applied to the contents to the stack pointer. The above-mentioned RNI instruction processing is performed in one instruction cycle. 4. Interrupt Processing Routine The interruption is received regardless of the program being run when the interrupt request is issued if this is the program area where the interrupt is enabled. Therefore, to restore the base program after the interrupt processing is completed, it is necessary to return to the state in which interrupt processing was not being performed. For this reason, it is necessary to perform the shunting and return operations within the interrupt processing routine, at least for those items such as the register and data memory that can be operated within the interrupt processing routine. Shunting processing In the execution of the shunting processing, it is essential that a carry flag be shunted. If interruption is received during the execution of arithmetic or similar operations, the contents of the carry flag (CY), etc., will change, resulting in the program making incorrect decisions. For this reason, the contents of the carry flag are shunted in the data memory once through the IN1 instruction in the data of the carry flag of the I/O map. The contents of the data memory used by the interruption processing routine and the contents of a general register are also made to shunt if needed. Furthermore, when MVGD, MVGS or DAL instruction is used in the interrupt routine, it is necessary to shunt the contents of the G-register or the DAL address register. (2) Return processing Return processing should do the opposite to the above-mentioned shunting processing. Since, when the interrupt is received, the interrupt master enable flag is reset to “0”, it follows that before receiving the interrupt, the interrupt master enable flag must have been “1”. For this reason, the RNI instruction is executed and a master enable flag is returned. (1) 5. Multiplex Interrupt Multiplex Interrupt is a method of processing others interrupt during interrupt processing. As shown in the figure, the other interrupt factor C or D is processed during the interrupt processing of interrupt factors A and B. In this process, the depth of the interrupt is called the interrupt level. Main routine Interrupt level 1 Interrupt level 2 Interrupt level 3 Interrupt level 4 MAIN B D A B C D C The example of multiplex interrupt 33 2006-03-02 TC9329AFAG/AFCG Caution is required for the following points when using multiplex interrupt. ① The priority of interrupt factors ② Restriction of the address stack level used at the time of interrupt request issue ③ Shunting processing of the carry flag, the data memory, etc. (1) Priority of interrupt factor In this priority ranking, the processing of interrupt C must be given priority even if the interrupt processing of A or B is in progress; and the processing of D must be given priority even if the interrupt processing of C is in progress. The necessity of determining priority in the handling of multiple interruptions can be illustrated as follows. Suppose, for example, there are the interruption factors A and B. For factor A, a request is generated about every 10 ms and the interrupt processing time is 4 ms; for factor B, a request is generated about every 2 ms and the interrupt processing time is 1 ms. If no priority were applied to A and B, then a request for interrupt A that came in during the processing of interrupt B could lead to interrupt A being processed, resulting in the processing of interrupt B being repeatedly stopped. Such a case requires a program that establishes the priority A B, not only prohibiting interrupt A during the processing of interrupt B but also enabling the reception of interrupt B during the processing of interrupt A. As explained in the item on the interrupt priority circuit block, when all individual enable flags are set to “1” (enable state), the priority of the hardware can be changed by manipulating the individual enable flags in the program. As a rule, received interrupts and low-priority interrupts are prohibited, and high-priority interrupts are enabled in the interrupt processing routine. Restriction of address stack level As explained in the item on interrupt reception processing, when an interrupt request is issued, the return address is shunted automatically to the address stack. As explained in the item on registers, an address stack is also used for execution of sub-routine call instructions on eight levels. For this reason, if the interrupt level and sub routine call level exceed eight levels, the contents of the return address recorded from the first address stack are destroyed. Therefore restriction is necessary. Shunting processing When using the Multiplex Interrupt function, it is necessary to secure a shunting area for shunting processing separately for each interrupt factor. (2) (3) 34 2006-03-02 TC9329AFAG/AFCG ○ External Interrupt and Timer Counter Function There are two types of external interrupt: that using the INTR1 terminal and that using the INTR2 terminal. Interrupt requests are issued by the rising or falling edge of a signal applied to these terminals. The timer counter is an 8-bit binary counter and has the function of timer and external clock timer. The input of the external clock timer function is used as an external interrupt terminal (INTR1, INTR2). 1. External Interrupt Function There are two input terminals for external interrupt, INTR1 and INTR2; and an interrupt request is issued on detection of the edge of these inputs. There is a noise canceller for the input: a noise removal clock uses a frequency of 75 kHz, and any pulse under this frequency is removed as noise. The IE bit is an enable bit which permits 8-bit timer counter operation, and interrupt and external interrupt requests. It is possible to select either the rising or falling edge as the input edge for each terminal. Usually, this bit is set to “1”. These controls are accessed using an OUT2 instruction for which [CN 7H] has been specified in the operand. The program will branch to address 0001H on receipt of an INTR1 interrupt, and to address 0002H on receipt of an INTR2 interrupt. These terminals are used as input ports and the input status can be read into the data memory by execution of an IN2 instruction for which [CN 7H] has been specified in the operand. Y1 Y2 Y4 IE Y8 φL27 POL1 POL2 INTR1 INTR2 Edge select * 8-bitsTimer and control external interrupt operation enable control “0”: Prohibition “1”: Enable Usually, the bit is set “1”. 1: Rising edge 0: Falling edge Pulse less than 13.3 µs eliminated more than 40 µs regarded as a signal Note: The edge of the external clock of the timer counter is also controlled. No noise cancel function is used for the input to the timer counter. Therefore, even if no interrupt occurs, caution is necessary regarding the input of a clock pulse of less than 40 s into the clock pulse counter. 1: Count by rising edge 0: Count by falling edge Select edge of timer counter Y1 Y2 Y4 INTR2 Y8 O 0: Input “L” level 1: Input “H” level φK17 ( HOLD ) INTR1 The input state of each Note: An interrupt request may be issued if an edge is changed using POL bits. For this reason, when changing an edge, be sure to prohibit interruption beforehand. After making the change, reset the interrupt latch and return to normal operation. Note: The INTR1 terminal and INTR2 terminal are used as IFin1 terminal and HOLD terminal respectively. If using only the INTR1 terminal be sure to set IF1/INTR bits (φL16) to “0”. Also, the same data is output at the HOLD input and INTR2 input port. 35 2006-03-02 TC9329AFAG/AFCG 2. Timer Counter Function Timer counter are consists of 8-bit binary counter, counter coincidence register, digital comparator and controlled the control circuit. If timer counter is coincided with the contents of counter coincidence register, timer counter is outputted a coincidence signal pulse and interrupt request is done by inputting timer clock to 8-bit binary counter timer clock. Reset of Timer counter is possible with a coincidence pulse and a program, and it can perform enable and prohibition of reset by the coincidence pulse. As a clock of timer, it can be selected INTR1/2 input and an instruction cycle and 1 kHz. (1) Timer counter register configuration The timer counter register consists of a counter data, coincidence register and a control register. φL2A Y1 ID0 Y2 ID1 Y4 ID2 Y8 ID3 φL2B Y1 ID4 Y2 ID5 Y4 ID6 Y8 ID7 Timer counter coincidence data φK2A Y1 ID0 Y2 ID1 Y4 ID2 Y8 ID3 φK2B Y1 ID4 Y2 ID5 A coincidence pulse will be output if in agreement with the timer counter. Y4 ID6 Y8 ID7 Timer counter data Timer counter data is read into data memory as binary data. Y1 Y2 CK1 Y4 GT Y8 CR φL2C CK0 Select of timer clock Timer counter reset･･･“Whenever sets “1”, counter is reset. Enable counter reset by coincidence pulse. 0: Enable 1: Prohibition CK1 0 0 1 1 CK0 0 1 0 1 Timer clock INTR1 terminal input INTR2 terminal input Instruction cycle clock (40 µs) 1 kHz Select clock edge by POL bit 0: Count by raising edge 1: Count by falling edge Note: To use the timer counter, it is necessary to set the IE bit to “1”. Note: Set the IF1/INTR bits (φL16) to “0” when the INTR1 terminal is used as a timer clock. 36 2006-03-02 TC9329AFAG/AFCG (2) Timer mode Timer mode is detected fixed time. Interrupt request is done and reset to counter whenever it detects fixed time. At this time, control bit is set to 1 kHz or an instruction as timer clock, “0” to GT bit and “0” (it does not reset) to CR bit. Timer coincidence data is Timer time = IDn (coincidence data) × Timer clock cycle It sets up the data which corresponding to time. In addition, although an external terminal can be used for Timer clock, a clock frequency should use the frequency below 25 kHz. If GT bit is setup “1”, it can be also be integrated of an external clock. It is used by inputting more than 40 µs cycle at the time of an external clock input. Timer clock Timer data IDn 00H 01H 02H 03H ID (N − 1) IDn 00H 01H 02H 03H Coincidence pulse Request for interrupt and reset timer counter. 37 2006-03-02 TC9329AFAG/AFCG ○ Internal Interrupt and Interrupt Function Interrupt has two types of timer counter and serial interface. 1. Interrupt of Timer Counter If timer counter value is same as coincidence register value, interrupt of timer counter is occurred interruption. Refer to the item of timer counter function in detail. 2. Interrupt of Serial Interface Interrupt of serial interface is occurred interruption at the time of finishing operation of serial interface. Refer to the item of serial interface function in detail. 3. Interruption Block Configuration Serial interface interrupt HOLD 75 kHz ILR1 INTR1 35 (IFin1) INTR2 34 ( HOLD ) POL1 Noise canceller Noise canceller ILR2 ILR3 ILR4 S IL1 R S IL2 R S IL3 R S IL4 R 1 kHz Instruction cycle clock INTR2 INTR1 POL2 EF1 EF2 EF3 EF4 Decoder Priority determination•Vector address generate circuit La Vector address Interrupt receiving signal CK0 CK1 Selector CT0~CT7 CR 8 bits binary counter R Coincidence pulse Coincidence register (ID0~ID7) GT DI instruction RNI instruction EI instruction S IMF R 38 2006-03-02 TC9329AFAG/AFCG ○ Programmable Counter The programmable counter consists of two modulus prescalers, a 4-bit + 13 bit programmable counter and a port to control these elements. The programmable counter controls the ON/OFF functions for the contents of the reference port and HOLD input status. By using external prescaler (TD6134AF/TD7101/04F) or 1 chip tuner IC that is built-in for 1/16 prescaler (TA2142FN), it’s possible to reduce the emission from the tuner portion and consumption current. 1. Programmable Counter Control Port This port is controlling for division frequency, division method and operating current and gain of prescaler. Y1 Y2 PW0 Y4 PW1 Y8 FM φL10 HF Power control Division method setting φL11 Y1 P0 Y2 P1 Y4 P2 Y8 P3 φL12 Y1 P4 Y2 P5 Y4 P6 Y8 P7 φL13 Y1 P8 Y2 P9 Y4 Y8 φL14 Y1 Y2 Y4 Y8 φL15 Y1 Y2 Y4 Y8 P16 P10 P11 P12 P13 P14 P15 LSB Setting the number of divisions of the programmable counter MSB The division method and power control of the prescaler are accessed using an OUT1 instruction for which [CN = 0H] has been specified in the operand. The division frequency setting is accessed using an OUT1 instruction for which [CN = 1~5H] has been specified and the setting is made by writing in the P16 bits (φL15). All data between P0 to P16 are updated when P16 is set. It is therefore necessary to access P16 without fail even when updating only certain items of data and to perform setting as the final process. Y1 Y2 Y4 Prescaller IN Y8 PSC ENA 0: PSC output prohibition 1: PSC output permission φL39 PSC output permission setup Pre-scaler IF counter input setup 0: Regular PLL composition 1: Pre-scaler division output is input to IF counter. PSC output permission setup is used at the time of connection of external prescaler. In the setup to prescaler IF input, if the bit is set to “1”, a programmable counter stops and prescaler 1/15 and 16 are fixed to 16 division. Usually, consisting of PLL, the bit is set to “0”. (→ Refer to the IF counter item) 39 2006-03-02 TC9329AFAG/AFCG 2. Division Method Setting The pulse swallow method or direct method are selected using the HF and FM bit. The power control bits (PW0/1) control the gain of the amplifier and prescaler (1/2  1/15•16). Although the power bit in each mode has five methods, set it up as shown in a table. By using the single-chip tuner IC that is built-in for the 1/16 prescaler (TA2142FN), set the LF mode and set the division value after the 1/16 division frequency. Example of Receiving Band MW/LW SW FM TV (1 ch~12 ch) Operation Frequency Range 0.5~8 MHz 3~30 MHz 1~10 MHz 60~130 MHz 2•n 80~230 MHz n Division Number (Note) Mode LF HF1 HF2 FM VHF HF 0 1 1 1 1 PW0 1 1 0 1 0 PW1 0 0 1 0 1 FM 0 0 0 1 1 Division Method Direct division method Pulse swallow method (1/15•16) Pulse swallow method (1/2 + 1/15•16) Note: “n” represents the number of divisions programmed. Note: Do not perform a setup except for the above-mentioned power control setup. There are not normal operation such as flowing over-current or unlocked PLL etc.. Note: A local oscillation input is common to each mode, and is altogether input into OSCin terminal. 3. Frequency Division Number Setting The frequency division number for the programmable counter is set in bits P0 to P16 in binary. • Pulse swallow method (17 bit) MSB P16 P15 P14 P13 P12 P11 P10 2 16 LSB P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 2 0 The range of frequency division number setting (n = 210H~1FFFFH (528~131071) • Direct division method (13 bit) MSB P16 P15 P14 P13 P12 P11 P10 12 LSB P9 P8 P7 P6 P5 P4 0 P3 P2 P1 P0 2 2 The range of frequency division number setting (n = 10H~1FFFH (16~8191) Don’t care 40 2006-03-02 TC9329AFAG/AFCG 4. PSC Output Permission Setting In case of using the external pre-sccaler (TD6134AF/TD7101/04F), PSC output permission bit is setup to “1”. At this time, a swallow counter will be operating and prescaler will be in a stop state, and PSC output is outpu P2-3 terminal. A division method is set as LF mode, and AM VCO input and an external prescaler output are changed and input into AMin input terminal. P3 terminal is used by setting it as an output port. TC9329AFAG/AFCG TD6134AF PSC 53 7 PSC 0.01 µF OSCin 38 0.001 µF 5 OUT 2 FMin 0.001 µF 3 VHFin AM VCO FM/TV VCO The example of an external pre-scaler connection circuit 5. Programmable Counter Circuit Configuration • Pulse swallow method circuit configuration This circuit consists of amplifier, two 1/15•16 modulus prescalers, the 4-bit swallow counter and a 13-bit binary programmable counter. A 1/2 frequency divider is added to the front stage of the prescaler when in the VHF/FM mode. P0~P3 PW0/1 4 bit swallow counter Pre-set 13 bit programmable counter OSCin 0.01 µF 38 Amplifier 1/2 1/16 1/15•16 1/15 To the phase comparator P4~P16 41 2006-03-02 TC9329AFAG/AFCG • Direct division method circuit configuration The prescaler is not required if this is selected; instead, the13-bit programmable counter is used. PW0/1 Amplifier OSCin 38 Pre-set 13-bit programmable counter To the phase comparator P4~P16 Note: OSCin terminal has been fitted into the amplifier, and small amplitue possible by linking them to a condenser. The input is high impedance when PLL is in the off mode. VCO input serves as each of operation mode common terminal. Note: If it becomes PLL off-mode, all programmable counter parts will be stopped. The contents of each control port are held at this time. ○ Reference Frequency Divider The reference frequency divider divides the oscillation frequency of the external 75 kHz crystal and generates the following seven types of PLL reference frequency signals; 1 kHz, 3 kHz, 3.125 kHz, 5 kHz, 6.25 kHz, 12.5 kHz and 25 kHz. These signals are selected with reference port data. The selected signal is supplied as a reference frequency for the phase comparator as described below. Also, the PLL is switched on and off with the contents of the reference port. 1. Reference Port The reference port is an internal port for selecting the seven reference frequency signals. This port is accessed using an OUT1 instruction for which [CN 5H] has been specified in the operand ( L15). Operations for the programmable counter, the IF counter and reference counter are suspended; and the PLL assumes the off mode when the contents of the reference port are all “1”. As the frequency division setting data for the programmable counter is updated when the reference port is set, it is necessary to set the frequency division number of the programmable counter prior to setting the reference port. Y1 Y2 R1 Y4 R2 Y8 R2 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 Reference Frequency 1 kHz 3 kHz 3.125 kHz 5 kHz 6.25 kHz 12.5 kHz 25 kHz PLL off mode φL15 R0 0 Reference frequency selection code 0 0 0 1 1 1 1 42 2006-03-02 TC9329AFAG/AFCG ○ Phase Comparator and Lock Detection Port The phase comparator compares the difference in phasing between the reference frequency signal supplied from the reference frequency divider and frequency division output of the programmable counter and outputs the result. It then controls the VCO (voltage control oscillator) via a low pass filter in order to ensure that the two frequency signals and the phase difference match. In order to use a phase comparator and a charge pump output are constant voltage Vreg potential (1.5 V), it is possible to stabilized phase comparison even if VDD potential was set to 0.9 V. The DO terminal can also be used as a general-purpose output with the Do control port. 1. Do control Port and the Unlock Detection Port Y1 Y2 Y4 DO control PN M0 M1 M1 0 0 1 1 M0 0 1 0 1 DO Output Status Do output “L” level “H” level “HZ” Y8 φL19 UNLOCK RESET Set up DO output DO terminal output state Setup → set to “0” Unlock F/F and unlock enable are reset whenever the data is set at “1”. Y1 Y2 Y4 (INTR1) Y8 IN2 φK19 UNLOCK F/F ENA 0: Input terminal “L” level 1: Input terminal “H” level Input port Note: An input state is read for IF counter input combination terminal from this port at the time of an input port setup. INTR1 data turns into the same data as INTR1 port of an interruption item.1 0: PLL unlock detection stand-by 1: PLL unlock detection enabled Unlock enable Unlock detection bit 0: PLL lock status 1: PLL unlock status Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 φL2D SEL1 Data select Y1 Y2 Y4 Y8 φL3B A Vreg ON * * * 1.5 V constant voltage operation control of Vreg terminal output 0: Constant voltage OFF 1: Constant voltage ON 43 2006-03-02 TC9329AFAG/AFCG M0 and M1 bit of DO control ports are perform a general-purpose output port setup of DO output, and a setup of high impedance. The power supply of a phase comparison and a charge pump output circuit is using Vreg terminal. The Vreg terminal is output constant voltage of 1.5 V and “H” level of charge pump output is output Vreg terminal. For a reason, phase comparison operation power supply voltage was stabilized by 0.9 V is possible. The operation control of Vreg Constant voltage is controlled by Vreg ON bit (φL3BA), if the bit is set “0”, the Vreg terminal potential is output VDD level and set “1”, it becomes 1.5 V Constant voltage potential For this reason, it is set “1” at the time of PLL on mode and set “0” at the time of PLL off-mode. Unlock F/F detects the phase difference of a programmable counter division output and reference frequency to the timing from which about 180 degrees of phases shifted. When a phase does not suit at this time (that is unlock status), unlock F/F is set. The unlock F/F status is reset whenever the UNLOCK RESET bit is set as “1”. It is necessary to access to UNLOCK F/F after establishing more time than is required for the reference frequency cycle after the unlock F/F has been reset in order to detect the phase difference with the reference frequency cycle. It is for this purpose that the enable bit has been made available, but the unlock F/F must not be accessed until after it has been confirmed that the unlock enable has been set at “1”. Note: When PLL off mode is set during the DO output setup, the output of this terminal becomes as high impedance. In DO terminal, when PLL off-mode or the clock stop mode is set up at the time of a general-purpose output port setup, this output state is held. 2. Phase Comparator and Unlock Port timing Reference frequency Programmable counter output High impedance Do output “H” level (Vreg) “L” level (GND) Phase difference Lock detection strobe Unlock reset execution Unlock F/F Unlock enable 44 2006-03-02 TC9329AFAG/AFCG 3. Phase Comparator and the Unlock Port Circuit Configuration Vreg Decoder Reference frequency Phase comparator Programmable counter output 40 DO/OT M1, M0 bit UNLOCK ENABLE UNLOCK RESET UNLOCK F/F VDB (VDD × 2 doubler power supply) Constant voltage circuit 41 Vreg VregON Note: At the time of PLL on mode, VregON bit is setup “1” and PLL off mode, set up “0”. C1 R2 DO/OT 40 R1 LPF Vreg 41 0.47 µF (Typ.) To the VCO variable capacitor FN/VHF/AM VCO DC-DC converter 100 kΩ 0.01 µF 10 kΩ 1 µF 4.7 kΩ 4.7 kΩ 40 DO/OT Example of low pass filter circuit (for reference) Example of an active low pass filter circuit (for reference) Note: The filter circuits illustrated in the above diagrams are for reference purposes only. Be sure to design the actual circuits taking into account the band configuration of the system and required characteristics. 0.1 µF 45 2006-03-02 TC9329AFAG/AFCG ○ IF Counter The IF counter is a 20-bit general-purpose IF counter that calculates Fm and AM intermediate frequencies (IF) during auto-tuning and can be used for detecting auto-stop signals, etc. The VCO of an analog tuner is measured, and detection of the received frequency and detection of the CR oscillation frequency can be performed. 1. IF Counter Control Port and Data Port Y1 Y2 PW Y4 IF1/INTR1 Y8 IF2/IN2 φL16 IF1/ 2 Selection of IF input /Input port 0: Set input port 1: Set IF input port Set IF amplifier gain → set up “0” Selection IF input 0: Set IFin2 input 1: Set IFin1 input Note: At the time of an input port setup, the terminal becomes CMOS input type and be able to detect frequency by IF counter. Y1 Y2 MANUAL Y4 G0 Y8 G1 Selection of the gate time for frequency measurements (measurement time) G1 0 0 1 1 G0 0 1 0 1 Gate Time 1 ms 4 ms 16 ms 64 ms φL17 STA/ STP Frequency measurements automatic/manual mode switching bit 0: Automatic mode (measurement is performed with the above-mentioned gate time when in automatic mode) 1: Manual mode (starts/stops measurements with the STA/ STP bits) IF counter start/stop control bit 0: Counter stop 1: Counter start Y1 Y2 IF counter Split Y4 Prescaller IN Y8 φL39 OSCin pre-scaler input setups at IF counter 0: Set IFin terminal input 1: Set OSCin terminal input IF counter division operation setup 0: IF counter 20 bit operation 1: Inputs into 8 bits of IF counter higher ranks from INTR2 terminal. Note: When a prescaler input is set as IF counter input, at the time of a setup of a pulse-swallow system, prescsler;1/15•16 are fixed to 16 division, and this frequency is input into IF counter. Note: When a division operation setup of the IF counter is carried out, the counter of 8 bits of higher ranks is input from INTR2 terminal. However, only 8 bits of this higher rank cannot perform a gate setup by the auto mode. Reset of this counter is reset by setting up “1” to STA/ STP bit. 46 2006-03-02 TC9329AFAG/AFCG Y1 Y2 MANUAL Y4 OVER Y8 0 0: IF counter calculation value < 220 − 1 = 1: IF counter calculation value > 220 (overflow status) = 0: IF counter automatic mode 1: IF counter manual mode φK10 BUSY Overflow detection Operation mode 0: IF counter calculation ended Operation monitor 1: IF counter calculation in progress φK11 Y1 F0 20 LSB Y2 F1 Y4 F2 Y8 F3 φK12 Y1 F4 Y2 F5 Y4 F6 Y8 F7 φK13 Y1 F8 Y2 F9 Y4 Y8 φK14 Y1 Y2 Y4 Y8 φK15 Y1 Y2 Y4 Y8 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 219 IF counter data MSB Note: When it is set as IF input, in PLL off-mode, IF input amplifier is turned off in PLL-off mode. In using IF counter in PLL off-mode, it sets it as an input port (CMOS input). Note: The input amplifier un-chosen by IF1/ 2 bit. If input amplifier turns off, this input will serve as high impedance. (3) IF counter automatic mode A setup in the auto mode of IF counter is set “0” to MANUAL bit and gate time is set up according to the frequency band to measure. If the STA/ STP is set “1”, operation of IF counter will be started and the set-up clock in gate time will be input, and this number of input pulses is counted and it ends. An end of the calculation of IF counter can be judged by referring to BUSY bit. When more 220 pulses are input for a total numerical value, OVER bit is set to “1”. BUSY bit and OVER bit are judged “0” and the frequency input can be measured by taking in IF data of F0-F19. IF counter manual mode By internal time base (10 Hz etc.), it is used when gate time is controlled and it measures frequency. The manual mode is set “1” to MANUAL bit. At this time, a gate time setup serves as don't care. In STA/ STP bit is set to “1”, it starts calculation. In STA/ STP bit is set to “0”, it will end and calculation will take in data by the binary. (4) (5) An input setup and division setup of IF counter Usually, intermediate frequency (IF) Measurement is input into IFin1 or IFin2 terminal input, and measures this frequency. These terminals contain input amplifier and small-size width operation is possible. In addition, the following setup is possible to the input to IF counter, and use it for it according to specification. IF1/ 2 1 1 0 0 IF1/INTR1 IF2/IN2 IF Prescaller Ifin counter IN (φL3B6:Y1) Split 0 0 0 0 0 0 0 0 0 0 0 0 IF Input Setup IFin1 input (amplifier operation) INTR1 (IFin1) input (CMOS input) IFin2 input (amplifier operation) IN2 (IFin2) input (CMOS input) VHF mode (32 divided frequency) (Note) (Note) (Note) (Note) 1 0 * * 1 0 * * * * * 0 1 0 OSCin FM mode (32 divided frequency) input HF1/2 mode (16divided frequency) LF mode (input frequency) * * * * * * 0 1 1 1 CR Oscillation frequency (fCR) Input from PCTRin (HOLD ) terminal only 8 bits only of higher ranks. * * Note: Refer to the programmable counter item for the input frequency range at the time of prescaler input setup. 47 2006-03-02 TC9329AFAG/AFCG 2. IF Counter Circuit Configuration The IF counter circuit consists of an input amplifier, a gate time control circuit and a 12  8 bit binary counter. The OSCin prescaler and CR oscillation clocks can be input as IF counters. PW0/1 OSCin 0.01 µF 38 amplifier 1/2 1/15•16 To programmable counter PSC PW IFin1 0.01 µF 35 IF2/IN2 IF1/INTR1 fCR Prescaller IN CR oscillation circuit IF counter Split PrescallerIN, IFin F0~F11 12 bit binary counter F12~F19 8 bit binary counter OVER OVER IFin2 0.01 µF 36 Gate IF1/ 2 IN2 IN1 1 kHz Gate time control circuit Manual G0 G1 PCTRin 34 HOLD STA/ STP Note: All the binary counters of the IF counter operate in a standup. Note: During input of the OSCin into the IF counter, the 1/15･16 of the prescaler is fixed to a dividing frequency of 1/16. This dividing frequency becomes 1/32 in VHF/FM mode and 1/16 in HF mode. In LF mode, the OSC frequency can be input directly. IF counter input “1” Data set to STA/ STP bit BUSY bit 1 kHz Gate Binary counter input An example of IF counter auto mode operation timing 48 2006-03-02 TC9329AFAG/AFCG ○ LCD Driver The LCD driver uses a 1/4 duty and 1/2 bias drive method (62.5 Hz frame frequency). The common output outputs the VLCD, VLCD/2 (VEE) and the GND electrical potential, and the segment output outputs the VLCD and GND electrical potential. A combination of four common outputs and 18 segment outputs enables a maximum of 72 segments to be illuminated. The S11 to S18 segment output pins for the LCD driver can also be used as I/O ports on being set to function as I/O ports after system reset. The I/O port and segment output can be changed using bit units. All LCD output pins (COM1-S14) can be changed to output ports. The LCD driver is incorporates a constant voltage circuit (VEE = 1.5 V) for display purposes and a voltage doubler circuit (VLCD = 3.0 V). The voltage doubler (VDB), which raises the power supply voltage to twice its level, is used for the constant voltage circuit for the display (VEE). For this reason, it is even possible to stabilize the LCD display at a power supply voltage of 0.9 V. 1. LCD Driver Port Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 φL2D SEL1 Data select Segment-1 data Y1 Y2 Y4 Y8 Y1 Segment-2 data Y2 Y4 Y8 φL2E Y1 Y2 Y4 Y8 COM1 COM2 COM3 COM4 Y1 Y2 Y4 Y8 0 S1 1 2 S2 S3 φL2F Y1 Y2 Y4 Y8 COM1 COM2 COM3 COM4 Y1 Y2 Y4 Y8 0 S13 1 2 S14 S15 COM1 COM2 COM3 COM4 5 Y1 S11 Y2 S18 S12 Y4 S13 Y8 S14 Y8 S18 Segment data 0: Extinguished 1: Illuminated COM1 COM2 COM3 COM4 B S12 Change for segment and I/O port 0: I/O port 1: Segment output 6 Y1 Y2 Y4 Segment /IO select S15 7 S16 S17 Segment /IO select LCD display off control bit 0: All LCD display illuminated 1: All LCD display extinguished LCD off control bit 0: LCD output setting 1: Output port setting F DISP OFF LCD OFF OTB -UP * Note: If the DISP off-bit is set to “1”, common output and a segment output.are output at “L” level. Note: The segment data controls the illumination and extinguishing of segment lighting corresponding to the common output and segment output.. Note: During clock stop mode and about 100 ms after system reset, all the common and segment outputs are fixed at “L” level.. 49 2006-03-02 TC9329AFAG/AFCG The LCD driver control port consists of the segment data selection port and the segment data port. These ports are accessed using an OUT2 instruction for which [CN = DH~FH] has been specified in the operand. The segment data for the LCD driver is set through the segment data ports (φL2E, φL2F). The LCD display will be extinguished when the segment data port is set to “0”, and will be illuminated when the port is set at “1”. Also, the segment-2 data (φL2FF) specified with FH in the segment selection port becomes the DISP OFF bit and LCD OFF bit without setting of the segment data. It is possible to extinguish the entire LCD display using the DISP OFF bit without setting the segment data. If this bit is set to “1”, the common output and segment output are fixed to “L” level and the entire LCD display is extinguished. The segment data is retained at this point, and the previous display appears on the LCD if the DISP off bit is set to “0”. In addition, rewriting of segment data is possible during DISP OFF. Moreover, after reset and CKSTP instruction execution, the DISP off bit is set to “1”. The LCD off bit can set all LCD output terminals to serve as output ports. For the LCD display, this bit is set “0”. (→ Refer to the output port item) The terminals S11 to S18 terminal are used as I/O Ports. This control is done a segment/IO port select port (φL2F6, φL2F7). Set to “1”, the port will become segment output port and set to “0”, it will become an I/O Port. (→ Refer to the output port item) These data is divided and undirected setting by data selects port (φL2D). The data of a specification port to set a segment data port to beforehand is set, and the data port corresponding to it is accessed. A data select port is +1 increment whenever accessing data port (φL2E, φL2F). For this reason, after setting up a data selection port, it can set up continuously. Note: The data select port is +1 increment automatically by accessing φL2E, φL2F, φL3B, φK3B on I/O map. 2. LCD Driver Circuit Configuration COM1/OT1 COM2/OT2 COM3/OT3 COM4/OT4 S10/OT14 P8-0/S11 P8-1/S12 P9-2/S17 21 I/O-8•9 Port VLCD OFF 75 kHz/2 1 2 3 4 5 6 7 14 15 16 22 DIPS OFF 500 Hz Common output circuit Segment driver Segment data 75 kHz/2 VDD Power supply voltage Double voltage circuit (VDD × 2) Constant voltage circuit (VEE = 1.5 V) Voltage doubler circuit (VEE × 2) To A/D converter Constant voltage circuit (Vreg) 60 59 58 61 62 63 0.47 µF 0.1 µF VLCD VDB C2 C1 VEE C3 C4 64 0.1 µF 0.1 µF Note: If set to serve as an I/O port, this output port is Nch open drain. Note: In case of setting segment output as output port in setup “1” to VLCD OFF bit ,“H” level of all output becomses VLCD potential output. When “H” output is made into VDD remove the capacitor between C3/C4, and connect VLCD and VDD. Note: During clock stop mode and reset, the potential of VLCD/VEE/VDB becomes as VDD level. 0.1 µF 10 µF 50 2006-03-02 P9-3/S18 S1/OT5 S2/OT6 S3/OT7 TC9329AFAG/AFCG COM1 COM2 0 COM3 S1 S2 COM4 1 (S2) COM1 COM2 COM3 COM4 1 1 0 1 (S1) Example of segment data Segment data -1 (φL2E) Y1 Y2 Y4 Y8 COM1 COM2 COM3 COM4 1 Y1 0 Y2 1 Y4 0 Y8 Segment data selection (φL2D) DISP OFF 16 ms (62.5 Hz) 2 ms COM1 VLCD VEE GND VLCD COM2 VEE GND VLCD COM3 VEE GND VLCD COM VEE GND VLCD S1 GND VLCD S2 GND VLCD COM1-S1 (ON waveform) GND −VLCD VLCD COM2-S1 (OFF waveform) GND −VLCD The potential of the LCD driver waveform outputs the potential of the VLCD and GND, and the middle potential level that is 1/2 these values. 51 2006-03-02 TC9329AFAG/AFCG ○ Serial Interface (SIO1/2) There are two kinds of serial interface: SIO1 and SIO2. SIO1 is the serial I/O port, which transmits and receives data (4 bits or 8 bits) in synchronization with an internal or external serial clock. The SI, SO, and SCK terminals transmit and receive together with the extension LSI and microcomputer, etc. Interruption is issued when the serial interface stops operating. All outputs are Nch open drain outputs. SIO2 inputs 26-bit data serially in synchronization with an external serial clock. SIO2 has a function for decoding the input serial data, and interruption is issued for every input serial clock edge. 1. Control Port and Data Port of the Serial Interface Y1 Y2 Y4 Y8 φL22 edge SCK-INV SCK - I/ O SIO-ON Selection of the I/O port-3 and serial interface 0: I/O port-3 selection (P3-1~P3-3) 1: Serial interface SIO1 or SIO2 function selection SCK clock external/internal selection 0: External clock output 1: Internal clock output Inversion of the SCK clock signal 0: SCK clock output from “HZ” level 1: SCK clock output from “L” level Logical selection of serial data shift operation (SIO1/2 common) 0: Shift at the SCK rising edge 1: Shift at the SCK falling edge Y1 Y2 SO - I/ O Y4 8/ 4 bit Y8 SIO Select φL23 STA Permission operation of the serial interface 2 (SIO2) 0: SIO2 mode stop (Interrupts on end of SIO1 serial operation end.) 1: SIO2 mode operation (interrupt on SCK clock edge) Selection of the data length of serial data 0: 4 bit data 1: 8 bit data Selection of input and output of SO terminal 0: SO output 1: SI input Serial operation start and internal port reset 0: Don’t care 1: Reset COUNT, SIO F/F and the serial output data in the shift register. Serial operation is started when the internal SCK clock is selected. Reset SIO2 shift register data (26 bits) 52 2006-03-02 TC9329AFAG/AFCG φL24 Y1 SO0 Y2 SO1 Y4 SO2 Y8 SO3 φL25 Y1 SO4 Y2 SO5 Y4 SO6 Y8 SO7 Serial output data: The data set in these ports is output in serial format φK24 Y1 SI0 Y2 SI1 Y4 SI2 Y8 SI3 φK25 Y1 SI4 Y2 SI5 Y4 SI6 Y8 SI7 Serial input data: It is possible to load data input in serial format into data memory Y1 Y2 Y4 SIO F/F Y8 0 φK23 BUSY COUNT SIO start flag 0: SIO operations performed 1: SIO operations not performed SCK clock count detection 0: Clock count normal (SCK clock count is in multiple of four) 1: Clock count abnormal (SCK clock count is not in multiple of four) SIO operation monitor 0: SIO operations ended 1: SIO operation in progress Serial interface control and data are accessed with an OUT2 and IN2 instruction for which [CN = 2H~5H] has been specified in the operand. The serial interface terminal is used together with the I/O-3 P3-1, P3-2, and P3-3 terminals, and each of the I/O port-3 terminals are switched to operate as SI, SO and SCK terminals by setting the SIO ON bit to “1”. Note: All the serial interface inputs incorporate Schmidt circuits. Note: Since the SI (P3-1) terminal can be used as an I/O port even when the serial interface function is selected, it can be used for the SIO strobe signal, etc. If this terminal is used for serial input, be sure to enter “1” for the setting of the P3-1 output data and change it to the input state. 53 2006-03-02 TC9329AFAG/AFCG ① edge, SCK-INV, SCK-I/O bits The edge bit is setup the edge of a shift and the SCK-INV bit set up the input-and-output waveform of a shift clock. Serial clock (SCK) shift operation is performed on the rising edge if the edge bit is set to “0”, and on the falling edge if the edge bit is set to “1”. SCK-INV bit is set the bit of serial clock output from “H” or L”. In case of setting "0", it starts shift operation from “H” output, and setting “1”, it starts shift operation from “L” output. These bits perform serial operation in accordance with the settings as shown in the following table. Make the settings in accordance with the controlling serial format. SCK-I/O bit is setup the input-output of serial clock. Usually, when this product is used as a master, t “1” to SCK-I/O bit and then it used as serial clock output and in the case of a slave, set to “0” and then it used as serial input. SCK-INV = 0 SCKINV = 1 STA bit set as “1” SCK terminal SO terminal SI terminal BUSY SO0 SI0 1 SO1 SI1 2 SO2 SI2 3 SO3 SI3 4 SCK terminal SO terminal SI terminal BUSY Interrupt 1 STA bit set as “1” 2 SO0 SI0 SI1 SO1 SI2 3 SO2 SI3 4 SO3 edge = 0 Interrupt STA bit set as “1” SCK terminal 1 SO0 SI0 SI1 2 SO1 SI2 3 SO2 SI3 4 SO3 SCK terminal SO terminal SI terminal BUSY STA bit set as “1” 1 SO0 SI0 SO1 SI1 2 SO2 SI2 3 SO3 SI3 4 edge = 1 SO terminal SI terminal BUSY Interrupt Interrupt Note: The “H” level of the SCK/SO terminal indicates its pull-up status. In this period this status will be “HZ”. 54 2006-03-02 TC9329AFAG/AFCG ② 8/4 bit The 8/4 bit selects the length of the serial data. The length of the serial data is set at 4 bits when this bit is “0” and at 8 bits when this bit is “1”. If SIO is started when a serial clock is set as an internal clock, a clock (4 bits or 8 bits) will be continuously output by the state of this bit. STA bit set as “1” SCK terminal 1 2 3 4 5 6 7 8 SO terminal SO0 SO1 SO2 SO3 SO4 SO5 SO6 SO7 SI terminal SI0 SI1 SI2 SI3 SI4 SI5 SI6 SI7 BUSY Interrupt Example of serial operation for an 8 bit setting ③ SO - I/ O bit This bit sets the serial I/O for the SO terminal. The SO terminal outputs serial data when the bit is set at “0”, and is used for serial data input when this bit is set at “1”. This control is used as a serial bus system for outputting and inputting serial data through one terminal. Changing edge SCK terminal 1 2 3 4 1 2 3 4 SO terminal SO0 SO1 SO2 SO3 Set STA bit to “1” Set SO-I/O bit to “1” SI0 SI1 SI2 SI3 Set STA bit to “1” Set SO-I/O bit to “0” Example for serial input-output operation ④ Serial interface operation monitor The operational status of the serial interface is determined by referencing the BUSY, COUNT, and SIO F/F bits. As the BUSY bit becomes “1” during SIO operations, control data switching and serial data access is performed when the BUSY bit is “0”. It interrupts in falling of BUSY bit and a demand is published. The COUNT bit determines whether the sending/receiving of data has been performed in multiples of four. The bit is set to “0” if shift operation was performed in multiples of four, and to “1” if not. . The SIO F/F bit is set to “1” when the SCK terminal starts shift operation. Both COUNT bb it and SIO F/F bits are reset to “0” when “1” is set in the STA bit. These two bits are mostly used when the SCK terminal sets external clocks (slave mode). An external clock is input and it can be judged to be the information that serial data was transmitted and received whether operation was performed normally. Usually, since interruption is published, interruption processing performs a serial interface end. STA bit STA bit is used to start serial interface operation. Serial operation is started whenever the STA bit is set to “1”. If the STA bit is set to “1”, serial output data will be transmitted to a shift register, and the COUNT bit and SIO F/F bit will be reset. A serial clock is output for an internal SCK setting; and a state of waiting for the serial clock input will take effect in the case of an external setting. ⑤ 55 2006-03-02 TC9329AFAG/AFCG 2. Composition of the Serial Interface 1 (SIO1) STA SCK - I/ O Interrupt requirement COUNT BUSY SIO F/F Control circuit SCK-INV 45 SCK (P3-3) SO - I/ O edge 44 SO (P3-2) 8/ 4 bit 4 bit shift register 4 bit shift register 43 SI (P3-1) SO0 SO1 SO2 SO3 Serial output data SI0~SI3 SO4 SO5 SO6 SO7 -3 SI4~SI7 -2 -1 -0 I/O port-3 I/O control data Serial input data -3 -2 -1 -0 I/O port-3 data Srial interface 1 consists of a control circuit, a shift register, and an I/O Port. Note: The erminal can be used as I/O Port -3 (P3-1). Note: The shift memory contents for the data and serial input data are stored by the data memory. For this reason, the contents of the data set to serial output data and those of the serial input data are not in agreement. Note: All serial input terminals are the Schmitt input type. Note: The output of the SO terminal and the serial clock output of SCK terminal are Nch open drain outputs. For this reason, connect pull-up resistance. In addition, be sure to use a pull-up potential of 3.6 V or less. 56 2006-03-02 TC9329AFAG/AFCG 3. Serial Interface Timing of SIO1 Circuit The clock frequency output from the SCK terminal when the SCK clock is set as an internal clock is 37.5 kHz (Duty. = 50%). When the SCK clock is as an external input, a clock of a maximum of 200 kHz can be input. External clock: Tcyc = 5 µs min, Th = 2.5 µs min, TPLH/TPLL = 2 µs max Internal clock: Tcyc = 26.6 µs typ., Th = 13.3 µs typ., TPLH/TPLL = 2 µs max Tcyc SCK terminal TPLH/TPLL SO terminal SO0 SO1 SO2 SO3 a At internal clock 26.6 µs Th SI terminal a b c d Y8 Serial input Data port (φK24) Y4 Y2 Y1 × × × × SO3 SO2 SO1 SO0 a SO3 SO2 SO1 b a SO3 SO2 c b a SO3 d c b a ×: Unfixed STA bit Set “1” Interrupt Set “1” BUSY bit COUNT bit SIO F/F bit 57 2006-03-02 TC9329AFAG/AFCG 4. Serial Interface 2 (SIO2) control and Data Ports Note: ∀: EXOR (exclusive logic sum) 0 0 0 1 0 0 0 OFS9 = (INF14 ∀ INF13 ∀ INF12 ∀ INF11 ∀ INF10 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF1) 1 0 1 1 1 1 0 OFS8 = (INF13 ∀ INF12 ∀ INF11 ∀ INF10 ∀ INF9 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF1 ∀ INF0) 1 0 1 0 0 1 1 OFS7 = (INF14 ∀ INF13 ∀ INF9 ∀ INF8 ∀ INF5 ∀ INF4 ∀ INF0) 0 0 0 1 1 0 1 OFS6 = (INF15 ∀ INF14 ∀ INF11 ∀ INF10 ∀ INF8 ∀ INF7 ∀ INF5 ∀ INF2∀INF1) ∀CHK8 ∀CHK8 ∀CHK7 ∀CHK6 ∀CHK5 ∀CHK4 ∀CHK3 ∀CHK2 ∀CHK1 ∀CHK0 Other data 0 0 1 0 1 0 1 OFS5 = (INF15 ∀ INF14 ∀ INF13 ∀ INF10 ∀ INF9 ∀ INF7 ∀ INF6 ∀ INF4 ∀ INF1 ∀ INF0) 1 0 1 1 0 1 1 OFS4 = (INF15 ∀ INF11 ∀ INF10 ∀ INF9 ∀ INF8 ∀ INF6 ∀ INF4 ∀ INF2 ∀ INF1 ∀ INF0) 0 0 0 0 1 1 1 OFS3 = (INF13 ∀ INF12 ∀ INF11 ∀ INF9 ∀ INF8 ∀ INF7 ∀ INF4 ∀ INF2 ∀ INF0) 1 0 1 0 0 0 1 OFS2 = (INF15 ∀ INF14 ∀ INF13 ∀ INF8 ∀ INF7 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF2) 0 0 0 0 0 0 0 OFS1 = (INF15 ∀ INF14 ∀ INF13 ∀ INF12 ∀ INF7 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF1) 0 0 0 0 0 0 0 OFS0 = (INF15 ∀ INF14 ∀ INF13 ∀ INF12 ∀ INF11 ∀ INF6 ∀ INF5 ∀ INF4 ∀ INF3 ∀ INF2 ∀ INF0) ⎯ 194h 000h 1B4h 350h 168h 198h 0FCh 0 654B321 Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 φL2D SEL1 Data select Y1 Y2 Y4 Y8 φK3B 7 DEC0 DEC1 DEC2 DEC3 Y1SIO2 Y2 decode Y4 data INF0 8 INF1 INF2 Y8 INF3 Y1 Y2 Y4 SIO2 information data 1 Y8 INF4 9 INF5 INF6 INF7 Information data SIO2 information data 2 INF12 INF13 INF14 INF15 B Y1 Y2 Y4 SIO2 information data 4 Y8 OFS0/ CHK0 OFS1/ CHK1 OFS5/ CHK5 OFS9/ CHK9 OFS2/ CHK2 OFS6/ CHK6 OFS3/ CHK3 OFS7/ CHK7 C Y2 Y4 SY1 offset/Check data 1Y8 IO2 OFS4/ CHK4 D Y2 Y4 Y8 SY1 Offset/Check data 2 IO2 OFS8/ CHK8 Offset/Check data 0 0 E SIO2 Offset/Check data 3 Y1 Y2 Y4 Y8 φK3B SIO2 Data 8 Select * * * Change of offset/check data 0: Loading of offset data 1: Loading of check data 58 2006-03-02 TC9329AFAG/AFCG The data port of the serial interface 2 (SIO2) is constituted of 16-bit information data (φK3B8~B), 10-bit check data, 10-bit offset data and 4-bit decoding data (φK3B7). In 26-bit serial data, serial data of 16-bit are information data and 10-bit are check data. As shown in the above-mentioned table, the data that took the exclusive logic sum of each bit of 26-bit data turns into offset data. Furthermore, when the offset data is specialized in the above –mentioned, the data of 1~6h and Bh are output as 4-bit decoding data. Loading port of check data and offset data (φK3BC~E) are common and selection of loading is SIO2 data Select bit (φL3B8). If the bit is set to “0”, the offset data will be loaded and set to “1”, the check data will be loaded. If the data “1” is set to SIOon bit (φL22) and SIO Select bit (φL23), SIO2 will be in a permission state of operation. If the data “1” is set to STA bit (φL23), 26-bit shift registers are all reset and SI terminal input state will be serially input one by one by the shift register with the shift clock of SCK terminal clock. If SIO interruption is permitted at this time, interruption will be published with edge contrary to the shift edge of a shift clock. SI terminal and SO terminal can be changed to a serial input terminal by the SO-I/O bit, if the data “0” is set up, SI terminal will serve as a serial data and “1” will be set up, SO terminal will serve as a serial data input. If SI terminal is selected as a serial input, since SO terminal turns into a SIO1 serial output terminal, we recommend use of SO terminal to a serial input. These data is divided and indirect specified set up by the data select port (φL2D). The data of a specification port to set DAL address port to beforehand is set, and the data port corresponding to it is accessed. A data selection port is +1 increment by accessing of DAL address port (φKL3B). For this reason, after setting up a data selection port, it can set up continuously. Note: The data select port is +1 increment automatically by accessing φL2E, φL2F, φL3B and φK3B on I/O map. Control and serial data of the serial interface-2 is accessed using an OUT2 instruction for which [CN = 3H] has been specified in the operand. 5. Control and Serial Data of the Serial Interface 2 SIO Interruption SCK terminal SI terminal SI (P3-1) 43 SO (P3-2) 44 SCK (P3-3) 45 SO - I/ O INF16 INF15 INF14 CHK3 CHK2 CHK1 CHK0 CHK16 Check data Information data 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 bit shift register edge SIO interruption EXOR circuit for offset data detection OFS0~OFS9 (Offset data) Decode circuit DEC0~DEC3 (Decode data) Note: If the SI terminal is used for serial input, the SO terminal will serve as an SIO1 serial output. When using the SI terminal as a serial input, be sure to set the P3-1 output data to “1” and change it to the input state. Note: Serial input is inputt and shifted also SIO1 at the same time. CHK0 CHK1 CHK2 CHK3 CHK4 CHK5 CHK6 CHK7 CHK8 CHK9 INF0 INF1 INF2 INF3 INF4 INF5 INF6 INF7 INF8 INF9 INF10 INF11 INF12 INF13 INF14 INF15 59 2006-03-02 TC9329AFAG/AFCG ○ A/D Converter The A/D converter is used for measuring the strength of electric fields and the voltage of batteries with 4-channel 6-bit resolution. 1. A/D Converter Control Port and Data Port Y1 Y2 AD SEL1 Y4 AD SEL2 Y8 STA φL21 AD SEL0 A/D converter start bit A/D conversion is performed whenever this bit is set at “1”. A/D input selection SEL2 0 0 0 0 1 SEL1 0 0 1 1 SEL0 0 1 0 1 ADINPUT ADin1 ADin2 ADin3 ADin4 Vreg/2 * * φK20 Y1 AD0 Y2 AD1 Y4 AD2 Y8 AD3 φK21 Y1 AD4 Y2 AD5 Y4 BUSY Y8 0 A/D operation monitor LSB A/D Conversion data MSB 0: A/D conversion ended 1: A/D conversion in progress A/D converter is the serial comparison systems of 6 bit decomposition ability. An internal power supply (VDD) is used for the standard voltage of A/D conversion. The voltage dividing this power supply by 64 and the A/D input voltage are compared, and the data is output to the A/D conversion data port. The A/D conversion input follows the multiplex method for the four channels of the external input terminals (ADin1~ADin4 terminal) and the 1/2 potential of the Vreg terminal voltage, and is selected using bits AD SEL0 to AD SEL2. The A/D converter performs A/D conversion whenever the STA bit is set at “1”, and this ends after seven machine cycles (280 µs). The completion of A/D conversion is determined by reference to the BUSY bit, and the A/D conversion data is loaded into the data memory after conversion has finished. The result of A/D conversion is obtained through the following calculation. VDD × n − 0.5 64 (63 > n > 1) < A/D input voltage < VDD × == = = n + 0.5 64 (62 > n > 0) == (n is the A/D conversion data value. [decimal]) The Vreg/2 to the A/D input is used for battery detection. The Vreg potential is 1.5 V ± 0.15 V and 1/2 potential: 0.75 V ± 0.075 V of Vreg terminal voltage is chosen as A/D input, and VDD potential which is standard potential can be detected by carrying out A/D conversion of this potential. When VDD potential is 1.5 V, A/D conversion data is set to 20H, and if A/D data goes up and VDD potential serves as 0.75 V as VDD potential falls, it will serve as 3FH. If this function is used, the VregON bit is set to “1”. These controls are accessed with an OUT2/IN2 instruction for which [CN = 0H, 1H] has been specified in the operand. Note: If the VregON bit is set to “1” , the CPU operating consumption current is increased. The Vreg terminal also supplies power to the phase comparator. 60 2006-03-02 TC9329AFAG/AFCG 2. A/D Converter Circuit Configuration Comparator 46 ADin1 (P5-0) Sample hold 47 ADin2 (P5-1) VDD SEL0~2 BUSY 49 ADin4 (P5-3) 48 ADin3 (P5-2) AD0 ~ AD5 A/D conversion data latch A/D conversion data Control circuit Decoder STA BUSY VDB (VDD × 2 doubler power supply) R/2 R R R 3R/2 Constant voltage circuit 41 Vreg VregON BUSY To phase comparator The A/D converter consists of a 6-bit D/A converter, a comparator, an A/D conversion latch and control circuit. Since the 6-bit D/A converter and comparator part operate only when the BUSY bit is “1”, there is no A/D converter power when the A/D converter is inoperative. The doubler voltage (twice that of VDD) is used to drive the A/D converter part. Note: To the output data of I/O Port -5 (Nch open drain) corresponding to A/D input terminal to use set up “1” and use it by changing into an input state. 61 2006-03-02 TC9329AFAG/AFCG ○ Buzzer Output The buzzer output can be used to output tones and alarm tones to confirm key operations and the tuning scan mode. The buzzer type can be selected from a combination of four output modes and eight different frequencies. 1. Buzzer Control Port Y1 Y2 BF1 Y4 BF2 Y8 BEN BF2 0 Buzzer frequency selection data 0 0 0 1 1 1 1 BF1 0 0 1 1 0 0 1 1 BF0 0 1 0 1 0 1 0 1 Buzzer Frequency 0.625 kHz 0.75 kHz 1 kHz 1.25 kHz 1.5 kHz 2.08 kHz 2.5 kHz 3 kHz Duty 1/2 1/2 2/3 1/2 1/2 2/3 1/2 2/3 φL1A BF0 Buzzer output enable bit 0: Buzzer output fixed (at POL = “0”, “L” level, POL = “1”, “H” level) 1: Buzzer output enabled Y1 Y2 BM1 Y4 BUZR ON Y8 POL Buzzer output logic setup Buzzer output mode setup 0: Positive logic output. Buzzer frequency is output in positive logic from “L” level. 1: Negative logic output. Buzzer output is outputted in negative logic from “H” level. I/O port-4 and buzzer output selection 0: I/O port-4 (P4-0) selection 1: Buzzer output selection BM1 0 0 1 1 BM0 0 1 0 1 Continual output Staggered output 10 Hz intermittent output 10 Hz intermittent output with 1Hz intervals Buzzer Output Mode (mode A) (mode B) (mode C) (mode D) φL1B BM0 Ports P4-0 I/O are also used for buzzer output. In order to set it as a buzzer output, BUZR ON bit is set up “1” and it changes to a buzzer output by setting it as an output by the P4-0 I/O control port. After logic setting up of buzzer frequency, mode setup and a logic setup, buzzer enable bit is set up “1”, it outputs buzzer. At the time of condition setup, buzzer enable bit is setup “0”. In continual output mode (mode A), if the buzzer enable bit is set to “1”, the buzzer frequency will be output continuously; if “0” is set, the buzzer output will stop. In staggered output mode, whenever the buzzer enable bit is set to “1”, the buzzer is output and stopped at 50-ms intervals. Under a buzzer output (50 ms), if buzzer enable bit is set to “1” again, the buzzer is extended to 50 ms, being output for 100 ms. Given that a further extension of 50 ms to 150 ms is possible, the buzzer time can be set up easily. In the 10-Hz intermittent output mode (mode C), if the buzzer enable bit is set to “1”, a 50-ms buzzer output and 50-ms buzzer pause are carried out continuously. A setting of “0” stops the buzzer output. 62 2006-03-02 TC9329AFAG/AFCG 10 Hz intermittent output with 1 Hz intervals mode (mode D), if buzzer enable bit is set “1”, 50 ms buzzer output and 50 ms buzzer pause will carry out 500 ms output, after that 500 ms pause output of 50 ms buzzer output and the 50 ms buzzer pause is carried out again, and this operation is repeated. A set of “0” stops a buzzer output. At mode B, C, and D, a buzzer is in an output state, even if it sets “0” to buzzer enable bit and it makes it stop, the buzzer of 50 ms is output and stops. In addition, a buzzer output state can be judged according to the contents of a timer port. The timer port 10 Hz bit is “0”, buzzer is an output state and it is in a pause state at the time of “1”. The control of buzzer is accessed by an OUT 1 instruction for which [CN = AH, BH] has been specified in the operand. 2. Buzzer Circuit Configuration 10 Hz 1 Hz 0.625 kHz~3 kHz Multiplexer Buzzer output circuit 28 BUZR (P4-0) BF0~BF2 BEN BM0~BM1 3. Buzzer Output Timing Buzzer frequency “1” Data set to BEN bit “1” “0” 10 Hz Buzzer output (mode A) During a buzzer output, if “1” is set to BEN bit again, 50 ms extension will be carried out. 50 ms Buzzer output (mode C) 50 ms Period of buzzer frequency output Period of non-output Buzzer output (mode B) The output state in mode C Buzzer output (mode D) Period of non-output 500 ms 500 ms Period of output Note: When making the buzzer output function active, be sure to set P4-0 to the input state (by setting the I/O control port to “1”). Note: The change of buzzer frequency is updated in modifications of 10 Hz. 63 2006-03-02 TC9329AFAG/AFCG ○ Pulse Counter The pulse counter is an 8-bit up/down counter and detection of the number of clocks can be performed with PCTRin terminal (CMOS input type) used also HOLD terminal. It can use for the count and detection of a tape run. 1. Pulse Counter Control Port, Data Port Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 φL2D SEL1 Data select DAL Address data Y1 Y2 Y2 DA1 Y4 Y4 DA2 Y8 Y8 DA3 Y8 Y8 Y1 DAL Address data Y2 Y2 DA1 Y4 Y4 DA2 Y8 Y8 DA3 Y8 Y8 φL3B 0 1 Y DA01 φK3B 0 1 Y DA01 Y1 Y2 Y4 DAL Address data 1 Y1 Y2 Y4 DAL Address data 2 2 3 DAL Address data 3 Y1 Y2 Y4 DAL Address data 1 Y1 Y2 Y4 DAL Address data 2 2 3 DAL Address data 3 DAL Address data 4 DOWN POL 4 DAL Address data 4 PC0 4 PC1 PC2 PC3 * * Pulse counter control CTR OVER RESET RESET 5 Pulse counter data PC4 5 PC5 PC6 PC7 Data Pulse counter data OVER 6 0 0 0 Control * * Pulse counter control Pulse counter control • DOWN bit............................. Set up 8 bit up/down counter 0: Up count action 1: Down count action • POL bit................................. Set up input terminal (PCTRin terminal) counter input edge 0: Cont for input fallig edge 1: Count for input rising edge • • CTR RESET bit .................... whenever it set to “1”, a 8-bit rise down counter is reset. OVER RESET bit ................. whenever it set to “1”, OVER F/F is reset. PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 2 0 OVER 2 Pulse counter data 7 LSB MSB OVER F/F bit ................. Detected of overflow 0: Counter calculation value < 28 − 1 = 1: Counter calculation value > 28 = (Overflow status) 64 2006-03-02 TC9329AFAG/AFCG The pulse counter measures the number of pulses in the PCTRin input terminal. POL bit set up the clock edge of input terminal. If “0” is set, it will count in the falling of an input and it will set to “1”, it will count in the rising of an input. Usually, this bit is used fixed. DOWN bit sets up a up/down of 8-bit counter. If it sets to “0” and it will set to rise count operation and “1”, down count operation will be done. A change of a rise/down can be performed freely. However, if a clock pulse is input during change command execution, since it is canceled, be careful of this count. When 28 or more pulses are input, OVER F/F bit is set to “1”. When performing count operation of 8-bits or more, this OVER F/F are detected, and on a data memory, only the number of times of overflow is added and subtracted, and can correspond. After detection by this bit, and OVER RESET bit is set “1” and OVER F/F is reset. The CTR RESET bit resets only the 8-bit counter. The counter is reset whenever this bit is set to “1”. Counter data loaded data in a data memory by the binary. The control of pulse counter and data loading is accessed using the OUT3/IN3 instructions for which [CN = BH] have been specified in the operand and arranges in DAL address register port. This port is set up by data select port (φL2D), which specified the division. The data of a specification port to set beforehand is set and the data port corresponding to it can be accessed. The data select port is +1 increments whenever it accesses DAL address port (φL3B, φK3B). For this reason, after setting up a data selection port, it can set up continuously. Note: If POL bit is changed, a clock pulse may enter. Reset data by the reset bit after changing. Note: If data select port is +1 increments whenever it accesses φL2E, φL2F, φL3B, φK3B on the I/O map. 2. Pulse Counter Circuit Configuration OVER RESET CTR RESET To interrupt circuit DOWN F/F 8-bit up/down counter POL 34 HOLD (PCTRin) OVER F/F PC0~PC7 Note: It can be used together as pulse counter and interrupt function ( HOLD terminal input). 3. Example for Pulse Counter Timing CTR/OVER RESET execution Data set to pulse counter control bit DOWN bit Pulse width 1 µs (min) OVER RESET execution DOWN bit set to “1” PCTRin input Counter data 01H 02H 03H FFH 00H 01H 02H N N+1 N−1 N−2 OVER F/F 65 2006-03-02 TC9329AFAG/AFCG ○ Input and Output Port (I/O Port) There are 28 I/O ports available between I/O ports 1~5, 8-9 of which are used to input and output control signals. Of these 28 I/O ports, 12 I/O ports are CMOS type and 16 I/O ports are Nch open drain type. The combination function and the functional features of each I/O port are as follows. I/O Port Combination and Additional Function It is possible to set pull-up/pull-down. Structure I/O port-1 But, a combination of pull-up pull down is not available. P2-0~-2 CMOS ⎯ Prescaller PSC output I/O port-2 P2-3 I/O port-3* P3-0 P3-1~3 P4-0 I/O port-4 P4-1~3 I/O port-5 I/O port-8 I/O port-9 The potential to VLCD (3 V) can be input. I/O port 6-bit A/D converter analog input The potential to VDB (VDD × 2) can be input. Nch open drain ⎯ Serial interface input/output port Buzzer output Nch open drain CMOS Note: I/O port-3 terminal of * markis Nch high output buffer output and output-proof is 3.6 V (max). 1. I/O Port Control, I/O Port Data Y1 Y2 SEL2 Y4 SEL4 Y8 SEL8 φL2D SEL1 Data select Segment-2 data Y1 Y2 S12 Y4 S13 Y8 S14 Y8 Segment and I/O port changing S15 7 S16 S17 S18 Y8 -3 Y8 -3 Y8 -3 I/O control data (Input/output setting) 0: I/O port input 1: I/O port output S Y1 egment /IO select Y2 Y4 -0 8 Y1 -0 9 Y1 -0 A -1 -2 0: I/O port 1: Segment output φL2F 6 S11 Y1 Segment /IO select Y2 Y4 I/O control-1 Y2 Y4 -1 -2 I/O control-2 Y2 Y4 -1 -2 I/O control-4 Note: I/O-1, I/O-2, - - - - - is correspond to the name of P1-0~-3, P2-0~-3, - - - - - terminal. 66 2006-03-02 TC9329AFAG/AFCG Y1 Y2 -1 Y4 -2 Y8 -3 Y8 -3 Y8 -3 Y8 -3 Y8 -3 Y1 Y2 Y4 Y8 Port 1 Pull up I/O port data Control pull-down or pull-up of I/O port-1 0: Pull-up or pull-down off 1: Pull-up or pull-down on Y1 Y2 PD1 Y4 PD2 Y8 PD3 φLK30 φLK31 φLK32 φLK33 φLK34 -0 Y1 -0 Y1 -0 Y1 -0 Y1 -0 φL20 PD0 Y2 port-1 Y4 I/O -1 -2 Y2 port-2 Y4 I/O -1 -2 Y2 port-3 Y4 I/O -1 -2 Y2 port-4 Y4 I/O -1 -2 I/O port pull-down Note: PD0~PD3 is correspond to P1-0~P1-3 I/O port-5 φL3A φLK37 φLK38 -0 Y1 -0 -1 -2 -3 Y8 -3 Y2 port-8 Y4 I/O -1 -2 Control bit of pull-up/pull-down of I/O port-1 0: Set up pull-down 1: Set up pull-up I/O port-9 CMOS I/O port 0: I/O terminal “L” level 1: I/O terminal “H” level 0: I/O terminal “L” level 1: I/O terminal “H” level output terminal is high impedance Nch open drain I/O port The I/O port for the I/O ports is set with the contents of the I/O control data port. “0” is set in the I/O control data port bit which corresponds to the relevant port when setting the input port, and “1” is set when setting the output port. I/O control data port is arranged segment-2 data port and set up by data select port (φL2D), which specified the division. The data of a specification port to set beforehand is set and the data port corresponding to it can be accessed. The data select port is +1 increments whenever it accesses DAL address port (φL2F). For this reason, after setting up a data selection port, it can set up continuously. The output status of the I/O port is controlled by executing the OUT3 instruction for which corresponds to each I/O port during output port setting. The contents of the data currently output can also be loaded into the data memory by executing the IN3 instruction. In addition, the data read by the IN3 command is not surely in agreement with the data output by the OUT3 instruction and, in order to read the state of a terminal. The data input in the I/O port is loaded into the data memory by executing the IN3 instruction which corresponds to each I/O port during input port setting. The contents of the output latch will have absolutely no effect on the input data at this point. Nch open drain I/O ports have not I/O control data. When it makes an input, it is set “1” in I/O data port, the status becomes high impedance and read the input status into data memory by IN3 instruction. When output state becomes "L" level, it set “0” in I/O data port by OUT3 command. The execution of the WAIT instruction and CKSTP instruction is cancelled and CPU operations are re-started when the status of the I/O port input specified in the input port changes with I/O port-1. Also, the MUTE port and MUTE bit are forcibly set to “1” during changes in the input status when the MUTE port’s I/O bit is set at “1”. By control port of I/O port-1 pull-down, it sets up pull-down or pull-up status. It can set up a pull-down or pull-up for every terminal and if the port is set up “1”, it will become a pull-up or a pull-down. The pull-up/pull down control bit of I/O Port -1 perform a change of a pull-up and a pull down. The status is pull-down if the bit is set to “0”, and pull-up if the bit is set to “1” 67 2006-03-02 TC9329AFAG/AFCG Set up the pull-up and pull-down is used for key matrix configuration. I/O Port -1 with a pull down or a pull-up is considered for a usual I/O Port output as an input as an output of a key matrix, and a key matrix is constituted. It is able to constitute of the key matrix of a low noise by the following methods. In setting pull-down to I/O port-1, the output side of a key matrix is usually high impedance (input state), output and scan to “H” level on key loaded line, detected key input or non by loading input status of I/O port-1. In the case of a pull-up, “L” level is output and it detected on a key loading line. During executing of CKSTP instruction and WAIT instruction, the existence of this key input can also be judged and re-started. When re-starting at the time of CKSTP command execution, I/O Port -1 is used by changing into a pull-up state. For the clock stop mode, since the outputs of an I/O Port are output all “L” level, I/O Port -1 stands by in the state of a pull-up, and if a key is input, I/O Port -1 input will change and re-start. In this case, since the standby time of about 100 ms occurs as time lag after being canceled of a clock stop. Since release of WAIT instruction holds the output state, re-starting is possible by the method of both a pull-up and a pull down, and since there is no time lag from release, detection and operation of a key are quickly possible. Using these backup modes together can reduce consumption current. Since the input of I/O Port -1 is an inverter input, the usage that serves as middle potential cannot be done to this input. But, only at the time of execution of the input instruction, since an input will be in an ON state, even if middle potential is input, as for other I/O Port inputs, unusual consumption current does not occur. For this reason, use of the pull-up in potential lower than VDD potential, the three value output of an output level, etc. is possible. I/O Port -2, -4 terminals are the I/O Ports of CMOS structure, P2-3 terminal is the prescaler PSC output, P4-0 terminal is the buzzer output and P3-1-3 terminals are the serial interface serve a double purpose, respectively. I/O port-3, -5, -8~-9 are Nch open drain I/O port. I/O Port -3 uses VLCD (3 V) for the gate potential of Nch output buffer. For this reason, the output current by which power supply voltage was stabilized also in the time of low voltage can be obtained. This port can perform the input and output to 3.6 V. I/O port-5 is used as 6-bit A/D converter input. This port is able to input VDB potential (the potential to VDD × 2). I/O Port -8, -9 are using also LCD driver. VLCD (3 V) is used for the gate potential of an Nch open output buffer. For this reason, the output current by which power supply voltage was stabilized also in the time of low voltage can be obtained. These terminals can perform the input and output to VLCD (3 V). These terminals are set as the input of an I/O Port after reset. Note: The data select port is +1 increments automatically when it accesses φL2E, φL2F, φL3B, φK3B on the I/Omap. The following is an example of key input matrix circuit configuration. Without key input, it pulled-up and key is pushed, it input “L” level from souce side(I/O port-9). It is necessary to take into consideration the shift time to the pull-up of a key input from “L”. They are all about a key souce side at the time of WAIT instruction execution and “L” WAIT instruction can be lifted, whenever a key input will be pushed, if it stands by on the level. P1-3 P1-2 P1-1 P1-0 P9-3 P9-0 19 P9-2 P9-1 Example for key input matrix circuit P9-0 I/O port-1 Loaded into data Pull-up Pull-up Pushing of P9-3 and P1-1 keys VDD P1-3 26 P1-2 25 P1-1 24 P1-0 23 P9-3 22 P9-2 21 P9-1 20 Pull-up High impedance 68 2006-03-02 TC9329AFAG/AFCG ○ Register Port The G-register and data register outlined in the explanation on the CPU are also used as a single internal port. 1. G-register (φKL1D, φKL1E) This register addresses the data memory’s row addresses (DR = 04H~3FH) during execution of the MVGD instruction and MVGS instruction. The register is accessed using an OUT1/IN1 instruction for which [CN = DH~EH] has been specified in the operand. Moreover, if STGI instruction is used, data can be set to this register using a single instruction. Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction are executed and are ineffective when any other instruciton is executed. Moreover, this register is not affected by MVGD instruction and MVGS instruction. Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 3FH in the G-register. (DR = 00H~3FH) Note: For a reason with a RAM capacity of 256 words, this product will become unfixed if 10H-3FH is specified to be G-register. Note: Writing and read-out are possible for this register. Please evacuate and return in a data memory if needed at the time of interruption. φKL1D Y1 G0 Y2 G1 Y4 G2 Y8 G3 φKL1E Y1 G4 Y2 G5 Y4 Y8 * * G5 0 G4 0 0 0 G3 0 0 0 G2 1 1 1 G1 0 0 1 G0 0 1 0 DR 04H 05H 06H Data memory row address specification STGI instruction I0 I1 I2 I* I3 Transmit I4 I5 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0FH 10H 1 1 1 1 1 1 1 1 1 1 0 1 3EH 3FH 69 2006-03-02 Can’t specified in this area TC9329AFAG/AFCG 2. Data Register (φKL3C~φKL3F), DAL Address Register (φKL3B0~φKL3B3) and Control Bit φL2D Y1 SEL1 Y2 SEL2 Y4 SEL4 Y8 SEL8 0 1 Data select 2 φL/K3B Y1 Y2 Y4 Y8 Y8 φL/K3A Y1 DAL Y2 (data) → DA/0 Y4 /0 Y8 /0 φY1 DAL address1 L/K3B Y2 Y4 DA0Y1 DALY2 DA2Y41DA3Y8 A1 アドレス DA4Y1 DALY2 DA6Y41DA7Y8 A5 アドレス DA8 DAL アドレス 1 A9 DA10 DA11 3 DA12 DA13 */0 */0 0: DAL ADD3, (r) instruction select 1: DAL DA instruction select DAL address register DA13 DA12 MSB DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 LSB DAL instruction indirect specification Whenever it sets “1”, the contents of a data register are transmitted to DAL address register. φKL3F Y1 d15 MSB Y2 d14 Y4 d13 Y8 d12 φKL3E Y1 d11 Y2 d10 Y4 d9 Y8 d8 φKL3D Y1 d7 Y2 d6 Y4 d5 Y8 d4 φKL3C Y1 d3 Y2 d2 Y4 d1 Y8 d0 LSB Data register 16-bit data It transmits 16 bits of program memories by DAL instruction b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Program memory 16-bit data 70 2006-03-02 TC9329AFAG/AFCG The data register is 16-bit register for which load the program memory data when the DAL instruction is executed. The contents of this register are loaded into the data memory in 4-bit units with the execution of the OUT1/IN1 instructions for which [CN = CH~FH] has been specified in the operand. This register can be used for loading LCD segment decoding operations, radio band edge data and the data related to binary to BCD conversion. The DAL address register (DA) is 14-bit register for which specified the program memory indirectly when the DAL instruction is executed. There are 2 kinds of operation methods of DAL instruction. The control is selected by DAL bit. When DAL bit is set “0”, ADDR3 (6 bit) of the operand and contents of general register (r) becomes the reference address of program memory and when DAL bit is set “1”, 14 bit of DAL address register becomes reference address. At the time of setting DAL bit is “0” and execution of DAL instruction, only program memory area (0000H~03FFH) becomes reference area and DAL bit is set “1” and execution of DAL instruction, all program memory area (0000H~3FFFH) becomes reference area. If (DATA) → DA bit is set to “1”, it can transfer from the contents of data register to 14 bit DAL address register by executing of single instruction. The contents of DAL address register are accessed the data in 4-bit units with the execution of the OUT3/IN3 instruction for which [CN = BH] have been specified in the operand. DAL address register port is setup by data select port (φL2D) for which divides and indirect specified. The data of a specification port to set beforehand is set and the data port corresponding to it is accessed. Data select port is +1 incremented whenever is accessed this port(φL3B, φK3B). For this reason, after setting up a data selection port, it can access continuously. DAL bit and (DATA) → DA bit are accessed with the execution of OUT3/IN3 instruction for which [CN = AH] has been specified in the operand. Note: DAL address register becomes effective only execution of DAL instruction when setting “1” and becomes unrelated at the time of other instruction execution. It does not have the influence on this register by DAL instruction. Note: For this product have 4 k step of ROM Capacity, If 1000H - 3FFFH is specified to be DAL address register and DAL instructiion is executed, the contents of a data register will become unfixed. Note: It’s possible to write in and read out for data register and DAL address register. Please evacuate and return in a data memory if needed at the time of interruption. Note: It’s no action when (DATA) → DA bit is set “0” . When it accesses to φK3A, it only read out only the DAL bit. (The other bit is “0”.) 3. Carry F/F (Ca flag, φKL1C) This is set when either Carry or Borrow are issued in the result of calculation instruction execution and is reset if neither of these is issued. The carry F/F is accessed with OUT1/IN1 instructions for which [CN = CH] have been specified. For this reason, evacuation and a return of the carry F/F at the time of interruption can be performed easily. Carry F/F is written in a data memory by IN1 instruction at the time of evacuation, it is evacuated, and the data evacuated by OUT1 instruction is transmitted to carry F/F from a data memory at the time of a return. Y1 Y2 Y4 Y8 φL/K1C CA flag */0 */0 */0 Carry F/F 71 2006-03-02 TC9329AFAG/AFCG ○ Timer Port The timer is equipped with 100 Hz, 10 Hz and 2 Hz F/F bits and is used for counting clock operations and tuning scan mode, etc. 1. Timer Port Y1 Y2 Timer Y4 Y8 φL26 2 Hz F/F The 10 Hz, 100 Hz and under 1 kHz bits are reset whenever “1” is set. The 2 Hz is reset whenever “1” is set. Reset port Y1 Y2 Y4 Y8 φK26 2 Hz F/F 10 Hz 100 Hz Timer The timer ports are accessedusing an OUT2 instruction for which [CN = 6H] has been specified in the operand. 2. Timer Port Timing The 2-Hz timer F/F is set with the 2 Hz (500 ms) signal and is reset by setting “1” in the 2-Hz F/F of the reset port. This bit is usually used as a clock counter. The 2-Hz timer F/F can only by reset with the 2-Hz F/F of the reset port, and incorrect counts will be output and correct timers not acquired if not reset within a 500 ms cycle. 2 HzF/F output 2 HzF/F reset execution t < 500 ms 2 Hz clock 500 ms t The 10 Hz and 100 Hz timers are output to 10 Hz and 100 Hz bits will respective cycles of 100 ms and 10 ms and a pulse of duty 50%. Counters at 1 kHz or below will be reset whenever the reset port’s timer bit is set at “1”. 100 Hz 5 ms 10 ms 10 Hz 50 ms 100 ms 72 2006-03-02 TC9329AFAG/AFCG ○ Output Port (Both as LCD Driver Terminal) There are 14-output ports of 14 CMOS type. These output ports are used as LCD driver and changed output port by VLCD OFF bit. If VLCD OFF bit is set to “1”, this port becomes output port. The output data to output port is used as segment data port-1 (φL2E). This data is accessed with OUT2 instruction for which [CN = EH] is specified and is setup by data select port ( φL2D) for which divides and indirect specified as same as segment data. The data of a specification port to set a segment data port to beforehand is set, and the data port corresponding to it is accessed. The data select port is +1 incremented whenever is accessed segment data port-1 (φL2E). For this reason, after setting up a data selection port, it can set up continuously. Output data is +1 increment with OT count UP bit by executing one instruction. For this reason, it can be used as an address signal output when using an external memory etc. Output buffer capability can be changed at the time of an output setup. If OTB-UP bit is set “0”, it becomes low output buffer (same performance of LCD output driver) and set “1”, it becomes high output buffer. During output port setup, this bit is usually set to “1”. The power supply of this output port is used VLCD doubler potential, when using it as an output port, remove for the capacitor of VLCD doubler potential (between C3-C4) and connect with VDD terminal and use VLCD terminal. Note: Data select port is +1 increment automatically whenever is accessed φL2E, φL2F, φL3B, φK3B on I/O map. Note: If set “0” to OT count UP bit, it’s not performed count-up. Note: Refer to LCD driver item. φL2D Y1 SEL1 Y2 SEL2 Y4 SEL4 Y8 SEL8 0 1 Data select 2 φL2E Y1 Y2 Y4 Y8 Y8 If VLCD off-bit is set “1”, segment output data will turn into output port data. φY1 Output port data L/K3B Y2 Y4 OT1Y1 DALY2 OT3Y41OT4Y8 OT2 アドレス OT5Y1 DALY2 OT7Y41OT8Y8 OT6 アドレス OT9 OT10アドレス 1 DAL OT11 OT12 3 OT13 OT14 * * φL3A Y1 Y2 Y4 OT count up Y8 In this bit whenever is set “1”, all the OT1 - OT14 is count up (+1). OT1 bit is lower bit; OT14 bit is upper bit and count up from OT1 bit. φL2FF Y1 Y2 Y4 OTB -UP Y8 Control bit for output port (OT) buffer performance 0: Low output buffer 1: High output buffer At set up output port, it set to “1”. 73 2006-03-02 TC9329AFAG/AFCG ○ MUTE Output This is a dedicated 1-bit CMOS output port for muting control purposes. 1. MUTE Port φL/K18 Y1 MUTE Y2 I/O Y4 POL Y8 HOLD Control by change of HOLD input state changing 0: Even if HOLD input status changes, MUTE output does not change. 1: By changing HOLD input status, MUTE bit is set to “1”. MUTE output polarity control 0: Positive logic: MUTE bit output without modification 1: Negative logic: MUTE bit inversed and output Control selection by changes in the I/O port-1input status 0: MUTE output not amended when changes in I/O port-1input status exist 1: MUTE bit set at “1” when changes in I/O port-1 input status exist MUTE output setting 0: MUTE output set at “L” level during positive logic and “H” level during negative logic. 1: MUTE output set at “H” level during positive logic and “L” level during negative logic. This port is accessed using an OUT1/IN1 instruction for which [CN = 8H] has been specified in the operand. The MUTE output is used for muting control. This function prevents noise from being generated during linear circuit switching when band is performed with the I/O port-1 or HOLD input. This control is set up according to the contents of I/O bit and HOLD bit. POL bit sets up the logic of MUTE output. Please set up according to specification. 2. Circuit Composition of MUTE Output MUTE bit S POL bit 32 MUTE I/O bit Signal of input change of I/O Port -1 Reset signal HOLD bit Signal of HOLD input terminal changing 74 2006-03-02 TC9329AFAG/AFCG ○ Test Port Access is performed using an OUT1 instruction for which [CN = FH] has been specified in the operand, and an OUT2 instruction for which [CN = 6H] has been specified in the operand. “0” is usually set with the program. φL1F Y1 #0 Y2 #1 Y4 #2 Y8 #3 φL26 Y1 Y2 Y4 Y8 #4 Test port Test port If the following data is set as test port from #3 to #0, various signals can be made to output from MUTE terminal. #3 0 0 0 #2 0 0 0 #1 0 0 1 #0 0 1 0 Data 0 1 2 MUTE Terminal Output MUTE output Programmable counter frequency Reference frequency Prohibition CR VCO frequency Prohibition ~ ~ ~ ~ 0 1 0 1 5 ~ ~ ~ ~ 1 1 1 1 ○ Application to an Emulator Chip If TEST terminal is supplied “H” level (test mode), the device operates as an emulator chip. Three kinds of test modes are abailable and can constitute a soft development tool by using three devices. Radio operation can be checked by the connection between this soft development tool and IC for tuners, performing soft development. Please refer to TC932AFAG/AFCG software development tool specifications of a development tool. ~ F ~ 75 2006-03-02 TC9329AFAG/AFCG Absolute Maximum Ratings (Ta = 25°C) Characteristics Supply voltage Voltage doubler boosting voltage Output voltage 1 (N-channel open drain) Output voltage 2 (N-channel open drain) Output voltage 3 (N-channel open drain) Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VDB VO1 (*) VO2 (*) VO3 (*) VIN PD Topr Tstg Rating Unit V V V V V V mW °C °C −0.3~4.0 −0.3~4.0 −0.3~4.0 −0.3~VDB + 0.3 −0.3~VLCD + 0.3 −0.3~VDD + 0.3 100 −10~60 −65~150 *: VO1: P3-0~P3-3 pin VO2: P5-0~P5-3 pin VO3: P8-0~P8-3, P9-0~P9-3 pin Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = 1.5 V) Characteristics Range of operating supply voltage Symbol VDD1 VDD2 Range of memory retention voltage VHD Test Circuit Test Condition Under CPU operation Under PLL operation (*) (*) Min 0.9 0.9 0.75 Typ. ~ ~ ~ Max 1.8 1.8 1.8 V Unit V ⎯ ⎯ ⎯ ⎯ ⎯ Crystal oscillation stopped (CKSTP instruction executed) (*) PLL operation (VHF mode), at input FMin = 230 MHz Under CPU operation only (PLL off, display turned on, Vreg Off) Under CPU operation only (PLL off, display turned on, Vreg On) In Hard wait mode, (PLL off, crystal oscillator operating only) At Soft wait executed, (PLL off, CPU stopped) Under CPU accelerated operation, (CR oscillator operation, PLL off, display on) Crystal oscillation stopped (CKSTP instruction executed) (*) Crystal oscillation fXT = 75 kHz VDD = 1.1~1.8 V, Ta = −10~60°C IDD1 ⎯ ⎯ 6 10 mA IDD2 40 80 IDD3 Operating current IDD4 ⎯ ⎯ 50 ⎯ µA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.8 20 40 IDD5 30 ⎯ IDD6 250 500 Memory retention current Crystal oscillation frequency Crystal oscillation start-up time CR oscillation frequency IHD fXT tst fCRW 0.1 75 1.0 µA kHz s MHz ⎯ 1.0 1.2 ⎯ 1.0 *: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C 76 2006-03-02 TC9329AFAG/AFCG Voltage Doubler Boosting Circuit Characteristics Doubled voltage Doubled voltage output current Doubled voltage reference voltage Constant voltage for phase comparator Constant voltage temperature characteristic Power supply output current for phase comparator Doubled voltage Doubled voltage output current Symbol VDB IDB VEE Vreg Dv Ireg VLCD ILCD Test Circuit Test Condition GND reference (VDB) VOH = VDB − 0.1 V (VDB) GND reference (VEE) GND reference (Vreg) GND reference (VEE) VOH = Vreg − 0.1 V (Vreg) (Note 1) GND reference (VLCD) VOH = VLCD − 0.1 V (VLCD) (Note 1) (*) Min Typ. VDD ×2 Max Unit V ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −50 1.35 1.35 ⎯ ⎯ 1.65 1.65 −200 1.50 1.50 µA V V mV/°C ― −50 2.7 −5 −200 3.0 ⎯ ⎯ 3.3 µA V −50 −200 ⎯ µA *: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C Note 1: The “H” level output current of the pin using the Vreg/VLCD power supply must not exceed the power supply (doubled voltage: VDB) output current. Programmable Counter/IF Counter Operating Frequency Range Characteristics OSCin (VHF mode) OSCin (FM mode) Symbol f VHF f FM f HF1 OSCin (HF mode) f HF2 OSCin (LF mode) IFin1, IFin2 PSC transfer delay time f LF f IF tpd Test Circuit Test Condition VIN = 0.1 Vp-p, VDD = 0.9~1.8 V VIN = 0.1 Vp-p, VDD = 0.9~1.8 V VIN = 0.1 Vp-p, VDD = 0.9~1.8 V VIN = 0.1 Vp-p, VDD = 0.9~1.8 V VIN = 0.1 Vp-p, VDD = 0.9~1.8 V VIN = 0.1 Vp-p, VDD = 0.9~1.8 V CL = 15 pF, VDD = 1.1~1.8 V (PSC) (*) (*) (*) (*) (*) (*) (*) Min 80 60 3.0 1.0 0.5 0.3 Typ. ~ ~ ~ ~ ~ ~ Max 230 130 30 MHz 10 8 12 400 MHz MHz ns Unit MHz MHz ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ― ― *: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C Programmable Counter/IF Counter Input Amplitude Range Characteristics OSCin (VHF mode) OSCin (FM mode) OSCin (HF mode) OSCin (LF mode) IFin1, IFin2 Symbol V VHF V FM V HF V LF V IF Test Circuit Test Condition Same as for f VHF Same as for f FM Same as for f HF1~2 Same as for f LF Same as for f IF (*) (*) (*) (*) (*) Min 0.1 0.1 0.1 0.1 0.1 Typ. ~ ~ ~ ~ ~ Max 0.6 0.6 0.6 0.6 0.6 Unit Vp-p Vp-p Vp-p Vp-p Vp-p ― ― ― ― ― *: Guaranteed when VDD = 0.9~1.8 V, Ta = −10~60°C 77 2006-03-02 TC9329AFAG/AFCG LCD Common Output/Segment Output (COM1~COM4, S1~S18) Characteristics Symbol Test Circuit Test Condition VLCD = 3 V, VOH = VLCD − 0.3 V (COM1~COM4) VLCD = 3 V, VOH = VLCD − 0.3 V (S1~S18) VLCD = 3 V, VOL = 0.3 V (COM1~COM4) VLCD = 3 V, VOL = 0.3 V (S1~S18) No load (COM1~COM4) Min Typ. Max Unit IOH1 “H” level Output current IOH2 IOL1 “L” level IOL2 Output voltage 1/2 level VBS ⎯ ⎯ ⎯ ⎯ ⎯ −0.10 −0.05 0.10 0.05 1.35 −0.20 −0.10 0.30 0.15 1.5 ⎯ ⎯ ⎯ ⎯ 1.65 V mA Output Port, I/O Port (OT1~OT14, P8-0~P8-3, P9-0~P9-3) Characteristics Symbol Test Circuit Test Condition VLCD = 3 V, VOH = VLCD − 0.3 V (Note 2, except I/O port) VLCD = 3 V, VOL = 0.3 V VIH = VLCD, VIL = 0 V (P8-0~P8-3, P9-0~P9-3) (P8-0~P8-3, P9-0~P9-3) (P8-0~P8-3, P9-0~P9-3) Min Typ. Max Unit Output current “H” level “L” level IOH3 IOL3 ILI ⎯ ⎯ ⎯ ⎯ ⎯ −1.5 1.5 −3.0 3.0 ⎯ ⎯ ±1.0 VDD mA Input leak current “H” level Input voltage “L” level ⎯ VDD × 0.8 0 ⎯ ~ ~ µA VIH1 VIL1 V VDD × 0.2 Note 2: The “H” level output current is the current when the pin power supply is fixed. Make sure that pins using the Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB) output current. 78 2006-03-02 TC9329AFAG/AFCG I/O Port (P1-0~P5-3) Characteristics Symbol Test Circuit Test Condition VDD = 1.5 V, VOH = VDD − 0.2 V (I/O port P2, P4) VDD = 0.9 V, VOH = VDD − 0.2 V (I/O port P2, P4) VDD = 1.5 V, VOL = 0.2 V (except I/O port P3) VDD = 0.9 V, VOL = 0.2 V (except I/O port P3) VDD = 0.9~1.8 V, VOL = 0.2 V (I/O port P3) VIH = VDD, VIL = 0 V (I/O port P1, P2, P4) VIH = 3.6 V, VIL = 0 V (I/O port P3) VIH = VDB, VIL = 0 V (I/O port P5) except I/O port 3 I/O port 3 Min Typ. Max Unit IOH4 “H” level IOH5 Output current IOL4 “L” level IOL5 IOL6 ⎯ −0.4 −0.8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −0.04 −0.2 ⎯ ⎯ ⎯ ⎯ ±1.0 ±1.0 ±1.0 VDD 3.6 VDD × 0.2 120 200 kΩ kHz V mA 0.5 0.1 1.0 1.0 0.3 2.0 ⎯ ⎯ ⎯ VDD × 0.8 VDD × 0.8 ⎯ ⎯ ⎯ ~ ~ ~ 60 Input leak current ILI ⎯ ⎯ µA VIH2 “H” level Input voltage “L” level Input pull-down resistor SCK clock external input frequency VIH4 VIL2 RIN1 fSIO ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ W hen P1-0~P1-3 are set to pull-down or pull-up W hen I/O port P3-3 are set to serial clock input 0 30 ⎯ ⎯ MUTE Output Characteristics Symbol IOH4 “H” level Output current “L” level IOL5 IOH5 IOL4 Test Circuit Test Condition VDD = 1.5 V, VOH = VDD − 0.2 V VDD = 0.9 V, VOH = VDD − 0.2 V VDD = 1.5 V, VOL = 0.2 V VDD = 0.9 V, VOL = 0.2 V Min Typ. Max Unit ⎯ ⎯ ⎯ ⎯ −0.4 −0.04 0.5 0.1 −0.8 −0.2 1.0 0.3 ⎯ ⎯ ⎯ ⎯ mA HOLD , INTR1/2, IN1/2 Input Port, RESET Input Characteristics Input leak current “H” level Input voltage “L” level VIL3 Symbol ILI VIH3 Test Circuit Test Condition VIH = VDD, VIL = 0 V Min Typ. Max Unit ⎯ ⎯ ⎯ ⎯ VDD × 0.8 0 ⎯ ~ ~ ±1.0 VDD µA ⎯ ⎯ V VDD × 0.2 Note 2: The “H” level output current is the current when the pin power supply is fixed. Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB) output current. 79 2006-03-02 TC9329AFAG/AFCG A/D Converter (ADin1~ADin4) Characteristics Analog input voltage range Resolution Conversion total error Analog input leak Symbol VAD VRES Test Circuit Test Condition Min 0 Typ. ~ 6 Max VDB Unit V bit LSB ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VDD = VDB, VIH = VDB, VIL = 0 V ⎯ ⎯ ⎯ ⎯ ±1.0 ±1.0 ⎯ ILI ±0.5 ⎯ µA DO Output Characteristics “H” level “L” level Output off leak current Symbol IOH4 IOL4 ITL Test Circuit Test Condition Vreg = 1.5 V, VOH = Vreg − 0.2 V (Note 2) 0.5 1.0 Vreg = 1.5 V, VOL = 0.2 V VDD = 1.5 V, VTLH = 1.5 V, VTLL = 0 V Min Typ. Max Unit Output current ⎯ ⎯ ⎯ −0.4 −0.8 ⎯ ⎯ ±100 mA ⎯ ⎯ nA Others Characteristics Input pull-down resistance XIN amp. feedback resistance XOUT output resistance Symbol RIN2 RfXT ROUT Test Circuit Test Condition (TEST) (XIN-XOUT) (XOUT) VHF mode, FM mode (OSCin) HF mode, LF mode (OSCin) (IFin1, IFin2) Min 5 Typ. 10 20 4 200 600 600 Max 30 Unit kΩ MΩ kΩ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 100 300 300 ⎯ ⎯ 400 1200 1200 Input amp. feedback resistance RfIN1 ⎯ RfIN2 kΩ ⎯ Note 2: The “H” level output current is the current when the pin power supply is fixed. Make sure that pins using Vreg/VLCD power supply do not exceed the power supply (doubled voltage: VDB) output current. 80 2006-03-02 TC9329AFAG/AFCG Package Dimensions W eight: 0.32 g (typ.) 81 2006-03-02 TC9329AFAG/AFCG Package Dimensions Note: Lead type SN-Ag W eight: 0.26 g (typ.) 82 2006-03-02 TC9329AFAG/AFCG 83 2006-03-02