TC9446FG

TC9446FG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9446FG Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio TC9446FG is the various digital signal processor for decoding. It contains the decode processing program which embraced encoding signals, such as Dolby Digital (AC-3)/Pro Logic (Note 1), MPEG2 audio and DTS (Note 2). Decoding of Dolby Digital or MPEG2 audio is made with a single chip. Moreover, an external memory can be connected to the TC9446FG to decode DTS. Features • • Dolby digital (AC-3) or MPEG2 audio decode Acceptable bit rate upto 640 kbps Audio interface 4 output port, 2 input port (2 port of LRCK and BCK) DIR (digital audio interface receiver) built-in DIT (digital audio interface transmitter) built-in DIR and DIT are available upto 96 kHz sampling of 2 channel • • • Operating clock: DLL oscillator upto 6th times for DSP clock Instruction cycle: 20 ns/1 instruction at 50 MIPS operation DSP Processor: 24 bit × 24 bit + 51 bit multiplier and adder, 51 bit ALU Data bus: 24 bit × 3 Data RAM: 12 k word Coefficient ROM: 4 k word Program ROM: 12 k word Program RAM: 128 word • • MCU interface: Serial interface or I2C bus interface Others It is possible to connect external RAM, 256 k or 1 M SRAM External interruption input terminal Flag input terminal: 4 inputs P-QFP100-1420-0.65Q Weight: 1.57 g (typ.) General-purpose output port: 8 outputs (The ports can be used as interrupt outputs to MCU and logic control outputs.) incorrect operation detect • • • Operating Voltage: 3.0 ± 0.3 V In CMOS structure and high-speed processing 100 pin flat package design Note 1: “Dolby”, “Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. Note 2: “DTS” and “DTS Digital Surround” are registered trademarks of Digital Theater Systems, Inc. Note 3: Since this product has a weak terminal in serge voltage, please advise handling it enough. 1 2005-09-28 TC9446FG Pin Connection AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 VDD AD0 VDD VSS IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 OE CE VSS PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 VDDDL LPFO DLON DLCKS SCKO VSSDL SCKI VSSX XO XI VDDX 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 WR VSS LOCK CKO VSSA CKI AMPO AMPI PLON VDDA PDO TSTSUB2 TSTSUB1 TC9446FG 40 39 38 37 36 35 34 33 32 31 FCONT TSTSUB0 VSS RX TEST3 TEST2 TXO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 RST MILP LRCKOA BCKOA 2 LRCKOB BCKOB MICK MIACK LRCKA BCKA MICS LRCKB BCKB MIMD MIDIO VDD IRQ VSS FI0 FI1 FI2 FI3 TEST0 TEST1 SDO0 SDO1 SDO2 SDO3 SDI0 SDI1 2005-09-28 TC9446FG Block Diagram Program Timing ROM 4 k word × 3 XRAM RAM 128 word Program Instruction control 40 bit Instruction Decoder X bus Y bus Bus switch 4 k word YRAM 4 k word CROM 4 k word ERAM 4 k word X pointer register Y pointer register C pointer register Address operator ×2 SCKO SCKI DLL DLON LPFO IRQ I bus Interrupt Register X0, X1, X2 Y0, Y2, Y3 External SRAM interface 3 17 8 CE , OE , WR ADn IOn SDIn SDOn LRCK/BCK RX LOCK RST MIMD MICS MILP MIDIO MICK 2 4 Audio Interface MX MY MAC MZ AX ALU AY General output port Flag 8 POn DIR A1 4 FIn A0 A2 A3 DIT TXO Timer Round/Limiter Round/Limiter MCU interface MIACK 3 2005-09-28 TC9446FG Pin Functions Pin No. 1 2 3 Symbol RST MIMD I/O I I Description of Pin Functions Reset signal input terminal (L: reset, H: normal operation) Mode select input for MCU interface (L: serial, H: I C bus) 2 Remarks Pull-up resistor, Schmitt input Pull-down resistor, Schmitt input MICS MILP MIDIO MICK MIACK FI0 FI1 FI2 FI3 IRQ VSS LRCKA BCKA SDO0 SDO1 SDO2 SDO3 LRCKB BCKB SDI0 SDI1 VDD LRCKOA BCKOA TEST0 TEST1 LRCKOB BCKOB TXO TEST2 TEST3 RX VSS I I I/O I O I I I I I Chip select input for MCU interface Latch pulse input for MCU interface Data input and output for MCU interface Clock input for MCU interface Acknowledge output for MCU interface Flag input 0 Flag input 1 Flag input 2 Flag input 3 Interruption input Digital ground LR clock input-A for audio interface Bit clock input-A for audio interface Data output-0 for audio interface Data output-1 for audio interface Data output-2 for audio interface Data output-3 for audio interface LR clock input-B for audio interface Bit clock input-B for audio interface Data input-0 for audio interface Data input-1 for audio interface Digital power supply LR clock output-A for audio interface Bit clock output-A for audio interface Test input-0 (L: test, H: normal operation) Test input-1 (L: test, H: normal operation) LR clock output-B for audio interface Bit clock output-B for audio interface SPDIF output Test input-2 (L: test, H: normal operation) Test input-3 (L: test, H: normal operation) SPDIF input Digital ground Schmitt input Schmitt input Schmitt input/ Open-drain output Schmitt input 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Pull-down resistor, Schmitt input ⎯ I I O O O O I I I I Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input Schmitt input ⎯ O O I I O O O I I I Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Schmitt input ⎯ 4 2005-09-28 TC9446FG Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Symbol TSTSUB0 FCONT TSTSUB1 I/O I O I I O Description of Pin Functions Test sub input-0 (L: test, H: normal operation) Frequency control output for VCO circuit Test sub input-1 (L: test, H: normal operation) Test sub input-2 (L: test, H: normal operation) Phase detect signal output Analog power supply Clock selection input (L: external clock, H: VCO clock) Amplifier input for Low pass filter Amplifier output for Low pass filter External clock input Analog ground DIR clock output VCO lock output Digital ground Write signal output for external SRAM Enable signal output for external SRAM Chip enable signal output for external SRAM Digital power supply Data I/O-7 for external SRAM Data I/O-6 for external SRAM Data I/O-5 for external SRAM Data I/O-4 for external SRAM Data I/O-3 for external SRAM Data I/O-2 for external SRAM Data I/O-1 for external SRAM Data I/O-0 for external SRAM Digital ground Address output-0 for external SRAM Address output-1 for external SRAM Address output-2 for external SRAM Address output-3 for external SRAM Address output-4 for external SRAM Address output-5 for external SRAM Address output-6 for external SRAM Address output-7 for external SRAM Digital power supply Address output-8 for external SRAM Address output-9 for external SRAM Address output-10 for external SRAM Address output-11 for external SRAM Address output-12 for external SRAM Address output-13 for external SRAM Remarks Pull-up resistor, Schmitt input Tri-state output Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Tri-state output TSTSUB2 PDO VDDA PLON AMPI AMPO CKI VSSA CKO LOCK VSS WR OE CE VDD IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 VSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VDD AD8 AD9 AD10 AD11 AD12 AD13 ⎯ I I O I Pull-up resistor, Schmitt input ⎯ O O ⎯ O O O ⎯ I/O I/O I/O I/O I/O I/O I/O I/O Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor ⎯ O O O O O O O O Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor ⎯ O O O O O O Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor 5 2005-09-28 TC9446FG Pin No. 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Symbol AD14 AD15 AD16 VSS PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 VDDDL LPFO DLON I/O O O O Description of Pin Functions Address output-14 for external SRAM Address output-15 for external SRAM Address output-16 for external SRAM Digital ground General output port-0 General output port-1 General output port-2 General output port-3 General output port-4 General output port-5 General output port-6 General output port-7 Power supply for DLL circuit Low pass filter output for DLL circuit DLCKS pin “L” 93 DLCKS I “L” “H” “H” 94 95 96 97 98 99 100 SCKO VSSDL SCKI VSSX XO XI VDDX O ASP clock output Ground for DLL circuit External system clock input Ground for crystal oscillator Crystal oscillator output Crystal oscillator input Digital power supply DLON pin “L” “H” “L” “H” DLL clock setting SCKI input (DLL = off) 4th times of XI clock 3rd times of XI clock 6th times of XI clock Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Remarks Pull-up resistor Pull-up resistor Pull-up resistor ⎯ O O O O O O O O ⎯ O I ⎯ I ⎯ O I ⎯ 6 2005-09-28 TC9446FG Description of Operation 1. Micro Controller Interface The TC9446FG can perform transmission and reception of serial data with a micro controller in the serial mode or the I2C mode. MIMD terminal performs a change in the serial mode and the I2C mode, and input and output of data are performed at MSB first. The use terminal and the function in the serial mode and the I2C mode are shown in Table 1. The bit composition of a 24 bit command is shown in Table 2. Note 4: This data sheet shows the general control method, refer to the program explanation data of an attached sheet for a detailed command list, the control method, etc. Table 1 Terminal MICS MILP MIDIO MICK MIACK Use Terminal and Function in the Serial Mode and the I C Mode Serial Mode (MIMD = L) Functions Chip selection signal input Latch pulse signal input Data input/output Clock input Acknowledge signal output and out of control detection output I C Mode (MIMD = H) Functions Not used (fixed “L”) Not used (fixed “L”) Data input/output (SDA) Clock input (SCL) Out of control detection output 2 2 Transmission Mode Input/Output Input (3-5 V) Input (3-5 V) Input (3-5 V)/Output (3 V) Input (3-5 V) Output (3 V) Note 5: MIDIO terminal needs pull-up resistance for the terminal exterior because of an open-drain output. 2 When using it by I C bus, pull-up resistance is required also for MICK terminal. Note 6: The addresses of an I C bus are write-in address 3Ah and read-out address 3Bh. 2 Table 2 Bit Assign 23-8 7 6 5 4 16 bit address Bit Composition of 24 Bit Command Functions Remarks Refer to the command list of the program explanation data sheet Starting the incorrect operation detection output by “1” Starting the program RAM boot by “1” Setting the soft reset ON by “1” Setting the read by “1” “0h”; a word Starting the incorrect operation detection output Starting the program RAM boot Setting the soft reset Setting the Read/Write (R/W) 3-0 Setting the number of words for transmission ↓ “Fh”; 16 words 7 2005-09-28 TC9446FG 2. Data Transmission Format 2-1. Serial Mode Setting 2-1-1. Data Transmission Format in the Serial Mode A data transmission format in the serial mode is shown in Figure 1. After the data transmission at the time of the serial mode sets MICS signal to “L”, fundamentally, it checks that MIACK signal is “L” and transmits a 24 bit command at MSB first. However, it cannot transmit at the time of MIACK signal = “H”. Then, the word set up by the 24 bit command which the Read or Write (R/W) of 24 bit data of a number (1-16 word) is performed, and, finally, MICS signal is set to “H”. However, since there is a term when MIACK signal after transmission is set to “H” in a 24 bit command, at the time of Read, command transmission back also needs to check that MIACK signal is set to “L”. Transmission data (1 to 16 words) MICS MIACK MILP MICK MIDIO COMMAND (24 bit) DATA-1 (24 bit) DATA-16 (24 bit) Figure 1 Serial Mode Data Transmission Format 2-1-2. Data Transmission Method in the Serial Transmission Mode 1) Program boot and a program start As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h. Therefore, in order to operate TC9446FG, it needs to interrupt and a program needs to be booted to a vector address. In addition, a program load needs to be continuously performed to an interruption vector address to store a program in 000Ah-007Fh. In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24 bit command transmitted after reset need to be set to “H”. (command = 000060h) And, after command transmission, program data (40 bit) is divided into 20 bit of a higher rank/low rank, and it transmits by the low-rank stuffing of 24 bit data in the order of a higher rank (20 bit) and a low rank (20 bit). Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of words and MICS is set to “H”, program boot will complete it. In addition, the write-in address of program boot always starts from 0000h. A start of a program carries out and transmits the soft reset bit in a 24 bit command to “L”, and is performed by setting MICS to “H”, without performing data transmission. The procedure of program boot and a program start is shown in Figure 2. 8 2005-09-28 TC9446FG Reset of Hardware (or reset of software by command) MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Write of the 24 bit command (program boot = 000060h) Setting “H” for bit of program boot and soft reset bit. Write of program data (higher rank 20 bit at address 0000h) Write of program data (low rank 20 bit at address 0000h) Program data is 20 bit lower assign. It is possible to do the program boot for address of 007Fh maximum. Write of program data (higher rank 20 bit at address 0007h) Write of program data (low rank 20 bit at address 0007h) MICS = “H” It finished the program boot. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Write of the 24 bit command (soft reset off = 000000h) MICS = “H” Program starting Figure 2 Procedure of Program Boot and Program Start 9 2005-09-28 TC9446FG 2) Write of 24 bit data The number of words of data written in while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446FG during program operation is set up. And, 24 bit data of the number required after transmitting a 24 bit command of words is written in. The procedure of the write of 24 bit data is shown in Figure 3. MICS = “L” Checking of MIACK = “L” (at the MIACK = “L”, waiting for becoming to MIACK = “L”) Write of 24 bit command (write of data = xxxx0xh) Setting of 16 bit address and umber of the transmission word. Write of 24 bit data (1) It is possible to write the 24 bit data until 16 word maximum. Write of 24 bit data (2) Write of 24 bit data (n) MICS = “H” It finished to write the data Figure 3 Procedure of Write of 24 Bit Data 10 2005-09-28 TC9446FG 3) Read-out of 24 bit data The number of words of data read while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “H”, when reading data of TC9446FG from a MCU during program operation is set up. And, after transmitting a 24 bit command, MIACK = “L” is checked and 24 bit data of the required number of words is read. MIACK = “L” is checked after command transmission for waiting to set data which should be read to data buffer. The procedure of read-out of 24 bit data is shown in Figure 4. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Write of 24 bit command (read of data = xxxx1xh) A 16 bit address and a transmission word number are set up. Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) Read of 24 bit data (1) It is possible to read out the 24 bit data until 16 word maximum. Read of 24 bit data (2) Read of 24 bit data (n) MICS = “H” It finished to read of the data Figure 4 Procedure of Read-Out of 24 Bit Data 11 2005-09-28 TC9446FG 4) ON/OFF of soft reset The case where a program is started after program boot, and in restarting a program, it performs ON/OFF of soft reset. ON/OFF of soft reset are performed by carrying out and transmitting the bit of the soft reset in a 24 bit command to “H” (ON) and “L” (OFF). Since data with which ON/OFF of soft reset follow a command is not required, it is made into MICS = “H” after 24 bit command transmission. In addition, in order to return from a incorrect operation state, when turning ON soft reset, a 24 bit command can be transmitted irrespective of the state of MIACK signal. The procedure of ON/OFF of soft reset is shown in Figure 5. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) It is possible to transmit the command data of soft reset ON at MIACK = “H”. Soft reset ON: Bit = “1”. Soft reset OFF: Bit = “0”. Transmission of 24 bit command (soft reset ON/OFF = 0000x0h) MICS = “H” Soft reset ON/OFF Figure 5 Procedure of ON/OFF of Soft Reset 12 2005-09-28 TC9446FG 5) Incorrect operation detection Incorrect operation detection of the internal program of TC9446FG can be made to perform by setting the incorrect operation detection start bit in a 24 bit command to “H”. As for this incorrect operation detection start bit, the reversal output only of the case of MICS terminal = “H” is carried out from MIACK terminal. And, since this incorrect operation detection start bit is periodically cleared by “L” when an internal program is operating normally, MIACK terminal at the time of MICS terminal = “H” is set to “H” from “L”. However, since it will stop being cleared if an internal program becomes a incorrect operation state, as for MIACK terminal at the time of MICS terminal = “H”, the state of “L” will continue. Thus incorrect operation detection of a program is attained by supervising MIACK terminal at the time of MICS terminal = “H”. Moreover, although it checks that MIACK terminal is “L” after setting MICS terminal to “L” in case a MCU starts access to TC9446FG, MCU can judge that an internal program is a incorrect operation state, when the state of MIACK = “H” continues. In addition, when a incorrect operation state is detected, it can return from a incorrect operation state by initializing by transmitting the soft reset command which the reset terminal was set to “L” or was mentioned above. The procedure of incorrect operation detection is shown in Figure 6. MICS = “L” Checking of MIACK = “L” (waiting for becoming to MIACK = “L” at the MIACK = “H”) When not set to “L” with “H”, it is the state of incorrect operation. Transmission of 24 bit command (starting the incorrect operation detection = 000080h) It starts the incorrect operation detection by “1”. MICS = “H” MIACK = “L” Program makes to clear the incorrect operation detection bit MIACK = “L” is continue at incorrect operation, as detection bit isn’t cleared. MIACK = “H” Figure 6 Procedure of Incorrect Operation Detection 13 2005-09-28 TC9446FG 2-2. I C Mode Setting 2 2 2-2-1. Data Transmission Format in I C Mode The foundations of a data transmission format in the I2C mode are shown in Figure 7. Fundamentally, the data transmission at the time of the I2C mode checks that ACK bit is set to “L”, after making I2C Address (write = 3Ah) to transmission. However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I2C Address (3Ah). I2C Transmit 24 bit command after Address transmission. And, at the time of data Write of TC9446FG, Write of 24 bit data of the number (1-16 word) of words set up by 24 bit command is performed from a MCU, and, finally, END Condition is transmitted. Moreover, it checks that transmit I2C Address (read = 3Bh) from TC9446FG at the time of Read to a MCU, without performing END Condition after 24 bit command transmission, and ACK bit is set to “L”. However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I2C Address (3Bh). The word set up by 24 bit command after checking that ACK bit is “L”. Although Read of 24 bit data of a number (1-16 word) is performed, as for the inside of Read, a MCU needs to set ACK bit to “L” for every 8-bit Read data. And, only ACK bit added to the last 8 bits is set to “H”, and STOP Condition is transmitted. Moreover, at the time of transmission of only a 24 bit command which does not perform R/W of data, END Condition is transmitted after 24 bit command transmission. In addition, in TC9446FG, polling of the access demand from a MCU is carried out every about 6 ms at the time of decode processing. Therefore, R/W of data from a MCU need to be performed at the interval of 6 ms or more. At the time of Write-in, Read-out and a command only shows the transmission format to Figure 7 to Figure 10. SDA SCL I2C Address (3Ah) R/W ACK DATA Hi (8 bit) ACK DATA Mid (8 bit) ACK DATA Lo (8 bit) ACK I2C Address START Condition 24 bit DATA (1 word to 16 word) STOP Condition Figure 7 Data Transmission Format in the I C Mode 2 14 2005-09-28 TC9446FG (3Ah) START I2C Address 24 bit COMMAND W A COMMAND (H) A COMMAND (M) A COMMAND (L) A All of ACK are returned to MCU from TC9446FG The interval of 6 ms or more is required until next START. DATA (H) A 24 bit Write DATA (1 word to 16 word) DATA (M) A DATA (L) A STOP Figure 8 Format at Time of Write (3Ah) START I2C Add. 24 bit COMMAND W A COMMAND (H) A COMMAND (M) A COMMAND (L) A These of ACK are returned to MCU from TC9446FG START (3Bh) I2C Add. 24 bit Read DATA (1 word to 16 word) R A RD (H) A RD (M) A RD(L) A STOP These of ACK are retarned to TC9446FG from MCU The interval of 6 ms or more is required This ACK is MCU set up at “H”. Figure 9 Format at Time of Read (3Ah) START I2C Address 24 bit COMMAND W A COMMAND (H) A COMMAND (M) A COMMAND (L) A All of ACK are returned to MCU from TC9446FG. STOP Figure 10 Format Only a Command at the Time of Transmission. 15 2005-09-28 TC9446FG 2-2-2. The Data Transmission Method in I C Mode 1) Program boot and a program start As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h. Therefore, in order to operate TC9446FG, it needs to interrupt at least and a program needs to be booted to a vector address. In addition, a program load needs to be continuously performed to an interruption vector address to store a program in 000Ah-007Fh. In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24 bit command transmitted after reset need to be set to “H”. (command = 000060h) And after command transmission, program data (40 bits) is divided into 20 bits of a higher rank/low rank, and it transmits by the low-rank stuffing of 24 bit data in the order of a higher rank (20 bits) and a low rank (20 bits). Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of words and END Condition is transmitted, program boot will complete it. In addition, the write-in address of program boot always starts from 0000h. A start of a program is performed by carrying out and transmitting the soft reset bit in a 24 bit command to “L”, and transmitting END Condition, without performing data transmission. The procedure of program boot and a program start is shown in Figure 11. 2 16 2005-09-28 TC9446FG Reset of hardware (or reset of software by command) START Condition At the time of ACK = “H”, it resumes from START Condition. Transmission of I C Address (3Ah) 2 Checking of ACK bit = “L” Write of 24 bit command (program boot = 000060h) The bit of program boot and soft reset is set to “H”. Write of program data (higher rank 20 bit at address 0000h) Write of program data (low rank 20 bit at address 0000h) Program data is 20 bits of low-rank stuffing. Boot is possible to the address of a maximum of 007Fh. Write of program data (higher rank 20 bit at address 0007h) Write of program data (low rank 20 bit at address 0007h) START Condition The completion of program boot. STOP Condition At the time of ACK = “H”, it resumes from START Condition. Transmission of I C Address (3Ah) 2 Checking of ACK bit = “L” Write of 24 bit command (soft reset OFF = 000000h) STOP Condition Program starting Figure 11 Procedure of Program Boot and Program Start 17 2005-09-28 TC9446FG 2) Write of 24 bit data The number of words of data written in while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446FG during program operation is set up. And, 24 bit data of the number required after transmitting a 24 bit command of words is written in. In addition, completion of internal taking in of write-in data requires the time of about 6 ms of the maximum from END Condition. Therefore, access of a next MCU needs to keep the term for about 6 ms after END Condition transmission. The procedure of the write of 24 bit data is shown in Figure 12. START Condition At the time of ACK = “H”, it resumes from START Condition. Transmission of I C Address (3Ah) 2 Checking of ACK bit = “L” Write of 24 bit command (write of data = xxxx0xh) A 16 bit address and a transmission word number are set up. Write of 24 bit data (1) It is possible to Write in the 24 bit data until 16 word maximum. Write of 24 bit data (2) Write of 24 bit data (n) STOP Condition It is data write-in completion after STOP Condition transmission and within about 6 ms term. Figure 12 Procedure of Write of 24 Bit Data 18 2005-09-28 TC9446FG 3) Read of 24 bit data The number of words of data read while data required for the 16 bit address in a 24 bit command is set up and R/W bit is set to “L”, when reading data of TC9446FG from a MCU during program operation is set up. And, after transmitting a 24 bit command, I2C Address is set to 3Bh after the term progress for about 6 ms, and it transmits with START Condition. Then, 24 bit data of the required number of words is read. Although ACK bit of a data Read term needs to give “L” from a MCU, it needs to set only ACK bit added to last 8 bit data to “H”. This is because the Basra in of SDA where TC9446FG are the master is opened wide and a MCU can transmit STOP Condition. In addition, the term progress for about 6 ms after command transmission is for waiting to set data which should be read to data buffer of TC9446FG. The procedure of read-out of 24 bit data is shown in Figure 13. START Condition At the time of ACK = “H”, it resumes from START Condition. Transmission of I C Address (3Ah) 2 Checking of ACK bit = “L” Transmission of 24 bit command (read of data = xxxx1xh) A 16 bit address and a transmission word number are set up. A term is stood by for about 6 ms. START Condition At the time of ACK = “H”, it resumes from START Condition. Transmission of I C Address (3Bh) 2 Checking of ACK bit = “L” Read of 24 bit data (1) It is possible to Write in the 24 bit data until 16 word maximum. Read of 24 bit data (2) Read of 24 bit data (n) The last ACK bit is set to “H”. STOP Condition It finished to read of the data Figure 13 Procedure of Read-Out of 24 Bit Data 19 2005-09-28 TC9446FG 4) ON/OFF of soft reset The case where a program is started after program boot, and in restarting a program, it performs ON/OFF of soft reset. ON/OFF of soft reset are performed by carrying out and transmitting the bit of the soft reset in a 24 bit command to “H” (ON) and “L” (OFF). Since data with which ON/OFF of soft reset follows a command is not required, STOP Condition is transmitted after 24 bit command transmission. In addition, in order to return from a incorrect operation state, when turning ON soft reset, it is also possible to transmit a 24 bit command irrespective of the state of ACK bit. The procedure of ON/OFF of soft reset is shown in Figure 14. START Condition Transmission of I C Address (3Ah) 2 At the time of ACK = “H”, it resumes from START Condition. However, it is possible to disregard and carry out command transmission of the ACK bit at the time of a reckless run. Checking of ACK bit = “L” Transmission of 24 bit command (soft reset ON/OFF = 0000x0h) Soft reset ON: Bit = “1”. Soft reset OFF: Bit = “0”. STOP Condition Soft reset ON/OFF Figure 14 Procedure of ON/OFF of Soft Reset 5) Incorrect operation detection Incorrect operation detection of the internal program of TC9446FG is judged by the existence of the reaction to the access demand from a MCU. Therefore, R/W of data need to be performed from a MCU to TC9446FG at the interval of about 6 ms or more. ACK bit is set to “L”, when the following access demand opens the interval of about 6 ms or more and is performed, since R/W of data were performed between about 6 ms back to the access demand from a MCU when TC9446FG were operating normally. However, if TC9446FG become a incorrect operation state, even if it is going to stop receiving the access demand from a MCU, it is going to open the interval of about 6 ms or more and MCU is going to make it access again, it will become a state ACK bit is “H” continued. A MCU can perform incorrect operation detection by seeing this ACK bit. That is, since TC9446FG are in a incorrect operation state when it is “H” fixation, even if ACK bit passes about 6 ms or more, ACK bit is disregarded, soft reset is turned ON, and each setup of TC9446FG is performed again. 20 2005-09-28 TC9446FG 3. Setting Procedure Until it Starts Decode Program Operation Setting procedure until it starts operation of the decode program built in TC9446FG is shown below. First, 10 words program data is transmitted in the program boot mode after release of the power-on reset at the time of a power-supply injection. However, when there is a program required for others, program data of a maximum of 128 words can be transmitted. And, if the command of soft reset-off is transmitted, a program will begin to operate and decode will be started by transmitting addresses of the write-in command shown in an attached sheet (the program explanation data) after that 9 words of 0000h-0008h. Procedure until it starts operation of a decode program to Figure 15 is shown. Power ON reset Program boot Soft reset OFF Write-in command transmission. (9 word of 0000h to 0008h) (9 word of continuing from 0000h are transmitted.) Starting of decode Figure 15 Procedure to Decode Program Operation Start Note 7: Internal RAM is cleared, in order to muting for output, after transmitting a setup of command 0003h “decode off” in the case of AC-3 decoder program. Please transmit following data after checking that ACK is set to “L” from “H”, since such a case has the time for about 23 ms (maximum) in this processing. If processing of the internal RAM clearance by the “decode off” command is completed, it will return at the waiting time for 1 or less ms. In addition, according to the kind of decode program, please transmit following data after checking that ACK is set to “L” from “H”, since the waiting time which the data transmission at the time of decode on/off takes differs. 21 2005-09-28 TC9446FG 4. Read/Write of Command Write and a read of command change with decode programs built in. For details, please refer to program explanation data. 5. Digital Audio Interface (DIR/DIT) 1) A setup of DIR/DIT The digital reception recovery (DIR) for the audio interfaces and the abnormal-conditions transmission (DIT) based on CEI “IEC958 standard” and the JEITA “CP-1201 standard” are built in. DIR corresponds to the input of 96 kHz sampling (2 channels). Please refer to program explanation data about the various contents of a setting of DIR/DIT. VCO oscillation and PLL Since VCO oscillation circuit is built in, PLL circuit can consist of connecting an external low path filter simply. VCO oscillation circuit and the example of composition of PLL are shown in Figure 16. 2) (A) Crystal/XI clock Setting of command register 48 LOCK 47 CKO Clock output VDDA VSSA 45 CKI 44 AMPO 43 VDD/2 42 PLON 41 VDDA Phase detector Frequency detector Demodulation circuit 40 PDO 37 FCONT 34 RX 31 TXO DIT output DIR input VSSA VSS AMPI L: CKI/XI clock H: VCO clock VSSA External clock input (when CKI does not use, it connect to VSS line.) XI/CKI selector Timing generator Selector 46 VCO circuit Modulation circuit Figure 16 VCO Oscillation Circuit and Example of Composition of PLL 22 2005-09-28 TC9446FG 3) DIR input part When you input a signal into DIR, please be sure to input, as shown in Figure 17 through a signal amplification circuit, a 5 V-3 V conversion circuit, etc. 3V COAXIAL RX VSS VSS 5V OPTICAL VSS 5 V-3 V level shifter 34 DIR (3 V input) Figure 17 DIR Input Part 4) Lock detection When VCO circuit locks LOCK terminal and it is operating, “H” level is outputted and “L” level is outputted at the time of the Ann lock. At the time of the Ann lock, latch operation of reception recovery data and channel status is stopped, and it holds last value. If the state of a no error continues the time of the following table, LOCK terminal will be set to “H” level and a reception recovery will be started. Period of error LOCK Terminal Data of Receiving Demodulation Channel Status tB tA Figure 18 Internal Operation Timing at Time of Error Table 3 Release Time After the Lock Detection Operation Data of Receiving Demodulation tA (ms) 384.0 278.6 256.0 128.0 Channel Status tB (ms) 288.0 209.0 192.0 96.0 Sampling Frequency (kHz) 32 44.1 48 96 23 2005-09-28 TC9446FG 5) Non-inputted detection When existence of the edge of the input signal from RX terminal is detected and there is no fixed time edge, VCO oscillation operates by free run. Since VCO oscillation frequency and CKO terminal output are set to about 80 MHz, please change it to an external clock automatically by the internal program at the time of less inputting, or choose XI input by setup of command register. Table 4 Non-Inputted Judgment Time of Input Signal Sampling Frequency (kHz) 32 44.1 48 96 Time of Last Edge (ms) approx. 1000 approx. 750 approx. 700 approx. 350 6) Miss lock detection By comparing the input signal and the oscillation frequency from RX terminal, a Miss lock is detected and the signal for escaping from a miss lock is outputted from FCONT terminal. Higher than objective frequency VDD FCONT Output VSS Hiz Objective frequency Lower than objective frequency Figure 19 Miss Lock Detection Operation Timing 6. DSP Part Clock Generating Circuit It is the circuit which generates a clock required in order to operate a decode program. DLL circuit can generate the DLL clock of a crystal oscillation clock. DLL circuit and a crystal oscillation circuit block are shown in Figure 20. XI (A) CKI/XI selector 99 DLL oscillator (*3, *4, *6) 98 XO 96 SCKI Selector 94 SCKO Clock output VSSX External clock input (when the SCKI does not use, it connect to VSS line.) Internal DSP clock Selector 93 DLCKS 92 DLON 91 LPFO VSS VSS Figure 20 Crystal Oscillation Circuit and DLL Circuit Block 24 2005-09-28 TC9446FG DLL oscillation clock can be chosen with DLCKS terminal and DLON terminal, as shown in Table 5. Table 5 Setup of DLL Circuit DLCKS Terminal (93 pin) “L” “L” “H” “H” DLON Terminal (92 pin) “L” “H” “L” “H” DLL Oscillation Clock SCKI input (DLL = off) XI input * 4th times XI input * 3rd times XI input * 6th times When DLCKS terminal and DLON terminal are “L”, the external clock input from SCKI terminal is chosen. An internal clock of operation is a half divided clock of the DLL clock, and processing speed can correspond a maximum of 75 MIPS. The clock outputted from DLL circuit should choose a crystal oscillation clock to be set to less than 150 MHz. The example of DLL clock by the crystal oscillation clock is shown in Table 6. Table 6 Crystal Oscillation Clock and DLL Clock Crystal Oscillation Clock 12.288 MHz (48 kHz*256) 18.432 MHz (48 kHz*384) 24.576 MHz (48 kHz*512) 25.00 MHz (asynchronous) 27.00 MHz (asynchronous) 30.0 MHz (asynchronous) 36.864 MHz (48 kHz*768) 6th Times Clock 73.728 MHz (36 MIPS operation) 110.592 MHz (55 MIPS operation) 147.456 MHz (73 MIPS operation) to 150 MHz (75 MIPS operation) Not available Not available Not available 4th Times Clock 49.152 MHz (24 MIPS operation) 73.728 MHz (36 MIPS operation) 98.304 MHz (49 MIPS operation) 100.00 MHz (50 MIPS operation) 108.00 MHz (54 MIPS operation) to 120 MHz (60 MIPS operation) Not available 3rd Times Clock 38.864 MHz (18 MIPS operation) 55.296 MHz (27 MIPS operation) 73.728 MHz (36 MIPS operation) 75.00 MHz (37 MIPS operation) 81.00 MHz (40 MIPS operation) 90.00 MHz (45 MIPS operation) 110.592 MHz (55 MIPS operation) Note 8: Crystal oscillation clock is as asynchronous as the system clocks (AD converter, DA converter, etc.) of external LSI. A case needs to input the clock oscillated externally into CKI terminal, and needs to synchronize with them. 7. Flag Input (FI0-FI3 terminal) It is used when inputting a flag from a MCU. However, a function changes with built-in programs. FI0 to FI3 terminal should fix each terminal to “H”, or since pull-up resistance is built in, when not being specified by the program, please it be open and be used for it. 8. Interruption Input (IRQ terminal) It is used when interrupting and inputting from a MCU. However, operation changes with built-in programs. IRQ terminal should fix a terminal to “L”, or since pull down resistance is built in, when not being specified by the program, please it be open and be used for it. 9. General-Purpose Output Terminal (PO0-PO7 terminal) It can be used when carrying out logic control of the case where it is used as an interruption output to the flag and the MCU for detection of internal operation, or the external LSI. However, the function and operation of a terminal change with built-in programs. Since PO0-PO7 terminal contains pull-up resistance, when not being specified by the program, please carry out and use each output terminal for opening. At the time of a power-supply injection, the output of a general-purpose output terminal becomes unfixed. “L” level will be outputted if it initializes with a reset terminal. 25 2005-09-28 TC9446FG 10. External SRAM Connection It can be used by the ability of able to connect external SRAM to processing of data tables, such as coefficient data, or data delay. The function of the terminal for external SRAM control is shown in Table 7. Moreover, the example of connection of external SRAM is shown in Figure 21. Table 7 Function of Terminal for External SRAM Control Terminal Name WR terminal OE terminal CE terminal IO0 to IO7 terminal Write signal output terminal for external SRAM Output enable signal output terminal for external SRAM Chip enable signal output terminal for external SRAM Data input/output terminal for external SRAM (8 bit I/O) It is 3rd times accessing at 24 bit I/O. Address output terminal for external SRAM It can access to address 00000h to 20000h. Functions AD0 to AD16 terminal Example of High-speed 1 M SRAM connection TC9446FG (3.3 AD0¯AD16 IO0¯IO7 CE OE WR 17 8 1 M HS SRAM (3.3 V) Example of High-speed 256 k SRAM connection TC9446FG (3.3 256 k HS SRAM (3.3 V) AD15, 16 N.C 15 8 AD0¯AD14 IO0¯IO7 CE OE WR AD0¯AD14 IO0¯IO7 CE OE WR AD0¯AD16 IO0¯IO7 CE OE WR Figure 21 Example of Connection of External SRAM 26 2005-09-28 TC9446FG 11. Serial Data Input-and-Output Terminal Since two terminals (SDI0 and SDI1 terminal) are prepared for an audio serial data input and four terminals (SDO0-SDO3 terminal) are prepared for an output, the connection with external AD/DA converter LSI is easy. Although an input terminal (SDI0, SDI1, LRCKA, BCKA, LRCKB, and BCKB terminal) can be inputted by 3-5 V, an output terminal (SDO0-3, LRCKOA, BCKOA, LRCKOB, and BCKOB terminal) is outputted by 3 V. Therefore, when the input terminal of external LSI does not correspond to TTL level input, please carry out level conversion using a level shifter circuit etc. Figure 22 the example of connection of AD/DA converter is shown. However, when an input-and-output signal has the same sampling frequency, it is restricted. Since a sampling frequency differs when the signal of 2 fs is inputted and it outputs a signal by 1 fs, the connection method needs to be changed. AD/DA converter TC9446FG DATA OUT Analog input DATA IN0 Analog output DATA IN1 DATA IN2 LRCKI BCKI SCKI SDI0 (fs) SDO0 (not used) SDO1 SDO2 SDO3 LRCKOA (2 fs/fs) BCKOA LRCKA BCKA LRCKOB (not used) BCKOB (not used) LRCKB BCKB SDI1 (not used) CKO RX (2 fs/fs) TXO (2 fs/fs) DIT DIR input DIT output Figure 22 Example of AD/DA Converter Connection 27 2005-09-28 TC9446FG 12. Example of Processing of Dolby Digital (AC-3) (Note 9) Decoder IEC958 Dolby Digital (AC-3) 5.1 ch decode Configuration C/Sch delay SFC IEC958 Dolby Digital (AC-3) 5.1 ch decode 2 ch Down Mix IEC958 Dolby Digital (AC-3) 5.1 ch decode 3D sound IEC958 Dolby Digital (AC-3) 2 ch decode Dolby Pro Logic SFC IEC958 Dolby Digital (AC-3) 2 ch decode Dolby Pro Logic 3D sound IEC958 Dolby Digital (AC-3) 2 ch decode 3D sound Note 9: “Dolby”,”Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. 28 2005-09-28 TC9446FG 13. Example of System Application MCU TC9446FG MCU Interface 384 fs TIMING CKO LRCKOA BCKOA 384 fs fs 64 fs DAC R OUT RX (IEC958) DIR (VCO) L OUT CKI 384 fs LRCKA BCKA DLL (×6) DAC SR OUT 110.592 MHz SDO0¯3 C OUT DAC DECODE (55 MIPS) LFE OUT DIT TXO (IEC958) SL OUT 18.432 MHz L IN ADC R IN SDI0 LRCK BCK 384 fs 29 2005-09-28 TC9446FG 14. Example of Application Circuit SRAM I/F (3.3 V) 0.1 µF VDD AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VDD IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 VSS VSS PO0 PO1 EXT OUT (3.3 V) PO2 PO3 PO4 PO5 PO6 PO7 0.1 µF 0.033 µF to 0.1 µF WR VSS LOCK 0.1 µF 81 OE CE 80 51 50 AUDIO SCK MCU I/F 0.1 µF 47 µF CKO VSSA CKI AMPO AMPI PLON TC9446FG (top view) 0.01 µF 0.47 µF 100 Ω 4.7 kΩ VDDDL LPFO DLON DLCKS SCKO VSSDL SCKI VDDA PDO TSTSUB2 TSTSUB1 1 kΩ (1%) 1 kΩ (1%) FCONT TSTSUB0 VSS RX TEST3 TEST2 TXO 0.1 µF * * VSSX XO XI DIR IN 18.432 MHz 20 pF 2.2 M 20 pF LRCKOA LRCKOB VDDX LRCKA MIACK MIDIO SDO0 SDO1 SDO2 SDO3 BCKA MIMD MICS MICK MILP BCKB SDI0 RST SDI1 100 1 DIT OUT BCKOA BCKOB LRCKB TEST0 VSS IRQ FI0 FI1 FI2 FI3 VDD * * TEST1 31 30 0.1 µF 4.7 µF MCU I/F (3.3 V) 0.1 µF AUDIO I/F (3.3 V) VDDX and VSSX line which the *-mark attached should dissociate and connect with other VDD and VSS line. Note 10: According to the diving noise of outside which receives a power supply line and GND line, etc., or jitters of the input signal, and other operating conditions (power-supply voltage, temperature conditions, etc.), the lock of PLL may separate from this product and it may become unstable. Please determine constant value according to the characteristic of a circuit in the case of use of this product. In addition, the constant value in the example of an application circuit is for explaining operation of this product, and application, and does not offer a guarantee of operation. 100 pF 15 kΩ 120 pF 10 kΩ 10 kΩ 30 2005-09-28 TC9446FG Maximum Ratings (Ta = 25°C) Characteristics Power supply voltage Input voltage-1 Symbol VDD VIN1 Rating Unit V V −0.3 to +4.0 −0.3 to VDD + 0.3 −0.3 to VDD + 3.0 (Note 11) Input voltage-2 Power dissipation Operating temperature Storage temperature VIN2 PD Topr Tstg V mW °C °C 1500 −40 to +85 −55 to +150 Note 11: MICS , MILP , MIDIO, MICK , LRCKA, BCKA, LRCKB, BCKB, SDI0, SDI1, RX (schmitt input terminals) Electrical Characteristics DC Characteristics Characteristics Operating power supply voltage-1 Operating power supply voltage-2 Operating frequency range-1 (unless otherwise specified, Ta = 25°C, VDD = VDDX = VDDA = VDDDL = 3.3 V) Symbol VDD1 VDD2 fopr1 Test Circuit Test Condition Ta = −40 to +85°C, fopr < 140 MHz = Ta = −40 to +85°C, fopr > 140 MHz DLL oscillation frequency (4th times) DLL oscillation frequency (6th times), At fopr > 140 MHz, VDD = 3.1 to 3.6 V. fopr = 150 MHz 75 MIPS operating Min 3.0 3.1 Typ. 3.3 3.3 Max 3.6 3.6 120 Unit V V MHz ⎯ ⎯ ⎯ ⎯ ⎯ Operating frequency range-2 fopr2 ⎯ ⎯ ⎯ 150 MHz Power supply current IDD ⎯ ⎯ 110 160 mA Clock Terminals Input voltage “H” level “L” level “H” level “L” level VIH1 VIL1 IOH1 IOL1 ⎯ ⎯ ⎯ ⎯ XI pin, (Note 14) VOH = 2.8 V VOL = 0.5 V 2.5 ⎯ ⎯ ⎯ ⎯ ⎯ 0.8 ⎯ XO pin V Output current ⎯ 15 −8 ⎯ mA Note 14: CKI, SCKI (CMOS input terminals) 31 2005-09-28 TC9446FG Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Input Terminals Input voltage “H” level “L” level VIH2 VIL2 ⎯ ⎯ (Note 11), (Note 12), (Note 13), (Note 15) (Note 11), (Note 12), (Note 15), AMPI pin 2.8 ⎯ ⎯ ⎯ 0.5 ⎯ V “H” level Input leakage current “L” level IIH ⎯ VIN = VDD ⎯ ⎯ ±10 µA IIL ⎯ VIN = 0 V (Note 11), (Note 13) AMPI pin ⎯ ⎯ ±10 Output Terminals Output current “H” level “L” level Output current “H” level “L” level IOH2 IOL2 IOH3 IOL3 ⎯ ⎯ ⎯ ⎯ VOH = 2.8 V VOL = 0.5 V VOH = 2.8 V VOL = 0.5 V (Note 15), (Note 16), (Note 17) AMPO pin ⎯ 15 ⎯ ⎯ ⎯ ⎯ −8 ⎯ −1 ⎯ mA ⎯ 1 mA 3-State Output Terminals Output current “H” level “L” level IOH4 IOL4 IOZ4 ⎯ ⎯ ⎯ VOH = 2.8 V VOL = 0.5 V VOH = VDD, VOL = 0 V FCONT, PD pins ⎯ 15 ⎯ ⎯ ⎯ −8 ⎯ ±10 mA Output off leakage current ⎯ µA Open-Drain Output Terminals Output current “L” level IOL6 IOL6 ⎯ ⎯ VOL = 0.5 V VOH = VDD, VOL = 0 V MIDIO pin 20 ⎯ ⎯ ⎯ ±10 mA Output off leakage current ⎯ µA Pull-Up Resistor and Pull-Down Resistor Built-In Terminals Pull-up resistor Pull-down resistor Rup Rdwn ⎯ ⎯ VIN = 0 V VIN = 3.3 V (Note 12), (Note 15), (Note 16) (Note 13) 45 55 ⎯ ⎯ 75 85 kΩ kΩ Note 11: MICS , MILP , MIDIO, MICK , LRCKA, BCKA, LRCKB, BCKB, SDI0, SDI1, RX (schmitt input terminals) Note 12: RST , TSTSUB0 to 2, TEST0 to 3, PLON, DLON, DLCKS, FI0 to 3 (schmitt input terminals with pull-up resistor) Note 13: MIMD, IRQ (schmitt input terminals with pull-down resistor) Note 15: IO0 to 7 (input/output terminals with pull-up resistor) Note 16: PO0 to 7, AD0 to 16, WE , OE , CE (output terminals with pull-up resistor) Note 17: MIACK, SDO0 to 3, LRCKOA, BCKOA, LRCKOB, BCKOB, TXO, CKO, SCKO, LOCK (output terminals) 32 2005-09-28 TC9446FG Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit AC Characteristics (1) Timing Clock Input Terminals (XI) Clock frequency Clock duty fXI fDTY DLL oscillation circuit (4th times) ⎯ ⎯ ⎯ 40 ⎯ 50 30 60 MHz % ⎯ Clock Input Terminals (CKI) Clock frequency Clock “H” duration Clock “L” duration fCI tCIH tCIL ⎯ ⎯ ⎯ 384 fs, fs = 96 kHz ⎯ 13 13 ⎯ ⎯ ⎯ 37 MHz ns ns ⎯ ⎯ ⎯ ⎯ Clock Input Terminals (SCKI) Clock frequency Clock “H” duration Clock “L” duration fSI tSIH tSIL ⎯ ⎯ ⎯ 75 MIPS operating ⎯ 3.3 3.3 ⎯ ⎯ ⎯ 150 MHz ns ns ⎯ ⎯ ⎯ ⎯ Reset Terminal ( RST ) Stand-by time Reset pulse width tRRS tWRS ⎯ ⎯ ⎯ ⎯ 10 10 ⎯ ⎯ ⎯ ⎯ ms µs Audio Serial Interface (LRCKA to B, BCKA to B, LRCKOA to B, BCKOA to B, SDI0 to 1, SDO0 to 3) LRCK setup time LRCK hold time SDI setup time SDI hold time BCK clock cycle BCK clock “H” duration BCK clock “L” duration SDO output delay time-1 SDO output delay time-2 LRCK output delay time tLBS tLBH tSDI tHDI tBCK tBCH tBCL tDO1 tDO2 tDCLR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz CL = 30 pF, fs = 96 kHz 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 60 ns ns ns ns ns ns ns ns ns ns −60 20 20 160 80 80 ⎯ ⎯ ⎯ ⎯ ⎯ 10 10 10 ⎯ ⎯ ⎯ 33 2005-09-28 TC9446FG Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Micro Controller Interface Serial Transmission Mode ( MICS , MICK , MIDIO, MILP , MIACK) Stand-by time MICS fall-MICK rise setup time MIACK fall-MICK rise setup time MICK clock cycle MICK “L” duration MICK “H” duration MICK rise-MILP fall setup time MILP “duration MIDIO input data setup time MIDIO input data hold time MIDIO output data delay time MICS “H” duration MIACK output delay time MILP rise-MICS rise setup time tSTB t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 25 0.5 0.5 1.0 0.5 0.5 0.5 0.5 0.5 0.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.5 ms µs µs µs µs µs µs µs µs µs µs µs µs µs ⎯ 0.5 ⎯ 0.1 ⎯ 0.5 ⎯ Note 18: “H” duration of MIACK signal depends on firmware of TC9446FG. I C Mode ( MICK , MIDIO) MICK clock frequency MICK “H” duration MICK “L” duration Data setup time Data hold time Transmission start condition hold time Repeat transmission start condition setup time Transmission end condition setup time Data transmission interval I2C rise time I2C fall time fIFCK tH tL tDS tDH tSCH tSCS tECS tBUF tR tF 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF 0 0.6 1.3 0.1 0 0.6 0.6 0.6 1.3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 400 kHz ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.1 µs µs µs µs µs µs µs µs µs µs ⎯ 0.5 ⎯ 34 2005-09-28 TC9446FG Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit External RAM Memory Interface (WR, OE, CE, IO0 to 7, AD0 to 16) (1) Memory read input/output tASR tAHR tPCR tRC Address setup time Address hole time Pre-charge time Read cycle width ⎯ ⎯ ⎯ ⎯ CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating 8 bit, one time access CL = 30 pF, 75 MIPS operating 16 bit, two times access CL = 30 pF, 75 MIPS operating 24 bit, three times access ⎯ ⎯ 14 27 27 14 0 ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ⎯ ⎯ ⎯ Until read end from chip select tCR ⎯ 54 ⎯ ⎯ ns 80 ⎯ ⎯ ⎯ 0 ⎯ 15 15 ns ns ns ns ns OE access time of external SRAM CE access time of external SRAM Output data hold time of external SRAM Address access time of external SRAM CE disable time of external SRAM tOE tCO tOH tACC tCOD ⎯ ⎯ ⎯ ⎯ ⎯ CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15 14 ⎯ ⎯ (2) Memory write output tASW tWP tAHW tPCW tWC Address setup time WR pulse width Address hold time Pre-charge time Write cycle width ⎯ ⎯ ⎯ ⎯ ⎯ CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating 8 bit, one time access CL = 30 pF, 75 MIPS operating 16 bit, two times access CL = 30 pF, 75 MIPS operating 24 bit, three times access ⎯ 17 14 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ⎯ 0 ⎯ 14 27 27 ⎯ ⎯ ⎯ Until write end from chip select tCW ⎯ 54 ⎯ ⎯ ns 80 ⎯ 23 4 0 0 ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns Output data setup time Output data hold time OE setup time OE hold time tDS tDH tOES tOEH ⎯ ⎯ ⎯ ⎯ CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating CL = 30 pF, 75 MIPS operating ⎯ ⎯ ⎯ ⎯ 35 2005-09-28 TC9446FG AC Characteristics Measurement Points (1) Clock terminal (XI, CKI, SCKI) Clock 50% tH, tCIH, tSIH tL, tCIL, tSIL fXI, fCI, fSI Duty cycle (fDTY) = tH/(tL + tH) × 100 (%) (2) Reset VDD RST 100% 0% 90% tRRS tWRS 90% (3) Audio serial interface (LRCKx, BCKx, SDIx, LRCKOx, BCKOx, SDOx, CKO) CKO 100% 0% 50% tDCLR 50% LRCKOx tBCK tBCL LRCKx/ LRCKOx tLBH BCKx/ BCKOx SDIx tSDI SDOx tDO1 tDO2 tHDI tLBS tBCH 36 2005-09-28 TC9446FG (4) Micro controller interface (4-1) Serial transmission interface mode ( MICS , MICK , MIDIO, MILP , MIACK ) RST MICS tSTB MICS t1 t2 ΜΙΑCΚ t4 MICK t3 t5 t6 t7 t12 MILP t8 t9 DATA IN MIDIO MIDIO t10 DATA OUT t11 MICS t13 ΜΙΑCΚ MICK t6 t7 MILP MIDIO DATA IN MIDIO DATA OUT 37 2005-09-28 TC9446FG (4-2) I2C mode ( MICK , MIDIO) RST MIDIO (SDA) tBUF MIDIO (SDA) MICK (SCL) tSCH tR tL tH tDS tDH tSCS tF tECS tSTB 38 2005-09-28 TC9446FG (5) External RAM memory interface (5-1) READ cycle timing AD0-AD16 ADDRESS tASR CE tPCR WR tACC OE tOE IO0-IO7 tCO tOH DATA IN tCOD tAHR tRC tCR (5-2) WRITE cycle timing AD0-AD16 ADDRESS tASW CE tWP WR tPCW tAHW tWC tWC OE tOES IO0-IO7 DATA OUT tDS tDH tOEH 39 2005-09-28 TC9446FG Package Dimensions P-QFP100-1420-0.65Q Unit : mm W eight: 1.57 g (typ.) (Note) Palladium plate 40 2005-09-28 TC9446FG 41 2005-09-28