TC94A39FAG

TC94A39FAG/FB TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A39FAG, TC94A39FB Single-Chip CD Processor with Built-in Controller (CD-DX) The TC94A39FAG/FB is a single-chip CD processor for digital servo, which incorporates a 4-bit microcontroller. The controller features an LCD driver, 4-channel 6-bit AD converter, 1 port 2-channel 2/3-line or UART serial interface module, a buzzer, 20-bit general-purpose counter function, interrupt function, and 8-bit timer/counter. The CPU can select one of four operating clocks (16.9344-MHz, 75-kHz or 32.768-kHz crystal oscillator and CR oscillator), facilitating interface with the CD processor. The CD processor incorporates sync separation protection and interpolation, EFM demodulator, error correction, digital equalizer for servo, and servo controller. The CD processor also incorporates a 1-bit DA converter. In combination with the TA2157F/FN digital servo head amplifier, the TC94A39FAG/FB can very simply configure an adjustment-free CD player. Thus, the IC is suitable for CD systems for automobiles and radio-cassette players. TC94A39FAG TC94A39FB Features · · Single-chip CD processor with on-chip CMOS LCD driver and 4-bit microcontroller Operating supply voltage: CD in operation: VDD = 3.0 to 3.6 V (3.3 V typ.) CD stopped: VDD = 1.8 to 3.6 V (only CPU in operation) · Supply current: CD in operation: IDD = 30 mA (typ.) CD stopped: IDD = 1.5 mA (CD standby mode, with 16.9344-MHz crystal oscillator, CPU in operation) CD stopped: IDD = 50 µA (CD standby mode, with 75-kHz crystal oscillator, CPU in operation) · · · Operating temperature range: Ta = −40 to 85°C Package: LQFP/QFP-64 (0.5/0.65-mm pitch, 1.4 mm thick) E2PROM: TC94AE29FAG/FB Weight LQFP64-P-1010-0.50: 0.32 g (typ.) QFP64-P-1212-0.65: 0.45 g (typ.) 1 2003-04-01 TC94A39FAG/FB 4-bit Microcontroller · Program memory (ROM): 16 bits ´ 8 Ksteps · Data memory (RAM): 4 bits ´ 512 words · Instruction execution time: 1.42 ms, 40 ms, 91.6 ms, TOSC ´ 3 (Every instruction consists of a single word.) · Crystal oscillator frequency: 16.9344 MHz, 75 kHz, 32.768 kHz, CR oscillation frequency · Stack levels: 6 · AD converter: 6 bits ´ 4 channels · LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 64 segments (max.) · I/O ports: CMOS I/O ports: 26 (max.) N-channel open-drain I/O ports (for up to 5.5 V): 3 (max.) · Timer/counter: 8 bits (timer mode, pulse width detector and measure function) · General-purpose counter: 20 bits, 0.1 MHz to 20 MHz, Vin = 0.2 Vpp (min.), input amplifier incorporated · Serial interface module: 1 port 2 channel supporting 2/3-line method or UART (two input channels) · Four buzzer types: 0.75 kHz, 1 kHz, 1.5 kHz, and 3 kHz · Four modes: continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz intervals · Interrupts: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer) · Back-up mode: Four types: CD standby (CD processor stopped) Clock stop (oscillator stopped) Hardware wait (only crystal oscillator in operation) Software wait (CPU in intermittent operation) · Reset function: Power-on reset circuit, supply voltage detector (detection voltage = 1.5 V typ.) CD Processor · Reliable sync pattern detection, sync signal protection and interpolation · Built-in EFM demodulator and subcode decoder · High-correction capability using Cross Interleave Read Solomon Code (CIRC) logical equation C1 correction: dual C2 correction: quadruple · Jitter absorption capability of ± 6 frames · Built-in 16 KB RAM · Built-in digital output circuit · Built-in L/R independent digital attenuator · Bilingual audio output · Audio output: 32fs, 48fs or 64fs selectable · Subcode Q data is read-timing free and can be driven out in sync with audio data. · Built-in data slicer and analog PLL (adjustment-free VCO used) circuit · Automatic adjustment of loop gain, offset, and balance at focus servo and tracking servo · Built-in RF gain auto-adjusting circuit · Built-in digital equalizer for phase compensation · Supports different pickups using on-chip digital equalizer coefficient RAM. · Built-in focus and tracking servo control circuit · Search control supports all modes and realizes high-speed, stable search. · Lens kick and feed kick use speed control method. · Built-in AFC and APC circuits for disc motor CLV servo · Built-in defect/shock detector · Built-in 8 times over-sampling digital filter and 1-bit DA converter · Built-in analog filter for 1-bit DA converter · Built-in zero-data detection output circuit · Supports double-speed operation. Note: Output pins for subcode Q data and audio data have multiplexed functions for controller-dedicated pins. The function of each pin can be switched by program. 2 2003-04-01 TC94A39FAG/FB Pin Connections RFGC TEBC DVDD CVDD DVSS CVSS DMO FMO Pull-up/pull-down can be specified. 48 Reset input RESET 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 CD processor-dedicated control input/output pins 29 28 27 26 25 24 23 22 21 20 19 TEZI TEI SBAD FEI RFRP RFZI VREF AVDD RFI SLCO AVSS VCOF LPFO LPFN TMAX PDO 49 50 51 52 53 LCD driver (4 ´ 16 = 64 segments max.) 54 55 56 57 58 59 60 61 62 63 64 1 2 1-bit DAC 75-kHz / 32.768-kHz/CR P8-0/MXI/OSC (BRK1) P8-1/MXO (BRK2) P2-0/COM1 P2-1/COM2 P2-2/COM3 Test mode input P2-3/COM4 TEST/P3-0/S1 P3-1/S2 P3-2/S3 P3-3/S4 P4-0/S5 P4-1/S6 P4-2/S7 P4-3/S8 P5-0/S9 16.9344-MHz oscillator LQFP/QFP-64 (0.5/0.65-mm pitch) Top view AD converter Serial interface 1 Controller-dedicated pins FOO 18 17 16 Interrupt input P7-2/INTR/SI2 (BRK16) DVR 3 4 5 6 7 8 9 10 11 12 13 14 15 P1-1/SDIO1/TX1/SFSY (BRK11) P6-1/S14/ADin2/IPF (BRK7) P1-2/SI1/SBSY (BRK12) P6-2/S15/ADin3/SBOK (BRK8) P6-3/S16/ADin4/CLCK (BRK9) P6-0/S13/ADin1/DOUT (BRK6) Pull-up/pull-down can be specified. CMOS I/O ports (up to 26 ports) Also used for CD function P1-0/SCK1/RX1/CTin/DATA (BRK10) N-ch open-drain I/O (3 pins, 5.5 V max.) Serial interface 2 Frequency counter input Buzzer output Note: For BRK1 to BRK16, the backup state can be set to be released in port units. Note: The TEST pin (pin 56) is pulled down during a reset, thus accepting test mode input. Therefore, it should be applied low or left open during a reset. 3 P7-1/SDIO2/TX2 (BRK15) P5-3/S12/AOUT (BRK5) P5-1/S10/BCK (BRK3) P5-2/S11/LRCK (BRK4) P7-0/SCK2/RX2 (BRK14) P1-3/BUZR (BRK13) MVDD MVSS TRO SEL RO LO XO XI 2003-04-01 TC94A39FAG/FB Block Diagram RFGC SBAD RFRP TEBC AVDD AVSS VREF VREF DMO FMO RFZI VREF FOO TEZI TRO SEL TEI FEI Clock gene. PWM XI XO Crystal OSC CD clock VREF DA Data slicer RFI SLCO ZDET Servo control VREF 1-bit DAC LPF AD PLL TMAX TMAX PDO DVDD RO DVSS LO DVR VCOF ROM RAM Digital equalizer Automatic adjustment circuit CLV servo Sub code decoder Synchronous guarantee EFM decoder VREF VCO VREF LPFO LPFN Audio out Digital out CD Reset 16-k SRAM Correction circuit CVSS MPX Microcontroller interface Reset SBSY BCK, LRCK, AOUT, DOUT IPF, SBOK, CLCK, DATA, SFSY CPU clock CR OSC P8-0/MX1/OSC (BRK1) P8-1/MXO (BRK2) Crystal OSC Port 8 Mask ROM (16 ´ 8192 Steps) Timer SBSY INTR Interrupt cont. F/F Serial interface (SIO) Program Counter Instruction Decoder Reset RESET Data Reg (16 bits) G-Reg. R/W Buf. RAM (4 ´ 512 words) ALU Power on Reset P7-0/SCK2/RX2 (BRK14) P7-1/SDIO2/TX2 (BRK15) P7-2/INTR/SI2 (BRK16) Bias BCK, LRCK, AOUT, DOUT, IPF, SBOK, CLCK, DATA, SFSY, SBSY AD conv. 20-bit counter Buzzer Port 7 Stack Reg. (16 Levels) MVDD MVSS Address CVDD LCD Driver/IO Port 2, 3, 4, 5, 6 Port 1 SIO P1-1/SDIO1/TX1/SFSY (BRK11) TEST/P3-0/S1 P6-1/S14/ADin2/IPF (BRK7) P5-1/S10/BCK (BRK3) P6-2/S15/ADin3/SBOK (BRK8) P6-3/S16/ADin4/CLCK (BRK9) P1-0/SCK1/RX1/CTin/DATA (BRK10) P1-2/SI1/SBSY (BRK12) P5-2/S11/LRCK (BRK4) P2-0/COM1 P2-1/COM2 P2-2/COM3 P2-3/COM4 P5-3/S12/AOUT (BRK5) P3-1/S2 P5-0/S9 4 P6-0/S13/ADin1/DOUT (BRK6) P1-3/BUZR (BRK13) 2003-04-01 TC94A39FAG/FB Pin Functions Pin No. Symbol Pin Name Function and Operation System reset input pin for the device. A reset is applied while the RESET signal is low. When it is high, the 16.9344-MHz crystal oscillator (XI, XO) starts operating. The controller counts clock pulses from this oscillator and waits a specified standby time (approximately 50 ms) before starting the controller program from address 0. The CD processor is placed in the standby state at this time. Normally, raising the voltage on MVDD from 0 to 1.8 V or higher triggers a system reset (power-on reset) so that the RESET pin should be held at high. MVDD Remarks 49 RESET Reset input MVSS MVDD 2-bit CMOS I/O port. Input/output can be specified for each bit. When the pins are used as I/O port input, each pin can be pulled up or down by program. When backup release for clock stop mode or wait mode is enabled for the pins, a change in a pin can release the backup state. The program can set these pins to be used for a 75-kHz or 32.768-kHz dedicated crystal oscillator. The P8-0 pin can also be used for a CR oscillator. These clocks are used for the operation of the controller and peripheral devices. Upon a system reset, the 16.9344-MHz crystal oscillator (XI, XO) is selected as the clock for controller and peripheral device operation. The program can subsequently set the pins to oscillator pins and switch the clock generated from the oscillator to the controller clock. When the pins are used for an oscillator, executing the CKSTP instruction causes its oscillation to stop. (Note) When the P8-0 pin is used for a CR oscillator, the P8-1 pin can used as an I/O port pin. MVDD Input instructio RIN1 MVDD MVSS (When used for I/O port) 50 P8-0 /MXI /OSC (BRK1) I/O port 8-0 /crystal oscillator /CR oscillator Rout2 MXO RfXT2 MVDD MXI MVSS 51 P8-1 /MXO (BRK2) I/O port 8-1 /crystal oscillator (Note) Backup release is enabled for both pins (When used for crystal oscillator) simultaneously. (Note) Use a crystal oscillator having a good startup characteristic. (Note) Upon a system reset, the pins are set to I/O port input. (Note) After setting the pins to oscillator pins, wait until oscillation settles before switching the controller clock. R OSC MVDD MVDD C MVSS (When P8-0 is used for CR oscillator) 5 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name Function and Operation Remarks 24-bit CMOS I/O port and 3-bit N-channel open-drain I/O port. 52 53 54 55 P2-0/COM1 P2-1/COM2 P2-2/COM3 P2-3/COM4 Input/output can be specified for each bit. When the P6-0 to P6-3 pins are used as I/O port input, each pin can be pulled up or down by program. When the P5-1 (BRK3) to P7-2 (BRK16) pins I/O port 2 are used as I/O port input and backup release /LCD common output for clock stop mode or wait mode is enabled for those pins (enabled/disabled in port units), a change in any of the pins can release the backup state. The P7-0 to P7-2 pins constitute an N-channel open-drain I/O port, to which a voltage of up to 5.5 V can be applied. I/O ports 2 to 6 can be set to LCD driver output pins by program. The COM1 to COM4 pins drive common signals to the LCD panel while the S1 to S16 pins drive segment signals. The COM1 to COM4 signals configure a matrix with the S1 to S16 signals to display up to 64 segments. When the LCDoff bit is set to 0, the COM1 to COM4 and S1 to S4 pins are collectively set to LCD output. For S5 to S16, the program can specify either I/O port or segment output individually for each pin. LCD voltage MVDD MVDD Input instruction LCD voltage MVDD 56 TEST /P3-0/S1 Test input /I/O port 3-0 The LCD can be driven by the 1/4-duty, 1/2-bias /LCD segment output method (frame frequency: 62.5 Hz) or the 1/4-duty, 1/3-bias method (frame frequency: 125 Input Hz). When the 1/2 bias method is set, three instruction common output levels (MVDD, 1/2MVDD and RIN2 GND) and two segment output levels (MVDD and GND) appear on the pins. When the 1/3 bias method is set, four common and segment output levels (MVDD, 1/3MVDD, 2/3MVDD and GND) appear on the pins. Upon a system reset or after clock stop mode is released, a non-select waveform (bias voltage) is driven and the DISP OFF bit is set to 0, after which the common signals are driven. During a system reset ( RESET = low), the TEST/P3-0/S1 pin is pulled down and accepts test mode input. This pin should be left open or applied low level during a reset. The P5-1 to P6-3 and P1-0 to P1-2 pins can be set to CD processor-dedicated pins on a per pin basis. The CD processor functions are as I/O port 4 /LCD segment output follows: Input (Continued on next page) instruction MVDD Reset signal MVSS 57 58 59 P3-1/S2 P3-2/S3 P3-3/S4 I/O port 3 /LCD segment output LCD voltage MVDD 60 61 62 63 P4-0/S5 P4-1/S6 P4-2/S7 P4-3/S8 MVDD 6 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name Function and Operation ●BCK: Bit clock output pin. One of three frequencies, 32, 48 or 64 can be specified using a CD command. At normal speed: 32 fs = 1.4112 MHz ●LRCK: LR channel clock output pin. For the L channel, this pin drives a low level. For the R channel, it drives a high level. I/O port 5-0 The polarity can be inverted using a /LCD segment output CD command. At normal speed: 44.1 kHz ●AOUT: Audio data output pin. Either MSB first or LSB first can be specified using a Input CD command. instruction ●DOUT: Digital data output pin. It drives data at up to double speed (complying with CP-1201). ●IPF: 1 P5-1/S10 /BCK (BRK3) P5-2/S11 /LRCK (BRK4) P5-3/S12 /AOUT (BRK5) Correction flag output pin. If the AOUT output is C2 error detection/correction, a high level appears to indicate an uncorrectable symbol. (Also called C2PO) LCD voltage MVDD MVDD Remarks LCD voltage MVDD 64 P5-0/S9 2 I/O port 5 /LCD segment output ●SBOK: CRCC test result output pin for subcode Q data. A high level appears /CD processor when the data has passed the test. function ●CLCK: Clock input/output pin for reading subcode P to W data. The input/output Input polarity can be inverted using a CD instruction command. Release enable ●DATA: Subcode P to W data output pin. ●SFSY: Frame sync signal output pin for playback. ●SBSY: Block sync signal output pin for subcode. When a subcode sync is detected, a high level appears at S1. The controller enables CD interrupts. When an interrupt occurs on the falling edge of the SBSY signal, the program jumps to address 2. (Note) Interrupts should not be enabled when CD processor operation is undefined. I/O port 6 /LCD segment output /CD processor function P6-0 to P6-3 pins have multiplexed functions for the on-chip 6-bit 4-channel AD converter analog input. The on-chip AD converter uses Input successive approximation. The conversion time instruction is 242 ms when the 16.9344-MHz crystal Release oscillator is used and 7 instruction cycles enable (280 ms) when the 75-kHz crystal oscillator is RIN1 used. The program can specify necessary pins for AD analog input on a per bit basis. The internal power supply (MVDD) is used as the reference voltage. When the P6-0 to P6-3 pins are used as I/O port input, each pin can be MVDD pulled up or down by program. AD input LCD voltage MVDD MVDD 3 4 P6-0/S13 /ADin1 /DOUT (BRK6) P6-1/S14 /ADin2 /IPF (BRK7) P6-2/S15 /ADin3 /SBOK (BRK8) P6-3/S16 /ADin4 /CLCK (BRK9) 5 MVDD 6 7 MVSS (Continued on next page) 7 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name I/O port 1-0 /serial clock input/output 1 /serial receive data 1 /counter clock input /CD processor function Function and Operation The P1-0 pin has multiplexed functions for general-purpose counter input. The input frequency is 0.1 MHz to 20 MHz. The counter incorporates an input amplifier and operates with capacitance-coupled small amplitudes. The counter is a 20-bit counter and can store 20-bit data directly in memory. The gate time can be selected from among 1 ms, 4 ms, 16 ms and 64 ms (when the 75-kHz crystal oscillator is used). In manual mode, the gate can be turned on and off within the specified time using instructions. Remarks 10 P1-0/SCK1 /RX1 /CTin /DATA (BRK10) MVDD 11 P1-1/SDIO1 /TX1 /SFSY (BRK11) 12 P1-2/SI1 /SBSY (BRK12) 13 P1-3/BUZR (BRK13) 14 P7-0/SCK2 /RX2 (BRK14) P7-1/SDIO2 /TX2 (BRK15) 15 I/O port 1-1 /serial data input/output 1 /serial transmit data 1 The P1-0 to P1-2 and P7-0 to P7-2 pins have /CD processor multiplexed functions for serial interface (SIO) function circuit input/output pins. I/O port 1-2 The SIO is a serial interface supporting 2-line /serial data input 1 and 3-line methods as well as UART. The /CD processor TC94A39FAG/FB has CMOS input/output pins function (SCK1/RX1, SDIO1/TX1, SI1) and N-channel open-drain (supporting up to 5.5 V) input/output pins (SCK2/RX2, SDIO2/TX2, SI2). One of the two sets of pins can be selected as serial interface. The serial interface circuit supports various options, including the number of the I/O port 1-3 clock edge to be used, the serial clock /buzzer output input/output, and the clock frequency. These options facilitate controlling the LSI and communications between the controllers. When SIO interrupts are enabled, an interrupt is generated as soon as execution of the SIO completes, causing the program to jump to I/O port 7-0 address 4. /serial clock The P1-3 pin has multiplexed functions for a input/output 2 /serial receive data 2 buzzer output pin. One of four frequencies within the range from 0.75 kHz, 1 kHz, 1.5 kHz I/O port 7-1 and 3 kHz can be selected for buzzer output /serial data (when the 75-kHz clock is used). The buzzer is input/output 2 driven at the selected frequency in one of four /serial transmit data 2 modes: continuous, single-shot, 10-Hz intermittent, and 10-Hz intermittent at 1-Hz intervals. MVSS MVDD Input instruction Release enable (When used for I/O port) RfIN MVDD CTin MVSS (When P1-0 is used for general-purpose counter) 16 P7-2/INTR /SI2 (BRK16) I/O port 7-2 /interrupt input /serial data input 2 The P7-2 pin has multiplexed functions for an external interrupt input pin. When interrupts are enabled and a pulse of 1.65 ms to 4.96 ms or more (13.3 ms to 40 ms when the 75-kHz clock is Input instruction used) is applied to this pin, an interrupt is Release generated and the program jumps to address 1. enable The input logic and rising/falling edge can be selected for interrupt inputs. This input can be applied as the clock gate signal to the internal 8-bit timer/counter, which allows input pulse width to be detected and measured. (Note) Backup release is enabled or disabled in port units. (Note) Upon a system reset, the pins are set to I/O port input. (Note) When the 32.768-kHz crystal oscillator or the CR oscillator is used, the general-purpose counter is used as a timer. MVSS MVDD 8 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name Function and Operation Power supply pins for the controller block. Normally, VDD = 3.0 to 3.6 V. When only the CPU operates (when the 75-kHz/32.768-kHz oscillator is used), it can operate at VDD = 1.8 to 3.6 V. In the backup state (when the CKSTP instruction is executed), current dissipation decreases (10 mA or below), allowing the power Power supply pins for supply voltage to be reduced to 1.0 V. controller block Raising the voltage on MVDD pin from 0 V to 1.8 V or higher triggers a system reset, causing the program to start from address 0 (power-on reset). 9 MVSS (Note) At power-on reset operation, allow 1 ms to 50 ms while the device power supply voltage rises. (Note) The backup current is the total of currents for CVDD, MVDD and DVDD. MVSS MVDD Remarks 8 MVDD AVDD Output pin for a phase error signal between the EFM and PLCK signals. 17 PDO Drives one of four values: AVDD, Hi-Z, VREF, AVSS VREF Rout4 AVSS TMAX detection result output pin. 18 TMAX Longer than specified cycle: Drives a high level (AVDD) Shorter than specified cycle: Drives a low level (AVSS) Within specified cycle: Hi-Z AVDD CD processor control input/output pin AVSS 19 LPFN Inverted input pin for PLL low-pass filter amplifier. VREF LPFN AVDD 20 LPFO Output pin for PLL low-pass filter amplifier. LPFO VREF VCO 21 VCOF VCO filter pin VCOF ¾ 22 AVSS Ground pin for analog block 9 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name Function and Operation Remarks 23 SLCO DAC output pin for generating data slice level. RFI Zin1 VREF AVDD 24 RFI RF signal input pin. The value of Zin1 can be selected using a CD command. SLCO DAC 25 AVDD Power supply pin for analog block. Normally, VDD = 3.0 to 3.6 V. In CD standby mode, turn this power supply off. Analog reference voltage pin. Normally, a voltage of 1/2 AVDD is supplied (when VDD = 3.3 V, VREF = 1.65 V). ¾ 26 VREF ¾ AVDD RFZI 27 RFZI RFRP zero-cross signal input pin VREF Zin2 1 kW typ. 32 kW typ. 28 RFRP CD processor control input/output pin RF ripple signal input pin RFRP AVDD 29 FEI Focus error signal input pin FEI 30 SBAD Subbeam addition signal input pin SBAD TEI 31 TEI Tracking error input pin. The pin is read when tracking servo is turned on. AVDD TEZI 32 TEZI Tracking error/zero-cross signal input pin VREF Zin2 1 kW typ. 32 kW typ. 33 FOO Focus equalizer output pin Rout3 AVDD A VDD to AVSS 34 TRO Tracking equalizer output pin 10 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name Function and Operation Remarks 35 RFGC Control signal output pin for adjusting RF amplitude. Drives three-level PWM signal (PWM carrier = 88.2 kHz). AVDD Rout3 36 TEBC Tracking balance control signal output pin. Drives three-level PWM signal (PWM carrier = 88.2 kHz). VREF AVDD CD processor control APC circuit ON/OFF signal output pin. When laser is turned on, this pin will be in a input/output pin high-impedance state. 37 SEL 38 FMO Feed equalizer output pin. Drives three-level PWM signal (PWM carrier = 88.2 kHz). Rout3 AVDD 39 DMO Disc equalizer output pin. Drives three-level PWM signal (PWM carrier = 88.2 kHz). VREF CVDD 40 CVDD Logic power supply pins for the CD processor block and 16.9344-MHz dedicated crystal oscillator. Normally, the same power supply as that for the MVDD and MVSS pins is connected. In CD standby mode, current dissipation decreases. CVSS Power supply pins 43 CVSS 41 XO Input/output pins for the CD processor-dedicated crystal oscillator. Connect a 16.9344-MHz crystal oscillator. This clock is used as the CD processor system clock and controller system clock. Upon a system reset, this clock is supplied as the controller system clock and starts the CPU. The crystal oscillator can be stopped by Crystal oscillator pins program. If the 75/32.768-kHz or CR oscillator is selected as the controller system clock, the CD processor oscillator is stopped by program when the CD processor is turned off. Rout1 XO RfXT1 CVDD XI CVSS 42 XI (Note) When switching the controller system clock from the controller oscillator to the CD crystal oscillator, make sure that the CD crystal oscillator is sufficiently stable. 11 2003-04-01 TC94A39FAG/FB Pin No. Symbol Pin Name Function and Operation DA converter block power supply pin 44 DVDD The TC94A39FAG/FB consumes less current in CD standby mode. DVR DVDD Remarks 45 RO R-channel data forward rotation output pin 46 DVSS Audio DAC output DA converter block ground pin RO/LO DVDD 47 LO L-channel data forward rotation output pin DVSS VSS 48 DVR Reference voltage pin 12 2003-04-01 TC94A39FAG/FB Maximum Ratings (Ta = 25°C, CVDD = DVDD = AVDD = MVDD) Characteristic Supply voltage CVDD pin Input voltage (Note 1) AVDD pin DVDD pin MVDD pin Symbol VDD VIN1 VIN2 VIN3 VIN4 VIN5 TC94A39FAG Power dissipation TC94A39FB Operating temperature Storage temperature PD Topr Tstg Rating -0.3 to 4.0 -0.3 to CVDD + 0.3 -0.3 to AVDD + 0.3 -0.3 to DVDD + 0.3 -0.3 to MVDD + 0.3 -0.3 to 6.0 400 mW 500 -40 to 85 -65 to 150 °C °C V Units V Note 1: VIN1; Pins 41 and 42 VIN2; Pins 17 to 39 (excluding power supply pins) VIN3; Pins 45, 47 and 48 VIN4; Pins 1 to 13 and 49 to 64 (excluding power supply pins) VIN5; Pins 14, 15 and 16 13 2003-04-01 TC94A39FAG/FB Electrical Characteristics Parameter (Ta = 25°C, CVDD = MVDD = DVDD = AVDD = 3.3 V, VREF = 1.65 V unless otherwise stated) Symbol Test Circuit Test Condition CPU and CD in operation MVDD = CVDD > DVDD = AVDD = Min Typ. Max Units VDD1 Operating supply voltage range 3.0 (Note 4) 3.0 ~ 3.6 VDD2 ¾ CPU in operation (CD standby, 16.9344-MHz crystal oscillator/CR oscillator used) (Note 4) Only CPU in operation (CD standby, 75-kHz/32.768-kHz crystal oscillator used) (Note 5) ~ 3.6 V VDD3 ¾ 1.8 ~ 3.6 Memory hold voltage range MVHD IDD1 IDD2 Crystal oscillator stopped (CKSTP (Note 4) instruction executed) CPU and CD in operation (XI = 16.9344-MHz crystal oscillator used) Only CPU in operation (XI = 16.9344-MHz crystal oscillator used) 1.0 ¾ ~ 30 1.5 50 2.0 3.6 50 V mA ¾ ¾ ¾ ¾ ¾ 100 ¾ mA mA mA Operating power supply current (Note 2) IDD3 IDD4 ¾ CPU in operation (MXI = 75-kHz crystal oscillator connected) CPU in operation (OSC = 0.5-MHz oscillation) Standby mode (only crystal oscillator in operation, MXI = 75 kHz) IDD5 40 80 Memory hold current MIHD ¾ (CVDD/MVDD/AVDD/DVDD) Crystal oscillator stopped (CKSTP instruction executed) (MXI-MXO) Crystal oscillator selected (Note 3) (Note 5) ¾ 0.1 10 mA fMXT Oscillation frequency fXT fOSC Oscillating frequency error Crystal oscillator start time Crystal oscillator amplifier feedback resistance Crystal oscillator output resistance Dropout voltage detect voltage Dropout voltage detector operating current DfOSC tst RfXT1 RfXT2 Rout1 Rout2 VDET IDD-VD ¾ ¾ ¾ ¾ 30 ¾ 0.01 ¾ ¾ 0.5 ¾ 0.25 50 1.4 ~ 16.9344 ~ ¾ ¾ 1.0 16 0.5 100 1.5 100 100 ¾ 0.75 15 1.0 2.0 ¾ 1.0 200 1.6 ¾ kHz (XI-XO) (OSC) CR oscillator selected (OSC) CR oscillator selected (Note 4) MHz ％ s MW (MXI-MXO) Crystal oscillator fmxt = 75 kHz/32.768 kHz (XI-XO) (MXI-MXO) (XO) (MXO) ¾ ¾ kW V mA (MVDD) Dropout voltage detector enabled ¾ ¾ Note 2: The operating power supply current includes the total current through all CVDD, MVDD, DVDD and AVDD power supply pins. Note 3: Design and specify constants according to the crystal oscillator to be connected. Note 4: The values are guaranteed when CVDD = MVDD = DVDD = AVDD = 3.0 to 3.6 V, Ta = -40 to 85°C. Note 5: The values are guaranteed when CVDD = MVDD = DVDD = AVDD = 1.8 to 3.6 V, Ta = -30 to 75°C. 14 2003-04-01 TC94A39FAG/FB General-purpose counter (CTin) Parameter Frequency range Input amplitude range Operating power supply current Input amplifier feedback resistance Symbol fCT VCT IDD-CT RfIN Test Circuit ¾ ¾ ¾ ¾ VIN = 0.2 VP-P Test Condition (Note 4) (Note 4) General-purpose counter operating current, fin = 20 MHz (CTin) Min 0.1 0.2 ¾ 200 Typ. ¾ ¾ 0.7 350 Max 20 2.0 ¾ 1000 Units MHz VP-P mA kW Note 4: The values are guaranteed when CVDD = MVDD = DVDD = AVDD = 3.0 to 3.6 V, Ta = -40 to 85°C. LCD common and segment outputs (COM1 to COM4, S1 to S16) Parameter Output current High level Low level 1/2 level Bias current 1/3 level 2/3 level LCD operating power supply current Symbol IOH1 IOL1 VBS2 VBS1 VBS3 IDD-LCD ¾ LCD driver operating current ¾ Test Circuit ¾ Test Condition VOH = 2.9 V (LCD output) VOL = 0.4 V (LCD output) No load (common output, 1/2 bias method) No load (LCD output, 1/3 bias method) 3.13 ¾ 3.33 50 3.53 ¾ mA Min ¾ ¾ 2.3 1.47 Typ. -300 450 2.5 1.67 Max ¾ ¾ 2.7 1.87 V Units mA I/O ports (P1-0 to P6-3, P8-0, P8-1, P7-0 to P7-3) Parameter High level Output current Low level Symbol IOH2 IOL2 IOL3 Input leakage current ILI ¾ ¾ Test Circuit Test Condition VOH = 2.9 V (P1-0~P6-3, P8-0, P8-1) VOL = 0.4 V (P1-0~P6-3, P8-0, P8-1) VOL = 0.4 V (P7-0 to P7-3) VIH = 3.3 V, VIL = 0 V (P1-0 to P6-3, P8-0, P8-1) VIH = 5.5 V, VIL = 0 V (P7-0 to P7-3) High level Input voltage Low level VIL RIN1 RIN2 VIH ¾ ¾ (P6-0 to P6-3, P8-0, P8-1) Pull-down/up specified (P3-0) Test input pulled down ¾ Min -1.0 1.0 5 ¾ ¾ VDD ´ 0.8 0 25 ¾ Typ. -2.0 2.0 15 ¾ ¾ ~ ~ 50 10 Max ¾ ¾ ¾ ±1.0 ±1.0 MVDD V MVDD ´ 0.2 120 ¾ kW mA mA Units Input pull-up/down resistance ¾ AD converter (ADin1 to ADin4) Parameter Analog input voltage range Resolution Symbol VAD VRES Test Circuit ¾ ¾ Test Condition ADin1 to ADin4 ¾ MVDD = 1.8 to 3.6 V, Ta = -30 to 75°C (Note 6) MVDD = 2.0 to 3.6 V, Ta = -40 to 85°C (Note 6) VIH = 3.3 V, VIL = 0 V (ADin1 to ADin4) Min 0 ¾ ¾ ¾ ¾ Typ. ~ 6 ¾ ¾ ¾ Max MVDD ¾ ±2.0 LSB ±1.0 ±1.0 mA Units V bit Total conversion error ¾ ¾ Analog input leakage current ILI ¾ Note 6: The values are guaranteed when CVDD = DVDD = AVDD = 3.0 to 3.6 V. 15 2003-04-01 TC94A39FAG/FB PDO, TMAX, RFGC, TEBC, FMO, DMO, TRO, FOO, and SEL output Parameter Output current High level Low level Output resistance VREF output ON resistance Symbol IOH6 IOL4 Rout3 Rout4 Ron Test Circuit ¾ Test Condition VOH = 2.9 V (SEL, TMAX) VOL = 0.4 V (SEL, TMAX) (RFGC, TEBC, FMO, DMO, TRO, FOO) (PDO) (RFGC, TEBC, FMO, DMO, PDO) Min -2.0 2.0 ¾ ¾ ¾ Typ. ¾ ¾ 3.0 5.0 ¾ Max ¾ ¾ ¾ ¾ 500 Units mA ¾ ¾ kW W Transfer delay time (BCK, LRCK, AOUT, DOUT, IPF, SBOK, CLCK, DATA, SFSY, SBSY) Parameter Transfer delay time High level Low level Symbol tpLH tpHL Test Circuit ¾ Test Condition ¾ ¾ Min ¾ ¾ Typ. 10 10 Max ¾ ¾ Units ns CD processor AD conversion block (FEI, TEI, RFRP, SBAD) Parameter Resolution Sampling frequency Symbol ¾ ¾ ¾ Test Circuit ¾ ¾ ¾ Test Condition (FEI, TEI, RFRP, SBAD) (FEI, TEI, RFRP) (SBAD) AVDD = 3.3 V (FEI, TEI, RFRP, SBAD) Min ¾ ¾ ¾ 0.15 ´ AVDD Typ. 8 176.4 88.2 ¾ Max ¾ ¾ ¾ 0.85 ´ AVDD Units bit kHz Conversion input range V CD processor DA conversion block (focus tracking system) Parameter Number of bits Sampling frequency Conversion output range Symbol ¾ ¾ ¾ Test Circuit ¾ ¾ ¾ (FOO, TRO) (FOO, TRO) AVDD = 3.3 V (FOO, TRO) Test Condition Min ¾ ¾ AVSS Typ. 5 2.8 ¾ Max ¾ ¾ AVDD Units bit MHz V CD processor PLL/VCO block Parameter Input/output signal range Frequency characteristic Oscillation center frequency Frequency variable range Symbol ¾ ¾ ¾ ¾ Test Circuit ¾ ¾ ¾ ¾ (LPFN, LPFO) (LPFN-LPFO) -3dB point (Gain = 1) LPFO = VREF [VCOGSL] bit = Low [VCOGSL] bit = High” Test Condition Min AVSS ¾ ¾ -30 -40 Typ. ¾ 8 34 ¾ ¾ Max AVDD ¾ ¾ +30 +40 Units V MHz MHz % CD processor comparator (TEZI, RFZI) Parameter Input range Hysteresis voltage Input resistance Symbol ¾ ¾ Zin2 Test Circuit ¾ ¾ ¾ (TEZI, RFZI) (TEZI, RFZI) VREF reference (TEZI, RFZI) Test Condition Min AVSS -50 ¾ Typ. ¾ ¾ 10 Max AVDD +50 ¾ Units V mV kW 16 2003-04-01 TC94A39FAG/FB CD processor data slicer (RFI/SLCO) Parameter Input amplitude Input resistance DAC resolution DAC output conversion range DAC output impedance Symbol ¾ Zin1 ¾ ¾ ¾ Test Circuit ¾ ¾ ¾ ¾ ¾ Test Condition (RFI) VREF reference (RFI) Set resistance by CD command (SLCO) R-2R DAC (SLCO) R-2R DAC (SLCO) R-2R DAC Min 0.6 ¾ ¾ ¾ 0.75 ´ VREF ¾ Typ. 1.2 20 10 6 ¾ 2.5 Max 2.0 ¾ ¾ ¾ 1.25 ´ VREF ¾ Units VP-P kW bit V kW 1-bit DA converter Parameter Total harmony distortion S/N ratio S/N (2) Dynamic range Crosstalk Analog output level DR CT DACout Symbol THD + N S/N (1) Test Circuit ¾ ¾ ¾ ¾ ¾ Test Condition 1-kHz sine wave, full-scale input Internal Zero detect = OFF Internal Zero detect = ON 1-kHz sine wave, input reduction of -60dB 1-kHz sine wave, full-scale input 1-kHz sine wave, full-scale input Min ¾ 85 95 83 ¾ 790 Typ. -85 91 100 90 -90 825 Max -77 ¾ ¾ ¾ -83 860 Units dB dB dB dB mVrms 17 2003-04-01 TC94A39FAG/FB Package Dimensions Weight: 0.32 g (typ.) 18 2003-04-01 TC94A39FAG/FB Package Dimensions Weight: 0.45 g (typ.) 19 2003-04-01 TC94A39FAG/FB RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 20 2003-04-01