TC94A48FG

TC94A48FG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC94A48FG Single-chip Audio Digital Signal Processor The TC94A48FG is a single-chip audio Digital Signal Processor, incorporating two channels AD converter and six channels DA converter. It can realize many applications, including sound field control, such as hall simulation, digital filters, such as equalizers, surround sound, base boost and more. Features • • • Incorporates a 1-bit Σ-∆ AD converter (2 channels). THD+N: -78 dB (typ.), S/N ratio: 92 dB (typ.) Incorporates a multi-bit Σ-∆ DA converter (6 channels). THD+N: -88 dB (typ.), S/N ratio: 98 dB (typ.) Digital input/output ports Four input ports (8 channels) Four output ports (8 channels) The DSP block specifications are as follows: Data bus : 24 bits Multiplier/adder : 24 bits × 24 bits + 51 bits → 51 bits Accumulator : 51 bits (sign extension: 4 bits) Program ROM : 3072 words × 16 bits Program RAM : 1024 words × 16 bits XRAM : 4096 words × 24 bits YRAM : 1024 words × 24 bits CROM : 1024 words × 24 bits The microcontroller interface can be selected between serial mode and I2C bus mode. Operating supply voltage: 3.3 V (some pins accept 5 V) CMOS silicon structure supports high speed. The package is a 64-pin LQFP (0.5-mm pitch) package. P-LQFP64-1010-0.50E Weight: 0.4 g (typ.) • • • • • 1 2005-09-28 TC94A48FG Block Diagram 11.2896MHz(256fs) LRCKO /MIACK /MIDIO MCKO GPO1 GPO0 BCKO /MICS /MICK MIMD GPI1 GPI0 MILP PLLC XO XI ＰＬＬ Timing Generalperpose port Microcontroller interface /RST BTMD LRCKI0 LRCKI1 BCKI0 BCKI1 SDI0 SDI1 SDI2 SDI3 (8ch) SDO0 ＳＯ SDO1 SDO2 ＳＩ (8ch) 16bit Instruction DSP ΣΔ ΣΔ ＤＡＣ １ｃｈ ＤＡＣ ２ｃｈ ＤＡＣ ３ｃｈ VREF ΣΔ ΣΔ ΣΔ ＤＡＣ ４ｃｈ ＤＡＣ ５ｃｈ ＤＡＣ ６ｃｈ SDO3 DAO1 DAO2 LIN ＡＤＣ Ｌｃｈ ＭＡＦ( →4fs) (4fs rate × 6ch) (4fs rate ×2ch) ΣΔ DAO3 VRI ADVL ADVR VREF VREF REG Buffer (64w ×21b) (4fs rate ×6ch) MUX (4fs rate × 2ch) DAO4 RIN ＡＤＣ Ｒｃｈ DAO5 DAO6 Pin Layout /MIACK /MIDIO MCKO GNDP BCKO 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 XO 2 VDDX 3 VDD1 4 DAO1 5 GND12 6 DAO2 7 VDD23 8 DAO3 9 10 11 12 13 14 15 16 GND56 GND3 GND4 DAO4 DAO5 VDD45 DAO6 VRI VDDP /MICK /MICS GPO0 GPO1 PLLC MILP GPI0 GPI1 GND VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 BTMD MIMD /RST VDD GND TEST1 TEST0 GNDL LIN ADVL VDDA ADVR RIN GNDR GNDX XI 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LRCKO SDO0 SDO1 SDO2 SDO3 BCKI0 BCKI1 LRCKI0 LRCKI1 SDI0 SDI1 SDI2 SDI3 GND VDD VDD6 TC94A48FG 2 2005-09-28 TC94A48FG Pin Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol XO VDDX VDD1 DAO1 GND12 DAO2 VDD23 DAO3 GND3 VRI GND4 DAO4 VDD45 DAO5 GND56 DAO6 VDD6 VDD GND SDI3 SDI2 SDI1 SDI0 LRCKI1 LRCKI0 BCKI1 BCKI0 SDO3 SDO2 SDO1 SDO0 LRCKO BCKO I/O O － － O － O － O － I － O － O － O － － － I I I I I I I I O O O O O O Function Crystal oscillator connecting or clock output pin Power pin for oscillator circuit Analog power pin for DAC1 DAC1 signal output pin Analog ground pin for DAC1/2 DAC2 signal output pin Analog power pin for DAC2/3 DAC3 signal output pin Analog power pin for DAC3 Reference voltage pin for DAC Analog ground pin for DAC4 DAC4 signal output pin Analog power pin for DAC4/5 DAC5 signal output pin Analog ground pin for DAC5/6 DAC6 signal output pin Analog power pin for DAC6 Digital power pin Digital ground pin Audio serial data input pin 3 It connects to GND or VDD pins when if it is unused this pin. Audio serial data input pin 2 It connects to GND or VDD pins when if it is unused this pin. Audio serial data input pin 1 It connects to GND or VDD pins when if it is unused this pin. Audio serial data input pin 0 It connects to GND or VDD pins when if it is unused this pin. LR clock input pin 1 It connects to GND or VDD pins when if it is unused this pin. LR clock input pin 0 It connects to GND or VDD pins when if it is unused this pin. Bit clock input pin 1 It connects to GND or VDD pins when if it is unused this pin. Bit clock input pin 0 It connects to GND or VDD pins when if it is unused this pin. Audio serial data output pin 3 It leaves to open when if it is unused. Audio serial data output pin 2 It leaves to open when if it is unused. Audio serial data output pin 1 It leaves to open when if it is unused. Audio serial data output pin 0 It leaves to open when if it is unused. LR clock output pin It leaves to open when if it is unused. Bit clock output pin It leaves to open when if it is unused. Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Push-pull output Push-pull output Push-pull output Push-pull output Push-pull output Push-pull output Remarks 3 2005-09-28 TC94A48FG Pin No. 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Symbol MCKO GPO1 GPO0 GND VDD GPI1 GPI0 /MICS /MICK /MIDIO /MIACK MILP GNDP PLLC VDDP BTMD I/O O O O － － I I I I Function System clock output pin It leaves to open when if it is unused. General-purpose output pin 1 It leaves to open when if it is unused. General-purpose output pin 0 It leaves to open when if it is unused. Digital ground pin Digital power pin General-purpose input pin 1 It connects to GND or VDD pins when if it is unused this pin. General-purpose input pin 0 It connects to GND or VDD pins when if it is unused this pin. Microcontroller interface: Chip select signal input pin Microcontroller interface: Clock input pin Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input 5V tolerant Schmitt input / Open-drain output, 5V tolerant Open-drain output 5V tolerant Schmitt input 5V tolerant Remarks Push-pull output Open-drain output 5V tolerant Open-drain output 5V tolerant I/O Microcontroller interface: Data input/output pin O I － I － I Microcontroller interface: Acknowledge signal output pin Microcontroller interface: Latch pulse input pin Ground pin for PLL Charge pump for PLL Power pin for PLL Boot mode setting pin Schmitt input It is set to “L” when if software specification does not indicate 5V tolerant since there is deference by each program ROMs. Microcontroller interface: Mode select input pin Reset input pin Digital power pin Digital ground pin Test setting pin 1 Usually it connects to GND pins. Test setting pin 0 Usually it connects to GND pins. Ground pin for ADC-Lch ADC-Lch signal input pin Reference voltage pin for ADC-Lch Analog power pin for ADC Reference voltage pin for ADC-Rch ADC-Rch signal input pin Ground pin for ADC-Rch Ground pin for oscillator circuit Crystal oscillator connecting or clock input pin 5V intolerant Schmitt input 5V intolerant Schmitt input 5V intolerant Schmitt input 5V tolerant Schmitt input 5V tolerant 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MIMD /RST VDD GND TEST1 TEST0 GNDL LIN AVDL VDDA ADVR RIN GNDR GNDX XI I I － － I I － I I － I I － － I Note 1: 5V tolerant pins can have voltage applied even when the power to the device is turned off. 4 2005-09-28 TC94A48FG Description of Operation 1. Timing System The TC94A48FG uses pulses from the XI-XO pins as the reference clock. The system is divided into blocks that use the reference clock directly or by dividing its frequency and blocks that operate on a clock the PLL generates based on the crystal resonation clock. The analog and microcontroller interface blocks operate on the crystal resonation clock while the DSP block operates on the PLL-generated clock. Crystal PLL Dividing Clock for DSP PLL-generated Input= 256fs Divider Clock for Analog Block (256fs) Clock for Analog Block (256fs or 512fs) Timing output to pins (LRCKO,BCKO,MCKO) Crystal precision Figure 1 Timing System The system can divide the clock from the crystal and provide three types of clock from output pins. MCKO Clock Xi fs256 Xo ｆxi = 11.2896MHz (44.1kHz×256) LRCKO, BCKO Clock ADC, DAC ×1/2 ～ ×1/512 LRCKO fs128～fs0.5 MCKO BCKO MAF, ΣΔ Audio I/F MCU I/F ×1/M REFCK VARCK Phase Comp. VCO ×1/Ｊ DSP ×1/Ｎ PLL Figure 2 Block diagram of clock generator circuit 5 2005-09-28 TC94A48FG 1.1 Timing register setting [AIFA] Bit 15-14 Default ＊ Contents BCKi-1 clock frequency 00 32fs 01 48fs 10 64fs 11 64fs BCKi-0 clock frequency 00 32fs 01 48fs 10 64fs 11 64fs LRCKi-1 polarity Lch=Low (interrupt by fall edge) 0 Lch=High (interrupt by rise edge) 1 LRCKi-0 polarity Lch=Low (interrupt by fall edge) 0 Lch=High (interrupt by rise edge) 1 SDi clock select LRCKi-0/BCKi-0 0 LRCKi-1/BCKi-1 1 SDo clock select 0 LRCKi-0/BCKi-0 1 LRCKi-1/BCKi-1 SDi input format 00 LSB justified 01 MSB justified 10 I2S 11 I2 S SDi input bit clock 00 16bit 01 18bit 10 20bit 11 24bit SDo output format 00 LSB justified 01 MSB justified 10 I2 S 11 I2 S SDo output bit clock 00 16bit 01 18bit 10 20bit 11 24bit 13-12 ＊ 11 ＊ 10 ＊ 9 ＊ 8 ＊ 7-6 ＊ 5-4 ＊ 3-2 ＊ 1-0 ＊ Note 2: In 48fs frequency setup of BCKi-1 and BCKi-0, LRCKi/BCKi coresponds only an input, and LRCKo / BCKo does not correspond. 6 2005-09-28 TC94A48FG [MOD_O] Bit 15-12 11 Default ＊ 10 ＊ 9 ＊ 8 ＊ 7 6 5 ＊ 4 ＊ 3 ＊ 2 ＊ 1 ＊ 0 ＊ Contents Reserved Fixed to “0” SDo3 is used as a general-purpose output Po5. 0 Disable 1 Enable SDo2 is used as a general-purpose output Po4. 0 Disable 1 Enable SDo1 is used as a general-purpose output Po3. 0 Disable 1 Enable SDo0 is used as a general-purpose output Po2. 0 Disable 1 Enable Reserved Fixed to “0” Reserved Fixed to “1” Synchronization of LRCKi and LRCKo 0 Disable 1 Enable BCCMP/BCJMP Enable 0 Disable 1 Enable DAC Enable 0 Disable 1 Enable ADC Enable 0 Disable 1 Enable LRCKo is connected to LRCKi1. 0 It does not connect. 1 It connects. LRCKo is connected to LRCKi0. 0 It does not connect. 1 It connects. 7 2005-09-28 TC94A48FG [TMGA] Bit 15-14 13 Default ＊ 12-7 6 ＊ 5-3 2-0 ＊ Contents Reserved Fixed to “0” DSP clock output select 0 Disable 1 Enable Reserved Fixed to “0” MCKO clock output select 1/1 Xi clock 0 1 1/2 Xi clock Reserved Fixed to “0” DSP clock divider setting (1/J) 000 1/1 001 1/2 010 1/4 011 1/8 100 1/16 101 1/3 110 1/6 111 Prohibit [TMGB] Bit 15-14 Default ＊ 13 ＊ 12-8 ＊ 7-0 ＊ Contents LRCKo/BCKo clock select 00 FS1/FS32(BCK=fs32) 01 FS1/FS64(BCK=fs64) 10 FS2/FS64(BCK=fs32) 11 FS2/FS128(BCK=fs64) LRCKo/BCKo output clock select 0 Disable 1 Enable Reference clock divider setting (1/M) 00h 1/1 01h 1/2 ・ ・ 09h 1/10 ・ 1Fh 1/32 Variable clock divider setting (1/N) 00h 1/1 01h 1/2 ・ ・ 3Fh 1/64 ・ FFh 1/256 8 2005-09-28 TC94A48FG 1.2 Timing Output Mode 0 1 2 3 4 LRCKO Pin Output Fixed to GND 1fs 1fs 2fs 2fs BCKO Pin Output Fixed to ground 32fs 64fs 64fs 128fs Remarks Initial Value LRCKO / BCKO Pin Output Settings MCKO Pin Output Settings Mode 0 1 2 Note 3: MCKO Pin Output Fixed to GND XCKI (=XI) 0.5 × XCKI Remarks It can be initialized by reset. Undefined until set by microcontroller or built-in DSP program A setup of a timing output is performed by the built-in firmware. 1.3 Example of oscillator circuit The example of a circuit at the time of the crystal oscillator use in an oscillation part is shown in figure 3. Crystal oscillator connection XI 64 1 XO 11.2896MHz 1MΩ 22pF 22pF Figure 3 Example of oscillator circuit 1.4 Example of PLL circuit A PLL circuit can consist of connecting LPF to a PLLC terminal easily. The example of a circuit is shown in figure 4. VCO GNDP PLLC Phase　 Comp. VDDP 0.1uF 47uF VDD 46 47 48 220Ω 0.01uF Figure 4 Example of PLL circuit The above-mentioned external constant is a reference value. It may change with application. 9 2005-09-28 TC94A48FG 1.5 1.5.1 Audio Input/Output Format Audio Serial Data Input Format The TC94A48FG supports MSB-first input only. In slave mode, it supports all setting formats for the number of bit clock slots. In master mode, it does not support 24 slots. M = MSB L = LSB don't care(invalid data, padded with "0" when read by DSP internal firmware) Timing Chart Remarks Number Data Word MO Length of DE (bit) Slots 0 16 1 16 Format MSBjustified (LSBjustified) I2S M 15 14 13 12 11 M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L 0 Initial Value L 10 9 8 7 6 5 4 3 2 1 0 2 MSBjustified M 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 L 0 3 16 LSBjustified M 15 L 0 4 24 I2S M 15 L 0 Unavailable in master mode(Note) 5 24 6 MSBjustified (LSBjustified) I2S M 23 L 0 M 23 L 0 7 MSBjustified M 15 L 0 8 16 LSBjustified M 15 L 0 9 32 10 I2S M 15 L 0 MSBjustified M 23 L 0 11 24 LSBjustified M 23 L 0 12 I2S M 23 L 0 Note 4: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices). 10 2005-09-28 TC94A48FG 1.5.2 Audio Serial Data Output Format The valid part of data is the same as that for the input format. The TC94A48FG supports MSB-first output only. In slave mode, it supports all setting formats for the number of bit clock slots. In master mode, it does not support 24 slots. M MO DE ＝MSB L ＝LSB Format ＝fixed to “0” (data sent from DSP is ignored) Timing Chart Remarks Number Data Word Length of (bits) SLOT 0 M L 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 16 16 I2S M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 1 L 0 2 M 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 L 0 3 16 M 15 L 0 4 24 I2S M 15 L 0 Unavailable in master mode(Note) 5 M L 0 24 6 I2S 23 M 23 L 0 7 M 15 L 0 8 16 M 15 L 0 9 32 10 I2S M 15 L 0 M 23 L 0 11 24 M 23 L 0 12 I2S M 23 L 0 Note 5: These formats cannot be used in master mode (when LRCK and BCK are supplied to external devices). 11 2005-09-28 TC94A48FG The audio input block and output block support different clock settings. Input and output port settings are, however, shared as follows: LR Clock Setting for Input Block Mode Master Mode Slave Mode Signal Signal delivered to LRCKO pin (crystal resonation clock divided) LRCKI0 pin input LRCKI1 pin input Bit Clock Setting for Input Block Mode Master Mode Slave Mode Signal Signal delivered to BCKO pin (crystal resonation clock divided) BCKI0 pin input BCKI1 pin input LR Clock Setting for Output Block Mode Master Mode Slave Mode Signal Signal delivered to LRCKO pin (crystal resonation clock divided) LRCKI0 pin input LRCKI1 pin input Bit Clock Setting for Input Block Mode Master Mode Slave Mode Signal Signal delivered to BCKO pin (crystal resonation clock divided) BCKI0 pin input BCKI1 pin input 12 2005-09-28 TC94A48FG 2. Microcontroller Interface The TC94A48FG can exchange data with a microcontroller in either normal transmission mode or I2C mode. It uses the MIMD pin to select the mode and inputs/outputs data in MSB-first format. Table 1 shows the features supported and the pins used in each mode. Table 2 shows the bit composition of a 24-bit command. Note 6: This data sheet shows general control methods. Refer to the separate program explanation data sheet for a complete command list or detailed description of control methods. Table 1 Pins Used and Features Supported in Normal Transmission Mode and I2C Mode Transmission Mode Pin Input/Output Input Input Input Output (open-drain) Input, Input / Output (I2C mode) Output (open-drain) Normal Transmission Mode (MIMD=L) Function Chip select Input Latch pulse input Data input / output Clock input Acknowledge output I2C Mode (MIMD=H) Function Not used (fixed to “L”) Not used (fixed to “L”) Data input / output (SDA) Clock input (SCL) Not used /MICS MILP /MIDIO /MICK /MIACK Note 7: The input High voltage for these pins should be VDD-0.2 V to 5.5V. Note 8: The open-drain /MIDIO and /MIACK pins require external pull-up resistors. In I C mode, the /MICK pin also requires a pull-up resistor. The pulled-up voltage for these pins should be VDD-0.2V to 5.5V. Note9: The I C bus write address is 30 h and read address is 31h. 2 2 Table 2 Bit Composition of a 24-bit Command Bit 23-8 7 6 5 4 Function 16-bit address Not used Start program RAM boot Specify soft reset Specify read or write (R/W) Set the number of words to be transmitted Remarks Refer to the command list in the program explanation data sheet. ― "1" starts program RAM boot. "1" triggers a soft reset. "1" specifies a read. 0h” ; 1word 3-0 ↓ “7h” ; 8words 13 2005-09-28 TC94A48FG 2.1 2.1.1 Normal Transmission Mode Data Transfer Format in Normal Transmission Mode Figure 1 shows the data transfer format in normal transmission mode. In normal transmission mode, the system first drives /MICS low and then checks that /MIACK is low before transferring a 24-bit command MSB first. It cannot transfer data if /MIACK is high. The system then reads or writes as many 24-bit data words (one to eight) as specified with the 24-bit command and finally drives /MICS high. For a read, it should also make sure that /MIACK is low after transferring a 24-bit command because /MIACK becomes high temporarily after the command is transferred. 24bit DATA(1～8word) /MICS /MIACK /MILP /MICK /MIDIO COMMAND(24bit) DATA(24bit) DATA(24bit) Figure 5(a) Data Transfer Format in Normal Transmission Mode 2.1.2 (1) Data Transfer Method in Normal Transmission Mode Program boot and program start The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to 003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a program loading process must follow the interrupt vector address. For a program boot, the 24-bit command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to "1" (command = xxxx60h). The command must be followed by 16-bit program data, set in lower bits in 24-bit data. The write address is automatically incremented (by one) from the command (000h). The program boot completes once /MICS is driven high upon transferring the required number of words. The write address for a program boot always starts from the command (000h). To start the program, transfer a 24-bit command with the soft reset bit cleared and then drive /MICS high without transferring data. Figure 6 shows the program boot and program start procedure. 14 2005-09-28 TC94A48FG Hard reset (or soft reset) ／ＭＩＣＳ＝ ”Ｌ ” Check ＭＩＡＣＫ＝ =”Ｌ ” If ＭＩＡＣＫ＝ ”Ｈ ” , wait until ＭＩＡＣＫ＝ ”Ｌ ” Write 24-bit command (program boot = 000060h) Write program data (16bits at address 000h) Write program data (16bits at address 001h) Set the program boot and soft reset bits to “H” Program data stored in lower 16bits Bootable for address of up to 3FFh Write program data (Address 3FEh) Write program data (Address 3FFh) ／ＭＩＣＳ＝ ”Ｈ ” Program boot finished ／ＭＩＣＳ＝ ”Ｌ ” Check ＭＩＡＣＫ＝ =”Ｌ ” If ＭＩＡＣＫ＝ ”Ｈ ” , wait until ＭＩＡＣＫ＝ ”Ｌ ” Write 24-bit command (soft reset off = 000000h) ／ＭＩＣＳ＝ ”Ｈ ” Start program Figure 6 Program Boot and Program Start Procedure 15 2005-09-28 TC94A48FG (2) Writing 24-bit data When the host microcontroller writes data to the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "0" and sets the number of words to be written. Then, it transfers the 24-bit command, followed by a required number of 24-bit data words. Figure 7 shows the 24 bit data write procedure. ／ＭＩＣＳ＝“Ｌ” Check MＩＡＣＫ = “Ｌ” (If MIACK = “H” , wait until MIACK = “L”) Write 24-bit command (data write = xxxx0xh) Set 16-bit address and the number of words to be transferred. Write 24-bit data (1) Can write up to eight 24-bit data words Write 24-bit data (2) Write 24-bit data (n) ／ＭＩＣＳ＝“Ｈ” Data write finished Figure 7 shows the 24-bit data write procedure. 16 2005-09-28 TC94A48FG (3) Reading 24-bit data When the host microcontroller reads data from the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of words to be read. Then, it transfers the 24-bit command, check that /MIACK = "L", and read a required number of 24-bit data words. The host microcontroller should check that /MIACK = "L" because it has to wait until the data to be read is set in the data buffer. Figure 8 shows the 24 bit data read procedure. ／ＭＩＣＳ＝“Ｌ” Check ＭＩＡＣＫ＝“Ｌ” （If MＩＡＣＫ＝“Ｈ” , wait until MIACK = “Ｌ”) Transfer 24-bit command (data read = xxxx1xh) Check ＭＩＡＣＫ＝“Ｌ” （If MＩＡＣＫ＝“Ｈ” , wait until MIACK = “Ｌ”) Can read up to eight 24-bit data word Read 24-bit data (1) Set 16 bit address and the number of words to be transferred. Read 24-bit data (2) Read 24-bit data (n) ／ＭＩＣＳ＝“Ｈ” Data read finished Figure 8 shows the 24-bit data read procedure. 17 2005-09-28 TC94A48FG (4) Triggering and terminating a soft reset A soft reset is required before the system can start a program after program boot or restart a program. A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit cleared terminates a soft reset. When trigging or terminating a soft reset, drive /MICS high after transferring the 24-bit command because no data needs to follow the command. Figure 9 shows the procedure for trigging or terminating a soft reset. ／ＭＩＣＳ＝“Ｌ” Check MＩＡＣＫ = “Ｌ” (If MIACK = “H” , wait until MIACK = “L”) Transfer 24-bit command (soft reset ON/OFF = 0000x0h) ／ＭＩＣＳ＝“Ｈ” If a malfunction occurs, perform a hard reset prior to a soft reset. “1” triggers a reset “0” terminates a reset Soft reset triggered or terminated Figure 9 Procedure for Trigging or Terminating a Soft Reset 18 2005-09-28 TC94A48FG 2.2 2.2.1 I C Bus Mode Data Transfer Format in I C Bus Mode Figure 10 shows the data transfer format in I2C bus mode. In I2C bus mode, the host microcontroller first transfers an I2C address (write = 30h) and then checks that the ACK bit is low. If the ACK bit is high, it retransmits a start condition (without transmitting a stop condition) and then transfers an I2C address of 30h. After transferring an I2C address, the host microcontroller transfers a 24-bit command. When the host microcontroller writes data to the TC94A48FG, it writes as many 24-bit data words as specified with the 24-bit command (1 to 8 words) and then transfers an end condition. When the host microcontroller reads data from the TC94A48FG, it transfers a 24-bit command and then, without transmitting an end condition, transfers an I2C address (read =31h) and check that the ACK bit is low. If the ACK bit is high, the host microcontroller retransmits a start condition (without transmitting a stop condition) and then transfers an I2C address of 31h. After checking that the ACK bit is low, the host microcontroller reads as many 24-bit data words as specified with the 24-bit command (1 to 8 words). During a read, the host microcontroller sets the ACK bit to low after reading every eight bits. The ACK bit accompanying the last eight bits must be set to high, after which the host microcontroller transmits a stop condition. When transferring only a 24-bit command without reading or writing data, transmit an end condition after transferring the command. Figures 11 to 13 show the data transfer formats for writing, reading, and transferring a command only. 2 2 SDA SCL I2C Address(30h) R/W ACK DATA Hi(8bit) ACK DATA Mid(8bit) DATA Low(8bit) ACK I2C Address Start Condition 24bit Command and 24bit DATA (1～8word) Stop Condition Figure 10 Data Transmission Format in I2C Mode (30h) START I2C Address W A COMMAND(H) A 24bit COMMAND COMMAND(M) A COMMAND(L) A 24bit Write DATA(1word～ 8word) DATA(H) A DATA(M) A DATA(L) A STOP Each ACK signal sent from TC94A48FG to Host An interval of at least 1fs(32μs@1fs=32kHz) is required before next START Figure 11 Format for Writing (30h) START I2C Address 24bit COMMAND WA COMMAND(H) (31h) COMMAND(L) 24bit Read DATA(1word～ 8word) RA RD(H) A COMMAND(M) A A START I2C Address A RD(M) A RD(L) A STOP Each ACK signal sent from TC94A48FG to Host An interval of at least 1fs(32μs@1fs=32kHz) is required before next START These ACK signals are sent from host to TC94A48FG This ACK signal is set to “H” by the Host Figure 12 (30h) Format for Reading 24bit COMMAND COMMAND(M) A COMMAND(L) A START I2 C Address W A COMMAND(H) A STOP Each ACK signal sent from TC94A48FG to Host Figure 13 Format for Transferring a Command Only 19 2005-09-28 TC94A48FG 2.2.2 (1) Data Transfer Method in I C Mode Program boot and program start The TC94A48FG has 1k-word RAM assigned to program addresses 000h to 3FFh, in which 000h to 003h are interrupt vector addresses. To enable the TC94A48FG to operate, a program must be booted to an interrupt vector address. If you want to store a program in the area from 004h to 3FFh, a program loading process must follow the interrupt vector address. For a program boot, the 24-bit command transferred upon a reset must have the program RAM boot start bit and soft reset bit set to "1" (command = xxxx60h). The command must be followed by 16-bit program data, set in lower bits in 24-bit data. The write address is automatically incremented (by one) from the command (000h). The program boot completes once an end condition is transmitted upon transferring the required number of words. The write address for a program boot always starts from the command (000h). To start the program, transfer a 24-bit command with the soft reset bit cleared and then transmit an end condition without transferring data. Figure 14 shows the program boot and program start procedure. 2 20 2005-09-28 TC94A48FG Hard reset (or soft reset) ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ Transfer I2C　Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Write 24-bit command (program boot = 000060h) Write program data (16 bits at address 0000h) Write program data (16 bits at address 0001h) Program data stored in lower 16bits Bootable for address of up to 3FFh Set the program boot and soft reset bits to “H” If ACK = “H” , restart from START condition. Write program data (16bits at address 3FEh) Write program data (16bits at address 3FFh) ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Program boot finished ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ Transfer I2C　Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Write 24-bit command (soft reset OFF = 000000h) ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Start program If ACK = “H” , restart from START condition. Figure 14 Program Boot and Program Start Procedure 21 2005-09-28 TC94A48FG (2) Writing 24-bit data When the host microcontroller writes data to the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "0" and sets the number of words to be written. Then, it transfers the 24-bit command, followed by a required number of 24-bit data words. An interval of at least 1fs(32μs@1fs=32kHz) is required before next started. Figure 15 shows the 24 bit data write procedure. ＳＴＡＲＴ　Ｃｏｎｄｉｔｉｏｎ Transfer I2C　Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Write 24-bit command (data write = xxxx0xh) Set 16-bit address and the number of words to be transferred. If ACK = “H” , restart from START condition. Write 24-bit data (1) Can write up to eight 24-bit data words Write 24-bit data (2) Write 24-bit data (n) ＳＴＯＰ　Ｃｏｎｄｉｔｉｏｎ Data write finished Figure 15 shows the 24-bit Data Write Procedure. 22 2005-09-28 TC94A48FG (3) Reading 24-bit data When the host microcontroller reads data from the TC94A48FG during the execution of a program, it sets a 16-bit address in a 24-bit command as well as sets its R/W bit to "1" and sets the number of words to be read. Then, it transfers the 24-bit command, waits about 1fs, and then transfers an I2C address of 31h, followed by a start condition. Finally, it reads a required number of 24-bit data words. During a read, the host microcontroller should set the ACK bits to low but the ACK bit accompanying the last eight bits of data must be high, thus causing the TC94A48FG to relinquish the SDA bus line so that the host microcontroller can transmit a stop condition. The host microcontroller should wait about 1fs after transferring a command because it has to wait until the data to be read is set in the data buffer of the TC94A48FG. Figure 16 shows the 24-bit data read procedure. ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ Transfer I2C Ａｄｄｒｅｓｓ (30h) Check ACK bit = “L” Transfer 24-bit command (data read = xxxx1xh) Wait about 1fs ＳＴＡＲＴ Ｃｏｎｄｉｔｉｏｎ Transfer I2C Ａｄｄｒｅｓｓ (31h) Check ACK bit = “L” Read 24-bit data (1) Read 24-bit data (2) If ACK = “H” , restart from START condition. Set a 16-bit address and the number of words to be transferred. If ACK = “H” , restart from START condition. Can read up to eight 24-bit data words Read 24-bit data (n) ＳＴＯＰ Ｃｏｎｄｉｔｉｏｎ Set the last ACK bit to “H” Data read finished Figure 16 shows the 24-bit Data Read Procedure 23 2005-09-28 TC94A48FG (4) Triggering and terminating a soft reset A soft reset is required before the system can start a program after program boot or restart a program. A 24-bit command with its soft reset bit set to "1" triggers a soft reset and a command with the bit cleared terminates a soft reset. When trigging or terminating a soft reset, transmit a stop condition after transferring the 24-bit command because no data needs to follow the command. Figure 17 shows the procedure for triggering or terminating a soft reset. ＳＴＡＲＴ　Ｃｏｎｄｉｔｉｏｎ Transfer I2C　Ａｄｄｒｅｓｓ（３０ｈ） Check ACK bit = “L” Transfer 24-bit command (soft reset ON/OFF = 0000x0h) ＳＴＯＰ　Ｃｏｎｄｉｔｉｏｎ If ACK = “H” , restart from START Condition. If a system crash(malfunction) occurs, perform a hard reset prior to a soft reset. “1” triggers a reset “0” terminates a reset Soft reset triggered or terminated Figure 17 Procedure for Triggering or Terminating a Soft Reset 3. Write and Read Commands The specifications of write and read commands depend on the built-in program. For details, refer to the program explanation data sheet. 24 2005-09-28 TC94A48FG Maximum Ratings (Ta = 25°C) Characteristics Supply Voltage Input voltage 1 Input voltage 2 (Note10) Power dissipation Operating temperature Storage temperature Symbol VDD Vin1 Vin2 PD Topr Tstg Rating −0.3~4.0 −0.3~VDD + 0.1 −0.3~+ 5.5 400 −40~+85 −55~+150 Unit V V V mW °C °C Note10: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, /MICS, /MICK, /MIDIO, MILP, BTMD, MIMD, /RST Electrical Characteristics (unless otherwise specified, Ta = 25°C, VDD = VDDX = VDD12 = VDD3 = VDD45 = VDD6 = VDDP = VDDA = 3.3V) DC Characteristics Characteristics Operating supply voltage Operating frequency range PLL clock frequency range Operating supply current Symbol VDD fopr fplo IDD Test circuit ⎯ ⎯ ⎯ ⎯ fopr =75MHz (75MIPS) Test Condition Ta = −40~85°C Using PLL for DSP clock Min. 3.0 30 90 ⎯ Typ. 3.3 ⎯ ⎯ 90 Max. 3.6 75 225 100 Unit V MHz MHz mA Clock pins (XI,XO) Characteristics Input voltage(1) “H” level “L” level “H” level “L” level Symbol VIH1 VIL1 IOH1 IOL1 Test circuit ⎯ XI pin VOH = 2.8 V VOL = 0.5 V Test Condition Min. 2.8 ⎯ XO pin ⎯ 3.0 Typ. ⎯ ⎯ ⎯ ⎯ Max. ⎯ 0.5 −2.5 ⎯ Unit V Output voltage(1) ⎯ mA Input pins Characteristics Input voltage(2) Input leakage current “H” level “L” level “H” level “L” level Symbol VIH2 VIL2 IIH2 IIL2 Test circuit ⎯ Test Condition (Note 11) VIN = VDD VIN = 0 V (Note 11), (Note 12) Min. 2.8 ⎯ ⎯ −10 Typ. ⎯ ⎯ ⎯ ⎯ Max. ⎯ 0.5 10 ⎯ Unit V ⎯ µA Note 11: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, /MICS, /MICK, /MIDIO, MILP, BTMD, MIMD, /RST, TEST0~1, PLLC Note 12 : XI 25 2005-09-28 TC94A48FG Output pins Characteristics Output current(2) “H” level “L” level “H” level “L” level “L” level Symbol IOH2 IOL2 IOH3 IOL3 IOL4 IOZ5 Test circuit ⎯ Test Condition VOH = 2.8 V VOL = 0.5 V VOH = 2.8 V VOL = 0.5 V VOL = 0.5 V VOH = VDD (Note 13) (Note 13) (Note 14) (Note 14) (Note 15) (Note 15) Min. ⎯ 5 ⎯ 3 5 ⎯ Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max. −5 ⎯ −3 ⎯ ⎯ ±10 µA mA Unit Output current(3) Output current(4) Output-off leakage current ⎯ ⎯ ⎯ Note 13: SDO0~3, LRCKO, BCKO (push-pull output) Note 14: MCKO (push-pull output) Note 15: GPO0~1, /MIDIO, /MIACK (open-drain output) 26 2005-09-28 TC94A48FG AC Characteristics • • • The gain through the firmware is 0 dB (pass-through), except for +2 dB for DC-cut-HPF. VDD (for all power supplies) = 3.3V, Ta = 25°C Test circuit MCU Digital SG/Analyzer I/F 0.01uF 220Ω 48 39 49 VDDP 47 PLLC 46 GNDP 45 MILP 44 /MIACK 43 /MIDIO 42 /MICK 10kΩ 10kΩ 10kΩ 10kΩ 41 /MICS 40 GPI0 39 GPI1 38 VDD 37 GND 36 GPO0 35 GPO1 34 MCKO GND56 15 33 65 BCKO 39 32 LRCKO SDO0 31 SDO1 30 SDO2 29 SDO3 28 BCKI0 27 BCKI1 26 BTMD 50 MIMD 51 /RST 52 VDD 53 GND 54 TEST1 55 TEST0 Lch 1kΩ 2200pF 1kΩ 2200pF 4.7μF 4.7μF AGND 56 GNDL 57 LIN TC94A48FG LRCKI0 25 LRCKI1 24 SDI0 23 SDI1 22 SDI2 21 SDI3 20 GND 19 VDD 18 47μF 47μF 58 ADVL 59 VDDA 60 ADVR 61 RIN 62 GNDR 63 GNDX GND12 VDD23 GND3 GND4 VDDX DAO1 DAO2 DAO3 DAO4 DAO5 DAO6 VDD1 64 XI XO 1 VDD45 VRI Rch VDD6 17 2 3 4 5 6 7 8 9 10 11 12 13 14 16 47uF 1MΩ 22pF Analog VDD Analog GND Digital Digital VDD GND 22pF 270Ω 2200pF 10μF 10kΩ 270Ω 270Ω 270Ω 270Ω 270Ω 2200pF 10μF 10kΩ 2200pF 2200pF 10μF 10μF 10kΩ 10kΩ 2200pF 2200pF 10μF 10μF 10kΩ 10kΩ DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 27 2005-09-28 TC94A48FG AD Converter: LIN and RIN pin input, Vin_ref: 1 kHz, 800 mVrms (unless otherwise specified), SDO0 pin output monitored Characteristics Maximum input signal Input impedance S/N ratio THD + N Crosstalk Dynamic range L to R gain error Symbol Vin Zin S/Na THDa CTa DRa Vdlr Test Condition Input level that drives ADC output to digital full scale. Each of LIN and RIN pins A-Weight, Input AC shorted, Crystal: 11.2896 MHz 20 kHz LPF, Crystal: 11.2896 MHz 20 kHz LPF, Lch to Rch/ Rch to Lch, Crystal: 11.2896 MHz A-Weight, -60dB for Vin_ref input, Crystal: 11.2896 MHz Min. ⎯ 20 87 ⎯ ⎯ 87 −0.5 Typ. ⎯ 27 93 −83 −85 93 0 Max. 800 34 ⎯ −77 −78 ⎯ 0.5 dB Unit mVrms kΩ DA Converter: SDO0 to SDO3 pin input, SDI0_ref = 0 dBFS, 1 kHz (unless otherwise specified), DAO1 to DAO6 pin output monitored. Characteristics Output signal level S/N ratio THD + N Crosstalk Dynamic range Channel-to-channel gain error Symbol Ao S/Nd THDd CTd DRd Vddo Test Condition Output voltage at digital full-scale input A-Weight, Crystal: 11.2896 MHz 20 kHz LPF Crystal: 11.2896 MHz 20 kHz LPF, Crystal: 11.2896 MHz A-Weight Crystal: 11.2896 MHz DAO1~DAO6 pin output monitored. Min. 790 90 ⎯ ⎯ 88 −0.5 Typ. 830 98 −88 −90 95 0 Max. 870 ⎯ −75 −83 ⎯ 0.5 dB Unit mVrms 28 2005-09-28 TC94A48FG Timing Clock input pin (XI) Characteristics Clock cycle Clock “H” duration Clock “L” duration Symbol tXI tXIH tXIL Test Condition fs=32kHz~48kHz, 256fs input ⎯ ⎯ Min. 80.0 40.0 40.0 Typ. 88.6 44.3 44.3 Max. 124.0 62.0 62.0 ns Unit Reset pin (/RST) Characteristics Standby time Reset pulse width Symbol tRRS tWRS Test Condition ⎯ ⎯ Min. 10 1.0 Typ. ⎯ ⎯ Max. ⎯ ⎯ Unit ms µs Note 16: The /RST pin must be driven low at power-on. Audio Serial Interface (BCKI0~1, BCKO, LRCKI0~1, LRCKO, SDI0~3, SDO0~3) Characteristics LRCKIx setup time LRCKIx hold time SDIx setup time SDIx hold time BCKIx clock cycle BCKIx clock “H” duration BCKIx clock “L” duration SDOx output delay(1) SDOx output delay(2) LRCKO output delay Symbol tLBS tLBH tSDI tHDI tBCK tBCH tBCL tDO1 tDO2 tDCLR CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF fs = 48 kHz or lower BCKI0 and BCKI1 input: 64 fs or lower Test Condition Min. 75 −75 50 50 300 150 150 ⎯ ⎯ ⎯ Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max. ⎯ 75 ⎯ ⎯ ⎯ ⎯ ⎯ 60 60 40 ns Unit 29 2005-09-28 TC94A48FG Microcontroller Interface Normal Transmission Mode (/MICS, /MICK, /MIDIO, MILP, /MIACK) Characteristics Standby time /MICS fall to /MICK rise setup time /MIACK fall to /MICK rise setup time /MICK clock cycle /MICK “L” duration /MICK “H” duration /MICK rise to /MILP fall setup time MILP “L” duration /MIDIO input data setup time /MIDIO input data hold time /MIDIO output data delay /MICS “H” duration /MIACK output delay MILP rise to /MICS rise setup time Symbol tSTB t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Test Condition ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Min. 20 0.5 0.5 1.0 0.5 0.5 0.5 0.5 0.5 0.5 ⎯ 0.5 ⎯ 0.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.5 ⎯ 1.0 ⎯ µs Typ. ⎯ ⎯ ⎯ Max. ⎯ ⎯ ⎯ Unit ms ⎯ ⎯ ⎯ ⎯ Note 17: The /MIACK output timing and /MIACK "H" duration vary with the firmware. I2C Mode (/MICK, /MIDIO) Characteristics /MICK clock frequency /MICK “H” duration /MICK “L” duration Data setup time Data hold time Transmission start condition hold time Repeated transmission start condition setup time Transmission end condition setup time Data transmission interval I C rise time I C fall time 2 2 Symbol fIFCK tH tL tDS tDH tSCH tSCS tECS tBUF tR tF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF CL = 400 pF Test Condition Min. 0 0.6 1.3 0.2 0 0.6 0.6 0.6 1.3 ⎯ ⎯ Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max. 400 ⎯ ⎯ ⎯ 0.9 ⎯ ⎯ ⎯ ⎯ 0.3 0.3 Unit kHz µs 30 2005-09-28 TC94A48FG AC Characteristics Measurement Points 1. Clock Pin (XI) XI 50% tXIH tXI tXIL 2. Reset Pin (/RST) 100% VDD 0% /RST tRRS 50% tWRS 90% 3. Audio Serial Interface (LRCKIx, BCKIx, SDIx, LRCKO, BCKO, SDOx, MCKO) XI 50% tDCLR 50% 0% tBCK tBCL LRCKIx/ LRCKO tLBH BCKIx/ BCKO tLBS tBCH 100% LRCKO SDIx tSDI SDOx tDO1 tDO2 tHDI 31 2005-09-28 TC94A48FG 4. Microcontroller Interface 4-1. Serial Mode (/MICS, /MICK, /MIDIO, MILP, /MIACK) /RST /MICS tSTB t1 /MICS t2 /MIACK t3 t4 /MICK t5 t6 t7 t8 t9 DATA IN t12 MILP /MIDIO /MIDIO t10 DATA OUT t13 t11 /MICS /MIACK /MICK t7 t6 DATA IN MILP /MIDIO /MIDIO DATA OUT 32 2005-09-28 TC94A48FG 4-2. I C Mode (/MICK, /MIDIO) 2 /RST /MIDIO (SDA) tSTB tBUF /MIDIO (SDA) /MICK (SCL) tSCH tR tL tH tDS tDH tSCS tF tECS 33 2005-09-28 TC94A48FG Equivalent Circuit Diagrams Type Equivalent Circuit Diagram Schmitt Input Description A Schmitt Input. 5V tolerant. B A voltage can be applied to this pin even when the power supply pin of the TC94A48FG is driven to 0V. Push-pull output. C The amplitude is 3.3 V. If external devices require 5V amplitude, perform a level conversion. Open-drain output This pin must be pulled up to VDD or 5V externally. D Schmitt input and open-drain output This pin must be pulled up to VDD or 5V externally. A voltage can be applied to this pin even when the power supply pin of the TC94A48FG is driven to 0V. E [Caution] When using the pin for input, connect it to an open-drain output pin of an external device. Type A: TEST0, TEST1 Type B: SDI0~3, LRCKI0~1, BCKI0~1, GPI0~1, BTMD, MILP, /MICK, /MICS, MIMD, /RST Type C: SDO0~3, MCKO, BCKO, LRCKO Type D: GPO0~1, /MIACK Type E: /MIDIO 34 2005-09-28 TC94A48FG Package Dimensions L Q F P 6 4 - P- 1 0 1 0 - 0 . 5 0 E U n it: m m (Note) Palladium plate Weight : 0.4g (typ.) 35 2005-09-28 TC94A48FG 36 2005-09-28