THGBMFG7C1LBAIL
TOSHIBA e-MMC Module
16GB THGBMFG7C1LBAIL
INTRODUCTION
THGBMFG7C1LBAIL is 16GB density of e-MMC Module product housed in 153 ball BGA package. This unit is utilized
advanced TOSHIBA NAND flash device(s) and controller chip assembled as Multi Chip Module. THGBMFG7C1LBAIL
has an industry standard MMC protocol for easy use.
FEATURES
THGBMFG7C1LBAIL Interface
THGBMFG7C1LBAIL has the JEDEC/MMCA Version 5.1 interface with either 1-I/O, 4-I/O and 8-I/O mode support.
(*) MMCA Version 5.1 is under discussion in JEDEC.
Pin Connection
P-WFBGA153-1113-0.50 (11.5mm x 13mm, H0.8mm max. package)
14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
13
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
11
NC
NC
NC
NC
NC
NC
10
NC
NC
NC
VSF VSF RFU Vss
Vcc RFU
NC
NC
RFU
9
NC
NC
NC
VSF
Vcc
NC
NC
NC
8
NC
NC
NC
RFU
Vss
NC
NC
NC
7
RFU NC
NC
Vss
6
Vss
DAT7
VccQ
Vcc
5
DAT2
DAT6
NC
4
DAT1
DAT5
VssQ
NC index
3
DAT0
DAT4
NC
NC
NC
NC
RFU NC
NC
NC
2
NC
DAT3 VDDi
NC
NC
NC
NC
NC
NC
1
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
G
H
Top View
RFU Vcc
Vss
DS
Vss
RFU
NC
NC
RFU
RFU
CLK
NC
VssQ
RST_n
CMD VssQ VccQ
VccQ
VccQ
VssQ
NC
NC
NC
VccQ
NC
NC
NC
VssQ
NC
NC
NC
NC
NC
NC
NC
J
K
L
M
N
P
Pin Number
Name
Pin Number
Name
Pin Number
Name
Pin Number
Name
A3
DAT0
C2
VDDi
J5
Vss
N4
VccQ
A4
DAT1
C4
VssQ
J10
Vcc
N5
VssQ
A5
DAT2
C6
VccQ
K5
RST_n
P3
VccQ
A6
Vss
E6
Vcc
K8
Vss
P4
VssQ
B2
DAT3
E7
Vss
K9
Vcc
P5
VccQ
B3
DAT4
F5
Vcc
M4
VccQ
P6
VssQ
B4
DAT5
G5
Vss
M5
CMD
B5
DAT6
H5
DS
M6
CLK
B6
DAT7
H10
Vss
N2
VssQ
NC: No Connect, shall be connected to ground or left floating.
RFU: Reserved for Future Use, shall be left floating for future use.
VSF: Vendor Specific Function, shall be left floating.
1
Jan. 23th, 2015
THGBMFG7C1LBAIL
Part Numbers
Available e-MMC Module Products – Part Numbers
TOSHIBA Part Number
Density
Package Size
NAND Flash Type
Weight
THGBMFG7C1BAIL
16GB
11.5mm x 13mm x 0.8mm(max)
1 x 128Gbit 15nm
0.18g typ.
Operating Temperature and Humidity Conditions
-25°C to +85°C, and 0%RH to 95%RH non-condensing
Storage Temperature and Humidity Conditions
-40°C to +85°C, and 0%RH to 95%RH non-condensing
Performance
X8 mode/ Sequential access (4MByte access size)
Typ. Performance
TOSHIBA Part Number
Density
NAND Flash Type
Interleave
Frequency
Operation
/Mode
Read
Write
1.8V
45
25
3.3V
45
25
1.8V
90
25
3.3V
90
25
HS200
1.8V
180
25
HS400
1.8V
220
25
52MHz/SDR
THGBMFG7C1LBAIL
16GB
1 x 128Gbit 15nm
Non
Interleave
[MB/sec]
VccQ
52MHz/DDR
Power Supply
Vcc =
VccQ =
2.7V to 3.6V
1.7V to 1.95V / 2.7V to 3.6V
Operating Current (RMS)
The measurement for max RMS current is done as average RMS current consumption over a period of 100ms
TOSHIBA Part
Number
Density
NAND Flash Type
Interleave
Operation
Frequency
/Mode
Iccq
Icc
1.8V
95
40
3.3V
110
40
1.8V
115
40
3.3V
140
40
HS200
1.8V
170
45
HS400
1.8V
215
45
52MHz/SDR
THGBMFG7C1LBAIL
16GB
1 x 128Gb 15nm
2
Non
Interleave
VccQ
Max Operating
Current [mA]
52MHz/DDR
Jan. 23th, 2015
THGBMFG7C1LBAIL
Sleep Mode Current
TOSHIBA Part Number
THGBMFG7C1LBAIL
Density
16GB
NAND Flash Type
1 x 128Gbit 15nm
Interleave
Operation
Non
Interleave
Iccqs [μA]
Iccqs+Iccs [μA]
Typ. *1
Max. *2
Typ. *1
Max. *2
100
515
120
590
*1 : The conditions of typical values are 25°C and VccQ = 3.3V or 1.8V.
*2 : The conditions of maximum values are 85°C and VccQ = 3.6V or 1.95V.
3
Jan. 23th, 2015
THGBMFG7C1LBAIL
Product Architecture
The diagram in Figure 1 illustrates the main functional blocks of the THGBMFG7C1LBAIL.
Specification of the CREG and recommended values of the CVCC, and CVCCQ in the Figure 1 are as follows.
Parameter
Symbol
VDDi capacitor value
CREG
Unit
Min.
Typ.
Max.
μF
0.10
-
2.2*
Except HS400
μF
1.00
-
2.2*
HS400
VCC capacitor value
CVCC
μF
-
2.2 + 0.1
-
VCCQ capacitor value
CVCCQ
μF
-
2.2 + 0.1
-
Remark
* Toshiba recommends that the value should be usually applied as the value of CREG.
Figure 1 THGBMFG7C1LBAIL Block Diagram
4
Jan. 23th, 2015
THGBMFG7C1LBAIL
PRODUCT SPECIFICATIONS
Package Dimensions
P-WFBGA153-1113-0.50 (11.5mm x 13mm, H0.8mm max. package)
Unit: mm
Remark: Data A, B and S are defined by the least square method of all solder balls
5
Jan. 23th, 2015
THGBMFG7C1LBAIL
Density Specifications
Density
Part Number
Interleave
Operation
User Area Density
[Bytes]
SEC_COUNT in
Extended CSD
16GB
THGBMFG7C1LBAIL
Non Interleave
15,758,000,128
0x01D5A000
1) User area density shall be reduced if enhanced user data area is defined.
Register Informations
OCR Register
OCR bit
VDD Voltage window
Value
[6:0]
Reserved
000 0000b
[7]
1.70-1.95
1b
[14:8]
2.0-2.6
000 0000b
[23:15]
2.7-3.6
1 1111 1111b
[28:24]
Reserved
0 0000b
[30:29]
Access Mode
10b
[31]
( card power up status bit (busy) )
1
1) This bit is set to LOW if the Device has not finished the power up routine.
CID Register
Name
Field
Width
Value
[127:120]
Manufacturer ID
MID
8
0001 0001b
[119:114]
Reserved
-
6
0b
[113:112]
Device/BGA
CBX
2
01b
[111:104]
OEM/Application ID
OID
8
0b
[103:56]
Product name
PNM
48
0x30 31 36 47 37 30 (016G70).
[55:48]
Product revision
PRV
8
0x00
[47:16]
Product serial
PSN
32
Serial number
[15:8]
Manufacturing date
MDT
8
see-JEDEC Specification
[7:1]
CRC7 checksum
CRC
7
CRC7
Not used, always ‘1’
-
1
1b
CID-slice
[0]
6
Jan. 23th, 2015
THGBMFG7C1LBAIL
CSD Register
CSD-slice
Name
Field
Width
Cell Type
Value
[127:126]
CSD structure
CSD_STRUCTURE
2
R
0x3
[125:122]
System specification version
SPEC_VERS
4
R
0x4
[121:120]
Reserved
-
2
R
0x0
[119:112]
Data read access-time 1
TAAC
8
R
0x27
NSAC
8
R
0x00
[111:104]
Data read access-time 2 in CLK cycles
(NSAC * 100)
[103:96]
Max. bus clock frequency
TRAN_SPEED
8
R
0x32
[95:84]
Device command classes
CCC
12
R
0x0F5
[83:80]
Max. read data block length
READ_BL_LEN
4
R
0x9
[79:79]
Partial blocks for read allowed
READ_BL_PARTIAL
1
R
0x0
[78:78]
Write block misalignment
WRITE_BLK_MISALIGN
1
R
0x0
[77:77]
Read block misalignment
READ_BLK_MISALIGN
1
R
0x0
[76:76]
DSR implemented
DSR_IMP
1
R
0x0
[75:74]
Reserved
-
2
R
0x0
[73:62]
Device size
C_SIZE
12
R
0xFFF
[61:59]
Max. read current @ VDD min.
VDD_R_CURR_MIN
3
R
0x7
[58:56]
Max. read current @ VDD max.
VDD_R_CURR_MAX
3
R
0x7
[55:53]
Max. write current @ VDD min.
VDD_W_CURR_MIN
3
R
0x7
[52:50]
Max. write current @ VDD max.
VDD_W_CURR_MAX
3
R
0x7
[49:47]
Device size multiplier
C_SIZE_MULT
3
R
0x7
[46:42]
Erase group size
ERASE_GRP_SIZE
5
R
0x1F
[41:37]
Erase group size multiplier
ERASE_GRP_MULT
5
R
0x1F
[36:32]
Write protect group size
WP_GRP_SIZE
5
R
0x07
[31:31]
Write protect group enable
WP_GRP_ENABLE
1
R
0x1
[30:29]
Manufacturer default ECC
DEFAULT_ECC
2
R
0x0
[28:26]
Write speed factor
R2W_FACTOR
3
R
0x1
[25:22]
Max. write data block length
WRITE_BL_LEN
4
R
0x9
[21:21]
Partial blocks for write allowed
WRITE_BL_PARTIAL
1
R
0x0
[20:17]
Reserved
-
4
R
0x0
[16:16]
Content protection application
CONTENT_PROT_APP
1
R
0x0
[15:15]
File format group
FILE_FORMAT_GRP
1
R/W
0x0
[14:14]
Copy flag (OTP)
COPY
1
R/W
0x0
[13:13]
Permanent write protection
PERM_WRITE_PROTECT
1
R/W
0x0
[12:12]
Temporary write protection
TMP_WRITE_PROTECT
1
R/W/E
0x0
[11:10]
File format
FILE_FORMAT
2
R/W
0x0
[9:8]
ECC code
ECC
2
R/W/E
0x0
[7:1]
CRC
CRC
7
R/W/E
CRC
[0]
Not used, always ‘1’
-
1
-
0x1
7
Jan. 23th, 2015
THGBMFG7C1LBAIL
Extended CSD Register(TBD)
CSD-slice
Name
Field
Size
(Bytes)
Cell Type
Value
[511:506]
Reserved
-
6
-
All ‘0’
[505]
Extended Security Commands Error
EXT_SECURITY_ERR
1
R
0x00
[504]
Supported Command Sets
S_CMD_SET
1
R
0x01
[503]
HPI features
HPI_FEATURES
1
R
0x01
[502]
Background operations support
BKOPS_SUPPORT
1
R
0x01
[501]
Max_packed read commands
MAX_PACKED_READS
1
R
0x3F
[500]
Max_packed write commands
MAX_PACKED_WRITES
1
R
0x3F
[499]
Data Tag Support
DATA_TAG_SUPPORT
1
R
0x01
[498]
Tag Unit Size
TAG_UNIT_SIZE
1
R
0x03
[497]
Tag Resource Size
TAG_RES_SIZE
1
R
0x00
[496]
Context management capabilities
CONTEXT_CAPABILITIES
1
R
0x7F
[495]
Large Unit size
LARGE_UNIT_SIZE_M1
1
R
0x00
[494]
Extended partitions attribute support
EXT_SUPPORT
1
R
0x03
[493]
Supported modes
SUPPORTED_MODES
1
R
0x01
[492]
FFU features
FFU_FEATURES
1
R
0x00
[491]
Operation codes timeout
OPERATION_CODES_TIMEOUT
1
R
0x00
[490:487]
FFU Argument
FFU_ARG
4
R
0xFFFFFFFF
[486]
Barrier support
BARRIER_SUPPORT
1
R
0x01
[485:309]
Reserved
-
177
-
All ‘0’
[308]
CMD Queuing Support
CMDQ_SUPPORT
1
R
0x00
[307]
CMD Queuing Depth
CMDQ_DEPTH
1
R
0x00
[306]
Reserved
-
1
-
0x00
[305:302]
Number of FW sectors correctly programmed
4
R
All ’0’
[301:270]
Vendor proprietary health report
32
R
All ‘0’
[269]
Device life time estimation type B
DEVICE_LIFE_TIME_EST_TYP_B
1
R
0x00
[268]
Device life time estimation type A
DEVICE_LIFE_TIME_EST_TYP_A
1
R
0x01
[267]
Pre EOL information
PRE_EOL_INFO
1
R
0x01
[266]
Optimal read size
OPTIMAL_READ_SIZE
1
R
0x08
[265]
Optimal write size
OPTIMAL_WRITE_SIZE
1
R
0x08
[264]
Optimal trim unit size
OPTIMAL_TRIM_UNIT_SIZE
1
R
0x01
[263:262]
Device version
DEVICE_VERSION
2
R
0x00
[261:254]
Firmware version
FIRMWARE_VERSION
8
R
0x02
[253]
Power class for 200MHz, DDR at VCC=3.6V
PWR_CL_DDR_200_360
1
R
0xCC
[252:249]
Cache size
CACHE_SIZE
4
R
0x00001000
[248]
Generic CMD6 timeout
GENERIC_CMD6_TIME
1
R
0x0A
[247]
Power off notification(long) timeout
POWER_OFF_LONG_TIME
1
R
0x32
[246]
Background operations status
BKOPS_STATUS
1
R
0x00
[245:242]
Number of correctly programmed sectors
4
R
0x00000000
[241]
1
1
R
0x1E
st
initialization time after partitioning
NUMBER_OF_FW_SECTORS_C
ORRECTLY_PROGRAMMED
VENDOR_PROPRIETARY
_HEALTH_REPORT
CORRECTLY
_PRG_SECTORS_NUM
INI_TIMEOUT_AP
8
Jan. 23th, 2015
THGBMFG7C1LBAIL
CSD-slice
Name
Field
Size
(Bytes)
Cell Type
Value
[240]
Cache Flushing Policy
CACHE_FLUSH_POLICY
1
R
0x01
[239]
Power class for 52MHz, DDR @ 3.6V
PWR_CL_DDR_52_360
1
R
0x66
[238]
Power class for 52MHz, DDR @ 1.95V
PWR_CL_DDR_52_195
1
R
0xBB
[237]
Power class for 200MHz @ 3.6V
PWR_CL_200_360
1
R
0xBB
[236]
Power class for 200MHz @ 1.95V
PWR_CL_200_195
1
R
0xBB
MIN_PERF_DDR_W_8_52
1
R
0x00
MIN_PERF_DDR_R_8_52
1
R
0x64
[235]
[234]
Minimum Write Performance for 8bit
@ 52MHz in DDR mode
Minimum Read Performance for 8bit
@ 52MHz in DDR mode
[233]
Reserved
-
1
-
0x00
[232]
TRIM Multiplier
TRIM_MULT
1
R
0x01
[231]
Secure Feature support
SEC_FEATURE_SUPPORT
1
R
0x55
[230]
Secure Erase Multiplier
SEC_ERASE_MULT
1
R
0xF3
[229]
Secure TRIM Multiplier
SEC_TRIM_MULT
1
R
0xF7
[228]
Boot information
BOOT_INFO
1
R
0x07
[227]
Reserved
-
1
R
0x00
[226]
Boot partition size
BOOT_SIZE_MULTI
1
R
0x20
[225]
Access size
ACC_SIZE
1
R
0x08
[224]
High-capacity erase unit size
HC_ERASE_GRP_SIZE
1
R
0x08
[223]
High-capacity erase timeout
ERASE_TIMEOUT_MULT
1
R
0x11
[222]
Reliable write sector count
REL_WR_SEC_C
1
R
0x01
[221]
High-capacity write protect group size
HC_WP_GRP_SIZE
1
R
0x01
[220]
Sleep current (Vcc)
S_C_VCC
1
R
0x07
[219]
Sleep current (VccQ)
S_C_VCCQ
1
R
0x09
1
R
0x0A
PRODUCTION_STATE
[218]
Production state awareness timeout
[217]
Sleep/awake timeout
S_A_TIMEOUT
1
R
0x14
[216]
Sleep Notification Timeout
SLEEP_NOTIFICATION_TIME
1
R
0x10
[215:212]
Sector Count
SEC_COUNT
4
R
0x01D5A000
[211]
Secure Write Protect Information
SECURE_WP_INFO
1
R
0x00
MIN_PERF_W_8_52
1
R
0x00
MIN_PERF_R_8_52
1
R
0x78
MIN_PERF_W_8_26_4_52
1
R
0x00
MIN_PERF_R_8_26_4_52
1
R
0x46
MIN_PERF_W_4_26
1
R
0x00
MIN_PERF_R_4_26
1
R
0x1E
[210]
[209]
[208]
[207]
[206]
[205]
Minimum Write Performance for 8bit
@ 52MHz
Minimum Read Performance 8bit
@ 52MHz
Minimum Write Performance for 8bit
@ 26MHz, for 4bit at 52MHz
Minimum Read Performance for 8 bit
@ 26MHz, for 4bit at 52MHz
Minimum Write Performance for 4bit
@ 26MHz
Minimum Read Performance for 4bit
@ 26MHz
_AWARENESS_TIMEOUT
9
Jan. 23th, 2015
THGBMFG7C1LBAIL
CSD-slice
Name
Field
Size
(Bytes)
Cell Type
Value
[204]
Reserved
-
1
-
0x00
[203]
Power class for 26MHz @ 3.6V
PWR_CL_26_360
1
R
0x55
[202]
Power class for 52MHz @ 3.6V
PWR_CL_52_360
1
R
0x55
[201]
Power class for 26MHz @ 1.95V
PWR_CL_26_195
1
R
0xBB
[200]
Power class for 52MHz @ 1.95V
PWR_CL_52_195
1
R
0xBB
[199]
Partition switching timing
PARTITION_SWITCH_TIME
1
R
0x0A
[198]
Out-of-interrupt busy timing
OUT_OF_INTERRUPT_TIME
1
R
0x0A
[197]
I/O Driver Strength
DRIVER_STRENGTH
1
R
0x1F
[196]
Device Type
DEVICE_TYPE
1
R
0x57
[195]
Reserved
-
1
-
0x00
[194]
CSD structure version
CSD_STRUCTURE
1
R
0x02
[193]
Reserved
-
1
-
0x00
[192]
Extended CSD revision
EXT_CSD_REV
1
R
0x07
[191]
Command Set
CMD_SET
1
R/W/E_P
0x00
[190]
Reserved
-
1
-
0x00
[189]
Command set revision
CMD_SET_REV
1
R
0x00
[188]
Reserved
-
1
-
0x00
POWER_CLASS
1
R/W/E_P
0x00
1
-
0x00
1
[187]
Power class
[186]
Reserved
-
[185]
High-speed interface timing
HS_TIMING
1
R/W/E_P
0x00
[184]
Strobe Support
STROBE_SUPPORT
1
R
0x01
[183]
Bus width mode
BUS_WIDTH
1
W/E_P
0x00
[182]
Reserved
-
1
-
0x00
[181]
Erased memory content
ERASED_MEM_CONT
1
R
0x00
[180]
Reserved
-
1
-
0x00
[179]
Partition configuration
PARTITION_CONFIG
1
[178]
Boot config protection
BOOT_CONFIG_PROT
1
[177]
Boot bus width
BOOT_BUS_WIDTH
1
R/W/E
0x00
[176]
Reserved
-
1
-
0x00
[175]
High-density erase group definition
ERASE_GROUP_DEF
1
R/W/E_P
0x00
[174]
Boot write protection status registers
BOOT_WP_STATUS
1
R
0x00
[173]
Boot area write protection register
BOOT_WP
1
[172]
Reserved
-
1
R/W/E &
R/W/E_P
R/W &
R/W/C_P
R/W &
R/W/C_P
-
0x00
0x00
0x00
0x00
R/W,
[171]
User area write protection register
USER_WP
1
R/W/C_P
&
0x00
R/W/E_P
[170]
Reserved
-
1
-
0x00
[169]
FW configuration
FW_CONFIG
1
R/W
0x00
10
Jan. 23th, 2015
THGBMFG7C1LBAIL
CSD-slice
Name
Field
Size
(Bytes)
Cell Type
Value
[168]
RPMB Size
RPMB_SIZE_MULT
1
R
0x20
[167]
Write reliability setting register
WR_REL_SET
1
R/W
0x1F
[166]
Write reliability parameter register
WR_REL_PARAM
1
R
0x15
[165]
Start Sanitize operation
SANITIZE_START
1
W/E_P
0x00
[164]
Manually start
BKOPS_START
1
W/E_P
0x00
[163]
Enable background operations handshake
BKOPS_EN
1
R/W
0x00
[162]
H/W reset function
RST_n_FUNCTION
1
R/W
0x00
[161]
HPI management
HPI_MGMT
1
R/W/E_P
0x00
[160]
Partitioning Support
PARTITIONING_SUPPORT
1
R
0x07
MAX_ENH_SIZE_MULT
3
R
0x000757
background operations
2
[159:157]
Max Enhanced Area Size
[156]
Partitions attribute
PARTITIONS_ATTRIBUTE
1
R/W
0x00
[155]
Partitioning Setting
PARTITION_SETTING_COMPLET
ED
1
R/W
0x00
[154:143]
General Purpose Partition Size
3
GP_SIZE_MULT
12
R/W
0x00
[142:140]
Enhanced User Data Area Size
4
ENH_SIZE_MULT
3
R/W
0x00
[139:136]
Enhanced User Data Start Address
ENH_START_ADDR
4
R/W
0x00
[135]
Reserved
-
1
-
0x00
[134]
Bad Block Management mode
SEC_BAD_BLK_MGMNT
1
R/W
0x00
1
R/W/E
0x00
TCASE_SUPPORT
1
W/E_P
0x00
PERIODIC_WAKEUP
1
R/W/E
0x00
1
R
0x01
[133]
Production state awareness
PRODUCTION_STATE
5
_AWARENESS
1
[132]
Package Case Temperature is controlled
[131]
Periodic Wake-up
[130]
Program CID/CSD in DDR mode support
[129:128]
Reserved
-
2
-
All ‘0’
[127:64]
Vendor Specific Fields
VENDOR_SPECIFIC_FIELD
1
-
-
[63]
Native sector size
NATIVE_SECTOR_SIZE
1
R
0x01
[62]
Sector size emulation
USE_NATIVE_SECTOR
1
R/W
0x00
[61]
Sector size
DATA_SECTOR_SIZE
1
R
0x00
[60]
1st initialization
after disabling sector size emulation
INI_TIMEOUT_EMU
1
R
0x0A
[59]
Class 6 commands control
CLASS_6_CTRL
1
R/W/E_P
0x00
[58]
Number of addressed group to be Released
DYNCAP_NEEDED
1
R
0x00
[57:56]
Exception events control
EXCEPTION_EVENTS_CTRL
2
R/W/E_P
0x00
[55:54]
Exception events status
EXCEPTION_EVENTS_STATUS
2
R
All ‘0’
[53:52]
Extended partitions attribute
EXT_PARTITIONS_ATTRIBUTE
2
R/W
0x00
[51:37]
Context configuration
CONTEXT_CONF
15
R/W/E_P
0x00
[36]
Packed command status
PACKED_COMMAND_STATUS
1
R
0x00
[35]
Packed command failure index
PACKED_FAILURE_INDEX
1
R
0x00
[34]
Power Off Notification
POWER_OFF_NOTIFICATION
1
R/W/E_P
0x00
[33]
Control to turn the Cache ON/OFF
CACHE_CTRL
1
R/W/E_P
0x00
1
1
PROGRAM_CID_CSD_DDR_SUP
PORT
11
Jan. 23th, 2015
THGBMFG7C1LBAIL
CSD-slice
Name
Field
Size
(Bytes)
Cell Type
Value
[32]
Flushing of the cache
FLUSH_CACHE
1
W/E_P
0x00
[31]
Control to turn the Barrier ON/OFF
BARRIER_CTRL
1
R/W
0x00
[30]
Mode config
MODE_CONFIG
1
R/W/E_P
0x00
[29]
Mode operation codes
MODE_OPERATION_CODES
1
W/E_P
[28:27]
Reserved
-
2
R
All ‘0’
[26]
FFU status
FFU_STATUS
1
R
0x00
PRE_LOADING_DATA_SIZE
4
R/W/E_P
0x00757000
4
R
0x00757000
5
0x00(not support.
Return switch error)
[25:22]
Pre loading data size
[21:18]
Max pre loading data size
[17]
Product state awareness enablement
[16]
Secure Removal Type
SECURE_REMOVAL_TYPE
1
R/W & R
0x39
[15]
Command Queue Mode Enable
CMDQ_MODE_EN
1
R/W/E_P
0x00
[14:0]
Reserved
-
15
-
All ‘0’
MAX_PRE_LOADING_DATA
_SIZE
5
PRODUCT_STATE
_AWARENESS_ENABLEMENT
1
R/W/E
&R
1
Although these fields can be re-written by host, TOSHIBA e-MMC does not support.
2
Max Enhanced Area Size (MAX_ENH_SIZE_MULT [159:157]) has to be calculated by following formula.
0x03
Max Enhanced Area = MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512kBytes
4
Enhanced general partition sizei Enhanced user data area Max enhanced area
i1
3
General Purpose Partition Size (GP_SIZE_MULT_GP0 - GP_SIZE_MULT_GP3 [154:143]) has to be calculated
by following formula.
General_Purpose_Partition_X Size = (GP_SIZE_MULT_X_2 x 216 + GP_SIZE_MULT_X_1 x 28
0
+ GP_SIZE_MULT_X_0 x 2 ) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes
4
Enhanced User Data Area Size (ENH_SIZE_MULT [142:140]) has to be calculated by following formula.
Enhanced User Data Area x Size = (ENH_SIZE_MULT_2 x 216 + ENH_SIZE_MULT_1 x 28
+ ENH_SIZE_MULT_0 x 20 ) x HC_WP_GRP_SIZE
x HC_ERASE_GRP_SIZE x 512kBytes
5
- Pre loading data size = PRE_LOADING_DATA_SIZE x Sector Size
Pre-loading data size should be multiple of 4KB and the pre-loading data should be written by multiple of 4KB
chunk size, aligned with 4KB address. This is because the valid data size will be treated as 4KB when host
writes data less than 4KB.
- If the host continues to write data in Normal state (after it wrote PRE_LOADING_DATA_SIZE amount
of data) and before soldering, the pre-loading data might be corrupted after soldering.
- If a power cycle is occurred during the data transfer, the amount of data written to device is not clear.
Therefore in this case, host should erase the entire pre-loaded data and set again
PRE_LOADING_DATA_SIZE[25:22], PRODUCTION_STATE_AWARENESS[133], and
PRODUCT_STATE_AWARENESS_ENABLEMENT[17].
12
Jan. 23th, 2015
THGBMFG7C1LBAIL
ELECTRICAL CHARACTERISTICS
DC Characteristics
Absolute Maximum Ratings
The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must
not be exceeded during operation, even for an instant.
If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably
altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with
exceeded ratings may cause break down, damage, and/or degradation to any other equipment. Applications using
the device should be designed such that each maximum rating will never be exceeded in any operating conditions.
Before using, creating, and/or producing designs, refer to and comply with the precautions and conditions set forth
in this document.
Parameter
Symbol
Test Conditions
Min
Max
Unit
Supply voltage 1
VCC
-0.5
4.1
V
Supply voltage 2
VccQ
-0.5
4.1
V
VIO
-0.5
VccQ+0.5(≦4.1)
V
Voltage Input
General
Parameter
Symbol
Test Conditions
Peak voltage on all lines
Min
Max
Unit
-0.5
VccQ+0.5
V
-100
100
μA
-2
2
μA
-100
100
μA
-2
2
μA
Min
Max
Unit
2.7
3.6
V
1.7
1.95
V
2.7
3.6
V
All Inputs
Input Leakage Current (before initialization sequence
and/or the internal pull up resistors connected)
1
Input Leakage Current (after initialization sequence and
the internal pull up resistors disconnected)
All Outputs
Output Leakage Current (before initialization sequence)
Output Leakage Current (after initialization sequence)
1) Initialization sequence is defined in Power-Up chapter of JEDEC/MMCA Standard
Power Supply Voltage
Parameter
Symbol
Supply voltage 1
VCC
Supply voltage 2
VccQ
Test Conditions
1) Once the power supply VCC or VCCQ falls below the minimum guaranteed voltage (for example, upon sudden power fail),
the voltage level of VCC or VCCQ shall be kept less than 0.5 V for at least 1ms before it goes beyond 0.5 V again.
13
Jan. 23th, 2015
THGBMFG7C1LBAIL
Supply Current
Parameter
Symbol
Interleave
Operation
Mode
IROP
Non Interleave
Operation
(RMS)
IWOP
Non Interleave
Max
Unit
Icc
Iccq
Icc
1.8V
95
15
3.3V
110
15
1.8V
115
20
3.3V
140
20
HS200
1.8V
170
35
mA
HS400
1.8V
215
40
mA
1.8V
60
40
3.3V
60
40
1.8V
60
40
3.3V
60
40
HS200
1.8V
65
45
mA
HS400
1.8V
70
45
mA
DDR
SDR
Write
Min
Iccq
SDR
Read
VccQ
DDR
14
mA
mA
mA
mA
Jan. 23th, 2015
THGBMFG7C1LBAIL
Internal resistance and Device capacitance
Parameter
Single device capacitance
Internal pull up resistance DAT1 – DAT7
Symbol
Test Conditions
Min
Max
Unit
CDEVICE
6
pF
RINT
10
150
kΩ
Bus Signal Levels
Open-Drain Mode Bus Signal Level
Parameter
Symbol
Test Conditions
Min
Max
Unit
Output HIGH voltage
VOH
IOH = -100μA
VccQ - 0.2
V
Output LOW voltage
VOL
IOL = 2mA
0.3
V
Symbol
Test Conditions
Min
Max
Unit
Output HIGH voltage
VOH
IOH = -100μA @ VDD min
0.75 * VccQ
V
Output LOW voltage
VOL
IOL = 100μA @ VDD min
0.125 * VccQ
V
Input HIGH voltage
VIH
0.625* VccQ
VccQ + 0.3
V
Input LOW voltage
VIL
VSS - 0.3
0.25 * VccQ
V
Min
Max
Unit
Push-Pull Mode Bus Signal Level (High-Voltage)
Parameter
Push-Pull Mode Bus Signal Level (Dual-Voltage)
Parameter
Symbol
Test Conditions
Output HIGH voltage
VOH
IOH = -2mA @ VDD min
VccQ - 0.45
V
Output LOW voltage
VOL
IOL = 2mA @ VDD min
0.45
V
Input HIGH voltage
VIH
0.65 * VccQ
VccQ + 0.3
V
Input LOW voltage
VIL
VSS - 0.3
0.35 * VccQ
V
15
Jan. 23th, 2015
THGBMFG7C1LBAIL
Driver Types Definition
Driver Type-0 is defined as mandatory for e-MMC HS200&HS400 Device. While four additional Driver Types (1, 2,
3 and 4) are defined as optional, to allow the support of wider Host loads. The Host may select the most appropriate
Driver Type of the Device (if supported) to achieve optimal signal integrity performance.
Driver Type-0 is targeted for transmission line, based distributed system with 50Ω nominal line impedance.
Therefore, it is defined as 50Ω nominal driver.
For HS200, when tested with CL = 15pF Driver Type-0 shall meet all AC characteristics and HS200 Device output
timing requirements. The test circuit defined in section 10.5.4.3 of JEDEC/MMCA Standard 5.0 is used for testing of
Driver Type-0.
For HS400, when tested with the reference load defined in page 24 HS400 reference load figure, Driver Type-0 or
Driver Type-1 or Driver-4 shall meet all AC characteristics and HS400 Device output timing requirements.
The Optional Driver Types are defined with reference to Driver Type-0.
Driver
Type
HS200
&HS400
Support
TOSHIBA
e-MMC
Normal
Impedance
Approximated driving
capability compared to
Type-0
Remark
Default Driver Type.Supports up to 200MHz operation.
0
Mandatory
Supported
50 Ω
x1
1
Optional
Supported
33 Ω
x1.5
Supports up to 200MHz operation.
2
Optional
Supported
66 Ω
x0.75
The weakest driver that supports up to 200MHz
operation.
3
Optional
Supported
100 Ω
x0.5
4
Optional
Supported
40 Ω
X1.2
For low noise and low EMI systems.
Maximal operating frequency is decided by Host
design.
1) Support of Driver Type-0 is mandatory for HS200&HS400 Device, while supporting Driver types 1, 2 and 3 is optional for
HS200 and Driver type 4 is optional for HS400 Device.
2) Nominal impedance is defined by I-V characteristics of output driver at 0.9V when VCCQ = 1.8V.
*Toshiba recommends Driver Type Value 0x4 in HS400 mode.
16
Jan. 23th, 2015
THGBMFG7C1LBAIL
Bus Timing
Device Interface Timings (High-speed interface timing)
Parameter
Symbol
2
Test Conditions
CL ≤ 30pF
Min
Max
Unit
0
52
3
MHz
0
400
KHz
Clock frequency Data Transfer Mode (PP)
fpp
Clock frequency Identification Mode (OD)
fOD
Tolerance: +20KHz
Clock high time
tWH
CL ≤ 30pF
6.5
ns
Clock low time
tWL
CL ≤ 30pF
6.5
ns
tTLH
CL ≤ 30pF
3
ns
tTHL
CL ≤ 30pF
3
ns
Input set-up time
tISU
CL ≤ 30pF
3
ns
Input hold time
tIH
CL ≤ 30pF
3
ns
tODLY
CL ≤ 30pF
13.7
ns
Output hold time
tOH
CL ≤ 30pF
2.5
ns
5
trise
CL ≤ 30pF
3
ns
tfall
CL ≤ 30pF
3
ns
Clock rise time
4
Clock fall time
Tolerance: +100KHz
Inputs CMD,DAT (referenced to CLK)
Outputs CMD,DAT (referenced to CLK)
Output Delay time during Data Transfer
Signal rise time
Signal fall time
1) CLK timing is measured at 50% of VccQ
2) This product shall support the full frequency range from 0-26MHz, or 0-52MHz
3) e-MMC can operate as high-speed interface timing at 26MHz clock frequency.
4) CLK rise and fall times are measured by min(VIH) and max(VIL).
5) Inputs CMD,DAT rise and fall times area measured by min(VIH) and max(VIL), and outputs CMD, DAT rise and fall times
are measured by min(VOH) and max(VOL).
17
Jan. 23th, 2015
THGBMFG7C1LBAIL
Device Interface Timings (Backward-compatible interface timing)
Parameter
Symbol
3
Test Conditions
Min
Max
Unit
Clock frequency Data Transfer Mode (PP)
fpp
CL ≤ 30pF
0
26
MHz
Clock frequency Identification Mode (OD)
fOD
Tolerance: +20KHz
0
400
KHz
Clock high time
tWH
CL ≤ 30pF
10
ns
Clock low time
tWL
CL ≤ 30pF
10
ns
tTLH
CL ≤ 30pF
10
ns
tTHL
CL ≤ 30pF
10
ns
Input set-up time
tISU
CL ≤ 30pF
3
ns
Input hold time
tIH
CL ≤ 30pF
3
ns
tOSU
CL ≤ 30pF
11.7
ns
tOH
CL ≤ 30pF
8.3
ns
Clock rise time
4
Clock fall time
Inputs CMD,DAT (referenced to CLK)
Outputs CMD,DAT (referenced to CLK)
Output set-up time
5
5
Output hold time
1) The e-MMC must always start with the backward-compatible interface timing. The timing mode can be switched to
high-speed interface timing by the host sending the SWITCH command (CMD6) with the argument for high-speed
interface select.
2) CLK timing is measured at 50% of VccQ
3) For compatibility with e-MMCs that support the v4.2 standard or earlier, host should not use >26MHz before switching to
high-speed interface timing.
4) CLK rise and fall times are measured by min(VIH) and max(VIL).
5) tOSU and tOH are defined as values from clock rising edge. However, the e-MMC device will utilize clock falling edge to
output data in backward compatibility mode. Therefore, it is recommended for hosts either to set tWL value as long as
possible within the range which will not go over tCK - tOH(min) in the system or to use slow clock frequency, so that host
could have data set up margin for the device.
Toshiba e-MMC device utilize clock falling edge to output data in backward compatibility mode.
Host should optimize the timing in order to have data set up margin as follows.
tWL
CLK
tODLY
Output
tOSU
tOH
Invalid
Data
tOSU (min) =
tWL(min) -
tODLY(max 8ns)
Figure 2 Output timing
18
Jan. 23th, 2015
THGBMFG7C1LBAIL
Bus Timing for DAT signals for during 2x data rate operation
These timings applies to the DAT[7:0] signals only when the device is configured for dual data mode operation. In
this dual data mode, the DAT signals operates synchronously of both the rising and the falling edges of CLK. the
CMD signal still operates synchronously of the rising edge of CLK and therefore complies with the bus timing
specified in High-speed interface timing or Backward-compatible interface timing.
High-speed dual data rate interface timings
Parameter
Input CLK
Symbol
Remark
1
Min
Max
Unit
45
55
%
Includes jitter, phase noise
1
Clock duty cycle
Clock rise time
tTLH
3
ns
CL ≤ 30pF
Clock fall time
tTHL
3
ns
CL ≤ 30pF
Input CMD(referenced to CLK-SDR mode)
Input set-up time
Input hold time
tISUddr
3
ns
CL ≤ 20pF
tIHddr
3
ns
CL ≤ 20pF
ns
CL ≤ 20pF
ns
CL ≤ 20pF
Output CMD(referenced to CLK-SDR mode)
Output delay time during data transfer
tODLY
13.7
Output hold time
tOH
2.5
Signal rise time
tRISE
3
ns
CL ≤ 20pF
Signal fall time
tFALL
3
ns
CL ≤ 20pF
19
Jan. 23th, 2015
THGBMFG7C1LBAIL
Parameter
Remark
1
Symbol
Min
Max
Unit
Input set-up time
tISUddr
2.5
ns
CL ≤ 20pF
Input hold time
tIHddr
2.5
ns
CL ≤ 20pF
tODLYddr
1.5
7
ns
CL ≤ 20pF
tRISE
2
ns
CL ≤ 20pF
tFALL
2
ns
CL ≤ 20pF
Input DAT (referenced to CLK-DDR mode)
Output DAT (referenced to CLK-DDR mode)
Output delay time during data transfer
Signal rise time (all signals)
2
Signal fall time (all signals)
1)
CLK timing is measured at 50% of VccQ.
2)
Inputs CMD, DAT rise and fall times are measured by min (VIH) and max (VIL), and outputs CMD, DAT rise and fall
times are measured by min (VOH) and max (VOL).
20
Jan. 23th, 2015
THGBMFG7C1LBAIL
Bus Timing Specification in HS200 mode
HS200 Clock Timing
Host CLK Timing in HS200 mode shall conform to the timing specified in following figure and Table. CLK input shall
satisfy the clock timing over all possible operation and environment conditions. CLK input parameters should be
measured while CMD and DAT lines are stable high or low, as close as possible to the Device. The maximum
frequency of HS200 is 200MHz. Hosts can use any frequency up to the maximum that HS200 mode allows.
NOTE 1
VIH denote VIH(min.) and VIL denotes VIL(max.).
NOTE 2
VT=0.975V -
Clock Threshold,
indicates clock reference point for timing measurements.
Symbol
Min
Max
Unit
Remark
tPERIOD
5
ns
200MHz (Max.), between rising edges
tTLH, tTHL
0.2 * tPERIOD
ns
tTLH, tTHL < 1ns (max.) at 200MHz, CDEVICE=6pF,
The absolute maximum value of tTLH, tTHL is 10ns regardless of
clock frequency.
Duty Cycle
30
70
%
HS200 Device Input Timing
NOTE 1
tISU and tIH are measured at VIL(max.) and VIH(min.).
NOTE 2
VIH denote VIH(min.) and VIL denotes VIL(max.).
Symbol
Min
Max
Unit
Remark
tISU
1.40
ns
CDEVICE ≤ 6pF
tIH
0.8
ns
CDEVICE ≤ 6pF
21
Jan. 23th, 2015
THGBMFG7C1LBAIL
HS200 Device Output Timing
tPH parameter is defined to allow device output delay to be longer than tPERIOD. After initialization, the tPH may have
random phase relation to the clock. The Host is responsible to find the optimal sampling point for the Device outputs,
while switching to the HS200 mode.
While setting the sampling point of data, a long term drift, which mainly depends on temperature drift, should be
considered. The temperature drift is expressed by ∆TPH. Output valid data window (tVW) is available regardless of the
drift (∆TPH) but position of data window varies by the drift.
NOTE
VOH denotes VOH(min.) and VOL denotes VOL(max.).
Min
Max
Unit
tPH
0
2
UI
Device output momentary phase from CLK input to CMD
or DAT lines output.
Does not include a long term temperature drift.
-350
+1550
(∆T = -20 °C )
(∆T = 90 °C )
ps
Delay variation due to temperature change after tuning.
Total allowable shift of output valid window (TVW) from
last system Tuning procedure
∆TPH is 2600ps for ∆T from -25 °C to 125 °C during
operation.
UI
tVW =2.88ns at 200MHz
Using test circuit in following figure including skew
among CMD and DAT lines created by the Device.
Host path may add Signal Integrity induced noise,
skews, etc. Expected tVW at Host input is larger than
0.475UI.
∆TPH
tVW
0.575
22
Remark
1
Symbol
Jan. 23th, 2015
THGBMFG7C1LBAIL
∆TPH consideration
Implementation Guide:
Host should design to avoid sampling errors that may be caused by the ∆TPH drift.
It is recommended to perform tuning procedure while Device wakes up, after sleep.
One simple way to overcome the ∆TPH drift is by reduction of operating frequency.
23
Jan. 23th, 2015
THGBMFG7C1LBAIL
Bus Timing Specification in HS400 mode
HS400 Input Timing
The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode.
Note : VIH denote VIH(min) and VIL denotes VIL(max)
Parameter
Symbol
Min
Max
Unit
tPERIOD
5
ns
SR
1.125
V/ns
tCKDCD
0.0
Remark
Input CLK
Cycle time data transfer mode
200MHz(Max), between rising edges
With respect to VT
Slew rate
Duty cycle distortion
0.3
ns
With respect to VIH /VIL
Allowable deviation from an ideal 50% duty cycle.
With respect to VT
Includes jitter, phase noise
Minimum pulse width
tCKMPW
2.2
ns
With respect to VT
Input DAT(referenced to CLK)
Input set-up time
tISUddr
0.4
ns
CDevice≤6pF
With respect to VIH /VIL
Input hold time
tIHddr
0.4
ns
CDevice≤6pF
With respect to VIH /VIL
Slew rate
SR
1.125
V/ns
24
With respect to VIH /VIL
Jan. 23th, 2015
THGBMFG7C1LBAIL
HS400 Device Output Timing
The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC status response.
Note : VOH denotes VOH(min) and VOL denotes VOL(max)
Parameter
Symbol
Min
tPERIOD
5
Max
Unit
Remark
Data Strobe
Cycle time data transfer mode
ns
200MHz(Max), between rising edges
With respect to VT
Slew rate
Duty cycle distortion
SR
1.125
tDSDCD
0.0
V/ns
With respect to VOH/VOL and HS400 reference load
ns
Allowable deviation from the input CLK duty cycle
distortion(tCKDCD)
0.2
With respect to VT
Includes jitter, phase noise
Minimum pulse width
tDSMPW
2.0
ns
With respect to VT
Output DAT(referenced to Data Strobe)
Output skew
tRQ
Output hold skew
tRQH
Slew rate
SR
0.4
0.4
1.125
ns
With respect to VOH /VOL and HS400 reference load
ns
With respect to VOH /VOL and HS400 reference load
V/ns
With respect to VOH /VOL and HS400 reference load
25
Jan. 23th, 2015
THGBMFG7C1LBAIL
HS400 Device Command Output Timing
The Data Strobe is used to response of any command in HS400 mode.
Note : VOH denotes VOH(min) and VOL denotes VOL(max)
Parameter
Symbol
Min
tPERIOD
5
Max
Unit
Remark
Data Strobe
Cycle time data transfer
mode
200MHz(Max), between rising edges
With respect to VT
Slew rate
Duty cycle distortion
ns
SR
1.125
tDSDCD
0.0
0.2
V/ns
With respect to VOH/VOL and HS400 reference load
ns
Allowable deviation from the input CLK duty cycle
distortion(tCKDCD)
With respect to VT
Includes jitter, phase noise
Minimum pulse width
tDSMPW
2.0
ns
With respect to VT
CMD Response (referenced to Data Strobe)
Output skew(CMD)
tRQ_CMD
Output hold skew(CMD)
tRQH_CMD
Slew rate
SR
0.4
0.4
1.125
ns
With respect to VOH /VOL and HS400 reference load
ns
With respect to VOH /VOL and HS400 reference load
V/ns
With respect to VOH /VOL and HS400 reference load
26
Jan. 23th, 2015
THGBMFG7C1LBAIL
Driver
Device I/O
Measurement Point
Z0 = 50 Ohm
Td = 350 ps
CREFERENCE =4pF
Reference Load
Figure 3
HS400 reference load
HS400 Capacitance
The Data Strobe is used to read data in HS400 mode. The Data Strobe is toggled only during data read or CRC s
Parameter
Symbol
Min
Pull-up resistance for CMD
RCMD
Pull-up resistance for DAT0-7
Typ.
Max
Unit
4.7
100
㏀
RDAT
10
100
㏀
Pull-down resistance for Data Strobe
RDS
10
100
㏀
Internal pull up resistance DAT1-DAT7
Rint
10
150
㏀
Bus signal line capacitance
CL
13
pF
Single Device capacitance
CDEVICE
6
pF
27
Remark
Jan. 23th, 2015
THGBMFG7C1LBAIL
Overshoot/Undershoot Specification
VCCQ
Unit
1.70V-1.95V
Maximum peak amplitude allowed for overshoot area.
Max
0.9
V
Max
0.9
V
Max
1.5
V-ns
Max
1.5
V-ns
(See Figure Overshoot/Undershoot definition)
Maximum peak amplitude allowed for undershoot area.
(See Figure Overshoot/Undershoot definition)
Maximum area above VCCQ
(See Figure Overshoot/Undershoot definition)
Maximum area below VSSQ
(See Figure Overshoot/Undershoot definition)
Figure 4
Overshoot/Undershoot definition
H/W Reset Operation
(Note) *1 : Device will detect the rising edge of RST_n signal to trigger internal reset sequence
H/W Reset Timings
Parameter
Symbol
Test Conditions
Min
Max
Unit
μs
μs
μs
RST_n pulse width
tRSTW
1
RST_n to Command time
tRSCA
200
RST_n high period (interval time)
tRSTH
1
1
1) 74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA
2) During the device internal initialization sequence right after power on, device may not be able to detect RST_n signal,
because the device may not complete loading RST_n_ENABLE bits of the extended CSD register into the controller yet.
28
Jan. 23th, 2015
THGBMFG7C1LBAIL
Power-up sequence
Supply voltage
Vcc max
Vcc min
VccQ max
VccQ min
0.5V
time
Vccq Power up time
Vcc Power up time
Vccq Power up time
tPRUL
tPRUH
tPRUL
Figure 3 Power up sequence
Power-up parameter
Parameter
Symbol
Test Conditions
Min
Max
Supply power-up for 3.3V
tPRUH
5 μs
35 ms
Supply power-up for 1.8V
tPRUL
5 μs
25 ms
29
Remark
Jan. 23th, 2015
THGBMFG7C1LBAIL
Functional restrictions
- Pre loading data size is limited to MAX_PRE_LOADING_DATA_SIZE[21-18] regardless of using Production
State Awareness function.
- MAX_PRE_LOADING_DATA_SIZE[21-18] value will change when host sets Enhanced User area Partition.
Reliability Guidance
This reliability guidance is intended to notify some guidance related to using raw NAND flash. Although random
bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be
marked as bad when a program status failure or erase status failure is detected. The other failure modes may be
recovered by a block erase. ECC treatment for read data is mandatory due to the following Data Retention and
Read Disturb failures.
-Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after
either an auto program or auto block erase operation. The cumulative bad block count will increase along with the
number of write/erase cycles.
-Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge gain.
After block erasure and reprogramming, the block may become usable again. Also write/erase endurance
deteriorates data retention capability. The figure below shows a generic trend of relationship between write/erase
endurance and data retention.
-Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit errors
occur on other pages in the block, not the page being read. After a large number of read cycles (between block
erases), a tiny charge may build up and can cause a cell to be soft programmed to another state. After block erasure
and reprogramming, the block may become usable again.
Considering the above failure modes, TOSHIBA recommends following usage:
- Please avoid any excessive iteration of resets and initialization sequences (Device identification mode) as far as
possible after power-on, which may result in read disturb failure. The resets include hardware resets and software
resets.
e.g.1) Iteration of the following command sequence, CMD0 - CMD1 --The assertion of CMD1 implies a count of internal read operation in Raw NAND.
CMD0: Reset command, CMD1: Send operation command
e.g.2) Iteration of the following commands, CMD30 and/or CMD31
CMD30: Send status of write protection bits, CMD31: Send type of write protection
30
Jan. 23th, 2015
THGBMFG7C1LBAIL
Document Revision History
Rev0.1
Oct. 8th, 2014
- Released as preliminary revision
Rev0.2
Dec. 1st, 2014
- Revised values of performances.
Rev0.3
Dec. 18th, 2014
- Revised some typos
Rev1.0
Jan. 23th, 2015
- Revised some typos
- Revised some typos.
- Fixed values of Performance. (VccQ=1.8V)
- Fixed values of Operating Current and Sleep Mode Current.
- Fixed values of CID/CSD/Extended-CSD value
- Released as final revision.
31
Jan. 23th, 2015
THGBMFG7C1LBAIL
RESTRICTIONS ON PRODUCT USE
Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application
notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH
MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without
limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU
USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your
TOSHIBA sales representative.
Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF
SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES
OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION
AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED
TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the
U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited
except in compliance with all applicable export laws and regulations.
Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES
OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
32
Jan. 23th, 2015
工商网监
湘ICP备2023018690号
