TLP5214A(TP,E

TLP5214A Photocouplers Infrared LED & Photo IC TLP5214A Isolated IGBT/Power MOSFET gate drive AC and brushless DC motor drives Industrial Inverters and Uninterruptible Power Supply (UPS) Unit: mm The TLP5214A is a highly integrated 4.0 A output current IGBT gate drive photocoupler housed in a long creepage and clearance SO16L package. The TLP5214A, a smart gate driver photocoupler, includes functions of IGBT desaturation detection, isolated fault status feedback, soft IGBT turn-off, active Miller cramping and under voltage lockout (UVLO). Moreover, this phorocoupler has features of the desaturation leading edge blanking time, filtering time, and optimisation of the soft-shutdown performance for secure operation of applications. This photocoupler is suitable for driving IGBT and power MOSFET used in inverter applications. The TLP5214A consists two infrared LEDs and two high-gain and high-speed ICs. They realize high current, high-speed output control and output fault status feedback. • Peak output current: ±4.0 A (max) • Guaranteed performance over temperature: -40 to 110 °C • Supply current: 3.8 mA (max) • Power supply voltage: 15 V to 30 V • Threshold input current: 6 mA (max) • Propagation delay time: 150 ns (max) • DESAT leading edge blanking time: 1.1 μs (typ.) • Common-mode transient immunity: ±35 kV/μs (min) 5000 Vrms (min) • Isolation voltage: • UL-recognized : UL 1577, File No.E67349 • cUL-recognized :CSA Component Acceptance Service No. 5A, File No.E67349 • VDE approved: EN 60747-5-5, EN 62368-1 (Note 1) TOSHIBA 11-10M1 Weight: 0.37 g (typ.) • Construction mechanical rating SO16L Height Creepage Distance Clearance Insulation Thickness 2.3 mm (max) 8.0 mm (min) 8.0 mm (min) 0.4 mm (min) Note 1: When a VDE approved type is needed, please designate the Option(D4). Truth Table IF DESAT FAULT (14Pin DESAT Terminal Input) (3Pin FAULT Terminal Output) UVLO (VCC2-VE) VO OFF Not Active ( > VUVLO+) Not Active High Low ON Not Active ( > VUVLO+) Low ( < VDESATth) High High Not Active ( > VUVLO+) High ( > VDESATth) Low ( FAULT) Low ON ON Active ( < VUVLO-) Not Active High Low OFF Active ( < VUVLO-) Not Active High Low Start of commercial production 2017-03 © 2019 Toshiba Electronic Devices & Storage Corporation 1 2019-10-30 TLP5214A Pin Configuration (top view) VE 16 VLED 15 DESAT 14 VCC2 13 VEE 12 ANODE VOUT 11 7 ANODE VCLAMP 10 8 CATHODE 1 VS 2 VCC1 3 FAULT 4 VS 5 CATHODE 6 VEE 9 1: VS 2: VCC1 3: FAULT 4: VS 5: CATHODE 6: ANODE 7: ANODE 8: CATHODE 9: VEE 10: VCLAMP 11: VOUT 12: VEE 13: VCC2 14: DESAT 15: VLED 16: VE Internal Circuit VCC2 UVLO ANODE VOUT CATHODE DESAT DESAT VEE SHIELD VCLAMP VCC1 VCLAMP VE FAULT Vs VLED Note: A 1-μF bypass capacitor must be connected between pins 9 and 13, pins 13 and 16. © 2019 Toshiba Electronic Devices & Storage Corporation 2 2019-10-30 TLP5214A Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 °C) Characteristics LED Input forward current Input forward current derating (Ta ≥ 95°C) Peak transient input forward current (Note 1) Peak transient input forward current derating (Ta ≥ 95°C) Unit IF 25 mA ∆IF/∆Ta -1 mA/°C IFPT 1 A ∆IFPT/∆Ta -25 mA/°C VR 6 V Input power dissipation PD 145 mW ∆ PD /∆Ta -5.0 mW/°C VCC1 -0.5 to 7 V IOPH -4.0 A IOPL +4.0 A FAULT output current IFAULT 8 mA FAULT pin voltage VFAULT -0.5 to VCC1 V (VCC2-VEE) -0.5 to 35 V Negative output supply voltage (VE-VEE) -0.5 to 15 V Positive output supply voltage (VCC2-VE) -0.5 to 35 - (VE-VEE) V VO -0.5 to VCC2 V Peak clamping sinking current IClamp 1.7 A Miller clamping pin voltage VClamp -0.5 to VCC2 V DESAT voltage VDESAT VE to VE + 10 V PO 410 mW ∆ PO /∆Ta -14.0 mW/°C Topr -40 to 110 °C Positive input supply voltage “H” peak output current Ta = -40 to 110 °C (Note 2) “L” peak output current Total output supply voltage Output voltage Output power dissipation Output power dissipation derating (Ta ≥ 95°C) Common Rating Reverse input voltage Input power dissipation derating (Ta ≥ 95°C) Detector Symbol Operating temperature range Storage temperature range Tstg -55 to 125 °C Lead soldering temperature (10 s) (Note 3) Tsol 260 °C Isolation voltage (AC, 60 s, R.H. ≤ 60%) (Note 4) BVS 5000 Vrms Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note: A ceramic capacitor (1 μF) should be connected between pins 9 and 13, pins 13 and 16 to stabilize the operation of the high gain linear amplifier. Furthermore, in case VE - VEE > 0 V, a bypass capacitor, which has good high frequency characteristic, a ceramic capacitor (1 μF) should be connected between pins 9 and 16. Failure to provide the bypassing may impair the switching property. The total lead length between capacitor and coupler should not exceed 1 cm. Note 1: Pulse width PW ≤ 1 μs, 300 pps Note 2: Exponential waveform pulse width PW ≤ 0.2 μs, f ≤ 15 kHz, VCC2 = 15 V Note 3: For the effective lead soldering area. Note 4: This device considered a two-terminal device: All pins on the LED side are shorted together, and all pin on the photodetector side are shorted together. © 2019 Toshiba Electronic Devices & Storage Corporation 3 2019-10-30 TLP5214A Recommended Operating Conditions (Note) Characteristics Symbol Min Typ. Max Unit Total output supply voltage (Note 1) (VCC2-VEE) 15 - 30 V Negative output supply voltage (VE-VEE) 0 - 15 V Positive output supply voltage (VCC2-VE) 15 - 30 - (VE-VEE) V VCC1 3.3 - 5.5 V Positive input supply voltage Input on-state current (Note 2) Input off-state voltage Operating frequency (Note 3) IF(ON) 7.5 - 10 mA VF(OFF) 0 - 0.8 V f - - 50 kHz Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the device. Additionally, each item is an independent guideline respectively. In developing designs using this product, please confirm specified characteristics shown in this document. Note 1: If the VCC2 rise slope is sharp, an internal circuit might not operate with stability. Please design the VCC2 rise slope under 3.0 V / μs. Note 2: Input signal rise time (fall time) ≤ 0.5 μs. Note 3: Exponential waveform. IOPH ≥ -4.0 A (≤ 90 ns), IOPL ≤ 4.0 A (≤ 90 ns), Ta = 110 °C © 2019 Toshiba Electronic Devices & Storage Corporation 4 2019-10-30 TLP5214A Electrical Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 °C, VCC2 - VEE = 15 to 30 V, VE - VEE = 0 V) Symbol Test Circuit Input forward voltage VF ― IF = 10 mA, Ta = 25°C Input reverse current IR ― Input capacitance Ct ― VFAULTL ― Characteristics FAULT low level output voltage FAULT high level output current High level output current Low level output current (Note 1) (Note 1) IFAULTH IOPH ― 1 Test Condition Min Typ. Max Unit 1.4 - 1.7 V VR = 5 V - - 10 μA V = 0 V, f = 1 MHz, Ta = 25 °C - 95 - pF IFAULT = 1.1 mA, VCC1 = 5.5 V - 0.2 0.4 IFAULT = 1.1 mA, VCC1 = 3.3 V - 0.2 0.4 VFAULT = 5.5 V, VCC1 = 5.5 V, Ta = 25 °C - - 0.5 VFAULT = 5.5 V, VCC1 = 3.3 V, Ta = 25 °C - - 0.3 VO = VCC2 - 4 V - -4.0 -1.2 VO = VCC2 - 7 V - -6.5 -3.0 VO = VEE + 2.5 V 1.2 3.5 - VO = VEE + 7 V 3 5.5 - 90 150 230 V μA A IOPL 2 IOLF ― VO - VEE = 14 V High level output voltage VOH 3 IO = -100 mA VCC2-0.3 VCC2-0.1 - Low level output voltage VOL 4 IO = 100 mA - 0.1 0.2 VtClamp ― ― - 2.5 - ICL ― VO = VEE + 2.5 V 0.56 1.8 - High level supply current ICC2H 5 IO = 0 mA - 2.4 3.8 Low level supply current ICC2L 6 IO = 0 mA - 2.3 3.8 Blanking capacitor charging current ICHG 7 VDESAT = 2 V -0.33 -0.24 -0.13 Blanking capacitor discharge current IDSCHG 8 VDESAT = 7 V 10 49 - DESAT threshold voltage VDESAT ― VCC2 - VE ＞ VUVLO- 5.9 6.5 7.5 VUVLO+ 9 VO ＞ 5 V 10.5 11.6 13.5 VUVLO- 9 VO ＜ 5 V 9.2 10.3 11.1 UVLOHYS ― ― - 1.3 - Threshold input current (L/H) IFLH 10 VCC2 = 30 V, VO < 5 V - 2.6 6 mA Threshold input voltage (H/L) VFHL ― VCC2 = 30 V, VO > 5 V 0.8 - - V Low level output current during fault condition Clamp pin threshold voltage Clamp low level sinking current UVLO threshold voltage UVLO hysteresis mA V A mA V Note: All typical values are at Ta = 25 °C Note: This product is more sensitive than conventional products to electrostatic discharge ESD owing to its low power consumption design. It is therefore all the more necessary to observe general precautions regarding ESD when handling this component. Note 1: IO application time ≤ 50 μs, 1 pulse © 2019 Toshiba Electronic Devices & Storage Corporation 5 2019-10-30 TLP5214A Isolation Characteristics (Note) (Ta = 25 °C) Characteristic Capacitance input to output Isolation resistance Isolation voltage Symbol CS RS BVS Test Condition Min Typ. Max Unit Vs = 0 V, f = 1 MHz - 1.0 - pF R.H. ≤ 60 %, VS = 500 V 12 10 10 - Ω AC, 60 s 5000 - 14 Vrms Note: This device considered a two-terminal device: All pins on the LED side are shorted together, and all pin on the photodetector side are shorted together. © 2019 Toshiba Electronic Devices & Storage Corporation 6 2019-10-30 TLP5214A Switching Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 °C, VCC2 - V EE = 15 to 30 V, VE - VEE = 0 V) Characteristics Symbol Propagation delay time (Note 1) Test Circuit Test Condition Min Typ. Max L→H tpLH IF = 0 → 10 mA 50 85 150 H→L tpHL IF = 10 → 0 mA 50 90 150 Rg = 10 Ω, IF = 0 → 10 mA - 32 - Cg = 25 nF, IF = 10 → 0 mA - 18 - IF = 0 ↔ 10 mA - - 50 IF = 0 ↔ 10 mA -80 - 80 Cg = 25 nF - 230 500 Cg = 25 nF - 7.0 8.5 CDESAT = 100 pF, Cg = 10 nF Rg = 10 Ω, VCC2 = 30 V, RF = 2.1 kΩ, VCC1 = 5 V - 2.5 3.5 - 1.1 - - 90 - - 350 550 - 200 - 7 20 - 0.2 0.6 2 VO (min) = 26 V, VFAULT(min) = 2 V ±35 - - VO (max) = 1 V, VFAULT(max) = 0.8 V ±35 - - Output rise time (10-90 %) (Note 1) tr Output fall time (90-10 %) (Note 1) tf Pulse with distortion (Note 1) | tpHL-tpLH | Propagation delay skew (device to device) (Note 1) (Note 2) tpsk DESAT sense to 90% delay tDESAT(90%) DESAT sense to 10% delay tDESAT(10%) DESAT leading edge blanking time tDESAT(FILTER) DESAT sense to low level FAULT signal delay tDESAT(FAULT) tDESAT(LOW) DESAT input mute tDESAT(MUTE) Low-level Common-mode transient immunity 12 ns μs ns ns DESAT sense to low propagation delay High-level Common-mode transient immunity (Note 3) VCC2 = 30 V tDESAT(LEB) DESAT filter time RESET to high level FAULT signal delay 11 Unit CDESAT = 100 pF, Rg = 10 Ω, VCC2 = 30 V, RF = 2.1 kΩ, VCC1 = 5.5 V tRESET(FAULT) CMH CML (Note 4) 13 to 16 Ta = 25 °C, Rg = 10 Ω, Cg = 25 nF, VCC2 = 30 V, RF = 2.1 kΩ, CF = 15 pF, VCM = 1500 Vp-p μs kV/μs Note: All typical values are at Ta = 25 °C. Note 1: Input signal (f = 10 kHz, duty = 50%, tr = tf = 5 ns or less) CL is approximately 15 pF which includes probe and stray wiring capacitance. Note 2: The propagation delay skew, tpsk, is equal to the magnitude of the worst-case difference in tpHL and/or tpLH that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc). Note 3: CMH is the maximum rate of fall of the common mode voltage that can sustained with the output voltage in the logic high state (VO > 26 V or VFAULT > 2 V). Note 4: CML is the maximum rate of rise of the common mode voltage that can sustained with the output voltage in the logic low state (VO < 1 V or VFAULT < 0.8 V). © 2019 Toshiba Electronic Devices & Storage Corporation 7 2019-10-30 TLP5214A Test Circuit Test Circuit 1: IOPH Test Circuit 2: IOPL Test Circuit 3: VOH Test Circuit 4: VOL Test Circuit 5: ICC2H Test Circuit 6: ICC2L © 2019 Toshiba Electronic Devices & Storage Corporation 8 2019-10-30 TLP5214A Test Circuit 7: ICHG Test Circuit 8: IDSCHG Test Circuit 9: VUVLO Test Circuit 10: IFLH Test Circuit 11: tpLH, tpHL, tr, tf, | tpHL-tpLH | IF = 10 mA (P.G.) (f =10 kHz, duty = 50%, rise / fall time 5 ns or less) P.G.: Pulse generator Test Circuit 12: tDESAT(90%), tDESAT(10%), tDESAT(LEB), tDESAT(FILTER), tDESAT(FAULT), tDESAT(Low), tDESAT(MUTE), tRESET(FAULT) IF = 10 mA (P.G.) (f =10 kHz, duty = 50%, rise / fall time 5 ns or less) P.G.: Pulse generator © 2019 Toshiba Electronic Devices & Storage Corporation 9 2019-10-30 TLP5214A Test Circuit 13: CMR_LED1 ON Test Circuit 14: CMR_LED1 OFF Test Circuit 15: CMR_LED2 ON Test Circuit 16: CMR_LED2 OFF © 2019 Toshiba Electronic Devices & Storage Corporation 10 2019-10-30 TLP5214A Characteristics Curves (Note) IF - T a (V) IF - VF IOPH - Ta (VOH – VCC2) - IOPH IOPL - Ta VOL - IOPL © 2019 Toshiba Electronic Devices & Storage Corporation 11 2019-10-30 TLP5214A ICL - Ta (VCLAMP – VEE) - ICL ICC2L, ICC2H - Ta ICC2L, ICC2H - VCC2 ICHG - Ta © 2019 Toshiba Electronic Devices & Storage Corporation VDESAT - Ta 12 2019-10-30 TLP5214A (VOH – VCC2) - Ta VOL - Ta IFLH - Ta VO - IF tpHL, tpLH, |tpHL - tpLH| - Ta © 2019 Toshiba Electronic Devices & Storage Corporation tpHL, tpLH, |tpHL - tpLH| - IF 13 2019-10-30 TLP5214A tpHL, tpLH, |tpHL - tpLH| - VCC2 tDESAT(90%) - Ta tDESAT(10%) - Ta tDESAT(LEB) - Ta tDESAT(FILTER) - Ta © 2019 Toshiba Electronic Devices & Storage Corporation tDESAT(FAULT) - Ta 14 2019-10-30 TLP5214A tDESAT(LOW) - Ta tRESET(FAULT) - Ta Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. © 2019 Toshiba Electronic Devices & Storage Corporation 15 2019-10-30 TLP5214A Soldering and Storage (1) Precautions for Soldering The soldering temperature should be controlled as closely as possible to the conditions shown below, irrespective of whether a soldering iron or a reflow soldering method is used. ・When using soldering reflow The soldering temperature profile is based on the package surface temperature. (See the figure shown below, which is based on the package surface temperature.) Reflow soldering must be performed once or twice. The mounting should be complicated with the interval from the first to the last mountings being 2 weeks. An example of a temperature profile when lead(Pb)-free solder is used ・When using soldering flow Preheat the device at a temperature of 150 °C (package surface temperature) for 60 to 150 seconds. Mounting condition of 260 °C within 10 seconds is recommended. Flow soldering must be performed once. ・When using soldering iron Complete soldering within 10 seconds for lead temperature not exceeding 260 °C or within 3 seconds not exceeding 350 °C. Heating by soldering iron must be done only once per lead. (2) Precautions for General Storage ・Avoid storage locations where devices may be exposed to moisture or direct sunlight. ・Follow the precautions printed on the packing label of the device for transportation and storage. ・Keep the storage location temperature and humidity within a range of 5 °C to 35 °C and 45 % to 75 %. ・Do not store the products in locations with poisonous gases (especially corrosive gases) or in dusty conditions. ・Store the products in locations with minimal temperature fluctuations. Rapid temperature changes during storage can cause condensation, resulting in lead oxidation of corrosion, which will deteriorate the solderability of the leads. ・When restoring devices after removal from their packing, use anti-static containers. ・Do not allow loads to be applied directly to devices while they are in storage. ・If devices have been stored for more than two years under normal storage conditions, it is recommended that you check the leads for ease of soldering prior to use. © 2019 Toshiba Electronic Devices & Storage Corporation 16 2019-10-30 TLP5214A Land Pattern Dimensions for Reference Only Unit: mm Marking Lot No. TLP5214A J Part No. (or abbreviation code) Process lot No. Country of origin J; Japan Pin No. 1 © 2019 Toshiba Electronic Devices & Storage Corporation 17 2019-10-30 TLP5214A 1. Ordering Method When placing an order, please specify the part number, the tape and the quantity (Multiples of 1500) as shown in the following example. Example) TLP5214A(TP,E 1500 pcs Part number: TLP5214A Tape type: TP (12-mm pitch) [[G]]/RoHS COMPATIBLE: E (Note 1) Quantity (must be a multiple of 1500): 1500 pcs Note 1 : Please contact your Toshiba sales representative for details on environmental information such as the product’s RoHS compatibility. RoHS is the Directive 2011/65/EU of the European Parliament and of the Council of 8 June 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment. © 2019 Toshiba Electronic Devices & Storage Corporation 18 2019-10-30 TLP5214A RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. 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