TLP5231(D4-TP,E

TLP5231 (Preliminary) Photocouplers Infrared LED & Photo IC TLP5231 Preliminary 1. Applications ・Isolated IGBT/Power MOSFET Gate Driers (Pre-driver) ・AC and brushless DC Motor Drives ・Industrial Inverters and Uninterruptible Power Supply (UPS) 2. General The TLP5231 is a highly integrated 2.5 A dual-output IGBT gate drive photocoupler which a multi-functional IC is housed in a long creepage and clearance SO16L package. This photocoupler is suitable as a pre-driver to driver power devices via external p- and n- channel MOSFET as buffer. The TLP5231, a smart gate driver photocoupler, includes functions of IGBT/power MOSFET desaturation detection, isolated fault status feedback, soft gate turn-off, active Miller cramping and under voltage lockout (UVLO). The TLP5231 consists two GaAℓAs infrared light-emitting diodes (LEDs) and two high-gain and high-speed ICs. They realize output current control and fault status feedback with electrical isolation between first and second stage. 3. Features (1) Peak output current: ±2.5 A (max) (2) Guaranteed performance over temperature: -40 to 110 ℃ (3) Threshold input current: 3.5 mA (max) (4) Propagation delay time: 300 ns (max) (5) Common-mode transient immunity: ±25 kV/μs (min) (6) Isolation voltage: 5000 Vrms (min) (7) Safety standards UL: UL1577, File No.E67349 cUL: CSA Component Acceptance Service No.5A File No.E67349 VDE: EN60747-5-5, EN60065, EN60950-1, EN 62368-1 (Note 1) CQC: GB4943.1, GB8898 (to be applied) Note 1:When a VDE approved type is needed, please designate the Option (D4). 1 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) 4. Pin Configuration 1 : No connection 2 : Cathode 3 : Anode 4 : Cathode 5 : Input side ground 6 : Input side supply voltage 7 : Fault output 8 : Input side ground 9 : Negative output supply voltage 10 : No connection, for testing only 11 : Low side voltage output 12 : High side voltage output 13 : Positive output supply voltage 14 : External MOSFET control pin 15 : Desat over current sensing 16 : Common output supply voltage (power device emitter or source) 5. Internal Circuit (Note) Note: A 10-μF bypass capacitor must be connected between pins 9 (VEE) and 13 (VCC2), and a 1-μF bypass capacitor must be connected between pins 13 (VCC2) and 16 (VE), and pins 9 (VEE) and 16 (VE). The total lead length between capacitor and coupler should not exceed 1 cm. 2 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) 6. Principle of Operation 6.1 Truth Table IF UVLO_P, UVLO_N DESAT FAULT VOUTP VOUTN VGMOS X Active Not active H (VCC1) H (VCC2) H (VE) H (VE) ON Not active Active (with DESAT fault) H (VCC1) H (VCC2) L (VEE) H (VE) ON Not active Active (without DESAT fault) L (VGND1) L (VE) L (VEE) L (VEE) OFF Not active Not active L (VGND1) H (VCC2) H (VE) L (VEE) 6.2 Mechanical Parameters 3 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) 7. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 ℃) Characteristics Symbol Input forward current LED Input forward current derating (Ta ≥ 95 ℃) Peak transient input forward current Peak transient input forward current derating (Ta ≥ 95 °C) Unit 25 mA ΔIF /ΔTa -0.84 mA/℃ IFPT (Note 1) 1 A ΔIFPT /ΔTa (Note 3) -34 mA/℃ VR 5 V Input power dissipation PD 150 mW -5.0 mW/℃ -0.5 to 7 V (Ta ≥ 95 ℃) Positive input supply voltage Peak high-level output current Peak low-level output current (Ta = -40 to 110 ℃) (Ta = -40 to 110 ℃) ΔPD /ΔTa VCC1 (Note 3) IOPH (Note 2) -2.5 IOPL (Note 2) +2.5 A FAULT output current IFAULT 8 mA FAULT pin voltage VFAULT -0.5 to VCC1 V Total output supply voltage Detector Note Reverse Voltage Input power dissipation derating (VCC2 – VEE) (Note 6) -0.5 to 35 V Negative output supply voltage (VE – VEE) (Note 6) -0.5 to 17 V Positive output supply voltage (VCC2 – VE) (Note 6) -0.5 to 30 V High side output voltage VOUTP(Peak) VE – 0.5 to VCC2 + 0.5 V Low side output voltage VOUTN(Peak) VEE – 0.5 to VE + 0.5 V DESAT voltage VDESAT VE – 0.5 to VCC2 + 0.5 V VGMOS voltage VGMOS VEE – 0.5 to VE + 0.5 V PO 410 mW -14.0 mW/℃ Output power dissipation Output power dissipation derating Common RATING IF (Ta ≥ 95 °C) ΔPO /ΔTa (Note 3) Operating temperature Topr -40 to 110 Storage temperature Tstg -55 to 125 Lead soldering temperature (10 s) Tsol (Note 4) 260 Isolation voltage (AC,1 min.,R.H. ≤ 60%,Ta=25 ℃) BVs (Note 5) 5000 Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/”Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc.) Note: A ceramic capacitor (10 μF) must be connected between pins 9 (VEE) and 13 (VCC2), and a ceramic capacitor (1 μF) must be connected between pins 13 (VCC2) and 16 (VE), and pins 9 (VEE) and 16 (VE) to stabilize the operation of the high gain linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length between capacitor and coupler should not exceed 1 cm. Note 1: Pulse width ≤ 1 μs, 300 pps Note 2: Exponential waveform. Pulse width ≤ 0.2 μs, f ≤ 15 kHz, VCC2 = 15 V Note 3: Soldered on a substrate designated by JEDEC. Note 4: For the effective lead soldering area.. Note 5: This device is considered as a two-terminal device: Pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together. Note 6: Power supply sequence must be 1) VE ー VEE, 2) VCC2 ー VE. 4 Ver2.3.0: 2018-11-21 (HOC-4564) ℃ Vrms TLP5231 (Preliminary) 8. Recommended Operating Conditions (Note) Characteristics Symbol Note Min Typ. Max Unit (VCC2 - VEE) (Note 1) 21 - 30 V Negative output supply voltage (VE - VEE) (Note 1) 6 - 15 V Positive output supply voltage (VCC2 - VE) (Note 1) Total output supply voltage Positive input supply voltage VCC1 Input on-state current IF(ON) Input off-stage voltage VF(OFF) 15 - 30 - (VE - VEE) V 3.3 - 5.5 V (Note 2) 5.3 - 12 mA (Note 2) 0 - 0.8 V Note: The recommended operating conditions are given as a design guide necessary to obtain the intended performances of the device. Each parameter is an independent value. When creating a system design using this device, the electrical characteristics specified in this datasheet should also be considered. Note 1: If the VCC2 and VEE rise is sharp, an internal circuit might not be operate with stability. Please design the VCC2 and VEE rise slope under 0.1 V/μs. Note 2: The rise and fall times of the input on-current should be less than 0.5 μs. 5 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) 9. Electrical Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 ℃, VCC2 – VE = 15 V, VE – VEE = 8 V) Characteristics Symbol Note Test Test Condition Circuit Typ. Max Unit 1.45 - 1.7 V Input forward voltage VF Input reverse current IR VR = 5 V - - 10 μA Input capacitance Ct V = 0 V, f = 1 MHz, Ta = 25 ℃ - 60 - pF VFAULTL VDESAT = 0 V, RF = 10 kΩ, CF = 1 nF, VCC1 = 3.3 or 5.5 V - 0.1 0.25 V VFAULTH VDESAT = Open, RF = 10 kΩ, CF = 1 nF, VCC1 = 3.3 or 5.5 V - VCC1 - V IFAULTL VFAULT = 0.15 V, VCC1 = 3.3 or 5 V - 1.2 - mA VFAULT = VCC1 = 3.3 or 5 V - 0.01 1 μA ― ― -1.0 A 1.0 ― ― ― ― -1.0 1.0 ― ― FAULT low level output voltage FAULT high level output voltage FAULT low level output current FAULT high level output current VOUTP high level output current VOUTP low level output current VOUTN high level output current VOUTN low level output current IF = 10 mA, Ta = 25 ℃ Min IFAULTH IOUTPH IOUTPL IOUTNH IOUTNL (Note 1) TBD VCC2 – VOUTP = 7 V VOUTP – VE = 7 V, IF = 8 mA (Note 1) TBD (Note 1) TBD VE – VOUTN = 7 V (Note 1) TBD VOUTN – VEE = 7 V, IF = 8 mA VOUTP high level output resistance ROUTPH (Note 1) ― IOUTP = -1.0 A, VF = 0 V ― 1.6 4.4 VOUTP low level output resistance ROUTPL (Note 1) ― IOUTP = 1.0 A, IF = 8 mA ― 1.2 3.3 VOUTN high level output resistance ROUTNH (Note 1) ― IOUTN = -1.0 A, VF = 0 V ― 1.9 5.0 VOUTN low level output resistance ROUTNL (Note 1) ― IOUTN = 1.0 A, IF = 8 mA ― 1.0 3.3 VOUTP high level output voltage VOUTPH TBD IOUTP = ­100 mA, VF = 0 V VCC2­0.43 VCC2­0.15 ― VOUTP low leve output voltage VOUTPL TBD IOUTP = 100 mA, IF = 8 mA ― VE+0.1 VE+0.32 VOUTN high level output voltage VOUTNH TBD IOUTN = ­100 mA, VF = 0 V VE­0.4 VE­0.2 ― VOUTN low leve output voltage VOUTNL TBD IOUTN = 100 mA, IF = 8 mA ― VEE+0.1 VEE+0.3 VGMOS high level ouptut current IOUTGH TBD VE – VGMOS = 8 V, IF = 8 mA, DESAT = Open - - −105 VGMOS low level output current IOUTGL TBD VGMOS – VEE = 8 V, VF = 0 V, DESAT = Open 90 - - VGMOS high level output resistance ROUTGH ― IOUTG = -80 mA, IF = 8 mA - 10 30 VGMOS low leve output resistance ROUTGL ― IOUTN = 80 mA, VF = 0 V, DESAT = Open - 4 10 VGMOS high level output voltage VOUTGH ― IOUTG = -1 mA, IF = 8 mA, DESAT = Open - VE - VGMOS low level output voltage VOUTGL ― IOUTN = 1 mA, VF = 0 V, DESAT = Open - VEE - 6 Ver2.3.0: 2018-11-21 (HOC-4564) Ω V mA Ω V TLP5231 (Preliminary) Electrical Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 ℃, VCC2 – VE = 15 V, VE – VEE = 8 V) Characteristics Symbol Note Test Test Condition Circuit Min Typ. Max Unit ― 6 10.2 mA ― 6.5 10.2 High level supply current (VCC2) ICC2H TBD VF = 0 V, no load Low level supply current (VCC2) ICC2L TBD IF = 8 mA, no load High level supply current (VEE) IEEH TBD VF = 0 V, no load -9.2 -5 ― Low leve supply current (VEE) IEEL TBD IF = 8 mA, no load -9.2 -5 ― Threshold input current (H/L) IFHL ― VOUTP – VE < 5 V, VOUTN – VEE < 1 V ― 1 3.5 Threshold input voltage (L/H) VFLH ― VOUTP – VE > 5 V, VOUTN – VEE > 1 V 0.8 ― ― UVLO_P threshold VUVLOP+ TBD IF = 8 mA, VOUTP – VE < 5 V 12 13 14 (VCC2 ­ VE) VUVLOP- IF = 8 mA, VOUTP – VE > 5 V 11 12 13  ― 1 ― UVLO_P hysteresis VUVLOP_HYS V (VCC2 ­ VE) UVLO_N threshold (VE ­ VEE) VUVLON+ IF = 8 mA, VOUTN – VEE < 1 V -6 -5.3 -5 VUVLON- IF = 8 mA, VOUTN – VEE > 1 V -5.7 -5.0 -4.7 UVLO_N hysteresis (VE ­ VEE) VUVLON_HYS  ― 0.3 ― VCC2 – VE > VUVLOP-, VE – VEE > VUVLON- 7.5 8.0 9.0 VDESAT = 2 V -0.9 -0.5 -0.2 mA ― 1.1 3.0 V DESAT threshold VDESAT ― Blanking capacitor charging current ICHG TBD VDSCHG TBD DESAT low voltage when blanking capacitor discharge IDSCHG = 10 mA Note: All typical values are at Ta = 25 ℃. Note: This device is designed for low power consumption, making it more sensitive to ESD than its predecessors. Extra care should be taken in the design of circuitry and pc board implementation to avoid ESD problems. Note 1: IO application time ≤ 10 μs, single pulse 10. Isolation Characteristics (Unless otherwise specified, Ta = 25 ℃) Characteristics Total capacitance (input to output) Isolation resistance Isolation voltage Symbol Note CS (Note 1) Test conditions VS = 0 V, f = 1 MHz RS (Note 1) VS = 500 V, R.H. ≤ 60 % BVS (Note 1) AC, 60 s Min Typ. Max Unit - 1.0 - pF - Ω - Vrms 12 1 x 10 5000 14 1 x 10 - Note1: This device considered a two-terminal device: All pins on the LED side are shorted together, and all pin on the photodetector side are shorted together. 7 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) 11. Switching Characteristics (Note) (Unless otherwise specified, Ta=-40 to 110 ℃, VCC2 – VE = 15 V, VE – VEE = 8 V) Characteristics Propagation delay time (L/H) Propagation delay time (H/L) Pulse width distortion Propagation delay skew (device to device) LED off to 90 % of VOUTP LED on to 10 % of VOUTN Non-overlap time low to high Non-overlap time high to low Symbol tpLH Test Circuit (Note 1) TBD tDP IF = 0  (Note 1) f = 20 kHz, duty = 50 % (Note 2) (Note 1) IF = 8 IF = 0 IF = 8 tNLH tNHL Fall time on VOUTN tNF IF = 0 IF = 8 0 mA, CP = CN = 4 nF, 8 mA, CP = CN = 4 nF, 0 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % IF = 0 8 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % IF = 8 0 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % IF = 0 8 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % t1 TBD threshold to 50 % of high VGMOS CP = CN = 4 nF, CG = 1 nF, f = 100 Hz, duty = 50 %, t2 IF = 8 mA, CBLANK = 200 pF, threshold to 50 % of high VOUTP Min Typ. Max 100 200 300 100 200 300 - - 150 -200 - 200 50 150 250 50 130 250 - 60 - - 50 - - 50 - - 50 - - 50 - - 40 - ― 450 750 ― 340 700 ― 9 20 Unit ns VDESAT = 8.0 V, Pos-edge t3 RF = 10 kΩ, CF = 1 nF, VCC1 = 3.3 or 5 V, f = 100 Hz, threshold to 50 % of high VFAULT μs duty = 50 %, IF = 8 mA t4 CP = CN =4 nF, CG = 1 nF, ― 11 ― f = 100 Hz, duty = 50 %, VGMOS to 50 % of VOUTN DESAT filter time 8 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % tNR DESAT leading edge blanking time 0 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % Rise time on VOUTN Mute time (Note 3) 8 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % tPF Propagation delay time from 50% 8 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % tDN Fall time on VOUTP Propagation delay time from DESAT 0 mA, CP = CN = 4 nF, f = 20 kHz, duty = 50 % tPR Propagation delay time from DESAT IF = 8 IF = 0 | tpHL - tpLH| tpsk Condition f = 20 kHz, duty = 50 % tpHL Rise time on VOUTP Propagation delay time from DESAT Note ns IF = 8 mA tMUTE (Note 3) IF = 8 mA tDESAT(LEB) tDESAT(FILTER) 0.68 1 1.7 ms ― ― 520 ― ns RDESAT = 100 Ω, Vin = 10 V, ― 270 ― ±25 ― ― ±25 ― ― Pw = 1 μs, Monitor: VOUTP, VGMOS CMH (Note 4) TBD VCM = 1000 Vp-p, IF = 0 mA, Common-mode transient immunity at Vin = 5 V, VCC = 15 V, high level Rin = 220 Ω (with split resistors) kV/μs Ta = 25 ℃, VO(min) = 10 V CML (Note 5) VCM = 1000 Vp-p, IF = 10 mA, Common-mode transient immunity at Vin = 5 V, VCC = 15 V, low level Rin = 220 Ω (with split resistors) Ta = 25 ℃, VO(min) = 1 V 8 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) Note: All typical values are at Ta = 25 ℃. Note 1: Input signal: tr = tf = 5 ns or less CL is approximately 15 pF which includes probe and stray wiring capacitance. Note 2: The propagation delay skew, tpsk, is equal to the magnitude of the worst-case difference in tpHL and/or tpLH that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc). Note 3: Automatic reset: This is the minimum time when VOUTP is high, VOUTN is low, VGMOS is high and FAULT is high, after DESAT threshold is exceeded. LED trigger reset: After tMUTE, operation will be resumed when IF changes from high to low. Note 4: CMH is the maximum rate of fall of the common mode voltage that can sustained with the output voltage in the logic high state (VOUTP – VE > 12 V, VOUTN – VEE > 5 V or VFAULT > 2 V). Note 5: CML is the maximum rate of rise of the common mode voltage that can sustained with the output voltage in the logic low state (VOUTP – VE < 1 V, VOUTN – VEE < 1 V or VFAULT < 0.8 V). 9 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) 12. Timing diagram Fig.12.1 Normal state Fig.12.2 DESAT fault state (LED turn off before tMUTE timeout: Automatic reset) Fig.12.3 DESAT fault state (LED turn off after tMUTE timeout: Reset by LED trigger) 10 Ver2.3.0: 2018-11-21 (HOC-4564) TLP5231 (Preliminary) RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”. • TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 11 Ver2.3.0: 2018-11-21 (HOC-4564)