TLP558
TOSHIBA Photocoupler IRED & Photo IC
TLP558
Isolated Bus Driver
High Speed Line Receiver
Microprocessor System Interfaces
MOS FET Gate Driver
Transistor Inverter
Unit: mm
The TOSHIBA TLP558 consists of an infrared emitting diode and integrated
high gain, high speed photodetector.
This unit is 8-lead DIP package.
The detector has a three state output stage that provides source drive and
sink drive, and built-in schmitt trigger. The detector IC has an internal shield
that provides a guaranteed common mode transient immunity of 1000V / μs.
TLP558 is inverter logic type. For buffer logic type, TLP555 is in line-up.
Input current: IF=1.6 mA (max)
Power supply voltage: VCC=4.5 to 20 V
Switching speed: tpHL, tpLH=400ns (max)
Common mode transient immunity: ±1000V/μs (min)
TOSHIBA
11-10C4S
Weight: 0.54 g (typ.)
Guaranteed performance over temperature: -25 to 85°C
Isolation voltage: 2500Vrms (min)
UL-recognized: UL 1577, File No.E67349
Pin Configuration (top view)
cUL-recognized: CSA Component Acceptance Service
No.5A File No.E67349
8 1 : NC
2 : Anode
7 3 : Cathode
4 : NC
6 5 : GND
6 : VO(Output)
5 7 : VE(Enable)
8 : VCC
VCC
1
2
Truth Table
Input
Enable
Output
H
H
L
L
H
H
H
L
Z
L
L
Z
3
4
GND
Shield
Schematic
IE
A 0.1μF bypass capacitor must be connected between pins
8 and 5.
ICC 7
8
IF
+
VF
−
IO
2
6
3
Shield
VE
VCC
VO
GND
5
Start of commercial production
1987-05
© 2019
Toshiba Electronic Devices & Storage Corporation
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2019-06-24
TLP558
Absolute Maximum Ratings
Charactersitic
Symbol
Rating
Unit
IF
10
mA
IFPT
1
A
LED
Forward current
Peak transient forward current
(Note 1)
Reverse voltage
VR
5
V
Diode power dissipation
PD
45
mW
Output current
IO
40 / -25
mA
IOP
80 / -50
mA
Output voltage
VO
-0.5 to 20
V
Supply voltage
VCC
-0.5 to 20
V
Three state enabel voltage
VE
-0.5 to 20
V
Output power dissipation
PO
100
mW
ΔPO/ΔTa
-1.8
mW/°C
PT
200
mW
ΔPT/ΔTa
-3.6
mW/°C
Operating temperature range
Topr
-40 to 85
°C
Storage temperature range
Tstg
-55 to 125
°C
Detector
Peak output current
(Note 2)
Output power dissipation derating (Ta > 70 °C)
Total package power dissipation
Total package power dissipation derating (Ta > 70 °C)
Lead solder temperature(10 s)
(Note 3)
Tsol
260
°C
Isolation voltage (AC, 60 s, R.H. ≤ 60 %, Ta=25°C)
(Note 4)
BVS
2500
Vrms
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Pulse width ≤ 1 μs, 300 pps.
Note 2: Pulse width ≤ 5μ s, duty ratio ≤ 0.025.
Note 3: 1.6 mm below seating plane.
Note 4: Device considered a two terminal device: Pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8 shorted
together.
Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
―
5
mA
Input current, on
IF(ON)
Input voltage, off
VF(OFF)
0
―
0.8
V
Supply voltage
VCC
4.5
―
20
V
Enable voltage high
VEH
2.0
―
20
V
Enable voltage low
VEL
0
―
0.8
V
Fan out(TTL load)
N
―
―
4
―
Topr
-25
―
85
°C
Operating temperature
2 (Note 1)
Typ.
Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the
device. Additionally, each item is an independent guideline respectively. In developing designs using this product,
please confirm specified characteristics shown in this document.
Note 1: 2 mA condition permits at least 20 % CTR degradation guardband.
Initial switching threshold is 1.6 mA or less.
© 2019
Toshiba Electronic Devices & Storage Corporation
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TLP558
Electrical Characteristics (unless otherwise specified, Ta = -25 to 85°C, VCC = 4.5 to 20V)
Characteristic
Symbol
Input forward voltage
VF
Temperature coefficient of
forward voltage
ΔVF / ΔTa
Test Condition
Min
Typ.
Max
Unit
IF = 5 mA, Ta = 25 °C
―
1.55
1.7
V
IF = 5 mA
―
-2.0
―
mV / °C
Input reverse current
IR
VR = 5 V, Ta = 25 °C
―
―
10
μA
Input capacitance
CT
VF = 0 V, f = 1 MHz, Ta = 25 °C
―
45
―
pF
VO = VE = 5.5 V
―
―
100
VO = VE = 20 V
―
0.01
500
Output leakage current
(VO > VCC)
IOHH
VF = 0 V,
VCC = 4.5 V
Logic low output voltage
VOL
IOL = 6.4 mA, IF = 1.6 mA
VE = 2 V
―
0.4
0.5
V
Logic high output voltage
VOH
IOH = -2.6 mA, VF = 0.8 V
VE = 2 V
2.4
3.3
―
V
Logic low enable current
IEL
VE = 0.4 V
―
-0.13
-0.32
mA
VE = 2.7 V
―
―
20
VE = 5.5 V
―
―
100
VE = 20 V
―
0.01
250
Logic high enable current
IEH
μA
μA
Logic low enable voltage
VEL
―
―
―
0.8
V
Logic high enable voltage
VEH
―
2.0
―
―
V
Logic low supply current
ICCL
IF = 5 mA
VCC = VE = 5.5 V
―
4.0
6.0
VCC = VE = 20 V
―
4.6
7.5
Logic high supply current
ICCH
VF = 0 V
IOZL
VF = 0 V
VE = 0.8 V
IOZH
IF = 5 mA
VE = 0.8 V
High impedance state
output current
VCC = VE = 5.5 V
―
4.2
6.0
VCC = VE = 20 V
―
4.7
7.5
VO = 0.4 V
―
―
-20
VO = 2.4 V
―
―
20
VO = 5.5 V
―
―
100
VO = 20 V
―
1
500
VO = VCC = 5.5 V
25
55
―
VO = VCC = 20 V
40
80
―
VCC = 5.5 V
-10
-25
―
VCC = 20 V
-25
-60
―
Logic low short circuit
output current
(Note 1)
IOSL
IF = 5 mA
VE = 2 V
Logic high short circuit
output current
(Note 1)
IOSH
VF = 0 V, VO = GND
VE = 2 V
mA
mA
μA
mA
mA
Input current logic low output
IFL
VE = 2 V, IO = 6.4 mA
VO < 0.4 V
―
0.4
1.6
mA
Input voltage logic high output
VFH
VE = 2 V, IO = -2.6 mA
VO > 2.4 V
0.8
―
―
V
Input current hysteresis
IHYS
VCC = VE = 5 V
―
0.05
―
mA
5×1010
1014
―
Ω
―
1.0
―
pF
Resistance (input-output)
RS
VS = 500 V, R.H. ≤60 %
Ta = 25 °C
Capacitance(input-output)
CS
VS = 0 V, f = 1 MHz, Ta = 25 °C
(Note 2)
(Note 2)
Note: All typical values are at Ta = 25 °C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified.
Note 1: Duration of output short circuit time should not exceed 10 ms.
Note 2: Device considered a two terminal device: Pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8
shorted together.
© 2019
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TLP558
Switching Characteristics (unless otherwise specified, VCC = 4.5 to 20V, Ta = 25°C)
Characteristic
Symbol
Propagation delay time to
logic high output
(Note 1)
tpLH
Propagation delay time to
logic low output
(Note 1)
tpHL
Test
Circuit
1
Test Condition
Min
Typ.
Max
Unit
IF = 3→ 0 mA
―
250
400
ns
IF = 0→ 3 mA
―
270
400
ns
Output rise time (10-90%)
tr
IF = 3→ 0 mA, VCC = 5 V
―
35
75
ns
Output fall time (90-10%)
tf
IF = 0→ 3 mA, VCC = 5 V
―
20
75
ns
IF = 0 mA, VCM = 50 V
VO (Min) = 2 V
1000
―
―
V / μs
IF = 1.6 mA, VCM = 50 V
VO (Max) = 0.8 V
-1000
―
―
V / μs
Common mode transient
immunity at logic high
output
(Note 2)
Common mode transient
immunity at logic low
output
(Note 2)
CMH
3
CML
Note: All typical values are at Ta = 25 °C, VCC = 5 V
Note: A ceramic capacitor (0.1 μF) should be connected from pin 8 to pin 5 to stabilize the operation of the high gain
linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length
between capacitor and coupler should not exceed 1cm.
Note 1: The tpLH propagation delay is measured from the 50 % point on the trailing edge of the input pulse to the 1.3
V point on the leading edge of the output pulse. The tpHL propagation delay is measured from the 50 % point
on the leading edge of the input pulse to the 1.3 V point on the trailing edge of the output pulse.
Note 2: CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in
the logic low state (VO < 0.8 V).
CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic state (VO > 2.0 V).
© 2019
Toshiba Electronic Devices & Storage Corporation
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TLP558
Test Circuit 1: tpLH, tpHL, tr and tf
IF(ON)
50%
IF Monitor
VOL
Output
VO
IF = IF (ON)
S1 Closed
S2 Open
Output VO
IF = 0mA
S1 Open
S2 Closed
S1 and S2
Closed
IF
VOL
tpZH
1.3V
0V
tpHZ
GND
4
620Ω
6
5
D1
D1 to D4
: 1S1588
D2
D3
D4
CL
VE
Monitor
5V
VCC
VO
VOH
to 1.5V
t
0.5V
S1 and S2
Closed
1
VCC 8
2
7
3
6
GND
4
S1
620Ω
0.5V
3
0V
tpLZ
1.3V
7
Pulse
generator
ZO=50Ω
tr = tf = 5ns
3V
1.3V
tpZL
2
CL is approximately 15pF which includes
probe and stray wiring capacitance.
Test Circuit 2: tpHZ, tpZH, tpLZ and tpZL
Input VE
VCC 8
D1
5
D1 to D4
: 1S1588
D2
D3
D4
5kΩ
tr
1
5kΩ
VOH
1.3V
10%
tf
IF
100Ω
90%
Output VO
5V
0mA
tpLH
0.1μF
tpHL
VO Monitor
0.1μF
Input IF
VCC
Pulse generation
tr = tf = 5ns
VO = 5V
CL
S2
CL is approximately 15pF which includes
probe and stray wiring capacitance.
Test Circuit 3: Common Mode Transient Immunity
10%
0V
tf
tr
IF
B
VOH
Output
VOH
VOL
VO (MIN.)
Switch at A : IF=0mA
45(V)
tf(μs)
VFF
VCC 8
2
7
3
6
GND
4
VO(MAX)
+
, CML=
5
VO
Monitor
VCM
Switch at B : IF=1.6mA
CMH=
A
1
0.1μF
VCM
VCC
50V
90%
-
Pulse generator
ZO =50Ω
45(V)
tf(μs)
© 2019
Toshiba Electronic Devices & Storage Corporation
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TLP558
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