TLP5754(TP,E

TLP5754 Photocouplers Infrared LED & Photo IC TLP5754 1. Applications • Induction Cooktop and Home Appliances • Industrial Inverters • Air Conditioner Inverters • MOSFET Gate Drivers • IGBT Gate Drivers 2. General The TLP5754 consists of an infrared LED and integrated high-gain, high-speed photodetector and is house in the 6-pin SO6L package. The TLP5754 is 50 % smaller than the 8-pin DIP package and meets the reinforced insulation class requirements of international safety standards. Therefore the mounting area can be reduced in equipment requiring the safety standard certification. The TLP5754 has an internal faraday shield that provides a guaranteed common-mode transient immunity of ±35 kV/µs. In particular, the TLP5754 has rail to rail output, and this enables stable operation and better switching performance in system. 3. Features (1) Buffer logic type (totem pole output) (2) Output peak current: ±4.0 A (max) (3) Operating temperature: -40 to 110 (4) Supply current: 3.0 mA (max) (5) Supply voltage: 15 to 30 V (6) Threshold input current: 4 mA (max) (7) Propagation delay time: tpHL/tpLH = 150 ns (max) (8) Common-mode transient immunity: ±35 kV/µs (min) (9) Isolation voltage: 5000 Vrms (min) (10) Safety standards UL-recognized: UL 1577, File No.E67349 cUL-recognized: CSA Component Acceptance Service No.5A File No.E67349 VDE-approved: EN 60747-5-5, EN 62368-1 (Note 1) CQC-approved: GB4943.1, GB8898 Japan and Thailand Factory Note 1: When a VDE approved type is needed, please designate the Option (D4) (D4). Start of commercial production ©2015-2019 Toshiba Electronic Devices & Storage Corporation 1 2014-06 2019-12-22 Rev.9.0 TLP5754 4. Packaging (Note) TLP5754 TLP5754(LF4) 11-4N1A Note: 11-4N101A Lead forming option: (LF4) 5. Pin Assignment 1: Anode 2: N.C. 3: Cathode 4: GND 5: VO (Output) 6: VCC 6. Internal Circuit (Note) Note: A 1-µF bypass capacitor must be connected between pin 6 and pin 4. ©2015-2019 Toshiba Electronic Devices & Storage Corporation 2 2019-12-22 Rev.9.0 TLP5754 7. Principle of Operation 7.1. Truth Table Input LED M1 M2 Output H ON ON OFF H L OFF OFF ON L 7.2. Mechanical Parameters Characteristics Size Unit Height 2.3 (max) mm Creepage distances 8.0 (min) Clearance distances 8.0 (min) Internal isolation thickness 0.4 (min) 8. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 ) Characteristics LED Symbol Input forward current Input forward current derating IF (Ta ≥ 105 ) Peak transient input forward current Peak transient input forward current derating Note ∆IF/∆Ta IFPT (Ta ≥ 85 ) (Note 1) ∆IFPT/∆Ta Rating Unit 20 mA -1 mA/ 1 A -25 mA/ Input reverse voltage VR 5 V Input power dissipation PD 40 mW ∆PD/∆Ta -1.0 mW/ Tj 125  A Input power dissipation derating (Ta ≥ 85 ) Junction temperature Detector Peak high-level output current Peak low-level output current (Ta = -40 to 110 ) IOPH (Note 2) -4.0 (Ta = -40 to 110 ) IOPL (Note 2) +4.0 Output voltage VO 35 Supply voltage VCC 35 Output power dissipation Output power dissipation derating (Ta ≥ 85 ) Junction temperature Common Operating temperature Storage temperature Lead soldering temperature Isolation voltage V PO 450 mW ∆PO/∆Ta -4.5 mW/ Tj 125  Topr -40 to 110 Tstg -55 to 125 (10 s) Tsol (Note 3) 260 AC, 60 s, R.H. ≤ 60% BVS (Note 4) 5000 Vrms Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: Pulse width (PW) ≤ 1 µs, 300 pps Note 2: Exponential waveform. Pulse width ≤ 2 µs, f ≤ 15 kHz Note 3: ≥ 2 mm below seating plane. Note 4: This device is considered as a two-terminal device: Pins 1, 2 and 3 are shorted together, and pins 4, 5 and 6 are shorted together. ©2015-2019 Toshiba Electronic Devices & Storage Corporation 3 2019-12-22 Rev.9.0 TLP5754 9. Recommended Operating Conditions (Note) Characteristics Symbol Note Min Typ. Input on-state current IF(ON) (Note 1) 6 Input off-state voltage VF(OFF) 0 15  30   -4.0   +4.0   50 Supply voltage VCC Peak high-level output current IOPH Peak low-level output current IOPL Operating frequency f (Note 2) (Note 3) Max Unit  15 mA  0.8 V A kHz Note: The recommended operating conditions are given as a design guide necessary to obtain the intended performance of the device. Each parameter is an independent value. When creating a system design using this device, the electrical characteristics specified in this data sheet should also be considered. Note: A ceramic capacitor (1 µF) should be connected between pin 6 (VCC) and pin 4 (GND) to stabilize the operation of a high-gain linear amplifier. Otherwise, this photocoupler may not switch properly. The bypass capacitor should be placed within 1 cm of each pin. Note 1: The rise and fall times of the input on-current should be less than 0.5 µs. Note 2: Denotes the operating range, not the recommended operating condition. Note 3: Exponential waveform. IOPH ≥ -4.0 A (≤ 90 ns), IOPL ≤ 4.0 A (≤ 90 ns), Ta = 110  10. Electrical Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 ) Characteristics Input forward voltage Input forward voltage temperature coefficient Symbol Note Test Circuit VF ∆VF/∆Ta Test Condition Min Typ. Max Unit IF = 10 mA, Ta = 25  1.45 1.55 1.70 V IF = 10 mA  -1.8  mV/ Input reverse current IR VR = 5 V, Ta = 25    10 µA Input capacitance Ct V = 0 V, f = 1 MHz, Ta = 25   60  pF IF = 5 mA, VCC = 30 V, V6-5 = -3.5 V   -1.2 A IF = 5 mA, VCC = 15 V, V6-5 = -7 V   -3.0 IF = 0 mA, VCC = 30 V, V5-4 = 2.5 V 1.2   IF = 0 mA, VCC = 15 V, V5-4 = 7 V 3.0   14.7 14.9  Peak high-level output current Peak low-level output current IOPH IOPL (Note 1) (Note 1) Fig. 13.1.1 Fig. 13.1.2 High-level output voltage VOH Fig. 13.1.3 IF = 4 mA, VCC = 15 V, IO = -100 mA Low-level output voltage VOL Fig. 13.1.4 VF = 0.8 V, VCC = 15 V, IO = 100 mA  0.07 0.2 High-level supply current ICCH Fig. 13.1.5 IF = 10 mA, VCC = 30 V, VO = Open  1.8 3.0 Low-level supply current ICCL Fig. 13.1.6 IF = 0 mA, VCC = 30 V, VO = Open  1.7 3.0 Threshold input current (L/H) IFLH VCC = 15 V, VO > 1 V  1.4 4 Threshold input voltage (H/L) VFHL VCC = 15 V, VO < 1 V 0.8   Supply voltage VCC  15  30 UVLO threshold voltage UVLO hysteresis VUVLO+ IF = 5 mA, VO > 2.5 V 12.1 12.7 13.5 VUVLO- IF = 5 mA, VO < 2.5 V 11.1 11.7 12.4  1.0  UVLOHYS  V mA V Note: Note: All typical values are at Ta = 25 . This device is designed for low power consumption, making it more sensitive to ESD than its predecessors. Extra care should be taken in the design of circuitry and pc board implementation to avoid ESD problems. Note 1: IO application time ≤ 50 µs; single pulse. ©2015-2019 Toshiba Electronic Devices & Storage Corporation 4 2019-12-22 Rev.9.0 TLP5754 11. Isolation Characteristics (Unless otherwise specified, Ta = 25 ) Characteristics Symbol Note Test Conditions Min Typ. Max Unit Total capacitance (input to output) CS (Note 1) VS = 0 V, f = 1 MHz  1.0  pF Isolation resistance RS (Note 1) VS = 500 V, R.H. ≤ 60 % 1012 1014  Ω (Note 1) AC, 60 s 5000   Vrms Isolation voltage BVS Note 1: This device is considered as a two-terminal device: Pins 1, 2 and 3 are shorted together, and pins 4, 5 and 6 are shorted together. 12. Switching Characteristics (Note) (Unless otherwise specified, Ta = -40 to 110 ) Characteristics Symbol Note Propagation delay time (L/H) tpLH (Note 1) Propagation delay time (H/L) tpHL Test Circuit Fig. 13.1.7 Test Condition Min Typ. Max Unit IF = 0 → 10 mA, VCC = 30 V, Rg = 10 Ω, Cg = 25 nF 50  150 ns IF = 10 → 0 mA, VCC = 30 V, Rg = 10 Ω, Cg = 25 nF 50  150 Rise time tr (Note 1) IF = 0 → 10 mA, VCC = 30 V, Rg = 10 Ω, Cg = 25 nF  15  Fall time tf (Note 1) IF = 10 → 0 mA, VCC = 30 V, Rg = 10 Ω, Cg = 25 nF  8  |tpHL-tpLH| (Note 1) tpsk (Note 1), (Note 2) IF = 0 ←→ 10 mA, VCC = 30 V, Rg = 10 Ω, Cg = 25 nF High-level common-mode transient immunity CMH (Note 3) Low-level common-mode transient immunity CML (Note 4) Pulse width distortion Propagation delay skew (device to device) Fig. 13.1.8   50 -80  80 VCM = 1000 Vp-p, IF = 5 mA, VCC = 30 V, Ta = 25 , VO(min) = 26 V ±35 ±40  VCM = 1000 Vp-p, IF = 0 mA, VCC = 30 V, Ta = 25 , VO(max) = 1 V ±35 ±40  kV/µs Note: All typical values are at Ta = 25 . Note 1: Input signal ( f = 25 kHz, duty = 50%, tr = tf = 5 ns or less ). CL is less than 15 pF which includes probe and stray wiring capacitance. Note 2: The propagation delay skew, tpsk, is equal to the magnitude of the worst-case difference in tpHL and/or tpLH that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc). Note 3: CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 26 V). Note 4: CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 1 V). ©2015-2019 Toshiba Electronic Devices & Storage Corporation 5 2019-12-22 Rev.9.0 TLP5754 13. Test Circuits and Characteristics Curves 13.1. Test Circuits Fig. 13.1.1 IOPH Test Circuit Fig. 13.1.2 IOPL Test Circuit Fig. 13.1.3 VOH Test Circuit Fig. 13.1.4 VOL Test Circuit Fig. 13.1.5 ICCH Test Circuit Fig. 13.1.6 ICCL Test Circuit Fig. 13.1.7 Switching Time Test Circuit and Waveform ©2015-2019 Toshiba Electronic Devices & Storage Corporation 6 2019-12-22 Rev.9.0 TLP5754 Fig. 13.1.8 Common-Mode Transient Immunity Test Circuit and Waveform ©2015-2019 Toshiba Electronic Devices & Storage Corporation 7 2019-12-22 Rev.9.0 TLP5754 13.2. Characteristics Curves (Note) Fig. 13.2.1 IF - VF Fig. 13.2.2 IF - Ta Fig. 13.2.3 PO - Ta Fig. 13.2.4 IFLH - Ta Fig. 13.2.5 ICCL - Ta Fig. 13.2.6 ICCH - Ta ©2015-2019 Toshiba Electronic Devices & Storage Corporation 8 2019-12-22 Rev.9.0 TLP5754 Fig. 13.2.7 VOL - Ta Fig. 13.2.8 VOH - Ta Fig. 13.2.9 VOL - IOPL Fig. 13.2.10 (VOH-VCC) - IOPH Fig. 13.2.11 tpLH,tpHL,|tpHL-tpLH| - Ta Fig. 13.2.12 tpLH,tpHL,|tpHL-tpLH| - IF ©2015-2019 Toshiba Electronic Devices & Storage Corporation 9 2019-12-22 Rev.9.0 TLP5754 Fig. 13.2.13 tpLH,tpHL,|tpHL-tpLH| - VCC Note: The above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. ©2015-2019 Toshiba Electronic Devices & Storage Corporation 10 2019-12-22 Rev.9.0 TLP5754 14. Soldering and Storage 14.1. Precautions for Soldering The soldering temperature should be controlled as closely as possible to the conditions shown below, irrespective of whether a soldering iron or a reflow soldering method is used. • When using soldering reflow. The soldering temperature profile is based on the package surface temperature. (See the figure shown below, which is based on the package surface temperature.) Reflow soldering must be performed once or twice. The mounting should be completed with the interval from the first to the last mountings being 2 weeks. Fig. 14.1.1 An Example of a Temperature Profile When Lead(Pb)-Free Solder Is Used • When using soldering flow Preheat the device at a temperature of 150  (package surface temperature) for 60 to 120 seconds. Mounting condition of 260  within 10 seconds is recommended. Flow soldering must be performed once. • When using soldering Iron Complete soldering within 10 seconds for lead temperature not exceeding 260  or within 3 seconds not exceeding 350  Heating by soldering iron must be done only once per lead. 14.2. Precautions for General Storage • Avoid storage locations where devices may be exposed to moisture or direct sunlight. • Follow the precautions printed on the packing label of the device for transportation and storage. • Keep the storage location temperature and humidity within a range of 5  to 35  and 45 % to 75 %, respectively. • Do not store the products in locations with poisonous gases (especially corrosive gases) or in dusty conditions. • Store the products in locations with minimal temperature fluctuations. Rapid temperature changes during storage can cause condensation, resulting in lead oxidation or corrosion, which will deteriorate the solderability of the leads. • When restoring devices after removal from their packing, use anti-static containers. • Do not allow loads to be applied directly to devices while they are in storage. • If devices have been stored for more than two years under normal storage conditions, it is recommended that you check the leads for ease of soldering prior to use. ©2015-2019 Toshiba Electronic Devices & Storage Corporation 11 2019-12-22 Rev.9.0 TLP5754 15. Land Pattern Dimensions (for reference only) Unit: mm TLP5754 TLP5754(LF4) Fig. 15.1 Lead Forming Option (standard) Fig. 15.2 Lead Forming Option (LF4) 16. Marking ©2015-2019 Toshiba Electronic Devices & Storage Corporation 12 2019-12-22 Rev.9.0 TLP5754 17. EN 60747-5-5 Option (D4) Specification • Part number: TLP5754 (Note 1) • The following part naming conventions are used for the devices that have been qualified according to option (D4) of EN 60747. Example: TLP5754(D4-TP,E D4: EN 60747 option TP: Tape type E: [[G]]/RoHS COMPATIBLE (Note 2) Note 1: Use TOSHIBA standard type number for safety standard application. e.g., TLP5754(D4-TP,E → TLP5754 Note 2: Please contact your Toshiba sales representative for details on environmental information such as the product's RoHS compatibility. RoHS is the Directive 2011/65/EU of the European Parliament and of the Council of 8 June 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment. Fig. 17.1 EN 60747 Insulation Characteristics ©2015-2019 Toshiba Electronic Devices & Storage Corporation 13 2019-12-22 Rev.9.0 TLP5754 Fig. 17.2 Insulation Related Specifications (Note) Note: This photocoupler is suitable for safe electrical isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Fig. 17.3 Marking on Packing Fig. 17.4 Marking Example (Note) Note: The above marking is applied to the photocouplers that have been qualified according to option (D4) of EN 60747. ©2015-2019 Toshiba Electronic Devices & Storage Corporation 14 2019-12-22 Rev.9.0 TLP5754 Fig. 17.5 Measurement Procedure ©2015-2019 Toshiba Electronic Devices & Storage Corporation 15 2019-12-22 Rev.9.0 TLP5754 18. Ordering Information (Example of Item Name) Item Name Packaging VDE Option Packing (MOQ) TLP5754(E Magazine (125 pcs) TLP5754(TP,E Tape and reel (1500 pcs) TLP5754(D4,E EN 60747-5-5 Magazine (125 pcs) TLP5754(D4-TP,E EN 60747-5-5 Tape and reel (1500 pcs) TLP5754(LF4,E LF4, Wide forming Magazine (125 pcs) TLP5754(TP4,E LF4, Wide forming Tape and reel (1500 pcs) TLP5754(D4-LF4,E LF4, Wide forming EN 60747-5-5 Magazine (125 pcs) TLP5754(D4-TP4,E LF4, Wide forming EN 60747-5-5 Tape and reel (1500 pcs) Package Dimensions Unit: mm TLP5754 Weight: 0.126 g (typ.) Package Name(s) TOSHIBA: 11-4N1A ©2015-2019 Toshiba Electronic Devices & Storage Corporation 16 2019-12-22 Rev.9.0 TLP5754 Package Dimensions Unit: mm TLP5754(LF4) Weight: 0.126 g (typ.) Package Name(s) TOSHIBA: 11-4N101A ©2015-2019 Toshiba Electronic Devices & Storage Corporation 17 2019-12-22 Rev.9.0 TLP5754 RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". • TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. 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