TLP705(TP,F)

TLP705 TOSHIBA Photocoupler IRED + Photo IC TLP705 Unit: mm Plasma Display Panel Industrial Inverter IGBT/Power MOS FET Gate Drive 4.58±0.25 Peak output current : ±0.45 A (max) : 250kHz (max) • Operating frequency • Guaranteed performance over temperature : -40 to 100°C • Supply current : 3.0mA (max) • Power supply voltage : 10 to 20 V • Threshold input current : IFLH = 8 mA (max) • Switching time (tpLH / tpHL) : 200 ns (max) • Common mode transient immunity : 10 kV/μs (min) • Isolation voltage : 5000 Vrms (min) • Construction Mechanical Rating Creepage Distance Clearance Insulation Thickness 7.0 mm (min) 7.0 mm (min) 0.4 mm (min) • • UL-recognized : UL 1577, File No.E67349 cUL-recognized : CSA Component Acceptance Service No.5A • VDE-approved : EN 60747-5-5 , EN 62368-1 (Note 1) 1 2 3 1.27±0.2 1.25±0.25 0.4±0.1 TOSHIBA 4.0 -0.20 -0.05 0.25± +0.10 7.62±0.25 +0.25 6.8±0.25 4 3.65 +0.15 -0.25 TLP705 consists of an infrared LED and an integrated photodetector. This unit is 6-lead SDIP package. TLP705 is 50% smaller than 8pin DIP and has suited the safety standard reinforced insulation class. So mounting area in safety standard required equipment can be reduced. TLP705 is suitable for gate driving circuit of IGBT or power MOS FET. Especially TLP705 is capable of “direct” gate drive of lower Power IGBTs. • 6 5 9.7±0.3 11-5J1S Weight: 0.26 g (t yp .) Pin Configuration (Top View) 1 6 2 5 3 4 SHIELD 1: ANODE 2: NC 3: CATHODE 4: GND 5: VO (OUTPUT) 6: VCC File No.E67349 Schematic Note 1: When a VDE approved type is needed, please designate the Option(D4). (Tr1) IF ICC 6 VCC 1+ Truth Table Input VF 3LED Tr1 Tr2 (Tr2) Output H ON ON OFF H L OFF OFF ON L SHIELD IO 5 VO 4 GND Note: A 0.1 µF bypass capacitor must be connected between pins 6 and 4. Start of commercial production © 2019 Toshiba Electronic Devices & Storage Corporation 1 2004-04 2019-09-25 TLP705 Absolute Maximum Ratings (Ta = 25°C) Characteristics Forward current LED Forward current derating (Ta ≥ 85°C) Peak transient forward current (Note 1) Reverse voltage Diode power dissipation Diode power dissipation derating (Ta ≥ 85°C) Detector Junction temperature Symbol Rating Unit IF 20 mA ∆IF/∆Ta -0.54 mA/°C IFP 1 A VR 5 V PD 40 mW ΔPD/°C -1.0 mW/°C Tj 125 °C “H” peak output current (Note 2) IOPH -0.45 A “L” peak output current (Note 2) IOPL 0.45 A Output voltage VO 25 V Supply voltage VCC 25 V Power dissipation PC 400 mW ΔPC / °C -4.0 mW / °C Tj 125 °C f 250 kHz Storage temperature range Tstg -55 to 125 °C Operating temperature range Topr -40 to 100 °C Power dissipation derating (Ta ≥25°C) Junction temperature Operating frequency (Note 3) Lead soldering temperature (10 s) (Note 4) Tsol 260 °C Isolation voltage (AC, 60 s, R.H. ≤ 60 %) (Note 5) BVS 5000 Vr m s Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc.). Note : A ceramic capacitor (0.1 µF) should be connected from pin 6 to pin 4 to stabilize the operation of the high gain linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length between capacitor and coupler should not exceed 1 cm. Note 1: Pulse width PW ≤ 1 µs, 300 pps Note 2: Exponential waveform pulse width PW ≤ 2 µs, f ≤15 kHz Note 3: Exponential waveform IOPH ≤-0.25 A (PW ≤80 ns), IOPL ≤+0.25 A (PW ≤80 ns), Ta = 100 °C Note 4: It is effective soldering area of Lead. Note 5: Device considered a two terminal device: pins 1, 2 and 3 shorted together, and pins 4, 5 and 6 shorted together. © 2019 Toshiba Electronic Devices & Storage Corporation 2 2019-09-25 TLP705 Recommended Operating Conditions Characteristics Input current, ON Input voltage, OFF Supply voltage Peak output current Operating temperature (Note 1) Symbol Min Typ. Max Unit IF (ON) 10  15 mA VF (OFF) 0  0.8 V VCC 10  20 V IOPH / IOPL   ± 0.15 A Topr - 40  100 °C Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the device. Additionally, each item is an independent guideline respectively. In developing designs using this product, please confirm specified characteristics shown in this document. Note: If the rising slope of the supply voltage (VCC) for the detector is steep, stable operation of the internal circuits cannot be guaranteed. Be sure to set 3.0 V/µs or less for a rising slope of the VCC. Note 1: Input signal rise time (fall time) < 0.5 µs. © 2019 Toshiba Electronic Devices & Storage Corporation 3 2019-09-25 TLP705 Electrical Characteristics (Ta = -40 to 100°C, unless otherwise specified) Symbol Test Circuit VF  ∆VF/∆Ta Input reverse current Input capacitance Characteristics Forward voltage Temperature coefficient of forward voltage “H” Level Output current (Note 1) Min Typ. Max Unit IF = 10 mA, Ta = 25 °C  1.6 1.8 V  IF = 10 mA  -2.0  mV/°C IR  VR = 5 V, Ta = 25 °C   10 µA CT  V = 0 V, f = 1 MHz, Ta = 25 °C  45  pF IOPH 1 VCC = 15 V IF = 10 mA V6-5 = 4 V -0.15 -0.35  V6-5 = 10 V -0.3 -0.6  VCC = 15 V IF = 0 mA V5-4 = 2 V 0.15 0.36  V5-4 = 10 V 0.3 0.62  IO = -100 mA, IF = 10 mA 6.0 8.5  IO = 100 mA, VF = 0.8 V  0.4 1.0  2.0 3.0  2.0 3.0 “L” Level IOPL 2 “H” Level VOH 3 Test Condition VCC = 10 V Output voltage A V “L” Level VOL 4 “H” Level ICCH 5 “L” Level ICCL 6 VCC = 10 to 20 V IF = 10 mA VO = open IF = 0 mA Threshold input current L→H IFLH  VCC = 15 V, VO > 1 V  2.5 8 mA Threshold input voltage H→L VFHL  VCC = 15 V, VO < 1 V 0.8   V VCC  10  20 V Supply current Supply voltage  mA Note: All typical values are at Ta = 25°C Note: This product is more sensitive than the conventional product to static electricity (ESD) because of a lowest power consumption design. General precaution to static electricity (ESD) is necessary for handling this component. Note 1: Duration of IO time ≤ 50 µs Isolation Characteristics (Ta = 25°C) Characteristic Symbol Test Condition Min Typ. Max Unit ― 1.0 ― pF Capacitance input to output CS V = 0 V, f = 1 MHz Isolation resistance RS R.H. ≤ 60 %, VS = 500 V 1012 1014 ― Ω Isolation voltage BVS AC, 60 s 5000 ― ― Vrms Note : Device considered a two terminal device: pins 1, 2 and 3 shorted together, and pins 4, 5 and 6 shorted together. © 2019 Toshiba Electronic Devices & Storage Corporation 4 2019-09-25 TLP705 Switching Characteristics (Ta = -40 to 100°C, unless otherwise specified) Characteristics Propagation delay time Propagation delay time Propagation delay skew Symbol L→H tpLH H→L tpHL L→H tpLH H→L tpHL (Note 1) tpsk Switching time dispersion between ON and OFF Test Circuit 7 Test Condition Min Typ. Max 70 95 170 70 105 170 50  200 50  200 Ta= -40 to100 °C IF = 10 mA -90  90 Ta= -40 to100 °C IF = 10 mA -65  65 Ta= 25 °C IF = 0→10 mA Ta= 25 °C IF = 10→ 0 mA Ta= -40 to100 °C IF = 0→10 mA Ta= -40 to100 °C IF = 10→0 mA VCC = 20 V Rg = 30 Ω Cg = 1 nF F = 250 kHz Duty Cycle = 50 % |tpHL-tpLH| Output rise time (10-90%) tr IF = 0 → 10 mA    Output fall time (90-10%) tf IF = 10 → 0 mA    IF = 10 mA VO (min) = 16 V -10000   IF = 0 mA VO (max) = 1 V 10000 Common mode transient immunity at high level output CMH 8 Common mode transient immunity at low level output CML VCM = 1000 Vp-p VCC = 20 V Ta = 25 °C Unit ns V/µs   Note: All typical values are at Ta = 25 °C Note 1: Propagation delay difference between any two parts. Test Circuit 1: IOPH 1 Test Circuit 2: IOPL 1 6 A IF 6 IOPL V6-5 IOPH A VCC 3 VCC 3 4 Test Circuit 3: VOH 1 6 Test Circuit 4: VOL 1 VOH V 6 VF IF VOL VCC 3 6 VCC V 3 4 Test Circuit 5: ICCH 1 V5-4 4 4 Test Circuit 6: ICCL 1 ICCH 6 A ICCL A VCC IF VCC 3 3 4 © 2019 Toshiba Electronic Devices & Storage Corporation 5 4 2019-09-25 TLP705 Test Circuit 7 : tpLH, tpHL, tr, tf, PWD 6 1 0.1 µF IF (f=250 kHz, Duty=50 %) VO Rg = 30 Ω Cg = 1 nF 3 IF tr VOH tf VCC 90% 50% 10% VO 4 tpHL tpLH 1: Test Circuit 8: CMH, CML IF 1 6 VCM SW A 0.1 µF VO B tf • SW A: IF = 10 mA VO VCM + 10% tr VCC 4 3 1000 V 90% - 1V • SW B: IF = 0 mA CML = CMH 16V CML 800 V tr (µs) CMH =- 800 V tf (µs) Note: CML (CMH) is the maximum rate of rise (fall) of the common mode voltage that can be sustained with the output voltage in the low (high) state. © 2019 Toshiba Electronic Devices & Storage Corporation 6 2019-09-25 TLP705 RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. 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