TMP88PS43FG

8 Bit Microcontroller TLCS-870/X Series TMP88PS43FG TMP88PS43FG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S © 2006 TOSHIBA CORPORATION All Rights Reserved Revision History Date 2007/7/12 Revision 1 First Release Table of Contents TMP88PS43FG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Functional Description 2.1 Functions of the CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Address Map ............................................................................................................................... 9 Program Memory (ROM) ........................................................................................................................ 10 Data Memory (RAM) ............................................................................................................................... 10 System Clock Control Circuit .................................................................................................................. 11 Clock Generator Timing Generator Standby Control Circuit Controlling Operation Modes External Reset Input Adress Trap Reset Watchdog Timer Reset System Clock Reset 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.4.1 2.1.4.2 2.1.4.3 2.1.4.4 2.1.5.1 2.1.5.2 2.1.5.3 2.1.5.4 Reset Circuit ........................................................................................................................................... 23 3. Interrupt Control Circuit 3.1 3.2 3.3 Interrupt latches (IL38 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt acceptance processing is packaged as follows. ....................................................................... 30 Saving/restoring general-purpose registers ............................................................................................ 31 Using Automatic register bank switcing Using register bank switching Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 27 Individual interrupt enable flags (EF38 to EF3) ...................................................................................... 27 3.3.1 3.3.2 3.4 3.5 3.3.3 3.4.1 3.4.2 3.3.2.1 3.3.2.2 3.3.2.3 3.3.2.4 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Address error detection .......................................................................................................................... 34 Debugging .............................................................................................................................................. 34 Interrupt return ........................................................................................................................................ 33 4. Special Function Register 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 i 5. Input/Output Ports 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Port P0 (P03 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P8 (P87 to P80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P9 (P97 to P90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 46 47 48 49 50 51 53 55 56 6. Time Base Timer (TBT) and Divider Output (DVO) 6.1 6.2 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT) ...................................................................................................... Watchdog Timer Reset ........................................................................................................................... 62 63 64 64 65 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 8. 16-Bit TimerCounter 1 (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Timer mode ............................................................................................................................................. External Trigger Timer Mode .................................................................................................................. Event Counter Mode ............................................................................................................................... Window Mode ......................................................................................................................................... Pulse Width Measurement Mode ............................................................................................................ Programmable Pulse Generate (PPG) Output Mode ............................................................................. 70 72 74 75 76 79 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 9. 16-Bit Timer (CTC) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Timer mode with software start ............................................................................................................... Timer mode with external trigger start .................................................................................................... Event counter mode ................................................................................................................................ Programmable Pulse Generate (PPG) output mode .............................................................................. 87 88 89 90 9.3.1 9.3.2 9.3.3 9.3.4 ii 10. 8-Bit TimerCounter 3 (TC3) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.3.1 Timer mode ........................................................................................................................................... 97 Figure 10-3 ...................................................................................................................................................... 99 10.3.3 Capture Mode ..................................................................................................................................... 100 11. 8-Bit TimerCounter 4 (TC4) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Timer Mode ......................................................................................................................................... Event Counter Mode ........................................................................................................................... Programmable Divider Output (PDO) Mode ....................................................................................... Pulse Width Modulation (PWM) Output Mode .................................................................................... 103 103 103 104 11.3.1 11.3.2 11.3.3 11.3.4 12. 8-Bit TimerCounter 5,6(TC5, 6) 12.1 12.2 12.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8-Bit Timer Mode (TC5 and 6) ............................................................................................................ 8-Bit Event Counter Mode (TC5, 6) .................................................................................................... 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)................................................................. 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6).............................................................. 16-Bit Timer Mode (TC5 and 6) .......................................................................................................... 16-Bit Event Counter Mode (TC5 and 6) ............................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ........................................... 112 113 113 115 117 118 118 121 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 13. Motor Control Circuit (PMD: Programmable motor driver) 13.1 13.2 13.3 Outline of Motor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Configuration of the Motor Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Position Detection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Configuration of the position detection unit ......................................................................................... 128 Position Detection Circuit Register Functions ..................................................................................... 129 Outline Processing in the Position Detection Unit .............................................................................. 132 13.4 13.5 13.3.1 13.3.2 13.3.3 13.4.1 Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Configuration of the Timer Unit ........................................................................................................... 134 Timer Circuit Register Functions Outline Processing in the Timer Unit 13.4.1.1 13.4.1.2 Three-phase PWM Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Configuration of the three-phase PWM output unit ............................................................................. 138 Register Functions of the Waveform Synthesis Circuit ....................................................................... Port output as set with UOC/VOC/WOC bits and UPWM/VPWM/WPWM bits ................................... Protective Circuit ................................................................................................................................. Functions of Protective Circuit Registers ............................................................................................ Pulse width modulation circuit (PWM waveform generating unit) Commutation control circuit 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 13.5.1.1 13.5.1.2 13.6 Electrical Angle Timer and Waveform Arithmetic Circuit . . . . . . . . . . . . . . . . . . 150 142 144 146 148 iii 13.6.1 Electrical Angle Timer and Waveform Arithmetic Circuit .................................................................... 151 Functions of the Electrical Angle Timer and Waveform Arithmetic Circuit Registers List of PMD Related Control Registers 13.6.1.1 13.6.1.2 14. Asynchronous Serial interface (UART) 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 168 Data Receive Operation ..................................................................................................................... 168 169 169 169 170 170 171 163 164 166 167 167 168 168 168 14.8.1 14.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Parity Error .......................................................................................................................................... Framing Error ...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full ..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 14.9.1 14.9.2 14.9.3 14.9.4 14.9.5 14.9.6 15. Synchronous Serial Interface (SIO) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Clock source ....................................................................................................................................... 175 Shift edge ............................................................................................................................................ 177 Leading edge Trailing edge Internal clock External clock 15.3.1.1 15.3.1.2 15.3.2.1 15.3.2.2 15.3.1 15.3.2 15.4 15.5 15.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 4-bit and 8-bit transfer modes ............................................................................................................. 178 4-bit and 8-bit receive modes ............................................................................................................. 180 8-bit transfer / receive mode ............................................................................................................... 181 15.6.1 15.6.2 15.6.3 16. 10-bit AD Converter (ADC) 16.1 16.2 16.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Software Start Mode ........................................................................................................................... 187 Repeat Mode ...................................................................................................................................... 187 Register Setting ................................................................................................................................ 188 16.4 16.5 16.6 16.3.1 16.3.2 16.3.3 STOP mode during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 190 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Analog input pin voltage range ........................................................................................................... 191 16.6.1 iv 16.6.2 16.6.3 Analog input shared pins .................................................................................................................... 191 Noise Countermeasure ....................................................................................................................... 191 17. 8-Bit High-speed PWM (HPWM0 and HPWM1) 17.1 17.2 17.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Operation modes ................................................................................................................................ 194 8-bit mode 7-bit mode 6-bit mode 17.3.1.1 17.3.1.2 17.3.1.3 17.3.1 17.3.2 Setting output data .............................................................................................................................. 197 18. OTP operation 18.1 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MCU mode .......................................................................................................................................... 199 Program Memory Data Memory Input/Output Circuiry 18.1.1.1 18.1.1.2 18.1.1.3 18.1.2.1 18.1.2.2 18.1.1 18.1.2 PROM mode ....................................................................................................................................... 200 Programming Flowchart (High-speed program writing) Program Writing using a General-purpose PROM Programmer 19. Input/Output Circuitry 19.1 19.2 Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 20. Electrical Characteristics 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics, AC Characteristics (PROM mode) . . . . . . . . . . . . . . . . . . . Read operation in PROM mode .......................................................................................................... 210 Program operation (High-speed) ........................................................................................................ 211 207 208 208 209 209 210 20.6.1 20.6.2 Recommended Oscillation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 21. Package Dimensions This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/X (LSI). v vi TMP88PS43FG CMOS 8-Bit Microcontroller TMP88PS43FG The TMP88PS43FG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 65536 bytes of One-Time PROM. It is pin-compatible with the TMP88CS43FG (Mask ROM version). The TMP88PS43FG can realize operations equivalent to those of the TMP88CS43FG by programming the on-chip PROM. Product No. TMP88PS43FG ROM (EPROM) 65536 bytes RAM 4224 bytes Package QFP80-P-1420-0.80B MaskROM MCU TMP88CS43FG 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/X series - Instruction execution time : 0.20 µs (at 20 MHz) - 181 types & 842 basic instructions 2. 35 interrupt sources (External : 6 Internal : 29) 3. Input / Output ports (71 pins) Large current output: 24pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer Divider output function (DVO) 5. Watchdog Timer Select of "internal reset request" or "interrupt request". 6. 16-bit timer counter: 1 ch - Timer, External trigger, Window, Pulse width measurement, Event counter, Programmable pulse generate (PPG) modes 7. 16-bit timer/counter(CTC): 1ch - CTC:Timer,event counter or PPG (Programmable Pulse) output 8. 8-bit timer counter : 1 ch 060116EBP • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP88PS43FG - Timer, Event counter, Capture modes 9. 8-bit timer counter : 1 ch - Timer, Event counter, Pulse width modulation (PWM) output, Programmable divider output (PDO) modes 10. 8-bit timer counter : 2 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 11. Programmable motor driver (PMD) : 2 ch - Sine wave drive circuit (built-in sine wave data-table RAM) Rotor position detect function Motor contro timer and capture function Overload protective function Auto commutation and auto position detection start function 12. 8-bit UART : 1 ch 13. 8-bit SIO: 1 ch 14. 10-bit successive approximation type AD converter - Analog input: 16 ch 15. 8-bit High-speed PWM (HPWM0 and HPWM1) 16. Clock oscillation circuit : 1 set 17. Low power consumption operation (2 modes) - STOP mode: Oscillation stops. (Battery/Capacitor back-up.) - IDLE mode: CPU stops. Only peripherals operate using high frequency clock. Release by interruputs (CPU restarts). 18. Operation voltage: 4.5 V to 5.5 V at 20MHz Page 2 TMP88PS43FG 1.2 Pin Assignment VSS XIN XOUT TEST VDD (TC3/INT3) P21 (PWM4/PDO4/TC4/INT4) P22 RESET Figure 1-1 Pin Assignment (STOP/INT5) P20 (Z1) P30 (Y1) P31 (X1) P32 (W1) P33 (V1) P34 (U1) P35 (EMG1) P36 (CL1) P37 (PDW1) P40 (PDV1) P41 (PDU1) P42 (SCK) P43 (SI/RXD1) P44 (SO/TXD1) P45 (PPG2) P46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (INT0) P10 (INT1) P11 (TC1/INT2) P12 (TC5/DVO) P13 (PWM5/PDO5/PPG1) P14 (PDU2) P15 (PDV2) P16 (PDW2) P17 (CL2) P50 (EMG2) P51 (U2) P52 (V2) P53 (W2) P54 (X2) P55 (Y2) P56 (Z2) P57 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P03 (HPWM1) P02 (HPWM0) P01 (TXD2/PDO6/PWM6/PPG6) P00 (RXD2/TC6) P97 P96 P95 P94 P93 P92 P91 P90 P87 P86 P85 P84 P83 P82 P81 P80 AVSS AVDD VAREF P77 (AIN15/DBOUT2) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P76 (AIN14) P75 (AIN13) P74 (AIN12) P73 (AIN11) P72 (AIN10) P71 (AIN9) P70 (AIN8) P67 (AIN7/DBOUT1) P66 (AIN6) P65 (AIN5) P64(AIN4) P63(AIN3) P62(AIN2) P61(AIN1) P60(AIN0) P47(CTC) Page 3 1.3 Block Diagram TMP88PS43FG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP88PS43FG 1.4 Pin Names and Functions The TMP88PS43FG has MCU mode and PROM mode. Table 1-1 shows the pin functions in MCU mode. The PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/4) Pin Name P03 HPWM1 Pin Number 64 Input/Output IO O IO O IO O O IO I I IO I IO I IO I IO O O IO O I IO I I IO I IO I IO I I O IO I I IO I I IO I IO I Functions PORT03 High-spped PWM1 output PORT02 High-spped PWM0 output PORT01 UART data output 2 PDO6/PWM6/PPG6 output PORT00 UART data input 2 TC6 input PORT17 PMD control input W2 PORT16 PMD control input V2 PORT15 PMD control input U2 PORT14 PPG1 output PWM5/PDO5 output PORT13 Divider Output TC5 input PORT12 External interrupt 2 input TC1 input PORT11 External interrupt 1 input PORT10 External interrupt 0 input PORT22 External interrupt 4 input TC4 input PWM4/PDO4 output PORT21 External interrupt 3 input TC3 pin input PORT20 External interrupt 5 input STOP mode release signal input PORT37 PMD over load protection input1 PORT36 PMD emergency stop input1 P02 HPWM0 63 P01 TXD2 PDO6/PWM6/PPG6 62 P00 RXD2 TC6 P17 PDW2 P16 PDV2 P15 PDU2 P14 PPG1 PWM5/PDO5 61 72 71 70 69 P13 DVO 68 TC5 P12 INT2 TC1 P11 INT1 P10 INT0 67 66 65 P22 INT4 TC4 PWM4/PDO4 7 P21 INT3 TC3 P20 INT5 STOP 6 9 P37 CL1 17 P36 EMG1 16 Page 5 1.4 Pin Names and Functions TMP88PS43FG Table 1-1 Pin Names and Functions(2/4) Pin Name P35 U1 P34 V1 P33 W1 P32 X1 P31 Y1 P30 Z1 P47 CTC P46 PPG2 Pin Number 15 Input/Output IO O IO O IO O IO O IO O IO O I I IO O IO O O IO I I IO IO IO I IO I IO I IO O IO O IO O IO O IO O IO O IO I IO I PORT35 PMD control output U1 PORT34 PMD control output V1 PORT33 PMD control output W1 PORT32 PMD control output X1 PORT31 PMD control output Y1 PORT30 PMD control output Z1 PORT47 CTC input PORT46 PPG2èoóÕ PORT45 UART data output 1 Serial Data Output PORT44 UART data input 1 Serial Data Input PORT43 Serial Clock I/O PORT42 PMD control input U1 PORT41 PMD control input V1 PORT40 PMD control input W1 PORT57 PMD control output Z2 PORT56 PMD control output Y2 PORT55 PMD control output X2 PORT54 PMD control output W2 PORT53 PMD control output V2 PORT52 PMD control output U2 Functions 14 13 12 11 10 25 24 P45 TXD1 SO P44 RXD1 SI P43 SCK 23 22 21 P42 PDU1 P41 PDV1 P40 PDW1 P57 Z2 P56 Y2 P55 X2 P54 W2 P53 V2 P52 U2 P51 EMG2 20 19 18 80 79 78 77 76 75 74 PORT51 PMD emergency stop input2 PORT50 PMD over load protection input2 P50 CL2 73 Page 6 TMP88PS43FG Table 1-1 Pin Names and Functions(3/4) Pin Name P67 AIN7 DBOUT1 P66 AIN6 P65 AIN5 P64 AIN4 P63 AIN3 P62 AIN2 P61 AIN1 P60 AIN0 P77 AIN15 DBOUT2 P76 AIN14 P75 AIN13 P74 AIN12 P73 AIN11 P72 AIN10 P71 AIN9 P70 AIN8 P87 P86 P85 P84 P83 P82 P81 P80 P97 P96 Pin Number Input/Output IO I O IO I IO I IO I IO I IO I IO I IO I IO I O IO I IO I IO I IO I IO I IO I IO I IO IO IO IO IO IO IO IO IO IO PORT67 Analog Input7 PMD debug output1 PORT66 Analog Input6 PORT65 Analog Input5 PORT64 Analog Input4 PORT63 Analog Input3 PORT62 Analog Input2 PORT61 Analog Input1 PORT60 Analog Input0 PORT77 Analog Input15 PMD debug output2 PORT76 Analog Input14 PORT75 Analog Input13 PORT74 Analog Input12 PORT73 Analog Input11 PORT72 Analog Input10 PORT71 Analog Input9 PORT70 Analog Input8 PORT87 PORT86 PORT85 PORT84 PORT83 PORT82 PORT81 PORT80 PORT97 PORT96 Functions 33 32 31 30 29 28 27 26 41 40 39 38 37 36 35 34 52 51 50 49 48 47 46 45 60 59 Page 7 1.4 Pin Names and Functions TMP88PS43FG Table 1-1 Pin Names and Functions(4/4) Pin Name P95 P94 P93 P92 P91 P90 XIN XOUT RESET Pin Number 58 57 56 55 54 53 2 3 8 Input/Output IO IO IO IO IO IO I O I PORT95 PORT94 PORT93 PORT92 PORT91 PORT90 Functions Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test and the Serial PROM mode control pin. Usually fix to low level. Fix to high level when the Serial PROM mode starts. Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply Analog Power Supply +5V 0(GND) TEST 4 I VAREF AVDD AVSS VDD VSS 42 43 44 5 1 I I I I I Page 8 TMP88PS43FG 2. Functional Description 2.1 Functions of the CPU Core The CPU core consists mainly of the CPU, system clock control circuit, and interrupt control circuit. This chapter describes the CPU core, program memory, data memory, and reset circuit of the TMP88PS43FG. 2.1.1 Memory Address Map The memory of the TMP88PS43FG consists of four blocks: ROM, RAM, SFR (Special Function Registers), and DBR (Data Buffer Registers), which are mapped into one 1-Mbyte address space. The general-purpose registers consist of 16 banks, which are mapped into the RAM address space. Figure 2-1 shows a memory address map of the TMP88PS43FG. SFR RAM (128 bytes) RAM ( 4K bytes) 010BFH 00000H 0003FH 00040H 000BFH 000C0H 64 bytes 128 bytes 4096 bytes Special Function Register General-purpose Register Bank (8 registers × 16 banks) Random-Access Memory DBR 01F80H 128 bytes 01FFFH 04000H Data Buffer Register (peripheral hardware control register / status register) 65280 bytes Program Memory ROM ( 64K Kbytes) 13EFFH FFF00H FFF3FH FFF40H FFF7FH FFF80H FFFFFH 64 bytes 64 bytes 128 bytes Interrupt Vector Table Vector Table for Vector Call Instructions Interrupt Vector Table SFR: Special Function Registers Input/output port Peripheral hardware control register Peripheral hardware status register RAM: Random Access Memory System control register Data memory Interrupt control register Stack Program status word General-purpose register bank ROM: Read-Only Memory Program memory Vector Table DBR: Data Buffer Registers Input/output port Peripheral hardware control register Peripheral hardware status register Figure 2-1 Memory address map Page 9 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG 2.1.2 Program Memory (ROM) The TMP88PS43FG contains 64Kbytes program memory (OTP) located at addresses 04000H to 13EFFH and addresses FFF00H to FFFFFH. 2.1.3 Data Memory (RAM) The TMP88PS43FG contains 4Kbytes +128bytes RAM. The first 128bytes location (00040H to 000BFH) of the internal RAM is shared with a general-purpose register bank. The content of the data memory is indeterminate at power-on, so be sure to initialize it in the initialize routine. Example :Clearing the internal RAM of the TMP88PS43FG (clear all RAM addresses to 0, except bank 0) LD LD LD SRAMCLR: LD DEC JRS HL, 0048H A, 00H BC, 1077H (HL+), A BC F, SRAMCLR ; Set the start address ; Set the initialization data (00H) ; Set byte counts (-1) Note:Because general-purpose registers exist in the RAM, never clear the current bank address of RAM. In the above example, the RAM is cleared except bank 0. Page 10 TMP88PS43FG 2.1.4 System Clock Control Circuit The System Clock Control Circuit consists of a clock generator, timing generator, and standby control circuit. Timing generator control register Clock generator XIN High-frequency clock oscillator circuit XOUT fc Timing generator Standby control circuit 00038H SYSCR1 System clocks 00039H SYSCR2 TBTCR 00036H System control register Figure 2-2 System Clock Control Circuit 2.1.4.1 Clock Generator The Clock Generator generates the fundamental clock which serves as the reference for the system clocks supplied to the CPU core and peripheral hardware units. The high-frequency clock (frequency fc) can be obtained easily by connecting a resonator to the XIN and XOUT pins. Or a clock generated by an external oscillator can also be used. In this case, enter the external clock from the XIN pin and leave the XOUT pin open. The TMP88PS43FG does not support the CR network that produces a time constant. High-frequency Clock XIN XOUT XIN XOUT (Open) (a) Using a crystal or ceramic resonator (b) Using an external oscillator Figure 2-3 Example for Connecting a Resonator Adjusting the oscillation frequency Note: Although no hardware functions are provided that allow the fundamental clock to be monitored directly from the outside, the oscillation frequency can be adjusted by forwarding the pulse of a fixed frequency (e.g., clock output) to a port and monitoring it in a program while interrupts and the watchdog timer are disabled. For systems that require adjusting the oscillation frequency, an adjustment program must be created beforehand. 2.1.4.2 Timing Generator The Timing Generator generates various system clocks from the fundamental clock that are supplied to the CPU core and peripheral hardware units. The Timing Generator has the following functions: Page 11 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG 1. Generate a divider output (DVO) pulse 2. Generate the source clock for the time base timer 3. Generate the source clock for the watchdog timer 4. Generate the internal source clock for the timer counter 5. Generate a warm-up clock when exiting STOP mode (1) Configuration of the Timing Generator The Timing Generator a 3-stage prescaler, 21-stage dividers, and a machine cycle counter. When reset and when entering/exiting STOP mode, the prescaler and dividers are cleared to 0. Machine cycle counter DV1CK Prescaler fc S A Y B Selector Divider Divider 012 123456 7 8 9 10111213141516171819 2021 Standby control circuit Watchdog timer Timer counter Time base timer Divider Output etc. Figure 2-4 Configuration of the Timing Generator Page 12 TMP88PS43FG Divider Control Register CGCR (0030H) 7 0 6 0 5 DV1CK 4 3 2 0 1 0 0 0 (Initial value: 000* *000) DV1CK Selects input clock to the first divider stage 0: fc/4 1: fc/8 R/W Note 1: fc: the high-frequency clock [Hz], *: Don’t care Note 2: The CGCR Register bits 4 and 3 show an indeterminate value when read. Note 3: Be sure to write “0” to CGCR Register bits 7, 6, 2, 1 and 0. Timing Generator Control Register TBTCR (0036H) 7 DVOEN 6 DVOCK 5 4 0 3 TBTEN 2 1 TBTCK 0 (Initial value: 0000 0000) Note 1: *: Don’t care Note 2: Be sure to write “0” to TBTCR Register bit 4. (2) Machine cycle Instruction execution and the internal hardware operations are synchronized to the system clocks. The minimum unit of instruction execution is referred to as the “mgmachine cycle”. The TLCS870/X series has 15 types of instructions, from 1-cycle instructions which are executed in one machine cycle up to 15-cycle instructions that require a maximum of 15 machine cycles. A machine cycle consists of four states (S0 to S3), with each state comprised of one main system clock cycle. 1/fc Main system clock States S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle (0.20 µs at 20 MHz) Figure 2-5 Machine Cycles Page 13 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG 2.1.4.3 Standby Control Circuit The Standby Control Circuit starts/stops the high-frequency clock oscillator circuit and selects the main system clock. The System Control Registers (SYSCR1, SYSCR2) are used to control operation modes of this circuit. Figure 2-6 shows an operation mode transition diagram, followed by description of the System Control Registers. (1) Single clock mode Only the high-frequency clock oscillator circuit is used. Because the main system clock is generated from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s]. 1. NORMAL mode In this mode, the CPU core and peripheral hardware units are operated with the high-frequency clock. The TMP88PS43FG enters this NORMAL mode after reset. 2. IDLE mode In this mode, the CPU and watchdog timer are turned off while the peripheral hardware units are operated with the high-frequency clock. IDLE mode is entered into by using System Control Register 2. The device is placed out of this mode and back into NORMAL mode by an interrupt from the peripheral hardware or an external interrupt. When IMF (interrupt master enable flag) = 1 (interrupt enabled), the device returns to normal operation after the interrupt has been serviced. When IMF = 0 (interrupt disabled), the device restarts execution beginning with the instruction next to one that placed it in IDLE mode. 3. STOP mode The entire system operation including the oscillator circuit is halted, retaining the internal state immediately before being stopped, with a minimal amount of power consumed. STOP mode is entered into by using System Control Register 1, and is exited by STOP pin input (level or edge selectable). After an elapse of the warm-up time, the device restarts execution beginning with the instruction next to one that placed it in STOP mode. Table 2-1 Single Clock Mode Oscillator Circuit Operation Mode High Frequency Low Frequency CPU Core Peripheral Circuit Reset 4/fc [s] Operate Stop STOP Stop Stop Machine Cycle Time RESET Single Clock NORMAL IDLE Oscillate - Reset Operate RESET Reset deasserted Instruction NORMAL mode Interrupt Input for releasing mode STOP mode Instruction IDLE mode Figure 2-6 Operation Mode Transition Diagram Page 14 TMP88PS43FG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP Place the device in STOP mode Select method by which the device is released from STOP mode Select operation mode after exiting STOP mode Select port output state during STOP mode 0: Keep the CPU core and peripheral hardware operating 1: Stop the CPU core and peripheral hardware (placed in STOP mode) 0: Released by a rising edge on STOP pin input 1: Released by a high level on STOP pin input 0: Returns to NORMAL mode 1: Reserved 0: High-impedance state 1: Hold output When Returning to NORMAL Mode DV1CK = 0 DV1CK = 1 3 × 217/fc 217/fc 215/fc Reserved R/W RELM RETM OUTEN WUT Unit of warm-up time when exiting STOP mode 00 01 10 11 3 × 216/fc 216/fc 214/fc Reserved Note 1: When entering from NORMAL mode into STOP mode, always be sure to set SYSCR1 to 0. Note 2: When the device is released from STOP mode by RESET pin input, it always returns to NORMAL mode regardless of how SYSCR1 is set. Note 3: fc: High-frequency clock [Hz], *: Don’t care Note 4: The values of the SYSCR1 Register bits 1 and 0 are indeterminate when read. Note 5: When placed the device in STOP mode, make sure to set "1" to SYSCR1. Note 6: Releasing the device from the STOP mode causes the STOP bit to be automatically cleared to “0”. Note 7: Select an appropriate value for the warm-up time according to the characteristic of the resonator used. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 0 5 SYSCK 4 IDLE 3 2 1 0 (Initial value: 1000 ****) XEN SYSCK IDLE Control high-frequency oscillator Select (write)/monitor (read) system clock Place the device in IDLE mode 0: Stop oscillation 1: Continue or start oscillating 0: High-frequency clock (NORMAL/IDLE) 1: Reserved 0: Keep the CPU and WDT operating 1: Stop the CPU and WDT (IDLE mode entered) R/W R/W R/W RETM 0 1 Operation Mode after Releasing STOP Mode NORMAL mode No operation XEN 1 0 SYSCK 0 1 Note 1: When exiting STOP mode, SYSCR2 are automatically rewritten according to SYSCR1.. Note 2: When SYSCR2is cleared to 0, the device is reset. Note 3: WDT: Watchdog Timer, *: Don’t care Note 4: Be sure to write "0" to SYSCR2 Register bit6. Note 5: The values of the SYSCR2 Register bits 3 to 0 are indeterminate when read. Note 6: Change the operation mode after disabling external interrupts. If interrupts are enabled after changing operation mode, clear interrupt latches as appropriate in advance. Page 15 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG 2.1.4.4 Controlling Operation Modes (1) STOP mode STOP mode is controlled by System Control Register 1 (SYSCR1) and the STOP pin input. The STOP pin is shared with P20 port and INT5 (external interrupt input 5). STOP mode is entered into by setting STOP (SYSCR1 Register bit 7) to 1. During STOP mode, the device retains the following state. 1. Stop oscillation, thereby stopping operation of all internal circuits. 2. The data memory, register, program status word, and port output latch hold the state in which they were immediately before entering STOP mode. 3. Clear the prescaler and divider for the timing generator to 0. 4. The program counter holds the instruction address two instructions ahead the one that placed the device in STOP mode (e.g., “SET (SYSCR1).7”). The device is released from STOP mode by the active level or edge on STOP pin input as selected by SYSCR1. Note: Before entering STOP mode, be sure to disable interrupts. This is because if the signal on an external interrupt pin changes state during STOP (from entering STOP mode till completion of warm-up) the interrupt latch is set to 1, so that the device may accept the interrupt immediately after exiting STOP mode. Also, when reenabling interrupts after exiting STOP mode, be sure to clear the unnecessary interrupt latches beforehand. a. Released by level (when RELM = 1) The device is released from STOP mode by a high level on STOP pin input. Any instruction to place the device in STOP mode is ignored when executed while STOP pin input level is high, and the device immediately goes to a release sequence (warm-up) without entering STOP mode. Therefore, before STOP mode can be entered while RELM = 1, the STOP pin input must be verified to be low in a program. There are following methods to do this verification. 1. Testing the port status 2. INT5 interrupt (interrupt generated at a falling edge on INT5 pin input) Example 1 :Entering STOP mode from NORMAL mode by testing P20 port LD SSTOPH : TEST JRS DI SET (SYSCR1) . 7 (SYSCR1), 01010000B (P2DR) . 0 F, SSTOPH ; IMF ← 0 ; Place the device in STOP mode ; Select to be released from STOP mode by level ; Wait until STOP pin input goes low Example 2 :Entering STOP mode from NORMAL mode by INT5 interrupt PINT5 : TEST (P2DR) . 0 ; Do not enter STOP mode if P20 port input level is high, to eliminate noise ; Do not enter STOP mode if P20 port input level is high, to eliminate noise ; Select to be released from STOP mode by level ; IMF ← 0 (SYSCR1) . 7 ; Place the device in STOP mode JRS LD DI SET SINT5 : RETI F, SINT5 (SYSCR1), 01010000B Page 16 TMP88PS43FG STOP pin VIH XOUT pin NORMAL operation STOP mode Detect low on STOP pin input in a program before entering STOP mode Warm-up NORMAL operation Released from STOP mode in hardware Always released by a high level on STOP pin input Figure 2-7 Released from STOP Mode by Level Note 1: Once warm-up starts, the device does not return to STOP mode even when the STOP pin input is pulled low again. Note 2: If RELM is changed to 1 (level mode) after being set to 0 (edge mode), STOP mode remains unchanged unless a rising edge on STOP pin input is detected. a. Released by edge (when RELM = 0) The device is released from STOP mode by a rising edge on STOP pin input. This method is used in applications where a relatively short time of program processing is repeated at certain fixed intervals. Apply a fixed-period signal (e.g., clock from the low-power oscillating source) to the STOP pin. When RELM = 0 (edge mode), the device is placed in STOP mode even when the STOP pin input level is high. Example :Entering STOP mode from NORMAL mode DI LD (SYSCR1) , 10010000B ; IMF ← 0 ; Set to be released by edge when entering STOP mode STOP pin VIH XOUT pin NORMAL operation Placed into STOP mode in a program STOP mode Warm-up NORMAL operation STOP mode Released from STOP mode in hardware by a rising edge on STOP pin input. Figure 2-8 Released from STOP Mode by Edge Page 17 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG The device is released from STOP mode following the sequence described below. 1. Only the high-frequency oscillator is oscillating. 2. A warm-up time is inserted in order to allow for the clock oscillation to stabilize. During warm-up, the internal circuits remain idle. The warm-up time can be selected from three choices according to the oscillator characteristics by using SYSCR1. 3. After an elapse of the warm-up time, the device restarts normal operation beginning with the instruction next to one that placed it in STOP mode. At this time, the prescaler and divider for the timing generator start from the zero-cleared state. Table 2-2 Warm-up Time (Example: fc = 20 MHz) Warm-up Time [ms] WUT When Returning to NORMAL Mode DV1CK = 0 00 01 10 11 9.831 3.277 0.819 Reserved DV1CK = 1 19.662 6.554 1.638 Reserved Note: Because the warm-up time is obtained from the fundamental clock by dividing it, if the oscillation frequency fluctuates while exiting STOP mode, the warm-up time becomes to have some error. Therefore, the warm-up time must be handled as an approximate value. The device can also be released from STOP mode by pulling the RESET pin input low, in which case the device is immediately reset as is normally reset by RESET. After reset, the device starts operating from NORMAL mode. Note: When exiting STOP mode while the device is retained at low voltage, the following caution is required. Before exiting STOP mode, the power supply voltage must be raised to the operating voltage. At this time, the RESET pin level also is high and rises along with the power supply voltage. If the device has a time-constant circuit added external to the chip, the voltage on RESET pin input does not rise as fast as the power supply voltage. Therefore, if the voltage level on RESET pin input is below the RESET pin’s noninverted, high-level input voltage (hysteresis input), the device may be reset. Page 18 Oscillator circuit Oscillation Stop Main system clock a+3 Stop Program counter SET (SYSCR1). 7 a+2 Instruction execution n+1 n+2 n+3 n+4 Divider n 0 (a) Entering STOP mode (Example: Entered into by the SET (SYSCR1). 7 instruction placed at address a) Figure 2-9 Entering and Exiting STOP Mode (when DV1CK = 0) a+3 a+4 a+5 a+6 Instruction at address a + 2 Instruction at address a + 3 0 (b) Exiting STOP mode 1 2 3 Page 19 Warm-up STOP pin input Oscillator circuit Stop Oscillation Main system clock Program counter Instruction execution Stop Instruction at address a + 4 Divider 0 Count up TMP88PS43FG 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG (2) IDLE mode IDLE mode is controlled by System Control Register 2 (SYSCR2) and a maskable interrupt. During IDLE mode, the device retains the following state. 1. The CPU and watchdog timer stop operating. The peripheral hardware continues operating. 2. The data memory, register, program status word, and port output latch hold the state in which they were immediately before entering IDLE mode. 3. The program counter holds the instruction address two instructions ahead the one that placed the device in IDLE mode. Example :Placing the device in IDLE mode SET (SYSCR2) . 4 Place the device in IDLE mode (by instruction) Stop the CPU and WDT Reset input ? No No Yes Reset Interrupt request ? Yes No IMF = 1 Yes (Released by interrupt) (Released normally) Interrupt handling Execute the instruction next to one that placed device IDLE mode Figure 2-10 IDLE Mode Page 20 TMP88PS43FG The device can be released from IDLE mode normally or by an interrupt as selected with the interrupt master enable flag (IMF). a. Released normally (when IMF = 0) The device can be released from IDLE mode by the interrupt source enabled by the interrupt individual enable flag (EF), and restarts execution beginning with the instruction next to one that placed it in IDLE mode. The interrupt latch (IL) for the interrupt source used to exit IDLE mode normally needs to be cleared to 0 using a load instruction. b. Released by interrupt (when IMF = 1) The device can be released from IDLE mode by the interrupt source enabled by the interrupt individual enable flag (EF), and enters interrupt handling. After interrupt handling, the device returns to the instruction next to one that placed it in IDLE mode. The device can also be released from IDLE mode by pulling the RESET pin input low, in which case the device is immediately reset as is normally reset by RESET. After reset, the device starts operating from NORMAL mode. Note: If a watchdog timer interrupt occurs immediately before entering IDLE mode, the device processes the watchdog timer interrupt without entering IDLE mode. Page 21 Main system clock 2. Functional Description 2.1 Functions of the CPU Core Interrupt request a+2 a+3 IDLE Program counter SET (SYSCR2). 4 Instruction execution Operating Watchdog timer (a) Entering IDLE mode (Example: Entered into by the SET instruction placed at address a) Main system clock Interrupt request a+3 a+4 Program counter Instruction at address a + 2 Figure 2-11 Entering and Exiting IDLE Mode Operating a+3 Interrupt accepted Operating Page 22 Instruction execution IDLE Watchdog timer IDLE 1. Released normally Main system clock Interrupt request Program counter Instruction execution IDLE Watchdog timer IDLE 2. Released by interrupt TMP88PS43FG (b) Exiting IDLE mode TMP88PS43FG 2.1.5 Reset Circuit The TMP88PS43FG has four ways to generate a reset: external reset input, address trap reset, watchdog timer reset, or system clock reset. Table 2-3 shows how the internal hardware is initialized by reset operation. At power-on time, the internal cause reset circuits (watchdog timer reset, address trap reset, and system clock reset) are not initialized. Table 2-3 Internal Hardware Initialization by Reset Operation Internal Hardware Program Counter (PC) Stack Pointer (SP) General-purpose Registers (W, A, B, C, D, E, H, L) Register Bank Selector (RBS) Jump Status Flag (JF) Zero Flag (ZF) Carry Flag (CF) Half Carry Flag (HF) Sign Flag (SF) Overflow Flag (VF) Interrupt Master Enable Flag (IMF) Interrupt Individual Enable Flag (EF) Interrupt Latch (IL) Interrupt Nesting Flag (INF) Initial Value (FFFFEH to FFFFCH) Not initialized Not initialized 0 Watchdog timer 1 Not initialized Not initialized Not initialized Output latch of input/output port Not initialized Not initialized 0 0 Control register 0 0 RAM See description of each control register. Not initialized See description of each input/output port. Enable Prescaler and divider for the timing generator 0 Internal Hardware Initial Value 2.1.5.1 External Reset Input The RESET pin is a hysteresis input with a pull-up resistor included. By holding the RESET pin low for at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operating voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initialized. When the RESET pin input is released back high, the device is freed from reset and starts executing the program beginning with the vector address stored at addresses FFFFCH to FFFFEH. VDD RESET Reset input Figure 2-12 Reset Circuit 2.1.5.2 Adress Trap Reset If the CPU should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal RAM,SFR or DBR area, the device generats an internal reset. The addess trap permission/prohibition is set by the address trap reset control register (ATAS,ATKEY). The address trap is permited initially and the internal reset is generated by fetching from internal RAM,SFR or DBR area. If the address trap is prohibited, instructions in the internal RAM area can be executed. Page 23 2. Functional Description 2.1 Functions of the CPU Core TMP88PS43FG Address Trap Control Register ATAS (1F94H) 7 6 5 4 3 2 1 0 ATAS (initial value: **** ***0) ATAS Select the address trap permission / prohibition 0: Permit address trap 1: Prohibit address trap (It may be available after setting control code for ATKEY register) Write only Address Trap Control Code Register ATKEY (1F95H) 7 6 5 4 3 2 1 0 (initial value: **** ****) ATKEY Write control code to prohibit address trap D2H: Address trap prohibition code Others: Ineffective Write only Note: Read-modify-write instructions, such as a bit manipulation, cannot access ATAS or ATKEY register because these register are write only. Note 1: In development tools, address trap cannot be prohibited in the internal RAM,SFR or DBR area with the address trap control registers. When using development tools, even if the address trap permission/prohibition setting is changed in the user’s program, this change is ineffective. To execute instructions from the RAM area, development tools must be set accordingly. Note 2: While the SWI instruction at an address immediately before the address trap area is executing, the program counter is incremented to point to the next address in the address trap area; an address trap is therefore taken immediately. Development tool setting • To prohibit the address trap: 1. Modify the iram (mapping attribute) area to (00040H to 000BFH) in the memory map window. 2. Set 000C0H to "address trap prohibition area" as a new eram (mapping attribute) area. 3. Load the user program 4. Execute the address trap prohibition code in the user’s program 2.1.5.3 Watchdog Timer Reset Refer to the Section “Watchdog Timer.” 2.1.5.4 System Clock Reset When SYSCR2 is cleared to 0 or when SYSCR2 is cleared to 0 while SYSCR2 = 0, the system clock is turned off, causing the CPU to become locked up. To prevent this problem, upon detecting SYSCR2 = 0, SYSCR2 = SYSCR2 = 0 or SYSCR2 = 1, the device automatically generates an internal reset signal to let the system clock continue oscillating. Page 24 TMP88PS43FG 3. Interrupt Control Circuit The TMP88PS43FG has a total of 35 interrupt sources excluding reset. Interrupts can be nested with priorities. Two of the internal interrupt sources are pseudo nonmaskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch – – IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL24 IL25 IL26 IL27 IL28 IL29 IL30 IL31 IL32 IL33 IL34 IL35 IL36 IL37 IL38 Vector Address FFFFC FFFF8 FFFF4 FFFF0 FFFEC FFFE8 FFFE4 FFFE0 FFFDC FFFD8 FFFD4 FFFD0 FFFCC FFFC8 FFFC4 FFFC0 FFFBC FFFB8 FFFB4 FFFB0 FFFAC FFFA8 FFFA4 FFFA0 FFF9C FFF98 FFF94 FFF90 FFF8C FFF88 FFF84 FFF80 FFF3C FFF38 FFF34 FFF30 FFF2C FFF28 FFF24 Interrupt Factors Internal/External Internal Internal External (Reset) INTSWI (Software interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Nonmaskable Pseudo nonmaskable Pseudo nonmaskable IMF• EF3 = 1, INT0EN = 1 IMF• EF4 = 1 IMF• EF5 = 1 IMF• EF6 = 1 IMF• EF7 = 1 IMF• EF8 = 1 IMF• EF9 = 1 IMF• EF10 = 1 IMF• EF11 = 1 IMF• EF12 = 1 IMF• EF13 = 1 IMF• EF14 = 1 IMF• EF15 = 1 IMF• EF16 = 1 IMF• EF17 = 1 IMF• EF18 = 1 IMF• EF19 = 1 IMF• EF20 = 1 IMF• EF21 = 1 IMF• EF22 = 1 IMF• EF23 = 1 IMF• EF24 = 1 IMF• EF25 = 1 IMF• EF26 = 1 IMF• EF27 = 1 IMF• EF28 = 1 IMF• EF29 = 1 IMF• EF30 = 1 IMF• EF31 = 1 IMF• EF32 = 1 IMF• EF33 = 1 IMF• EF34 = 1 IMF• EF35= 1 IMF• EF36 = 1 IMF• EF37 = 1 IMF• EF38 = 1 Priority High 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Low 38 (External interrupt 0) Reserved External Internal INT1 (External interrupt 1) INTTBT (TBT interrupt) Reserved Internal Internal Internal Internal Internal Internal INTEMG1 (ch1 Error detect interrupt) INTEMG2 (ch2 Error detect interrupt) INTCLM1 (ch1 Overload protection interrupt) INTCLM2 (ch2 Overload protection interrupt) INTTMR31 (ch1 Timer 3 interrupt) INTTMR32 (ch2 Timer 3 interrupt) Reserved External Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal Internal External External External Internal Internal Internal Internal Internal Internal Internal INT5 (External interrupt 5) INTPDC1 (ch1 Posision detect interrupt) INTPDC2 (ch2 Posision detect interrupt) INTPWM1 (ch1 Waveform generater interrupt) INTPWM2 (ch2 Waveform generater interrupt) INTEDT1 (ch1 Erectric angle Timer interrupt) INTEDT2 (ch2 Erectric angle Timer interrupt) INTTMR11 (ch1 Timer1 interrupt) INTTMR12 (ch2 Timer1 interrupt) INTTMR21 (ch1 Timer2 interrupt) INTTMR22 (ch2 Timer2 interrupt) INTTC1 (TC1 interrupt) INTCTC1 (CTC interrupt) INTTC6 (TC6 8bit/16bit interrupt) INT2 (External interrupt 2) INT3 (External interrupt 3) INT4 (External interrupt 4) INTRXD (UART receive interrupt) INTTXD (UART transmit interrupt) INTSIO (SIO interrupt) INTTC3 (TC3 interrupt) INTTC4 (TC4 interrupt) INTTC5 (TC5 interrupt) INTADC (A/D converter interrupt) Page 25 3. Interrupt Control Circuit 3.1 Interrupt latches (IL38 to IL2) TMP88PS43FG Note 1: To use the watchdog timer interrupt (INTWDT), clear WDTCR1 to "0" (It is set for the "Reset request" after reset is released). It is described in the section "Watchdog Timer" for details. 3.1 Interrupt latches (IL38 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to “0” during reset. The interrupt latches are located on address 003CH, 003DH, 002EH, 002FH and 002BH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 should be set to "1". If the read-modifywrite instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. But interrupt latches are not set to “1” by an instruction. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LD LD LD LD LD EI (ILL), 1110100000111111B (ILH), 1110100000111111B (ILE), 1110100000111111B (ILD), 1110100000111111B (ILC), 1110100000111111B ; IMF ← 0 ; IL2 to IL7 ← 0 ; IL8 to IL15 ← 0 ; IL16 to IL23 ← 0 ; IL24 to IL31 ← 0 ; IL32 toIL38 ← 0 ; IMF ← 1 Example 2 :Reads interrupt latches LD LD LD WA, (ILL) BC, (ILE) D, (ILC) ; W ← (ILH), A ← (ILL) ; B ← (ILD), C ← (ILE) ; D ← (ILC) Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump Page 26 TMP88PS43FG 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the pseudo nonmaskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Pseudo non-maskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH, 003BH, 002CH, 002DH and 002AH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled temporarily. IMF flag is set to "1" by the maskable interrupt return instruction [RETI] after executing the interrupt service program routine, and MCU can accept the interrupt again. The latest interrupt request is generated already, it is available immediately after the [RETI] instruction is executed. On the pseudo non-maskable interrupt, the non-maskable return instruction [RETN] is adopted. In this case, IMF flag is set to "1" only when it performs the pseudo non-maskable interrupt service routine on the interrupt acceptable status (IMF=1). However, IMF is set to "0" in the pseudo non-maskable interrupt service routine, it maintains its status (IMF="0"). The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to “0”. 3.2.2 Individual interrupt enable flags (EF38 to EF3) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” disables acceptance. During reset, all the individual interrupt enable flags (EF38 to EF3) are initialized to “0” and all maskable interrupts are not accepted until they are set to “1”. Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example :Enables interrupts individually and sets IMF DI SET CLR CLR CLR : EI ; IMF ← 1 (EIRL), .5 (EIRL), .6 (EIRH), .4 (EIRD), .0 ; IMF ← 0 ; EF5 ← 1 ; EF6 ← 0 ; EF12 ← 0 ; EF24 ← 0 Page 27 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP88PS43FG Interrupt Latches (Initial value: 0*000000 *00*0000) ILH,ILL (003DH, 003CH) 15 IL15 14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 6 IL6 5 IL5 4 3 IL3 2 IL2 1 INF 0 ILH (003DH) ILL (003CH) (Initial value: 00000000 00000000) ILD,ILE (002FH, 002EH) 15 IL31 14 IL30 13 IL29 12 IL28 11 IL27 10 IL26 9 IL25 8 IL24 7 IL23 6 IL22 5 IL21 4 IL20 3 IL19 2 IL18 1 IL17 0 IL16 ILD (002FH) ILE (002EH) (Initial value: *0000000) ILC (002BH) 7 6 IL38 5 IL37 4 IL36 3 IL35 2 IL34 1 IL33 0 IL32 ILE (002BH) Read IL38 to IL2 Interrupt latches 0: No interrupt request 1: Interrupt request 00: Out of interrupt service 01: On interrupt service of level 1 01: On interrupt service of more than level 2 01: On interrupt service of more than level 3 Write 0: Clears the interrupt request (Note1) 1: (Unable to set interrupt latch) 00: Reserved 01: Clear the nesting counter 10: Count-down 1 step for the nesting counter (Note2) 11: Reserved R/W INF Interrupt Nesting Flag Note 1: IL2 cannot alone be cleard. Note 2: Unable to detect the under-flow of counter. Note 3: The nesting counter is set "0" initially, it performs count-up by the interrupt acceptance and count-down by executing the interrupt return instruction. Note 4: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 5: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 0*000000 *00*0**0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 6 EF6 5 EF5 4 3 EF3 2 1 0 IMF EIRH (003BH) EIRL (003AH) (Initial value: 00000000 00000000) EIRD,EIRE (002DH, 002CH) 15 EF31 14 EF30 13 EF29 12 EF28 11 EF27 10 EF26 9 EF25 8 EF24 7 EF23 6 EF22 5 EF21 4 EF20 3 EF19 2 EF18 1 EF17 0 EF16 EIRD (002DH) EIRE (002CH) (Initial value: *0000000) EIRE (002AH) 7 6 EF38 5 EF37 4 EF36 3 EF35 2 EF34 1 EF33 0 EF32 EIRE (002AH) Page 28 TMP88PS43FG EF38 to EF3 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: Do not set IMF and the interrupt enable flag (EF38 to EF3) to “1” at the same time. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 29 3. Interrupt Control Circuit 3.3 Interrupt Sequence TMP88PS43FG 3.3 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to “0” by resetting or an instruction. Interrupt acceptance sequence requires 12 machine cycles (2.4 µs @20 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”. c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSWH, PSWL, PCE, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 5. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. Read the RBS control code from the vector table, add its MSB(4bit) to the register bank selecter (RBS). f. Count up the interrupt nesting counter. g. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute instruction PC Execute instruction a-1 a a+1 Execute instruction Interrupt acceptance Execute RETI instruction a b b+1 b+2 b+3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-4 n-5 n-4 n-3 n-2 n-1 n Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 62/fc [s] at maximum (If the interrupt latch is set at the first machine cycle on 15 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Page 30 TMP88PS43FG Vector table address Entry address FFFE4H FFFE5H FFFE6H FFFE7H 45H 23H 01H 06H RBS control code Vector 12345H 12346H 12347H 12348H Interrupt service program Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. But don’t use the read-modify-write instruction for EIRL(0003AH) on the pseudo non-maskable interrupt service task. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following four methods are used to save/restore the general-purpose registers. 3.3.2.1 Using Automatic register bank switcing By switching to non-use register bank, it can restore the general-purpose register at hige speed. Usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. To make up its data memory efficiency, the common bank is assigned for non-multiple intrrupt factor. It can return back to main-flow by executing the interrupt return instructions ([RETI]/[RETN]) from the current interrupt register bank automatically. Thus, no need to restore the RBS by a program. Example :Register bank switching PINTxx: (interrupt processing) RETI : VINTxx: DP DB PINTxx 1 ; PINTxx vector address setting ; RBS TC1DRB Note 4: Set TC1DRB after changing the mode of TC1M to the PPG mode. Page 79 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PS43FG Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs (fc = 20 MHz, CGCR = “0”) Setting port LD LDW LDW LD (TC1CR), 10001011B (TC1DRA), 04E2H (TC1DRB), 00FAH (TC1CR), 10010111B ; Sets the PPG mode, selects the source clock ; Sets the cycle (1 ms ÷ 24/fc µs = 04E2H) ; Sets the low-level pulse width (200 µs ÷ 24/fc = 00FAH) ; Starts the timer I/O port output latch shared with PPG output Port output enable PPG pin Data output D R Q Function output TC1CR Write to TC1CR Internal reset Match to TC1DRB Match to TC1DRA Set Clear Toggle Q Timer F/F1 INTTC1 interrupt request TC1CR clear Figure 8-7 PPG Output Page 80 TMP88PS43FG Timer start Internal clock Counter 0 1 2 n n+1 m0 1 2 n n+1 m0 1 2 TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Note: m > n (a) Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter 0 1 n n+1 m 0 TC1DRB n TC1DRA m PPG pin output INTTC1 interrupt request [Application] One-shot pulse output (b) One-shot pulse generation (TC1S = 10) Note: m > n Figure 8-8 PPG Mode Timing Chart Page 81 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP88PS43FG Page 82 Stop Start control Start Trigger clear CTC1S CTC1SM CTC1SE CTC1CY CTC1E 9.1 Configuration Rising edge CTC pin S A Y 9. 16-Bit Timer (CTC) B 11 12 Edge detection Falling edge fc/27 or fc/2 8 fc/25 or fc/26 fc/2 or fc/2 fc/23 or fc/24 fc/22 or fc/23 2 fc/2 or fc/2 fc or fc/2 Y Last coincidence 2 CTC1REG 3 3 Comparator Select write register CTC1DRA CTC1DRB CTC1DRC CTC1M Select read register 2 Read/Write control and clear interrupt CTC1M Interrupt 16-bit up counter H A B C D E F G Figure 9-1 CTC Block Diagram Page 83 CTC1FF0 S INTCTC1 interrupt CTC1CK CTC1S CTC1SM CTC1E Toggle Q Set Clear PPG2 pin CTC1SE CTC1CY CTC1M PPGFF0 CTC1RES CTC1CR1 CTC1REG CTC1CK CTC1FF0 EXTREGDIS 2 3 TMP88PS43FG CTC1CR2 PPGFF0 9. 16-Bit Timer (CTC) 9.2 Control TMP88PS43FG 9.2 Control Compare timer/counter 1 is controlled using Compare timer/counter 1 Control Registers (CTC1CR1 and CTC1CR2), as well as three 16-bit Timer Registers (CTC1DRA, CTC1DRB, and CTC1DRC). Compare Timer Registers (CTC1DRH: 00017h, CTC1DRL: 00016h) CTC1DRA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTC1DRAH 15 14 13 12 11 10 9 8 7 6 5 CTC1DRAL 4 3 2 1 0 Write only (Initial value: ******** ********) Write only Initial value: ******** ******** Write only Initial value: ******** ******** CTC1DRB CTC1DRBH 15 14 13 12 11 10 9 8 7 6 5 CTC1DRBL 4 3 2 1 0 CTC1DRC CTC1DRCH CTC1DRCL Note: CTC1DRA, CTC1DRB, and CTC1DRC are write-only registers and must not be used with any of the read-modify-write instructions such as SET, CLR, etc. Compare Timer/Counter 1 Control Registers (CTC1CR2: 00015h, CTC1CR1: 00014h) CTC1CR1 lower address CTC1CR2 upper address 7 CTC1RES 7 * 6 PPGFF0 6 EXTRGDIS 5 CTC1M 5 CTC1REG 4 CTC1CY 4 3 CTC1SE 3 2 CTC1E 2 CTC1CK 1 CTC1SM 1 0 CTC1S 0 CTC1FF0 R/W (Initial value: 00000000) R/W (Initial value: *0000000) Note 1: *: Don’t care Note 2: The CTC1CR1 is 0 when read. Note 3: Use the LDW instruction for write to the CTC1DR H/L Registers. Set a value equal to or greater than 2. Note 4: Write to CTC1DR H/L A, B, and C Registers as many as set with the CTC1CR2 Register CTC1REG bit. Note 5: Data are written to CTC1DR H/L Registers in order of CTC1DRA, CTC1DRB, and CTC1DRC. Page 84 TMP88PS43FG Setting-up the CTC1CR1 Register Timer CTC1S Control start 0: Stop and clear counter 1: Command start 0: Software start 1: External trigger start 0: Enable one edge 1: Enable both edges 0: Rising edge 1: Falling edge 0: Successive 1: One shot ο ο CTC1SM Select start ο ο ο ο ο ο ο ο Event ο ο ο × ο × ο ο ο × PPG ο ο ο ο ο ο ο ο ο ο R/W CTC1E Select external trigger edge Select external trigger start edge Select cycle CTC1SE CTC1CY CTC1M PPGFF0 CTC1RES Set operation mode Select PPG output Reset all 0: Timer/Event counter modes 1: PPG (programmable pulse generator) output mode 0: Forward output immediately after start 1: Reverse output immediately after start 0: Normal operation 1: CTC1 reset Setting-up the CTC1CR2 Register CTC1FF0 Control timer output F/F0 0: Clear 1: Set NORMAL and IDLE Modes DV1CK = 0 000 001 CTC1CK Select timer/counter clock source Unit: Hz 010 011 100 101 110 111 Set registers used by timer/ counter fc/211 fc/27 fc/25 fc/23 fc/22 fc/2 DV1CK = 1 fc/212 fc/28 fc/26 fc/24 fc/23 fc/22 R/W External clock input (CTC1 pin input) 1REG 2REG 3REG CTC1REG 00: CTC1DRA 01: CTC1DRA + CTC1DRB 10: CTC1DRA + CTC1DRB + CTC1DRC 11: Reserved 0: Enable external trigger input 1: Disable external trigger input EXTRGDIS External trigger input Note 1: fc: Clock [Hz] Note 2: Make sure the timer/counter is idle (CTC1CR1 = 00) before setting operation mode, edge, start, source clock, external trigger timer mode control, and PPG output control. Note 3: The CTC1DRB and CTC1DRC Registers cannot be accessed for write unless they are set for PPG output mode and specified with CTC1CR2. Note 4: CTC1CR1 is effective only when using an external clock as trigger (CTC1CR1). Note 5: Data must be written to as many data registers as set with CTC1CR2. Note 6: To write data to CTC1DRA/B/C, use the LDW instruction, or use the LD instruction writing in order of L, H. Note 7: Data register values must be written to the respective registers before starting. To modify the values after starting, write the new data within an interval from an INTCTC1 interrupt to the next INTCTC1. Note 8: Specifying CTC1CR1 = 1 causes all conditions to be reset. Even when the CTC circuit is operating, they are reset, and the PPG output becomes “0”. However, only the INTCTC1 signal is not reset if the signal is being generated. Note 9: For event counter mode (when CTC pin input is selected in timer mode), the active edge of the external trigger to count can be selected with CTC1CR1. Note 10:Disabling external trigger input with CTC1CR2 creates the 0 input state. Note 11:To stop the counter by software at trigger start, set CTC1CR2 = 00. Page 85 9. 16-Bit Timer (CTC) 9.2 Control TMP88PS43FG Note 12:The number of registers set and the values set in the timer registers must meet the conditions shown below. Number of Registers 1 Register CTC1REG 2 Register 3 Register CTC1DRA ≥ 2 Timer Register Value Conditions CTC1DRB > CTC1DRA + 1, and CTC1DRA ≥ 2 CTC1DRC > CTC1DRB + 1, CTC1DRB > CTC1DRA + 1, and CTC1DRA ≥ 2 Page 86 TMP88PS43FG 9.3 Function Compare timer/counter 1 has three modes: timer, event counter, and programmable pulse generator output modes. 9.3.1 Timer mode with software start In this mode, the timer/counter (16-bit counter) counts up synchronously with the internal clock. When the counter value and the set value of Compare Timer Register 1 (CTC1DRA) match, an INTCTC1 interrupt is generated and the counter is cleared. After the counter is cleared, it restarts and continues counting up. Table 9-1 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz) NORMAL and IDLE Modes CTC1CK Resolution [µs] 000 001 010 011 100 101 110 102.4 6.4 1.6 0.4 0.2 0.1 - DV1CK = 0 Maximum Setting Time [s] 6.71 0.419 0.105 26.21 m 13.11 m 6.55 m Resolution [µs] 204.8 12.8 3.2 0.8 0.4 0.2 - DV1CK = 1 Maximum Setting Time [s] 13.42 0.839 0.210 52.43 m 26.21 m 13.11 m - Internal clock Counter 0 1 2 3 n-1 n 1 2 3 4 5 6 7 8 9 Timer Register A n INTCTC1 interrupt Successive Figure 9-2 Timer Mode Timing Chart Note:If the CTC input port (P47) is set for input mode, the timer/counter is reset by an input edge on port. When using the timer/counter as an ordinary timer, set CTC1CR2 to 1 or set P47 for output mode. Page 87 9. 16-Bit Timer (CTC) 9.2 Control TMP88PS43FG 9.3.2 Timer mode with external trigger start In this timer mode, the timer/counter starts counting as triggered by input on CTC pin (rising or falling edge selected with CTC1CR1). The source clock is an internal clock. For successive cycles, when the counter value and the set value of the CTC1DRA Register match, an INTCTC1 interrupt is generated and the counter is cleared and then restarted. The counter is stopped by a trigger input on CTC pin and restarted by the next trigger input. For a one-shot cycle, when the counter value and the set value of the CTC1DRA Register match, an INTCTC1 interrupt is generated and the counter is cleared and stopped. The counter restarts counting up by input on CTC pin. When CTC1CR1 = 1, the counter is cleared and stops counting at an edge on CTC pin input opposite the active edge that triggers the counter to start counting. In this mode, an interrupt can be generated by entering a pulse which has a certain width. When CTC1CR1 = 0, opposite edges on CTC input are ignored. (I) When rising edge start is selected, with counting enabled on one edge ( CTC1SE = 0, CTC1E = 0 ) Count start Stop Trigger Count start Trigger CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt Successive Count start Count start Trigger 0 1 2 n-1 n 1 Clear 2 3 4 1 2 n CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt One Shot 0 1 2 n-1 n Stop 0 1 2 3 4 5 6 n Figure 9-3 External Trigger Mode Timing Chart Page 88 TMP88PS43FG (II) When rising start edge is selected, with counting enabled on both edges ( CTC1SE = 0, CTC1E = 1 ) Count start Count stop Trigger Count start Trigger CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt Successive Count start Count start Trigger Count clear Trigger Note) m < n 0 1 2 m 0 1 n-1 n 1 23 n CTC pin input Trigger Internal clock Counter Timer Register A INTCTC1 interrupt One Shot 0 1 2 n 0 1 2 3 4 50 1 2 3 n Figure 9-4 External Trigger Mode Timing Chart 9.3.3 Event counter mode In this mode, the timer/counter counts up at the active edge on CTC pin input (rising or falling edge selected with the CTC1CR1 which is provided for selecting external trigger edge). When the counter value and the set value of the CTC1DRA Register match, an INTCTC1 interrupt is generated and the counter is cleared. After the counter is cleared, it restarts and continues counting up at each edge on CTC pin input. The maximum applied frequency is shown in the table below. Because coincidence detection is made at an edge opposite the selected edge, the external clock signal on CTC pin must always be entered. When rising start edge is selected Command start CTC pin input Counter 0 1 2 n-1 n 0 1 Timer Register INTCTC1 interrupt n Figure 9-5 Event Counter Mode Timing Chart Page 89 9. 16-Bit Timer (CTC) 9.2 Control TMP88PS43FG Table 9-2 External Clock Source for Compare Timer/Counter 1 NORMAL and IDLE Modes Maximum applied frequency [Hz] Minimum pulse width Up to fc/22 22/fc and over 9.3.4 Programmable Pulse Generate (PPG) output mode The timer/counter starts counting as a command or edge on CTC pin input (rising/falling edge and one/both edges respectively selected with the CTC1CR1 and CTC1CR1). The source clock is an internal clock. When matched with the CTC1DR A/B/C Registers, the timer output F/F corresponding to each mode is inverted. When matched with the CTC1DR A/B/C Registers next time, the timer output F/F is inverted again. An INTCTC1 interrupt request is generated when the counter value matches the maximum register value set by CTC1CR2. The timer output F/F is cleared to 0 when reset. Because CTC1CR2 can be used to set the initial value for the timer output F/F, an active-high or active-low pulse whichever is desired can be output. The CTC1DRB and CTC1DRC Registers cannot be accessed for write unless they are set for PPG output mode and the registers used are selected with CTC1CR2. The number of registers set can be altered during operation. In this case, however, be sure to set the number of registers used and write values to the data registers before the next CTC1INIT1 is output after the first CTC1INIT1 output. Even when only altering the data register values while leaving the number of registers unchanged, be sure to do this within the same period of time. Table 9-3 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz) NORMAL and IDLE Modes CTC1CK Resolution [µs] 000 001 010 011 100 101 110 102.4 6.4 1.6 0.4 0.2 0.1 - DV1CK = 0 Maximum Setting Time [s] 6.71 0.419 0.105 26.21 m 13.11 m 6.55 m Resolution [µs] 204.8 12.8 3.2 0.8 0.4 0.2 - DV1CK = 1 Maximum Setting Time [s] 13.42 0.839 0.210 52.43 m 26.21 m 13.11 m - (I) One register used When command start, interrupt output, and counter clear are set in Timer Register A Command start CTC pin input Counter 0 1 n 1 n 1 n 1 n 1 2 3 Timer Register A n PPG2 pin output INTCTC1 interrupt Successive Figure 9-6 PPG Output Mode Timing Chart Page 90 TMP88PS43FG (II) Two registers used (CTC1REG = 01) When external trigger rising edge start, one edge enable, interrupt output, and counter clear are set in Timer Register B. Command start Stop CTC pin input Internal clock Counter 0 1 m m+1 n 1 m m+1 n 1 2 0 Timer Register A m Timer Register B n PPG2 pin output INTCTC1 interrupt Successive Command start Initial value Start CTC pin input Internal clock Counter 0 1 m m+1 n 0 1 Timer Register A m Timer Register B n PPG2 pin output INTCTC1 interrupt One shot Figure 9-7 PPG Output Two Register Mode Timing Chart Page 91 9. 16-Bit Timer (CTC) 9.2 Control TMP88PS43FG When external trigger rising edge start, both edges enable, interrupt output, and counter clear are set in Timer Register B. Command start Stop Start CTC pin input Internal clock Counter 0 1 m m+1 n 1 m 0 1 Timer Register A m Timer Register B n Initial value PPG2 pin output INTCTC1 interrupt Successive Start Start Start Start CTC pin input Internal clock Counter 0 1 m m+1 n 0 1 201 m m+1 01 m m+1 n0 Timer Register A m Timer Register B n PPG2 pin output INTCTC1 interrupt One shot Figure 9-8 PPG Output External Trigger Mode Timing Chart Page 92 TMP88PS43FG (III) Three registers used (CTC1REG = 10) When command start, interrupt output, and counter clear are set in Timer Register C. Command start CTC pin input Counter 0 1 m m+1 n n+1 s 1 m m+1 n Timer Register A m Timer Register B n Timer Register C s PPG2 pin output INTCTC1 interrupt Successive Command start Command restart CTC pin input Counter 0 1 m m+1 n n+1 s 0 1 m m+1 Timer Register A m Timer Register B n Timer Register C s PPG2 pin output INTCTC1 interrupt One shot Note: In the single-shot mode, the PPG pin output is not toggled at the last register match; it stays at the value specified with CTC1CR2. Figure 9-9 PPG Output Three Register Mode Timing Chart Page 93 9. 16-Bit Timer (CTC) 9.2 Control TMP88PS43FG Detail operation at start that varies depending on how CTC1CR2 and CTC1CR1 are set during PPG output. Table 9-4 Varying PPG Output Timing Depending on Settings CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 0 PPGFF0 = 0 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 1 PPGFF0 = 0 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 0 PPGFF0 = 1 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output CTC1FF0 setting (write to CTC1CR1 Register) Command start or trigger start Internal clock CTC1FF0 = 1 PPGFF0 = 1 Counter 0 1 2 3 n n+1 n+2 n+3 PPG output By changing the port-shared output for PPG output before the counter starts counting after setting CTC1CR2, it is possible to determine the initial value of PPG output. Page 94 TMP88PS43FG 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration Falling INTTC3 interrupt Clear Edge detector Rising TC3 pin TC3S Port (Note) fc/213, fc/2 14 fc/212, fc/2 13 fc/211 , fc/2 12 fc/210, fc/2 11 fc/2 9 , fc/210 fc/2 8 , fc/2 9 fc/2 7 , fc/2 8 H AY B C D E F G S 3 Source clock 8-bit up-counter Overflow detect TC3S CMP Match detect A B S Y TC3DRB Capture TC3DRA Capture 8-bit timer register TC3CK TC3M TC3CR TC3 contorol register Note: Function input may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 10-1 TimerCounter 3 (TC3) ACAP TC3S Page 95 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP88PS43FG 10.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB). Timer Register and Control Register TC3DRA (001CH) TC3DRB (001DH) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) Read only (Initial value: 1111 1111) TC3CR (001EH) 7 6 ACAP 5 4 TC3S 3 2 TC3CK 1 0 TC3M (Initial value: *0*0 0000) ACAP TC3S Auto capture control TC3 start control 0: – 1: Auto capture 0: Stop and counter clear 1: Start NORMAL, IDLE mode DV1CK=0 000 001 fc/2 13 R/W R/W DV1CK=1 fc/214 fc/213 fc/212 fc/211 fc/210 fc/29 fc/28 R/W fc/212 fc/211 fc/210 fc/29 fc/28 fc/27 External clock (TC3pin input) TC3CK TC3 source clock select [Hz] 010 011 100 101 110 111 TC3M TC3 operating mode select 0: Timer/event counter mode 1: Capture mode R/W Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: Set the operating mode and source clock when TimerCounter stops (TC3CR = 0). Note 3: To set the timer registers, the following relationship must be satisfied. TC3DRA > 1 (Timer/event counter mode) Note 4: Auto-capture (TC3CR) can be used only in the timer and event counter modes. Note 5: When the read instruction is executed to TC3CR, the bit 5 and 7 are read as a don’t care. Note 6: Do not program TC3DRA when the timer is running (TC3CR = 1). Note 7: When the STOP mode is entered, the start control (TC3CR) is cleared to 0 automatically, and the timer stops. After the STOP mode is exited, TC3CR must be set again to use the timer counter. Page 96 TMP88PS43FG 10.3 Function TimerCounter 3 has three types of operating modes: timer, event counter and capture modes. 10.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 3A (TC3DRA) value is detected, an INTTC3 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Setting TC3CR to 1 captures the upcounter value into the timer register 3B (TC3DRB) with the auto-capture function. The count value during timer operation can be checked by executing the read instruction to TC3DRB. Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Clock TC3DRA Up-counter Match detect C8 C6 C7 C8 00 01 TC3DRB C6 C7 C8 01 Note: In the case that TC3DRB is C8H Figure 10-2 Auto-Capture Function Table 10-1 Source Clock for TimerCounter 3 (Example: fc = 20 MHz) TC3CK DV1CK = 0 Resolution [µs] 000 001 010 011 100 101 110 409.6 204.8 102.4 51.2 25.6 12.8 6.4 Maximum Time Setting [ms] 104.45 52.22 26.11 13.06 6.53 3.06 1.63 Resolution [µs] 819.2 409.6 204.8 102.4 51.2 25.6 12.8 NORMAL, IDLE mode DV1CK = 1 Maximum Time Setting [ms] 208.90 104.45 52.22 26.11 13.06 6.53 3.06 Page 97 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP88PS43FG Timer start Source clock Counter 0 1 2 3 4 n0 1 2 3 4 5 6 7 TC3DRA INTTC3 interrupt ? n Match detect Counter clear (a) Timer mode Source clock Counter m m+1 m+2 n n+1 Capture Capture m+1 m+2 n TC3DRB ? m n+1 TC3CR (b) Auto capture Figure 10-3 Timer Mode Timing Chart Page 98 TMP88PS43FG 10.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC3 pin. When a match between the up-counter and TC3DRA value is detected, an INTTC3 interrupt is generated and up-counter is cleared. After being cleared, the up-counter restarts counting at each rising edge of the input pulse to the TC3 pin. Since a match is detected at the falling edge of the input pulse to TC3 pin, an INTTC3 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC3DRA. The maximum applied frequencies are shown in Table 10-2. The pulse width larger than one machine cycle is required for high-going and low-going pulses. Setting TC3CR to 1 captures the up-counter value into TC3DRB with the auto-capture function. The count value during a timer operation can be checked by the read instruction to TC3DRB. Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB. (Figure 10-2) Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s LD LD LD (TC3CR), 00001110B (TC3DRA), 19H (TC3CR), 00011110B : Sets the clock mode : 0.5 s ÷ 1/50 = 25 = 19H : Starts TC3. Table 10-2 Maximum Frequencies Applied to TC3 Minimum Pulse Width NORMAL, IDLE mode High-going Low-going 22/fc 22/fc Timer start TC3 pin input Counter 0 1 2 3 n 0 1 2 3 Match detect Counter clear TC3DRA n INTTC3 interrupt Figure 10-4 Event Counter Mode Timing Chart Page 99 10. 8-Bit TimerCounter 3 (TC3) 10.1 Configuration TMP88PS43FG 10.3.3 Capture Mode In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are measured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60 Hz. When the falling edge of the TC3 input is detected after the timer starts, the up-counter value is captured into TC3DRB. Hereafter, whenever the rising edge is detected, the up-counter value is captured into TC3DRA and the INTTC3 interrupt request is generated. The up-counter is cleared at this time. Generally, read TC3DRB and TC3DRA during INTTC3 interrupt processing. After the up-counter is cleared, counting is continued and the next up-counter value is captured into TC3DRB. When the rising edge is detected immediately after the timer starts, the up-counter value is captured into TC3DRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When the read instruction is executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset) is read. The minimum input pulse width must be larger than one cycle width of the source clock programmed in TC3CR. The INTTC3 interrupt request is generated if the up-counter overflow (FFH) occurs during capture operation before the edge is detected. TC3DRA is set to FFH and the up-counter is cleared. Counting is continued by the up-counter, but capture operation and overflow detection are stopped until TC3DRA is read. Generally, read TC3DRB first because capture operation and overflow detection resume by reading TC3DRA. Timer start TC3CR Source clock Counter TC3 pin input Internal waveform 0 1 i-1 i i+1 k-1 k 0 1 m-1 m m+1 n-1 n 0 1 2 3 FE FF 0 1 2 3 Capture TC3DRA TC3DRB INTTC3 interrupt request Read of TC3DRA Capture i k Capture m Capture n Capture FE FF (Overflow) Overflow Figure 10-5 Capture Mode Timing Chart Page 100 TMP88PS43FG 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TC4S fc/211, fc212 fc/27, fc28 fc/25, fc26 fc/23, fc24 fc/22, fc23 fc/2, fc22 fc, fc/2 (Note) A B Source C Clock Clear D EY 8-bit up-counter Y F G H Overflow detect 0 1 S Y TC4 pin S 3 CMP Match detect Timer F/F TC4CK Toggle Port (Note) TC4S TC4M 2 0 Y 1 Clear S PWM4/ PDO4/ pin TC4CR TC4DR PWM output mode TC4S INTTC4 interrupt PDO mode Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port". Figure 11-1 TimerCounter 4 (TC4) Page 101 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP88PS43FG 11.2 TimerCounter Control The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and timer registers 4 (TC4DR). Timer Register and Control Register TC4DR (001BH) 7 6 5 4 3 2 1 0 Read/Write (Initial value: 1111 1111) TC4CR (001AH) 7 6 5 TC4S 4 3 TC4CK 2 1 TC4M 0 Read/Write (Initial value: **00 0000) TC4S TC4 start control 0: Stop and counter clear 1: Start NORMAL, IDLE mode DV1CK = 0 000 001 fc/2 11 R/W DV1CK = 1 fc/212 fc/28 fc/26 fc/24 fc/23 fc/22 (fc/2)Note8 R/W fc/27 fc/25 fc/23 fc/22 fc/2 (fc)Note8 TC4CK TC4 source clock select [Hz] 010 011 100 101 110 111 External clock (TC4 pin input) TC4M TC4 operating mode select 00: Timer/event counter mode 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode R/W Note 1: fc: High-frequency clock [Hz], *: Don’t care Note 2: To set the timer registers, the following relationship must be satisfied. 1 ≤ TC4DR ≤ 255 Note 3: To start timer operation (TC4CR = 0 → 1) or disable timer operation (TC4CR = 1→ 0), do not change the TC4CR setting. During timer operation (TC4CR = 1→ 1), do not change it, either. If the setting is programmed during timer operation, counting is not performed correctly. Note 4: The event counter and PWM output modes are used only in the NOMAL and IDLE modes. Note 5: When the STOP mode is entered, the start control (TC4S) is cleared to “0” automatically. Note 6: The bit 6 and 7 of TC4CR are read as a don’t care when these bits are read. Note 7: In the timer, event counter and PDO modes, do not change the TC4DR setting when the timer is running. Note 8: When the high-frequency clock fc exceeds 10 MHz, do not select the source clock of TC4CR< TC4CK> = 110. Note 9: For available source clocks depending on the operation mode, refer to the following table. Timer Mode 000 001 010 TC4CK 011 100 101 110 111 O O O O − − − − Event Counter Mode − − − − − − − O PDO Mode O O O − − − − − PWM Mode − − − O O O O × Note: O : Available source clock Page 102 TMP88PS43FG 11.3 Function TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and pulse width modulation (PWM) output modes. 11.3.1 Timer Mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Table 11-1 Internal Source Clock for TimerCounter 4 (Example: fc = 20 MHz) TC4CK DV1CK = 0 Resolution [µs] 000 001 010 011 102.4 6.4 1.6 0.4 Maximum Time Setting [ms] 26.11 1.63 0.41 0.10 Resolution [µs] 204.8 12.8 3.2 0.8 NORMAL, IDLE Mode DV1CK = 1 Maximum Time Setting [ms] 52.22 3.28 0.82 0.20 11.3.2 Event Counter Mode In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin. When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4 pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR. The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two machine cycles is required for high- and low-going pulses. Note:The event counter mode can used in the NORMAL and IDLE modes only. Table 11-2 External Source Clock for TimerCounter 4 Minimum Pulse Width NORMAL, IDLE mode High-going Low-going 23/fc 23/fc 11.3.3 Programmable Divider Output (PDO) Mode The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is cleared at this time and then counting is continued. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4 interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued. When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is low, the duty pulse may be shorter than the programmed value. Page 103 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP88PS43FG Example :Generating 1024 Hz pulse (fc = 20.0 Mhz and CGCR = 0) LD SET LD LD (TC4CR), 00000110B (P2DR), 2 (TC4DR), 4CH (TC4CR), 00100110B : Sets the PDO mode. (TC4M = 10, TC4CK = 001) : Sets the P22 output latch to 1. : 1/1024 ÷ 27/fc ÷ 2 (half cycle period) = 4CH : Start TC4 Internal clock Counter TC4DR Timer F/F 0 1 2 n0 1 2 n0 1 2 n0 1 2 n0 1 n Match detect PDO4 pin INTTC4 interrupt request Figure 11-2 PDO Mode Timing Chart 11.3.4 Pulse Width Modulation (PWM) Output Mode The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock. When a match between the up-counter and the TC4DR value is detected, the logic level output from the PWM4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM4 pin becomes high. The INTTC4 interrupt request is generated at this time. When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is low, one PMW cycle may be shorter than the programmed value. TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically. For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR to 1. Note 1: The PWM output mode can be used only in the NORMAL and IDEL modes. Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated (typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is issued. Page 104 TMP88PS43FG TC4CR Internal clock Counter TC4DR 0 1 n n+1 FF 0 1 n n+1 FF 0 1 m Rewrite ? n m Rewrite p Rewrite Data shift m Data shift Shift register Timer F/F ? n Data shift Match detect Match detect Match detect PWM4 pin INTTC4 interrupt request n n m PWM cycle Figure 11-3 PWM output Mode Timing Chart (TC4) Table 11-3 PWM Mode (Example: fc = 20 MHz) TC4CK DV1CK = 0 Resolution [ns] 000 001 010 011 100 101 110 – – – 400 200 100 – Cycle [µs] – – – 102.4 51.2 25.6 – NORMAL, IDLE Mode DV1CK = 1 Resolution [ns] – – – 800 400 200 – Cycle [µs] – – – 204.8 102.4 51.2 – Page 105 11. 8-Bit TimerCounter 4 (TC4) 11.1 Configuration TMP88PS43FG Page 106 TMP88PS43FG 12. 8-Bit TimerCounter 5,6(TC5, 6) 12.1 Configuration PWM mode Overflow fc/211, fc/212 INTTC6 interrupt request fc/2 , fc/2 5 6 fc/2 , fc/2 fc/23, fc/24 7 8 TC6 pin TC6M TC6S TFF6 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC6S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F6 PDO6/PWM6/ PPG6 pin TC6CK TC6CR TTREG6 PWREG6 PWM, PPG mode DecodeEN TFF6 PDO, PWM, PPG mode 16-bit mode TC5S PWM mode fc/211, fc/212 7 8 fc/2 , fc/2 fc/25, fc/26 3 4 fc/2 , fc/2 TC5 pin TC5M TC5S TFF5 A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC5 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F5 PDO5/PWM5/ pin TC5CK TC5CR TTREG5 PWREG5 PWM mode DecodeEN TFF5 PDO, PWM mode 16-bit mode Figure 12-1 8-Bit TimerCouter 5, 6 Page 107 12. 8-Bit TimerCounter 5,6(TC5, 6) 12.1 Configuration TMP88PS43FG 12.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 (0022H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG5 (0024H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG5) setting while the timer is running. Note 2: Do not change the timer register (PWREG5) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 5 Control Register TC5CR (0020H) 7 TFF5 6 5 TC5CK 4 3 TC5S 2 1 TC5M 0 (Initial value: 0000 0000) TFF5 Time F/F5 control 0: 1: Clear Set NORMAL, IDLE mode DV1CK = 0 DV1CK = 1 fc/212 fc/28 fc/26 fc/24 TC5I pin input R/W 000 001 TC5CK Operating clock selection [Hz] 010 011 100 101 110 111 TC5S TC5 start control 0: 1: 000: 001: TC5M TC5M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 - R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC6M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] Note 2: Do not change the TC5M, TC5CK and TFF5 settings while the timer is running. Note 3: To stop the timer operation (TC5S= 1 → 0), do not change the TC5M, TC5CK and TFF5 settings. To start the timer operation (TC5S= 0 → 1), TC5M, TC5CK and TFF5 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC6CR, where TC5M must be fixed to 011. Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC5CK. Set the timer start control and timer F/F control by programming TC6CR and TC6CR, respectively. Note 6: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 12-1. Page 108 TMP88PS43FG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 122. Page 109 12. 8-Bit TimerCounter 5,6(TC5, 6) 12.1 Configuration TMP88PS43FG The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 (0023H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG6 (0025H) R/ W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG6) setting while the timer is running. Note 2: Do not change the timer register (PWREG6) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 6 Control Register TC6CR (0021H) 7 TFF6 6 5 TC6CK 4 3 TC6S 2 1 TC6M 0 (Initial value: 0000 0000) TFF6 Timer F/F6 control 0: 1: Clear Set NORMAL, IDLE mode DV1CK = 0 DV1CK = 1 fc/212 fc/28 fc/25 fc/23 TC6I pin input R/W 000 001 TC6CK Operating clock selection [Hz] 010 011 100 101 110 111 TC6S TC6 start control 0: 1: 000: 001: 010: TC6M TC6M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/23 - R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] Note 2: Do not change the TC6M, TC6CK and TFF6 settings while the timer is running. Note 3: To stop the timer operation (TC6S= 1 → 0), do not change the TC6M, TC6CK and TFF6 settings. To start the timer operation (TC6S= 0 → 1), TC6M, TC6CK and TFF6 can be programmed. Note 4: When TC6M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC6 overflow signal regardless of the TC5CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC6M, where TC5CR must be set to 011. Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR. Set the timer start control and timer F/F control by programming TC6S and TFF6, respectively. Page 110 TMP88PS43FG Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 12-1. Note 8: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 122. Table 12-1 Operating Mode and Selectable Source Clock (NORMAL and IDLE Modes) Operating mode 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter 16-bit PWM 16-bit PPG fc/211 Ο – Ο Ο Ο – Ο Ο fc/27 Ο – Ο Ο Ο – Ο Ο fc/25 Ο – Ο Ο Ο – Ο Ο fc/23 Ο – Ο Ο Ο – Ο Ο TC5 pin input – Ο – – – Ο Ο Ο TC6 pin input – Ο – – – – – – Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note 2: Ο : Available source clock Table 12-2 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter 16-bit PWM 1≤ (TTREGn) ≤255 1≤ (TTREGn) ≤255 2≤ (PWREGn) ≤254 1≤ (TTREG6, 5) ≤65535 2≤ (PWREG6, 5) ≤65534 1≤ (PWREG6, 5) < (TTREG6, 5) ≤65535 16-bit PPG and (PWREG6, 5) + 1 < (TTREG6, 5) Register Value Note: n = 5 to 6 Page 111 12. 8-Bit TimerCounter 5,6(TC5, 6) 12.1 Configuration TMP88PS43FG 12.3 Function The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 12.3.1 8-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses. Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 5, 6 Table 12-3 Source Clock for TimerCounter 5, 6 (Internal Clock) Source Clock NORMAL, IDLE mode DV1CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV1CK = 1 fc/212 [Hz] fc/28 fc/26 fc/24 Resolution DV1CK = 0 fc = 20 MHz 128 µs 8 µs 2 µs 500 ns Repeated Cycle DV1CK = 0 fc = 20 MHz 32.6 ms 2.0 ms 510 µs 127.5 µs Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 64 µs later (TimerCounter6, fc = 20.0 MHz) LD DI SET EI LD LD (TC6CR), 00010000B (TC6CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC6. (EIRC). EF37 : Enables INTTC6 interrupt. (TTREG6), 0AH : Sets the timer register (80 µs÷27/fc = 0AH). TC6CR Internal Source Clock Counter TTREG6 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 12-2 8-Bit Timer Mode Timing Chart (TC6) Page 112 TMP88PS43FG 12.3.2 8-Bit Event Counter Mode (TC5, 6) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL or IDLE mode. Note 1: In the event counter mode, fix TCjCR to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses. Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 5, 6 TC6CR TC6 pin input Counter TTREG6 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 12-3 8-Bit Event Counter Mode Timing Chart (TC6) 12.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR. Upon reset, the timer F/Fj value is initialized to 0. To use the programmable divider output, set the output latch of the I/O port to 1. Example :Generating 1024 Hz pulse using TC6 (fc = 20.0 MHz) Setting port LD LD LD (TTREG6), 3DH (TC6CR), 00010001B (TC6CR), 00011001B : 1/1024÷27/fc÷2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC6. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR after the timer is stopped. Do not change the TCjCR setting upon stopping of the timer. Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR (TCjCR).3: Stops the timer. CLR (TCjCR).7: Sets the PDOj pin to the high level. Note 3: j = 5, 6 Page 113 12.1 Configuration 12. 8-Bit TimerCounter 5,6(TC5, 6) TC6CR TC6CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 12-4 8-Bit PDO Mode Timing Chart (TC6) Match detect Match detect Match detect Page 114 Counter 0 1 2 TTREG6 ? n Match detect Timer F/F6 Set F/F PDO6 pin INTTC6 interrupt request Held at the level when the timer is stopped TMP88PS43FG TMP88PS43FG 12.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR, positive and negative pulses can be generated. Upon reset, the timer F/Fj is cleared to 0. (The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.) Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immediately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output, the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the reading data of PWREGj is previous value until INTTCj is generated. For the pin used for PWM output, the output latch of the I/O port must be set to 1. Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR after the timer is stopped. Do not change the TCjCR upon stopping of the timer. Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped CLR (TCjCR).3: Stops the timer. CLR (TCjCR).7: Sets the PWMj pin to the high level. Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping the timer when fc or fc/2 is selected as the source clock, a pulse is output from the PWMj pin during the warm-up period time after exiting the STOP mode. Note 4: j = 5, 6 Table 12-4 PWM Output Mode Source Clock NORMAL, IDLE mode DV1CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV1CK = 1 fc/212 [Hz] fc/28 fc/26 fc/24 Resolution DV1CK = 0 fc = 20 MHz 102.4 µs 6.4 µs 1.6 µs 0.4 µs DV1CK = 1 fc = 20 MHz 204.8 µs 12.8 µs 3.2 µs 0.8 µs Repeated Cycle DV1CK = 0 fc = 20 MHz 26.21 ms 1.64 ms 410 µs 102 µs DV1CK = 1 fc = 20 MHz 52.43 ms 3.28 ms 819 µs 205 µs Page 115 12.1 Configuration 12. 8-Bit TimerCounter 5,6(TC5, 6) TC6CR TC6CR Internal source clock n Write to PWREG6 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 Write to PWREG6 FF 0 1 p Figure 12-5 8-Bit PWM Mode Timing Chart (TC6) m Shift Shift m Match detect Match detect Page 116 n One cycle period m PWREG6 ? n p Shift p Match detect Shift Shift registar ? n Match detect Timer F/F6 PWM6 pin n p INTTC6 interrupt request TMP88PS43FG TMP88PS43FG 12.3.5 16-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR to 1, an INTTC6 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter continues counting. Program the lower byte and upper byte in this order in the timer register. (Programming only the upper or lower byte should not be attempted.) Note 1: In the timer mode, fix TCjCR to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse. Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 5, 6 Table 12-5 Source Clock for 16-Bit Timer Mode Source Clock NORMAL, IDLE mode DV1CK = 0 fc/211 fc/2 7 Resolution DV1CK = 0 fc = 20 MHz 102.4 µs 6.4 µs 1.6 µs 0.4 µs DV1CK = 1 fc = 20 MHz 204.8 µs 12.8 µs 3.2 µs 0.8 µs Maximum Time Setting DV1CK = 0 fc = 20 MHz 6.7 s 419.4 ms 104.9 µs 26.2 µs DV1CK = 1 fc = 20 MHz 13.4 s 838.8 ms 209.7 ms 52.4 ms DV1CK = 1 fc/212 fc/2 8 fc/25 fc/2 3 fc/26 fc/2 4 Example :Setting the timer mode with source clock fc/27 [Hz], and generating an interrupt 240 ms later (fc = 20.0 MHz) LDW DI SET EI LD (TC5CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRD). EF28 : Enables INTTC6 interrupt. (TTREG5), 927CH : Sets the timer register (300 ms÷27/fc = 927CH). LD LD (TC6CR), 04H (TC6CR), 0CH TC6CR Internal source clock Counter TTREG5 (Lower byte) TTREG6 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 12-6 16-Bit Timer Mode Timing Chart (TC5 and TC6) Page 117 12. 8-Bit TimerCounter 5,6(TC5, 6) 12.1 Configuration TMP88PS43FG 12.3.6 16-Bit Event Counter Mode (TC5 and 6) In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5 and 6 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR to 1, an INTTC6 interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC5 pin. Two machine cycles are required for the low- or high-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL or IDLE mode. Program the lower byte (TTREG5), and upper byte (TTREG6) in this order in the timer register. (Programming only the upper or lower byte should not be attempted.) Note 1: In the event counter mode, fix TCjCR to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses. Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation may not be obtained. Note 3: j = 5, 6 12.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC6 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode. Since the initial value can be set to the timer F/F6 by TC6CR, positive and negative pulses can be generated. Upon reset, the timer F/F6 is cleared to 0. (The logic level output from the PWM6 pin is the opposite to the timer F/F6 logic level.) Since PWREG6 and 5 in the PWM mode are serially connected to the shift register, the values set to PWREG6 and 5 can be changed while the timer is running. The values set to PWREG6 and 5 during a run of the timer are shifted by the INTTCj interrupt request and loaded into PWREG6 and 5. While the timer is stopped, the values are shifted immediately after the programming of PWREG6 and 5. Set the lower byte (PWREG5) and upper byte (PWREG5) in this order to program PWREG6 and 5. (Programming only the lower or upper byte of the register should not be attempted.) If executing the read instruction to PWREG6 and 5 during PWM output, the values set in the shift register is read, but not the values set in PWREG6 and 5. Therefore, after writing to the PWREG6 and 5, reading data of PWREG6 and 5 is previous value until INTTC6 is generated. For the pin used for PWM output, the output latch of the I/O port must be set to 1. Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC6 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR after the timer is stopped. Do not program TC6CR upon stopping of the timer. Example: Fixing thePWM6 pin to the high level when the TimerCounter is stopped CLR (TC6CR).3: Stops the timer. CLR (TC6CR).7 : Sets the PWM6 pin to the high level. Page 118 TMP88PS43FG Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc or fc/2 is selected as the source clock, a pulse is output from the PWM6 pin during the warm-up period time after exiting the STOP mode. Table 12-6 16-Bit PWM Output Mode Source Clock NORMAL, IDLE mode DV1CK = 0 fc/211[Hz] fc/27 fc/25 fc/23 DV1CK = 1 fc/212 [Hz] fc/28 fc/26 fc/24 Resolution DV1CK = 0 fc = 20MHz 102.4 µs 6.4 µs 1.6 µs 0.4 µs DV1CK = 1 fc = 20MHz 204.8 µs 12.8 µs 3.2 µs 0.8 µs Repeated Cycle DV1CK = 0 fc = 20 MHz 6.7 s 419.4 ms 104.9 ms 26.2 ms DV1CK = 1 fc = 20 MHz 13.4 s 838.8 ms 209.7 ms 52.4 ms Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 20.0 MHz) Setting ports LDW LD (PWREG5), 07D0H (TC5CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC6CR), 056H (TC6CR), 05EH Page 119 12.1 Configuration 12. 8-Bit TimerCounter 5,6(TC5, 6) TC6CR TC6CR Internal source clock an Write to PWREG5 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG5 FFFF 0 1 cp PWREG5 (Lower byte) ? Write to PWREG6 n m p Write to PWREG6 Figure 12-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 120 b Shift Shift bm Match detect an One cycle period bm PWREG6 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F6 PWM6 pin an cp INTTC6 interrupt request TMP88PS43FG TMP88PS43FG 12.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected, and the counter is cleared. The INTTC6 interrupt is generated at this time. Since the initial value can be set to the timer F/F6 by TC6CR, positive and negative pulses can be generated. Upon reset, the timer F/F6 is cleared to 0. (The logic level output from the PPG6 pin is the opposite to the timer F/F6.) Set the lower byte and upper byte in this order to program the timer register. (TTREG5 → TTREG6, PWREG5 → PWREG6) (Programming only the upper or lower byte should not be attempted.) For PPG output, set the output latch of the I/O port to 1. Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 20.0 MHz) Setting ports LDW LDW LD (PWREG5), 07D0H (TTREG5), 8002H (TC5CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC6CR), 057H (TC6CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR after the timer is stopped. Do not change TC6CR upon stopping of the timer. Example: Fixing the PPG6 pin to the high level when the TimerCounter is stopped CLR (TC6CR).3: Stops the timer CLR (TC6CR).7: Sets the PPG6 pin to the high level Note 3: i = 5, 6 Page 121 12.1 Configuration 12. 8-Bit TimerCounter 5,6(TC5, 6) TC6CR TC6CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG5 (Lower byte) ? n Figure 12-8 16-Bit PPG Mode Timing Chart (TC5 and TC60) Page 122 Match detect Match detect Match detect mn mn PWREG6 (Upper byte) ? m Match detect Match detect TTREG5 (Lower byte) ? r TTREG6 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F6 PPG6 pin INTTC6 interrupt request TMP88PS43FG TMP88PS43FG 13. Motor Control Circuit (PMD: Programmable motor driver) The TMP88PS43FG contains two channels of motor control circuits used for sinusoidal waveform output. This motor control circuit can control brushless DC motors or AC motors with or without sensors. With its primary functions like those listed below incorporated in hardware, it helps to accomplish sine wave motor control easily, with the software load significantly reduced. 1. Rotor position detect function • Can detect the rotor position, with or without sensors • Can be set to determine the rotor position when detection matched a number of times, to prevent erroneous detection • Can set a position detection inhibit period immediately after PWM-on 2. Independent timer and timer capture functions for motor control • Contains one-channel magnitude comparison timer and two-channel coincidence comparison timers that operate synchronously for position detection 3. PWM waveform generating function • Generates 12-bit PWM with 100 ns resolution • Can set a frequency of PWM interrupt occurrence • Can set the dead time at PWM-on 4. Protective function • Provides overload protective function based on protection signal input 5. Emergency stop function in case of failure • Can be made to stop in an emergency by EMG input or timer overflow interrupt • Not easily cleared by software runaway 6. Auto commutation/Auto position detection start function • Comprised of dual-buffers, can activate auto commutation synchronously with position detection or timer • Can set a position detection period using the timer function and start auto position detection at the set time 7. Electrical angle timer function • Can count 360 degrees of electrical angle with a set period in the range of 0 to 383 • Can output the counted electrical angle to the waveform arithmetic circuit 8. Waveform arithmetic circuit • Calculate the output duty cycle from the sine wave data and voltage data which are read from the RAM based on the electrical angle timer • Output the calculation result to the waveform synthesis circuit Page 123 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.1 Outline of Motor Control The following explains the method for controlling a brushless DC motor with sine wave drive. In a brushless DC motor, the rotor windings to which to apply electric current are determined from the rotor’s magnetic pole position, and the current-applied windings are changed as the rotor turns. The rotor’s magnetic pole position is determined using a sensor such as a hall IC or by detecting polarity change (zero-cross) points of the induced voltage that develops in the motor windings (sensorless control). For the sensorless case, the induced voltage is detected by applying electric current to two phases and not applying electric current to the remaining other phase. In this two-phase current on case, there are six current application patterns as shown in Table 13-1, which are changed synchronously with the phases of the rotor. In this two-phase current on case, the current on time in each phase is 120 degrees relative to 180 degrees of the induced voltage. Table 13-1 Current Application Patterns Current Application Pattern Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Upper Transistor u ON ON OFF OFF OFF OFF v OFF OFF ON ON OFF OFF w OFF OFF OFF OFF ON ON x OFF OFF OFF ON ON OFF Lower Transistor Current on Winding y ON OFF OFF OFF OFF ON z OFF ON ON OFF OFF OFF U→ V U→ W V→W V→ U W→ U W→ V Note: One of the upper or lower transistors is PWM controlled. For brushless DC motors, the number of revolutions is controlled by an applied voltage, and the voltage application is controlled by PWM. At this time, the current on windings need to be changed in synchronism with the phases of the voltage induced by revolutions. Control timing in cases where the current on windings are changed by means of sensorless control is illustrated in Figure 13-4. For three-phase motors, zero-crossing occurs six times during one cycle of the induced voltage (electrical angle 360 degrees), so that the electrical angle from one zero-cross point to the next is 60 degrees. Assuming that this period comprises one mode, the rotor position can be divided into six modes by zero-cross points. The six current application patterns shown above correspond one for one to these six modes. The timing at which the current application patterns are changed (commutation) is out of phase by 30 degrees of electrical angle, with respect to the position detection by an induced voltage. Mode time is obtained by detecting a zero-cross point at some timing and finding an elapsed time from the preceding zero-cross point. Because mode time corresponds to 60 degrees of electrical angle, the following applies for the case illustrated in Figure 13-4. 1. Current on windings changeover (commutation) timing 30 degrees of electrical angle = mode time/2 2. Position detection start timing 3. Failure determination timing 45 degrees of electrical angle = mode time × 3/4 120 degrees of electrical angle = mode time × 2 Timings are calculated in this way. The position detection start timing in 2 is needed to prevent erroneous detection of the induced voltage for reasons that even after current application is turned off, the current continues flowing due to the motor reactance. Control is exercised by calculating the above timings successively for each of the zero-cross points detected six times during 360 degrees of electrical angle and activating commutation, position detection start, and other operations according to that timing. In this way, operations can be synchronized to the phases of the induced voltage of the motor. The timing needed for motor control as in this example can be set freely as desired by using the internal timers of the microcontroller’s PMD unit. Also, sine wave control requires controlling the PWM duty cycle for each pulse. Control of PWM duty cycles is accomplished by counting degrees of electrical angle and calculating the sine wave data and voltage data at the counted degree of electrical angle. Page 124 TMP88PS43FG MCU Speed control Error handling, etc. PMD circuit Three-phase PWM Protective control Position detection Electrical angle timer Waveform calculation DC current U, V, W, X, Y, Z CL, EMG PDU, PDV, PDW DC motor Power drive Upper phase: u, v, w Lower phase: x, y, z Figure 13-1 Conceptual Diagram of DC Motor Control Mode Induced voltage Six-phase output 0 1 Zero crossing 2 U phase 3 4 V phase 5 W phase U phase H V phase W phase X phase Y phase Z phase Position detection Commutation Position detection start Failure determination Internal signal 60 30 45 120 L Figure 13-2 Example of Sensorless DC Motor Control Timing Chart Page 125 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.2 Configuration of the Motor Control Circuit The motor control circuit consists of various units. These include a position detection unit to detect the zero-cross points of the induced voltage or position sensor signal, a timer unit to generate events at three instances of electrical angle timing, and a three-phase PWM output unit to produce three-phase output PWM waveforms. Also included are an electrical angle timer unit to count degrees of electrical angle and a waveform arithmetic unit to calculate sinusoidal waveform output duty cycles. The input/output units are configured as shown in the diagram below. When using ports for the PMD function, set the Port input/output control register (P3CRi and P5CRi) to 0 for the input ports, and for the output ports, set the data output latch (P3i and P5i) to 1 and then the port input/output control register to 1. Other input/output ports can be set in the same way for use of the PMD function. CPU core Data and address buses Motor control circuit Timer circuit Electrical angle timer circuit Waveform generation circuit Waveform arithmetic circuit Position detection circuit Position signal input Error detection input U, V, W, X, Y, Z Figure 13-3 Block Diagram of the Motor Control Circuit Note 1: Always use the LDW instruction to set data in the 9, 12 and 16-bit data registers. Note 2: The EMG circuit initially is enabled. For PMD output, fix the EMG input port (P36 and P51) "H" high level or disable the EMG circuit before using for PMD output. Note 3: The EMG circuit initially is enabled. When using Port P3 and P5 as input/output IO ports, disable EMG. Note 4: When going to STOP mode, be sure to turn all of the PMD functions off before entering STOP mode. Page 126 TMP88PS43FG 13.3 Position Detection Unit The Position Detection Unit identifies the motor's rotor position from input patterns on the position signal input port. Applied to this position signal input port is the voltage status of the motor windings for the case of sensorless DC motors or a Hall element signal for the case of DC motors with sensors included. The expected patterns corresponding to specific rotor positions are set in the PMD Output Register (MDOUT) beforehand, and when the input position signal and the expected value match as the rotation, a position detection interrupt (INTPDC) is generated. Also, unmatch detection mode is used to detect the direction of motor rotation, where when the status of the position detection input port changes from the status in which it was at start of sampling, a position detection interrupt is generated. For three-phase brushless DC motors, there are six patterns of position signals, one for each mode, as summarized in Table 13-2 from the timing chart in Figure 13-2. Once a predicted position signal pattern is set in the MDOUT register, a position detection interrupt is generated the moment the position signal input port goes to mode indicated by this expected value. The position signals at each phase in the diagram are internal signals which cannot be observed from the outside. Table 13-2 Position Signal Input Patterns Position Detection Mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 U Phase (PDU) H H H L L L V Phase (PDV) L L H H H L W Phase (PDW) H L L L H H Page 127 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.3.1 Configuration of the position detection unit PMD output register MDOUT - E,D,C - - - - Position signal expected value Position signal input PDNUM PDU Latch PDV PDW Clock selector 2 Sampling control Latch MDOUTsync Coincidence detection Erroneous detection prevention circuit Counter Position detection interrupt INTPDC fc/4 Sampling control circuit Reset control 4 2 Timer interrupt INTTMR2/3 PWMON Delay circuit SDREG Sampling delay set register -, 6, 5, 4, 3, 2, 1, 0 7, 6 5, 4 3, 2, 1, 0 7, 6, 5, 4 3 2 1 0 PDCRA PDCRB Position detection control register Figure 13-4 Configuration of the Position Detection Circuit • The position detection unit is controlled by the Position Detection Control Register (PDCRA, PDCRB). After the position detection function is enabled, the unit starts sampling the position detection port with Timer 2 or in software. For the case of ordinary mode, when the status of the position detection input port matches the expected value of the PMD Output Register, the unit generates a position detection interrupt and finishes sampling, waiting for start of the next sampling. • When unmatch detection mode is selected for position detection, the unit stores the sampled status of the position detection port in memory at the time it started sampling. When the port input status changes from the status in which it was at start of sampling, an interrupt is generated. • In unmatch detection mode, the port status at start of sampling can be read (PDCRC). • When starting and stopping position detection synchronously with the timer, position detection is started by Timer 2 and position detection is stopped by Timer 3. • Sampling mode can be selected from three modes available: mode where sampling is performed only while PWM is on, mode where sensors such as Hall elements are sampled regularly, and mode where sampling is performed while the lower side is conducting current (when performing sampling only while PWM is on, DUTY must be set for all three phases in common). • When sampling mode is selected for detecting position while the lower phases are conducting current, sampling is performed for a period from when the set sampling delay time has elapsed after the lower side started conducting current till when the current application is turned off. Sampling is performed independently at each phase, and the sampling result is retained while sampling is idle. If while sampling at some phase is idle, the input and the expected value at other phase being sampled match, position is detected and an interrupt is generated. Page 128 TMP88PS43FG • A sampling delay is provided for use in modes where sampling is made while PWM is on or the lower phases are conducting current. It helps to prevent erroneous detection due to noise that occurs immediately after the transistor turns on, by starting sampling a set time after the PWM signal turned on. • When detecting position while PWM is on or the lower phases are conducting current, a method can be selected whether to recount occurrences of matched position detection after being compared for each PWM signal on (logical sum of three-phase PWM signals) (e.g., starting from 0 in each PWM cycle) or counting occurrences of matching continuously ( PDCRB is used to enable/disable recounting occurrences of matching while PWM is on). 13.3.2 Position Detection Circuit Register Functions PDCRC Hold result of position detection at PWM edge (Detect position detected position) Monitor sampling status Hold position signal input status These bits hold the comparison result of position detection at falling or rising edge of PWM pulse. Bits 5 and 4 are set to 1 when position is detected at the falling or the rising edge, respectively. They show whether position is detected in the current PWM pulse, during PWM off, or in the immediately preceding PWM pulse. When read, this bit shows the sampling status. This bit holds the status of the position signal input at the time position detection started in unmatch mode. 5, 4 EMEM 3 2 to 0 SMON PDTCT PDCRB 7, 6 5, 4 SPLCK SPLMD Sampling period Sampling mode Select fc/22, fc/23, fc/24, or fc/25 for the position detection sampling period. Select one of three modes: sampling only when PWM signal is active (when PWM is on), sampling regularly, or sampling when the lower side (X, Y, Z) phases are conducting current. In ordinary mode, when the port status and the set expected value match and continuously match as many times as the sampling counts set, a position detection signal is output and an interrupt is generated. In unmatch detection mode, when the said status and value do not match and continuously unmatch as many times as the sampling counts set, a position detection signal is output and an interrupt is generated. 3 to 0 PDCMP Sampling count PDCRA Sampling can be stopped in software by setting this bit to 1 (e.g., by writing to this register). Sampling is performed before stopping and when position detection results match, a position detection interrupt is generated, with sampling thereby stopped. Sampling can be started by setting this bit to 1 (e.g., by writing to this register). Sampling can be stopped by a trigger from Timer 3 by setting this bit to 1. Sampling is performed before stopping and when position detection results match, a position detection interrupt is generated, with sampling thereby stopped. Sampling can be started by a trigger from Timer 3 by setting this bit to 1. Select whether to use three pins (PDU/PDV/PDW) or one pin (PDU only) for position signal input. When one pin is selected, the expected values of PDV and PDW are ignored. When performing position detection with two pins or a pin other than PDU, position signal input can be masked as 0 by setting unused pin(s) for output. When performing sampling while PWM is on, occurrences of matching are recounted each time PWM signal turns on by setting this bit to 1 (when recounting occurrences of matching, the count is reset each time PWM turns off). When this bit is set to 0, occurrences of matching are counted continuously regardless PWM interval. Setting this bit to 0 selects ordinary mode where position is detected when the expected value set in the register and the port input unmatch and then match. Setting this bit to 1 selects unmatch detection mode where position is detected at the time the port status changes to another one from the status in which it was when sampling started. The position detection function is activated by setting this bit to 1. 7 SWSTP Stop sampling in software 6 5 4 SWSTT SPTM3 STTM2 Start sampling in software Stop sampling using Timer 3 Start sampling using Timer 2 Number of position signal input pins 3 PDNUM 2 RCEN Recount occurrences of matching when PWM is on 1 DTMD Position detection mode 0 PDCEN Position detection function Page 129 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG SDREG 6 to 0 SDREG Sampling delay Set a time for which to stop sampling in order to prevent erroneous detection due to noise that occurs immediately after PWM output turns on (immediately after the transistor turns on). (Figure 13-5) PWMON period PWM ON OFF Position detection match Sampling period Sampling delay Sampling pause Align the arrow to the start of counter switching. Number of position detection matches (n = 5) Match 0 1 2 3 4 5 0 Figure 13-5 Position Detection Sampling Timing with the PWMON Period Selected EMEM: Detects when a position detection match has occurred (the value is held aftr position detection). (Check on whether sampling has started on the previous pulse) PWM CASE1 CASE2 CASE3 CASE4 ON OFF EMEM value 11 01 10 00 1 Match (Sampling start) 1 1 0 0 0 0 1 11 A match with n = 5 means that it has started on the previous pulse. 01 00 10 Erroneous detection Figure 13-6 Detection Timing of the Position Detection Position Page 130 TMP88PS43FG Position Detection Circuit Registers [Addresses (PMD1 and PMD2)] PDCRC (01FA2H) (01FD2H) 7 – 6 – 5 EMEM 4 3 SMON 2 1 PDTCT 0 (Initial value: **00 0000) 5, 4 EMEM Hold result of position detection at PWM edge (Detect position detected position) Monitor sampling status Hold position signal input status 00: Detected in the current pulse 01: Detected while PWM off 10: Detected in the current pulse 11: Detected in the preceding pulse 0: Sampling idle 1: Sampling in progress Holds the status of the position signal input during unmatch detection mode. Bits 2 to 0 correspond to W, V, and U phases. R 3 2 to 0 SMON PDTCT PDCRB (01FA1H) (01FD1H) 7 SPLCK 6 5 SPLMD 4 3 2 PDCMP 1 0 (Initial value: 0000 0000) 00: fc/22 [Hz] (200 ns at 20 MHz) 7, 6 SPLCK Select sampling input clock 01: fc/23 10: fc/24 11: fc/25 (400 ns at 20 MHz) (800 ns at 20 MHz) (1.6 µs at 20 MHz) R/W 5, 4 SPLMD Sampling mode 00: Sample when PWM is on 01: Sample regularly 10: Sample when lower phases conducting current 11: Reserved 1 to 15 times (Counts 0 and 1 are assumed to be one time.) 3 to 0 PDCMP Position detection matched counts Note: When changing setting, keep the PDCEN bit reset to “0” (disable position detection function). PDCRA (01FA0H) (01FD0H) 7 SWSTP 6 SWSTT 5 SPTM3 4 STTM2 3 PDNUM 2 RCEN 1 DTMD 0 PDCEN (Initial value: 0000 0000) 7 6 5 4 3 2 1 0 SWSTP SWSTT SPTM3 STTM2 PDNUM RCEN DTMD PDCEN Stop sampling in software Start sampling in software Stop sampling using Timer 3 Start sampling using Timer 2 Number of position signal input pins Recount occurrences of matching when PWM is on Position detection mode Enable/Disable position detection function 0: No operation 1: Stop sampling 0: No operation 1: Start sampling 0: Disable 1: Enable 0: Disable 1: Enable 0: Compare three pins (PDU/PDV/PDW) 1: Compare one pin (PDU) only 0: Continue counting from previously PWM on 1: Recount each time PWM turns on 0: Ordinary mode 1: Unmatch detection mode 0: Disable 1: Enable (Sampling starts) W R/W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the PDCRA because it contains a write only bit. Page 131 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG SDREG (01FA3H) (01FD3H) 7 – 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: *000 0000) 6 to 0 SDREG Sampling delay 23/fc × n bits (n = 0 to 6, maximum 50.8 µs, resolution of 400 ns at 20 MHz) R/W Note: When changing setting, keep the PDCEN bit reset to “0” (disable position detection function). 13.3.3 Outline Processing in the Position Detection Unit Software Set mode pattern Hardware Write expected value MDOUT (E, D, C) Start position detection Sample position signal input Match with expected value? Yes Increment matching counts Specified count reached? No No INTTMR2 Timer unit Interrupt handling Increment mode counts INTPDC Yes Generate INTPDC interrupt End of position detection Page 132 TMP88PS43FG 13.4 Timer Unit Mode timer control registers MTCRA 7, 6, 5 4, 3, 2, 1 0 Overflow 4 fc/4 Clock selector Mode timer Timer reset control circuit Debug output - 3 7 MTCRB 5 - 3, 2, 1 3 Capture overwrite Capture control circuit Capture Overload protective interrupt INTCLM Position detection interrupt INTPDC MCAP F to 0 Mode capture register Timer 1 interrupt INTTMR1 (Commutation) CMP1 F to 0 Timer compare register Timer 1 magnitude comparison Timer 2 interrupt INTTMR2 (Position detection start) CMP2 F to 0 Timer 2 matching comparison CMP3 F to 0 Timer 3 matching comparison Timer 3 interrupt INTTMR3 (Overflow) Figure 13-7 Timer Circuit Configuration The timer unit has an up counter (mode timer) which is cleared by a position detection interrupt (INTPDC). Using this counter, it can generate three types of timer interrupts (INTTMR1 to 3). These timer interrupts may be used to produce a commutation trigger, position detection start trigger, etc. Also, the mode timer has a capture function which automatically captures register data in synchronism with position detection or overload protection. This capture function allows motor revolutions to be calculated by measuring position detection intervals. Page 133 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.4.1 Configuration of the Timer Unit The timer unit consists mainly of a mode timer, three timer comparator, and mode capture register, and is controlled by timer control registers and timer compare registers. • The mode timer can be reset by a signal from the position detection circuit, Timer 3, or overload protective circuit. If the mode timer overflows without being reset, it stops at FFFFH and sets an overflow flag in the control register. • The value of the mode timer during counting can be read by capturing the count in software and reading the capture register. • Timer 1 and Timers 2 and 3 generate an interrupt signal by magnitude comparison and matching comparison, respectively. Therefore, Timer 1 can generate an interrupt signal even when it could not write to the compare register in time and the counter value at the time of writing happens to exceed the register’s set value. • When any one of Timers 1 to 3 interrupts occurs, the next interrupts can be enabled by writing a new value to the respective compare registers (CMP1, CMP2, CMP3). • When capturing by position detection is enabled, the capture register has the timer value captured in it each time position is detected. In this way, the capture register always holds the latest value. Page 134 TMP88PS43FG 13.4.1.1 Timer Circuit Register Functions MTCRB Debug output can be produced by setting this bit to 1. Because interrupt signals to the interrupt control circuit are used for each interrupt, hardware debugging without software delays are possible. See the debug output diagram (Figure 13-8). Output ports: P67 for PMD1, P77 for PMD2. This bit shows that the timer has overflowed. When this bit is set to 1, the timer value can be captured using the overload protection signal (CL) as a trigger. When this bit is set to 1, the timer value can be captured in software (e.g., by writing to this register). When this bit is set to 1, the timer value can be captured using the position detection signal as a trigger. 7 DBOUT Debug output 5 3 2 1 TMOF CLCP SWCP PDCCP Mode timer overflow Capture mode timer by overload protection Capture mode timer in software Capture mode timer by position detection MTCRA 7, 6, 5 4 3 2 1 TMCK RBTM3 RBCL SWRES RBPDC Select clock Reset mode timer from Timer 3 Reset mode timer by overload protection Reset mode timer in software Reset mode timer by position detection Enable/disable mode timer Select the timer clock. When this bit is set to 1, the mode timer is reset by a trigger from Timer 3. When this bit is set to 1, the mode timer is reset by the overload protection signal (CL) as a trigger. When this bit is set to 1, the mode timer is reset in software (e.g., by writing to this register) When this bit is set to 1, the mode timer is reset by the position detection signal as a trigger. The mode timer is started by setting this bit to 1. Therefore, Timers 1 to 3 must be set with CMP before setting this bit. If this bit is set to 0 after setting CMP, CMP settings become ineffective. 0 TMEN MCAP Mode capture Position detection interval can be read out. CMP1 CMP2 CMP3 Timer 1 (commutation) Timer 2 (position detection start) Timer 3 (overflow) Timers 1 to 3 are enabled while the mode timer is operating. An interrupt can be generated once by setting the corresponding bit in this register. The interrupt is disable when an interrupt is generated or the timer is reset. To use the timer again, set the register back again even if data is same. Timer 1 interrupt (commutation) Timer 2 interrupt (position detection start) Timer 3 interrupt or position detection interrupt Debug output (P67, P77) Figure 13-8 DBOUT Debug Output Diagram Page 135 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG Timer Circuit Registers [Addresses (PMD1 and PMD2)] MTCRB (01FA5H) (01FD5H) 7 DBOUT 6 – 5 TMOF 4 – 3 CLCP 2 SWCP 1 PDCCP 0 – (Initial value: 0*0*0 000*) 7 5 3 2 1 DBOUT TMOF CLCP SWCP PDCCP Debug output Mode timer overflow Capture mode timer by overload protection Capture mode timer in software Capture mode timer by position detection 0: Disable 1: Enable (P67 for PMD1, P77 for PMD2) 0: No overflow 1: Overflowed 0: Disable 1: Enable 0: No operation 1: Capture 0: Disable 1: Enable R/W R R/W W R/W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRB because it contains a write-only bit. MTCRA (01FA4H) (01FD4H) 7 6 TMCK 5 4 RBTM3 3 RBCL 2 SWRES 1 RBPDC 0 TMEN (Initial value: 0000 0000) 000: fc/23 (400 ns at 20 MHz) 010: fc/24 (800 ns at 20 MHz) 100: fc/25 (1.6 µs at 20 MHz) 7, 6, 5 TMCK Select clock 110: fc/26 (3.2 µs at 20 MHz) 001: fc/27 (6.4 µs at 20 MHz) 011: Reserved 101: Reserved 111: Reserved 4 3 2 1 0 RBTM3 RBCL SWRES RBPDC TMEN Reset mode timer from Timer 3 Reset mode timer by overload protection Reset mode timer in software Reset mode timer by position detection Enable/disable mode timer 0: Disable 1: Enable 0: Disable 1: Enable 0: No operation 1: Reset 0: Disable 1: Enable 0: Disable 1: Enable timer start W R/W R/W Note 1: When changing MTCRA setting, keep the MTCRA bit reset to “0” (disable mode timer). Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRA because it contains a write-only bit. MCAP (01FA7H, 01FA6H) (01FD7H, 01FD6H) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) MCAP Mode capture Position detection interval R CMP1 (01FA9H, 01FA8H) (01FD9H, 01FD8H) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) CMP2 (01FABH, 01FAAH) (01FDBH, 01FDAH) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) Page 136 TMP88PS43FG CMP3 (01FADH, 01FACH) (01FDDH, 01FDCH) F DF E DE D DD C DC B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000 0000 0000) CMP1 CMP2 CMP3 Timer 1 Timer 2 Timer 3 Magnitude comparison compare register Matching comparison compare register Matching comparison compare register R/W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRB or MTCRA register because these registers contain write-only bits. 13.4.1.2 Outline Processing in the Timer Unit Software Interrupt handling Read MCAP Calculate timer set value MCAP ´ 1/2 MCAP ´ 3/4 MCAP ´ 2 Set timer Processing unnecessary CMP1, CMP2, CMP3 Commutation INTTMR1 To PWM MCAP Hardtware INTPDC Position detection unit Start Start Mode timer count up Mode timer MCAP Clear mode timer End Greater than compare 1? No Match with compare 2? No Match with compare 3? No Yes Generate INTTMR1 interrupt Generate INTTMR2 interrupt Generate INTTMR3 interrupt End of timer 1 ¯ Processing unnecessary Position detection start INTTMR2 To the position detection Error determination unit INTTMR3 Yes End of timer 2 Interrupt handling error handling Yes End of timer 3 Page 137 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.5 Three-phase PWM Output Unit The Three-phase PWM Output Unit has the function to generate three-phase PWM waves with any desired pulse width and the commutation function capable of brushless DC motor control. In addition, it has the protective functions such as overload protection and emergency stop functions necessary to protect the power drive unit, and the dead time adding function which helps to prevent the in-phase upper/lower transistors from getting shorted by simultaneous turn-on when switched over. For the PWM output pin (U,V,W,X,Y,Z), set the port register PxDR and PxCR (x = 3,5) to 1. The PWM output initially is set to be active low, so that if the output needs to be used active high, set up the MDCRA Register accordingly. 13.5.1 Configuration of the three-phase PWM output unit The three-phase PWM output unit consists of a pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop and overload), and a dead time control circuit. 13.5.1.1 Pulse width modulation circuit (PWM waveform generating unit) This circuit produces three-phase independent PWM waveforms with an equal PWM frequency. For PWM waveform mode, triangular wave modulation or sawtooth wave modulation can be selected by using the PMD Control Register (MDCRA) bit 1. The PWM frequency is set by using the PMD Period Register (MDPRD). The following shows the relationship between the value of this register and the PWM counter clock set by the MDCRB Register, PWMCK. 1 Sawtooth wave PWM: MDPRD Register set value = -----------------------------------------------------------------------------------PWM frequency [ Hz ] × PWMCK 1 Triangular wave PWM: MDPRD Register set value = --------------------------------------------------------------------------------------------PWM frequency [ Hz ] × 2 × P WMCK The PMD Period Register (MDPRD) is comprised of dual-buffers, so that CMPU, V, W Register is updated with PWM period. When the waveform arithmetic circuit is operating, the PWM waveform output unit receives calculation results from the waveform arithmetic circuit and by using the results as CMPU, V, W Register set value, it outputs independent three-phase PWM waveforms. When the waveform calculation function is enabled by the waveform arithmetic circuit and transfer of calculation results into the CMPU to W Registers is enabled (with EDCRA Register bit 2), the CMPU to W Registers are disabled against writing. When the waveform calculation function is enabled (with EDCRA Register bit 1) and transfer of calculation results into the CMPU, V, W Registers is disabled (with EDCRA Register bit 4), the calculation results are transferred to the buffers of CMPU, V, W Registers, but not output to the port. Read-accessing the CMPU, V, and W registers can read the calculation results of the waveform arithmetic circuit that have been input to a buffer. After changing the read calculation result data by software, writing the changed data to the CMPU, V, and W registers enables an arbitrary waveform other than a sinusoidal wave to be output. When the registers are read after writing, the values written to the registers are read out if accessed before the calculation results are transferred after calculation is finished. Page 138 TMP88PS43FG [Sawtooth wave] MDCNT Data update [MDPRD] [CMPU] Time PWMU waveform [Triangular wave] On Off MDCNT Data update [MDPRD] [CMPU] Time On PWMU waveform Off Figure 13-9 PWM Waveforms The values of the PWM Compare Registers (CMPU/V/W) and the carrier wave generated by the PWM Counter (MDCNT) are compared for the relative magnitude by the comparator to produce PWM waveforms. The PWM Counter is a 12-bit up/down counter with a 100 ns (at fc = 20 MHz) resolution. For three-phase output control, two methods of generating three-phase PWM waveforms can be set. 1. Three-phase independent mode: Values are set independently in the three-phase PMD Compare Registers to produce three-phase independent PWM waveforms. This method may be used to produce sinusoidal or any other desired drive waveforms. 2. Three-phase common mode: A value is set in only the U-phase PMD Compare Register to produce three in-phase PWM waveforms using the U phase set value. This method may be used for DC motor square wave drive. The three-phase PMD Compare Registers each have a comparison register to comprise a dual-buffer structure. The values of the PMD Compare Registers are loaded into their respective comparison registers synchronously with PWM period. Page 139 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.5.1.2 Commutation control circuit Output ports are controlled depending on the contents set in the PMD Output Register (MDOUT). The contents set in this register are divided into two, one for selecting the synchronizing signal for port output, and one for setting up port output. The synchronizing signal can be selected from Timers 1 or 2, position detection signal, or without sync. Port output can be synchronized to this synchronizing signal before being further synchronized to the PWM signal sync. The MDOUT Register's synchronizing signal select bit becomes effective immediately after writing. Other bits are dual-buffered, and are updated by the selected synchronizing signal. Example: Commutation timing for one timer period with PWM synchronization specified INTTMR PWM Commutation Output on six ports can be set to be active high or active low independently of each other by using the MDCRA Register bits 5 and 4. Furthermore, the U, V, and W phases can individually be selected between PWM output and H/L output by using the MDOUT Register bits A to 8 and 5 to 0. When PWM output is selected, PWM waveforms are output; when H/L output is selected, a waveform which is fixed high or low is output. The MDOUT Register bits E to C set the expected position signal value for the position detection circuit. PWM control register MDCRA 7 6 − − 3, 2, 1 0 3 PWM control PWM synchronizing clock Up/Down PWM counter PWM interrupt INTPWM fc/2 MDCRB 1 to 0 Clock selector Selector/ Latch Selector/ Latch MDCNT B to 0 Stop MDCNT PMD period register MDPRD B to 0 PMD compare register CMPU B to 0 PWMU Buffer U Three-phase common/ Three-phase CMPV B to 0 PWMV Buffer V CMPW B to 0 PWMW Buffer W Figure 13-10 Pulse Width Modulation Circuit Page 140 TMP88PS43FG PMD output register − −, −, − B A, 9, 8 7, 6 5, 4, 3, 2, 1, 0 MDOUT 3 PWM synchronizing clock fc/4 S Selector 2 6 Position detection interrupt INTPDC Timer 1 interrupt INTTMR1 Timer 2 interrupt INTTMR2 S Selector Gate control Set Reset Latch MDOUT sync u PWMU x v PWMV y w PWMW z Figure 13-11 Commutation Control Circuit Dead time register DTR -, -, 5, 4, 3, 2, 1, 0 fc/8 u' x' ON delay circuit ON delay circuit PMD control register MDCRA --54---U X V Y W Z v' y' ON delay circuit w' z' Figure 13-12 Dead Time Circuit Page 141 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.5.2 Register Functions of the Waveform Synthesis Circuit MDCRB PWMCK Select PWM counter clock Select PWM counter clock. MDCRA 7 HLFINT Select half-period interrupt When this bit is set to 1, INTPWM is generated every half period (at triangular wave peak and valley) in the case of center PWM output and PINT = 00. In other cases, this setting has no meaning. Select whether to set the duty cycle independently for three phases using the CMPU to W Registers or in common for all three phases by setting the CMPU Register only. Select the upper-phase output port polarity. Make sure the waveform synthesis function (MDCRA Register bit 0) is idle before selecting this port polarity. Select the lower-phase output port polarity. Make sure the waveform synthesis function (MDCRA Register bit 0) is idle before selecting this port polarity. Select the frequency at which to generate a PWM interrupt from four choices available: every PWM period or once every 2, 4, or 8 PWM periods. When setting of this bit is altered while operating, an interrupt may be generated at the time the bit is altered. Select PWM mode. PWM mode 0 is an edge PWM (sawtooth wave), and PWM mode 1 is a center PWM (triangular wave). When enabling this circuit (for waveform output), be sure to set the output port polarity and other bits of this register (other than MDCRA bit 0) beforehand. 6 5 4 DTYMD POLH POLL DUTY mode Upper-phase port polarity Lower-phase port polarity 3, 2 PINT PWM interrupt frequency 1 0 PWMMD PWMEN PWM mode Enable/Disable waveform generation circuit DTR DTR Dead time Set the dead time between the upper-phase and lower-phase outputs. MDOUT F UPDWN PWM counter flag This bit indicates whether the PWM counter is counting up or down. When edge PWM (sawtooth wave) is selected, it is always set to 0. Set the data to be compared with the position detection input port. The comparison data is adopted as the expected value simultaneously when port output sync settings made with MDOUT are reflected in the ports. (This is the expected position detection input value for the output set with MDOUT next time.) Select whether or not to synchronize port output to PWM period after being synchronized to the synchronizing signal selected with SYNCS. If selected to be synchronized to PWM, output is kept waiting for the next PWM after being synchronized with SYNCS. Waveform settings are overwritten if new settings are written to the register during this time, and output is generated with those settings. Set U, V, and W-phase port outputs. (See the Table 13-3) Select the synchronizing signal with which to output UVW-phase settings to ports. The synchronizing signal can be selected from Timers 1 or 2, position detection, or asynchronous. Select asynchronous when the initial setting, otherwise the above setting isn’t reflected immediately. Set U, V, and W-phase port outputs. (See the Table 13-3) E, D, C PDEXP Mode compare register B PSYNC Select PWM synchronization A 9 8 WPWM VPWM UPWM Control UVW-phase PWM outputs 7, 6 SYNCS Select port output sync signal 5, 4 3, 2 1, 0 WOC VOC UOC Control UVW-phase outputs MDCNT PWM counter This is a 12-bit read-only register used to count PWM periods. MDPRD Set PWM period This register determines PWM period, and is dual-buffered, allowing PWM period to be altered even while the PWM counter is operating. The buffers are loaded every PWM period. When 100 ns is selected for the PWM counter clock, make sure the least significant bit is set to 0. Page 142 TMP88PS43FG CMPU CMPV CMPW Set PWM pulse width This comparison register determines the pulse widths output in the respective UVW phases. This register is dual-buffered, and the pulse widths are determined by comparing the buffer and PWM counter. Waveform Synthesis Circuit Registers [Addresses (PMD1 and PMD2)] MDCRB (01FAFH) (01FDFH) 7 – 6 – 5 – 4 – 3 – 2 – 1 PWMCK 0 (Initial value: **** **00) 00: fc/2 [Hz] (100 ns at 20 MHz) 1, 0 PWMCK PWM counterSelect clock 01: fc/22 10: fc/23 11: fc/24 (200 ns at 20 MHz) (400 ns at 20 MHz) (800 ns at 20 MHz) R/W Note: When changing setting, keep the PWMEN bit reset to “0” (disable wave form synthesis function). MDCRA (01FAEH) (01FDEH) 7 HLFINT 6 DTYMD 5 POLH 4 POLL 3 PINT 2 1 PWMMD 0 PWMEN (Initial value: 0000 0000) 7 6 5 4 HLFINT DTYMD POLH POLL Select half-period interrupt DUTY mode Upper-phase port polarity Lower-phase port polarity 0: Interrupt as specified in PINT 1: Interrupt every half period when PINT = 00 0: U phase in common 1: Three phases independent 0: Active low 1: Active high 0: Active low 1: Active high 00: Interrupt every period 01: Interrupt once every 2 periods 10: Interrupt once every 4 periods 11: Interrupt once every 8 periods 0: PWM mode0 (Edge: Sawtooth wave) 1: PWM mode1 (Center: Triangular wave) 0: Disable 1: Enable (Waveform output) R/W 3, 2 PINT Select PWM interrupt (trigger) 1 0 PWMMD PWMEN PWM mode Enable/disable waveform synthesis function DTR (01FBEH) (01FEEH) 7 – 6 – 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: **00 0000) 5 to 0 DTR Dead time 23/fc × 6 bit (maximum 25.2 µs at 20 MHz) R/W Note: When changing setting, keep the MDCRA bit reset to "0" (disable wave form synthesis function). Page 143 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG MDOUT (01FB3H, 01FB2H) (01FE3H, 01FE2H) F UPDWN 7 SYNCS E D PDEXP C B PSYNC A WPWM 2 VOC 9 VPWM 1 UOC 8 UPWM 0 (Initial value: 00000000 00000000) 6 5 WOC 4 3 F UPDWN PWM counter flag Comparison register for position detection Select PWM synchronization W-phase PWM output V-phase PWM output U-phase PWM output 0: Counting up 1: Counting down bit E: W-phase expected value bit D: V-phase expected value bit C: U-phase expected value 0: Asynchronous 1: Synchronized 0: H/L level output 1: PWM waveform output 0: H/L level output 1: PWM waveform output 0: H/L level output 1: PWM waveform output 00: Asynchronous 01: Synchronized to position detection 10: Synchronized to Timer 1 11: Synchronized to Timer 2 R E, D, C PDEXP B A 9 8 PSYNC WPWM VPWM UPWM R/W 7, 6 SYNCS Select port output synchronizing signal Control W-phase output Control V-phase output Control U-phase output 5, 4 3, 2 1, 0 WOC VOC UOC See the table 1-3 13.5.3 Port output as set with UOC/VOC/WOC bits and UPWM/VPWM/WPWM bits Table 13-3 Example of Pin Output Settings U-phase output polarity: Active high (POLH,POLL = 1) UPWM UOC 1: PWM output U phase 00 01 10 11 PWM U-phase output polarity: Active low (POLH,POLL = 0) UPWM UOC 1: PWM output U phase 00 01 10 11 PWM H PWM PWM 0: H/L level output U phase L L H H X phase L H L H 0: H/L level output U phase H H L L X phase H L H L X phase PWM PWM L PWM X phase PWM PWM L PWM PWM H PWM Page 144 TMP88PS43FG MDCNT (01FB5H, 01FB4H) (01FE5H, 01FE4H) F – E – D – C – B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) B to 0 PWM counter PWM period counter value R MDPRD (01FB7H, 01FB6H) (01FE7H, 01FE6H) F – E – D – C – B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) B to 0 PWM period PWM period MDPRD ≥ 010H R/W CMPU (01FB9H, 01FB8H) (01FE9H, 01FE8H) F – E – D – C – B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) CMPV (01FBBH, 01FBAH) (01FEBH, 01FEAH) F – E – D – C – B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) CMPW (01FBDH, 01FBCH) (01FEDH, 01FECH) F – E – D – C – B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****000000000000) CMPU B to 0 CMPV CMPW PWM compare U register PWM compare V register PWM compare W register Set U-phase duty cycle Set V-phase duty cycle Set W-phase duty cycle R/W Page 145 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.5.4 Protective Circuit This circuit consists of an EMG protective circuit and overload protective circuit. These circuits are activated by driving their respective port inputs active. EMG control register EMGCRB 7 6, 5 4 3, 2, 1, 0 2 4 EMGCRA 7, 6, 5, 4 − 2 1 0 4 Under protection 2 EMG disable code register EMGREL MDOUT A to 0 7, 6, 5, 4, 3, 2, 1, 0 8 EMG protective control Set "0" Overload protective input CL Timer 1 interrupt INTTMR1 PWM synchronizing clock PWM sync Overload protective interrupt INTCLM Stop MDCNT CL detection Reset control Overload protective control EMG EMG input INTEMG EMG interrupt u x v y w z u' x' v' y' w' z' Figure 13-13 Configuration of the Protective Circuit a. EMG protective circuit This protective circuit is used for emergency stop, when the EMG protective circuit is enabled. When the signal on EMG input port goes active (negative edge triggered), the six ports are immediately disabled high-impedance against output and an EMG interrupt (INTEMG) is generated. The EMG Control Register (EMGCRA) is used to set EMG protection. If the EMGCRA shows the value “1” when read, it means that the EMG protective circuit is operating. To return from the EMG protective state, reset the MDOUT Register bits A to 0 and set the EMGCRA to 1. Returning from the EMG protective state is effective when the EMG protective input has been released back high. To disable the EMG function, set data “5AH“ and “A5H“sequentially in the EMG disable Register (EMGREL) and reset the EMGCRA to 0. When the EMG function is disabled, EMG interrupts (INTEMG) are not generated. The EMG protective circuit is initially enabled. Before disabling it, fully study on adequacy. b. Overload protective circuit The overload protective circuit is set by using the EMG Control Registers (EMGCRA/B). To activate overload protection, set the EMGCRB to 1 to enable the overload protective circuit. The circuit starts operating when the overload protective input is pulled low. To return from overload state, there are three methods to use: return by a timer (EMGCRB), return by PWM sync (EMGCRB), or return manually (EMGCRB). These methods are usable when the overload protective input has been released back high. Page 146 TMP88PS43FG The number of times the overload protective input is sampled can be set by using the EMGCRA. The sampling times can be set in the range of 1 to 15 times at 200 ns period (when fc = 20 MHz). If a low level is detected as many times as the specified number, overload protection is assumed. The output disabled phases during overload protection are set by using the EMGCRB. This facility allows selecting to disable no phases, all phases, PWM phases, or all upper phases/all lower phases. When selected to disable all upper phases/all lower phases, port output is determined by their turn-on status immediately before being disabled. When two or more upper phases are active, all upper phases are turned on and all lower phases are turned off; when two or more lower phases are active, all upper phases are turned off and all lower phases are turned on. When output phase are cut off, output is inactive (low in the case of high active). When the overload protective circuit is disabled, overload protective interrupts (INTCLM) are not generated. I (Current) EMG setting current Overload protection setting current Input EMG pin Input CL pin PWM output ("H" active) Overload protection (Output cut off) EMG protection (High-Z output) t (time) Figure 13-14 Example of Protection Circuit Operation Page 147 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.5.5 Functions of Protective Circuit Registers EMGREL EMG disable The EMG protective circuit is disable from the disabled state by writing “5AH“ and “A5H“ to this register in that order. After that, the EMGCRA Register needs to be set. EMGCRB Return from overload protective state When this bit is set to 1, the motor control circuit is returned from overload protective state in software (e.g., by writing to this register). Also, the current state can be known by reading this bit. MDOUT outputs at return from the overload protective state remain as set before the overload protective input was driven active. When this bit is set to 1, the motor control circuit is returned from overload protective state by PWM sync. If RTCL is set to 1, RTCL has priority. When this bit is set to 1, the motor control circuit is returned from overload protective state by Timer 1 sync. If RTCL is set to 1, RTCL has priority. The status of overload protection can be known by reading this bit. Select the phases to be disabled against output during overload protection. This facility allows selecting to disable no phases, all phases, PWM phases, or all upper phases/all lower phases. Can stop the PWM counter during overload protection. Enable or disable the overload protective function. 7 RTCL 6 5 4 3, 2 RTPWM RTTM1 CLST CLMD Return by PWM sync Return by timer sync Overload protective state Select output disabled phases during overload protection Stop counter during overload protection Enable/Disable overload protection 1 0 CNTST CLEN EMGCRA 7 to 4 2 1 CLCNT EMGST RTE Overload protection sampling time EMG protective state Return from EMG protective state Set the length of time the overload protective input port is sampled. The status of EMG protection can be known by reading this bit. The motor control circuit is returned from EMG protective state by setting this bit to “1” . When returning, set the MDOUT Register A to 0 bits to “0” . Then set the EMGCRA Register bit 1 to “1” and set MDOUT waveform output. Then set up the MDCRA Register. The EMG protective circuit is activated by setting this bit to 1. This circuit initially is enabled. (To disable this circuit, make sure key code 5AH and A5H are written to the EMGREL1 Register beforehand.) 0 EMGEN Enable/Disable EMG protective circuit Page 148 TMP88PS43FG Protective Circuit Registers [Addresses (PMD1 and PMD2)] EMGREL (01FBFH) (01FEFH) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: 0000 0000) 7 to 0 EMGREL EMG disable Can disable by writing 5AH and then A5H. W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGREL register because this register is write only. EMGCRB (01FB1H) (01FE1H) 7 RTCL 6 RTPWM 5 RTTM1 4 CLST 3 CLMD 2 1 CNTST 0 CLEN (Initial value: 0000 0000) 7 RTCL Return from overload protective state Enable/Disable return from overload protective state by PWM sync Enable/Disable return from overload protective state by timer 1 Overload protective state 0: No operation 1: Return from protective state 0: Disable 1: Enable W 6 RTPWM R/W 0: Disable 1: Enable 0: No operation 1: Under protection 00: No phases disabled against output 01: All phases disabled against output 10: PWM phases disabled against output 11: All upper/All lower phases disabled against output (Note) 0: Do not stop 1: Stop the counter 0: Disable 1: Enable R/W R 5 RTTM1 4 CLST 3, 2 CLMD Select output disabled phases during overload protection Stop PWM counter during overload protection Enable/Disable overload protective circuit 1 0 CNTST CLEN Note: If during overload protection the port output state in two or more upper phases is on, all lower phases are disabled and all upper phases are enabled for output; when two or more lower phases are on, all upper phases are disabled and all lower phases are enabled for output. EMGCRA (01FB0H) (01FE0H) 7 6 CLCNT 5 4 3 2 EMGST 1 RTE 0 EMGEN (Initial value: 0000 *001) 7 to 4 2 1 0 CLCNT EMGST RTE EMGEN Overload protection sampling number of times. EMG protective state Return from EMG state Enable/Disable EMG protective circuit 22/fc × n ( n = 1 to 15, 0 and 1 are set as 1 at 20 MHz ) 0: No operation 1: Under protection 0: No operation 1: Return from protective state (Note 1) 0: Disable 1: Enable R/W R W R/W Note 1: An instruction specifying a return from the EMG state is invalid if the EMG input is “L”. Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EMGCRB or EMGCRA register because these registers contain write-only bits. Page 149 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.6 Electrical Angle Timer and Waveform Arithmetic Circuit Electrical Angle Timer fc/8 Clock select and divide circuit 12-bit counter Reset Position detection Caputure (EDCAP) 2 Comparator ELDEG 8, 7, 6, 5, 4, 3, 2, 1, 0 Count stop 9-bit electrical angle register 7 - 5, 4 -, -, -, EDCRA Period register buffer 4-bit counter Decoder Period correction circuit F to C Correction value (4 bits) B to 0 EDSET Electrical angle period (12 bits) Figure 13-15 Electrical Angle Timer Circuit Waveform Arithmetic Circuit AMP B, A, 8, 7, 6, 5, 4, 3, 2, 1, 0 Voltage set register Electrical angle timer interrupt (INTEDT) Selector (12 bits) Electrical angle timer (9 bits) Electrical angle RAM ´ 384 bytes Multiplier 12 bits 2-/3-phase modulation switch Selector ELDEG 8, 7, 6, 5, 4, 3, 2, 1, 0 WFMDR 76543210 Calculation finish 8 bits 3210 EDCRB - 6 -, - 3 2 1 0 EDCRA U-phase V-phase W-phase calculation calculation calculation result result result 12 bits 12 bits 12 bits CMPU CMPV CMPW Figure 13-16 Waveform Arithmetic Circuit Page 150 TMP88PS43FG 13.6.1 Electrical Angle Timer and Waveform Arithmetic Circuit The Electrical Angle Timer finishes counting upon reaching the value set by the Period Set Register (EDSET). The Electrical Angle Timer counts 360 degrees of electrical angle in the range of 0 to 383 (17FH) and is cleared to 0 upon reaching 383. In this way, it is possible to obtain the electrical angle of the frequency proportional to the value set by the Period Set Register. The period with which to count up can be corrected by using the Period Correction Register, allowing for fine adjustment of the frequency. The electrical angles counted by the Electrical Angle Timer are presented to the Waveform Arithmetic Circuit. An electrical angle timer interrupt signal is generated each time the Electrical Angle Timer finishes counting. The Waveform Arithmetic Circuit has a sine wave data table, which is used to extract sine wave data based on the electrical angle data received from the Electrical Angle Timer. This sine wave data is multiplied by the value of the Voltage Amplitude Register. For 2-phase modulation, the product obtained by this multiplication is presented to the waveform synthesis circuit. For 3-phase modulation, waveform data is further calculated based on the product of multiplication and the electrical angle data and the value of the PWM Period Register. The calculation is performed each time the Electrical Angle Timer finishes counting or when a value is set in the Electrical Angle Register, and the calculation results consisting of the U phase, the V phase (+120 degrees), and the W phase (+240 degrees) are sequentially presented to the PWM waveform output circuit. The sine wave data table is stored in the RAM and requires initialization. • To correct the period, set the number of times ‘n’ to be corrected in the Period Correction Register (EDSET Register F to C bits). The period is corrected by adding 1 to electrical angle counts 16 for ‘n’ times. For example, when a value 3 is set in the Period Correction Register, the period for 13 times out of electrical angle counts 16 is the value “mH” set in the Period Set Register, and that for 3 times is “m + 1H”. (Correction is made almost at equal intervals.) • Because the electrical angle counter (ELDEG) can be accessed even while the Electrical Angle Timer is operating, the electrical angles can be corrected during operation. • The Electrical Angle Capture EDCAP captures the electrical angle value from the Electrical Angle Counter at the time the position is detected. • When the waveform calculation function is enabled, waveform calculation is performed each time the electrical angle counter (ELDEG) are accessed for write or the Electrical Angle Timer finishes counting. • The calculation is performed in 35 machine cycle of execution time, or 7 µs (at 20 MHz). • When transfer of calculation result to the CMP Registers is enabled (EDCRA), the calculation results are transferred to the CMPU to W Registers. (This applies only when the waveform calculation function is enabled with the EDCRA.) The CMPU to W Registers are disabled against write while the transfer remains enabled. The calculation results can be read from the CMPU to W Registers while the waveform calculation function remains enabled. • The calculated results can be modified and the modified data can be set in the CMPU to W Registers in software. This makes it possible to output any desired waveform other than sine waves. If a transfer (EDCRA register bit 2) of the calculated results to the CMP register is disabled, readaccessing the CMPU to W registers can read the calculated results. (Before read-accessing these registers, make sure that the calculation is completed.) • To initialize the entire RAM data of the sine wave data table, set the addresses at which to set, sequentially from 000H to 17FH, in the ELDEG Register, and write waveform data to the WFMDR Register each time. Make sure the Waveform Arithmetic Circuit is disabled when writing this data. Note 1: The value set in the Period Set Register (EDSET Register EDT bits) must be equal to or greater than 010H. Any value smaller than this is assumed to be 010H. Note 2: The sine wave data that is read consists of the U phase, the V phase whose electrical angle is +120 degrees relative to the U phase, and the W phase whose electrical angle is +240 degrees relative to the U phase. Note 3: If a period corresponding to an electrical angle of one degree is shorter than the required calculation time, the previously calculated results are used. Page 151 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.6.1.1 Functions of the Electrical Angle Timer and Waveform Arithmetic Circuit Registers EDCRB 3 2 CALCST CALCBSY Start calculation by software Calculation flag Enable/disable calculation start synchronized with electrical angle Electrical angle interrupt Forcefully start calculation. When this bit is written while the waveform arithmetic circuit is calculating, the calculation is terminated and then newly started. By reading this bit, the operation status of the waveform arithmetic circuit can be obtained. Select whether to start calculation when the electrical angle timer finishes counting or when a value is set in the electrical angle register. When disabled, calculation is only started when CALCST is set to 1. Set the electrical angle interrupt signal request timing to either when the electrical angle timer finishes counting or upon end of calculation. 1 EDCALEN 0 EDISEL EDCRA 7 6 5, 4 EDCNT EDRV EDCK Electrical angle count up/ down Select V-, W-phase Select clock Set whether the electrical angle timer counts up or down. Select phase direction of V-phase and W-phase in relation to U-phase. Select the clock for the electrical angle timer. This setting can be altered even while the electrical angle timer is operating. Select the modulation method with which to perform waveform calculation. Two-phase modulation DATA = ramdata (ELDEG) × AMP 3 C2PEN Switch between 2-phase and 3-phase modulations MOPRD ramdata ( ELDEG ) × AMP Three-phase modulation: DATA = ---------------------- ± -------------------------------------------------------------------2 2 Note: The ± sign during 3-phase modulation changes depending on the electrical angle. + for electrical angles 0 to 179 degrees (191) − for electrical angles 180 (192) to 360 (383) degrees 2 RWREN Auto transfer calculation results to CPM registers Enable/disable transfer of calculation results by the waveform arithmetic circuit. When the waveform calculation function is enabled while at the same time transfer is enabled, calculation results are set as U, V, and W-phase duty cycles of the PWM generation circuit and are reflected in the ports. Enable/disable the waveform calculation function. Calculations are performed by the waveform arithmetic circuit by enabling the waveform calculation function. When the waveform calculation function is enabled, the calculated results can be read from the U, V, and W-phase compare registers (CMPU, V, W) of the PWM generation circuit. Enable/disable the electrical angle timer. When enabled, the electrical angle timer starts counting; when disabled, the electrical angle timer stops counting and is cleared to 0. 1 CALCEN Enable/disable waveform calculation function 0 EDTEN Electrical angle timer EDSET F to C B to 0 EDTH EDT Correct electrical angle period Electrical angle period Correct the period by adding 1 to electrical angle counts 16 for “n” times. The timer counts the electrical angle period set value “m”’for (16 − n) times and counts (m + 1) for “n” times Set the electrical angle period. ELDEG Electrical angle Read the electrical angle. This register can also be set to initialize or correct the angle while counting. Any value greater than 17FH cannot be set. AMP Set voltage amplitude Set the voltage amplitude. The waveform arithmetic circuit multiplies the data set here by the sine wave data read out from the sine wave RAM. The amplitude has its upper limit determined by the set value of the MDPRD register when performing this multiplication. EDCAP Capture electrical angle Capture the value from the electrical angle timer when the position is detected. WFMDR Set sine wave data To initialize the entire RAM data of the sine wave table, set the addresses at which to set, sequentially from 000H to 17FH, in the ELDEG register, and write waveform data to the WFMDR register each time. Make sure the waveform arithmetic circuit is disabled when writing this data. Page 152 TMP88PS43FG Typical Settings of Sine Wave Data Two-phase modulation 100% Data amplitude 255 0 0 Three-phase modulation 100% Data amplitude 255 64 60 (40H) 128 120 (80H) 192 (C0H) 256 (100H) 320 (140H) 383 (17FH) (ELDEG) 180 240 300 360 Electrical angle 0 0 64 60 (40H) 128 120 (80H) 192 (C0H) 256 (100H) 320 (140H) 383 (17FH) (ELDEG) 180 240 300 360 Electrical angle Note: During 3-phase modulation, the sign changes at 180 degrees of electrical angle. Figure 13-17 Typical Settings of Sine Wave Data Page 153 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG List of the Electrical Angle Timer and Waveform Arithmetic Circuit Registers [Addresses (PMD1 and PMD2)] EDCRB (01FC1H) (01FF1H) 7 – 6 – 5 – 4 – 3 CALCST 2 CALCBSY 1 EDCALEN 0 EDISEL (Initial value: **** 0000) 3 2 CALCST CALCBSY Start calculation by software Calculation flag Enable/disable calculation start synchronized with electrical angle Electrical angle interrupt 0: No operation 1: Start calculation 0: Waveform Arithmetic Circuit stopped 1: Waveform Arithmetic Circuit calculating 0: Start calculation insync with electrical angle 1: Do notcalculation insync with electrical angle 0: Interrupt when the Electrical Angle Timer finishes counting 1: Interrupt upon end of calculation W R 1 EDCALEN R/W 0 EDISEL Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the EDCRB register because this register is write only. EDCRA (01FC0H) (01FF0H) 7 EDCNT 6 EDRV 5 EDCK 4 3 C2PEN 2 RWREN 1 CALCEN 0 EDTEN (Initial value: 0000 0000) 7 6 EDCNT EDRV Electrical angle count up/down Select V-, W-phase 0: Count up 1: Count down 0: V = U + 120°, W = U + 240° 1: V = U − 120°, W = U − 240° 00: fc/23 (400 ns at 20 MHz) 5, 4 EDCK Select clock 01: fc/24 (800 ns at 20 MHz) 10: fc/25 (1.6 µs at 20 MHz) 11: fc/26 (3.2 µs at 20 MHz) R/W 3 2 1 0 C2PEN RWREN CALC EDTEN Switch between 2-/3-phase modulations Transfer calculation result to CMP registers Enable/disable waveform calculation function Electrical angleEnable/disable mode timer 0: 2-phase modulation 1: 3-phase modulation 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable Note: When changing the EDCRA setting, keep the EDCRA bit reset “0” (Disable electrical angle timer). Page 154 TMP88PS43FG EDSET (01FC3H, 01FC2H) (01FF3H, 01FF2H) F E D C B A 9 8 7 6 EDT 5 4 3 2 1 0 (Initial value: 00000000 00010000) EDTH F to C B to 0 EDTH EDT Correct period (n) Set period (m) 0 to 15 times ≥ 010H R/W One period of the Electrical Angle Timer, T, is expressed by the equation below. nT =  m + ----- × 384 × set clock [ s ] where m = set period, n = period correction  16 ELDEG (01FC5H, 01FC4H) (01FF5H, 01FF4H) F – E – D – C – B – A – 9 – 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: *******0 00000000) 8 to 0 ELDEG Electrical angle Set the Initially and the count values of electrical angle. R/W AMP (01FC7H, 01FC6H) (01FF7H, 01FF6H) F – E – D – C – B DB A DA 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ****0000 00000000) B to 0 AMP Set voltage Set the voltage to be used during waveform calculation. R/W EDCAP (01FC9H, 01FC8H) (01FF9H, 01FF8H) F – E – D – C – B – A – 9 – 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ******0 00000000) 8 to 0 EDCAP Captured value of electrical angle Electrical angle timer value when position is detected. R WFMDR (01FCAH) (01FFAH) 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (Initial value: ********) 7 to 0 WFMDR Sine wave data Write sine wave data to RAM of sine wave W Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the WFMDR register because this register is write only. Page 155 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG 13.6.1.2 List of PMD Related Control Registers (1) Input/output Pins and Input/output Control Registers PMD1 Input/Output Pins (P3, P4) and Port Input/Output Control Registers (P3CR, P4CR) Name Address Bit 7 P3DR 00003H 6 5 to 0 P4DR P3CR 00004H 01F89H 2 to 0 7 to 0 R or W R/W R/W R/W R/W R/W Overload protection (CL1) EMG input (EMG1) U1/V1/W1/X1/Y1/Z1 outputs. Position signal inputs (PDU1, PDV1, PDW1). P3 port input/output control (can be set bitwise). 0: Input mode 1: Output mode P0 port input/output control (can be set bitwise). 0: Input mode 1: Output mode Description P4CR 01F8AH 2, 1, 0 R/W PMD2 Input/Output Pins (P5, P1) and Port Input/Output Control Registers (P5CR, P1CR) Name Address Bit 0 P5DR 00005H 1 2 to 7 P1DR P5CR 00001H 01F8BH 5 to 7 7 to 0 R or W R/W R/W R/W R/W R/W Overload protection (CL2) EMG input (EMG2) U2/V2/W2/X2/Y2/Z2 outputs. Position signal inputs (PDU2, PDV2, PDW2). P3 port input/output control (can be set bitwise). 0: Input mode 1: Output mode P0 port input/output control (can be set bitwise). 0: Input mode 1: Output mode Description P1CR 0000BH 5, 6, 7 R/W Note: When using these pins as PMD function or input port, set the Output Latch (P*DR) to 1. Example of the PMD Pin Port Setting Input/Output CL1 EMG1 U1 PDU1 Input Input Output Input P3DR * * 1 – P3CR 0 0 1 – P4DR – – – * P4CR – – – 0 Input/Output CL2 EMG2 U2 PDU2 Input Input Output Input P5DR * * 1 – P5CR 0 0 1 – P1DR – – – * P1CR – – – 0 Page 156 TMP88PS43FG (2) Motor Control Circuit Control Registers [Address Upper Stage: PMD1, Lower Stage: PMD2] Position Detection Control Register (PDCR) and Sampling Delay Register (SDREG) Name Address Bit 5, 4 R or W R Description Detect the position-detected position. 00: Within the current pulse 01: When PWM is off 10: Within the current pulse 11: Within the preceding pulse Monitor the sampling status. 0: Sampling idle 1: Sampling in progress Holds the status of the position signal input during unmatch detection mode. Bits 2, 1, and 0: W, V, and U phases Select the sampling input clock [Hz]. 00: fc/22 10: fc/2 4 PDCRC 01FA2H 01FD2H 3 R 2 to 0 R 7, 6 01FA1H 01FD1H R/W 01: fc/23 11: fc/25 PDCRB 5, 4 R/W Sampling mode. 00: When PWM is on 01: Regularly 10: When lower phases are turned on Detection position match counts 1 to 15. 0: No operation 1: Stop sampling in software 0: No operation 1: Start sampling in software Stop sampling using Timer 3. 0: Disable 1: Enable Start sampling using Timer 2. 0: Disable 1: Enable Number of position signal input pins. 0: Compare three pins (PDU/PDV/PDW) 1: Compare one pin (PDU) only Count occurrences of matching when PWM is on. 0: Subsequent to matching counts when PWM previously was on 1: Eecount occurrences of matching each time PWM is on Position detection mode. 0: Ordinary mode 1: Unmatch detection mode Enable/Disable position detection function. 0: Disable 1: Enable (Sampling starts) Sampling delay. 23/fc × n bits (n = 0 to 6, maximum 50.8 µs at 20 MHz). 3 to 0 7 6 R/W W W 5 R/W 4 01FA0H 01FD0H R/W PDCRA 3 R/W 2 R/W 1 R/W 0 01FA3H 01FD3H R/W SDREG 6 to 0 R/W Page 157 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG Mode Timer Control Register (MTCR), Mode Capture Register (MCAP), and Compare Registers (CMP1, CMP2, CMP3) Name Address Bit 7 R or W R/W Description Debug output. 0: Disable 1: Enable (P67 for PMD1, P77 for PMD2) Mode timer overflow. 0: No overflow 1: Overflowed occurred Capture mode timer by overload protection. 0: Disable 1: Enable Capture mode timer by software. 0: No operation 1: Capture Capture mode timer by position detection. 0: Disable 1: Enable Select clock for mode timer [Hz]. 000: fc/23 (400 ns at 20 MHz) 010: fc/24 (800 ns at 20 MHz) 100: fc/25 (1.6 µs at 20 MHz) 7, 6, 5 R/W 110: fc/26 (3.2 µs at 20 MHz) 001: fc/27 (6.4 µs at 20 MHz) 011: Reserved 101: Reserved 111: Reserved 4 MTCRA 01FA4H 01FD4H 3 R/W R/W Reset timer by Timer 3. 0: Disable 1: Enable Reset timer by overload protection. 0: Disable 1: Enable Reset timer by software. 0: No operation 1: Reset Reset timer by position detection. 0: Disable 1: Enable Enable/Disable mode timer. 0: Disable 1: Enable (timer starts) Mode capture register. Compare Register 1. Compare Register 2. Compare Register 3. 5 R MTCRB 01FA5H 01FD5H 3 R/W 2 W 1 R/W 2 W 1 R/W 0 01FA7H, 01FA6H 01FD7H, 01FD6H 01FA9H, 01FA8H 01FD9H, 01FD8H 01FABH, 01FAAH 01FDBH, 01FDAH 01FADH, 01FACH 01FDDH, 01FDCH R/W MCAP CMP1 CMP2 CMP3 F to 0 F to 0 F to 0 F to 0 R R/W R/W R/W Page 158 TMP88PS43FG PMD Control Register (MDCR), Dead Time Register (DTR), and PMD Output Register (MDOUT) Name Address 01FAFH 01FDFH Bit R or W Description Select clock for PWM counter. 1, 0 R/W 00: fc/2 (100 ns at 20 MHz) 10: fc/2 (400 ns at 20 MHz) 7 R/W 3 MDCRB 01: fc/22 (200 ns at 20 MHz) 11: fc/24 (800 ns at 20 MHz) Select half-period interrupt 0: Interrupt every period as specified in PINT. 1: Interrupt every half-period only PINT=00. DUTY mode. 0: U phase in common 1: Three phases independent Upper-phase port polarity. 0: Active low 1: Active high Lower-phase port polarity. 0: Active low 1: Active high Select PWM interrupt (trigger). 00: Interrupt once every period 01: Interrupt once 2 periods 10: Interrupt once 4 periods 11: Interrupt once 8 periods PWM mode. 0: PWM mode0 (edge: sawtooth wave) 1: PWM mode1 (center: triangular wave) Enable/disable waveform synthesis function. 0: Disable 1: Enable (waveform output) Set dead time. 23/fc × 6bit (maximum 25.2 µs at 20 MHz). 0: Count up 1: Count down Comparison register for position detection. 6: W 5: V 4: U Select PWM synchronization. 0: Asynchronous with PWM period 1: Synchronized W-phase PWM output. 0: H/L level output 1: PWM waveform output V-phase PWM output. 0: H/L level output 1: PWM waveform output U-phase PWM output. 0: H/L level output 1: PWM waveform output Select port output synchronizing signal. 00: Asynchronous 01: Synchronized to position detection 10: Synchronized to Timer 1 11: Synchronized to Timer 2 Control W-phase output Control V-phase output Control U-phase output 6 R/W 5 R/W MDCRA 01FAEH 01FDEH 4 R/W 3, 2 R/W 1 R/W 0 01FBEH 01FEEH R/W DTR 5 to 0 F R/W R E, D, C R/W B R/W A R/W MDOUT 01FB3H, 01FB2H 01FE3H, 01FE2H 9 R/W 8 R/W 7, 6 R/W 5, 4 3, 2 1, 0 R/W R/W R/W Page 159 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG PWM Counter (MDCNT), PMD Period Register (MDPRD), and PMD Compare Registers (CMPU, CMPV, CMPW) Name MDCNT MDPRD CMPU CMPV CMPW Address 01FB5H, 01FB4H 01FE5H, 01FE4H 01FB7H, 01FB6H 01FE7H, 01FE6H 01FB9H, 01FB8H 01FE9H, 01FE8H 01FBBH, 01FBAH 01FEBH, 01FEAH 01FBDH, 01FBCH 01FEDH, 01FECH Bit B to 0 B to 0 B to 0 B to 0 B to 0 R or W R R/W R/W R/W R/W Description Read the PWM period counter value. PWM period MDPRD ≥ 010H. Set U-phase PWM duty cycle. Set V-phase PWM duty cycle. Set W-phase PWM duty cycle. EMG Disable Code Register (EMGREL) and EMG Control Register (EMGCR) Name EMGREL Address 01FBFH 01FEFH Bit 7 to 0 R or W W Description Code input for disable EMG protection circuit. Can be disable by writing 5AH and then A5H. Return from overload protective state. 0: No operation 1: Return from protective state Condition for returning from overload protective state: Synchronized to PWM. 0: Disable 1: Enable Enable/Disable return from overload protective state by timer 1. 0: Disable 1: Enable Overload protective state. 0: No operation 1: Under protection Select output disabled phases during overload protection. 00: No phases disabled against output 01: All phases disabled against output 10: PWM phases disabled against output 11: All upper/All lower phases disabled against output Stop PWM counter (MDCNT) during overload protection. 0: Do not stop 1: Stop Enable/Disable overload protective circuit. 0: Disable 1: Enable Overload protection sampling time. 22/fc × n (n = 1 to 15, at 20 MHz) EMG protective state. 0: No operation 1: Under protection Return from EMG protective state. 0: No operation 1: Return from protective state Enable/Disable fanction of the EMG protective circuit. 0: Disable 1: Enable (This circuit initially is enabled (= 1). To disable this circuit, make sure key code 5AH and A5H are written to the EMGREL1 Register beforehand.) 7 W 6 R/W 5 R/W EMGCRB 01FB1H 01FE1H 4 R 3, 2 R/W 1 R/W 0 R/W 7 to 4 R/W 2 R EMGCRA 01FB0H 01FE0H 1 W 0 R/W Page 160 TMP88PS43FG Electrical Angle Control Register (EDCR), Electrical Angle Period Register (EDSET), Electrical Angle Set Register (ELDEG), Voltage Set Register (AMP), and Electrical Angle Capture Register (EDCAP). Name Address Bit 3 2 1 0 7 6 R or W W R R/W R/W R/W R/W 0: No operation 1: Start calculation 0: Waveform Arithmetic Circuit stopped 1: Waveform Arithmetic Circuit calculatin 0: Start calculation insync with electrical angle 1: Do not calculation insync with electrical angle 0: Interrupt when the Electrical Angle Timer finishes counting 1: Interrupt upon end of calculation 0: Count up 1: Count down 0: V = U + 120°, W = U + 240° 1: V = U − 120°, W = U − 240° Select clock. 5, 4 R/W 00: fc/23 10: fc/2 3 R/W 5 Description EDCRB 01FC1H 01FF1H 01: fc/24 11: fc/26 EDCRA 01FC0H 01FF0H Switch between 2/3-phase modulations. 0: Two-phase modulation 1: Three-phase modulation Transfer calculation result to CMP registers. 0: Disable 1: Enable Enable/disable waveform calculation function. 0: Disable 1: Enable Electrical angle timer. 0: Disable 1: Enable Correct period (n) 0 to 15 times. Set period (1/m counter) ≥ 010H Initially set and count values of electrical angle. Set voltage used during waveform calculation. Electrical angle timer value when position is detected. Set sine wave data. 2 R/W 1 R/W 0 F to C B to 0 8 to 0 B to 0 8 to 0 7 to 0 R/W R/W R/W R/W R/W R W EDSET 01FC3H, 01FC2H 01FF3H, 01FF2H 01FC5H, 01FC4H 01FF5H, 01FF4H 01FC7H, 01FC6H 01FF7H, 01FF6H 01FC9H, 01FC8H 01FF9H, 01FF8H 01FCAH 01FFAH ELDEG AMP EDCAP WFMDR Page 161 13. Motor Control Circuit (PMD: Programmable motor driver) TMP88PS43FG Page 162 TMP88PS43FG 14. Asynchronous Serial interface (UART) The TMP88PS43FG has a asynchronous serial interface (UART) . It can connect the peripheral circuits through TXD and RXD pin. TXD and RXD pin are also used as the general port. For TXD pin, the corresponding general port should be set output mode (Set its output control register to "1" after its output port latch to "1"). For RXD pin, should be set input mode. The asynchronous serial interface (UART) can select the connection pin with the peripheral circuits. RXD1 and TXD1 are correspond to P44 and P45 pins, RXD2 and TXD2 are to P00 and P01 pins. But the synchronous serial interface (SIO) also use P44 and P45 pins, therefore these P44 and P45 are not available for UART when SIO is on working. 14.1 Configuration UART control register 1 UARTCRA Transmit data buffer TDBUF Receive data buffer RDBUF 3 2 Receive control circuit Transmit control circuit 2 Shift register Shift register Parity bit Stop bit Noise rejection circuit M P X M P X INTTXD RXD1 RXD2 TXD1 TXD2 INTRXD IrDA control Transmit/receive clock IRDACR IrDA output control register Y S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC4 fc/96 A B C D E F G H M P X A B C S 2 fc/26 7 fc/2 fc/28 2 Y Counter UARTSR 4 UARTCRB UARTSEL UART pin select register MPX: Multiplexer UART status register Baud rate generator UART control register 2 Figure 14-1 UART (Asynchronous Serial Interface) Page 163 14. Asynchronous Serial interface (UART) 14.2 Control TMP88PS43FG 14.2 Control UART is controlled by the UART Control Registers (UARTCRA, UARTCRB). The operating status can be monitored using the UART status register (UARTSR). TXD pin and RXD pin can be selected a port assignment by UART Pin Select Register (UARTSEL). UART Control Register1 UARTCRA (01F91H) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE RXE STBT EVEN PE Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 Input INTTC4 fc/96 Write only BRG Transmit clock select Note 1: When operations are disabled by setting UARTCRA bits to “0”, the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UARTCRA and UARTCRA should be set to “0” before UARTCRA is changed. Note 4: In case fc = 20MHz, the timer counter 4 (TC4) is available as a baud rate generator. UART Control Register2 UARTCRB (01F92H) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UARTCRB = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCRB = “10”, longer than 192/fc [s]; and when UARTCRB = “11”, longer than 384/fc [s]. Page 164 TMP88PS43FG UART Status Register UARTSR (01F91H) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR FERR OERR RBFL TEND TBEP Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty Read only Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART Receive Data Buffer RDBUF (01F93H) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART Transmit Data Buffer TDBUF (01F93H) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) UART Pin Select Register UARTSEL (01F90H) 7 6 5 4 3 2 1 TXD SEL 0 RXD SEL (Initial value: **** **00) RXDSEL TXDSEL RXD connect pin select TXD connect pin select 0: 1: 0: 1: RXD1 RXD2 TXD1 TXD2 R/W Note 1: Do not change UARTSEL register during UART operation. Note 2: Set UARTSEL register before performing the setting terminal of a I/O port when changing a terminal. Page 165 14. Asynchronous Serial interface (UART) 14.3 Transfer Data Format TMP88PS43FG 14.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCRA), and parity (Select parity in UARTCRA; even- or odd-numbered parity by UARTCRA) are added to the transfer data. The transfer data formats are shown as follows. PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 14-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 14-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 14-3 sequence except for the initial setting. Page 166 TMP88PS43FG 14.4 Transfer Rate The baud rate of UART is set of UARTCRA. The example of the baud rate are shown as follows. Table 14-1 Transfer Rate (Example) Source Clock BRG 16 MHz 000 001 010 011 100 101 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 When INTTC4 is used as the UART transfer rate (when UARTCRA = “110”), the transfer clock and transfer rate are determined as follows: Transfer clock [Hz] = TC4 source clock [Hz] / TC4DR setting value Transfer Rate [baud] = Transfer clock [Hz] / 16 14.5 Data Sampling Method The UART receiver keeps sampling input using the clock selected by UARTCRA until a start bit is detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority rule (The data are the same twice or more out of three samplings). RXD pin Start bit RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (a) Without noise rejection circuit Bit 0 RXD pin Start bit RT0 1 2 3 4 5 6 7 8 Bit 0 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (b) With noise rejection circuit Bit 0 Figure 14-4 Data Sampling Method Page 167 14. Asynchronous Serial interface (UART) 14.6 STOP Bit Length TMP88PS43FG 14.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCRA. 14.7 Parity Set parity / no parity by UARTCRA and set parity type (Odd- or Even-numbered) by UARTCRA. 14.8 Transmit/Receive Operation 14.8.1 Data Transmit Operation Set UARTCRA to “1”. Read UARTSR to check UARTSR = “1”, then write data in TDBUF (Transmit data buffer). Writing data in TDBUF zero-clears UARTSR, transfers the data to the transmit shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit, stop bits whose number is specified in UARTCRA and a parity bit if parity addition is specified. Select the data transfer baud rate using UARTCRA. When data transmit starts, transmit buffer empty flag UARTSR is set to “1” and an INTTXD interrupt is generated. While UARTCRA = “0” and from when “1” is written to UARTCRA to when send data are written to TDBUF, the TXD pin is fixed at high level. When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR is not zero-cleared and transmit does not start. 14.8.2 Data Receive Operation Set UARTCRA to “1”. When data are received via the RXD pin, the receive data are transferred to RDBUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to RDBUF (Receive data buffer). Then the receive buffer full flag UARTSR is set and an INTRXD interrupt is generated. Select the data transfer baud rate using UARTCRA. If an overrun error (OERR) occurs when data are received, the data are not transferred to RDBUF (Receive data buffer) but discarded; data in the RDBUF are not affected. Note:When a receive operation is disabled by setting UARTCRA bit to “0”, the setting becomes valid when data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting may not become valid. If a framing error occurs, be sure to perform a re-receive operation. Page 168 TMP88PS43FG 14.9 Status Flag 14.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR is set to “1”. The UARTSR is cleared to “0” when the RDBUF is read after reading the UARTSR. RXD pin Parity Stop Shift register UARTSR xxxx0** pxxxx0* 1pxxxx0 After reading UARTSR then RDBUF clears PERR. INTRXD interrupt Figure 14-5 Generation of Parity Error 14.9.2 Framing Error When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR is set to “1”. The UARTSR is cleared to “0” when the RDBUF is read after reading the UARTSR. RXD pin Final bit Stop Shift register UARTSR xxx0** xxxx0* 0xxxx0 After reading UARTSR then RDBUF clears FERR. INTRXD interrupt Figure 14-6 Generation of Framing Error 14.9.3 Overrun Error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected. The UARTSR is cleared to “0” when the RDBUF is read after reading the UARTSR. Page 169 14. Asynchronous Serial interface (UART) 14.9 Status Flag TMP88PS43FG UARTSR RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 UARTSR After reading UARTSR then RDBUF clears OERR. INTRXD interrupt Figure 14-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UARTSR is cleared. 14.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full flag UARTSR to "1". The UARTSR is cleared to “0” when the RDBUF is read after reading the UARTSR. RXD pin Final bit Stop Shift register RDBUF xxx0** yyyy xxxx0* 1xxxx0 xxxx After reading UARTSR then RDBUF clears RBFL. UARTSR INTRXD interrupt Figure 14-8 Generation of Receive Data Buffer Full Note:If the overrun error flag UARTSR is set during the period between reading the UARTSR and reading the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the UARTSR again to check whether or not the overrun error flag which should have been cleared still remains set. 14.9.5 Transmit Data Buffer Empty When no data is in the transmit buffer TDBUF, that is, when data in TDBUF are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag UARTSR is set to “1”. The UARTSR is cleared to “0” when the TDBUF is written after reading the UARTSR. Page 170 TMP88PS43FG Data write TDBUF Data write xxxx yyyy zzzz Shift register TXD pin *****1 1xxxx0 *1xxxx Bit 0 ****1x Final bit *****1 Stop 1yyyy0 Start UARTSR After reading UARTSR writing TDBUF clears TBEP. INTTXD interrupt Figure 14-9 Generation of Transmit Data Buffer Empty 14.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR = “1”), transmit end flag UARTSR is set to “1”. The UARTSR is cleared to “0” when the data transmit is stated after writing the TDBUF. Shift register TXD pin ***1xx ****1x *****1 1yyyy0 *1yyyy Stop Data write for TDBUF Start Bit 0 UARTSR UARTSR INTTXD interrupt Figure 14-10 Generation of Transmit End Flag and Transmit Data Buffer Empty Page 171 14. Asynchronous Serial interface (UART) 14.9 Status Flag TMP88PS43FG Page 172 TMP88PS43FG 15. Synchronous Serial Interface (SIO) The TMP88PS43FG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO, SI, SCK port. 15.1 Configuration SIO control / status register SIOSR SIOCR1 SIOCR2 CPU Control circuit Buffer control circuit Shift register Shift clock Transmit and receive data buffer (8 bytes in DBR) 7 6 5 4 3 2 1 0 SO Serial data output 8-bit transfer 4-bit transfer SI Serial data input INTSIO interrupt request Serial clock SCK Serial clock I/O Figure 15-1 Serial Interface Page 173 15. Synchronous Serial Interface (SIO) 15.2 Control TMP88PS43FG 15.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2. The data buffer is assigned to address 01F98H to 01F9FH for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in the receive mode or transmit/receive mode) interrupt (INTSIO) is generated. When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be selected with SIOCR2. SIO Control Register 1 SIOCR1 (1F96H) 7 SIOS 6 SIOINH 5 4 SIOM 3 2 1 SCK 0 (Initial value: 0000 0000) SIOS Indicate transfer start / stop 0: 1: 0: 1: 000: 010: Stop Start Continuously transfer Abort transfer (Automatically cleared after abort) 8-bit transmit mode 4-bit transmit mode 8-bit transmit / receive mode 8-bit receive mode 4-bit receive mode Except the above: Reserved NORMAL, IDLE mode DV1CK = 0 000 001 010 fc/2 13 SIOINH Continue / abort transfer Write only SIOM Transfer mode select 100: 101: 110: DV1CK = 0 fc/214 fc/29 fc/28 fc/27 fc/26 fc/25 Reserved Write only fc/28 fc/27 fc/26 fc/25 fc/24 SCK Serial clock select 011 100 101 110 111 External clock (Input from SCK pin) Note 1: fc; High-frequency clock [Hz] Note 2: Set SIOCR1 to "0" and SIOCR1 to "1" when setting the transfer mode or serial clock. Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Control Register 2 SIOCR2 (1F97H) 7 6 5 4 WAIT 3 2 1 BUF 0 (Initial value: ***0 0000) Page 174 TMP88PS43FG Always sets "00" except 8-bit transmit / receive mode. 00: WAIT Wait control 01: 10: 11: 000: 001: 010: BUF Number of transfer words (Buffer address in use) 011: 100: 101: 110: 111: Tf = TD(Non wait) Tf = 2TD(Wait) Tf = 4TD(Wait) Tf = 8TD (Wait) 1 word transfer 2 words transfer 3 words transfer 4 words transfer 5 words transfer 6 words transfer 7 words transfer 8 words transfer 01F98H 01F98H ~ 01F99H 01F98H ~ 01F9AH 01F98H ~ 01F9BH 01F98H ~ 01F9CH 01F98H ~ 01F9DH 01F98H ~ 01F9EH 01F98H ~ 01F9FH Write only Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. ( The first buffer address transmitted is 01F98H ). Note 3: The value to be loaded to BUF is held after transfer is completed. Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0). Note 5: *: Don't care Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. Note 7: Tf; Frame time, TD; Data transfer time (output) SCK output TD Tf Figure 15-2 Frame time (Tf) and Data transfer time (TD) SIO Status Register SIOSR (1F97H) 7 SIOF 6 SEF 5 4 3 2 1 0 (Initial value: 00** ****) SIOF SEF Serial transfer operating status monitor Shift operating status monitor 0: 1: 0: 1: Transfer terminated Transfer in process Shift operation terminated Shift operation in process Read only Note 1: After SIOCR1 is cleared to "0", SIOSR is cleared to "0" at the termination of transfer or the setting of SIOCR1 to "1". 15.3 Serial clock 15.3.1 Clock source Internal clock or external clock for the source clock is selected by SIOCR1. Page 175 15. Synchronous Serial Interface (SIO) 15.3 Serial clock TMP88PS43FG 15.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. Table 15-1 Serial Clock Rate NORMAL, IDLE mode SCK 000 001 010 011 100 101 110 111 Clock fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 External Baud Rate 2.44 Kbps 78.13 Kbps 156.25 Kbps 312.50 Kbps 625.00 Kbps 125.00 Kbps External Note: 1 Kbit = 1024 bit (fc = 20 MHz) Automatically wait function SCK pin (output) SO pin (output) Written transmit data a a0 a1 a2 a3 b b0 b1 c b2 b3 c0 c1 Figure 15-3 Automatic Wait Function (at 4-bit transmit mode) 15.3.1.2 External clock An external clock connected to the SCK pin is used as the serial clock. In this case, the SCK (P43) port should be set to input mode. To ensure shifting, a pulse width of more than 24/fc is required. This pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. SCK pin (Input) tSCKL tSCKH tSCKL, tSCKH > 24/fc Figure 15-4 External clock pulse width Page 176 TMP88PS43FG 15.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 15.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/ output). 15.3.2.2 Trailing edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SCK pin SO pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register 3210 *321 **32 ***3 (a) Leading edge SCK pin SI pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register **** 0*** 10** 210* 3210 *; Don’t care (b) Trailing edge Figure 15-5 Shift edge 15.4 Number of bits to transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving. The data is transferred in sequence starting at the least significant bit (LSB). 15.5 Number of words to transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2. An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of words is to be changed during transfer, the serial interface must be stopped before making the change. The number of words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not required to be stopped. Page 177 15. Synchronous Serial Interface (SIO) 15.6 Transfer Mode TMP88PS43FG SCK pin SO pin a0 a1 a2 a3 INTSIO interrupt (a) 1 word transmit SCK pin SO pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (b) 3 words transmit SCK pin SI pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (c) 3 words receive Figure 15-6 Number of words to transfer (Example: 1word = 4bit) 15.6 Transfer Mode SIOCR1 is used to select the transmit, receive, or transmit/receive mode. 15.6.1 4-bit and 8-bit transfer modes In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data (number of transfer words to be transferred) to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOCR1 to “1”. The data are then output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit (LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (Buffer empty) interrupt is generated to request the next transmitted data. When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer register by the time the number of data words specified with the SIOCR2 has been transmitted. Writing even one word of data cancels the automatic-wait; therefore, when transmitting two or more words, always write the next word before transmission of the previous word is completed. Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words. When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. The transmission is ended by clearing SIOCR1 to “0” or setting SIOCR1 to “1” in buffer empty interrupt service program. Page 178 TMP88PS43FG SIOCR1 is cleared, the operation will end after all bits of words are transmitted. That the transmission has ended can be determined from the status of SIOSR because SIOSR is cleared to “0” when a transfer is completed. When SIOCR1 is set, the transmission is immediately ended and SIOSR is cleared to “0”. When an external clock is used, it is also necessary to clear SIOCR1 to “0” before shifting the next data; If SIOCR1 is not cleared before shift out, dummy data will be transmitted and the operation will end. If it is necessary to change the number of words, SIOCR1 should be cleared to “0”, then SIOCR2 must be rewritten after confirming that SIOSR has been cleared to “0”. Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Output) SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO interrupt DBR a Write Write (a) (b) b Figure 15-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock) Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Input) SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO interrupt DBR a Write Write (a) (b) b Figure 15-8 Transfer Mode (Example: 8bit, 1word transfer, External clock) Page 179 15. Synchronous Serial Interface (SIO) 15.6 Transfer Mode TMP88PS43FG SCK pin SIOSR SO pin MSB of last word tSODH = min 3.5/fc [s] (In the NORMAL, IDLE modes) Figure 15-9 Transmiiied Data Hold Time at End of Transfer 15.6.2 4-bit and 8-bit receive modes After setting the control registers to the receive mode, set SIOCR1 to “1” to enable receiving. The data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the number of words specified with the SIOCR2 has been received, an INTSIO (Buffer full) interrupt is generated to request that these data be read out. The data are then read from the data buffer registers by the interrupt service program. When the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read. A wait will not be initiated if even one data word has been read. Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer register. If the previous data have not been read, the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read. The receiving is ended by clearing SIOCR1 to “0” or setting SIOCR1 to “1” in buffer full interrupt service program. When SIOCR1 is cleared, the current data are transferred to the buffer. After SIOCR1 cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has ended can be determined from the status of SIOSR. SIOSR is cleared to “0” when the receiving is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1 is set, the receiving is immediately ended and SIOSR is cleared to “0”. (The received data is ignored, and it is not required to be read out.) If it is necessary to change the number of words in external clock operation, SIOCR1 should be cleared to “0” then SIOCR2 must be rewritten after confirming that SIOSR has been cleared to “0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data receiving, SIOCR2 must be rewritten before the received data is read out. Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOCR1 to “0”, read the last data and then switch the transfer mode. Page 180 TMP88PS43FG Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Output) SI pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO Interrupt DBR a Read out b Read out Figure 15-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock) 15.6.3 8-bit transfer / receive mode After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1 to “1”. When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving, the data are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when the number of data words specified with the SIOCR2 has been transferred. Usually, read the receive data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted after reading the all received data. When the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. A wait will not be initiated if even one transfer data word has been written. When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written. The transmit/receive operation is ended by clearing SIOCR1 to “0” or setting SIOCR1 to “1” in INTSIO interrupt service program. When SIOCR1 is cleared, the current data are transferred to the buffer. After SIOCR1 cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted. That the transmitting/receiving has ended can be determined from the status of SIOSR. SIOSR is cleared to “0” when the transmitting/receiving is ended. When SIOCR1 is set, the transmit/receive operation is immediately ended and SIOSR is cleared to “0”. If it is necessary to change the number of words in external clock operation, SIOCR1 should be cleared to “0”, then SIOCR2 must be rewritten after confirming that SIOSR has been cleared to “0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/receive operation, SIOCR2 must be rewritten before reading and writing of the receive/transmit data. Page 181 15. Synchronous Serial Interface (SIO) 15.6 Transfer Mode TMP88PS43FG Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOCR1 to “0”, read the last data and then switch the transfer mode. Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (output) SO pin a0 c0 a1 c1 a2 c2 a3 c3 a4 c4 a5 c5 a6 c6 a7 c7 b0 d0 b1 d1 b2 d2 b3 d3 b4 d4 b5 d5 b6 d6 b7 d7 SI pin INTSIO interrupt DBR a Write (a) Read out (c) c b Write (b) d Read out (d) Figure 15-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock) SCK pin SIOSR SO pin Bit 6 Bit 7 of last word tSODH = min 4/fc [s] (In the NORMAL, IDLE modes) Figure 15-12 Transmitted Data Hold Time at End of Transfer / Receive Page 182 TMP88PS43FG 16. 10-bit AD Converter (ADC) The TMP88PS43FG have a 10-bit successive approximation type AD converter. 16.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 16-1. It consists of control register ADCCRA and ADCCRB, converted value register ADCDRH and ADCDRL, a DA converter, a sample-hold circuit, a comparator, and a successive comparison circuit. DA converter VAREF AVSS R/2 AVDD R Reference voltage R/2 Analog input multiplexer AIN0 Sample hold circuit A Y 10 Analog comparator AIN15 n S EN IREFON 4 SAIN ADRS AINDS Successive approximate circuit Shift clock Control circuit 2 AMD 3 ACK ADCCRB 8 ADCDRH 2 INTADC EOCF ADBF ADCCRA ADCDRL AD converter control register 1, 2 AD conversion result register 1, 2 Note: Before using AD converter, set appropriate value to I/O port register conbining a analog input port. For details, see the section on "I/O ports". Figure 16-1 10-bit AD Converter Page 183 16. 10-bit AD Converter (ADC) 16.2 Register configuration TMP88PS43FG 16.2 Register configuration The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCRA) This register selects the analog channels and operation mode (Software start or repeat) in which to perform AD conversion and controls the AD converter as it starts operating. 2. AD converter control register 2 (ADCCRB) This register selects the AD conversion time and controls the connection of the DA converter (Ladder resistor network). 3. AD converted value register 1 (ADCDRH) This register used to store the digital value after being converted by the AD converter. 4. AD converted value register 2 (ADCDRL) This register monitors the operating status of the AD converter. AD Converter Control Register 1 ADCCRA (0026H) 7 ADRS 6 AMD 5 4 AINDS 3 2 SAIN 1 0 (Initial value: 0001 0000) ADRS AD conversion start 0: 1: 00: 01: 10: 11: 0: 1: 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: AD conversion start AD operation disable Software start mode Reserved Repeat mode Analog input enable Analog input disable AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AMD AD operating mode AINDS Analog input control R/W SAIN Analog input channel select Note 1: Select analog input channel during AD converter stops (ADCDRL = "0"). Note 2: When the analog input channel is all use disabling, the ADCCRA should be set to "1". Note 3: During conversion, Do not perform port output instruction to maintain a precision for all of the pins because analog input port use as general input port. And for port near to analog input, Do not input intense signaling of change. Note 4: The ADCCRA is automatically cleared to "0" after starting conversion. Note 5: Do not set ADCCRA newly again during AD conversion. Before setting ADCCRA newly again, check ADCDRL to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine). Note 6: After STOP mode is started, AD converter control register1 (ADCCRA) is all initialized and no data can be written in this register. Therfore, to use AD converter again, set the ADCCRA newly after returning to NORMAL mode. Note 7: After RESET, ADCCRA is initialized Reserved setting. Therfore, set the appropriate analog input channel to ADCCRA when use AD converter. Note 8: After ADCCRA is set to 00H, AD conversion can not be started for four cycles. Thus, four NOPs must be inserted before setting the ADCCRA. Page 184 TMP88PS43FG AD Converter Control Register 2 ADCCRB (0027H) 7 6 5 IREFON 4 "1" 3 2 ACK 1 0 "0" (Initial value: **0* 000*) IREFON DA converter (Ladder resistor) connection control 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Connected only during AD conversion Always connected 39/fc Reserved 78/fc 156/fc 312/fc 624/fc 1248/fc Reserved ACK AD conversion time select (Refer to the following table about the conversion time) R/W Note 1: Always set bit0 in ADCCRB to "0" and set bit4 in ADCCRB to "1". Note 2: When a read instruction for ADCCRB, bit6 to 7 in ADCCRB read in as undefined data. Note 3: After STOP mode is started, AD converter control register2 (ADCCRB) is all initialized and no data can be written in this register. Therfore, to use AD converter again, set the ADCCRB newly after returning to NORMAL mode. Table 16-1 ACK setting and Conversion time (at CGCR="0") Condition ACK 000 001 010 011 100 101 110 111 78/fc 156/fc 312/fc 624/fc 1248/fc 15.6 µs 31.2 µs 62.4 µs Conversion time 39/fc 20 MHz Reserved 19.5 µs 39.0 µs 78.0 µs 19.5 µs 39.0 µs 78.0 µs 156.0 µs 16 MHz 8 MHz - Reserved Table 16-2 ACK setting and Conversion time (at CGCR="1") Condition ACK 000 001 010 011 100 101 110 111 78/fc 156/fc 312/fc 624/fc 1248/fc 15.6 µs 31.2 µs 62.4 µs Conversion time 39/fc 20 MHz Reserved 19.5 µs 39.0 µs 78.0 µs 19.5 µs 39.0 µs 78.0 µs 156.0 µs 16 MHz 8 MHz - Reserved Note 1: Setting for "−" in the above table are inhibited. fc: High Frequency oscillation clock [Hz] Note 2: Set conversion time setting should be kept more than the following time by Analog reference voltage (VAREF). VAREF = 4.5 to 5.5 V 15.6 µs and more Page 185 16. 10-bit AD Converter (ADC) 16.2 Register configuration TMP88PS43FG AD Converted value Register 1 ADCDRH (0029H) 7 AD09 6 AD08 5 AD07 4 AD06 3 AD05 2 AD04 1 AD03 0 AD02 (Initial value: 0000 0000) AD Converted value Register 2 ADCDRL (0028H) 7 AD01 6 AD00 5 EOCF 4 ADBF 3 2 1 0 (Initial value: 0000 ****) EOCF ADBF AD conversion end flag AD conversion BUSY flag 0: 1: 0: 1: Before or during conversion Conversion completed During stop of AD conversion During AD conversion Read only Note 1: The ADCDRL is cleared to "0" when reading the ADCDRH. Therfore, the AD conversion result should be read to ADCDRL more first than ADCDRH. Note 2: The ADCDRL is set to "1" when AD conversion starts, and cleared to "0" when AD conversion finished. It also is cleared upon entering STOP mode. Note 3: If a read instruction is executed for ADCDRL, read data of bit3 to bit0 are unstable. Page 186 TMP88PS43FG 16.3 Function 16.3.1 Software Start Mode After setting ADCCRA to “01” (software start mode), set ADCCRA to “1”. AD conversion of the voltage at the analog input pin specified by ADCCRA is thereby started. After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDRH, ADCDRL) and at the same time ADCDRL is set to 1, the AD conversion finished interrupt (INTADC) is generated. ADRS is automatically cleared after AD conversion has started. Do not set ADCCRA newly again (Restart) during AD conversion. Before setting ADCCRA newly again, check ADCDRL to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine). AD conversion start ADCCRA AD conversion start ADCDRL ADCDRH status Indeterminate 1st conversion result 2nd conversion result EOCF cleared by reading conversion result ADCDRL INTADC interrupt request ADCDRH Conversion result read Conversion result read Conversion result read Conversion result read ADCDRL Figure 16-2 Software Start Mode 16.3.2 Repeat Mode AD conversion of the voltage at the analog input pin specified by ADCCRA is performed repeatedly. In this mode, AD conversion is started by setting ADCCRA to “1” after setting ADCCRA to “11” (Repeat mode). After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDRH, ADCDRL) and at the same time ADCDRL is set to 1, the AD conversion finished interrupt (INTADC) is generated. In repeat mode, each time one AD conversion is completed, the next AD conversion is started. To stop AD conversion, set ADCCRA to “00” (Disable mode) by writing 0s. The AD convert operation is stopped immediately. The converted value at this time is not stored in the AD converted value register. Page 187 16. 10-bit AD Converter (ADC) 16.3 Function TMP88PS43FG ADCCRA AD conversion start ADCCRA “11” “00” Conversion operation 1st conversion result 2nd conversion result 3rd conversion result AD convert operation suspended. Conversion result is not stored. 3rd conversion result ADCDRH,ADCDRL Indeterminate 1st conversion result 2nd conversion result ADCDRL EOCF cleared by reading conversion result INTADC interrupt request ADCDRH ADCDRL Conversion result read Conversion result read Conversion result read Conversion result read Conversion result read Conversion result read Figure 16-3 Repeat Mode 16.3.3 Register Setting 1. Set up the AD converter control register 1 (ADCCRA) as follows: • Choose the channel to AD convert using AD input channel select (SAIN). • Specify analog input enable for analog input control (AINDS). • Specify AMD for the AD converter control operation mode (software or repeat mode). 2. Set up the AD converter control register 2 (ADCCRB) as follows: • Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Figure 16-1, Figure 16-2 and AD converter control register 2. • Choose IREFON for DA converter control. 3. After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1 (ADCCRA) to “1”. If software start mode has been selected, AD conversion starts immediately. 4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD converted value register 1 (ADCDRH) and the AD conversion finished flag (EOCF) of AD converted value register 2 (ADCDRL) is set to “1”, upon which time AD conversion interrupt INTADC is generated. 5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register read, although EOCF is cleared the previous conversion result is retained until the next conversion is completed. Page 188 TMP88PS43FG Example :After selecting the conversion time 15.6 µs at 20 MHz and the analog input channel AIN4 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH and store the upper 8 bits in address 0009FH in RAM. The operation mode is software start mode. : (port setting) : LD LD : : (ADCCRA) , 00100100B (ADCCRB) , 00011000B ;Set port register approrriately before setting AD converter registers. (Refer to section I/O port in details) ; Select Software start mode, Analog input enable, and AIN4 ;Select conversion time(312/fc) and operation mode SET SLOOP : TEST JRS (ADCCRA) . 7 (ADCDRB) . 5 T, SLOOP ; ADRS = 1(AD conversion start) ; EOCF= 1 ? LD LD LD LD A , (ADCDRL) (9EH) , A A , (ADCDRH) (9FH), A ; Read result data ; Read result data 16.4 STOP mode during AD Conversion When standby mode (STOP mode) is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized (ADCCRA and ADCCRB are initialized to initial value). Also, the conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (STOP mode).) When restored from standby mode (STOP mode), AD conversion is not automatically restarted, so it is necessary to restart AD conversion. Note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. Page 189 16. 10-bit AD Converter (ADC) 16.5 Analog Input Voltage and AD Conversion Result TMP88PS43FG 16.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 16-4. 3FFH 3FEH 3FDH AD conversion result 03H 02H 01H VAREF AVSS 0 1 2 3 1021 1022 1023 1024 Analog input voltage 1024 Figure 16-4 Analog Input Voltage and AD Conversion Result (Typ.) Page 190 TMP88PS43FG 16.6 Precautions about AD Converter 16.6.1 Analog input pin voltage range Make sure the analog input pins (AIN0 to AIN15) are used at voltages within VAREF to AVSS. If any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. The other analog input pins also are affected by that. 16.6.2 Analog input shared pins The analog input pins (AIN0 to AIN15) are shared with input/output ports. When using any of the analog inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other pins may also be affected by noise arising from input/output to and from adjacent pins. 16.6.3 Noise Countermeasure The internal equivalent circuit of the analog input pins is shown in Figure 16-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor external to the chip. Internal resistance AINi Permissible signal source impedance 5 kΩ (max) 5 kΩ (typ) Analog comparator Internal capacitance C = 22 pF (typ.) DA converter Note) i = 15 to 0 Figure 16-5 Analog Input Equivalent Circuit and Example of Input Pin Processing Page 191 16. 10-bit AD Converter (ADC) 16.6 Precautions about AD Converter TMP88PS43FG Page 192 TMP88PS43FG 17. 8-Bit High-speed PWM (HPWM0 and HPWM1) The TMP88PS43FG contains two-channels of high-speed PWM. The high-speed PWM works in such a way that when data are written to the data registers for the respective channels, waveforms differing from each other can be output. The high-speed PWM is shared with ports, P02 (HPWM0) and P03 (HPWM1). When using these pins for highspeed PWM, set the port output latches for P02 and P03 to 1. 17.1 Configuration HPWM0 X1 fc 8-bit up counter HPE0 HPE1 PWMST Comparator Additional Pulse Generator circuit HPE1 HPE0 PWMMOD HPWMCR Hight-speed PWM control register HPWMDR0 Data register HPWMDR1 Data register HPWM0 section HPWM1 section HPWM1 Figure 17-1 High-speed PWM (HPWM0 and HPWM1) Page 193 17. 8-Bit High-speed PWM (HPWM0 and HPWM1) 17.2 Control TMP88PS43FG 17.2 Control Control Register HPWMCR (000CH) 7 HPE1 6 HPE0 5 4 3 PWMST 2 1 0 R/W (Initial value: 00** 0*00) PWMMOD PWMMOD Select PWM mode 00: Mode 0 (8 bits) 01: Mode 1 (7 bits) 10: Mode 2 (6 bits) 11: Reserved 0: STOP 1: RUN 0: Disable 1: Enable 0: Disable 1: Enable R/W PWMST HPE0 HPE1 Run/stop 8-bit up counter Control HPWM0 output Control HPWM1 output Data Register HPWMDR0 (000DH) HPWMDR1 (000EH) 7 DATA7 7 DATA7 6 DATA6 6 DATA6 5 DATA5 5 DATA5 4 DATA4 4 DATA4 3 DATA3 3 DATA3 2 DATA2 2 DATA2 1 DATA1 1 DATA1 0 DATA0 0 DATA0 R/W (Initial value: **** ****) R/W (Initial value: **** ****) Note 1: The PWM output pulse width varies with the clock duty cycle. Note 2: For the data registers, set data 10H to F0H. Note 3: When HPWMCR = 0, the internal counter is cleared and data “1” is output to the port. Note 4: Before selecting PWM mode, make sure HPWMCR = 0. Note 5: Before entering STOP mode, set HPWMCR all to 0. Note 6: If HPWMCR is altered in the middle of PWM period, the waveform may be distorted. To avoid waveform distortion, make sure HPWMCR = 0 when enabling HPWM output. 17.3 Functional Description The high-speed PWM is controlled using the Control Register (HPWMCR) and Data Registers (HPWMDR0, 1). Before writing to these registers, set the HPWMCR = 1 to make them ready for setup. When the HPWMCR is set to 0, each control register is reset, so that the high-speed PWM can be reset in software. 17.3.1 Operation modes The high-speed PWM has the following three modes of operation: • 8-bit mode: (T = 28 × clock period, f ≈ 78 kHz) • 7-bit mode: (T = 27 × clock period, f ≈ 156 kHz) • 6-bit mode: (T = 26 × clock period, f ≈ 313 kHz) Note:These values apply to the case where the source clock (X1) is 20 MHz. Use the HPWMCR to select operation mode. Note that operation mode is common to both channels, and cannot be set separately for each channel. Page 194 TMP88PS43FG 17.3.1.1 8-bit mode In 8-bit mode, it is possible to generate a pulse with 12.8 µs period and approximately 78 kHz frequency (when X1 = 20 MHz). Data register value × 50 ns 12.8 µs 7 8-bit data 0 Data register Data register value × 50 ns 12.8 µs The minimum width of the pulse is 0.8 µs (data “10”), and the maximum width of the pulse is 12.0 µs (data “F0”). Pulse width = 8-bit data × 50 ns Figure 17-2 shows a typical waveform in 8-bit mode. (The values are for X1 = 20 MHz.) Data 800 ns 12.8 µs 800 ns 12.8 µs "10h" 850 ns 850 ns "11h" 12.0 µs 12.0 µs "F0h" Figure 17-2 8-Bit Mode 17.3.1.2 7-bit mode In 7-bit mode, it is possible to generate a pulse with 6.4 µs period and approximately 156 kHz frequency (when X1 = 20 MHz). Value of 1 low-order bits × 25 ns Value of 7 high-order bits × 50 ns 6.4 µs Value of 7 high-order bits × 50 ns 6.4 µs In 7-bit mode, the period is comprised of 7 bits (period = 27 × 50 ns) and one other bit provides a 25 ns resolution (half period of the source clock (X1)). Therefore, when the one low-order bit = 1, a plus-25 ns pulse is output. The minimum width of the pulse is 0.4 µs (data “10”), and the maximum width of the pulse is 6.0 µs (data “F0”: “78” + “0”). 7 0 Data register 7 hight-order bits 1 low-order bit Pulse width = (7 high-order Bits of data × 50 ns) + (1 low-order Bit of data × 25 ns) Figure 17-3 shows a typical waveform in 7-bit mode. (The values are for X1 = 20 MHz.) Page 195 17. 8-Bit High-speed PWM (HPWM0 and HPWM1) 17.3 Functional Description TMP88PS43FG Data 400 ns 6.4 µs 400 ns 6.4 µs "10h" 425 ns 425 ns "11h" 6.000 µs 6.000 µs "F0h" Figure 17-3 7-Bit Mode Note: The resolution of the LSB 1 bit (25 nsec) is a typical value and its precision is not guaranteed. 17.3.1.3 6-bit mode In 6-bit mode, it is possible to generate a pulse with 3.2 µs period and approximately 313 kHz frequency (when X1 = 20 MHz). Varies with value of 2 low-order bits 6 high-order bits × 50 ns 3.2 µs 6 high-order bits × 50 ns 3.2 µs In 6-bit mode, the period is comprised of 6 bits (period = 26 × 50 ns) and two other bits provide a 12.5 ns resolution. However, because the actually obtained resolution is 25 ns, said resolution is accomplished artificially. To obtain a 12.5 ns resolution, the first, second, and third pulses are output by adding 25 ns, 0 ns, and 25 ns, respectively. In this way, a 12.5 ns resolution is realized as being “equivalent to.” The minimum equivalent width of the pulse is 0.2 µs (data “10”), and the maximum equivalent width of the pulse is 3.0 µs (data “F0”: “3B” + “0”). 7 0 Data register 6 high-order bits 2 low-order bits Pulse width = (6 high-order bits of data × 50 ns) + (2 low-order bits of data *) * The equivalent plus times in 2 low-order bits of data are shown below. 2-bit data 0 0 1 1 0 1 0 1 Equivalent plus time 0 ns 12.5 ns 25 ns 37.5 ns Figure 17-4 Shows a typical waveform in 6-bit mode. (The values are for X1 = 20 MHz.) Page 196 TMP88PS43FG Data 225 ns 3.2 µs 200ns 3.2 µs 225 ns 3.2 µs "11h" 225 ns 225 ns 225 ns "12h" 250 ns 225 ns 250 ns "13h" "14h" 250 ns 250 ns 250 ns 3.0 µs 3.0 µs 3.0 µs "F0h" Figure 17-4 6-Bit Mode Note: The resolution of the LSB 2 bit (12.5 nsec) is a typical value and its precision is not guaranteed. 17.3.2 Setting output data To set output data, write it to the Data Registers (HPWMDR0 and 1). Example: To output a 5.75 µs waveform in 7-bit mode using HPWM0 when the source clock (X1) = 20 MHz 5.75 µs 6.4 µs Because the resolution in 7-bit mode is 50 ns, to output a 5.75 µs pulse 5.75 µs ÷ 50 ns = 115 = 73H Because 73H is placed in the 7 high-order bits, the value is shifted one bit to become E6H. Therefore, set E6H in the Data Register (HPWMDR0). Page 197 17. 8-Bit High-speed PWM (HPWM0 and HPWM1) 17.3 Functional Description TMP88PS43FG Page 198 TMP88PS43FG 18. OTP operation This section describes the funstion and basic operationalblocks of TMP88PS43FG. The TMP88PS43FG has PROM in place of the mask ROM which is included in the TMP88CS43FG. The configuration and function are the same as the TMP88CS43FG. In addition, TMP88PS43FG operates as the single clock mode when releasing reset. 18.1 Operating mode The TMP88PS43FG has MCU mode and PROM mode. 18.1.1 MCU mode The MCU mode is set by fixing the TEST/VPP pin to the low level. (TEST/VPP pin cannot be used open because it has no built-in pull-down resistor). 18.1.1.1 Program Memory The TMP88PS43FG has 64K bytes built-in one-time-PROM (addresses 04000 to 13EFFH and FFF00 to FFFFFH in the MCU mode, addresses 00000 to 0FFFFH in the PROM mode). When using TMP88PS43FG for evaluation of mask ROM products, the program is written in the program storing area shown in Figure 18-1. Since the TMP88PS43FG supports several mask ROM sizes, check the difference in memory size and program storing area between the one-time PROM and the mask ROM to be used. 00000 00040 to 008BF 00000 00040 to 010BF SFR RAM DBR Reserved SFR RAM DBR Reserved 00000 Program area Program area Vector table area 0FFFF MCU mode PROM mode 04000 Program area 13EFF FFF00 FFFFF Mask ROM Reserved Vector table area 04000 13EFF FFF00 FFFFF Reserved Vector table area 0FEFF 0FF00 Figure 18-1 Program Memory Area Note: The area that is not in use should be set data to FFH, or a general-purpose PROM programmer should be set only in the program memory area to access. 18.1.1.2 Data Memory TMP88PS43FG has a built-in 4K bytes + 128 bytes Data memory (static RAM). Note: The Data memory size of TMP88CS43FG is 2K bytes + 128 bytes (static RAM). 18.1.1.3 Input/Output Circuiry 1. Control pins The control pins of the TMP88PS43FG are the same as those of the TMP88CS43FG except that the TEST pin does not have a built-in pull-down resistor. Page 199 18. OTP operation 18.1 Operating mode TMP88PS43FG 2. I/O ports The I/O circuitries of the TMP88PS43FG I/O ports are the same as those of the TMP88CS43FG. 18.1.2 PROM mode The PROM mode is set by setting the RESET pin, TEST pin and other pins as shown in Table 18-1 and Figure 18-2. The programming and verification for the internal PROM is acheived by using a general-purpose PROM programmer with the adaptor socket. Table 18-1 Pin name in PROM mode Pin name (PROM mode) A16 A15 to A8 A7 to A0 D7 to D0 CE OE PGM I/O Input Input Input Input/Output Input Input Input Power supply Power supply Power supply Setting pin Setting pin Setting pin Input Output Function Program memory address input Program memory address input Program memory address input Program memory data input/output Chip enable signal input Output enable signal input Program mode signal input +12.75V/5V (Power supply of program) +6.25V/5V 0V Fix to "H" level in PROM mode Fix to "L" level in PROM mode Fix to "L" level in PROM mode Set oscillation with resonator In case of external CLK input, set CLK to XIN and set XOUT to open. Pin name (MCU mode) P12 P47 to P40 P67 to P60 P37 to P30 P13 P14 P15 TEST VDD VSS AVDD,P21 AVSS,VAREF,P10,P11,P20,P22 RESET VPP VCC GND VCC GND RESET XIN (CLK) XOUT XIN XOUT Note 1: The high-speed program mode can be used. The setting is different according to the type of PROM programmer to use, refer to each description of PROM programmer. TMP88PS43FG does not support the electric signature mode, apply the ROM type of PROM programmer to TC571000D/AD. Always set the adapter socket switch to the "N" side when using TOSHIBA’s adaptor socket. Page 200 TMP88PS43FG TMP88PS43FG VPP (12.5 V/5 V) VCC TEST VCC setting pins P60 to P67 P13 P14 P15 P30 to P37 CE OE PGM D0 to D7 A15 to A0 P40 to P47 P12 A16 XIN 20 MHz GND setting pins XOUT VSS Refer to pin function for the other pin setting. GND Note 1: EPROM adaptor socket (TC571000 • 1M bit EPROM) Note 2: PROM programmer connection adaptor sockets BM11680 for TMP88PS43FG Note 3: Inside pin name for TMP88PS43FG Outside pin name for EPROM Figure 18-2 PROM mode setting Page 201 18. OTP operation 18.1 Operating mode TMP88PS43FG 18.1.2.1 Programming Flowchart (High-speed program writing) Start VCC = 6.25 V VPP = 12.75 V Address = Start address N=0 Program 0.1 ms pulse N=N+1 N = 25? No Error Address = Address + 1 No Verify OK Last address ? Yes VCC = 5 V VPP = 5 V Yes Read all data OK Pass Error Fail Figure 18-3 Programming Flowchart The high-speed programming mode is set by applying Vpp=12.75V (programming voltage) to the Vpp pin when the Vcc = 6.25 V. After the address and data are fixed, the data in the address is written by applying 0.1[msec] of low level program pulse to PGM pin. Then verify if the data is written. If the programmed data is incorrect, another 0.1[msec] pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address (maximum of 25 times). Subsequently, all data are programmed in all address. When all data were written, verfy all address under the condition Vcc=Vpp=5V. Page 202 TMP88PS43FG 18.1.2.2 Program Writing using a General-purpose PROM Programmer 1. Recommended OTP adaptor BM11680 for TMP88PS43FG 2. Setting of OTP adaptor Set the switch (SW1) to "N" side. 3. Setting of PROM programmer a. Set PROM type to TC571000D/AD. Vpp: 12.75 V (high-speed program writing mode) b. Data transmission ( or Copy) (Note 1) The PROM of TMP88PS43FG is located on different address; it depends on operating mode: MCU mode and PROM mode. When you write the data of ROM for mask ROM products, the data shuold be transferred (or copied ) from the address for MCU mode to that for PROM mode before writing operation is executed. For the applicable program areas of MCU mode and PROM mode are different, refer to TMP88PS43FG" Figure 18-1 Program Memory Area ". Example: In the block transfer (copy) mode, executed as below. 64KB ROM capacity: 04000 to 13EFFH + FFF00 to FFFFFH → 00000~0FFFFH c. Setting of the program address (Note 1) Start address: 00000H End address: 0FFFFH 4. Writting Write and verify according to the above procedure "Setting of PROM programmer". Note 1: For the setting method, refer to each description of PROM programmer. Make sure to set the data of address area that is not in use to FFH. Note 2: When setting MCU to the adaptor or when setting the adaptor to the PROM programmer, set the first pin of the adaptor and that of PROM programmer socket matched. If the first pin is conversely set, MCU or adaptor or programmer would be damaged. Note 3: The TMP88PS43FG does not support the electric signature mode. If PROM programmer uses the signature, the device would be damaged because of applying voltage of 12±0.5V to pin 9(A9) of the address. Don’t use the signature. Page 203 18. OTP operation 18.1 Operating mode TMP88PS43FG Page 204 TMP88PS43FG 19. Input/Output Circuitry 19.1 Control pins The input/output circuitries of the TMP88PS43FG control pins are shown below. Control Pin I/O Input/Output Circuitry Remark Osc. enable fc VDD RO High-frequency resonator connecting pins Rf = 1.2 MΩ (typ.) RO = 0.5 kΩ (typ.) VDD XIN XOUT Input Output Rf XIN XOUT RIN RESET VDD Hysteresis input Pull-up resistor included RIN = 220 kΩ (typ.) Input TEST Input Without pull-down resistor Fix the TEST pin at “L” level in MCU mode. Note: The TEST pin of TMP88PS43 does not have a pull-down resistor (RIN) and protect diode (D1). Fix the TEST pin at “L” level in MCU mode. Page 205 19. Input/Output Circuitry 19.2 Input/output ports TMP88PS43FG 19.2 Input/output ports Port I/O Input/output Circuit Remark Initial "High-Z" Data output P0 P3 P4 P5 Tri-state output Programmable open-drain P3, P4, P5: Large-current port Hysteresis input Output control I/O Disable Pin input Initial "High-Z" Data output P8 P9 Output control I/O Tri-state output Programmable open-drain Disable Pin input Initial "High-Z" Data output P6 P7 I/O Tri-state output Disable Pin input Initial "High-Z" Data output P1 I/O Tri-state output Hysteresis input Disable Pin input Initial "High-Z" P2 I/O Data output Pin input Open-drain output Hysteresis input Page 206 TMP88PS43FG 20. Electrical Characteristics 20.1 Absolute Maximum Ratings The Absolute Maximum Ratings stipulate the standards, any parameter of which cannot be exceeded even in an instant. If the device is used under conditions exceeding the Absolute Maximum Ratings, it may break down or degrade, causing injury due to rupture or burning. Therefore, always make sure the Absolute Maximum Ratings will not be exceeded when designing your application equipment. (VSS = 0 V) Parameter Power supply voltage Program voltage Input voltage Output voltage Symbol VDD VPP VIN VOUT IOH Output current IOL1 IOL2 Σ IOUT1 Σ IOUT2 Mean output current Σ IOUT3 Σ IOUT4 Power dissipation Operating temperature Soldering temperature (time) Storage temperature PD Topr Tsld Tstg P4 P5 60 60 350 −40 to 85 260 (10 s) −55 to 125 °C mW P0, P1, P3, P4, P5, P6, P7, P8, P9 P0, P1, P2, P6, P7, P8, P9 P3, P4, P5 P0, P1, P2, P6, P7, P8, P9 P3 TEST/VPP Pins Standard −0.3 to 6.5 −0.3 to 13.0 −0.3 to VDD + 0.3 −0.3 to VDD + 0.3 −1.8 3.2 30 60 60 mA Total of all ports except large-current ports Total of 8 pins of large-current ports P30 to 7 Total of 8 pins of large-current ports P40 to 7 Total of 8 pins of large-current ports P50 to 7 QFP V Unit Remark Page 207 20. Electrical Characteristics 20.3 DC Characteristics TMP88PS43FG 20.2 Operating Conditions The Operating Conditions show the conditions under which the device be used in order for it to operate normally while maintaining its quality. If the device is used outside the range of Operating Conditions (power supply voltage, operating temperature range, or AC/DC rated values), it may operate erratically. Therefore, when designing your application equipment, always make sure its intended working conditions will not exceed the range of Operating Conditions. (VSS = 0 V, Topr = −40 to 85°C) Parameter Power supply voltage High level input voltage Symbol VDD VIH1 VIH2 VIL1 Low level input voltage VIL2 fc Normal (P6, P7, P8, P9) Hysteresis (P0, P1, P2, P3, P4, P5, RESET) Normal (P6, P7, P8, P9) Hysteresis (P0, P1, P2, P3, P4, P5, RESET) XIN, XOUT VDD ≥ 4.5 V 0 VDD ≥ 4.5 V Pins fc = 20 MHz Condition NORMAL/IDLE/STOP Min 4.5 VDD × 0.70 VDD × 0.75 VDD VDD × 0.30 VDD × 0.25 20 MHz V Max 5.5 Unit V Clock frequency VDD = 4.5 V to 5.5 V 8 20.3 DC Characteristics (VSS = 0 V, Topr = −40 to 85°C) Parameter Symbol IIN1 Input current IIN2 IIN3 Input resistance Output leakage current High level output voltage Low level output current NORMAL mode power supply current IDLE mode power supply current STOP mode power supply current IDD VDD = 5.5 V, VIN = 5.3 V/0.2 V fc = 20 MHz RIN2 ILO VOH IOL1 IOL2 TEST Sink Open Dran, Tri-state port RESET , STOP RESET Pins Condition Min Typ. Max Unit VDD = 5.5 V, VIN = 5.5 V/0 V – – ±2 µA 90 VDD = 5.5 V, VIN = 5.5 V/0 V VDD = 4.5 V, IOH = −0.7 mA VDD = 4.5 V, VOL = 0.4 V VDD = 4.5 V, VOL = 1.0 V – 4.1 1.6 – – – – 220 – – – 20 18 16 2 510 ±2 – – – 25 23 100 kΩ µA V Sink Open Drain, Tri-state port Tri-state port P0, P1, P2, P6, P7, P8, P9 P3, P4, P5 mA µA Note 1: Typical values show those at Topr = 25°C, VDD = 5V. Note 2: Input current (IIN3); The current through pull-up or pull-down resistor is not included. Note 3: IDD does not include IREF current. Page 208 TMP88PS43FG 20.4 AD Conversion Characteristics (Topr = −40 to 85°C) Parameter Analog reference voltage Analog input voltage range Analog reference power supply current Nonlinearity error Zero error Full scale error Overall error VDD = 5 V, VSS = 0 V AVDD = VAREF = 5 V AVSS = 0 V Symbol VAREF VAIN IREF VDD = AVDD = VAREF = 5.0 V VSS = AVSS = 0 V Condition VSS = 0 V, VDD = AVDD Min VDD −1.0 VASS – – – – – Typ. – – 0.5 – – – – ±1 ±1 ±1 ±2 Max 8 bit VDD VAREF 1.0 ±2 ±2 ±2 ±4 LSB 10 bit Unit V mA Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the idea conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to "Register Configuration" in the section of AD converter. Note 3: Please use input voltage to AIN input pin in limit of VAREF - VSS. When voltage or range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog reference voltage range; ∆VAREF = VAREF - VSS 20.5 AC Characteristics (VSS = 0 V, VDD = 4.5 to 5.5 V, Topr = −40 to 85°C) Parameter Machine cycle time High level clock pulse width Low level clock pulse width Symbol tcy tWCH tWCL Condition During NORMAL1 mode During IDLE mode When operating with external clock (XIN input) fc = 20 MHz Min 0.2 Typ. – Max 0.5 Unit µs 25 – – ns Page 209 20. Electrical Characteristics 20.5 AC Characteristics TMP88PS43FG 20.6 DC Characteristics, AC Characteristics (PROM mode) 20.6.1 Read operation in PROM mode (VSS = 0 V, Topr = −40 to 85°C) Parameter High level input voltage (TTL) Low level input voltage (TTL) Power supply Program power supply Address access time Symbol VIH4 VIL4 VCC VPP tACC VCC = 5.0 ± 0.25 V Condition Min VCC × 0.7 0 4.75 – Typ. – – 5.0 1.5tcyc + 300 Max VCC VCC × 0.12 5.25 – ns V Unit Note: tcyc = 250 ns at fCLK = 16 MHz A16 to A0 CE OE PGM tACC D7 to D0 High-Z Data output Page 210 TMP88PS43FG 20.6.2 Program operation (High-speed) (Topr = 25 ± 5 °C) Parameter High level input voltage (TTL) Low level input voltage (TTL) Power supply Program power supply Pulse width of initializing program Symbol VIH4 VIL4 VCC VPP tPW VCC = 6.0 V Condition Min VCC × 0.7 0 6.0 12.5 0.095 Typ. – – 6.25 12.75 0.1 Max VCC VCC × 0.12 6.5 13.0 0.105 ms V Unit High-speed program writing A16 to A0 CE OE D7 to D0 Unknown Input data tPW Output data PGM VPP Write Verify Note 1: The power supply of VPP (12.75 V) must be set power-on at the same time or the later time for a power supply of VCC and must be clear power-on at the same time or early time for a power supply of VCC. Note 2: The pull-up/pull-down device on the condition of VPP = 12.75 V ± 0.25 V causes a damage for the device. Do not pull-up/pull-down at programming. Note 3: Use the recommended adapter and mode. Using other than the above condition may cause the trouble of the writting. Page 211 20. Electrical Characteristics 20.8 Handling Precaution TMP88PS43FG 20.7 Recommended Oscillation Conditions XIN XOUT C1 C2 High-frequency oscillation Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. Note 2: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by Murata Manufacturing Co., Ltd. For details, please visit the website of Murata at the following URL: http://www.murata.com 20.8 Handling Precaution - The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown below. 1. When using the Sn-37Pb solder bath Solder bath temperature = 230 °C Dipping time = 5 seconds Number of times = once R-type flux used 2. When using the Sn-3.0Ag-0.5Cu solder bath Solder bath temperature = 245 °C Dipping time = 5 seconds Number of times = once R-type flux used Note: The pass criteron of the above test is as follows: Solderability rate until forming ≥ 95 % - When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. Page 212 TMP88PS43FG 21. Package Dimensions QFP80-P-1420-0.80B Rev 01 Unit: mm Page 213 21. Package Dimensions TMP88PS43FG Page 214 This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/X (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively. Both the hardware and software are supported continuously with version updates. The recent advances in CMOS LSI production technology have been phenomenal and microcomputer systems for LSI design are constantly being improved. The products described in this document may also be revised in the future. Be sure to check the latest specifications before using. Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS production technology and especially well proven CMOS technology. We are prepared to meet the requests for custom packaging for a variety of application areas. We are confident that our products can satisfy your application needs now and in the future.