TMP91C829

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C829 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91C829 CMOS 16-Bit Microcontroller TMP91C829FG 1. Outline and Features TMP91C829 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment.With 2 Kbytes of boot ROM included, it allows your programs to be erased and rewritten on board. TMP91C829FG comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) • • • • • Instruction mnemonics are upward compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (444 ns/2 bytes at 36 MHz) (2) Minimum instruction execution time: 111 ns (at 36 MHz) (3) Built-in RAM: 8 Kbytes Built-in ROM: None Built-in Boot ROM: 2 Kbytes 91C829-1 2006-03-15 TMP91C829 (4) External memory expansion • • Expandable up to 16 Mbytes (Shared program/data area) Can simultaneously support 8-/16-bit width external data bus … Dynamic data bus sizing (5) 8-bit timers: 6 channels (6) 16-bit timer/event counter: 1 channel (7) Serial bus interface: 2 channels (8) 10-bit AD converter: 8 channels (9) Watchdog timer (10) Chip select/wait controller: 4 blocks (11) Interrupts: 35 interrupts • • • 9 CPU interrupts: Software interrupt instruction and illegal instruction 19 internal interrupts: 7 priority levels are selectable 7 external interrupts: 7 priority levels are selectable (Level mode, rising edge mode and falling edge mode are selectable.) RD (12) Input/output ports: 46 pins (Except Data bus (8bit), Address bus (16bit) and (13) Standby function Three HALT modes: IDLE2 (Programmable), IDLE1, STOP (14) Operating voltage • • • VCC (5 V) = 4.75 V to 5.25 V (fc max = 36 MHz) VCC (3 V) = 3.0 V to 3.6 V (fc max = 36 MHz) 100-pin QFP: P-LQFP100-1414-0.50F pin) (15) Package Power on and power off the supply Power on and power off of the supply require the simultaneous execution of the 5 V power supply and 3.3 V power supply. If the both power supplies cannot be turned on or off simultaneously, turn on or off each power supply within the specifications shown in Figure 3.1.2 and 3.1.2 “Power On and Power Off of the Supply”. When power on and power off of the supply is performed on eigher of them, overlap current may run into the internal logic. Leaving overlap current running results in increase of power dissipation and short LSI life. Please avoid leaving either of power supplies on. 91C829-2 2006-03-15 TMP91C829 ADTRG (AN3/PA3) AN0 to AN7 (PA0 to PA7) VREFH VREFL AVCC AVSS CPU (TLCS-900L1) LVCC 3V HVCC 5V VSS BOOT 10-bit 8-ch AD converter Port A XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits AM0/AM1 RESET OSC Clock gear Port 1 Port 2 X1 X2 EMU0 EMU1 (P10 to P17) D8 to D15 (P20 to P27) A16 to A23 SR F F RD WR PC Port Z Watchdog timer (WDT) PZ2 ( HWR ) PZ3 Data bus Address bus D0 to D7 A0 to A7 A8 to A15 TXD0 (P80) RXD0 (P81) SCLK0/ CTS0 (P82) STS0 (P83) Serial I/O (Channel 0) Port 5 Serial I/O (Channel 1) BUSRQ (P53) BUSAK (P54) TXD1 (P84) RXD1 (P85) SCK1/ CTS1 (P86) STS1 (P87) Port 8 WAIT (P55) TA0IN/INT1 (P70) TA1OUT (P71) 8-bit timer (Timer 0) 8-bit timer (Timer 1) 8-Kbyte RAM 8-bit timer (Timer 2) CS/WAIT controller (4 blocks) CS0 (P60) CS1 (P61) CS2 (P62) CS3 (P63) Interrupt controller NMI INT0 (P56) TA3OUT/INT2 (P72) 8-bit timer (Timer 3) TB0IN0 (P93) TB0IN1 (P94) TB0OUT0 (P95) TB0OUT1 (P96) INT5 (P90) TA4IN/INT3 (P73) TA5OUT (P74) INT4 (P75) 8-bit timer (Timer 4) 8-bit timer (Timer 5) Port 7 2-Kbyte boot ROM 16-bit timer (TMRB0) Port 9 ( ): Initial function after reset Figure 1.1 TMP91C829 Block Diagram 91C829-3 2006-03-15 TMP91C829 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C829FG, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C829FG. Pin No. Pin name P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 A15 A14 A13 A12 Pin No. Pin name HVCC (5 V) BOOT 64 65 66 67 68 69 70 71 72 73 74 75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 TMP91C829FG 40 86 39 87 38 88 Top view 37 89 36 90 35 91 34 92 P-LQFP100-1414-0.50F 33 93 32 94 31 95 30 96 29 97 28 98 27 99 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 D7 D6 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RD WR LVCC (3 V) PZ2/ HWR VSS PA0/AN0 PA1/AN1 PA2/AN2 ADTRG /PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 100 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 D5 D4 D3 D2 D1 D0 P96/TB0OUT1 P95/TB0OUT0 P94/TB0IN1 P93/TB0IN0 P90/INT5 P75/INT4 P74/TA5OUT P73/TA4IN/INT3 P72/TA3OUT/INT2 P71/TA1OUT P70/TA0IN/INT1 RESET AM1 X1 DVSS X2 LVCC (oscillator) AM0 P63/ CS3 VREFH 1 VREFL 2 AVSS 3 AVCC 4 NMI 25 P62/ CS2 24 P61/ CS1 23 P60/ CS0 22 EMU1 21 EMU0 20 P87/ STS1 19 P86/SCLK0/ CTS1 18 P85/RXD1 17 P84/TXD1 16 P83/ STS0 15 P82/SCLK0/ CTS0 14 P81/RXD0 5 7 VSS 6 P53/ BUSRQ HVCC (5 V) 8 P54/ BUSAK 9 P55/ WAIT 10 P56/INT0 11 PZ3 12 P80/TXD0 13 Figure 2.1.1 Pin Assignment Diagram (100-pin LQFP) 91C829-4 2006-03-15 TMP91C829 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/3) Pin Name D0 to D7 P10 to P17 D8 to D15 P20 to P27 A16 to A23 A8 to A15 A0 to A7 RD Number of Pins 8 8 I/O I/O I/O I/O Functions Data (Lower): Bits 0 to 7 of data bus Port 1: I/O port that allows I/O to be selected at the bit level (when used to the external 8-bit bus) Data (Upper): Bits 8 to15 of data bus Port 2: Output port Address: Bits 16 to 23 of address bus Address: Bits 8 to 15 of address bus Address: Bits 0 to 7 of address bus Read: Strobe signal for reading external memory Write: Strobe signal for writing data to pins D0 to D7 Port 53: I/O port (with pull-up resistor) Bus request: Signal used to request bus release (High impedance) Port 54: I/O port (with pull-up resistor) Bus acknowledge: Signal used to acknowledge bus release (High impedance) Port 55: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait. Port 56: I/O port (with pull-up resistor) Interrupt request pin0: Interrupt request pin with programmable level/rising edge/falling edge Port 60: Output port Chip select 0: Outputs 0 when address is within specified address area Port 61: Output port Chip select 1: Outputs 0 when address is within specified address area Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area Port 63: Output port Chip select 3: Outputs 0 when address is within specified address area Port 70: I/O port Timer A0 input Interrupt request pin2: Interrupt request pin with programmable level/rising edge/falling edge Port 71: I/O port Timer A0 or timer A1 output Port 72: I/O port Timer A2 or timer A3 output Interrupt request pin2: Interrupt request pin with programmable level/rising edge/falling edge 8 8 8 1 1 1 1 Output Output Output Output Output Output I/O Input I/O Output WR P53 BUSRQ P54 BUSAK P55 WAIT 1 1 I/O Input I/O Input P56 INT0 P60 CS0 1 1 1 1 1 Output Output Output Output Output Output Output Output I/O Input Input P61 CS1 P62 CS2 P63 CS3 P70 TA0IN INT1 P71 TA1OUT P72 TA3OUT INT2 1 1 I/O Output I/O Output Input 91C829-5 2006-03-15 TMP91C829 Table 2.2.2 Pin Names and Functions (2/3) Pin Name P73 TA4IN INT3 P74 TA5OUT P75 INT4 P80 TXD0 P81 RXD0 P82 SCLK0 CTS0 Number of Pins 1 I/O I/O Input Input Port 73: I/O port Timer A4 input Functions Interrupt request pin 3: Interrupt request pin with programmable level/rising edge/falling edge Port 74: I/O port Timer A4 or timer A5 output Port 75: I/O port Interrupt request pin 4: Interrupt request pin with programmable Port 80: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin Port 81: I/O port (with pull-up resistor) Serial receive data 0 Port 82: I/O port: (with pull-up resistor) Serial clock I/O 0 Serial data send enable 0 (Clear to send) Port 83: I/O port (with pull-up resistor) Serial data request signal 0 Port 84: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin Port 85: I/O port (with pull-up resistor) Serial receive data 1 Port 86: I/O port: (with pull-up resistor) Serial clock I/O 1 Serial data send enable 1 (Clear to send) Port 87: I/O port (with pull-up resistor) Serial data request signal 1 Port 90: I/O port Interrupt request pin 5: Interrupt request pin with programmable level/rising edge/falling edge Port 93: I/O port Timer B0 input 0 Port 94: I/O port Timer B0 input 1 Port 95: I/O port Timer B0 output 0 Port 96: I/O port Timer B0 output 1 Port A0 to A7: Pin used to input port Analog input 0 to 7: Pins used to input to AD converter A/D trigger: Signal used to request AD start (PA3) Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) 1 1 1 1 1 I/O Output I/O Input I/O Output I/O Input I/O Input I/O P83 STS0 1 1 1 1 I/O I/O Output I/O Input I/O Input I/O P84 TXD1 P85 RXD1 P86 SCLK1 CTS1 P87 STS1 1 1 I/O I/O Input P90 INT5 P93 TB0IN0 P94 TB0IN1 P95 TB0OUT0 P96 TB0OUT1 PA0 to PA7 AN0 to AN7 ADTRG 1 1 1 1 8 I/O Input I/O Input I/O Output I/O Output Input Input Input PZ2 HWR 1 1 I/O Output I/O PZ3 91C829-6 2006-03-15 TMP91C829 Table 2.2.3 Pin Names and Functions (3/3) Pin Name BOOT NMI Number of Pins 1 1 2 I/O Input Input Input Functions This pin sets boot mode (with pull-up resistor) Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Address mode : External data bus with select pin When external 16-bit bus is fixed or external 8- or 16-bit buses are mixed, AM1 = 0 , AM0 = 1 When external 8-bit bus is fixed, AM1 = 0 , AM0 = 0 AM0 to AM1 RESET 1 1 1 1 1 2 2 2 3 1 1 Input Input Input I/O Reset: Initializes TMP91C829 (with pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND supply pin for AD converter Oscillator connection pins Power supply pins (5 V) Power supply pins (3 V) GND pins (0 V) VREFH VREFL AVCC AVSS X1/X2 HVCC LVCC DVSS EMU0 EMU1 Output Output Open pin Open pin Note 1: An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using the BUSRQ and BUSAK signal. Note 2: All pins which have a built-in pull-up resistor (Other than the RESET pin and the BOOT pin ) can be disconnected from the resistor in software. 91C829-7 2006-03-15 TMP91C829 3. Operation This section describes the basic components, functions and operation of the TMP91C829. Notes and restrictions which apply to the various items described here are outlined in section 7. “Points to Note and Restrictions” at the end of this databook. 3.1 CPU The TMP91C829 incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For a description of this CPU’s operation, please refer to the section of this databook which describes the TLCS-900/L1 CPU. The following sub sections describe functions peculiar to the CPU used in the TMP91C829; these functions are not covered in the section devoted to the TLCS-900/L1 CPU. 3.1.1 Reset When resetting the TMP91C829 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (8.89 μs at 36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low-level at least for 10 system clocks. Clock gear is intitialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 ×1/2). When the reset is accept, the CPU: • Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC PC PC • • • ← ← ← Data in location FFFF00H Data in location FFFF01H Data in location FFFF02H Sets the stack pointer (XSP) to 100H. Sets bits of the status register (SR) to 111. (Thereby setting the interrupt level mask register to level 7.) Sets the bit of the status register to 1 (MAX mode). (Note: As this product does not support MIN mode, do not write a 0 to the bit.) Clears bits of the status register to 000. (Thereby selecting register bank 0.) • When the reset is cleared, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is cleared. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. • • Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not change by resetting. Figure 3.1.1 shows the timing of a reset for the TMP91C829. 91C829-8 2006-03-15 fFPH sampling sampling RESET A23 to A0 0FFFF00H CS0, CS1,CS3 CS2 D0 to D15 Data-in Data-in Read Figure 3.1.1 TMP91C829 Reset Timing Example 91C829-9 Data-in RD (After reset released, starting 2 waits read cycle) D0 to D15 Write WR HW R (PZ2 input mode) Pull up (Internal) High-Z TMP91C829 2006-03-15 TMP91C829 3.1.2 VCC 5 Power On and Power Off of the Supply VCC 3.3 RESET Max 1 [s] Min 10 [ms] Min 0 [s] Max 1 [s] Oscillator operation time + Clock doubler stabilization time Figure 3.1.2 Power Supply On/Off Timing 3.2 Outline of Operation Modes There are multi chip and multi boot modes. Which mode is selected depends on the device’s pin state after a reset. • • Multi chip mode: The device normally operations in this mode. After a reset, the device starts executing the external memory program. Multi boot mode: This mode is used to rewrite the external flash memory by serial transfer (UART) or ATAPI transfer. After a reset, internal boot program starts up, executing a on-board rewrite program. Table 3.2.1 Operation Mode Setup Table Operation Mode Multi chip mode Multi boot mode Mode Setup Input Pin RESET BOOT H L 91C829-10 2006-03-15 TMP91C829 3.3 Memory Map Figure 3.3.1 is a memory map of the TMP91C829. Multi chip mode 000000H 000100H Internal I/O (4 Kbytes) 000000H 000100H Multi boot mode Internal I/O (4 Kbytes) Direct area (n) 001000H Internal RAM (8 Kbytes) 003000H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH 001000H Internal RAM (8 Kbytes) 003000H 16-Mbyte area (r32) (−r32) (r32+) (r32 + d8/16) (r32 + r8/16) External memory (nnn) External memory FFF800H FFFEFFH FFFF00H FFFFFFH Vector table (256 bytes) FFFF00H FFFFFFH Internal boot ROM (2 Kbytes) Vector table (256 bytes) ( = Internal area) Figure 3.3.1 TMP91C829 Memory Map 91C829-11 2006-03-15 TMP91C829 3.4 Triple Clock Function and Standby Function The TMP91C829 contains (1) a clock gearing system, (2) a standby controller, and (3) a noise-reducing circuit. It is used for low-power, low-noise systems. The clock operating mode is as follows: (a) Single clock mode (X1, X2 pins only). Figure 3.4.1 shows a transition figure. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Clock mode transition figure Figure 3.4.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc. In case of TMP91C829, fc = fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is regarded as one state. 91C829-12 2006-03-15 TMP91C829 3.4.1 Block Diagram of System Clock SYSCR0 SYSCR2 SYSCR0 Warm-up timer (High-frequency oscillator) φT φT0 fc/16 fFPH ÷2 ÷4 fFPH fc fc/2 fc/4 fc/8 fc/16 ÷2 fSYS X1 X2 High-frequency oscillator fOSCH ÷2 ÷4 ÷8 ÷16 SYSCR1 Clock gear fSYS TMRA01 to TMRA45 φT0 Prescaler CPU ROM RAM TMRB0 Prescaler Interrupt controller WDT I/O ports SIO0, SIO1 Prescaler Figure 3.4.2 Block Diagram of System Clock 91C829-13 2006-03-15 TMP91C829 3.4.2 SFRs 7 SYSCR0 Bit symbol (00E0H) Read/Write After reset Function 1 Always write “1”. − 6 − 0 Always write “0”. 5 − 1 Always write “1”. 4 − R/W 0 Always write “0”. 3 − 0 Always write “0”. 2 WUEF 0 Warm-up timer Write 0: Don’t care Write 1: Start timer Read 0: End warm-up Read 1: Do not end warm-up 2 GEAR2 R/W 1 PRCK1 0 PRCK0 0 0 Select prescaler clock 00: fFPH 01: Reserved 10: fc/16 11: Reserved 7 SYSCR1 Bit symbol (00E1H) Read/Write After reset Function 6 5 4 3 − 0 Always write “0”. 1 GEAR1 0 GEAR0 0 0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 2 HALTM0 R/W 1 1 0 DRVE R/W 0 1: Drive the pin during STOP mode 7 SYSCR2 Bit symbol (00E2H) Read/Write After reset Function 6 − R/W 0 Always write “0”. 5 WUPTM1 R/W 4 WUPTM0 R/W 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 1 0 Warm-up timer 00: Reserved 8 01: 2 inputted frequency 14 10: 2 inputted frequency 16 11: 2 inputted frequency Figure 3.4.3 SFR for System Clock 91C829-14 2006-03-15 TMP91C829 7 EMCCR0 Bit symbol (00E3H) Read/Write After reset Function PROTECT R 6 − R/W 5 − R/W 1 Always write “1”. 4 − R/W 0 Always write “0”. 3 − R/W 0 Always write “0”. 2 EXTIN R/W 0 1: External clock 1 − R/W 1 Always write “1”. 0 − R/W 1 Always write “1”. 0 0 Protect flag Always 0: OFF write “0”. 1: ON EMCCR1 Bit symbol (00E4H) Read/Write After reset Function Writing 1FH turns protections OFF. Writing any value other than 1FH turns protection ON. Figure 3.4.4 SFR for Noise Reducing 91C829-15 2006-03-15 TMP91C829 3.4.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The initialization = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after a reset. For example, fSYS is set to 1.125 MHz when the 36 MHz oscillator is connected to the X1 and X2 pins. Clock gear controller The fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8, or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example: Changing to a high-frequency gear SYSCR1 EQU LD X: Don’t care 00E1H (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. (Changing to high-frequency clock gear) To change the clock gear, write the appropriate value to the SYSCR1 register. The value of fFPH will not change until a period of time equal to the warm-up time has elapsed from the point at which the register is written to. There is a possibility that the instruction immediately following the instruction which changes the clock gear will be executed before the new clock setting comes into effect. To ensure that this does not happen, insert a dummy instruction (to execute a write cycle) as follows: Example: SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction. Instruction to be executed after clock gear has changed. 91C829-16 2006-03-15 TMP91C829 3.4.4 Prescaler Clock Controller For the internal I/O (TMRA01:45, TMRB0 and SIO0, SIO1), there is a prescaler which can divide the clock. The φT clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 register determines which clock signal is input. The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0 register determines which clock signal is input. 3.4.5 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Single drive for high-frequency oscillator (2) Protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 and EMCCR1 registers. (1) Single drive for high-frequency oscillator (Purpose) Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation (STOP + EMCCR0) X2 pin (Setting method) When a 1 is written to the EMCCR0, the oscillator is disabled and is operated as a buffer. The X2 pin always outputs a 1. is initialized to 0 by a reset. Note: Do not write EMCCR0 = “1” when using external resonator. 91C829-17 2006-03-15 TMP91C829 (2) Protection of register contents (Purpose) An item for mistake operation by inputted noise. To execute the program certainty which is occurred mistake operation, the protect-register can be disabled write operation for the specific SFR. Write disabled SFRs 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear (only EMCCR1 can be written to.) SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Block diagram) Protect register EMCCR0 To EMCCR1 Write value other than 1FH SQ Write 1FH R Write signal SFR Write signal to the disabled SFR Write signal to the other SFR (Setting method) Writing any value other than 1FH to the EMCCR1 register turns on protection, thereby preventing the CPU from writing to the specific SFR. Writing 1FH to EMCCR1 turns off protection. The protection status is set in EMCCR0. Resetting initializes the protection status to off. 91C829-18 2006-03-15 TMP91C829 3.4.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register. The subsequent actions performed in each mode are as follows: a. IDLE2: The CPU only is halted. In IDLE2 mode internal I/O operations can be performed by setting the following registers. Table 3.4.1 shows the registers of setting operation during IDLE2 mode. Table 3.4.1 The Registers of Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRB0 SIO0 SIO1 AD converter WDT SFR TA01RUN TA23RUN TA45RUN TB0RUN SC0MOD1 SC1MOD1 ADMOD1 WDMOD b. c. IDLE1: Only the oscillator to operate. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.4.2. Table 3.4.2 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO AD converter WDT Interrupt controller Operational Can be selected Stopped IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.4.5, Table 3.4.6 Maintain same state as when HALT instruction was executed. Block 91C829-19 2006-03-15 TMP91C829 (2) How to clear a HALT mode The halt state can be cleared by a reset or by an interrupt request. The combination of the value in of the interrupt mask register and the current HALT mode determine in which ways the HALT mode may be cleared. The details associated with each type of halt state clearance are shown in Table 3.4.3. • Clearance by interrupt request Whether or not the HALT mode is cleared and subsequent operation depends on the status of the generated interrupt. If the interrupt request level set before execution of the HALT instruction is greater than or equal to the value in the interrupt mask register, the following sequence takes place: The HALT mode is cleared, the interrupt is then processed, and the CPU then resumes execution starting from the instruction following the HALT instruction. If the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is not cleared. (If a non-maskable interrupt is generated, the HALT mode is cleared and the interrupt processed, regardless of the value in the interrupt mask register.) However, for INT0 to INT4 only, even if the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is cleared. In this case, the interrupt is not processed and the CPU resumes execution starting from the instruction following the HALT instruction. The interrupt request flag remains set to 1. Note: Usually, interrupts can release all halts status. However, the interrupts ( NMI , INT0 to INT4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. • Clearance by reset Any halt state can be cleared by a reset. When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms) must be allowed after the reset for the operation of the oscillator to stabilize. When a HALT mode is cleared by resetting, the contents of the internal RAM remain the same as they were before execution of the HALT instruction. However, all other settings are reinitialized. (Clearance by an interrupt affects neither the RAM contents nor any other settings – the state which existed before the HALT instruction was executed is retained.) 91C829-20 2006-03-15 TMP91C829 Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of Halt State Clearance NMI INTWDT INT0 to INT4 (Note) Interrupt INT5 INTTA0 to INTTA5 INTTB00, INTTB01, INTTBOF0 INTRX0, INTTX0 INTRX1, INTTX1 INTAD RESET Interrupt Enabled Interrupt Disabled (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE2 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ IDLE1 STOP ♦ × ♦ × × × × × × ♦ × ♦ × × × × × × *1 *1 IDLE2 − − IDLE1 STOP − − − − ○ × × × × × × ○ × × × × × × ○* 1 × × × × × × Reset initializes the LSI ♦: After clearing the HALT mode, CPU starts interrupt processing. ○: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. ×: Cannot be used to clear the HALT mode. −: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The HALT mode is cleared when the warm-up time has elapsed. Note: When the HALT mode is cleared by INT0 to INT4 interrupt of the level mode in the interrupt enabled status, hold the level until starting interrupt processing. Changing level before holding level, interrupt processing is correctly started. (Example: Clearing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH LD LD LD EI LD HALT (P5FC), 40H (IIMC0), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; Sets P56 to INT0 ; Sets INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine INT0 RETI 820FH LD XX, XX 91C829-21 2006-03-15 TMP91C829 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Clearing interrupt IDLE2 mode Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Clearing interrupt IDLE1 mode Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C829-22 2006-03-15 TMP91C829 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 register. Table 3.4.5, Table 3.4.6 summarizes the state of these pins in STOP mode. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. See the sample warm-up times in Table 3.4.4. Figure 3.4.7 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release STOP mode Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.4.4 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 36 MHz SYSCR2 01 (2 ) 7.1 μs 8 10 (214) 0.455 ms 11 (216) 1.820 ms 91C829-23 2006-03-15 TMP91C829 Table 3.4.5 Input buffer State Table Input Buffer State Input Function Name When the CPU is Operating During Reset When Used as Function Pin *1 ON − In HALT mode (IDLE2/IDLE1) In HALT mode (STOP) =1 When Used as Function Pin OFF ON − =0 When Used as Function Pin OFF − Port Name When Used When Used When Used as Input as Function as Input Port Port Pin − When Used as Input Port − When Used as Input Port − − D0-D7 D8-D15 BUSRQ P10-17 P53(*6) P54(*6) P55(*6) P56(*6) P70 P71 P72 P73 P74 P75 P80(*6) P81(*6) P82(*6) P83-P84(*6) P85(*6) P86(*6) P87(*6) P90 P93 P94 P95-P96 PA0-PA2(*7) PA3(*7) PA4-PA7(*7) PZ2-PZ3(*6) BOOT (*6) OFF ON OFF OFF ON − − ON *2 OFF ON OFF OFF ON OFF − OFF WAIT INT0 TA0IN INT1 − − OFF ON ON ON ON ON ON ON *3 ON *2 ON *2 − − ON INT2 TA4IN INT3 − − OFF ON OFF − OFF ON OFF ON *3 ON − ON ON − ON − INT4 − ON − ON − ON − ON − RXD0 SCLK0 CTS0 − ON ON − ON − ON − OFF − RXD1 SCLK1 CTS1 − − OFF ON ON ON − ON ON − ON OFF − INT5 TB0IN0 TB0IN1 − − − − − ON ON ON OFF AN0-AN2 AN3 ADTRG AN4-AN7 − − − − − − *4 OFF ON *4 *2 *5 *4 ON *4 OFF *4 ON *4 OFF *4 ON *4 NMI RESET (*6) ON − ON − ON − ON − ON AM0,AM1 X1 OFF OFF ON: The buffer is always turned on. A current flows the *1: The buffer is turned on if read external. input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable *2: The buffer is turned on if access port. *3: The buffer is turned off if FC register is “0”. The buffer is turned on if FC register is “1”. *4: The buffer is always enable to input. *5: The buffer is turned on if read port. *6: Port having a pull-up resistor.(Programmable) *7: AIN input does not cause a current to flow through the buffer. 91C829-24 2006-03-15 TMP91C829 Table 3.4.6 Output buffer State Table Output Buffer State Output Function Name When the CPU is Operating During Reset When Used as Function Pin *1 When Used as Output Port − Port Name In HALT mode (IDLE2/IDLE1) When Used as Function Pin OFF When Used as Output Port − In HALT mode (STOP) =1 When Used as Function Pin OFF When Used as Output Port − =0 When Used as Function Pin When Used as Output Port − − D0-D7 D8-D15 A16-A23 A8-A15 A0-A7 P10-P17 P20-P27 − − − − − ON ON ON OFF OFF ON ON RD WR − − − − ON − ON − − P53 P54 P55-P56 P60 P61 P62 P63 P70 P71 P72 P73 P74 P75 P80 P81 P82 P83 P84 P85 P86 P87 P90 P93-P94 P95 P96 PZ2 PZ3 X2 − − − BUSAK − ON − ON − ON − OFF − CS0 CS1 CS2 CS3 − − ON ON ON ON − ON OFF − − TA1OUT TA3OUT − ON − ON − ON − OFF − TA5OUT − ON − ON − ON − OFF − TXD0 − ON − ON ON − ON ON − ON OFF − OFF SCLK0 STS0 TXD1 − − ON − ON − ON − OFF − SCLK1 STS1 − − ON − ON − ON − OFF − TB0OUT0 TB0OUT1 HWR − − ON ON ON ON − OFF ON − − *3 − *3 ON: The buffer is always turned on. When the bus is *1: The buffer is turned on if write external. released, however, output buffers for some pins are turned off. OFF: The buffer is always turned off. *2: Port having a pull-up resistor.(Programmable) *3: The buffer output High level. -: No applicable 91C829-25 2006-03-15 TMP91C829 3.5 Interrupts Interrupts are controlled by the CPU interrupt mask register SR and by the built-in interrupt controller. The TMP91C829 has a total of 35 interrupts divided into the following five types: • • • Interrupts generated by CPU: 9 sources (Software interrupts, illegal instruction interrupt) Interrupts on external pins ( NMI and INT0 to INT5): 7 sources Internal I/O interrupts: 19 sources A (Fixed) individual interrupt vector number is assigned to each interrupt. One of seven (Variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register . If the priority level of the interrupt is higher than the value of the interrupt mask register, the CPU accepts the interrupt. The interrupt mask register value can be updated using the value of the EI instruction (EI num sets data to num). For example, specifying “EI 3” enables the maskable interrupts which priority level set in the interrupt controller is 3 or higher, and also non-maskable interrupts. Operationally, the DI instruction ( = 7) is identical to the EI 7 instruction. DI instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 0 to 6. The EI instruction is vaild immediately after execution. In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a micro DMA interrupt processing mode as well. The CPU can transfer the data (1 or 2 or 4 bytes) automatically in micro DMA mode, therefore this mode is used for speed up interrupt processing, such as transferring data to the internal or external peripheral I/O. Moreover, TMP91C829 has software start function for micro DMA processing request by the software not by the hardware interrupt. Figure 3.5.1 shows the overall interrupt processing flow. 91C829-26 2006-03-15 TMP91C829 Interrupt processing Interrupt specified by micro DMA start vector? No Yes Micro DMA soft start request Clear interrupt requenst flag Interrupt vector value “V” read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA Count ← Count − 1 PUSH PC PUSH SR SR ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA transfer end interrupt (INTTC0 to INTTC3) PC ← (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST ← INTNEST − 1 End Figure 3.5.1 Interrupt and Micro DMA Processing Sequence 91C829-27 2006-03-15 TMP91C829 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (Indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register . However, if the priority level of the accepted interrupt is 7, the register’s value is set to 7. (4) The CPU increases the interrupt nesting counter INTNEST by 1 (+1). (5) The CPU jumps to the address indicated by the data at address “FFFF00H + interrupt vector” and starts the interrupt processing routine. The above processing time is 18 states (1.0 μs at 36 MHz) as the best case (16-bit data bus width and 0 waits). When the CPU completed the interrupt processing, use the RETI instruction to return to the main routine. RETI restores the contents of program counter (PC) and status register (SR) from the stack and decreases the interrupt nesting counter INTNEST by 1 (−1). Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request which has a priority level equal to or greater than the value of the CPU interrupt mask register comes out, the CPU accepts its interrupt. Then, the CPU interrupt mask register is set to the value of the priority level for the accepted interrupt plus 1 (+1). Therefore, if an interrupt is generated with a higher level than the current interrupt during its processing, the CPU accepts the later interrupt and goes to the nesting status of interrupt processing. Moreover, if the CPU receives another interrupt request while performing the said (1) to (5) processing steps of the current interrupt, the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine. Specifying DI as the start instruction disables maskable interrupt nesting. A reset initializes the interrupt mask register to 111, disabling all maskable interrupts. Table 3.5.1 shows the TMP91C829 interrupt vectors and micro DMA start vectors. The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector area. 91C829-28 2006-03-15 TMP91C829 Table 3.5.1 TMP91C829 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 − 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 − to − Maskable Non-mask able Type Interrupt Source or Source of Micro DMA Request Reset or “SWI0” instruction “SWI1” instruction Illegal instruction or “SWI2” instruction “SWI3” instruction “SWI4” instruction “SWI5” instruction “SWI6” instruction “SWI7” instruction NMI : NMI pin input Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H − 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H to 00FCH Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H − FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48F FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H to FFFFFCH Micro DMA Start Vector − − − − − − − − − − − 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH − to − INTWD: Watchdog timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input INT5: INT5 pin input (Reserved) (Reserved) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 (Reserved) (Reserved) INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) (Reserved) (Reserved) INTTBOF0: 16-bit timer 0 (Overflow) (Reserved) INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial transmission (Channel 1) (Reserved) (Reserved) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) (Reserved) 91C829-29 2006-03-15 TMP91C829 3.5.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C829 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source’s level. The micro DMA is ignored on = “7” The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of interrupts at any one time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. The data are automatically transferred once (1 or 2 or 4 bytes) from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decreased by 1 (−1). If the decreased result is 0, the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA start vector register DMAnV is cleared to 0, the next micro DMA is disabled and micro DMA processing completes. If the decreased result is other than 0, the micro DMA processing completes if it isn’t specified the say later burst mode. In this case, the micro DMA transfer end interrupt (INTTC0 to INTTC3) aren’t generated. If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. Therefore, if only using the interrupt for starting the micro DMA (Not using the interrupts as a general-purpose interrupt: level 1 to 6), first set the interrupts level to 0 (Interrupt requests disabled). If using micro DMA and general-purpose interrupts together, first set the level of the interrupt used to start micro DMA processing lower than all the other interrupt levels (Note). In this case, the cause of general interrupt is limited to the edge interrupt. The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined by the interrupt level and the default priority as same as the other maskable interrupt. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA start vector” (in the Figure 3.5.1 ) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91C829-30 2006-03-15 TMP91C829 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The upper eight bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/transfer destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O. For details of the transfer modes, see (4) “Detailed description of the transfer mode register”. As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 23 interrupts shown in the micro DMA start vectors of Figure 3.5.1 and by the micro DMA soft start, making a total of 24 interrupts. Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even numbered values.) 1 state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Transfer source address Transfer destination address D0 to D15 Input Output Figure 3.5.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (Gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle. State 6: Dummy cycle (The address bus remains unchanged from state 5.) States 7 to 8: Micro DMA write cycle. Note 1: If the source address area is an 8-bit bus, it is increased by 2 states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by 2 states. Note 2: If the destination address area is an 8-bit bus, it is increased by 2 states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by 2 states. 91C829-31 2006-03-15 TMP91C829 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C829 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each bitm micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to 0. Only one-channel can be set for micro DMA at once. (Do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read 1, micro DMA transfer isn’t started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA transfer counter doesn’t change. Don’t use Read-modify –write instruction to avoid writing to other bits by mistake. Symbol Name DMA DMAR request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 R/W 1 DMAR1 0 0 DMAR0 0 DMA request (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. Data setting for these registers is done by an “LDC cr,r” instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0: Only use LSB 24 bits. DMA destination address register 0: Only use LSB 24 bits. DMA counter register 0: 1 to 65536. DMA mode register 0. Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3. DMA destination address register 3. DMA counter register 3. DMA mode register 3. 91C829-32 2006-03-15 TMP91C829 (4) Detailed description of the transfer mode register 8 bits DMAM0 to 0 DMAM3 0 0 Mode Note: When setting a value in this register, write 0 to the upper 3 bits. Number of Minimum Execution States Execution Time at fc = 36 MHz 8 states 444 ns Number of Transfer Bytes 000 (Fixed) 000 00 Byte transfer Mode Description Transfer destination address INC mode .............. I/O to memory (DMADn+) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode .............. I/O to memory (DMADn−) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode .............. Memory to I/O (DMADn) ← (DMASn+) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode .............. Memory to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Fixed address mode .............. I/O to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444ns 12 states 667 ns 8 states 444ns 12 states 667 ns 8 states 444 ns 12 states 667 ns Counter mode ............. For counting number of times interrupt is generated. DMASn ← DMASn + 1 DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. 5 states 278 ns Note 1: “n” is the corresponding micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increment register value after transfer) DMADn−/DMASn−: Post-decrement (Decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (both translation and destination address area)/0 waits/ fc = 36 MHz/selected high-frequency mode (fc × 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91C829-33 2006-03-15 TMP91C829 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 26 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: • • • • • When reset occurs When the CPU reads the channel vector after accepted its interrupt When executing an instruction that clears the interrupt (Write micro DMA start vector to INTCLR register) When the CPU receives a micro DMA request (when micro DMA is set) When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) are fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value in the status register by the interrupt request signal with the priority value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 (+1) in the CPU SR . Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR. The interrupt controller also has registers (4 channels) used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (See Table 3.5.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter register (e.g., DMAS and DMAD) prior to the micro DMA processing. 91C829-34 2006-03-15 Interrupt controller Interrupt request F/F S R V = 20H V = 24H Interrupt request signal Priority encoder to CPU IFF2:0 EI1 to 7 DI Interrupt level detect 1 7 3 INTRQ2 to 0 6 6 Interrupt mask F/F RESET Q 1 CPU NMI RESET interrupt vector read INTWD Priority setting register Dn Dn + 1 D Q CLR A B C 3 3 Dn + 2 Decoder Y1 Y2 Y3 Y4 Y5 Y6 if INTRQ2 to 0 ≥ IFF 2 to 0 then 1. Interrupt request signal INT0 D0 D1 Reset Interrupt vector read Micro DMA acknowledge 26 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 4CH Interrupt vector generator Interrupt vector read D2 D3 D4 D5 D6 D7 Interrupt request F/F Dn + 3 SQ R Interrupt request flag 1 2 Highest A 3 priority B interrupt C 4 level select 5 6 7 INT1 INT2 INT3 INT4 INT5 INTTA0 During IDLE1 During STOP Figure 3.5.3 Block Diagram of Interrupt Controller 91C829-35 V = 9CH V = A0H V = A4H V = A8H V = ACH 4 input OR Soft start D Q CLR INTTC 34 S 6 Selector A B Micro DMA channel priority encoder 2 4 DMA0V DMA1V DMA2V DMA3V 0 1 2 3 Halt release RESET INT0 to INT4 NMI Micro DMA request if IFF = 7 then 0 Micro DMA counter 0 interrupt INTAD INTTC0 INTTC1 INTTC2 INTTC3 Micro DMA start vector setting register D5 D4 D3 D2 D1 D0 RESET 2 Micro DMA channel specification TMP91C829 2006-03-15 TMP91C829 (1) Interrupt priority setting registers Symbol Name INTE0 & INTAD enable INT1 & INT2 enable INT3 & INT4 enable Address 7 IADC R 0 I2C R 0 I4C R 0 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 4 IADM0 0 I2M0 0 I4M0 0 3 I0C R 0 I1C R 0 I3C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 INTE0AD 90H INTE12 91H INTE34 92H INTE5 INT5 enable 93H I5C R 0 I5M2 0 ITA0M2 0 ITA2M2 0 ITA4M2 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W I5M0 0 ITA0M0 0 ITA2M0 0 ITA4M0 INTETA01 INTTA0 & INTTA1 enable INTTA2 & INTTA3 enable INTTA4 & INTTA5 enable INTTA1 (TMRA1) 95H ITA1C R 0 ITA3C R 0 ITA5C R 0 0 0 ITA5M2 0 ITA3M2 ITA1M2 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 0 0 ITA5M0 INTTA5 (TMRA5) 97H ITA4C R 0 0 ITA3M0 INTTA3 (TMRA3) 96H ITA2C R 0 ITA1M0 ITA0C R 0 INTTA0 (TMRA0) INTTA2 (TMRA2) INTETA23 INTTA4 (TMRA4) INTETA45 0 0 0 lxxM2 0 0 0 0 Interrupt request flag 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C829-36 2006-03-15 TMP91C829 Symbol Name Interrupt enable TMRB0 Address 7 ITB01C R 0 6 5 4 3 ITB00C R 0 ITF0C R 0 2 ITB00M2 0 ITF0M2 0 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 1 ITB00M1 R/W 0 ITF0M1 R/W 0 IRX0M1 R/W 0 IRX1M1 R/W 0 ITC0M1 R/W 0 ITC2M1 R/W 0 0 ITB00M0 0 ITF0M0 0 IRX0M0 0 IRX1M0 0 ITC0M0 0 ITC2M0 0 INTTB01 (TMRB0) INTETB0 99H ITB01M2 ITB01M1 ITB01M0 R/W 0 0 0 (Reserved) 9BH INTTB00 (TMRB0) Interrupt enable INTETB0V TMRB0V (overflow) Interrupt enable serial 0 INTTBOF0 (overflow) INTTX0 9CH ITX0C R 0 0 INTTX1 9DH ITX1C R 0 0 INTTC1 A0H ITC1C R 0 ITC3C R 0 0 0 INTTC3 A1H ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 ITX1M2 ITX1M1 R/W 0 0 ITX1M0 IRX1C R 0 ITX0M2 ITX0M1 R/W 0 0 ITX0M0 IRX0C R 0 INTES0 INTES1 Interrupt enable serial 1 INTTC0 & INTTC1 enable INTTC2 & INTTC3 enable INTETC01 INTETC23 lxxM2 0 0 0 0 Interrupt request flag 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C829-37 2006-03-15 TMP91C829 (2) External interrupt control Symbol Name Address 7 − 6 I2EDGE 0 5 I2LE 0 4 I1DGE W 0 3 I1LE 0 2 I0EDGE 0 1 I0LE 0 0 NMIREE 0 1: Operates even on rising + falling edge of NMI IIMC0 0 Interrupt 8CH Write “0”. input mode (Prohibit control 0 RMW) INT2EDGE INT2EDGE INT1EDGE INT1EDGE INT0EDGE INT0 0: Rising 0: Edge 0: Rising 0: Edge 0: Rising 0: Edge 1: Falling 1: Level 1: Falling 1: Level 1: Falling 1: Level INT2 level enable 0 1 0 1 0 1 0 1 Edge detect INT H Level INT Edge detect INT H Level INT Edge detect INT H Level INT INT request generation at falling edge INT request generation at rising/falling edge INT1 level enable INT0 level enable NMI rising edge enable Symbol Name Address Interrupt input mode control1 7 6 I5EDGE 5 I5LE 0 4 I4EDGE W 0 3 I4LE 0 2 I3EDGE 0 1 I3LE 0 0 IIMC1 8DH (Prohibit RMW) 0 INT5EDGE INT5 0: Rising 0: Edge 1: Falling 1: Level INT4EDGE INT4 0: Rising 0: Edge 1: Falling 1: Level INT3EDGE INT3 0: Rising 0: Edge 1: Falling 1: Level INT5 level enable 0 1 0 1 0 1 Edge detect INT H Level INT Edge detect INT H Level INT Edge detect INT H Level INT INT4 level enable INT3 level enable When switching IIMC0 and IIMC1 registers, first every FC registers in port which built-in INT function set to 0. 91C829-38 2006-03-15 TMP91C829 Setting functions on external interrupt pins Interrupt Pin NMI Mode Falling edge Both falling and rising edges Rising edge Setting Method = 0 = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 = 0, = 0 = 0, = 1 = 1, = 0 = 1, = 1 INT0 Falling edge High level Low level Rising edge INT1 Falling edge High level Low level Rising edge INT2 Falling edge High level Low level Rising edge INT3 Falling edge High level Low level Rising edge INT4 Falling edge High level Low level Rising edge INT5 Falling edge High level Low level (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.5.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH Symbol Name Address Interrupt INTCLR clear control 88H (Prohibit RMW) Clears interrupt request flag INT0. 6 5 CLRV5 0 7 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 Interrupt vector 91C829-39 2006-03-15 TMP91C829 (4) Micro DMA start vector registers These registers assign micro DMA processing to sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel’s micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) Symbol Name DMA0 start vector Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0V 80H 0 DMA1V5 81H 0 DMA2V5 82H 0 DMA3V5 83H 0 DMA0 start vector DMA1 start vector R/W DMA1 start vector DMA2 start vector R/W DMA2 start vector DMA3 start vector R/W DMA3 start vector DMA1V DMA2V DMA3V (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name Address DMA software request register DMA burst register 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 DMAR 1: DMA software request DMAB 8AH 0 1:DMA burst request 91C829-40 2006-03-15 TMP91C829 (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0008H and jump to interrupt vector address FFFF08H. To avoid the avobe problem, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1 instructions (ex. “NOP” * 1 time). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, take care as the following 2 circuits are exceptional and demand special attention. INT0 to INT5 level mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. (For example: In case of INT0) If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC0), 00H; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH; Clears interrupt request flag. NOP ; Wait EI instruction EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the Serial Channel Receive Buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0 to INT5: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. (H → L) INTRX: Instructions which read the receive buffer. 91C829-41 2006-03-15 TMP91C829 3.6 Port Functions The TMP91C829 features 53 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin. Table 3.6.2 lists the I/O registers and their specifications. Table 3.6.1 Port Functions (R: ↑ = with programmable pull-up resistor) Direction Setting Unit Bit Bit Bit Bit Bit Bit − − − − − − − − − − Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit − − − − − − − Bit Bit Bit Bit Bit (Fixed) (Fixed) Bit Bit Port Name Port 1 Port 2 Port 5 Pin Name P10 to P17 P20 to P27 P53 P54 P55 P56 Number of Pins 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 Direction I/O Output I/O I/O I/O I/O Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O I/O R − − Pin Name for Internal Function D8 to D15 A16 to A23 BUSRQ BUSAK WAIT INT0 CS0 CS1 CS2 CS3 Port 6 P60 P61 P62 P63 Port 7 P70 P71 P72 P73 P74 P75 TA0IN/INT1 TA1OUT TA3OUT/INT2 TA4IN/INT3 TA5OUT INT4 TXD0 RXD0 SCLK0/ CTS0 STS0 Port 8 P80 P81 P82 P83 P84 P85 P86 P87 TXD1 RXD1 SCLK1/ CTS1 STS1 Port 9 P90 P93 P94 P95 P96 INT5 TB0IN0 TB0IN1 TB0OUT0 TB0OUT1 ADTRG Port A Port Z PA3 PA0 to PA7 PZ2 PZ3 AN0 to AN7 HWR 91C829-42 2006-03-15 TMP91C829 Table 3.6.2 I/O Registers and Their Specifications (1/2) Port Port 1 Name P10 to P17 Input port Output port D8 to D15 bus Specification Pn X X X X X 0 1 X X 0 1 X 0 1 X 0 1 0 1 X X 0 1 X 0 1 X X X X X X X X X X X X X X X X X I/O Registers PnCR 0 1 1 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 1 None 1 1 1 0 1 0 0 1 1 0 0 0 1 0 0 0 None 1 1 1 1 None 1 1 1 None 0 0 0 1 1 0 0 0 1 None PnFC 0 0 1 0 1 0 0 0 1 Port 2 Port Z P20 to P27 PZ2 Output port A16 to A23 output Input port (without PU) Input port (with PU) Output port HWR output PZ3 Input port (without PU) Input port (with PU) Output port Port 5 P53 Input port (without PU) Input port (with PU) Output port BUSRQ input (without PU) BUSRQ input (with PU) P54 Input port (without PU) Input port (with PU) Output port BUSAK output P55 Input port/WAIT input (without PU) Input port/WAIT input (with PU) Output port P56 Input port/INT0 input (without PU) Input port/INT0 input (with PU) Output port Port 6 P60 to P63 P60 P61 P62 P63 Output port CS0 output CS1 output CS2 output CS3 output Port 7 P70 to P75 P70 P71 P72 P73 P74 P75 Input port Output port TA0IN input INT1 input TA1OUT output TA3OUT output INT2 input TA4IN input INT3 input TA5OUT output INT4 input X: Don’t care 91C829-43 2006-03-15 TMP91C829 Table 3.6.3 I/O Registers and Their Specifications (2/2) Port Port 8 P80 Name Specification Input port (without PU) Input port (with PU) Output port TXD0 output I/O Registers Pn 0 1 X X 0 1 X 0 1 X X 0 1 X X 0 1 X X 0 1 X 0 1 X X 0 1 X X X X X X X X X X X X X X X None PnCR 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 PnFC 0 0 0 1 None 0 0 0 1 0 0 0 1 0 0 0 1 None 0 0 0 1 0 0 0 1 0 0 1 P81 Input port/RXD0 input (without PU) Input port/RXD0 input (with PU) Output port P82 Input port/SCLK0/CTS0 input (without PU) Input port/SCLK0/CTS0 input (with PU) Output port SCLK0 output P83 Input port (without PU) Input port (with PU) Output port STS0 output P84 Input port (without PU) Input port (with PU) Output port TXD1 output P85 Input port/RXD1 input (without PU) Input port/RXD1 input (with PU) Output port P86 Input port/SCLK1/CTS1 input (without PU) Input port/SCLK1/CTS1 input (with PU) Output port SCLK1 output P87 Input port (without PU) Input port (with PU) Output port STS1 output Port 9 P90 Input port Output port INT5 input P93 to P96 P93 P94 P95 P96 Port A PA3 PA0 to PA7 X: Don’t care Input port Output port TB0IN0 input TB0IN1 input TB0OUT0 output TB0OUT1 output Input port ADTRG input Input port AN0 to AN7 None 1 1 Note 1: When PA1 to PA4 are used as AD converter input channels, a 3-bit field in the AD mode control register ADMOD1 is used to select the channel. Note 2: When PA0 is used as the ADTRG input, ADMOD1 is used to enable external trigger input. 91C829-44 2006-03-15 TMP91C829 After a reset the port pins listed below function as general-purpose I/O port pins. A reset sets I/O pins which can be programmed for either input or output to be input port pins. Setting the port pins for internal function use must be done in software. Note about bus release and programmable pull-up I/O port pins When the bus is released (e.g., when BUSAK = 0), the output buffers for D0 to D15, A0 to A23, and the control signals ( RD , WR , HWR and CS0 to CS3 ) are off and are set to high-impedance. However, the output of built-in programmable pull-up resistors are kept before the bus is released. These programmable pull-up resistors can be selected on/off by programmable when they are used as the input ports. When they are used as output ports, they cannot be turned on/off in software. Table 3.6.4 shows the pin states after the bus has been released. Table 3.6.4 Pin States (after bus release) Pin Names P10 to P17 (D8 to D15) P20 to P27 (A16 to 23) RD WR Pin State (after bus release) Used as Port Unchanged (e.g., not set to high-impedance (High-Z)) Unchanged (e.g., not set to high-impedance (High-Z)) ↑ First all bits are set high, then they are set to high-impedance (High-Z). ↑ The output buffer is set to off. ↑ The programmable pull-up resistor is set to on irrespective of the output latch. Used for Function High-impedance (High-Z) PZ2 ( HWR ) P60 ( CS0 ) P61 ( CS1 ) P62 ( CS2 ) P63 ( CS3 ) ↑ ↑ 91C829-45 2006-03-15 TMP91C829 Figure 3.6.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate. As a result, the watchdog timer also continues to run. Therefore, the bus release time must be taken into account and care must be taken when setting the detection time for the WDT. RD WR PZ2 ( HWR ) System control bus P60 ( CS0 ) P61 ( CS1 ) P62 ( CS2 ) P63 ( CS3 ) P20 (A16) to P27 (A23) Address bus (A23 to A16) Figure 3.6.1 Interface Circuit Example (Using bus release function) The above circuit is necessary to set the signal level when the bus is released. A reset sets ( RD ) and ( WR ), P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 ), P63 ( CS3 ) to output, and PZ2 ( HWR ) and P54 ( BUSAK ) to input with pull-up resistor. 91C829-46 2006-03-15 TMP91C829 3.6.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting, the control register P1CR to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (D8 to D15). In case of AM1 = 0, and AM = 1 (outside 16-bit data bus), port 1 always functions as the data bus (D8 to D15) irrespective of the setting in P1CR control register. Reset Direction control (on bit basis) P1CR write Output latch Internal data bus Output buffer P1 write Port 1 P10 to P17 (D8 to D15) P1 Read Figure 3.6.2 Port 1 Port 1 Register 7 P1 Bit symbol (0001H) Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR Bit symbol (0004H) Read/Write After reset (Note) Function P17C 6 P16C 5 P15C 4 P14C W 3 P13C 2 P12C 1 P11C 0 P10C 0/1 0/1 0/1 0/1 0: Input 0/1 1: Output 0/1 0/1 0/1 Note1: Read-modify-write is prohibited for P1CR. Note2: It is set to “Port” or “Data bus” by AM pins state. Port 1 I/O setting 0 1 Input Output Figure 3.6.3 Register for Port 1 91C829-47 2006-03-15 TMP91C829 3.6.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus. Reset S Function control (on bits basis) Internal data bus P2FC write S Output latch B P2 write A selector Port 2 P20 to P27 (A16 to A23) Output buffer P2 read Internal A16 to A23 Figure 3.6.4 Port 2 Port 2 Register 7 P2 Bit symbol (0006H) Read/Write After reset P27 1 6 P26 1 5 P25 1 4 P24 R/W 1 3 P23 1 2 P22 1 1 P21 1 0 P20 1 Port 2 Function Register 7 P2FC (0009H) Read/Write After reset Function Note: Read-modify-write is prohibited for P2FC. Bit symbol P27F 1 6 P26F 1 5 P25F 1 0: Port 4 P24F W 1 3 P23F 1 2 P22F 1 1 P21F 1 0 P20F 1 1: Address bus (A23 to A16) Figure 3.6.5 Register for Port 2 91C829-48 2006-03-15 TMP91C829 3.6.3 Port 5 (P53 to P56) Port 5 is an 4-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and the function register P5FC to 0 and sets P52 to P56 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port, port 5 also functions as I/O for the CPU’s control/status signal. Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Output latch P5 write P-ch (Programmable pull up) P53 ( BUSRQ ) Internal BUSRQ P5 read Figure 3.6.6 Port 53 91C829-49 2006-03-15 TMP91C829 Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Selector S Output latch P5 write BUSAK P-ch (Programmable pull up) A B P54( BUSAK ) Output buffer P5 read Figure 3.6.7 Port 54 Reset Direction control (on bit basis) P5CR write Internal data bus S Output latch P5 write P-ch (Programmable pull up) P55 ( WAIT ) Output buffer P5 read Internal WAIT Figure 3.6.8 Port 55 91C829-50 2006-03-15 TMP91C829 Reset Direction control (on bit basis) P5CR write Internal data bus Function control (on bit basis) P5FC write P-ch (Programmable pull up) S Output latch P5 write S P5 write B P56 (INT0) Output buffer selector A Level or edge and Rising edge or falling edge IIMC0 INT0 Figure 3.6.9 Port 56 91C829-51 2006-03-15 TMP91C829 Port 5 Register 7 P5 Bit symbol (000DH) Read/Write After reset Function 6 P56 5 P55 R/W 4 P54 3 P53 2 1 0 Data from external port (Output latch register is set to 1.) 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port 5 Control Register 7 P5CR Bit symbol (0010H) Read/Write After reset Function 6 P56C 0 5 P55C W 0 0: Input 4 P54C 0 1: Output 3 P53C 0 2 1 0 I/O setting 0 1 Input Output Port 5 Function Register 7 P5FC Bit symbol (0011H) Read/Write After reset Function 6 P56F W 0 0: Port 1: INT0 input 5 4 P54F W 0 0: Port 1: BUSAK 3 P53F 0 0: Port 1: BUSRQ 2 1 0 Note 1: Note 2: Read-modify-write is prohibited for register P5CR, P5FC. When port 5 is used in the input mode, P5 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When P55 pin is used as a WAIT pin, set P5CR to 0 and chip select/WAIT control register to 010. Figure 3.6.10 Register for Port 5 91C829-52 2006-03-15 TMP91C829 3.6.4 Port 6 (P60 to P63) Port 6 is a 4-bit output port. When reset, the P62 latch is cleared to 0 while the P60 to P63 output latches are set to 1. In addition to functioning as an output port, this port can output standard chip select signals ( CS0 to CS3 ). These settings are made by using the P6FC register. When reset, the P6FC register has all of its bits cleared to 0, so that the port is set for output mode. Reset Internal data bus Funtion control (on bit basis) P6FC write S S Output lacth P6 write A B Selector Output buffer P60 ( CS0 ), P61 ( CS1 ), P63 ( CS3 ) P6 read CS0 , CS1 , CS3 Figure 3.6.11 Port 60, 61, 63 Reset Function control Internal data bus (on bit basis) P6FC write S Selector R Output latch P6 write CS2 A B P62 ( CS2 ) Output buffer P6 read Figure 3.6.12 Port 62 91C829-53 2006-03-15 TMP91C829 Port 6 Register 7 P6 Bit symbol (0012H) Read/Write After reset 6 5 4 3 P63 1 2 P62 R/W 0 1 P61 1 0 P60 1 Port 6 Function Register 7 P6FC Bit symbol After reset Function Note: Read-modify-write is prohibited for the registers P6FC. 0 1 0 1 0 1 0 1 Port (P60) CS0 6 5 4 3 P63F 0 2 P62F W 1 P61F 0 P60F 0 (0015H) Read/Write 0 0 0: Port 1 1: CS Port (P61) CS1 Port (P62) CS2 Port (P63) CS3 Figure 3.6.13 Register for Port 6 91C829-54 2006-03-15 TMP91C829 3.6.5 Port 7 (P70 to P75) Port 7 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 7 to be an input port. In addition to functioning as a general-purpose I/O port, the individual port can also have the following functions: Port 70 and 73 can function as the inputs TA0IN and TA4IN to the 8-bit timer, and port 71, 72 and 74 can function as the 8-bit timer outputs TA1OUT, TA3OUT and TA5OUT. For each of the output pins, timer output can be enabled by writing a 1 to the corresponding bit in the port 7 function register (P7FC). Resetting resets all bits of the registers P7CR and P7FC to 0, and sets all bits to be input port pins. Reset Direction control (on bit basis) P7CR write Function control (on bit basis) Internal data bus P7FC write S Output latch SB P7 write Selector INT1 INT3 INT4 P70 (TA0IN/INT1) P73 (TA4IN/INT3) P75 (INT4) P7 read A Level or edge and Rising edge or falling edge TA0IN TA4IN IIMC0 IIMC1 IIMC1 Figure 3.6.14 Port 70, 73, 75 91C829-55 2006-03-15 TMP91C829 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus S Output latch P7 write AS Selector Timer F/F OUT B B Selector P7 read SA P71 (TA1OUT) P74 (TA5OUT) TA1OUT: TMRA1 TA5OUT: TMRA5 Figure 3.6.15 Port 71, 74 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus Function control (on bit basis) P7FC write S Output latch Timer F/F OUT AS Selector B B Selector P72 (TA3OUT/INT2) P7 write (TA3OUT: TMRA3) P7 read SA INT2 Edge or level and Rising edge or falling edge IIMC0 Figure 3.6.16 Port 72 91C829-56 2006-03-15 TMP91C829 Port 7 Register 7 P7 Bit symbol (0013H) Read/Write After reset 6 5 P75 4 P74 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to 1.) Port 7 Control Register 7 P7CR Bit symbol After reset Function (0016H) Read/Write 0 0 0 6 5 P75C 4 P74C 3 P73C W 2 P72C 0 1 P71C 0 0 P70C 0 0: Input 1: Output Port 7 I/O setting 0 1 Input Output Port 6 Function Register 7 P7FC Bit symbol (0017H) Read/Write After reset Function 6 P72F2 W 0 0: Port 1: INT2 input 5 P75F W 0 0: Port 1: INT4 input 4 P74F 0 0: Port 3 P73F W 0 0: Port input 2 P72F1 W 0 0: Port 1 P71F 0 0: Port 0 P70F W 0 0: Port input 1: TA5OUT 1: INT3 1: TA3OUT 1: TA1OUT 1: INT1 Note: Read-modify-write is prohibited for the registers P7CR and P7FC. Setting P71 as timer output 1 P7FC P7CR Setting P72 as timer output 3 P7FC P7CR Setting P74 as timer output 5 P7FC P7CR 1 1 1 1 1 1 Figure 3.6.17 Register for Port 7 91C829-57 2006-03-15 TMP91C829 3.6.6 Port 8 (P80 to P87) Port 80 to 87 constitute a 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets P80 to P87 to be an input port. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port, P80 to P87 can also function as the I/O for serial channels 0. These function can be enabled for I/O by writing a 1 to the corresponding bit of the port 8 function register (P8FC). Resetting resets all bits of the registers P8CR and P8FC to 0 and sets all bits to be input port (with pull-up resistors). (1) Port 80 (TXD0), 84 (TXD1) As well as functioning as I/O port, port 80, 84 can also function as serial channel TXD output pins. These port feature a programmable open-drain function. Reset Derection control (on bit basis) P8CR write P-ch (Programmable pul up) Internal data bus Function control (on bit basis) P8FC write S Output latch P8 write TXD0 or TXD1 A S P80 (TXD0) P84 (TXD1) Selector B S B Open-drain possible ODE output buffer Selector P8 read A Figure 3.6.18 Port 80, 84 91C829-58 2006-03-15 TMP91C829 (2) Port 81 (RXD0), 85 (RXD1) Port 81, 85 are I/O port and can also be used as RXD input pin for the serial channels. Reset P-ch (Programmable pull up) Derection control (on bit basis) P8CR write S Output latch P8 write P8 read RXD0 or RXD1 Internal data bus S B Output buffer P81 (RXD0) P85 (RXD1) Selector A Figure 3.6.19 Port 81, 85 (3) Port 82 ( CTS0 /SCLK0), 86 ( CTS1 /SCLK1) Port 82, 86 are I/O port and can also be used as the CTS input pins or SCLK I/O pins for the serial channels. Reset Direction control (on bit basis) P-ch (Programmable pull up) P8CR write Function contorl (on bit basis) P8FC write S Output latch P8 write SCLK0 SCLK1 Internal data bus A S P82 (SCLK0/ CTS0 ) P86 (SCLK1/ CTS1 ) Selector B SB Selector P8 read SCLK0, CTS0 input SCLK1, CTS1 input A Figure 3.6.20 Port 82, 86 91C829-59 2006-03-15 TMP91C829 (4) Port 83 ( STS0 ), 87 ( STS1 ) Port 83, 87 are I/O port and can also be used as STS output for the received data request signal. Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch P8 write STS0 or STS1 Internal data bus P-ch (Programmable pull up) S A Y Selector B S B Selector Y A P83 ( STS0 ) P87 ( STS1 ) P8 read Figure 3.6.21 Port 83, 87 91C829-60 2006-03-15 TMP91C829 Port 8 Register 7 P8 Bit symbol (0018H) Read/Write After reset Function P87 6 P86 5 P85 4 P84 R/W 3 P83 2 P82 1 P81 0 P80 Data from external port (Output latch register is set to 1.) 0(Output latch register) : Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON Port 8 Control Register 7 P8CR Bit symbol (001AH) Read/Write After reset Function P87C 0 6 P86C 0 5 P85C 0 4 P84C W 0 3 P83C 0 2 P82C 0 1 P81C 0 0 P80C 0 0: Input 1: Output Port 8 I/O setting 0 1 Input Output Port 8 Function Register 7 P8FC Bit symbol (001BH) Read/Write After reset Function P87F W 0 0: Port 1: STS1 output 6 P86F W 0 0: Port 1: SCLK1 output 5 4 P84F W 0 0: Port 1: TXD1 output 3 P83F W 0 0: Port 1: STS 0 output 2 P82F W 0 0: Port 1: SCLK0 output 1 0 P80F W 0 0: Port 1: TXD0 input To set P80, 84 for TXD0, TXD1 output P8FC P8CR Note 1: Read-modify-write is prohibited for the registers P8CR and P8FC. Note 2: Writing 1 to bit0 of the ODE register sets the TXD0, 1 pin to be open drain. No register is provided for switching between the I/O port and RXD input functions of the P81/RXD0, P85/RXD1 pin. Hence, when port 8 is used as an input port, the serial data input signals received on those pins are also input to the SIO. 1 1 To set P82, P86 for SCLK0, SCLK1 output P8FC P8CR 1 1 To set P83, P87 for STS 0 , STS1 output P8FC P8CR 1 1 Figure 3.6.22 Register for Port 8 91C829-61 2006-03-15 TMP91C829 3.6.7 Port 9 (P90, P93 to P96) Port 9 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output, Resetting sets port 9 to be an input port, it also sets all bits in the output latch register P9 to 1. In addtion to functioning as a general-purpose I/O port, the various pins of port 9 can also function as the clock input for the 16-bit timer flipflop putput, on as input INT5. These functions cn be enabled by writing a 1 to the corresponding bits in the port 9 function registers (P9FC). (1) P90 Reset Direction control (on bit basis) P9CR write Internal data bus S Output latch P90 (INT5) P9 write S B Selector Y A P9 read INT5 Level or edge and Rising edge or falling edge IIMC1 P9FC Figure 3.6.23 Port 90 91C829-62 2006-03-15 TMP91C829 (2) P93 to P96 Reset Direction control (on bit basis) P9CR write S Output latch P9 write P9 read TB0IN0 TB0IN1 Internal data bus A Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch A P9 write Timer F/F OUT TB0OUT0: TMRB0 TB0OUT1: TMRB0 P93 (TB0IN0) P94 (TB0IN1) S B Selector S P95 (TB0OUT0) P96 (TB0OUT1) Selector B B Selector P9 read SA Figure 3.6.24 Port P93 to P96 91C829-63 2006-03-15 TMP91C829 Port 9 Register 7 P9 Bit symbol (0019H) Read/Write After reset 6 P96 5 P95 R/W 4 P94 3 P93 2 1 0 P90 R/W Data from external port (Output latch register is set to 1.) Data from external port (Output latch register is set to 1.) Port 9 Control Register 7 P9CR Bit symbol (001CH) Read/Write After reset Function 6 P96C 0 5 P95C W 0 0: Input 1: Output 4 P94C 0 3 P93C 0 2 1 0 P90C W 0 0: Input 1: Output Port 9 I/O setting 0 1 Input Output Port 9 Function Register 7 P9FC Bit symbol (001DH) Read/Write After reset Function 6 P96F W 0 5 P95F W 0 4 3 2 1 0 P90F W 0 0: Port 1: INT5 input 0: Port 0: Port 1: TB0OUT1 1: TB0OUT0 To set P95 for timer 8 output 1 1 P9FC P9CR To set P96 for timer 9 output Note: Read-modify-write is prohibited for the registers P9CR and P9FC. 1 1 P9FC P9CR Figure 3.6.25 Register for Port 9 91C829-64 2006-03-15 TMP91C829 3.6.8 Port A (PA0 to PA7) Port A is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. PA0 to PA7 Internal data bus Port A read ( ADTRG , AN0 to AN7) AD read Conversion result register AD converter Channel selector ADTRG (Only PA3) Figure 3.6.26 Port A Port A Register 7 PA Bit symbol (0019H) Read/Write After reset PA7 6 PA6 5 PA5 4 PA4 R 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port. Note: The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.6.27 Register for Port A 91C829-65 2006-03-15 TMP91C829 3.6.9 Port Z (PZ2, PZ3) Port Z is a 4-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ to 1, the control register PZCR and the function register PZFC to 0 and sets PZ2 and PZ3 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port. Port Z also functions as I/O for the CPU’s control/status signal. Reset Direction control (on bit basis) PZCR write Function control Internal data bus (on bit basis) PZFC write S Selector S Output latch PZ write HWR P-ch (Programmable pull up) A B PZ2( HWR ) Output buffer PZ read Figure 3.6.28 Port Z2 Reset Direction control (on bit basis) Internal data bus PZCR write S Output latch PZ write PZ read S Output buffer B P-ch (Programmable pull up) PZ3 Selector A Figure 3.6.29 Port Z3 91C829-66 2006-03-15 TMP91C829 Port Z Register 7 PZ Bit symbol (007DH) Read/Write After reset 6 5 4 3 PZ3 R/W 2 PZ2 1 0 Data from external port (Output latch register is set to 1.) Port Z Control Register 7 PZCR Bit symbol (007EH) Read/Write After reset Function 6 5 4 3 PZ3 W 0 2 PZ2 0 1 0 0: Input 1: Output Setting port Z as I/O 0 1 Input Output Port Z Control Register 7 PZFC Bit symbol (007FH) Read/Write After reset Function 6 5 4 3 2 PZ2F W 0 0: Port 1: HWR 1 0 Note: Read-modify –write is prohibited for the registers PZCR and PZFC. Figure 3.6.30 Register for Port Z 91C829-67 2006-03-15 TMP91C829 3.7 Chip Select/Wait Controller On the TMP91C829, four user specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). The pins CS0 to CS3 (which can also function as P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function register P6FC must be set. External connection of ROM and SRAM is supported. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin which controls these states is the bus wait request pin ( WAIT ). 3.7.1 Specifying an Address Area The address areas CS0 to CS3 are specified using the memory start address registers (MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3). During each bus cycle, a compare operation is performed to determine whether or not the address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the result of the comparison is a match, it indicates that the corresponding CS area is to be accessed. If so, the corresponding CS0 to CS3 pin outputs the chip select signal and the bus cycle proceeds according to the settings in the corresponding B0CS to B3CS chip select/wait control register. (See 3.7.2 “Chip Select/Wait Control Registers”.) 91C829-68 2006-03-15 TMP91C829 (1) Memory start address registers Figure 3.7.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The eight most significant bits (A23 to A16) of the start address should be set in . The 16 least significant bits of the start address (A15 to A0) are fixed to 0. Thus the start address can only be set to lie on a 64-Kbyte boundary, starting from 000000H. Figure 3.7.2 shows the relationship between the value set in the start address register and the start address. Memory Start Address Registers (for areas CS0 to CS3) 7 MSAR0 (00C8H)/ Bit symbol MSAR1 (00CAH) Read/Write MSAR2 (00CCH)/ After reset MSAR3 (00CEH) Function S23 1 6 S22 1 5 S21 1 4 S20 R/W 1 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.7.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Value in start address register (MSAR0 to MSAR3) 000000H .................... 00H 010000H .................... 01H 020000H .................... 02H 030000H .................... 03H 040000H .................... 04H 050000H .................... 05H 060000H .................... 06H to to FF0000H .................... FFH FFFFFFH Figure 3.7.2 Relationship between Start Address and Start Address Register Value 91C829-69 2006-03-15 TMP91C829 (2) Memory address mask registers Figure 3.7.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0 to MAMR3) which is set to 1 masks the corresponding bit of the start address which has been set in the corresponding memory start address register (MSAR0 to MSAR3). The compare operation used to determine whether or not a bus address is in one of the areas CS0 to CS3 only compares address bits for which a 0 has been set in the corresponding bit position in the corresponding memory address mask register. Also, the address bits which each memory address mask register can mask vary from register to register; hence, the possible size settings for the areas CS0 to CS3 differ accordingly. Memory Address Mask Register (for CS0 area) 7 MAMR0 Bit symbol (00C9H) Read/Write After reset Function V20 1 6 V19 1 5 V18 1 4 V17 R/W 1 3 V16 1 2 V15 1 1 V14 to 9 1 0 V8 1 Sets size of CS0 area. 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes. Memory Address Mask Register (CS1) 7 MAMR1 Bit symbol (00CBH) Read/Write After reset Function V21 1 6 V20 1 5 V19 1 4 V18 R/W 1 3 V17 1 2 V16 1 1 V15 to 9 1 0 V8 1 Sets size of CS1 area. 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 MAMR2 (00CDH)/ Bit symbol MAMR3 (00CFH) Read/Write After reset Function V22 1 6 V21 1 5 V20 1 4 V19 R/W 1 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area. 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.7.3 Memory Address Mask Registers 91C829-70 2006-03-15 TMP91C829 (3) Setting memory start addresses and address areas Figure 3.7.4 shows an example in which CS0 is specified to be a 64-Kbyte address area starting at 010000H. First, MSAR0, the eight most significant bits of the start address register and which correspond to the memory start address, are set to 01H. Next, based on the desired CS0 area size, the difference between the start address and the end address (01FFFFH) is calculated. Bits 20 to 8 of this result constitute the mask value for the desired CS0 area size. Setting this value in MAMR0 (Bits 20 to 8 of the memory address mask register) sets the desired area size for CS0. In this example 07H is set in MAMR0, specifying an area size of 64 Kbytes. 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CS0 area size (64 Kbytes) Memory start address S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 to V9 V8 MSMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.7.4 Example Showing How to Set the CS0 Area A reset sets MSAR0 to MSAR3, and MAMR0 to MAMR3 to FFH. In addition, B0CS, B1CS and B3CS are reset to 0, disabling the CS0, CS1, and CS3 areas. However, since a reset resets B2CS to 0 and sets B2CS to 1, CS2 is enabled with the address range 003000H to 01F7FFH, 020000H to FFFFFFH. When addresses outside the areas specified as CS0 to CS3 are accessed, the bus width and number of waits specified in BEXCS are used. (See 3.7.2 “Chip Select/Wait Controller”.) 91C829-71 2006-03-15 TMP91C829 (4) Address area size specification Table 3.7.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A “Δ” indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register. If an area size for a CS area marked “Δ” in the table is to be set, the start address must either be set to 000000H or to a value that is greater than 000000H by an integer multiple of the desired area size. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the lowest-numbered CS area has highest priority (e.g., CS0 has a higher priority than any other area). Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. b. Invalid start addresses 64 Kbytes 128 Kbytes 128 Kbytes 000000H 010000H 030000H 050000H This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.7.1 Valid Area Sizes for Each CS Area Size (bytes) CS area 256 512 32 K 64 K 128 K Δ Δ Δ Δ 256 K Δ Δ Δ Δ 512 K Δ Δ Δ Δ 1M Δ Δ Δ Δ 2M Δ Δ Δ Δ 4M Δ Δ Δ 8M CS0 CS1 CS2 CS3 ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ Δ Δ 91C829-72 2006-03-15 TMP91C829 3.7.2 Chip Select/Wait Control Registers Figure 3.7.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width, and number of wait states for each address area (CS0 to CS3 plus any other) are set in the respective chip select/wait control registers, B0CS to B3CS or BEXCS. Chip Select/Wait Control Register 7 B0CS (00C0H) Readmodifywrite instructions are prohibited. 6 5 B0OM1 4 B0OM0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 1 B0W1 0 B0W0 Bit symbol Read/Write After reset Function B0E W 0 0: Disable 1: Enable 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: B1OM1 B1OM0 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B1W2 W B1W1 B1W0 B1CS (00C1H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B1E W 0 0: Disable 1: Enable B1BUS 0 Data bus width 0: 16 bits 1: 8 bits 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area B2OM1 B2OM0 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B2W2 B2W1 B2W0 B2CS (00C2H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B2E 1 0: Disable 1: Enable B2BUS W 0 Data bus width 0: 16 bits 1: 8 bits 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: B3OM1 B3OM0 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B3W2 W B3W1 B3W0 B3CS (00C3H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B3E W 0 0: Disable 1: Enable B3BUS 0 Data bus width 0: 16 bits 1: 8 bits 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don’t care 11: 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits BEXW2 W BEXW1 BEXW0 BEXCS (00C7H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits Master enable bit 0 1 CS area disable CS area enable Chip select output waveform selection 00 For ROM/SRAM 01 10 Don’t care 11 Number of address area waits (See 3.7.2 (3) “Wait control”.) Data bus width selection 0 1 16-bit data bus 8-bit data bus CS2 area selection 0 1 16-Mbyte area Specified address area Figure 3.7.5 Chip Select/Wait Control Registers 91C829-73 2006-03-15 TMP91C829 (1) Master enable bits Bit7 (, , , or ) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables the settings. A reset disables , and (e.g., sets them to 0) and enables (e.g., sets it to 1). Hence after a reset only the CS2 area is enabled. (2) Data bus width selection Bit3 (, , , , or ) of a chip select/wait control register specifies the width of the data bus. This bit should be set to 0 when memory is to be accessed using a 16-bit data bus, and to 1 when an 8-bit data bus is to be used. This process of changing the data bus width according to the address being accessed is known as dynamic bus sizing. For details of this bus operation see Figure 3.7.2. Table 3.7.2 Dynamic Bus Sizing Operand Data Operand Start Memory Data Bus Width Address Bus Width 8 bits 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 32 bits 2n + 0 (Even number) 8 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 1 (Odd number) 8 bits 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 16 bits 2n + 1 2n + 2 2n + 4 Input data in bit positions marked xxxxx is ignored during a read. During a write, the bus lines corresponding to these bit positions go high-impedance and the write strobe signal for the bus remains inactive. 91C829-74 2006-03-15 TMP91C829 (3) Wait control Bits 0 to 2 (, , , , or ) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits. Bit settings other than those listed in the table should not be made. Table 3.7.3 Wait Operation Settings 000 001 010 Number of Waits 2 waits 1 wait (1 + N) waits Wait Operation Inserts a wait of two states, irrespective of the WAIT pin state. Inserts a wait of one state, irrespective of the WAIT pin state. Inserts one wait state, then continuously samples the state of the WAIT pin. While the WAIT pin remains low, the wait continues; the bus cycle is prolonged until the pin goes high. Ends the bus cycle without a wait, regardless of the WAIT pin state. Do not set. 011 1xx 0 waits Reserved A reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS (bit6 of the chip select/wait control register for CS2) to 0 designates the 16-Mbyte area 001800H to 01F7FFH, 020000H to FFFFFFH as the CS2 area. Setting B2CS to 1 designates the address area specified by the start address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if B2CS = 1, CS2 is specified in the same manner as CS0, CS1, and CS3). A reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area. 91C829-75 2006-03-15 TMP91C829 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: a. b. c. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 . The CS0 to CS3 pins can also function as pins P60 to P63. To output a chip select signal using one of these pins, set the corresponding bit in the port 6 function register P6FC to 1. If a CS0 to CS3 address is specified which is actually an internal I/O, RAM or ROM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. Example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H ............Start address: 010000H MAMR0 = 07H...........Address area: 64 Kbytes B0CS = 83H ...............ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled. 91C829-76 2006-03-15 TMP91C829 3.7.3 Connecting External Memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91C829. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C829 CS0 CS1 CS2 Address bus CS CS CS CS A0 to A23 D8 to D15 D0 to D7 RD WR Upper byte ROM OE OE Lower byte ROM 8-bit RAM OE WE 8-bit I/O OE WE Figure 3.7.6 Example of External Memory Connection (ROM uses 16-bit bus; RAM and I/O use 8-bit bus.) A reset clears all bits of the port 4 control register P6CR and the port 6 function register P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91C829-77 2006-03-15 TMP91C829 3.8 8-Bit Timers (TMRA) The TMP91C829 features six built-in 8-bit timers. These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module consists of two channels and can operate in any of the following four operating modes. • • • • 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG − Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM − Variable duty cycle with constant period) Figure 3.8.1 to 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (Special function registers). Each of the four modules (TMRA01, TMRA23, and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. Table 3.8.1 Registers and Pins for Each Module Module Input pin for external External Pin clock Output pin for timer flip-flop Timer run register SFR Timer register TMRA01 TA0IN (Shared with P70) TA1OUT (Shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 No TA3OUT (Shared with P72) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TMRA45 TA4IN (Shared with P73) TA5OUT (Shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) (address) Timer mode register Timer flip-flop control register 91C829-78 2006-03-15 3.8.1 Prescaler 2 φT1 Timer flip-flop TA1FF TA01RUN Selector Selector 8-bit up counter (UC0) 2 overflow n Prescaler clock: φT0 4 φT4 φT16 φT256 8 16 32 64 128 256 512 Run/clear TA01RUN Block Diagrams Timer flip-flop output: TA1OUT TA01RUN TA1FFCR External input clock: TA0IN φT1 φT4 φT16 φT1 φT16 φT256 8-bit up counter (UC1) TA01MOD TA01MOD TA01MOD Figure 3.8.1 TMRA01 Block Diagram 91C829-79 8-bit up counter (CP0) TA01MOD 8-bit timer register TA0REG Match detect TA0TRG TA01RUN Register buffer 0 Internal data bus TMRA0 interrupt output: INTTA0 TMRA0 match output: TA0TRG Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG Internal data bus TMRA1 interrupt output: INTTA1 TMP91C829 2006-03-15 Prescaler Prescaler clock: φT0 2 φT1 φT4 φT16 φT256 Timer flip-flop TA3FF TA23RUN Selector φT1 φT4 φT16 8-bit up counter (UC2) 2 overflow TA23MOD n 4 8 16 32 64 128 256 512 Run/clear TA23RUN Timer flip-flop output: TA3OUT Selector φT1 φT16 φT256 TA23MOD 8-bit up counter (UC3) TA23RUN TA3FFCR Figure 3.8.2 TMRA23 Block Diagram TA23MOD 91C829-80 Match 8-bit comparator detect (CP2) TA2TRG TA23MOD 8-bit timer register TA2REG TA23RUN Register buffer 2 Internal data bus TMRA2 interrupt output: INTTA2 Match 8-bit comparator detect register (CP3) 8-bit timer register TA3REG TMRA2 Internal data bus TMRA3 match output: interrupt output: INTTA3 TA2TRG TMP91C829 2006-03-15 Prescaler 2 φT1 φT4 φT16 φT256 Timer flip-flop TA5FF Selector φT1 φT4 φT16 8-bit up counter (UC4) 2 overflow TA45MOD n Prescaler clock: φT0 4 8 16 32 64 128 256 512 Run/clear TA45RUN Timer flip-flop output: TA5OUT TA5FFCR TA45RUN Selector φT1 φT16 φT256 TA45MOD TA45RUN 8-bit up counter (UC5) External input clock: TA4IN Figure 3.8.3 TMRA45 Block Diagram TA45MOD 91C829-81 8-bit comparator (CP4) Match detect TA4TRG TA45MOD 8-bit timer register TA4REG TA45RUN Register buffer 4 Internal data bus TMRA4 interrupt output: INTTA4 TMRA4 match output: TA4TRG Match 8-bit comparator detect (CP5) 8-bit timer register TA5REG Internal data bus TMRA5 interrupt output: INTTA5 TMP91C829 2006-03-15 TMP91C829 3.8.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided by 4 and input to this prescaler. φT0 can be either fFPH or fc/16 and is selected using the prescaler clock selection register SYSCR0. The prescaler’s operation can be controlled using TA01RUN in the timer control register. Setting to 1 starts the count; setting to 0 clears the prescaler to zero and stops operation. Table 3.8.2 shows the various prescaler output clock resolutions. Table 3.8.2 Prescaler Output Clock Resolution at fc = 36 MHz Prescaler Clock Selection Gear Value 000 (fc) 001 (fc/2) 3 4 5 6 7 Prescaler Output Clock Resolution φT1 5 6 7 8 9 φT4 7 8 9 φT16 2 /fc (3.6 μs) 2 /fc (7.1 μs) 2 /fc (14 μs) 2 /fc (28 μs) 2 /fc (57 μs) 2 /fc (57 μs) 11 11 10 11 12 13 14 15 φT256 2 /fc (57 μs) 2 /fc (114 μs) 2 /fc (228 μs) 2 /fc (455 μs) 2 /fc (910 μs) 2 /fc (910 μs) 15 2 /fc (0.22 μs) 2 /fc (0.9 μs) 2 /fc (0.4 μs) 2 /fc (0.9 μs) 2 /fc (1.8 μs) 2 /fc (3.6 μs) 2 /fc (3.6 μs) 7 2 /fc (1.8 μs) 2 /fc (3.6 μs) 2 /fc (7.1 μs) 2 /fc (14 μs) 2 /fc (14 μs) 9 (fFPH) 010 (fc/4) 011 (fc/8) 100 (fc/16) 10 (fc/16 clock) xxx: Don’t care XXX (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks φT1, φT4, or φT16. The clock setting is specified by the value set in TA01MOD. The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the overflow output from UC0 is used as the input clock. In any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks φT1, φT16, or φT256, or the comparator output (The match detection signal) from TMRA0. For each interval timer the timer operation control register bits TA01RUN and TA01RUN can be used to stop and clear the up counters and to control their count. A reset clears both up counters, stopping the timers. 91C829-82 2006-03-15 TMP91C829 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN determines whether TA0REG’s double buffer structure is enabled or disabled. It is disabled if = 0 and enabled if = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2noverflow occurs in PWM mode, or at the start of the PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode. A reset initializes to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set to 1, and write the following data to the register buffer. Figure 3.8.4 shows the configuration of TA0REG. Timer registers 0 (TA0REG) Y Shift trigger Register buffers 0 Write Internal data bus Selector B A Write to TA0REG S Matching detection in PPG cycle n 2 overflow of PWM TA01RUN Figure 3.8.4 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When = 0, the same value is written to the register buffer and the timer register; when = 1, only the register buffer is written to. The address of each timer register is as follows. TA0REG: 000102H TA2REG: 00010AH TA4REG: 000112H TA1REG: 000103H TA3REG: 00010BH TA5REG: 000113H All these registers are write only and cannot be read. 91C829-83 2006-03-15 TMP91C829 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR in the timer flip-flop control register. A reset clears the value of TA1FF to 0. Writing 01 or 10 to TA1FFCR sets TA1FF to 0 or 1. Writing 00 to these bits inverts the value of TA1FF (This is known as software inversion). The TA1FF signal is output via the TA1OUT pin (which can also be used as P71). When this pin is used as the timer output, the timer flip-flop should be set beforehand using the port 7 function register P7FC. Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fSYS × 6) before the next overflow occurs by using an overflow interrupt. In the case of using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) n Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 91C829-84 2006-03-15 TMP91C829 3.8.3 SFRs TMRA01 Run Register 7 TA01RUN Bit symbol (0100H) Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 0: Stop and clear 1: Run (Count up) 6 5 4 3 I2TA01 2 TA01PRUN R/W 1 TA1RUN 0 0 TA0RUN 0 8-bit timer run/stop control TA0REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA01: Operation in IDLE2 mode TA01PRUN: Run prescaler TA1RUN: Run TMRA1 TA0RUN: Run TMRA0 Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN Bit symbol (0108H) Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 0: Stop and clear 1: Run (Count up) 6 5 4 3 I2TA23 2 TA23PRUN R/W 1 TA3RUN 0 0 TA2RUN 0 8-bit timer run/stop control TA2REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA23: Operation in IDLE2 mode TA23PRUN: Run prescaler TA3RUN: RunTMRA3 TA2RUN: Run TMRA2 Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.8.5 TMRA Registers 91C829-85 2006-03-15 TMP91C829 TMRA45 Run Register 7 TA45RUN Bit symbol (0110H) Read/Write After reset Function TA4RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 0: Stop and clear 1: Run (Count up) 6 5 4 3 I2TA45 2 TA45PRUN R/W 1 TA5RUN 0 0 TA4RUN 0 8-bit timer run/stop control TA4REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) I2TA45: Operation during IDLE2 mode TA45PRUN: Run for prescaler TA5RUN: Run TMRA5 TA4RUN: Run TMRA4 Note: The values of bits 4 to 6 of TA45RUN are undefined when read. Figure 3.8.6 TMRA Registers 91C829-86 2006-03-15 TMP91C829 TMRA01 Mode Register 5 4 PWM01 0 PWM cycle 00: Reserved 01: 2 6 7 8 7 TA01MOD Bit symbol (0104H) Read/Write After reset Function TA01M1 0 Operation mode 6 TA01M0 0 3 2 TA1CLK0 0 1 TA0CLK1 0 00: TA0IN pin 01: φT1 10: φT4 11: φT16 0 TA0CLK0 0 PWM00 R/W 0 TA1CLK1 0 00: TA0TRG 01: φT1 10: φT16 11: φT256 Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 10: 2 11: 2 TMRA0 source clock selection 00 01 10 11 TA0IN (External input) φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler) TMRA1 source clock selection TA01MOD ≠ 01 Comparator output from 00 TMRA0 01 10 11 φT1 φT16 φT256 TA01MOD = 01 Overflow output from TMRA0 (16-bit timer mode) PWM cycle selection 00 01 10 11 Reserved 2 × source clock 6 7 8 2 × source clock 2 × source clock TMRA01 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0), 8-bit timer (TMRA1) Figure 3.8.7 TMRA Registers 91C829-87 2006-03-15 TMP91C829 TMRA23 Mode Register 7 TA23MOD Bit symbol (010CH) Read/Write After reset Function 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 2 6 7 8 6 TA23M0 5 PWM21 4 PWM20 R/W 0 3 TA3CLK1 0 00: TA2TRG 01: φT1 10: φT16 11: φT256 2 TA3CLK0 0 1 TA2CLK1 0 00: Reserved 01: φT1 10: φT4 11: φT16 0 TA2CLK0 0 TA23M1 TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 10: 2 11: 2 TMRA2 source clock selection 00 01 10 11 Do not set φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler) TMRA3 source clock selection TA23MOD ≠ 01 Comparator output from 00 TMRA2 01 10 11 φT1 φT16 φT256 TA23MOD = 01 Overflow output from TMRA2 (16-bit timer mode) PWM cycle selection 00 01 10 11 Reserved 2 × source clock 6 7 8 2 × source clock 2 × source clock TMRA23 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0), 8-bit timer (TMRA3) Figure 3.8.8 TMRA Registers 91C829-88 2006-03-15 TMP91C829 TMRA45 Mode Register 7 TA45MOD Bit symbol (0114H) Read/Write After reset Function 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 2 6 7 8 6 TA45M0 5 PWM41 4 PWM40 R/W 0 3 TA5CLK1 0 00: TA4TRG 01: φT1 10: φT16 11: φT256 2 TA5CLK0 0 1 TA4CLK1 0 00: TA4IN pin 01: φT1 10: φT4 11: φT16 0 TA4CLK0 0 TA45M1 Source clock for TMRA5 Source clock for TMRA4 10: 2 11: 2 Source clock for TMRA4 00 01 10 11 TA4IN (External input) φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler) Source clock for TMRA5 TA45MOD ≠ 01 Comparator output from 00 TMRA4 01 10 11 φT1 φT16 φT256 TA45MOD = 01 Overflow output from TMRA4 (16-bit timer mode) PWM cycle 00 01 10 11 Reserved 2 × source clock 6 7 8 2 × source clock 2 × source clock Operation mode for TMRA45 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA4), 8-bit timer (TMRA5) Figure 3.8.9 TMRA Registers 91C829-89 2006-03-15 TMP91C829 TMRA1 Flip-flop Control Register 7 TA1FFCR (0105H) Readmodify-write instructions are prohibited. Bit symbol Read/Write After reset Function 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care 6 5 4 3 TA1FFC1 R/W 2 TA1FFC0 1 1 TA1FFIE R/W 0 TA1FF control for inversion 0: Disable 1: Enable 0 TA1FFIS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flip-flop 1 (TA1FF) (Don’t care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 Inversion of TA1FF 0 1 Disabled Enabled Control of TA1FF 00 01 10 11 Inverts the value of TA1FF Sets TA1FF to 1 Clears TA1FF to 0 Don’t care Figure 3.8.10 TMRA Registers 91C829-90 2006-03-15 TMP91C829 TMRA3 Flip-flop Control Register 7 TA3FFCR (010DH) Readmodify-write instructions are prohibited. Bit symbol Read/Write After reset Function 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care 6 5 4 3 TA3FFC1 R/W 2 TA3FFC0 1 1 TA3FFIE R/W 0 TA3FF control for inversion 0: Disable 1: Enable 0 TA3FFIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don’t care except in 8-bit timer mode) 0 1 Inversion by TMRA2 Inversion by TMRA3 Inversion of TA3FF 0 1 Disabled Enabled Control of TA3FF 00 01 10 11 Inverts the value of TA3FF Sets TA3FF to 1 Clears TA3FF to 0 Don’t care Figure 3.8.11 TMRA Registers 91C829-91 2006-03-15 TMP91C829 TMRA5 Flip-flop Control Register 7 TA5FFCR (0115H) Readmodify-write instructions are prohibited. Bit symbol Read/Write After reset Function 1 00: Invert TA5FF 01: Set TA5FF 10: Clear TA5FF 11: Don’t care 6 5 4 3 TA5FFC1 R/W 2 TA5FFC0 1 1 TA5FFIE R/W 0 TA5FF control for inversion 0: Disable 1: Enable 0 TA5FFIS 0 TA5FF inversion select 0: TMRA4 1: TMRA5 Inverse signal for timer flip-flop 5 (TA5FF) (Don’t care except in 8-bit timer mode) 0 1 Inversion by TMRA4 Inversion by TMRA5 Inversion of TA5FF 0 1 Disabled Enabled Control of TA5FF 00 01 10 11 Inverts the value of TA5FF Sets TA5FF to 1 Clears TA5FF to 0 Don’t care Figure 3.8.12 TMRA Registers 91C829-92 2006-03-15 TMP91C829 TMRA register 7 TA0REG (0102H) TA1REG (0103H) TA2REG (010AH) TA3REG (010BH) TA4REG (0112H) TA5REG (0113H) bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset 6 5 4 − W Undefined − W Undefined − W Undefined − W Undefined − W Undefined − W Undefined 3 2 1 0 Note: The above registers are prohibited read-modify-write instruction. Figure 3.8.13 TMRA Registers 91C829-93 2006-03-15 TMP91C829 3.8.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 8.8 μs at fc = 36 MHz, set each register as follows: * Clock state MSB TA01RUN TA01MOD TA1REG INTETA01 TA01RUN ← ← ← ← ← 7 – 0 0 X – 6 – 0 0 1 X 5 X X 1 0 X 4 X X 0 1 X 3 – 1 1 – – 2 – 0 0 – 1 1 0 X 0 – 1 LSB 0 – X 0 – – Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select φT1 ((2 /fc) μs at fc = 36 MHz) as the input clock. 3 System clock: High frequency (fc) Prescaler clock: fFPH Set TA1REG to 8.8 μs ÷ φT1 (2 /fc) = 40 = 28H 3 Enable INTTA1 and set it to level 5. Start TMRA1 counting. X: Don’t care, −: No change Select the input clock using Table 3.8.4 Note: The input clocks for TMRA0 and TMRA1 differ as follows: TMRA0: Uses TA0IN input and can be selected from φT1, φT4, or φT16. TMRA1: Match output of TMRA0 and can be selected from φT1, φT16, φT256. 91C829-94 2006-03-15 TMP91C829 b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.32 μs square wave pulse from the TA1OUT pin at fc = 36 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: fFPH 7 – 0 0 X X X – 6 X 0 0 X X X X 5 X X 0 X – – X 4 X X 0 X – – X 3 – 0 0 1 – X – 2 – 1 0 0 – – 1 1 0 – 1 1 1 1 1 0 – – 1 1 – X – TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN ← ← ← ← ← ← ← Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select φT1 ((2 /fc)s at fc = 36 MHz) as the input clock. 3 Set the timer register to 1.32 μs ÷ φT1(2 /fc)s ÷ 2 = 3 3 Clear TA1FF to 0 and set it to invert on the match detect signal from TMRA1. Set P71 to function as the TA1OUT pin. Start TMRA1 counting. X: Don’t care, −: No change φT1 TA01RUN Bit7 to 2 Up counter Bit1 Bit0 Comparator timing Comparator output (Match detect) INTTA1 UC1 clear TA1FF 0 1 2 3 0 1 2 3 0 1 2 3 0 TA1OUT 0.67μs at fc = 36 MHz Figure 3.8.14 Square Wave Output Timing Chart (50% duty) 91C829-95 2006-03-15 TMP91C829 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.8.15 TMRA1 Count Up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD to 01. In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of the value set in TA01MOD. Table 3.8.4 shows the relationship between the timer (Interrupt) cycle and the input clock selection. Setting example: To generate an INTTA1 interrupt every 0.22 seconds at fc = 36 MHz, set the timer registers TA0REG and TA1REG as follows: * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH If φT16 ((27/fc)s at 36 MHz) is used as the input clock for counting, set the following value in the registers: 0.22 s ÷ (27/fc)s ≈ 62500 = F424H (e.g., set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.23 [s]. 91C829-96 2006-03-15 TMP91C829 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, where the up counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA0 comparator match detect signal INTTA0 INTTA1 TA1OUT 0080H 0180H 0280H 0380H 0480H 0080H Inversion Figure 3.8.16 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-low or active-high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin (which can also be used as P71). tH When =”10” t tL When =”01” t tH tL Example when =”01” TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interruput INTTA1) TA1OUT TA0REG TA1REG Figure 3.8.17 8-Bit PPG Output Waveforms 91C829-97 2006-03-15 TMP91C829 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN should be set to 1 so that UC1 is set for counting. Figure 3.8.18 shows a block diagram representing this mode. TA1OUT TA0IN φT1 φT4 φT16 Selector 8-bit up counter (UC 0) TA01RUN TA1FF TA1FFCR Inversion INTTA0 Comparator INTTA1 TA01MOD Comparator Selector TA0REG-WR TA0REG Shift trigger Register buffer TA1REG TA01RUN Internal data bus Figure 3.8.18 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG and up counter Match with TA1REG TA0REG (Value to be compared) Register buffer Q1 Q2 Shift from register buffer Q2 Q3 TA0REG (Register buffer) write (Up counter = Q1) (Up countner = Q2) Figure 3.8.19 Operation of Register Buffer 91C829-98 2006-03-15 TMP91C829 Example: To generate 1/4 duty 50kHz pulses (at fc = 36 MHz): 20 μs * Clock state System clock: Clock gear: Prescaler clock: High frequency (fc) 1 (fc) fFPH Calculate the value which should be set in the timer register. To obtain a frequency of 50kHz, the pulse cycle t should be: t = 1/50 kHz = 20 μs φT1 = (23/fc)s (at 36 MHz); 20 μs ÷ (23/fc)s ≈ 90 Therefore set TA1REG to 90 (5AH) The duty is to be set to 1/4: t × 1/4 = 20 μs × 1/4 = 5 μs 5 μs ÷ (23/fc)s ≈ 22 Therefore, set TA0REG = 22 = 16H. 7 0 1 0 0 X X X 1 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR P7CR P7FC TA01RUN ← ← ← ← ← ← ← ← 6 X 0 0 1 X X X X 5 X X 0 0 X – – X 4 X X 1 1 X – – X 3 – X 0 1 0 – X – 2 0 X 1 0 1 – – 1 1 0 0 1 1 1 1 1 1 0 0 1 0 0 X – X 1 Stop TMRA0 and TMRA01 and clear it to 0. Set the 8-bit PPG mode, and select φT1 as input clock. Write 16H. Write 5AH. Set TA1FF, enabling both inversion and the double buffer. 10 generates a negative logic pulse. Set P71 as the TA1OUT pin. Start TMRA0 and TMRA01 counting. X: Don’t care, −: No change 91C829-99 2006-03-15 TMP91C829 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7, or 8 as specified by TA01MOD). The up counter UC0 is cleared when 2ncounter overflow occurs. The following conditions must be satisfied before this PWM mode can be used. Value set in TA0REG < Value set for 2n counter overflow Value set in TA0REG ≠ 0 TA0REG and UC0 match 2 overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) n Figure 3.8.20 8-Bit PWM Waveforms Figure 3.8.21 shows a block diagram representing this mode. TA01RUN TA0IN φT1 φT4 φT16 TA1OUT Selector 8-bit up counter (UC 0) Clear 2 overflow control n TAFF1 Invert TA01MOD TA1FFCR TA01MOD Overflow Comparator INTTA0 TA0REG Selector TA0REG-WR TA01RUN Internal data bus Shift trigger Register buffer Figure 3.8.21 Block Diagram of 8-Bit PWM Mode 91C829-100 2006-03-15 TMP91C829 In this mode the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 overflow TA0REG (Value to be compared) Register buffer Q1 Q2 Shift into TA0REG Q2 Q3 TA0REG (Register buffer) write n Up counter = Q2 Figure 3.8.22 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at fc = 36 MHz: 16.0 μs 28.4 μs * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH To achieve a 28.4 μs PWM cycle by setting φT1 to (23/fc)s (at fc = 36 MHz): 28.4 μs ÷ (23/fc)s ≈ 128 = 2n Therefore n should be set to 7. Since the low-level period is 16.0 μs when φT1 = (23/fc)s, set the following value for TA0REG: 16.0 μs ÷ (23/fc)s ≈ 72 = 48H MSB TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN ← ← ← ← ← ← ← 7 – 1 0 X X X 1 6 X 1 1 X X X X 5 X 1 0 X – – X 4 X 0 0 X – – X 3 – – 1 1 – X – 2 – – 0 0 – – 1 1 – 0 0 1 1 1 1 LSB 0 0 1 0 X – X 1 Stop TMRA0 and clear it to 0. 7 Select 8-bit PWM mode (Cycle: 2 ) and select φT1 as the input clock. Write 48H. Clear TA1FF to 0, enable the inversion and double buffer. Set P71 and the TA1OUT pin. Start TMRA0 counting. X: Don’t care, −: No change 91C829-101 2006-03-15 TMP91C829 Table 3.8.3 PWM Cycle at fc = 36 MHz Select Prescaler Clock PWM Cycle Gear Value 000 (fc) 2 φT1 14.2 μs 28.4 μs 56.8 μs 113 μs 227 μs 227 μs 6 2 φT16 227 μs 455 μs 910 μs 1820 μs 3640 μs 3640 μs 28 φT16 455 μs 910 μs 1820 μs 3640 μs φT4 56.8 μs 113 μs 227 μs 455 μs 910 μs 910 μs φT1 28.4 μs 56.8 μs 113 μs 227 μs 455 μs 455 μs φT4 113μs 227 μs 455 μs 910 μs φT1 56.8 μs 113 μs 227 μs 455 μs 910 μs 910 μs φT4 227 μs 455 μs 910 μs 1820 μs φT16 910 μs 1820 μs 3640 μs 7281 μs 00 (fFPH) 001 (fc/2) 10 (fc/4) 011 (fc/8) 00 (fc/16) 1820 μs 7281 μs 1820 μs 7281 μs 3640 μs 14563 μs 3640 μs 14563 μs 10 (fc/16 clock) XXX: Don’t care XXX (5) Settings for each mode Table 3.8.4 shows the SFR settings for each mode. Table 3.8.4 Timer Mode Setting Registers Register Name Function 8-bit timer × 2 channels TA01MOD Timer Mode PWM Cycle − TA1FFCR Lower Timer Input Clock External clock φT1, φT4, φT16 (00, 01, 10, 11) External clock φT1, φT4, φT16 (00, 01, 10, 11) External clock φT1, φT4, φT16 (00, 01, 10, 11) External clock − φT1, φT4, φT16 (00, 01, 10, 11) − − Upper Timer Input Clock Lower timer match φT1, φT16, φT256 (00, 01, 10, 11) − TA1FFIS Timer F/F Invert Signal Select 0: Lower timer output 1: Upper timer output 00 16-bit timer mode 01 − − 8-bit PPG × 1 channel 10 − − − 8-bit PWM × 1 channel 11 2 ,2 ,2 (01, 10, 11) − 6 7 8 8-bit timer × 1 channel −: Don’t care 11 φT1, φT16, φT256 (01, 10, 11) Output disabled 91C829-102 2006-03-15 TMP91C829 3.9 16-Bit Timer/Event Counters (TMRB) The TMP91C829 incorporates multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: • • • 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) mode The timer/event counter channel consists of a 16-bit up counter, two 16-bit timer registers (One of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. The timer/event counter is controlled by an 11-byte control SFR. This chapter consists of the following items: Table 3.9.1 Differences between TMRB0 Channel Spec External clock/capture trigger External Pins input pins Timer flip-flop output pins Timer run register Timer mode register Timer flip-flop control register TMRB0 TB0IN0 (Also used as P93) TB0IN1 (Also used as P94) TB0OUT0 (Also used as P95) TB0OUT1 (Also used as P96) TB0RUN (0180H) TB0MOD (0182H) TB0FFCR (0183H) TB0RG0L (0188H) TB0RG0H (0189H) TB0RG1L (018AH) TB0RG1H (018BH) TB0CP0L (018CH) TB0CP0H (018DH) TB0CP1L (018EH) TB0CP1H (018FH) SFR (address) Timer register Capture register 91C829-103 2006-03-15 3.9.1 INT output Internal data bus Internal data bus Register 0 Register 1 INTTB00 INTTB01 Block Diagrams Prescaler clock: φT0 2 φT1 Capture register 0 TB0CP0H/L Caputure register 1 TB0CP1H/L φT4 φT16 4 8 Run/ clear TB0RUN 16 32 TB0MOD Timer flip-flop TB0FF0 TB0FF1 Timer flip-flop output TB0OUT0 Timer flip-flop control TB0OUT1 Over flow INT INTTBOF1 TA1OUT (from TMRA01) TB0IN0 TB0IN1 TB0RUN TB0MOD 16-bit up counter (UC0) Selector TB0MOD Count φT1 clock φT4 φT16 TB0MOD Match detection Capture, external INT input control Figure 3.9.1 Block Diagram of TMRB0 91C829-104 16-bit comparator (CP0) 16-bit timer register TB0RG0H/L TB0RUN Register buffer 0 Internal data bus Match detection 16-bit comparator (CP1) 16-bit time register TB0RG1H/L Intenal data bus TMP91C829 2006-03-15 TMP91C829 3.9.2 Operation of Each Block (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0) is divided clock (divided by 4) from selected clock by the register SYSCR0 of clock gear. This prescaler can be started or stopped using TB0RUN. Counting starts when is set to 1; the prescaler is cleared to zero and stops operation when is set to 0. Table 3.9.2 Prescaler Clock Resolution at fc = 36 MHz Prescaler Clock Selection Clock Gear Value 000 (fc) 00 (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 10 (fc/16 clock) xxx: Don’t care XXX 3 4 5 6 7 Prescaler Clock Resolution φT1 2 /fc (0.2 μs) 2 /fc (0.4 μs) 2 /fc (0.9 μs) 2 /fc (1.8 μs) 2 /fc (3.6 μs) 2 /fc (3.6 μs) 7 5 6 7 8 9 φT4 2 /fc (0.9 μs) 2 /fc (1.8 μs) 2 /fc (3.6 μs) 2 /fc (7.1 μs) 2 /fc (14.2 μs) 2 /fc (14.2 μs) 9 φT16 2 /fc 2 /fc 9 10 11 8 7 (3.6 μs) (7.1 μs) 2 /fc (14.2 μs) 2 /fc (28.4 μs) 2 /fc (56.9 μs) 2 /fc (56.9 μs) 11 (2) Up counter (UC0) UC0 is a 16-bit binary counter which counts up pulses input from the clock specified by TB0MOD. Any one of the prescaler internal clocks φT1, φTB0 and φT16 or an external clock input via the TB0IN0 pin can be selected as the input clock. Counting or stopping and clearing of the counter is controlled by TB0RUN. When clearing is enabled, the up counter UC0 will be cleared to zero each time its value matches the value in the timer register TB0RG1H/L. Clearing can be enabled or disabled using TB0MOD. If clearing is disabled, the counter operates as a free-running counter. A timer overflow interrupt (INTTBOF0) is generated when UC0 overflow occurs. 91C829-105 2006-03-15 TMP91C829 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC0 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower registers is always needed. For example, either using 2-byte data transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order. The TB0RG0 timer register has a double-buffer structure, which is paired with register buffer. The value set in TB0RUN determines whether the double-buffer structure is enabled or disabled: it is disabled when = 0, and enabled when = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when the values in the up counter (UC0) and the timer register TB0RG1 match. After a reset, TB0RG0 and TB0RG1 are undefined. If the 16-bit timer is to be used after a reset, data should be written to it beforehand. On a reset TB0RUN is initialized to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set to 1, then write data to the register buffer as shown below. TB0RG0 and the register buffer both have the same memory addresses (000188H and 000189H) allocated to them. If = 0, the value is written to both the timer register and the register buffer. If = 1, the value is written to the register buffer only. The addresses of the timer registers are as follows: TMRB0 TB0RG0 Upper 8 bits (TB0RG0H) 000189H Lower 8 bits (TB0RG0L) 000188H TB0RG1 Upper 8 bits (TB0RG1H) 00018BH Lower 8 bits (TB0RG1L) 00018AH The timer registers are write-only registers and thus cannot be read. (4) Capture registers (TB0CP0H/L and TB0CP1H/L) These 16-bit registers are used to latch the values in the up counter UC0. Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. The addresses of the capture registers are as follows: TMRB0 TB0CP0 Upper 8 bits (TB0CP0H) 00018DH Lower 8 bits (TB0CP0L) 00018CH TB0CP1 Upper 8 bits (TB0CP1H) 00018FH Lower 8 bits (TB0CP1L) 00018EH The capture registers are read-only registers and thus cannot be written to. 91C829-106 2006-03-15 TMP91C829 (5) Capture input control This circuit controls the timing to latch the value of up counter UC0 into TB0CP0, TB0CP1. The latch timing for the capture register is determined by TB0MOD. In addition, the value in the up counter can be loaded into a capture register by software. Whenever 0 is written to TB0MOD, the current value in the up counter is loaded into capture register TB0CP0. It is necessary to keep the prescaler in run mode (e.g., TB0RUN must be held at a value of 1). Note: As described above, whenever 0 is written to TB0MOD, the current value in the up counter is loaded into capture register TB0CP0. However, note that the current value in the up counter is also loaded into capture register TB0CP0 when 1 is written to TB0MOD while this bit is holding 0. Note Write to TBnMOD register TBnMOD Capture operation Capture Capture Capture Capture NOP “0” WR “0” WR “1” WR “1” WR (6) Comparators (CP0 and CP1) CP0 and CP1 are 16-bit comparators which compare the value in the up counter UC0 with the value set in TB0RG0 or TB0RG1 respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). (7) Timer flip-flops (TB0FF0 and TB0FF1) These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers. Inversion can be enabled and disabled for each element using TB0FFCR. After a reset the value of TB0FF0 is undefined. If 00 is written to TB0FFCR or , TB0FF0 will be inverted. If 01 is written to the capture registers, the value of TB0FF0 will be set to 1. If 10 is written to the capture registers, the value of TB0FF0 will be set to 0. The values of TB0FF0 and TB0FF1 can be output via the timer output pins TB0OUT0 (which is shared with P95) and TB0OUT1 (which is shared with P96). Timer output should be specified using the port 9 function register. 91C829-107 2006-03-15 TMP91C829 3.9.3 SFRs TMRB0 Run Register 7 TB0RUN Bit symbol (0180H) Read/Write After reset Function TB0RDE R/W 0 Double buffer 0: Disable 1: Enable “0”. 6 − R/W 0 Always write 5 4 3 I2TB0 R/W 0 IDLE2 0: Stop 1: Operate 2 TB0PRUN R/W 0 1 0 TB0RUN R/W 0 16-bit timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 1 I2TB0: Note: The 1, 4 and 5 of TB0RUN are read as undefined value. Stop and clear Count Operation during IDLE2 mode TB0PRUN: Operation of prescaler TB0RUN: Operation of TMRB0 Figure 3.9.2 Register for TMRB 91C829-108 2006-03-15 TMP91C829 TMRB0 Run Register 7 TB0MOD (0182H) Bit symbol Read/Write After reset Function Read -modify -write instruction is prohibited 6 TB0ET1 R/W 0 5 TB0CP0I W* 1 Execute software capture 4 TB0CPM1 0 Capture timing 00: Disable 3 TB0CPM0 0 2 TB0CLE R/W 0 Control up counter 0: Disable 1 TB0CLK1 0 00: TB0IN0 pin 01: φT1 10: φT4 11: φT16 0 TB0CLK0 0 TB0CT1 0 TB0FF1 inversion 0: Disable trigger 1: Enable trigger TMRB0 source clock 01: TB0IN0 ↑ TB0IN1 ↑ clearing Invert when Invert when 0: Execute 10: TB0IN0 ↑ TB0IN1 ↓ 1: Undefined 11: TA1OUT ↑ TA1OUT ↓ 1: Enable the UC the UC value is captured to TB0CP1. value matches the value in TB0RG1. clearing TMRB0 source clock 00 01 10 11 TB0IN0 pin φT1 φT4 φT16 Up counter clear control 0 1 Capture Capture control 00 01 10 11 Disable CAP0 at TB0IN0 rising CAP1 at TB0IN1 rising CAP0 at TB0IN0 rising CAP1 at TB0IN1 rising CAP0 at TA1OUT rising CAP1 at TA1OUT falling Disable TB0RG1 clearing on match with TB0RG1. Software capture 0 1 Note: The value in the up counter is captured to TB0CP0. Undefined (Note) Whenever writing “0” to TB0MOD bit, present value of up counter is received to capture register TB0CP0. But write “1” to TB0MOD in condition of written “0” to TB0MOD bit, present value of up counter is received to capture register TB0CP0. Therefore you must to regard. Figure 3.9.3 Register for TMRB 91C829-109 2006-03-15 TMP91C829 TMRB0 Flip-flop Control Register 7 TB0FFCR Bit symbol (0183H) Read/Write After reset Function Read -modify -write instruction is prohibited 6 TB0FF1C0 0 W* 5 TB0C1T1 1 0: Disable trigger 1: Enable trigger 4 TB0C0T1 0 R/W 3 TB0E1T1 0 2 TB0E0T1 0 1 TB0FF0C1 0 Control TB0FF0 00: Invert 01: Set 10: Clear W* 0 TB0FF0C0 0 TB0FF1C1 0 Control TB0FF1 00: Invert 01: Set 10: Clear 11: Don’t care * Always read as “11”. TB0FF0 inversion trigger Invert when Invert when Invert when Invert when the UC value the UC value the UC value the UC value 11: Don’t care is loaded in is loaded in matches the matches the * Always read as “11”. to TB0CP1. to TB0CP0. value in TB0RG1. value in TB0RG0. TB0FF0 control Invert 00 01 10 11 Set to 11 Clear to 0 Don’t care Inverted when the UC value is loaded in to TB0CP1. 0 1 Disable trigger Enable trigger Inverted when the UC value is loaded in to TB0CP0. 0 1 Disable trigger Enable trigger Inverted when the UC value matches the valued in TB0RG1. 0 1 Disable trigger Enable trigger Inverted when the UC value matches the valued in TB0RG0. 0 1 Disable trigger Enable trigger Figure 3.9.4 Register for TMRB 91C829-110 2006-03-15 TMP91C829 7 TB0RG0L (0188H) TB0RG0H (0189H) TB0RG1L (018AH) TB0RG1H (018BH) bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset 6 TMRB0 Register 5 4 3 – W Undefined – W Undefined – W Undefined – W Undefined 2 1 0 Note: The above registers are prohibited read-modify-write instruction. Figure 3.9.5 TMRB Registers 91C829-111 2006-03-15 TMP91C829 3.9.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1. TB0RUN INTETB01 TB0FFCR TB0MOD TB0RG1 TB0RUN ← ← ← ← ← ← ← 7 0 X 1 0 * * 0 6 0 1 1 0 * * 0 5 X 0 0 1 * * X 4 X 0 0 0 * * X 3 – X 0 0 * * – 2 0 0 0 1 * * 1 1 X 0 1 0 0 0 1 Stop TMRB0. Enable INTTB01 and set interrupt level 4. Disable INTTB00. Disable the trigger. Select internal clock for input and disable the capture function. Set the interval time (16 bits). Start TMRB0. ** (** = 01, 10, 11) * * X * * 1 X: Don’t care, −: No change (2) 16-bit event counter mode As described above, in 16-bit timer mode, if the external clock (TB0IN0 pin input) is selected as the input clock, the timer can be used as an event counter. To read the value of the counter, first perform software capture once, then read the captured value. TB0RUN P8CR INTETB01 TB0FFCR TB0MOD TB0RG1 TB0RUN ← ← ← ← ← ← ← 7 0 – X 1 0 * * 0 6 0 – 1 1 0 * * 0 5 X – 0 0 1 * * X 4 X – 0 0 0 * * X 3 – 0 X 0 0 * * – 2 0 – 0 0 1 * * 1 1 X – 0 1 0 * * X 0 0 – 0 1 0 * * 1 Stop TMRB0. Set P93 input mode. Enable INTTB01 and set interrupt level 4. Disable INTTB00. Disable the trigger. Select TB0IN0 as the input clock. Set the number of counts (16 bits). Start TMRB0. X: Don’t care, −: No change When the timer is used as an event counter, set the prescaler in run mode (e.g., with TB0RUN = 1). 91C829-112 2006-03-15 TMP91C829 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low-active or high-active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be enabled by the match of the up counter UC0 with timer register TB0RG0 or TB0RG1 and to be output to TB0OUT0. In this mode the following conditions must be satisfied. (Value set in TB0RG0) < (Value set in TB0RG1) Match with TB0RG0 (INTTB00 inerrupt) Match with TB0RG1 (INTTB01 interrupt) TB0OUT0 pin Figure 3.9.5 Programmable Pulse Generation (PPG) Output Waveforms When the TB0RG0 double buffer is enabled in this mode, the value of register buffer 0 will be shifted into TB0RG0 at match with TB0RG1. This feature facilitates the handling of low-duty waves. Match with TB0RG0 Up counter = Q1 Match with TB0RG1 TB0RG0 (Value to be compared) Register buffer Q1 Q2 Up counter = Q2 Shift into theTB0RG1 Q2 Q3 Write into the TB0RG0 Figure 3.9.6 Operation of Register Buffer 91C829-113 2006-03-15 TMP91C829 The following block diagram illustrates this mode. TB0RUN TB0OUT0 (PPG output) 16-bit up counter UC0 Clear F/F (TB0FF0) Selector TB0IN0 φT1 φT4 φT16 16-bit comparator Match 16-bit comparator Selector TB0RG0 TB0RG0-WR Register buffer 0 TB0RUN TB0RG1 Internal data bus Figure 3.9.7 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: 7 0 * * 1 TB0RUN TB0RG0 TB0RG1 TB0RUN ← ← ← ← 6 0 * * 0 5 X * * X 4 X * * X 3 – * * – 2 0 * * 0 1 X * * X 0 0 * * 0 TB0FFCR TB0MOD P9CR P9FC TB0RUN ← ← ← ← ← X 0 – X 1 X 0 – – 0 0 1 1 1 X 0 1 1 1 0 001** (** = 01, 10, 11) – X X – X – X 1 – X X – 1 Disable the TB0RG0 double buffer and stop TMRB0. Set the duty ratio (16 bits). Set the frequency (16 bits). Enable the TB0RG0 double buffer. (The duty and frequency are changed on an INTTB01 interrupt.) Set the mode to invert TB0FF0 at the match with TB0RG0/TB0RG1. Set TB0FF0 to 0. Select the internal clock as the input clock and disable the capture function. Set P95 to function as TB0OUT0. Start TMRB0. X: Don’t care, −: No change 91C829-114 2006-03-15 TMP91C829 3.10 Serial Channel TMP91C829 includes one serial I/O channel. Either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. • I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data Mode 2: 8-bit data Mode 3: 9-bit data • UART mode In mode 1 and mode 2 a parity bit can be added. Mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (A multi-controller system). Figure 3.10.2 and Figure 3.10.3 are block diagrams. Table 3.10.1 Channels 0 and 1 Channel 0 Pin Name TXD0 (P80) RXD0 (P81) CTS0 /SCLK0 (P82) STS0 (P83) Channel 1 TXD1 (P84) RXD1 (P85) CTS0 /SCLK1 (P86) STS1 (P87) • Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 Stop Parity Start Bit0 1 2 3 4 5 6 Parity Stop • Mode 2 (8-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 7 Stop Parity Start Bit0 1 2 3 4 5 6 7 Parity Stop • Mode 3 (9-bit UART mode) Start Bit0 1 2 3 4 5 6 7 8 Stop Wakeup function Start Bit0 1 2 3 4 5 6 7 Bit8 Stop When Bit8 = 1, address (Select code) is denoted. When Bit8 = 0, data is denoted. Figure 3.10.1 Data Formats 91C829-115 2006-03-15 TMP91C829 STS0 and STS1 pins are built in port P83 and P87. STS0 and STS1 are the request signal for the next data send to the CPU. P8CR sets port as output mode, P8FC sets STS using mode, and bit 0 of SC0MOD1 (SC1MOD1) register sets low level. Then STS is enable to start to transfer the data. When SCLK signal is exactly falling edge, STS is disable. And when it is ended to transfer 8-bits data, the STS can be set to enable and request the next data. In SCLK output mode, the STS function can’t be used. RESIO S IOBUS WR D CK S D CK Q D CK Q Q STS output SCLK IPH SCLK input SCLK TXD STS is H level, when SCLK is falling edge timing. STS REG WR by programming 91C829-116 2006-03-15 TMP91C829 3.10.1 Block Diagrams Figure 3.10.2 is a block diagram representing serial channel 0. φT0 Prescaler 2 4 8 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR0CR BR0CR φT0 φT2 φT8 φT32 Prescaler Selector BR0ADD Selector Selector UART mode TA0TRG (from TMRA0) SIOCLK ÷2 SCLK0 Shared with P82 I/O interface Mode Selector fSYS BR0CR Baud rate generator SC0MOD0 SC0MOD0 I/O interface mode SC0CR INT request INTRX0 INTTX0 SC0MOD0 Serial channel interrupt control (Only UART ÷ 16) SCLK0 Shared with P82 (Only UART ÷ 16) Receive counter Transmision counter RXDCLK SC0MOD0 Receive control SC0CR Parity control TXDCLK Transmission control SC0MOD0 CTS0 Shared with P82 RXD0 Shared with P81 Receive buffer 1 (Shift register) RB8 Receive buffer 2 (SC0BUF) Error flag TB8 Transmission buffer SC0CR Internal data bus TXD0 Shared with P80 Figure 3.10.2 Block Diagram of the Serial Channel 0 91C829-117 2006-03-15 TMP91C829 φT0 Prescaler 2 4 8 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR1CR BR1CR φT0 φT2 φT8 φT32 Prescaler Selector BR1ADD Selector Selector UART mode TA0TRG (from TMRA0) SIOCLK ÷2 SCLK1 Shared with P86 I/O interface Mode Selector fSYS BR1CR Baud rate generator SC1MOD0 SC1MOD0 I/O interface mode SC1CR INT request INTRX1 INTTX1 SC1MOD0 Serial channel interrupt control (Only UART ÷ 16) SCLK1 Shared with P86 (Only UART ÷ 16) Receive counter Transmision counter RXDCLK SC1MOD0 Receive control SC1CR Parity control TXDCLK Transmission control SC1MOD0 CTS1 Shared with P86 RXD1 Shared with P85 Receive buffer 1 (Shift register) RB8 Receive buffer 2 (SC1BUF) Error flag TB8 Transmission buffer SC1CR Internal data bus TXD1 Shared with P84 Figure 3.10.3 Block Diagram of the Serial Channel 1 91C829-118 2006-03-15 TMP91C829 3.10.2 Operation of Each Circuit (1) Prescaler, prescaler clock select There is a 6-bit prescaler for waking serial clock. The clock selected using SYSCR is divided by 4 and input to the prescaler as φT0. The prescaler can be run by selecting the baud rate generator as the waking serial clock. Table 3.10.2 shows prescaler clock resolution into the baud rate generator. Table 3.10.2 Prescaler Clock Resolution to Baud Rate Generator Select Prescaler Clock Gear Value 000 (fc) 001 (fc/2) 00 (fFPH) 010 (fc/4) 011 (fc/8) 100 (fc/16) 10 (fc/16 clock) X: Don’t care, −: Cannot be used XXX Prescaler Output Clock Resolution φT0 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc − 6 5 4 3 2 φT2 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc 8 8 7 6 5 4 φT8 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc 10 10 9 8 7 6 φT32 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc 2 /fc 12 12 11 10 9 8 The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32 among the prescaler outputs. 91C829-119 2006-03-15 TMP91C829 (2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers. One of these input clocks is selected using the BR0CR field in the baud rate generator control register. The baud rate generator includes a frequency divider, which divides the frequency by 1 or N + (16 − K ) to 16 values, determining the transfer rate. 16 The transfer rate is determined by the settings of BR0CR and BR0ADD. • In UART mode The settings BR0ADD are ignored. The baud rate generator divides the selected prescaler clock by N, which is set in BR0CK (N = 1, 2, 3 … 16). (2) When BR0CR = 1 The N + (16 – K)/16 division function is enabled. The baud rate generator divides the selected prescaler clock by N + (16 – K)/16 using the value of N set in BR0CR (N = 2, 3 … 15) and the value of K set in BR0ADD (K = 1, 2, 3 … 15). Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Set BR0CR to 0. • In I/O interface mode The N + (16 – K)/16 division function is not available in I/O interface mode. Set BR0CR to 0 before dividing by N. The method for calculating the transfer rate when the baud rate generator is used is explained below. • In UART mode Baud rate = • Input clock of baud rate generator ÷ 16 Frequency divider for baud rate generator (1) When BR0CR = 0 In I/O interface mode Baud rate = Input clock of baud rate generator ÷2 Frequency divider for baud rate generator • Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency = φT2 (fc/16), the frequency divider N (BR0CR) = 5, and BR0CR = 0, the baud rate in UART mode is as follows: * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: System clock Baud rate = fc/16 ÷ 16 5 = 12.288 × 106 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps) Note: The N + (16 − K)/16 division function is disabled and setting BR0ADD is invalid. 91C829-120 2006-03-15 TMP91C829 • N + (16 − K)/16 divider (Only UART mode) Accordingly, when the source clock frequency (fc) = 4.8 MHz, the input clock frequency = φT0, the frequency divider N (BR0CR) = 7, K (BR0ADD) = 3, and BR0CR = 1, the baud rate in UART mode is as follows: * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: System clock Baud rate = Fc/4 7 + (16 − 3)/16 ÷16 = 4.8 × 106 ÷ 4 ÷ (7 + 13/16) ÷ 16 = 9600 (bps) Table 3.10.3 and 3.10.4 show examples of UART mode transfer rates. Additionally, the external clock input is available in the serial clock. (Serial channels 0 and 1). The method for calculating the baud rate is explained below: • In UART mode Baud rate = external clock input frequency ÷ 16 It is necessary to satisfy (External clock input cycle) ≥ 4/fc • In I/O interface mode Baud rate = external clock input frequency It is necessary to satisfy (External clock input cycle) ≥ 16/fc 91C829-121 2006-03-15 TMP91C829 Table 3.10.3 Transfer Rate Selection (when baud rate generator is used and BR0CR = 0) Unit (kbps) Input Clock fc [MHz] 9.830400 ↑ ↑ ↑ 12.288000 ↑ 14.745600 ↑ ↑ ↑ 19.6608 ↑ ↑ ↑ ↑ 22.1184 24.576 ↑ ↑ ↑ ↑ ↑ ↑ 27.0336 29.4912 ↑ ↑ ↑ ↑ ↑ ↑ ↑ 31.9488 34.4064 Frequency Divider N (BR0CR) 2 4 8 0 5 A 2 3 6 C 1 2 4 8 10 3 1 2 4 5 8 A 10 B 1 3 4 6 9 C F 10 D 7 φT0 76.800 38.400 19.200 9.600 38.400 19.200 115.200 76.800 38.400 19.200 307.200 153.600 76.800 38.400 19.200 115.200 384.000 192.000 96.000 76.800 48.000 38.400 24.000 38.400 460.800 153.600 115.200 76.800 51.200 38.400 30.720 28.800 38.400 76.800 φT2 19.200 9.600 4.800 2.400 9.600 4.800 28.800 19.200 9.600 4.800 76.800 38.400 19.10 9.600 4.800 28.800 96.000 48.000 24.000 19.200 12.000 9.600 6.000 9.600 115.200 38.400 28.800 19.200 12.800 9.600 7.680 7.200 9.600 19.200 φT8 4.800 2.400 1.200 0.600 2.400 1.200 7.200 4.800 2.400 1.200 19.200 93.600 4.800 2.400 1.200 7.200 24.000 12.000 6.000 4.800 3.000 2.400 1.500 2.400 28.800 9.600 7.200 4.800 3.200 2.400 1.920 1.800 2.400 4.800 φT32 1.200 0.600 0.300 0.150 0.600 0.300 1.800 1.200 0.600 0.300 4.800 2.400 1.200 0.600 0.300 1.800 6.000 3.000 1.500 1.200 0.750 0.600 0.375 0.600 7.200 2.400 1.800 1.200 1.800 1.600 1.480 0.450 0.600 1.200 Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above. Note 2: The values in this table are calculated for when fc is selected as the system clock, the clock gear is set for fc and the system clock is the prescaler clock input. Timer out clock (TA0TRG) can be used for source clock of UART mode only. Calculation method the frequency of TA0TRG Frequency of TA0TRG = Baud rate × 16 Note 1: The TMRA0 match detects signal cannot be used as the transfer clock in I/O interface mode. 91C829-122 2006-03-15 TMP91C829 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK input mode with the setting SC0CR = 1, the rising edge or falling edge will be detected according to the setting of the SC0CR register to generate the basic clock. • In UART mode The SC0MOD0 setting determines whether the baud rate generator clock, the internal system clock fSYS, the match detect signal from timer TMRA0 or the external clock (SCLK0) is used to generate the basic clock SIOCLK. (4) Receiving counter The receiving counter is a 4-bit binary counter used in UART mode which counts up the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each data bit is sampled three times – on the 7th, 8th, and 9th clock cycles. The value of the data bit is determined from these three samples using the majority rule. For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th, and 9th clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is taken to be 0. (5) Receiving control • In I/O interface mode In SCLK output mode with the setting SC0CR = 0, the RXD0 signal is sampled on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR setting. In SCLK input mode with the setting SC0CR = 1, the RXD0 signal is sampled on the rising or falling edge of the SCLK0 input, according to the SC0CR setting. • In UART mode The receiving control block has a circuit which detects a start bit using the majority rule. Received bits are sampled three times; when two or more out of three samples are 0, the bit is recognized as the start bit and the receiving operation commences. The values of the data bits that are received are also determined using the majority rule. 91C829-123 2006-03-15 TMP91C829 (6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads receiving buffer 2 (SC0BUF). Even before the CPU has finished reading the contents of receiving buffer 2 (SC0BUF), more data can be received and stored in receiving buffer 1. However, if receiving buffer 2 (SC0BUF) has not been read completely before all the bits of the next data item are received by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and SC0CR will be preserved. SC0CR is used to store either the parity bit − added in 8-bit UART mode − or the most significant bit (MSB) − in 9-bit UART mode. In 9-bit UART mode the wakeup function for the slave controller is enabled by setting SC0MOD0 to 1; in this mode INTRX0 interrupts occur only when the value of SC0CR is 1. (7) Transmission counter The transmission counter is a 4-bit binary counter which is used in UART mode and which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16 SIOCLK clock pulses. SIOCLK 15 TXDCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 Figure 3.10.4 Generation of the Transmission Clock (8) Transmission controller • In I/O interface mode In SCLK output mode with the setting SC0CR = 0, the data in the transmission buffer is output one bit at a time to the TXD0 pin on the rising edge or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR setting. In SCLK input mode with the setting SC0CR = 1, the data in the transmission buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input, according to the SC0CR setting. • In UART mode When transmission data sent from the CPU is written to the transmission buffer, transmission starts on the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT. 91C829-124 2006-03-15 TMP91C829 Handshake function Use of CTS0 pin allows data can be sent in units of one frame; thus, overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD setting. When the CTS0 pin goes high on completion of the current data send, data transmission is halted until the CTS0 pin goes low again. However, the INTTX0 interrupt is generated, it requests the next data send to the CPU. The next data is written in the transmission buffer and data sending is halted. Although there is no RTS pin, a handshake function can easily be configured by assigning any port to perform the RTS function. The RTS should be output high to request send data halt after data receive is completed by software in the RXD interrupt routine. TMP91C829 TMP91C829 TXD CTS0 RXD RTS (Any port) Sender Receiver Figure 3.10.5 Handshake Function Timing to writing to the transmission buffer Send is suspended from (1) and (2). CTS (1) SIOCLK 13 (2) 14 15 16 1 2 3 14 15 16 1 2 3 TXDCLK Bit0 TXD Note 1: Start bit If the CTS signal goes high during transmission, no more data will be sent after completion of the current transmission. Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the CTS signal has fallen. Figure 3.10.6 CTS (Clear to send) Timing 91C829-125 2006-03-15 TMP91C829 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU, in order one bit at a time starting with the least significant bit (LSB) and finishing with the most significant bit (MSB). When all the bits have been shifted out, the empty transmission buffer generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR in the serial channel control register is set to 1, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode. The SC0CR field in the serial channel control register allows either even or odd parity to be selected. In the case of transmission, parity is automatically generated when data is written to the transmission buffer SC0BUF. The data is transmitted after the parity bit has been stored in SC0BUF in 7-bit UART mode or in SC0MOD0 in 8-bit UART mode. SC0CR and SC0CR must be set before the transmission data is written to the transmission buffer. In the case of receiving, data is shifted into receiving buffer 1, and the parity is added after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared with SC0BUF in 7-bit UART mode or with SC0CR in 8-bit UART mode. If they are not equal, a parity error is generated and the SC0CR flag is set. (11) Error flags Three error flags are provided to increase the reliability of data reception. 1. Overrun error If all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is generated. Following shows the overrun generating process flow example. (Receiving interrupts routine) (1) Read of receiving buffer (2) Read of error flag (3) If = “1” Then A) B) C) D) E) F) Set to receiving enable write “0” to Wait end of now flame Read of receiving buffer Read of error flag Set to receiving enable write “1” to Request transmission again (4) Other process 2. Parity error The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. 3. Framing error The stop bit for the received data is sampled three times around the center. If the majority of the samples are 0, a framing error is generated. 91C829-126 2006-03-15 TMP91C829 (12) Timing generation a. In UART mode Receiving Mode Interrupt timing Framing error timing Parity error timing Overrun error timing 9 Bits (Note) Center of last bit (Bit8) Center of stop bit − Center of last bit (Bit8) 8 Bits + Parity (Note) Center of last bit (Parity bit) Center of stop bit Center of last bit (Parity bit) Center of last bit (Parity bit) 8 Bits, 7 Bits + Parity, 7 Bits Center of stop bit Center of stop bit Center of stop bit Center of stop bit Note: In 9-bit mode and 8 bits + parity mode, interrupts coincide with the 9th bit pulse. Thus, when servicing the interrupt, it is necessary to allow a 1-bit period to elapse (So that the stop bit can be transferred) in order to allow proper framing error checking. Transmitting Mode Interrupt timing 9 Bits Just before stop bit is transmitted 8 Bits + Parity Just before last data bit is transmitted 8 Bits, 7 Bits + Parity, 7 Bits Just before last data bit is transmitted b. I/O interface SCLK output mode SCLK input mode SCLK output mode SCLK input mode Immediately after the last bit. (See Figure 3.10.19) Immediately after rise of last SCLK signal rising mode, or immediately after fall in falling mode. (See Figure 3.10.20) Timing used to transfer received to data receive buffer 2 (SC0BUF) (e.g., immediately after last SCLK). (See Figure 3.10.21) Timing used to transfer received data to receive buffer 2 (SC0BUF) (e.g., immediately after last SCLK). (See Figure 3.10.22) Transmission interrupt timing Receiving interrupt timing 91C829-127 2006-03-15 TMP91C829 3.10.3 SFRs 7 SC0MOD0 Bit symbol (0202H) Read/Write After reset Function TB8 0 Transfer data bit8 6 CTSE 0 0: CTS disable 1: CTS enable 5 RXE 0 function 0: Receive disable 1: Receive enable 4 WU R/W 0 Wakeup function 0: Disable 1: Enable 3 SM1 0 2 SM0 0 1 SC1 0 (UART) 00: TMRA0 trigger 0 SC0 0 Hand shake Receive Serial transmission mode Serial transmission clock 00: I/O interface Mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 01: Baud rate generator 10: Internal clock fSYS 11: External clcok (SCLK0 input) Serial transmission clock source (UART) 00 01 10 Timer TMRA0 match detect signal Baud rate generator Internal clock fSYS 11 External clock (SCLK0 input) Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC0CR). Serial transmission mode 00 01 10 11 I/O interface mode UART 7-bit mode 8-bit mode 9-bit mode Wakeup function 9-Bit UART Other modes Interrupt generated when data is received Don’t care Interrupt generated only when SC0CR = 1 0 1 Receiving function 0 1 Receive disabled Receive enabled Handshake function ( CTS pin) 0 1 Disabled (Always transferable) Enabled Transmission data bit8 Figure 3.10.7 Serial Mode Control Register (Channel 0, SC0MOD0) 91C829-128 2006-03-15 TMP91C829 7 SC1MOD0 Bit symbol (020AH) Read/Write After reset Function TB8 0 Transfer data bit8 6 CTSE 0 0: CTS disable 1: CTS enable 5 RXE 0 function 0: Receive disable 1: Receive enable 4 WU R/W 0 Wakeup function 0: Disable 1: Enable 3 SM1 0 2 SM0 0 1 SC1 0 (UART) 00: TMRA0 trigger 0 SC0 0 Hand shake Receive Serial transmission mode Serial transmission clock 00: I/O interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode 01: Baud rate generator 10: Internal clock fSYS 11: External clcok (SCLK1 input) Serial transmission clock source (UART) 00 01 10 Timer TMRA0 match detect signal Baud rate generator Internal clock fSYS 11 External clock (SCLK1 input) Note: The clock selection for the I/O interface mode is controlled by the serial control register (SC1CR). Serial transmission mode 00 01 10 11 I/O interface mode UART 7-bit mode 8-bit mode 9-bit mode Wakeup function 9-Bit UART Other modes Interrupt generated when data is received Don’t care Interrupt generated only when SC1CR = 1 0 1 Receiving function 0 1 Receive disabled Receive enabled Handshake function ( CTS pin) 0 1 Disabled (Always transferable) Enabled Transmission data bit8 Figure 3.10.8 Serial Mode Control Register (Channel 1, SC1MOD0) 91C829-129 2006-03-15 TMP91C829 7 SC0CR (0201H) Bit symbol Read/Write After reset Function RB8 R 6 EVEN R/W 5 PE 0 Parity addition 0: Disable 1: Enable 4 OERR 0 3 PERR 0 1: Error 2 FERR 0 1 SCLKS R/W 0 0: SCLK0 0 IOC 0 0: Baud rate generator 1: SCLK0 pin input R (Cleared to 0 when read.) Undefined 0 Received Parity data bit8 0: Odd 1: Even Overrun Parity Framing 1: SCLK0 I/O interface input clock selection 0 1 Baud rate generator SCLK0 pin input Edge selection for SCLK pin 0 1 Transmits and receivers data on rising edge of SCLK0. Transmits and receivers data on falling edge SCLK0. Framing error flag Parity error flag Overrun error flag Parity addition enable 0 1 Disabled Enabled Cleared to 0 when read. Even parity addition/check 0 1 Odd parity Even parity Received data bit8 Note: As all error flags are cleared after reading. Do not test only a single bit with a bit testing instruction. Figure 3.10.9 Serial Control Register (Channel 0, SC0CR) 91C829-130 2006-03-15 TMP91C829 7 SC1CR (0209H) Bit symbol Read/Write After reset Function RB8 R 6 EVEN R/W 5 PE 0 Parity addition 0: Disable 1: Enable 4 OERR 0 3 PERR 0 1: Error 2 FERR 0 1 SCLKS R/W 0 0: SCLK1 0 IOC 0 0: Baud rate generator 1: SCLK1 pin input R (Cleared to 0 when read.) Undefined 0 Received Parity data bit8 0: Odd 1: Even Overrun Parity Framing 1: SCLK1 I/O interface input clock selection 0 1 Baud rate generator SCLK0 pin input Edge selection for SCLK pin 0 1 Transmits and receivers data on rising edge of SCLK1. Transmits and receivers data on falling edge SCLK1. Framing error flag Parity error flag Overrun error flag Parity addition enable 0 1 Disabled Enabled Cleared to 0 when read. Even parity addition/check 0 1 Odd parity Even parity Received data bit8 Note: As all error flags are cleared after reading. Do not test only a single bit with a bit testing instruction. Figure 3.10.10 Serial Control Register (Channel 1, SC1CR) 91C829-131 2006-03-15 TMP91C829 7 BROCR (0203H) Bit symbol Read/Write After reset Function 0 Received data bit8 − 6 BR0ADDE 0 division 0: Disable 1: Enable 5 BR0CK1 0 01: φT2 10: φT8 11: φT32 4 3 2 BR0S2 0 1 BR0S1 0 0 BR0S0 0 BR0CK0 BR0S3 R/W 0 0 +(16 − K)/16 00: φT0 Setting of the divided frequency +(16 − K)/16 division enable 0 1 Disable Enable Setting the input clock of baud rate generator 00 01 10 11 Internal clock φT0 Internal clock φT2 Internal clock φT8 Internal clock φT32 7 BR0ADD (0204H) Bit symbol Read/Write After reset Function 6 5 4 3 BR0K3 0 2 BR0K2 R/W 0 1 BR0K1 0 0 BR0K0 0 Sets frequency divisor K (divided by N = (16 − K)/16) Sets baud rate generator frequency divisor BR0CR = 1 BR0CR DR0ADD 0000 0001 (K = 1) to 1111 (K = 15) Disable 0000 (N = 16) or 0001 (N = 1) Disable 0000 (N = 2) or 1111 (N = 15) Disable Divided by N + 16 − K 16 BR0CR = 0 0001 (N = 1) (Only UART) to 1111 (N = 15) 0000 (N = 16) Divided by N Note1:Availability of +(16-K)/16 division function N 2 to 15 1 , 16 UART mode ○ × I/O mode × × The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in I/O interface mode. Note2:Set BR0CR to 1 after setting K (K = 1 to 15) to BR0ADD when +(16-K)/16 division function is used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is read from these unused bits. Figure 3.10.11 Baud Rate Generator Control (Channel 0, BR0CR, BR0ADD) 91C829-132 2006-03-15 TMP91C829 7 BR1CR (020BH) Bit symbol Read/Write After reset Function 0 Received data bit8 − 6 BR1ADDE 0 division 0: Disable 1: Enable 5 BR1CK1 0 01: φT2 10: φT8 11: φT32 4 3 2 BR1S2 0 1 BR1S1 0 0 BR1S0 0 BR1CK0 BR1S3 R/W 0 0 +(16 − K)/16 00: φT0 Setting of the divided frequency +(16 − K)/16 division enable 0 1 Disable Enable Setting the input clock of baud rate generator 00 01 10 11 Internal clock φT0 Internal clock φT2 Internal clock φT8 Internal clock φT32 7 BR1ADD (020CH) Bit symbol Read/Write After reset Function 6 5 4 3 BR1K3 0 2 BR1K2 R/W 0 1 BR1K1 0 0 BR1K0 0 Sets frequency divisor K (divided by N = (16 − K)/16) Sets baud rate generator frequency divisor BR0CR = 1 BR1CR DR1ADD 0000 0001 (K = 1) to 1111 (K = 15) Disable 0000 (N = 16) or 0001 (N = 1) Disable 0000 (N = 2) or 1111 (N = 15) Disable Divided by N + 16 − K 16 BR1CR = 0 0001 (N = 1) (Only UART) to 1111 (N = 15) 0000 (N = 16) Divided by N Note1:Availability of +(16-K)/16 division function N 2 to 15 1 , 16 UART mode ○ × I/O mode × × The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in I/O interface mode. Note2:Set BR1CR to 1 after setting K (K = 1 to 15) to BR1ADD when +(16-K)/16 division function is used. Writes to unused bits in the BR1ADD register do not affext operation, and undefined data is read from these unused bits. Figure 3.10.12 Baud Rate Generator Control (Channel 1, BR1CR, BR1ADD) 91C829-133 2006-03-15 TMP91C829 7 TB7 SC0BUF (0200H) 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2 1 TB1 0 TB0 (Transmission) 7 RB7 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 (Receiving) Note: Prohibit read-modify-write for SC0BUF. Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF) 7 SC0MOD1 Bit symbol (0205H) Read/Write After reset Function I2S0 R/W 0 IDLE2 0: Stop 1: Run 6 FDPX0 R/W 0 Duplex 0: Half 1: Full 5 4 3 2 1 0 STSEN0 W 1 STS0 0: Enable 1: Disable Figure 3.10.14 Serial Mode Control Register 1 (Channel 0, SC0MOD1) 7 TB7 SC1BUF (0208H) 6 TB6 5 TB5 4 TB4 3 TB3 2 TB2 1 TB1 0 TB0 (Transmission) 7 RB7 6 RB6 5 RB5 4 RB4 3 RB3 2 RB2 1 RB1 0 RB0 (Receiving) Note: Prohibit read-modify-write for SC1BUF. Figure 3.10.15 Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF) 7 SC1MOD1 Bit symbol (020DH) Read/Write After reset Function I2S1 R/W 0 IDLE2 0: Stop 1: Run 6 FDPX1 R/W 0 Duplex 0: Half 1: Full 5 4 3 2 1 0 STSEN1 W 1 STS1 0:Enable 1:Disable Figure 3.10.16 Serial Mode Control Register 1 (Channel 1, SC1MOD1) 91C829-134 2006-03-15 TMP91C829 3.10.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input external synchronous clock SCLK. Output extension TMP91C829 TXD SCLK Port Shift register SI SCK RCK A B C D E F G H Input extension TMP91C829 RXD SCLK Port Shift register QH CLOCK S/ L A B C D E F G H TC74HC595 or equivalent TC74HC165 or equivalent Figure 3.10.17 Example of SCLK Output Mode Connection Output extension TMP91C829 TXD SCLK Port Shift register SI SCK RCK A B C D E F G H Input extension TMP91C829 RXD SCLK Port Shift register QH CLOCK S/ L A B C D E F G H TC74HC595 or equivalent External clock External clock TC74HC165 or equivalent Figure 3.10.18 Example of SCLK Input Mode Connection 91C829-135 2006-03-15 TMP91C829 a. Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all the data has been output, INTES0 is set to 1, causing an INTTX0 interrupt to be generated. Timing to write transmission data SCLK0 output (=0 Rising edge mode) SCLK0 output (=1 Falling edge mode) TXD0 ITX0C (INTTX0 Interrupt request) Bit0 Bit1 Bit6 Bit7 (Internal clock timing) Figure 3.10.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode) (Channel 0) In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0 input becomes active after the data has been written to the transmission buffer by the CPU. When all the data has been output, INTES0 is set to 1, causing an INTTX0 interrupt to be generated. SCLK0input ( = 0 Rising edge mode) SCLK0 input ( = 1 Falling edge mode) TXD0 ITX0C (INTTX0 Interrupt request) Bit0 Bit1 Bit5 Bit6 Bit7 Figure 3.10.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode) (Channel 0) 91C829-136 2006-03-15 TMP91C829 b. Receiving In SCLK output mode the synchronous clock is output on the SCLK0 pin and the data is shifted to receiving buffer 1. This is initiated when the receive interrupt flag INTES0 is cleared as the received data is read. When 8-bit data is received, the data is transferred to receiving buffer 2 (SC0BUF) following the timing shown below and INTES0 is set to 1 again, causing an INTRX0 interrupt to be generated. Setting SC0MOD0to 1 initiates SCLK0 output. IRX0C (INTRX0 interrupt request) SCLK0 output (=0 Rising edge mode) SCLK0 output (=1 Fallingf edge mode) RXD0 Bit0 Bit1 Bit6 Bit7 Figure 3.10.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode) (Channel 0) In SCLK input mode the data is shifted to receiving buffer 1 when the SCLK input goes active. The SCLK input goes active when the receive interrupt flag INTES0 is cleared as the received data is read. When 8-bit data is received, the data is shifted to receiving buffer 2 (SC0BUF) following the timing shown below and INTES0 is set to 1 again, causing an INTRX0 interrupt to be generated. SCLK0 input ( = 0: Rising edge mode) SCLK0 input ( = 1: Falling edge mode) RXD0 IRX0C (INTRX0 ) Bit0 Bit1 Bit5 Bit6 Bit7 Figure 3.10.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode) (Channel 0) Note: The system must be put in the receive enable state (SCMOD0 = 1) before data can be received. 91C829-137 2006-03-15 TMP91C829 c. Transmission and receiving (Full duplex mode) When full duplex mode is used, set the receive interrupt level to 0 and set enable the level of transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data. The following is an example of this: Example: Channel 0, SCLK output Baud rate = 9600 bps fc = 14.7456 MHz * Clock state System clock: Clock gear: Main routine INTES0 P8CR P8FC 7 0 – – 6 0 – – 0 1 0 0 0 * 5 0 – – 0 0 0 1 1 * 4 1 – – 0 0 0 1 0 * 3 0 – – 0 0 0 0 0 * 2 0 1 1 0 0 0 0 0 * 1 0 0 – 0 0 0 1 0 * 0 0 1 1 0 0 0 1 0 * Select I/O interface mode. Select full duplex mode. SCLK_out, transmit on negative edge, receive on positive edge. BR0CR SC0BUF 0 * Baud rate = 9600 bps. Enable receiving. Set the transmit data and start. SC0MOD0 0 Set the INTTX0 level to 1. Set the INTRX0 level to 0. Set P80, P81, and P82 to function as the TXD0, RXD0, and SCLK0 pins respectively. SC0MOD0 0 SC0MOD1 1 SC0CR 0 High frequency (fc) 1 (fc) Prescaler clock: fFPH INTTX0 interrupt routine Acc SC0BUF SC0BUF – – X X – 1 X X Read the receiving buffer. Set the next transmit data. X: Don’t care, −: No change 91C829-138 2006-03-15 TMP91C829 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting the serial channel mode register SC0MOD0 field to 01. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR bit; whether even parity or odd parity will be used is determined by the SC0CR setting when SC0CR is set to 1 (Enabled). Setting example: When transmitting data of the following format, the control registers should be set as described below. This explanation applies to channel 0. Start Bit0 1 2 3 4 5 6 Even parity Stop Transmission direction (Transmission rate: 2400 bps at fc = 12.288 MHz) * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock P8CR P8FC SC0MOD SC0CR BR0CR INTES0 SC0BUF ← ← ← ← ← ← ← − − X X 0 1 76543210 −−−−−−1 −−−−−−1 0−X0101 11XXX00 0100101 100−−−− ******** Set P80 to function as the TXD0 pin. Select 7-bit UART mode. Add even parity. Set the transfer rate to 2400 bps. Enable the INTTX0 interrupt and set it to interrupt level 4. Set data for transmission. X: Don’t care, −: No change (3) Mode 2 (8-bit UART mode) 8-bit UART mode is selected by setting SC0MOD0 to 10. In this mode a parity bit can be added (Use of a parity bit is enabled or disabled by the setting of SC0CR); whether even parity or odd parity will be used is determined by the SC0CR setting when SC0CR is set to 1 (Enabled). Setting example: When receiving data of the following format, the control registers should be set as described below. Start Bit0 1 2 3 4 5 6 7 Odd parity Stop Transmission direction (Transmission rate: 9600 bps at fc = 12.288 MHz) 91C829-139 2006-03-15 TMP91C829 * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock 0 − 1 0 1 0 Main settings P8CR SC0MOD SC0CR BR0CR INTES0 ← ← ← ← ← 7654321 −−−−−−0 −01X100 X01XXX0 0001010 −−−−110 Set P80 to function as the TXD0 pin. Enable receiving in 8-bit UART mode. Add even parity. Set the transfer rate to 9600 bps. Enable the INTTX0 interrupt and set it to interrupt level 4. Interrupt processing Acc ← SC0CR AND 00011100 if Acc ≠ 0 then ERROR Acc ← SC0BUF X: Don’t care, −: No change Check for errors. Read the received data. (4) Mode 3 (9-bit UART mode) 9-bit UART mode is selected by setting SC0MOD0 to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is written to SC0MOD0. In the case of receiving it is stored in SC0CR. When the buffer is written and read, the MSB is read or written first, before the rest of the SC0BUF data. Wakeup function In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting SC0MOD0 to 1. The interrupt INTRX0 can only be generated when = 1. TXD RXD TXD RXD TXD RXD TXD RXD Master Slave 1 Slave 2 Slave 3 Note: The TXD pin of each slave controller must be in open-drain output mode. Figure 3.10.23 Serial Link Using Wakeup Function 91C829-140 2006-03-15 TMP91C829 Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC0MOD0 bit on each slave controller to 1 to enable data receiving. c. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller. The MSB (Bit8) of the data () is set to 1. Start Bit0 1 2 3 4 5 6 7 8 1 Stop Select code of slave controller d. Each slave controller receives the above frame. Each controller checks the above select code against its own select code. The controller whose code matches clears its WU bit to 0. e. The master controller transmits data to the specified slave controller (The controller whose SC0MOD bit has been cleared to 0). The MSB (Bit8) of the data () is cleared to 0. Start Bit0 1 2 3 Data 4 5 6 7 Bit8 0 Stop f. The other slave controllers (Whose bits remain at 1) ignore the received data because their MSBs (Bit8 or ) are set to 0, disabling INTRX0 interrupts. The slave controller whose WU bit = 0 can also transmit to the master controller. In this way it can signal the master controller that the data transmission from the master controller has been completed. 91C829-141 2006-03-15 TMP91C829 Setting example: To link two slave controllers serially with the master controller using the internal clock fSYS as the transfer clock. TXD RXD TXD RXD TXD RXD Master Slave 1 Select code 00000001 Slave 2 Select code 00001010 Since serial channels 0 and 1 operate in exactly the same way, channel 0 only is used for the purposes of this explanation. • Setting the master controller Main P8CR P8FC INTES0 SC0MOD0 SC0BUF ←−−−−−−01 ←−−−−−−X1 ←11001101 ←10101110 ←00000001 Set P80 and P81 to function as the TXD0 and RXD0 pins respectively. Enable the INTTX0 interrupt and set it to interrupt level 4. Enable the INTRX0 interrupt and set it to interrupt level 5. Set fSYS as the transmission clock for 9-bit UART mode. Set the select code for slave controller 1. INTTX0 interrupt SC0MOD0 SC0BUF ←0−−−−−−− ←******** Set TB8 to TB0. Set data for transmission. • Setting the slave controller Main P8CR P8FC ODE INTES0 SC0MOD0 ← ← ← ← ← − − X 1 0 − − X 1 0 − − X 0 1 − − X 1 1 − − X 1 1 − − X 1 1 01 X1 −1 10 10 Select P81 and P80 to function as the RXD0 and TXD0 pins respectively (Open-drain output). Enable INTRX0 and INTTX0. Set to 1 in 9-bit UART transmission mode using fSYS as the transfer clock. INTRX0 interrupt Acc ← SC0BUF if Acc = Select code then SC0MOD0 ← − − − 0 − − − − Clear to 0. 91C829-142 2006-03-15 TMP91C829 3.11 Analog/Digital Converter The TMP91C829 incorporates a 10-bit successive approximation type analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are shared with the input-only port, port A and can thus be used as an input port. Note: When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled. Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed. Internal data bus AD mode control register 1 ADMOD1 ADMOD1 AD mode control register 0 ADMOD0 Scan Repeat Interrupt Busy End Start AD converter control circuit INTAD interrupt ADTRG Analog input AN7 (PA7) AN6 (PA6) AN5 (PA5) Multiplexer AN4 (PA4) AN3 (PA3) AN2 (PA2) AN1 (PA1) AN0 (PA0) ADTRG (PA3) Decoder Channel select AD conversion result Sample and hold + − Comparator register ADREG04L to ADREG37L ADREG04H to ADREG37H VREFH VREFL DA converter Figure 3.11.1 Block Diagram of AD Converter 91C829-143 2006-03-15 TMP91C829 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the two AD mode control registers: ADMOD0 and ADMOD1. The eight AD conversion data upper and lower registers (ADREG04H/L, ADREG15H/L, ADREG26H/L, and ADREG37H/L) store the results of AD conversion. Figure 3.11.2 shows the registers related to the AD converter. AD Mode Control Register 0 7 ADMOD0 Bit symbol (02B0H) Read/Write After reset Function AD conversion end flag in progress complete 6 ADBF R 0 AD conversion busy flag stopped in progress 5 − 0 Always write “0”. 4 − 0 Always write “0”. 3 ITM0 0 Interrupt specification channel fixed 0: Every conversion 1: Every fourth conversion 2 REPEAT R/W 0 1 SCAN 0 AD 0 ADS 0 conversion 0: Don’t care 1: Start conversion Always “0” when read. EOCF 0 Repeat mode Scan mode specification specification conversion channel fixed mode channel scan mode in conversion 0: Single repeat mode 1: Repeat mode 0: Conversion start 0: Conversion 0: Conversion 1: Conversion 1: Conversion conversion 1: Conversion AD conversion start 0 1 Don’t care Start AD conversion Note: Always read as 0. AD scan mode setting 0 1 AD conversion channel fixed mode AD conversion channel scan mode AD repeat mode setting 0 1 AD single conversion mode AD repeat conversion mode Specify AD conversion interrupt for channel fixed repeat conversion mode Channel fixed repeat conversion mode = 0, = 1 0 1 Generates interrupt every conversion. Generates interrupt every fourth conversion. AD conversion busy flag 0 1 AD conversion stopped AD conversion in progress AD conversion end flag 0 1 Before or during AD conversion AD conversion complete Figure 3.11.2 AD Converter Related Register 91C829-144 2006-03-15 TMP91C829 AD Mode Control Register 1 7 ADMOD1 Bit symbol (02B1H) Read/Write After reset Function VREFON R/W 0 VREF application control 0: OFF 1: ON 6 I2AD R/W 0 IDLE2 0: Stop 1: Operate 5 4 3 ADTRGE 0 trigger start control 0: Disable 1: Enable 2 ADCH2 R/W 0 1 ADCH1 0 0 ADCH0 0 AD external Analog input channel selection. Analog input channel selection 000 001 010 011 100 101 110 111 0 Channel fixed AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AN0 → AN1 AN0 → AN1 → AN2 AN0 → AN1 → AN2 → AN3 AN4 AN4 → AN5 AN4 → AN5 → AN6 AN4 → AN5 → AN6 → AN7 1 Channel scanned AD conversion start control by external trigger ( ADTRG input) 0 1 Disabled Enabled IDLE2 control 0 1 Stopped In operation Control of application of reference voltage to AD converter 0 1 OFF ON Before starting conversion (before writing 1 to ADMOD0), set the bit to 1. AD Mode Control Register 2 7 ADMOD2 (2B2H) Bit symbol Read/Write After reset Function 0 0 0 1 ADM27 6 ADM26 5 ADM25 4 ADM24 R/W 3 ADM23 0 2 ADM22 0 1 ADM21 0 0 ADM20 1 Please write 1E AD Mode Control Register 3 7 ADMOD3 (2B3H) Bit symbol Read/Write After reset Function 1 1 0 0 ADM37 6 ADM36 5 ADM35 4 ADM34 R/W 3 ADM33 1 2 ADM32 1 1 ADM31 1 0 ADM30 1 Please write CF Figure 3.11.3 AD Converter Related Register 91C829-145 2006-03-15 TMP91C829 AD Conversion Data Lower Register 0/4 7 ADREG04L Bit symbol (02A0H) Read/Write After reset Function ADR01 R Undefined Stores lower 2 bits of AD conversion result. 6 ADR00 5 4 3 2 1 0 ADR0RF R 0 AD conversion data storage flag 1: Conversion result stored 7 ADREG04H Bit symbol (02A1H) Read/Write After reset Function ADR09 AD Conversion Data Upper Register 0/4 6 5 4 3 ADR08 ADR07 ADR06 R Undefined ADR05 2 ADR04 1 ADR03 0 ADR02 Stores upper 8 bits AD conversion result. 7 ADREG15L Bit symbol (02A2H) Read/Write After reset Function ADR11 R AD Conversion Data Lower Register 1/5 6 5 4 3 ADR10 2 1 0 ADR1RF R 0 AD conversion result flag 1: Conversion result stored Undefined Stores lower 2 bits of AD conversion result. 7 ADREG15H Bit symbol (02A3H) Read/Write After reset Function ADR19 AD Conversion Data Upper Register 1/5 6 5 4 3 ADR18 ADR17 ADR16 R Undefined ADR15 2 ADR14 1 ADR13 0 ADR12 Stores upper 8 bits AD conversion result. 9 Channel x conversion result 8 7 6 5 4 3 2 1 0 ADREGxH 7 6 5 4 3 2 1 0 7 6 ADREGxL 5 4 3 2 1 0 • Bits 5 to 1 are always read as 1. • Bit0 is the AD conversion data storage flag . When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.11.4 AD Converter Related Registers 91C829-146 2006-03-15 TMP91C829 AD Conversion Result Lower Register 2/6 7 ADREG26L Bit symbol (02A4H) Read/Write After reset Function ADR21 R Undefined Stores lower 2 bits of AD conversion result. 6 ADR20 5 4 3 2 1 0 ADR2RF R 0 AD conversion data storage flag 1: Conversion result stored 7 ADREG26H Bit symbol (02A5H) Read/Write After reset Function ADR29 AD Conversion Data Upper Register 2/6 6 5 4 3 ADR28 ADR27 ADR26 R Undefined ADR25 2 ADR24 1 ADR23 0 ADR22 Stores upper 8 bits of AD conversion result. 7 ADREG37H Bit symbol (02A6H) Read/Write After reset Function ADR31 R AD Conversion Data Lower Register 3/7 6 5 4 3 ADR30 2 1 0 ADR3RF R 0 AD date storage 1: Conversion result stored Undefined Stores lower 2 bits of AD conversion result. 7 ADREG37H Bit symbol (02A7H) Read/Write After reset Function ADR39 AD Conversion Result Upper Register 3/7 6 5 4 3 ADR38 ADR37 ADR36 R Undefined ADR35 2 ADR34 1 ADR33 0 ADR32 Stores upper 8 bits of AD conversion result. 9 Channel x conversion result 8 7 6 5 4 3 2 1 0 ADREGxH 7 6 5 4 3 2 1 0 7 6 ADREGxL 5 4 3 2 1 0 • Bits 5 to 1 are always read as 1. • Bit0 is the AD conversion data storage flag . When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.11.5 AD Converter Related Registers 91C829-147 2006-03-15 TMP91C829 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL, is divided by 1024 using string resistance. The result of the division is then compared with the analog input voltage. To turn off the switch between VREFH and VREFL, write a 0 to ADMOD1 in AD mode control register 1. To start AD conversion in the off state, first write a 1 to ADMOD1, wait 3 μs until the internal reference voltage stabilizes (This is not related to fc.), then set ADMOD0 to 1. (2) Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter. • In analog input channel fixed mode (ADMOD0 = 0) Setting ADMOD1 selects one of the input pins AN0 to AN7 as the input channel. In analog input channel scan mode (ADMOD0 = 1) Setting ADMOD1 selects one of the eight scan modes. Table 3.11.1 illustrates analog input channel selection in each operation mode. On a reset, ADMOD0 is set to 0 and ADMOD1 is initialized to 000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input channels can be used as standard input port pins. Table 3.11.1 Analog Input Channel Selection 000 001 010 011 100 101 110 111 • Channel Fixed = 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0 Channel Scan = 1 AN0 → AN1 AN0 → AN1 → AN2 AN0 → AN1 → AN2 → AN3 AN4 AN4 → AN5 AN4 → AN5 → AN6 AN4 → AN5 → AN6 → AN7 (3) Starting AD conversion To start AD conversion, write a 1 to ADMOD0 in AD mode control register 0 or ADMOD1 in AD mode control register 1, pull the ADTRG pin input from high to low. When AD conversion starts, the AD conversion busy flag ADMOD0 will be set to 1, indicating that AD conversion is in progress. Writing a 1 to ADMOD0 during AD conversion restarts conversion. At that time, to determine whether the AD conversion results have been preserved, check the value of the conversion data storage flag ADREGxL. During AD conversion, a falling edge input on the ADTRG pin will be ignored. 91C829-148 2006-03-15 TMP91C829 (4) AD conversion modes and the AD conversion end interrupt The four AD conversion modes are: • • • • Channel fixed single conversion mode Channel scan single conversion mode Chanel fixed repeat conversion mode Channel scan repeat conversion mode The ADMOD0 and ADMOD0 settings in AD mode control register 0 determine the AD mode setting. Completion of AD coversion triggers an INTAD AD conversion end interrupt request. Also, ADMOD0 will be set to 1 to indicate that AD conversion has been completed. a. Channel fixed single conversion mode Setting ADMOD0 and ADMOD0 to 00 selects conversion channel fixed single conversion mode. In this mode data on one specified channel is converted once only. When the conversion has been completed, the ADMOD0 flag is set to 1, ADMOD0 is cleared to 0, and an INTAD interrupt request is generated. b. Channel scan single conversion mode Setting ADMOD0 and ADMOD0 to 01 selects conversion channel scan single conversion mode. In this mode data on the specified scan channels is converted once only. When scan conversion has been completed, ADMOD0 is set to 1, ADMOD0 is cleared to 0, and an INTAD interrupt request is generated. c. Channel fixed repeat conversion mode Setting ADMOD0 and ADMOD0 to 10 selects conversion channel fixed repeat conversion mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0 is set to 1 and ADMOD0 is not cleared to 0 but held at 1. INTAD interrupt request generation timing is determined by the setting of ADMOD0. Setting to 0 generates an interrupt request every time an AD conversion is completed. Setting to 1 generates an interrupt request on completion of every fourth conversion. 91C829-149 2006-03-15 TMP91C829 d. Channel scan repeat conversion mode Setting ADMOD0 and ADMOD0 to 11 selects conversion channel scan repeat conversion mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0 is set to 1 and an INTAD interrupt request is generated. ADMOD0 is not cleared to 0 but held at 1. To stop conversion in a repeat conversion mode (e.g., in cases of c and d), write a 0 to ADMOD0. After the current conversion has been completed, the repeat conversion mode terminates and ADMOD0 is cleared to 0. Switching to a halt state (IDLE2 mode with ADMOD1 cleared to 0, IDLE1 mode or STOP mode) immediately stops operation of the AD converter even when AD conversion is still in progress. In repeat conversion modes (e.g., in cases of c and d), when the halt is released, conversion restarts from the beginning. In single conversion modes (e.g., in cases of a and b), conversion does not restart when the halt is released (The converter remains stopped). Table 3.11.2 shows the relationship between the AD conversion modes and interrupt requests. Table 3.11.2 Relationship between AD Conversion Modes and Interrupt Requests Mode Channel fixed single conversion mode Channel scan single conversion mode Channel fixed repeat conversion mode Channel scan repeat conversion mode X: Don’t care Interrupt Request Generation After completion of conversion After completion of scan conversion Every conversion Every forth conversion After completion of every scan conversion X X 0 1 X ADMOD0 0 0 1 1 0 1 0 1 (5) AD conversion time 84 states (4.7 μs at fFPH = 36 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG04H/L to ADREG37H/L) store the results of AD conversion. (ADREG04H/L to ADREG37H/L are read-only registers.) In channel fixed repeat conversion mode, the conversion results are stored successively in registers ADREG04H/L to ADREG37H/L. In other modes the AN0 and AN4, AN1 and AN5, AN2 and AN6, AN3 and AN7 conversion results are stored in ADREG04H/L, ADREG15H/L, ADREG26H/L, and ADREG37H/L respectively. Table 3.11.3 shows the correspondence between the analog input channels and the registers which are used to hold the results of AD conversion. 91C829-150 2006-03-15 TMP91C829 Table 3.11.3 Correspondence between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog Input Channel (Port A) AN0 AN4 AN1 AN5 AN2 AN6 AN3 AN7 ADREG37H/L ADREG37H/L Conversion Modes Other than at Right ADREG04H/L Channel Fixed Repeat Conversion Mode (every 4 th conversion) ADREG04H/L ADREG15H/L ADREG26H/L ADREG15H/L ADREG26H/L , bit0 of the AD conversion data lower register, is used as the AD conversion data storage flag. The storage flag indicates whether the AD conversion result register has been read or not. When a conversion result is stored in the AD conversion result register, the flag is set to 1. When either of the AD conversion result registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0. Reading the AD conversion result also clears the AD conversion end flag ADMOD0 to 0. Setting example: a. Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Main routine: 76543210 INTE0AD ADMOD1 ADMOD0 ←X100---←11XX0011 ←XX000001 Enable INTAD and set it to interrupt level 4. Set pin AN3 to be the analog input channel. Start conversion in channel fixed single conversion mode. Interrupt routine processing example: WA WA (0800H) ← ADREG37 >>6 ← WA Read value of ADREG37L and ADREG37H into 16-bit general-purpose register WA. Shift contents read into WA six times to right and zero fill upper bits. Write contents of WA to memory address 0800H. b. This example repeatedly converts the analog input voltages on the three pins AN0, AN1, and AN2, using channel scan repeat conversion mode. INTE0AD ADMOD1 ADMOD0 ←X000---←11XX0010 ←XX000111 Disable INTAD. Set pins AN0 to AN2 to be the analog input channels. Start conversion in channel scan repeat conversion mode. X: Don’t care, −: No change 91C829-151 2006-03-15 TMP91C829 3.12 Watchdog Timer (Runaway detection timer) The TMP91C829 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset. (The level of external RESET pin is not changed.) 3.12.1 Configuration Figure 3.12.1 is a block diagram of the watchdog timer (WDT). WDMOD RESET Reset control Internal reset WDTI interrupt WDMOD 2 fSYS (fFPH/2) 15 Selector 21 2 17 219 2 Binary counter (22 Stage) Reset R Q S Internal reset Write 4EH Write B1H WDMOD WDT control register WDCR Internal data bus Figure 3.12.1 Block Diagram of Watchdog Timer Note: The watchdog timer cannot operate by disturbance noise in some case. Take care when design the device. 91C829-152 2006-03-15 TMP91C829 The watchdog timer consists of a 22-stage binary counter which uses the system clock (fSYS) as the input clock. The binary counter can output fSYS/215, fSYS/217, fSYS/219 and fSYS/221. WDT counter n Overflow 0 WDT interrupt Clear write code WDT clear (Soft ware) Figure 3.12.2 Normal Mode The runaway is detected when an overflow occurs, and the watchdog timer can reset device. In this case, the reset time will be between 22 and 29 states (19.6 to 25.8 μs at fFPH = 36MHz, fOSCH = 2.25 state) is fFPH/2, where fFPH is generated by dividing the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function. Overflow WDT counter n WDT interrupt Internal reset (19.6 to 25.8 μs 22 to 29 states at fOSCH = 36 MHz, fFPH = 2.25 MHz) Figure 3.12.3 Reset Mode 91C829-153 2006-03-15 TMP91C829 3.12.2 Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a reset this register is initialized to WDMOD = 00. The detection times for WDT are shown in Figure 3.12.4. b. Watchdog timer enable/disable control register On a reset WDMOD is initialized to 1, enabling the watchdog timer. To disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (B1H) to the watchdog timer control register . This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting to 1. c. Watchdog timer out reset connection This register is used to connect the output of the watchdog timer with the RESET terminal internally. Since WDMODis initialized to 0 on a reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear the binary counter for the watchdog timer. • Disable control The watchdog timer can be disabled by clearing WDMOD to 0 and then writing the disable code (B1H) to the WDCR register. WDMOD WDCR ←0------←10110001 Clear WDMOD to 0. Write the disable code (B1H). • Enable control Set WDMOD to 1. • Watchdog timer clear control To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR register. WDCR ←01001110 Write the clear code (4EH). Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please refer to setting example.) Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once. 91C829-154 2006-03-15 TMP91C829 7 WDMOD (0300H) Bit symbol Read/Write After reset Function WDTE R/W 1 6 WDTP1 R/W 0 5 WDTP0 0 4 3 2 I2WDT R/W 0 IDLE2 0: Stop 1: Operate 1 RESCR 0 0 − R/W 0 WDT control Select detecting time 15 1: Enable 00: 2 /fSYS 01: 2 /fSYS 10: 2 /fSYS 11: 2 /fSYS 21 19 17 1: Internally Always connects write “0”. WDL out to the reset pin Watchdog timer out control 0 1 − Connects WDT out to a reset IDLE2 control 0 1 Watchdog timer detection time SYSCR1 Gear Value 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) Watchdog Timer Detection Time WDMOD 00 1.82 ms 3.64 ms 7.28 ms 14.56 ms 29.13 ms 01 7.28 ms 14.56 ms 29.13 ms 58.25 ms 116.51 ms 10 29.13 ms 58.25 ms 116.51 ms 232.02 ms 466.03 ms 11 116.51 ms 233.02 ms 466.03 ms 932.07 ms 1864.14 ms Stop Operation fc = 36 MHz Watchdog timer enable/disable control 0 1 Disabled Enabled Figure 3.12.4 Watchdog Timer Mode Register 7 WDCR (0301H) Read -modify -write instruction is prohibited 6 5 4 − 3 W − 2 1 0 Bit symbol Read/Write After reset Function B1H: WDT disable code 4EH: WDT clear code Disable/clear WDT B1H 4EH Others Disable code Clear code Don’t care Figure 3.12.5 Watchdog Timer Control Register 91C829-155 2006-03-15 TMP91C829 3.12.3 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD has elapsed. The watchdog timer must be zero cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (Runaway) due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti-mulfunction program. By connecting the watchdog timer out pin to a peripheral device’s reset input, the occurrence of a CPU malfunction can also be relayed to other devices. The watch dog timer works immediately after reset. The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter continues counting during bus release (When BUSAK goes low). When the device is in IDLE2 mode, the operation of WDT depends on the WDMOD setting. Ensure that WDMOD is set before the device enters IDLE2 mode. Example: a. Clear the binary counter. WDCR ←01001110 Write the clear code (4EH). b. Set the watchdog timer detection time to 217/fSYS. WDMOD ←101----←0-----XX ←10110001 c. Disable the watchdog timer. WDMOD WDCR Clear WDTE to 0. Write the disable code (B1H). 91C829-156 2006-03-15 TMP91C829 3.13 Multi Vector Control 3.13.1 Multi Vector Controller (1) Outline By rewriting the value of multi vector control register (MVEC0 and MVEC1), a vector table is arbitrarily movable. (2) Control register The amount of 228 bytes become an interruption vector area from the value set as vector control register (MVEC0 and MVEC1). Vector control register composition 7 MVEC0 Bit symbol (00AEH) Read/Write After reset Function VEC7 R/W 1 6 VEC6 R/W 1 5 VEC5 R/W 1 4 VEC4 R/W 1 3 VEC3 R/W 1 2 VEC2 R/W 1 1 VEC1 R/W 1 0 VEC0 R/W 1 Vector address A15 to A8 7 MVEC1 Bit symbol (00AFH) Read/Write After reset Function VEC15 R/W 1 6 VEC14 R/W 1 5 VEC13 R/W 1 4 VEC12 R/W 1 3 VEC11 R/W 1 2 VEC10 R/W 1 1 VEC9 R/W 1 0 VEC8 R/W 1 Vector address A23 to A16 Circuit composition CPU OUTPUT address AL23 to AL8 AL23 to AL8 CS circuit from FFFF28H to FFFFFFH CS AL8 Register (MVEC0) S A Y B A8 Internal address A23 to A8 Register (MVEC1) AL23 A23 Note: Write MVEC1, MVEC0 after making an interruption prohibition state. 91C829-157 2006-03-15 TMP91C829 3.13.2 Multi Boot Mode (1) Outline The TMP91C829 has multi boot mode available as an on-board programming operation mode. When in multi boot mode, the boot ROM is mapped into memory space. This boot ROM is a mask ROM that contains a program to rewrite the flash memory on board. Rewriting is accomplished by connecting the TMP91C829’s SIO and the programming tool (Controller) and then sending commands from the controller to the target board. The boot program included in the boot ROM only has the function of a loader for transferring program data from an external source into the device’s internal RAM. Rewriting can be performed by UART. From 1000H to 105FH in device’s internal RAM is work area of boot program. Don’t transfer program data in this work area. Figure 3.12.1 shows an example of how to connect the programming controller and the target board (when ROM has 16-bit data bus). UART 3 pin Programming controller TXD0 (Output) RXD0 (Input) RTS0 (P83) (Output) CS2 RD WR CS OE WE TMP91C829 ROM D0 to D15 AD0 to AD15 Boot/normal BOOT D0 to D15 A1 to A16 Figure 3.13.1 Example for Connecting Units for On-board Programming (2) Mode setting To execute on-board programming, start the TMP91C829 in multi boot mode. Settings necessary to start up in multi boot mode are shown below. BOOT = = L RESET After setting the BOOT pin each to the above conditions and a RESET , the TMP91C829 start up in multi boot mode. 91C829-158 2006-03-15 TMP91C829 (3) Memory map Figure 3.12.2 shows memory maps for multi chip and multi boot modes. When start up in multi boot mode, internal boot ROM is mapped in FFF800H address, the boot program starts up. When start up in multi chip mode, internal boot ROM is mapped in 1F800H address, it can be made to operate arbitrarily by the user. Program starting address is 1F800H. Multi chip mode 000000H 000100H Internal I/O (4 Kbytes) 000000H 000100H Multi boot mode Internal I/O (4 Kbytes) Direct area (n) 001000H Internal RAM (8 Kbytes) 003000H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH 001000H Internal RAM (8 Kbytes) 003000H 16-Mbyte area (r32) (−r32) (r32+) (r32 + d8/16) (r32 + r8/16) (nnn) External memory External memory FFF800H FFFEFFH FFFF00H FFFFFFH Vector table (256 bytes) FFFF00H FFFFFFH Internal boot ROM (2 Kbytes) Vector table (256 bytes) ( = Internal area) Figure 3.13.2 TMP91C829 Memory Map 91C829-159 2006-03-15 TMP91C829 (4) SIO interface specifications The following shows the SIO communication format in multi boot mode. Before on-board programming can be executed, the communication format on the programming controller side must also be setup in the same way as for the TMP91C829. Note that although the default baud rate is 9600 bps, it can be changed to other values as shown in Table 3.13.3. Serial transfer mode: Data length: Parity bit: STOP bit: Handshake: Baud rate (Default): UART (Asynchronous communication) mode, full-duplex communication. 8 bits. None. 1 bit. Microcontroller (P83) → Programming controller. 9600 bps. (5) SIO data transfer format Table 3.13.1 through 3.13.6 show supported frequencies, data transfer format, baud rate modification commands, operation commands, version management information, and frequency measurement result with data store location, respectively. Also refer to the description of boot program operation in the latter pages of this manual as you read these tables. Table 3.13.1 Supported Frequencies 16.000 MHz 20.000 MHz 22.579 MHz 25.000 MHz 32.000 MHz 33.868 MHz 36.000 MHz Table 3.13.2 Transfer Format Number of Bytes Transferred Boot ROM 1st byte 2nd byte 3rd byte : 6th byte 7th byte 8th byte 9th byte 10th byte : n’th − 4 byte n’th − 3 byte n’th − 2 byte n’th − 1 byte n’th byte RAM − Transfer Data from Controller to TMP91C829 Matching data (5AH) − − Baud Rate 9600 bps 9600 bps 9600 bps Transfer Data from TMP91C829 to Controller − (Frequency measurement and baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted Version management information (See Table 3.13.5) Frequency information (See Table 3.13.6) − OK: Echo back data Error: Error code X 3 − 9600 bps 9600 bps 9600 bps Baud rate modification command (See Table 3.13.3) − User program extended Intel Hex format (Binary) − − Changed new baud rate Error: Operation stop by checksum error Changed new baud rate OK: SUM (High) (See (6) (iii) Notes on SUM) Changed new baud rate OK: SUM (Low) Changed new baud rate − Changed new baud rate OK: Echo back data (C0H) Error: Error code X 3 User program start command (C0H) (See Table 3.13.4) − JUMP to user program start address Error code X 3 means sending an error code three times. Example, when error code is 62H, TMP91C829 sends 62H three times. About error code, see (6)(b) Error code. 91C829-160 2006-03-15 TMP91C829 Table 3.13.3 Baud Rate Modification Command Baud Rate (bps) Modification Command 9600 28H 19200 18H 38400 07H 57600 06H 115200 03H Table 3.13.4 Operation Command Operation Command C0H Operation Start user program Table 3.13.5 Version Management Information Version Information FRM1 ASCII code 46H, 52H, 4DH, 31H Table 3.13.6 Frequency Measurement Result Data Frequency of Resonator (MHz) 1000H (RAM store address) 16.000 00H 20.000 01H 22.579 02H 25.000 03H 32.000 04H 33.868 05H 36.000 06H (6) Description of SIO boot program operation When you start the TMP91C829 in multi BOOT mode, the boot program starts up. The boot program provides the RAM loader function described below. RAM loader The RAM loader transfers the data sent from the controller in extended Intel Hex format into the internal RAM. When the transfer has terminated normally, the RAM loader calculates the SUM and sends the result to the controller before it starts executing the user program. The execution start address is the first address received. This RAM loader function provides the user’s own way to control on-board programming. To execute on-board programming in the user program, you need to use the flash memory command sequence to be connected. (Must be matched to the flash memory addresses in multi boot mode.) a. Operational procedure of RAM loader 1. Connect the serial cable. Make sure to perform connection before resetting the microcontroller. 2. Set the BOOT pin to “boot” and reset the microcontroller. 3. The receive data in the 1st byte is the matching data. When the boot program starts in multi boot mode, it goes to a state in which it waits for the matching data to receive. Upon receiving the matching data, it automatically adjusts the serial channels’ initial baud rate to 9600 bps. The matching data is 5AH. 4. The 2nd byte is used to echo back 5AH to the controller upon completion of the automatic baud rate setting in the 1st byte. If the device fails in automatic baud rate setting, it goes to an idle state. 5. The 3rd byte through 6th byte are used to send the version management information of the boot program in ASCII code. The controller should check that the correct version of the boot program is used. 91C829-161 2006-03-15 TMP91C829 6. The 7th byte is used to send information of the measured frequency. The controller should check that the frequency of the resonator is measured correctly. 7. The receive data in the 8th byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table 3.13.3 are available. Even when you do not change the baud rate, be sure to send the initial baud rate data (28H; 9600 bps). Baud rate modification becomes effective after the echo back transmission is completed. 8. The 9th byte is used to echo back the received data to the controller when the data received in the 8th byte is one of the baud rate modification data corresponding to the device’s operating frequency. Then the baud rate is changed. If the received baud rate data does not correspond to the device’s operating frequency, the device goes to an idle state after sending 3 bytes of baud rate modification error code (62H). 9. The receive data in the 10th byte through n’th – 4 byte is received as binary data in extended Intel Hex format. No received data is echoed back to the controller. The RAM loader processing routine ignores the received data until it receives the start mark (3AH for “:”) in extended Intel Hex format. Nor does it send error code to the controller. After receiving the start mark, the routine receives a range of data from the data length to checksum and writes the received data to the specified RAM addresses successively. After receiving one record of data from start mark to checksum, the routine goes to a start mark waiting state again. If a receive error or checksum error of extended Intel Hex format occurs, the device goes to an idle state without returning error code to the controller. Because the RAM loader processing routine executes a SUM calculation routine upon detecting the end record, the controller should be placed in a SUM waiting state after sending the end record to the device. 10. The n’th – 3 byte and the n’th – 2 byte are the SUM value that is sent to the controller in order of upper byte and lower byte. For details on how to calculate the SUM, refer to “Notes on SUM” in the latter page of this manual. The SUM calculation is performed only when no write error, receive error, or extended Intel Hex format error has been encountered after detecting the end record. Soon after calculation of SUM, the device sends the SUM data to the controller. The controller should determine whether writing to the RAM has terminated normally depending on whether the SUM value is received after sending the end record to the device. 11. After sending the SUM, the device goes to a state waiting for the user program start code. If the SUM value is correct, the controller should send the user program start command to the n’th – 1 byte. The user program start command is C0H. 12. The n’th byte is used to echo back the user program start code to the controller. After sending the echo back to the controller, the stack pointer is set to 105FH and the boot program jumps to the first address that is received as data in extended Intel Hex format. 13. If the user program start code is wrong or a receive error occurs, the device goes to an idle state after returning three bytes of error code to the controller. 91C829-162 2006-03-15 TMP91C829 b. Error code The boot program sends the processing status to the controller using various code. The error code is listed in the table below. Table 3.13.7 Error Code Error Code 62H 64H A1H A3H Meaning of Error Code Baud rate modification error occurred. Operation command error occurred. Framing error in received data occurred. Overrun error in received data occurred. *1: When a receive error occurs when receiving the user program, the device does not send the error code to the controller. *2: After sending the error code, the device goes to an idle state. c. Notes on SUM 1. Calculation method SUM consists of byte + byte … + byte, the sum of which is returned in word as the result. Namely, data is read out in byte and sum of which is calculated, with the result returned in word. Example: If the data to be calculated consists of the four bytes A1H B2H C3H D4H shown to the left, SUM of the data is: A1H + B2H + C3H + D4H = 02EAH SUM (HIGH) = 02H SUM (LOW) = EAH 2. Calculation data The data from which SUM is calculated is the RAM data from the first address received to the last address received. The received RAM write data is not the only data to be calculated for SUM. Even when the received addresses are noncontiguous and there are some unwritten areas, data in the entire memory area is calculated. The user program should not contain unwritten gaps. d. Notes on extended Intel Hex format (Binary) 1. After receiving the checksum of a record, the device waits for the start mark (3AH for “:”) of the next record. Therefore, the device ignores all data received between records during that time unless the data is 3AH. Make sure that once the controller program has finished sending the checksum of the end record, it does not send anything and waits for two byes of data to be received (Upper and lower bytes of SUM). This is because after receiving the checksum of the end record, the boot program calculates the SUM and returns the calculated SUM in two bytes to the controller. It becomes the cause of incorrect operation to write to areas out of device’s internal RAM. Therefore, when an extended record is transmitted, be sure to set a paragraph address to 0000H. Always make sure the first record type is an extended record. Because the initial value of the address pointer is 00H. 2. 3. 4. 91C829-163 2006-03-15 TMP91C829 5. Transmit a user program not by the ASCII code but by binary. However, start mark “:” is 3AH (ASCII code). Example: Transmit data in the case of writing in 16-byte data from address 1060H Data record 3A 10 1060 00 0607F100030000F201030000B1F16010 77 Data Record type Address Number of data “:” (Start mark) Checksum End record 3A 00 0000 01 FF Checksum Record type Address Number of data “:” (Start mark) e. Error when receiving user program If the following errors occur in extended Intel Hex format when receiving the user program, the device goes to an idle state. • • When the record type is not 00H, 01H, 02H When a checksum error occurs f. Error between frequency measurement and baud rate The boot program measures the resonator frequency when receiving matching data. If an error is under 3%, the boot program decides on that frequency. Since there is an overlap between the margin of 3% for 32.000 MHz and 33.868 MHz, the boundary is set at the intermediate value between the two. The baud rate is set based on the measured frequency. Each baud rate includes a set error shown in Table 3.13.8. For example, in the case of 20.000 MHz and 9600 bps, the baud rate is actually set at 9615.38 bps with an error of 0.2%. To establish communication, the sum of the baud rate set error shown in Table 3.13.8 and the frequency error need to be under 3%. Table 3.13.8 Set Error of Each Baud Rate (%) 9600 bps 16.000 MHz 20.000 MHz 22.579 MHz 25.000 MHz 32.000 MHz 33.868 MHz 36.000 MHz 0.2 0.2 0 −0.2 19200 bps 0.2 0.2 0.7 0.5 0.2 0.2 0.2 38400 bps 0.2 0.2 0 −0.1 57600 bps −0.6 −0.2 115200 bps −0.8 0.9 0 0.5 0.6 0.7 0.2 0 0.5 0 0 0.2 0.1 0.2 0.2 0.2 0.2 −0.7 91C829-164 2006-03-15 TMP91C829 (7) Ports setup of the boot program Only ports shown in Table 3.13.9 are setup in the boot program. At the time of boot program use, be careful of the influence on a user system. Do not use CS0 space and P60 in the system which uses the boot program. Other ports are not setting up, and are the reset state or the state of boot program starting. Table 3.13.9 Ports Setting List Ports P60 P61 P62 P63 P80 P81 P82 P83 P84 P85 P86 P87 Function CS0 Input/output Output Output Output Output Input Input Input Input Input Input Input Input High/low − − Notes CS0 space is 20000H to 201FFH. Port Port Port Port RXD0 Port Port Port Port Port Port High − High High − Not open-drain port. This port becomes TXD0 after matching data reception. Low − − − − This port is set as the output and becomes RTS0 after matching data reception. −: Un-setting up (8) Setting method of microcontroller peripherals Although P83 has the RTS0 function, it is initially in a high-impedance state and not set as RTS0 . To establish serial communication, attach a pull-down resistor to P83. 91C829-165 2006-03-15 TMP91C829 4. 4.1 Electrical Characteristics Maximum Ratings Parameter Power supply voltage (5 V) Power supply voltage (3 V) Input voltage Output current (Per pin) Output current (Per pin) Output current (Total) Output current (Total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature Symbol HVcc LVcc VIN IOL IOH ΣIOL ΣIOH PD TSOLDER TSTG TOPR Rating −0.5 to 5.75 −0.5 to 4.0 −0.5 to Vcc + 0.5 2 −2 80 −80 600 260 −65 to 150 −20 to 70 Unit V mA mW °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. Solderability of lead free products Test parameter Solderability (1) Use of Sn-37Pb solder Bath Solder bath temperature =230°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature =245°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (use of lead free) Pass: solderability rate until forming ≥ 95% Test condition Note 91C829-166 2006-03-15 TMP91C829 4.2 DC Characteristics (1/2) Parameter Symbol HVCC LVCC HVIL VIL1 −0.3 Condition fc = 10 to 36 MHz fc = 10 to 36 MHz Min 4.75 3.0 Typ. (Note) Max 5.25 3.6 0.8 0.3 HVcc Unit V V Power supply voltage (5 V) (AVcc = HVcc) (AVss = DVss = 0 V) Power supply voltage (3 V) D0 to D7, P10 to P17 (D8 to D15) Input low voltage Other ports RESET , NMI P56 (INT0), P70 (INT1) P72 (INT2), P73 (INT3) P75 (INT4), P90 (INT5) AM0, AM1 X1 D0 to D7, P10 to P17 (D8 to D15) VIL2 0.25 HVcc VIL3 VIL4 VIH VIH1 2.2 0.7 HVcc 0.3 0.2 LVcc V Input low voltage Other ports RESET , NMI HVcc + 0.3 VIH2 0.75 HVcc P56 (INT0), P70 (INT1) P72 (INT2), P73 (INT3) P75 (INT4), P90 (INT5) AM0, AM1 X1 VIH3 VIH4 VOL VOH ILI ILO VSTOP RRST CIO VTH RKH 0.4 40 2.0 40 IOL = 1.6 mA IOH = −400 μA HVcc − 0.3 0.8 LVcc 4.2 0.02 0.05 ±5 ±10 LVcc + 0.3 0.45 0.0 ≤ VIN ≤ HVcc 0.2 ≤ VIN ≤ HVcc − 0.2 VIL2 = 0.2 HVcc, V IH2 = 0.8 HVcc HVcc = 5 V ± 5% fc = 1 MHz V kΩ pF V kΩ mA V μA Output low voltage Output high voltage Input leakage current Output leakage current Power down voltage (at STOP, RAM back up) RESET pull-up resistor Pin capacitance Schmitt width RESET , NMI , INT0 to INT5 Programmable pull-up resistor NORMAL (Note 2) 3.6 200 10 1.0 200 HVcc = 5 V ± 5% HVcc = 5 V ± 5% LVcc = 3.0 to 3.6 V fc = 36 MHz Icc IDLE2 IDLE1 STOP 40 20 14 100 HVcc = 5 V ± 5% LVcc = 3.0 to 3.6 V Ta ≤ 70°C μA Note 1: Typical values are for when Ta = 25°C, HVcc = 5.0 V and LVcc = 3.3 V unless otherwise noted. Note 2: Icc measurement conditions (NORMAL): All functions are operational; output pins are open and input pins are fixed. 91C829-167 2006-03-15 TMP91C829 4.3 AC Characteristics (1) HVcc = 5.0 V ± 5%, LVcc = 3.0 to 3.6 V No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Parameter fFPH period ( = x ) A0 to A23 valid → RD / WR fall RD rise → A0 to A23 hold WR rise → A0 to A23 hold Symbol tFPH tAC tCAR tCAW tAD tRD tRR tHR tWW tDW (1+N) waits (1+N) waits Variable Min 27.6 x − 26 0.5x −13.8 x − 13 3.5x − 40 2.5x − 34 2.5x − 25 0 2.0x − 25 1.5x − 35 x − 25 3.5x − 60 2.5x + 0 3.5x − 76 3.5x 3.5x + 60 fFPH = 36 MHz Min 27.6 1.6 0.0 14.6 56.6 35.0 44.0 0 30.2 6.4 2.6 36.6 69.0 20.6 96.6 156.6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 100 Max A0 to A23 valid → D0 to D15 input RD fall → D0 to D15 input RD low width RD rise → D0 to D15 hold WR low width D0 to D15 valid → WR rise WR rise → D0 to D15 hold RD / WR fall → WAIT hold tWD tAW tCW tAPH tAPH2 tAPO A0 to A23 valid → WAIT input A0 to A23 valid → Port input A0 to A23 valid → Port hold A0 to A23 valid → Port valid AC measuring conditions Output level: High = 2.2 V, Low = 0.8 Vcc, CL = 50 pF Input level: High = 2.4 V, Low = 0.45 V (D0 to D15) High 0.8 Vcc, Low 0.2 Vcc (except D0 to D15) Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting. 91C829-168 2006-03-15 TMP91C829 (2) Read cycle tFPH fFPH A0 to A23 CSn tAW tCW WAIT tAP Port input (Note) tAPH2 tAD RD tCAR tRR tAC tRD D0 to D15 tHR D0 to D15 Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91C829-169 2006-03-15 TMP91C829 (3) Write cycle fFPH A0 to A23 CSn WAIT tAPO Port output (Note) tCAW WR , WAIT tWW tDW tWD D0 to D15 D0 to D15 Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91C829-170 2006-03-15 TMP91C829 4.4 AD Conversion Characteristics AVcc = HVcc, AVss = Vss Parameter Analog reference voltage (+) Analog reference voltage (−) Analog input voltage range Analog current for analog Reference voltage = 1 = 0 Error (Not including quantizing errors) − Symbol VREFH VREFL VAIN IREF (VREFL = 0V) Min HVCC − 0.2 V DVSS VREFL Typ. HVCC DVSS Max HVCC DVss + 0.2 V VREFH Unit V 0.85 0.02 ± 1.0 1.20 5.0 ± 4.0 mA μA LSB Note 1: 1 LSB = (VREFH − VREFL)/1024 [V] Note 2: The value for Icc includes the current which flows through the AVcc pin. 91C829-171 2006-03-15 TMP91C829 4.5 Serial Channel Timing (I/O internal mode) Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting. (1) SCLK input mode Parameter Symbol Min tSCY tOSS tOHS tHSR tSRD tRDS 0 16X tSCY/2 − 4X − 85 tSCY/2 + 2X + 0 3X + 10 tSCY − 0 0 Variable Max 36 MHz (Note) Unit Min Max 0.44 25 276 92 440 μs SCLK period Output data → SCLK rising/falling edge* SCLK rising/falling edge* → Output data hold SCLK rising/falling edge* → Input data hold SCLK rising/falling edge* → Valid data input Valid data input → SCLK rising/falling edge* ns ns ns ns ns *) SCLK rising/falling edge: The rising edge is used in SCLK rising mode. The falling edge is used in SCLK falling mode. Note: at tSCY = 16X (2) SCLK output mode Parameter SCLK period (Programable) Output data → SCLK rising/falling edge* SCLK rising/falling edge* → Output data hold SCLK rising/falling edge* → Input data hold SCLK rising/falling edge* → Valid data input Valid data input → SCLK rising/falling edge* Symbol Min tSCY tOSS tOHS tHSR tSRD tRDS 1X + 90 16X Variable Max 8192X 36 MHz (Note) Unit Min Max 0.44 180 180 0 μs tSCY/2 − 40 tSCY/2 − 40 0 tSCY/2 − 1X − 90 ns ns ns 324 ns ns 117 *) SCLK rising/falling edge: The rising edge is used in SCLK rising mode. The falling edge is used in SCLK falling mode. Note: at tSCY = 16X tSCY SCLK SCLK tOSS Output data TXD Input data RXD 0 tSRD 0 Valid tOHS 1 tRDS 1 Valid tHSR 2 Valid 3 Valid 2 3 91C829-172 2006-03-15 TMP91C829 4.6 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1) Parameter Clock perild Clock low level width Clock high level width Symbol tVCK tVCKL tVCKH Variable Min 8X + 100 4X + 40 4X + 40 36 MHz Max Min 320 150 150 Max Unit ns ns ns Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting . 4.7 Interrupts Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting. (1) NMI , INT0 to INT5 interrupts Parameter NMI , INT0 to INT5 low level width NMI , INT0 to INT5 high level width Symbol tINTAL tINTAH Variable Min 4X + 40 4X + 40 36 MHz Min 150 150 Max Max Unit ns ns 91C829-173 2006-03-15 TMP91C829 4.8 Bus Request/Bus Acknowledge BUSRQ (Note 1) BUSAK tCBAL tBAA D0 to D15 A0 to A23, RD , WR CS0 to CS3 , tABA (Note 2) (Note 2) HWR Parameter Output buffer to BUSAK low BUSAK high to output buffer on Symbol tABA tBAA Variable Min 0 0 fFPH = 36 MHz Min 0 0 Unit ns ns Max 80 80 Max 80 80 Note 1: Even if the BUSRQ signal goes low, the bus will not be released while the WAIT signal is low. The bus will only be released when BUSRQ goes low while WAIT is high. Note 2: This line shows only that the output buffer is in the off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal. 91C829-174 2006-03-15 TMP91C829 5. Table of SFRs The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) Chip select/wait control (5) Clock gear (6) 8-bit timer (7) 16-bit timer (8) UART/serial channel (9) AD converter (10) Watchdog timer (11) Multi vector controller Table layout Symbol Name Address 7 6 1 0 Bit symbol Read/Write Initial value after Reset Remarks Note: “Prohibit RMW” in the a table means that you cannot use RMW instructions on these register. Example: When setting bit0 only of the register PxCR, the instruction “SET 0, (PxCR)” cannot be used. The LD (Transfer) instruction must be used to write all eight bits. Read/Write R/W: Both read and write are possible. R: W: Only read is possible. Only write is possible. W*: Both read and write are possible (when this bit is read as 1). Prohibit RMW: Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD, and RRD instruction are read-modify-write instructions.) R/W*: Read-modify-write is prohibited when controlling the pull-up resistor. 91C829-175 2006-03-15 TMP91C829 Table 5.1 Address Map SFRs [1] PORT Address 0000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name P1 Address 0010H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name P5CR P5FC P6 P7 P6CR P6FC P7CR P7FC P8 P9 P8CR P8FC P9CR P9FC PA Address Name 0020H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH ODE P1CR P2 P2FC P5 Address Name 0070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH PZ EH PZCR FH PZFC [2] INTC Address 0080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name DMA0V DMA1V DMA2V DMA3V Address 0090H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name INTE0AD INTE12 INTE34 INTE5 INTETA01 INTETA23 INTETA45 INTETB0 INTETB0V INTES0 INTES1 Address 00A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name INTETC01 INTETC23 INTCLR DMAR DMAB IIMC0 IIMC1 MVEC0 MVEC1 Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). 91C829-176 2006-03-15 TMP91C829 [3] CS/WAIT Address 00C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name B0CS B1CS B2CS B3CS [4] CGEAR, DFM Address 00E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name SYSCR0 SYSCR1 SYSCR2 EMCCR0 EMCCR1 BEXCS MSAR0 MAMR0 MSAR1 MAMR1 MSAR2 MAMR2 MSAR3 MAMR3 [5] TMRA Address 0100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name TA01RUN TA0REG TA1REG TA01MOD TA1FFCR Address 0110H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name TA45RUN TA4REG TA5REG TA45MOD TA5FFCR TA23RUN TA2REG TA3REG TA23MOD TA3FFCR Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). 91C829-177 2006-03-15 TMP91C829 [6] TMRB Address 0180H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name TB0RUN TB0MOD TB0FFCR [7] UART/SIO Address 0200H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name SC0BUF SC0CR SC0MOD0 BR0CR BR0ADD SC0MOD1 TB0RG0L TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H TB0CP1L TB0CP1H SC1BUF SC1CR SC1MOD0 BR1CR BR1ADD SC1MOD1 [8] 10-Bit ADC Address 02A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name ADREG04L ADREG04H ADREG15L ADREG15H ADREG26L ADREG26H ADREG37L ADREG37H Address 02B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name ADMOD0 ADMOD1 Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). [9] WDT Address 0300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name WDMOD WDCR Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). 91C829-178 2006-03-15 TMP91C829 (1) I/O port Symbol Name Address 7 P17 P1 Port 1 01H P27 P2 Port 2 06H 1 1 P56 P5 Port 5 0DH 1 P55 R/W* Data from external port (Output latch register is set to 1.) 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) P26 P25 P24 R/W 1 P54 1 P53 1 1 1 P23 P22 P21 P20 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON P63 P6 Port 6 12H 1 P75 P7 Port 7 13H P87 P8 Port 8 18H P86 P85 P84 R/W Data from external port (Output latch register is set to 1.) 0(Output latch register): Pull-up resistor OFF 1(Output latch register): Pull-up resistor ON P96 P95 R/W P9 Port 9 19H Data from external port (Output latch register is set to 1.) P94 P93 P90 R/W Data from external port (Output latch register is set to 1.) P62 R/W 0 P72 R/W P61 1 P71 P60 1 P70 P74 P73 Data from external port (Output latch register is set to 1.) P83 P82 P81 P80 PA7 PA Port A 1EH PA6 PA5 PA4 R PA3 PA2 PA1 PA0 Data from external port PZ3 R/W PZ Port Z 7DH Data from external port (Output latch register is set to 1.) PZ2 91C829-179 2006-03-15 TMP91C829 (2) I/O port control (1/2) Symbol Name Port 1 control Address 04H (Prohibit RMW) 0/1 P27F 1 0/1 P26F 1 P56C P5CR Port 5 control 10H (Prohibit RMW) 0 P56F P5FC Port 5 function 11H (Prohibit RMW) W 0 0: Port 1: INT0 15H (Prohibit RMW) 0 0: Port 1: CS3 P75C 0 P72F2 W 0 0: Port 1: INT2 P87C P8CR Port 8 control 1AH (Prohibit RMW) 1BH (Prohibit RMW) P87F W 0 0: Port 1: STS1 P86F W 0 0: Port 1: SCLK1 0 0 0 0 0: Input P84F W 0 0: Port 1: TXD1 P86C P75F W 0 0: Port 1: INT4 P85C P74C 0 P74F W 0 P73C W 0 0 : Input 17H (Prohibit RMW) P73F W 0 0 1 : Output P72F1 W 0 P71F W 0 P70F W 0 0 0 0 0: Port 1: CS2 P72C 0 0: Port 1: BUSAK 0 0: Input 0/1 P25F 1 P55C W 0 1: Output P54F W 0 0: Port 1: BUSRQ P63F P6FC Port 6 function P62F W 0 0: Port 1: CS1 P71C 0 0: Port 1: CS0 P70C P61F P60F P53F 0 0/1 0: Input Port 2 function 09H (Prohibit RMW) P24F W 1 P54C 1 P53C 1 1 1 0: Port 1: Address bus (A23 to A16) 7 P17C P1CR 6 P16C 5 P15C 4 P14C W 0/1 1: Output P23F P22F P21F P20F 0/1 0/1 0/1 3 P13C 2 P12C 1 P11C 0 P10C P2FC P7CR Port 7 control 16H (Prohibit RMW) P7FC Port 7 function 0: Port 0: Port 1: TA5OUT 1: INT3 P84C W 0 1: Output P83F W 0 0: Port 1: STS0 P83C 0: Port 0: Port 0: Port 1: TA3OUT 1: TA1OUT 1: INT1 P82C 0 P82F W 0 0: Port 1: SCLK0 P81C 0 P80C 0 P80F W 0 0: Port 1: TXD0 P8FC Port 8 function 91C829-180 2006-03-15 TMP91C829 I/O port control (2/2) Symbol Name Address 1CH (Prohibit RMW) P96F W 0 0 0 0: Input P95F W 0 7 6 P96C P9CR Port 9 control 5 P95C W 0 1: Output 0 4 P94C 3 P93C 2 1 0 P90C W 0 0: Input 1: Output P90F W 0 0: Port 1: INT5 PZ3C W 0 0: Input 7FH (Prohibit RMW) 0 1: Output PZ2F PZFC Port Z function W 0 0: Port 1: HWR ODE84 W 0 1: P84ODE ODE80 W 0 1: P80ODE PZ2C P9FC Port 9 function 1DH (Prohibit RMW) 0: Port 0: Port 1: TB0OUT1 1: TB0OUT0 PZCR Port Z control 7EH (Prohibit RMW) ODE Serial open drain 2FH (Prohibit RMW) 91C829-181 2006-03-15 TMP91C829 (3) Interrupt control (1/3) Symbol Name Interrupt INTE0AD enable 0 & AD 90H Address 7 IADC R 0 1: INTAD Interrupt INTE12 enable 2/1 91H I2C R 0 1: INT2 Interrupt INTE34 enable 4/3 92H I4C R 0 1: INT4 Interrupt INTE5 enable 5 93H 6 INTAD IADM2 IADM1 IADM0 R/W 0 0 0 Interrpt request level INT2 I2M2 I2M1 I2M0 R/W 0 0 0 Interrupt request level INT4 I4M2 I4M1 I4M0 R/W 0 0 0 Interrupt request level I3C R 0 1: INT3 I5C R 0 1: INT5 Interrupt INTETA01 enable timer A 1/0 Interrupt INTETA23 enable timer A 3/2 Interrupt INTETA45 enable timer A 5/4 Interrupt INTETB0 enable timer B0 99H 97H 96H 95H INTTA1 (TMRA1) ITA1C R 0 1: INTTA1 ITA3C R 0 1: INTTA3 ITA5C R 0 1: INTTA5 ITB01C R 0 1: INTTB01 Interrupt INTETB0V enable timer B0 (overflow) 9BH ITA1M2 ITA1M1 ITA1M0 R/W 0 0 0 Interrpt request level INTTA3 (TMRA3) ITA3M2 ITA3M1 ITA3M0 R/W 0 0 0 Interrpt request level INTTA5 (TMRA5) ITA5M2 ITA5M1 ITA5M0 R/W 0 0 0 Interrpt request level INTTB01 (TMRB0) ITB01M2 ITB01M1 ITB01M0 R/W 0 0 0 Interrpt request level ITB00C R 0 1: INTTB00 ITF0C R 0 1: INTTBOF0 5 4 3 I0C R 0 1: INT0 I1C R 0 1: INT1 2 INT0 I0M2 1 I0M1 0 I0M0 R/W 0 0 0 Interrpt request level INT1 I1M2 I1M1 I1M0 R/W 0 0 0 Interrpt request level INT3 I3M2 I3M1 I3M0 R/W 0 0 0 Interrpt request level INT5 I5M2 I5M1 I5M0 R/W 0 0 0 Interrpt request level INTTA0 (TMRA0) ITA0M2 ITA0M1 ITA0M0 ITA0C R 0 1: INTTA0 ITA2C R 0 1: INTTA2 ITA4C R 0 1: INTTA4 R/W 0 0 0 Interrpt request level INTTA2 (TMRA2) ITA2M2 ITA2M1 ITA2M0 R/W 0 0 0 Interrpt request level INTTA4 (TMRA4) ITA4M2 ITA4M1 ITA4M0 R/W 0 0 0 Interrpt request level INTTB00 (TMRB0) ITB00M2 ITB00M1 ITB00M0 R/W 0 0 0 Interrpt request level ITF0M2 ITF0M1 ITF0M0 INTTBOF0 (TMRB0 overflow) R/W 0 0 0 Interrpt request level 91C829-182 2006-03-15 TMP91C829 Interrupt control (2/3) Symbol Name Interrupt INTES0 enable serial 0 9CH Address 7 ITX0C R 0 1: INTTX0 Interrupt INTES1 enable serial 1 9DH ITX1C R 0 1: INTTX1 Interrupt INTETC01 enable TC0/1 A0H ITC1C R 0 Interrupt INTETC23 enable TC2/3 A1H ITC3C R 0 0 0 INTTC3 ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 0 0 INTTC1 ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 0 ITC2M0 ITC2M2 ITC2M1 R/W 0 0 ITC2M0 0 INTTX1 ITX1M2 ITX1M1 R/W 0 Interrpt request level 0 ITX1M0 IRX1C R 0 1: INTRX1 0 INTTC0 ITC0M2 ITC0M1 R/W 0 0 ITC0M0 6 INTTX0 ITX0M2 ITX0M1 R/W 0 Interrpt request level 0 ITX0M0 IRX0C R 0 1: INTRX0 0 INTRX1 IRX1M2 IRX1M1 R/W 0 Interrpt request level 0 IRX1M0 5 4 3 2 INTRX0 IRX0M2 IRX0M1 R/W 0 Interrpt request level 0 IRX0M0 1 0 91C829-183 2006-03-15 TMP91C829 Interrupt control (3/3) Symbol Name DMA 0 DMA0V request vector 80H Address 7 6 5 DMA0V5 0 DMA1V5 81H 0 DMA2V5 82H 0 DMA3V5 83H 0 CLRV5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 CLRV4 0 3 DMA0V3 R/W 0 DMA1V3 R/W 0 DMA2V3 R/W 0 DMA3V3 R/W 0 CLRV3 W 0 DMAR3 89H R/W 0 DMAB3 8AH R/W 0 − W Interrupt IIMC0 input mode control 0 (Prohibit RMW) 8CH 0 Always write “0”. I2EDGE W 0 INT2 edge 0: Rising 1: Falling INT2 0: Edge 1: Level I2LE W 0 I1EDGE W 0 INT1 edge 0: Rising 1: Falling INT1 0: Edge 1: Level I1LE W 0 0 DMAR2 R/W 0 DMAB2 R/W 0 I0EDGE W 0 INT0 edge 0: Rising 1: Falling INT0 0: Edge 1: Level 0 DMAR1 R/W 0 DMAB1 R/W 0 I0LE W 0 0 DMAR0 R/W 0 DMAB0 R/W 0 NMIREE W 0 1: NMI operation even on NMI rising edge I5EDGE Interrupt IIMC1 input mode control 1 (Prohibit RMW) INT5 edge 0: Rising 1: Falling 8DH W 0 INT5 0: Edge 1: Level I5LE W 0 INT4 edge 0: Rising 1: Falling I4EDGE W 0 INT4 0: Edge 1: Level I4LE W 0 INT3 edge 0: Rising 1: Falling I3EDGE W 0 INT3 0: Edge 1: Level I3LE W 0 Clear interrupt request DMA flag by writing to DMA start vector. DMA DMAR software request register DMA DMAB burst request register 0 CLRV2 0 CLRV1 0 CLRV0 DMA3 start vector Interrupt INTCLR clear control 88H (Prohibit RMW) 0 DMA3V2 0 DMA3V1 0 DMA3V0 DMA2 start vector DMA 3 DMA3V request vector 0 DMA2V2 0 DMA2V1 0 DMA2V0 DMA1 start vector DMA 2 DMA2V request vector 0 DMA1V2 0 DMA1V1 0 DMA1V0 DMA0 start vector DMA 1 DMA1V request vector 2 DMA0V2 1 DMA0V1 0 DMA0V0 1: DMA request in software 1 : DMA request on burst mode 91C829-184 2006-03-15 TMP91C829 (4) Chip select/wait control (1/2) Symbol Name Block 0 CS/WAIT control register Address 7 6 5 4 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B2BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits BEXBUS W 0 Data bus width 0: 16 bits 1: 8 bits S23 C8H 1 V20 C9H 1 S23 CAH 1 V21 CBH 1 S22 1 V19 1 S22 1 V20 1 S21 1 V18 1 CS0 Area size S21 1 V19 1 CS1area size S20 R/W 1 1 Start address A23 to A16 V17 R/W 1 1 1 0: Enable to address comparision S20 R/W 1 1 Stat address A23 to A16 V18 R/W 1 1 1 0: Enable to address comparsion 1 V17 1 V16 1 V15~9 1 V8 S19 S18 1 S17 1 S16 V16 1 V15 1 V14~9 1 V8 S19 2 1 0 B0E W C0H 0 0: Disable (Prohibit RMW) 1: Enable B0OM1 B0OM0 W W 0 0 00: ROM/SRAM 01: 10: Reserved 11: B1OM1 B1OM0 W W 0 0 00: ROM/SRAM 01: 10: Reserved 11: B2M W 0 0: 16 M space 1: Area setting B2OM1 B2OM0 W W 0 0 00: ROM/SRAM 01: 10: Reserved 11: B3OM1 B3OM0 W W 0 0 00: ROM/SRAM 01: 10: Reserved 11: B0W2 B0W1 B0W0 W W W 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B1W2 B1W1 B1W0 W W W 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B2W2 B2W1 B2W0 W W W 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits B3W2 B3W1 B3W0 W W W 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits BEXW2 BEXW1 BEXW0 W W W 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 1xx: Reserved 011: 0 waits S18 S17 S16 B0CS B1CS Block 1 CS/WAIT control register B1E W C1H 0 (Prohibit 0: Disable RMW) 1: Enable B2CS Block 2 CS/WAIT control register B2E W C2H 1 0: Disable (Prohibit RMW) 1: Enable B3CS Block 3 CS/WAIT control register B3E W C3H 0 0: Disable (Prohibit RMW) 1: Enable BEXCS External CS/WAIT control register C7H (Prohibit RMW) MSAR0 Memory start address register 0 Memory address MAMR0 mask register 0 Memory start address register 1 MSAR1 Memory address MAMR1 mask register 1 91C829-185 2006-03-15 TMP91C829 Chip select/wait control (2/2) Symbol Name Memory start address register 2 Address 7 S23 CCH 1 V22 CDH 1 S23 CEH 1 V22 CFH 1 6 S22 1 V21 1 S22 1 V21 1 5 S21 1 V20 1 CS2 area size S21 1 V20 1 CS3 area size 4 S20 3 S19 2 S18 1 V17 1 S17 1 V16 1 S17 1 V16 1 0 S16 1 V15 1 S16 1 V15 1 MSAR2 R/W 1 1 Start address A23 to A16 V19 R/W V18 Memory address MAMR2 mask register 2 Memory start address register 3 1 1 1 0: Enable address comparsion S20 R/W S19 S18 1 V17 MSAR3 1 1 Start address A23 to A16 V19 R/W V18 Memory address MAMR3 mask register 3 1 1 1 0: Enable to address comparsion 91C829-186 2006-03-15 TMP91C829 (5) Clock gear Symbol Name Address 7 − 1 Always System clock SYSCR0 control register 0 write “1”. E0H 6 − 0 Always write “0”. 5 − 1 Always write “1”. 4 − R/W 0 Always write “0”. 0 Always write “0”. 0 Warm-up timer 0 Write: Don’t care Write: Start timer Read: End warm-up Read: Not end warm-up GEAR2 R/W 0 Always System clock SYSCR1 control register 1 write “0”. E1H 1 0 0 High-frequency gear value selection (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) HALTM0 R/W 1 DRVE R/W 0 1: Drive the pin in STOP mode − R/W 1 Always − R/W 1 Always write “1”. 0 00: fFPH 01: Reserved 10: fc/16 11: Reserved 0 Prscaler clock seleciton 3 − 2 WUEF 1 PRCK1 0 PRCK0 − GEAR1 GEAR0 System clock SYSCR2 control register 2 − R/W 0 E2H Always write “0”. WUPTM1 R/W 1 WUPTM0 R/W 0 HALTM1 R/W 1 00: Reserved Warming-up time 00: Reserved 01: 2 /input frequency 10: 2 /input frequency 11: 2 /input frequency 16 14 8 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode − R/W 0 Always wirte “0”. EXTIN R/W 0 1: fc is clock. EMC EMCCR0 control register 0 PROTECT R 0 E3H Protection flag 0: OFF 1: ON − R/W 0 Always write “0”. − R/W 1 Always write “1”. − R/W 0 Always write “0”. external write “1”. EMC EMCCR1 control register 1 E4H Protection is turned off by writing 1FH. Protection is turned on by writing any value other than 1FH. Note: EMCCR1 If protection is on, write operations to the following SFRs are not possible. 1. CS/WAIT control B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, and MAMR3 2. Clock gear (Only EMCCR1 can be written to) SYSCR0, SYSCR1, SYSCR2 and EMCCR0 91C829-187 2006-03-15 TMP91C829 (6) 8-bit timer (1/2) (6−1) TMRA01 Symbol Name Address 7 TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 2 1 0 I2TA01 TA01PRUN TA1RUN TA0RUN R/W R/W R/W R/W 0 0 0 0 IDLE2 8-bit timer run/stop control 0: Stop 0: Stop and clear 1: Operate 1: Run (Count up) − W Undefined − W Undefined TA01M1 8-bit timer TA01MOD source CLK & MODE 104H 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 TA01M0 PWM00 TA1CLK1 TA1CLK0 R/W 0 0 0 0 00: Reserved 00: TA0TRG 6 01: 2 PWM cycle 01: φT1 7 10: φT16 10: 2 8 11: φT256 11: 2 TA1FFC1 TA1FFC0 R/W 1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care PWM01 TA0CLK1 TA0CLK0 0 8-bit TA01RUN timer RUN 100H 8-bit TA0REG timer register 0 8-bit TA1REG timer register 1 102H (Prohibit RMW) 103H (Prohibit RMW) 0 00: TA0IN pin 01: φT1 10: φT4 11: φT16 TA1FFIE 8-bit TA1FFCR timer flip-flop control 105H (Prohibit RMW) TA1FFIS R/W 0 0 1: TA1FF 0: TMRA0 invert 1: TMRA1 enable inversion (6−2) TMRA23 Symbol Name Address 7 TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 2 1 0 I2TA23 TA23PRUN TA3RUN TA2RUN R/W R/W R/W R/W 0 0 0 0 IDLE2 8-bit timer run/stop control 0: Stop 0: Stop and clear 1: Operate 1: Run (Count up) − W Undefined − W Undefined TA23M1 8-bit timer TA23MOD source CLK & MODE TA23M0 0 PWM21 PWM20 TA3CLK1 TA3CLK0 R/W 0 0 00: TA2TRG 01: φT1 10: φT16 11: φT256 TA3FFC1 TA3FFC0 R/W 1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care TA2CLK1 TA2CLK0 0 8-bit TA23RUN timer RUN 108H 8-bit TA2REG timer register 0 8-bit TA3REG timer register 1 10AH (Prohibit RMW) 10BH (Prohibit RMW) 10CH 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 00: Reserved 6 01: 2 PWM cycle 7 10: 2 8 11: 2 0 00: Reserved 01: φT1 10: φT4 11: φT16 TA3FFIE 8-bit timer TA3FFCR flip-flop control 10DH (Prohibit RMW) TA3FFIS R/W 0 0 1: TA3FF 0: TMRA2 invert 1: TMRA3 enable inversion 91C829-188 2006-03-15 TMP91C829 8-bit timer (2/2) (6-3) TMRA45 Symbol Name Address 7 TA4RDE R/W 8-bit TA45RUN timer RUN 110H 0 Double buffer 0: Disable 1: Enable 8-bit TA4REG timer register 0 8-bit TA5REG timer register 1 112H (Prohibit RMW) 113H (Prohibit RMW) TA45M1 8-bit timer TA45MOD source CLK & MODE 114H 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 00: Reserved 01: 2 PWM cycle 10: 2 7 8 6 6 5 4 3 I2TA45 R/W 0 IDLE2 0: Stop 2 TA45PRUN R/W 0 0: Stop and clear 1 TA5RUN R/W 0 0 TA4RUN R/W 0 8-bit timer run/stop control 1: Operate 1: Run (Count up) − W Undefined − W Undefined TA45M0 PWM41 PWM40 0 TA5CLK1 R/W 0 00: TA4TRG 01: φT1 10: φT16 11: φT256 TA5FFC1 TA5FFC0 1 R/W 1 00: Invert TA5FF 01: SET TA5FF 10: Clear TA5FF 11: Don’t care 0 1: TA5FF invert enable 0 0 00: TA4IN pin 01: φT1 10: φT4 11: φT16 TA5FFIE TA5FFIS 0 0: Timer4 1: Timer5 inversion R/W 0 TA5CLK0 TA4CLK1 TA4CLK0 11: 2 8-bit TA5FFCR timer flip-flop control 115H (Prohibit RMW) 91C829-189 2006-03-15 TMP91C829 (7) 16-bit timer (1/2) (7-1) TMRB0 Symbol Name Address 7 6 TB0RDE − R/W R/W 0 0 Always Double write “0”. buffer 0: Disable 1: Enable TB0CT1 TB0ET1 R/W 0 0 TB0FF1 INV TRG 0: TRG disable 1: TRG enable 5 4 3 2 1 0 I2TB0 TB0PRUN TB0RUN R/W R/W R/W 0 0 0 16-bit timer run/stop control IDLE2 0: Stop and clear 0: Stop 1: Run (Count up) 1: Operate TB0CPM0 0 TB0CLE R/W 0 1: UC0 clear enable TB0CLK1 0 Source clock 00: TB0IN0 pin 01: φT1 10: φT4 11: φT16 TB0CLK0 0 8-bit TB0RUN timer control 180H 16-Bit timer TB0MOD source CLK & MODE 182H TB0CP0I W* 1 TB0CPM1 0 (Prohibit RMW) Invert when 0: Soft Capture timing capture (TB0IN0, TB0IN1) 1: Undefined 00: Disable Invert when the UC value the UC value is captured to matches the value in TB0CP1. TB0RG1. 01: ↑, ↑ 10: ↑, ↓ 11: ↑, ↓ (TA1OUT) 16-bit TB0FFCR timer flip-flop control TB0FF1C1 TB0FF1C0 TB0C1T1 W* 1 1 0 00: Invert TB0FF1 183H 01: Set 10: Clear (Prohibit 11: Don’t care Invert when RMW) Always read as “11”. is loaded TB0C0T1 TB0E1T1 R/W 0 0 TB0FF0 invert trigger 0: Trigger disable 1: Trigger enable Invert when is loaded Invert when matches the TB0RG1. TB0E0T1 0 Invert when matches the value in TB0RG0. TB0FF0C1 TB0FF0C0 W* 0 0 00: Invert TB0FF0 01: Set 10: Clear 11: Don’t care Always read as “11”. the UC value the UC value the UC value the UC value into TB0CP1. into TB0CP0. value in 188H 16-bit timer TB0RG0L (Prohibit register 0L RMW) TB0RG0H 189H (Prohibit register 0H RMW) 16-bit timer 18AH (Prohibit register 1L RMW) 16-bit timer 18BH (Prohibit register 1H RMW) 16-bit timer Capture register 0L TB0CP0H Capture register 0H TB0CP1L Capture register 1L TB0CP1H Capture register 1H 18FH 18EH 18DH 18CH TB0RG1L TB0RG1H TB0CP0L − W Undefined − W Undefined − W Undefined − W Undefined − R Undefined − R Undefined − R Undefined − R Undefined 91C829-190 2006-03-15 TMP91C829 (8) UART/serial channel (8-1) UART/SIO Channel 0 Symbol SC0BUF Name Serial channel 0 buffer Address 200H (Prohibit RMW) RB8 Serial SC0CR channel 0 control 201H R Undefined 0 Receiving Parity 0: Odd data bit8 1: Even TB8 Serial SC0MOD0 channel 0 mode 0 202H 0 data bit8 7 RB7/TB7 6 RB6/TB6 5 RB5/TB5 4 RB4/TB4 3 RB3/TB3 2 RB2/TB2 1 RB1/TB1 0 RB0/TB0 R (Receiving)/W (Transmission) Undefined EVEN R/W 0 1: Parity enable RXE 0 enable Overrun WU R/W 0 enable 0 enable 0 00: I/O interface 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits − 0 BR0ADD 0 1: (16 − K)/16 00: φT0 divided enable PE OERR 0 PERR 0 1: Error Parity SM1 FERR 0 Framing SM0 0 SCLKS R/W 0 IOC 0 R (Cleared to 0 by reading.) 0:SCLK0↑ 1: Input 1:SCLK0↓ SCLK0 pin SC1 0 00: TA0TRG 01: Baud rate generator 10: Internal clock fSYS 11: External clock SCLK0 BR0S1 0 0 to F BR0S0 0 SC0 0 CTSE Transmission 1: CTS 1: Receive 1: Wakeup BR0CK1 0 01: φT2 10: φT8 11: φT32 BR0CK0 R/W BR0S3 0 BR0S2 0 BR0CR Baud rate control 203H Always write “0”. Set the frequency divisor N. Serial BR0ADD channel 0 K setting register I2S0 R/W Serial SC0MOD1 channel 0 mode 1 205H 0 IDLE2 0: Stop 1: Operate FDPX0 R/W 0 I/O interface 0: Half duplex 1: Full duplex 204H BR0K3 0 BR0K2 R/W 0 BR0K1 0 BR0K0 0 Baud rate 0 K. 1 to F STSEN0 W 1 STS0 1: Output 0: Stop 91C829-191 2006-03-15 TMP91C829 (8-2) UART/SIO channel 1 Symbol SC1BUF Name Serial channel 1 buffer Address 208H (Prohibit RMW) RB8 Serial SC1CR channel 1 control 209H R Undefined 0 Receiving Parity 0: Odd data bit8 1: Even TB8 Serial SC1MOD0 channel 1 mode 0 20AH 0 data bit8 7 RB7/TB7 6 RB6/TB6 5 RB5/TB5 4 RB4/TB4 3 RB3/TB3 2 RB2/TB2 1 RB1/TB1 0 RB0/TB0 R (Receiving)/W (Transmission) Undefined EVEN R/W 0 1: Parity enable RXE 0 enable Overrun WU R/W 0 enable 0 enable 0 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits − 0 BR1ADD 0 1: (16 − K)/16 00: φT0 divided enable PE OERR 0 PERR 0 1: Error Parity SM1 FERR 0 Framing SM0 0 SCLKS R/W 0 IOC 0 R (cleared to 0 by reading.) 0:SCLK1↑ 1: Input 1:SCLK1↓ SCLK1 pin SC1 0 00: TA0TRG 01: Baud rate generator 10: Internal clock fSYS 11: External clock SCLK1 BR1S1 0 0 to F BR1S0 0 SC0 0 CTSE Transmission 1: CTS 1: Receive 1: Wakeup 00: I/O interface BR1CK1 0 01: φT2 10: φT8 11: φT32 BR1CK0 R/W BR1S3 0 BR1S2 0 BR1CR Baud rate control 20BH Always write “0”. Set the frequency divisor N. Serial BR1ADD channel 1 K setting register I2S1 R/W Serial SC1MOD1 channel 1 mode 1 20DH 0 IDLE2 0: Stop 1: Operate FDPX1 R/W 0 I/O interface 1: Full duplex 0: Half duplex 20CH BR1K3 0 BR1K2 R/W 0 BR1K1 0 BR1K0 0 Baud rate 0 K. 1 to F STSEN1 W 1 STS1 1: Output 0: Stop 91C829-192 2006-03-15 TMP91C829 (9) AD converter Symbol Name Address 7 EOCF AD ADMOD0 MODE register 0 2B0H R 0 1: End 0 1: Busy 6 ADBF 5 − R/W 0 Always write “0”. VREFON R/W 0 AD ADMOD1 MODE register 1 2B1H I2AD R/W 0 0: Abort 1: Operate 4 − R/W 0 Always write “0”. 3 ITM0 R/W 0 repeat mode. ADTRGE R/W 0 1: Enable for external start 0 000: AN0 AN0 001: AN1 AN0 → AN1 010: AN2 AN0 → AN1 → AN2 011: AN3 AN0 → AN1 → AN2 → AN3 100: AN4 AN4 101: AN5 AN4 → AN5 110: AN6 AN4 → AN5 → AN6 111: AN7 AN4 → AN5 → AN6 → AN7 2 REPEAT R/W 0 1 SCAN R/W 0 1: Scan 0 ADS R/W 0 1: Start Interrupt in 1: Repeat ADCH2 ADCH1 R/W 0 Input channel ADCH0 0 1: VREF on IDLE2 AD ADMOD2 MODE register 2 2B2H ADM27 0 ADM37 2B3H 1 ADR01 2A0H ADR09 2A1H ADR11 2A2H ADR19 2A3H ADR21 2A4H ADR29 2A5H ADR31 2A6H ADR39 2A7H R R R R ADM26 0 ADM36 1 ADR00 ADM25 0 ADM35 0 ADM24 R/W 1 ADM34 R/W 0 ADM23 0 ADM33 1 ADM22 0 ADM32 1 ADM21 0 ADM31 1 ADM20 1 ADM30 1 ADR0RF R 0 Please write “1E”. AD ADMOD3 MODE register 3 AD result ADREG04L register 0/4 low AD result ADREG04H register 0/4 high ADREG15L AD result register 1/5 low AD result ADREG15H register 1/5 high AD result ADREG26L register 2/6 low AD result ADREG26H register 2/6 high AD result ADREG37L register 3/7 low AD result ADREG37H register 3/7 high ADR30 ADR20 ADR10 Please write “CF”. Undefined ADR08 ADR07 ADR06 R Undefined ADR05 ADR04 ADR03 ADR02 ADR1RF R 0 ADR17 ADR16 R Undefined ADR2RF R 0 ADR27 ADR26 R Undefined ADR3RF R 0 ADR37 ADR36 R Undefined ADR35 ADR34 ADR33 ADR32 ADR25 ADR24 ADR23 ADR22 ADR15 ADR14 ADR13 ADR12 Undefined ADR18 Undefined ADR28 Undefined ADR38 91C829-193 2006-03-15 TMP91C829 (10) Watchdog timer Symbol Name Address 7 WDTE R/W WDT WDMOD MODE register 300H 1 1: WDT enable 6 WDTP1 R/W 0 00: 2 /fSYS 01: 2 /fSYS 10: 2 /fSYS 11: 2 /fSYS − W − B1H: WDT disable 4EH: WDT clear 21 19 17 15 5 WDTP0 R/W 0 4 3 2 I2WDT R/W 0 IDLE2 0: Abort 1 RESCR R/W 0 RESET connect WDT out to reset pin 0 − R/W 0 Always write “0”. 1: Operate internally WDCR WDT control 301H (Prohibit RMW) (11) Multi vector controllor Symbol Name Multi MVEC0 vector control 00AEH Address 7 VEC7 R/W 1 6 VEC6 R/W 1 5 VEC5 R/W 1 4 VEC4 R/W 1 3 VEC3 R/W 1 2 VEC2 R/W 1 1 VEC1 R/W 1 0 VEC0 R/W 1 Vector address A15 to A8 Symbol Name Multi Address 7 VEC15 R/W 1 6 VEC14 R/W 1 5 VEC13 R/W 1 4 VEC12 R/W 1 3 VEC11 R/W 1 2 VEC10 R/W 1 1 VEC9 R/W 1 0 VEC8 R/W 1 MVEC1 vector control 00AFH Vector address A23 to A16 Note: Write MVEC1, MVEC0 after making an interruption prohibition state. 91C829-194 2006-03-15 TMP91C829 6. Port Section Equivalent Circuit Diagrams • Reading the circuit diagrams The gate symbols used are essentially the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active (1) when the HALT mode setting register is set to STOP mode (e.g., when SYSCR2 = 0, 1) and the CPU executes the HALT instruction. When the drive enable bit SYSCR2 is set to 1, however, STOP will remains at 0. • The input protection resistances ranges from several tens of ohms to several hundreds of ohms. D0 to D7, P10 to P17, P20 to P27, A0 to A15, P71, P74, P90, P93 to P96 VCC Output data Output enable STOP Input data P-ch N-ch I/O Input enable RD , WR , P60 to P63 Vcc Output data Output STOP 91C829-195 2006-03-15 TMP91C829 P53 to P55, P80 to P87, PZ2, PZ3 Vcc Output data Output enable STOP Input data Vcc Programmable pull-up resistor I/O Input enable PA (AN0 to AN7) Analog input channel select Analog input Input Input data Input enable P56 (INT0), P70 (INT1), P72 (INT2), P73 (INT3), P75 (INT4), P90 (INT5) Vcc Output data Output enable STOP Input data Schmitt trigger I/O P80 (TXD0) Vcc Output data Open-drain output enable STOP Input data Input enable I/O NMI NMI Schmitt trigger Input 91C829-196 2006-03-15 TMP91C829 AM0 to AM1 Input data Input RESET Vcc P-ch Reset Schmitt trigger WDTOUT Reset enable Input X1 and X2 Oscillator x2 High-frequency Oscillation enable P-ch N-ch x1 Clock VREFH and VREFL VREFON P-ch VREFH String resistor VREFL 91C829-197 2006-03-15 TMP91C829 7. Points to Note and Restrictions (1) Notation a. b. The notation for built-in/I/O registers is as follows register symbol (e.g., TA01RUN denotes bit TA0RUN of register TA01RUN). Read-modify-write instructions An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. Example 1: SET Example 2: INC • Exchange instruction EX (mem), R 3, (TA01RUN) … Set bit 3 of TA01RUN. 1, (100H) … Increment the data at 100H. Examples of read-modify-write instructions on the TLCS-900 Arithmetic operations ADD (mem), R/# SUB (mem), R/# INC #3, (mem) Logic operations AND (mem), R/# XOR (mem), R/# ADC (mem), R/# SBC (mem), R/# DEC #3, (mem) OR (mem), R/# Bit manipulation operations STCF #3/A, (mem) SET #3, (mem) TSET #3, (mem) RES #3, (mem) CHG #3, (mem) Rotate and shift operations RLC (mem) RRC RL (mem) RR SLA (mem) SRA SLL (mem) SRL RLD (mem) RRD c. fc, fFPH, fSYS and one state (mem) (mem) (mem) (mem) (mem) The clock frequency input on pins X1 and 2 is called fOSCH. The clock selected by DFMCR0 is called fc. The clock selected by SYSCR1 is called fFPH. The clock frequency give by fFPH divided by 2 is called fSYS. One cycle of fSYS is referred to as one state. 91C829-198 2006-03-15 TMP91C829 (2) Points to note a. b. c. d. AM0 and AM1 pins Fix these pins to VCC unless changing voltage. EMU0 and EMU1 Open pins. Reserved address areas The TMP91C829 does not have any reserved areas. HALT mode (IDLE1) When IDLE1 mode is used (in which oscillator operation only occurs), set RTCCR to 0 stop the timer for the real time clock before the HALT instructions is executed. e. Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request and output of the system clock. f. Programmable pull-up resistance The programmable pull-up resistor can be turned on/off by a program when the ports are set for use as input ports. When the ports are set for use as output ports, they cannot be turned ON/OFF by a program. The data registers (e.g., P3) are used to turn the pull-up/pull-down resistors on/off. Consequently read-modify-write instructions are prohibited. g. Bus releasing function Please refer to the note about bus release in Section 3.6 “Port Functions”. The pin state is written when the bus is released. h. Watchdog timer The watchdog timer starts operation immediately after a reset is released. When the watchdog timer is not to be used, disable it. i. Watchdog timer When the bus is released, neither internal memory nor internal I/O can be accessed. However, the internal I/O continues to operate. Hence the watchdog timer continues to run. Therefore be careful about the bus releasing time and set the detection timer of watchdog timer. j. AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption. When STOP mode is used, disable the resistor using the program before the HALT instruction is executed. k. CPU (Micro DMA) Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control registers in the CPU. (e.g., the transfer source address register (DMASn).) l. Undefined SFR The value of an undefined bit in an SFR is undefined when read. m. POP SR instruction Please execute the POP SR instruction during DI condition. 91C829-199 2006-03-15 TMP91C829 n. Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts ( NMI , INT0 to INT4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. 91C829-200 2006-03-15 TMP91C829 8. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 91C829-201 2006-03-15 TMP91C829 91C829-202 2006-03-15