TMP91CW18A

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91CW18A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91CW18A CMOS 16-Bit Microcontroller TMP91CW18AF 1. Outline and Features TMP91CW18A is a high-speed 16-bit microcontroller designed for the control of various mid-to large-scale equipment. TMP91CW18AF comes in a 80-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) • • • • • Instruction mnemonics are upward-compatible with TLCS-90/900/900H 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions: Bit transfer and arithmetic instructions Micro DMA: 4 channels (640 ns /2 bytes at 25 MHz) (2) Minimum instruction execution time: 160 ns (at 25 MHz) (3) Built-in RAM: 4 Kbytes Built-in ROM: 128 Kbytes (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) 91CW18A-1 2005-08-15 TMP91CW18A (5) Wait controller: 1 channel (6) 8-bit timer: 8 channels (7) 16-bit timer: 1 channel (8) General-purpose serial interface (UART): 1 channel (9) Serial bus interface (I2C/Select of synchronous): 1 channel (10) Serial bus interface (I2C): 2 channels (11) 10-bit AD converter (S/H): 12 channels • Conversion time: 84 states (6.72 μs at fFPH = 25 MHz) (12) Watchdog timer (13) Interrupts function • • • • • 9 CPU interrupts: Software interrupt instruction and illegal instruction 21 internal interrupts: 8 external interrupts: Seven selectable priority levels (14) Input/Output ports: 62 pins I/O: 50 pins (Programmable open drain: 12 pins) Input: 12 pins (15) Standby mode Three HALT modes: Programmable IDLE2, IDLE1, STOP (16) Clock controller • • • Clock gear: changes high-frequency clock fc to fc/16 Vcc = 4.5 V to 5.5 V (fc max = 25 MHz) P-QFP80-1420-0.80B (17) Open voltage (18) Package 91CW18A-2 2005-08-15 TMP91CW18A 25 MHz (P61) CTS /INT1 (P62) SCOUT/INT2 (P60) INT0 NMI H-OSC Port 6 X1 X2 EMU0 EMU1 RESET Interrupt controller CPU (TLCS-900/L1) XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Port 1 F 8-bit timer (TMRA0) (P70) TA1OUT 8-bit timer (TMRA1) 8-bit timer (TMRA2) (P71) TA3OUT Port 7 8-bit timer (TMRA3) 8-bit timer (TMRA4) 8-bit timer (TMRA5) AM0 AM1 ALE AD0 (P00) AD1 (P01) AD2 (P02) AD3 (P03) AD4 (P04) AD5 (P05) AD6 (P06) AD7 (P07) AD8/A8 (P10) AD9/A9 (P11) AD10/A10 (P12) AD11/A11 (P13) AD12/A12 (P14) AD13/A13 (P15) AD14/A14 (P16) AD15/A15 (P17) A0/A16 (P20) A1/A17 (P21) A2/A18 (P22) A3/A19 (P23) A4/A20 (P24) A5/A21 (P25) A6/A22 (P26) A7/A23 (P27) RD (P30) WR (P31) HWR (P32) Watchdog timer (WDT) (P72)TA5OUT (P73) INT5/TB0IN0 (P74) INT6/TB0IN1 (P75) TB0OUT0 16-bit timer (TMRB0) 4-Kbyte RAM 3 (P76) SCK0/INT3 I C bus/SIO interface 0 2 Port 3 (P.O.D) (P80) SDA0/SO0 (P81) SCL0/SI0 (P82) TXD (P83) RXD (P84) SDA1 (P85) SCL1 (P86) SDA2 (P87) SCL2 P80 to P83 (P.O.D.), P84 to P87 (O.D.) Wait controller 8-bit timer (TMRA6) 8-bit timer (TMRA7) Port 2 Port 0 WAIT (P33) UART interface I C bus interface 1 I2C bus interface 2 2 (P34) TA6IN (P35) TA7OUT (P36) INT4 (P37) AN11 (P43) AN10 (P42) AN9 (P41) ADTRG /AN8 (P40) AN7 (P57) AN6 (P56) AN5 (P55) AN4 (P54) AN3 (P53) AN2 (P52) AN1 (P51) AN0 (P50) AVCC AVSS VREFL VREFH 128-Kbyte ROM DVCC DVCC DVSS 10-bit 12-channel AD converter Port 5 DVCC DVSS ( ): Initial function after reset Figure 1.1 TMP91CW18A Block Diagram Port 4 91CW18A-3 2005-08-15 TMP91CW18A 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91CW18A, their names and functions are as follows. 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91CW18AF. A10/AD10 (P12) A9/AD9 (P11) A8/AD8 (P10) AD7 (P07) AD6 (P06) AD5 (P05) AD4 (P04) AD3 (P03) AD2 (P02) AD1 (P01) AD0 (P00) ALE SCL2 (P87) SDA2 (P86) SCL1 (P85) SDA1 (P84) EMU1 EMU0 RESET (P13) A11/AD11 (P14) A12/AD12 (P15) A13/AD13 (P16) A14/AD14 (P17) A15/AD15 (P20) A0/A16 (P21) A1/A17 DVSS DVCC (P22) A2/A18 (P23) A3/A19 (P24) A4/A20 (P25) A5/A21 (P26) A6/A22 (P27) A7/A23 NMI 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AM1 DVCC X1 DVSS X2 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Top view 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 DVCC AM0 (P83) RXD (P82) TXD (P81) SCL0/SI0 (P80) SDA0/SO0 (P76) SCK0/INT3 (P75) TB0OUT0 (P74) TB0IN1/INT6 (P73) TB0IN0/INT5 (P72) TA5OUT (P71) TA3OUT (P70) TA1OUT AVCC AVSS VREFL Figure 2.1.1 Pin Assignment Diagram (80-pin QFP) (P30) RD (P31) WR (P32) HWR (P33) WAIT P34 (P35) TA6IN (P36) TA7OUT (P37) INT4 (P60) INT0 (P61) CTS/INT1 (P62) SCOUT/INT2 (P50) AN0 (P51) AN1 (P52) AN2 (P53) AN3 (P54) AN4 (P55) AN5 (P56) AN6 (P57) AN7 (P40) AN8/ADTRG (P41) AN9 (P42) AN10 (P43) AN11 VREFH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ( ) : Initial function for after reset 91CW18A-4 2005-08-15 TMP91CW18A 2.2 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/3) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O Tri-state I/O Tri-state Output Functions Port 0: I/O port that allows I/O to be selected at the bit level Address and data (Lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (Upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: I/O port By setting (P3 = 0 , P3FC = 1), RD signal is generated during reading internal areas. Read: Strobe signal for reading external memory Open-drain output pin by programmable 8 I/O Output Output 1 I/O Output P31 WR 1 I/O Output Port 31: I/O port Write: Strobe signal for writing data to pins AD0 to AD7 Open-drain output pin by programmable Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins AD8 to AD15 Open-drain output pin by programmable Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Open-drain output pin by programmable Port 34: I/O port Open-drain output pin by programmable Port 35: I/O port Timer A6 input Open-drain output pin by programmable Port 36: I/O port Timer A7 output Open-drain output pin by programmable Port 37: I/O port Interrupt request pin 4: Interrupt request pin with programmable rising edge/falling edge levels Open-drain output pin by programmable P32 HWR 1 I/O Output P33 WAIT 1 I/O Input P34 P35 TA6IN P36 TA7OUT P37 INT4 1 1 I/O I/O Input 1 I/O Output 1 I/O Input P40 to P43 AN8 to AN11 ADTRG 4 Input Input Input Port 40: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD conversion Port 5: Pin used to input port Analog input: Pin used to input to AD converter Port 60: I/O port Interrupt Request pin 0: Interrupt request pin with programmable rising edge/falling edge levels Port 61: I/O port Serial data send enable (Clear to send) Interrupt request pin 1: Interrupt request pin with programmable rising edge/falling edge levels Port 62: I/O port System clock output: Outputs fFPH or fs clock Interrupt request pin 2: Interrupt request pin with programmable rising edge/falling edge levels P50 to P57 AN0 to AN7 P60 INT0 P61 CTS 8 1 Input Input I/O Input 1 I/O Input Input INT1 P62 SCOUT INT2 1 I/O Output Input 91CW18A-5 2005-08-15 TMP91CW18A Table 2.2.2 Pin Names and Functions (2/3) Pin Name P70 TA1OUT P71 TA3OUT P72 TA5OUT P73 TB0IN0 INT5 P74 TB0IN1 INT6 P75 TB0OUT0 P76 SCK0 INT3 P80 SO0 SDA0 P81 SI0 SCL0 P82 TXD P83 RXD P84 SDA1 P85 SCL1 P86 SDA2 P87 SCL2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Number of Pins 1 I/O I/O Output I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O I/O Input I/O Output I/O I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Port 70: I/O port Timer A1 output Port 71: I/O port Timer A3 output Port 72: I/O port Timer A5 output Port 73: I/O port Timer B0 input 0 Functions Interrupt request pin 5: Interrupt request pin with programmable rising edge/falling edge levels Port 74: I/O port Timer B0 input 1 Interrupt request pin 6: Interrupt request pin with rising edge levels Port 75: I/O port Timer B0 output 0 Port 76: I/O port Serial clock I/O 0 Interrupt request pin 3: Interrupt request pin with programmable rising edge/falling edge levels Port 80: I/O port Serial bus interface send data at SIO mode 0. 2 Serial bus interface send/receive data at I C mode 0. Open-drain output pin by programmable Port 81: I/O port Serial bus interface receive data at SIO mode 0. 2 Serial bus interface clock I/O data at I C mode 0. Open-drain output pin by programmable Port 82: I/O port Serial send data (UART) Open-drain output pin by programmable Port 83: I/O port Serial receive data (UART) Open-drain output pin by programmable Port 84: I/O port 2 Serial bus interface send/receive data at I C mode 1 N-ch FET open-drain output Port 85: I/O port 2 Serial bus interface clock I/O data at I C mode 1 N-ch FET open-drain output Port 86: I/O port 2 Serial bus interface send/receive data at I C mode 2 N-ch FET open-drain output Port 87: I/O port 2 Serial bus interface clock I/O data at I C mode 2 N-ch FET open-drain output 91CW18A-6 2005-08-15 TMP91CW18A Table 2.2.3 Pin Names and Functions (3/3) Pin Name ALE NMI Number of Pins 1 1 2 1 1 1 1 1 1 2 3 2 I/O Output Input Input Output Input Input Input Address latch enable Functions Can be disabled to reduce noise. Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Address mode: The Vcc pin should be connected. Test pins: Open pins Reset: Initializes TMP91CW18A (with pull-up resistor). Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) I/O High-frequency oscillator connection pins Power supply pins (All Vcc pins should be connected with the power supply pin.) GND pins (All pins should be connected with GND (0V).) AM0 to AM1 EMU0, EMU1 RESET VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS 91CW18A-7 2005-08-15 TMP91CW18A 3. Operation This section describes the basic components, functions and operation of the TMP91CW18A. Notes and restrictions which apply to the various items described here are outlined in Section 7. Precautions and restrictions at the end of this databook. 3.1 CPU The TMP91CW18A incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a description of this CPU’s operation, please refer to the section of this databook which describes the TLCS-900/L1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP91CW18A. These functions are not covered in the section devoted to the TLCS-900/L1 CPU. 3.1.1 Reset When resetting the TMP91CW18A microcontroller, ensure that the power supply voltage is within the operating voltage range and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (13 μs at 25 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). When the reset is accept, the CPU: • Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC PC PC • • • • ← ← ← Data in location FFFF00H Data in location FFFF01H Data in location FFFF02H Sets the stack pointer (XSP) to 100H. Sets bits of the status register (SR) to 111 (thereby setting the interrupt level mask register to level 7). Sets the bit of the status register to 1 (MAX mode). Note: As this product does not support MIN mode, do not write a 0 to the bit. Clears bits of the status register to 000 (thereby selecting register bank 0). When the reset is cleared, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is cleared. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. • • • Initializes the internal I/O registers. Sets the port pins including the pins that also act as internal I/O, to general-purpose input or output port mode. Sets the ALE pin to High-Z. Note: By resetting, register in CPU except program counter (PC), status register (SR), and stack Pointer (XSP) and the data in internal RAM are not changed. Figure 3.1.1 shows the timing of a reset for the TMP91CW18A. 91CW18A-8 2005-08-15 fFPH Sampling Sampling RESET A16 to A23 (P20 to P27 input mode) ALE AD0 to AD15 (P00 to P07, P10 to P17 input mode) (P30 output mode) Address Address Read RD (Start read cycle of 0 waits after released reset) AD0 to AD15 (P00 to P07, P10 to P17 input mode) (P31 output mode) Address Data output Address Write Figure 3.1.1 TMP91CW18A Reset Timing Example 91CW18A-9 (P32 input mode) (Output mode) (Input mode) (Input mode) WR HWR P30 to P31 P32 to P33 P00 to P07, P10 to P17, P20 to P27, P34 to P37, P60 to P62, P70 to P76, P80 to P87 TMP91CW18A Pull up (Internal) High-Z 2005-08-15 TMP91CW18A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91CW18A. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 001000H Internal RAM (4 Kbytes) 002000H 64-Kbyte area (nn) 010000H External memory 16-Mbyte area FE0000H (R) (−R) (R+) 128-Kbyte Internal ROM (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map 91CW18A-10 2005-08-15 TMP91CW18A 3.3 Standby Function/Noise Reducing Circuit The TMP91CW18A contains (1) a clock gearing system, (2) a standby controller and (3) a noise reduction circuit. It is used for low-power and low-noise systems. This chapter is organized as follows. 3.3.1 Block Diagram of System Clock 3.3.2 SFR 3.3.3 System Clock Controller 3.3.4 Prescaler Clock Controller 3.3.5 Noise Reduction Circuits 3.3.6 Standby Controller 91CW18A-11 2005-08-15 TMP91CW18A 3.3.1 Block Diagram of System Clock The clock operating modes are as follows: Single clock mode (X1, X2 pins only) Figure 3.3.1 shows a transition figure. The clock frequency input from the X1 and X2 pins is called fc. The clock frequency selected by SYSCR1 is called the system clock fFPH. The system clock fSYS is defined as the divided clock of fFPH and one cycle of fSYS is regard to as one state. Reset (fOSCH/32) Release reset Instruction IDLE2 mode (I/O operate) Interrupt NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Instruction IDLE1 mode (Operate only oscillator) Interrupt (a) Single clock mode transition figure Figure 3.3.1 System Clock Block Diagram 91CW18A-12 2005-08-15 TMP91CW18A SYSCR0 SYSCR2 Warm-up timer (High-frequency oscillator) SYSCR0 fc/16 fFPH φT φT0 ÷2 ÷4 fFPH fc SYSCR0 X1 X2 ÷2 fc/2 fc/4 fc/8 SYSCR1 fc/16 fSYS H-OSC ÷2 ÷4 ÷8 ÷16 Clock gear SYSCR1 fSYS TMRA01 to TMRA67 φT0 Prescaler CPU ROM RAM TMRB0 Prescaler Interrupt contloller WDT I/O port UART Prescaler I2C bus 1 to 2 Prescaler SBI0 φT Prescaler SCOUTC fFPH P62 SYSCR2 Figure 3.3.2 Block Diagram of System Clock 91CW18A-13 2005-08-15 TMP91CW18A 3.3.2 SYSCR0 (00E0H) SFR 7 Bit symbol Read/Write After reset Function 1 0 1 0 High-frequency Always write oscillator (fc) 0 0: Stop 1: Oscillation 6 − 5 RXEN 4 − R/W 3 − 0 Always write 0 2 WUEF 0 Warm-up timer Write 0: Don’t care Write 1: Start timer Read 0: End warm-up Read 1: Do not end warm-up 1 PRCK1 0 00: fFPH 01: Reserved 10: fc/16 11: Reserved 0 PRCK0 0 XEN High-frequency Always write oscillator (fc) 0 after release of Stop mode 0: Stop 1: Oscillation Select prescaler clock 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 − 0 2 GEAR2 R/W 1 1 GEAR1 0 0 GEAR0 0 Always write Select gear value of high frequency (fc) 000: fc 0 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function 0: fs 6 SCOSEL R/W 0 1: fFPH 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 Pin state control in STOP mode 0: I/O off 1: Remains the state before halt Warm-up timer 00: Reserved 01: 28/inputted frequency 10: 214 11: 216 Note 1: SYSCR1 and SYSCR2 are read as undefined-value. Note 2: When using the built-in I2C bus or the I2C bus/SIO, set the select prescaler clock register SYSCR0 to 00 (fFPH). Figure 3.3.3 SFR for System Clock 91CW18A-14 2005-08-15 TMP91CW18A 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 – R/W 0 Always write 0 5 – R/W 1 Always write 1 4 – R/W 0 Always write 0 3 ALEEN R/W 0 ALE pin output control 0: High-Z output 1: ALE output 2 EXTIN R/W 0 1: External clock 1 DRVOSCH 0 – R/W 1 Always write 1 R/W 1 fc oscillator driving ability 1: Normal 0: Weak EMCCR1 (00E4H) Bit symbol Read/Write After reset Function Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0, =”1”. Writing 1FH turns protections off. Writing any value other than 1FH turns protection on. Figure 3.3.4 SFR for Noise Reduction 91CW18A-15 2005-08-15 TMP91CW18A 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains gear circuit for high-frequency (fc) operation. The register SYSCR0 control enabling and disabling of each oscillator and SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings = 1, = 0, = 0 and = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after a reset. For example, fSYS is set to 0.78 MHz when the 25-MHz oscillator is connected to the X1 and X2 pins. (1) Switching from NORMAL mode to SLOW mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. Table 3.3.1 shows the warm-up time. Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Time Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode 10 (μs) 0.655 (ms) 2.621 (ms) at fOSCH = 25 MHz 91CW18A-16 2005-08-15 TMP91CW18A (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 = 0, fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example: Changing to a high-frequency gear SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0000B (SYSCR1), XXXX0100B ; ; Changes fSYS to fc/2. Changes fSYS to fc/32. X: Don't care (Changing to high-frequency clock gear) To change the clock gear, write the appropriate value to the SYSCR1 register. The value of fFPH will not change until a period of time equal to the warm-up time has elapsed from the point at which the register is written to. There is a possibility that the instruction immediately following the instruction which changes the clock gear will be executed before the new clock setting comes into effect. To ensure that this does not happen, insert a dummy instruction (to execute a write cycle) as follows. Example: SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed (3) Internal clock pin output function The P62/SCOUT/INT2 pin outputs an internal clock: fFPH or fS. The following combination of settings – port 6 control register P6CR = 1 and P6FC = 1 – specifies that a clock signal will be output on the P62/SCOUT/INT2 pin. The setting of SYSCR2 determines which clock is output. Table 3.3.2 shows the pin state of the P62/SCOUT/INT2 pin when it is selected for clock output in the different operation modes. Table 3.3.2 SCOUT Pin States in Different Operation Modes Operation Mode SCOUT Select = 0 = 1 Outputs fFPH clock. NORMAL, SLOW HALT mode IDLE2 IDLE1 STOP Outputs low. Fixed to 0 or 1. 91CW18A-17 2005-08-15 TMP91CW18A 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA67, TMRB0, TMRB1, SIO0, SIO1 and SBI) there is a prescaler which can divide the clock. The φT clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 register determines which clock signal is input. The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0 register determines which clock signal is input. 3.3.5 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) (2) (3) (4) Reduced driveability for high-frequency oscillator Single drive for high-frequency oscillator Disabling of ALE pin output Protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 and EMCCR1 registers. (1) Reduced driveability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) STOP C1 Resonator C2 X2 pin X1 pin Enable oscillation (STOP+EMCCR0) EMCCR0 fOSCH (Setting method) The driveability of the oscillator is reduced by writing 0 to the EMCCR0 register. On a reset, is initialized to 1 and the oscillator starts oscillation by normal driveability when the power supply is on. 91CW18A-18 2005-08-15 TMP91CW18A (2) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when the external oscillator is used. (Block diagram) STOP X1 pin Enable oscillation fOSCH EMCCR0 (STOP+EMCCR0) X2 pin (Setting method) When a 1 is written to the EMCCR0, the oscillator is disabled and is operated as a buffer. The X2 pin always outputs a 1. is initialized to 0 by a reset. Note: Do not write EMCCR0 = “1” when using external resonator. (3) Disabling ALE pin output (Purpose) If the CPU does not access any external area, output of the ALE pulse can be disabled, thereby reduction noise. (Block diagram) EMCCR0 Internal ALE ALE pin (Setting method) Writing 0 to the EMCCR0 register sets the ALE pin to high-impedance. is initialized to 0 by a reset. If the CPU needs to access an external area, 1 must first be written to . 91CW18A-19 2005-08-15 TMP91CW18A (4) Protection of register contents (Purpose) An item for mistake operation by inputted noise. To execute the program certainty which is occurred mistake operation, the protect register can be disabled write-operation for the specific SFR. Write disabled SFRs 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Block diagram) To EMCCR1 Write value other than 1FH Write 1FH Protect register EMCCR0 SQ R Write signal SFR Write signal to the disabled SFR Write signal to the other SFR (Setting method) Writing any value other than 1FH to the EMCCR1 register turns on protection, thereby preventing the CPU from writing to the specific SFR. Writing 1FH to EMCCR1 turns off protection. The protection status is set in EMCCR0. Resetting initializes the protection status to OFF. 91CW18A-20 2005-08-15 TMP91CW18A 3.3.6 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register. The subsequent actions performed in each mode are as follows. 1. IDLE2: The CPU only is halted. In IDLE2 mode internal I/O operations can be performed by setting the following registers. Table 3.3.3 shows the registers of setting operation during IDLE2 mode. Table 3.3.3 Registers of Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRA67 TMRB0 SIO0 (I C bus/SIO) SIO1 (I C bus) SIO2 (I C bus) UART AD converter WDT 2 2 2 SFR TA01RUN TA23RUN TA45RUN TA67RUN TB0RUN SBI0BR00 SBI0BR01 SBI0BR02 SC0MOD1 ADMOD1 WDMOD 2. 3. IDLE1: Only the oscillator continue to operate. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO, SBI AD converter WDT Interrupt controller Operation Available to select operation block. Stop IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.3.7, Table 3.3.8 Keep the state when the HALT instruction was executed. Block 91CW18A-21 2005-08-15 TMP91CW18A (2) How to clear a HALT mode The halt state can be cleared by a reset or by an interrupt request. The combination of the value in of the interrupt mask register and the current HALT mode determine in which ways the HALT mode may be cleared. The details associated with each type of halt state clearance are shown in Table 3.3.5. • Clearance by interrupt request Whether or not the HALT mode is cleared and subsequent operation depends on the status of the generated interrupt. If the interrupt request level set before execution of the HALT instruction is greater than or equal to the value in the interrupt mask register, the following sequence takes place. The HALT mode is cleared, the interrupt is then processed and the CPU then resumes execution starting from the instruction following the HALT instruction. If the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is not cleared. (If a non-maskable interrupt is generated, the HALT mode is cleared and the interrupt processed, regardless of the value in the interrupt mask register.) However, for NMI and INT0 to INT4 interrupts only, even if the interrupt request level set before execution of the HALT instruction is less than the value in the interrupt mask register, the HALT mode is cleared. In this case, the interrupt is not processed and the CPU resumes execution starting from the instruction following the HALT instruction. The interrupt request flag remains set to 1. Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. • Clearance by reset Any halt state can be cleared by a reset. When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms) must be allowed after the reset for the operation of the oscillator to stabilize. When a HALT mode is cleared by resetting, the contents of the internal RAM remain the same as they were before execution of the HALT instruction. However, all other settings are re-initialized. (Clearance by an interrupt affects neither the RAM contents nor any other settings – the state which existed before the HALT instruction was executed is retained.) 91CW18A-22 2005-08-15 TMP91CW18A Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of Halt State Clearance NMI INTWDT INT0 to INT4 (Note 1) Interrupt INT5, INT6 INTTA0 to INTTA7 INTTB00, 01, 10, 11, OF0, OF1 INTRX0, INTRX1, TX0, TX1 INTS2 INTAD RESET Interrupt Enabled Interrupt Disabled (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE2 ♦ ♦ ♦ ♦ (Note 2) ♦ ♦ ♦ ♦ ♦ IDLE1 STOP ♦ × IDLE2 − − IDLE1 STOP − − − − ♦ *1 ♦ × × × × × × ♦* 1 × × × × × × × ○ × × × × × × ○ × × × × × × ○* 1 × × × × × × Reset initializes the LSI ♦: After clearing the HALT mode, CPU starts interrupt processing. (RESET initializes the microcontroller.) ○: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. ×: Cannot be used to clear the HALT mode. −: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The HALT mode is cleared when the warm-up time has elapsed. Note 1: When the HALT mode is cleared by an INT0 to INT4 interrupt of the level mode in the interrupt enabled status, hold this level until starting interrupt processing. Changing level before holding level, interrupt processing is correctly started. Note 2: If one of the external interrupts INT5 and INT6 are generated in IDLE2 mode, TB0RUN is set to 1. (Example − clearing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (P6FC), 01H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ;Sets P60 to INT0 ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91CW18A-23 2005-08-15 TMP91CW18A (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.5 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 ALE AD0 to AD15 RD WR Address Data Address Address Data Clearing interrupt IDLE2 mode Figure 3.3.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.6 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 ALE AD0 to AD15 RD WR Address Data Address Data Clearing interrupt IDLE1 mode Figure 3.3.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91CW18A-24 2005-08-15 TMP91CW18A 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 register. Table 3.3.7 and Table 3.3.8 summarizes the state of these pins in STOP mode. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP mode has been cleared, either NORMAL mode or SLOW mode can be selected using the SYSCR0 register. Therefore, , and must be set. See the sample warm-up time in Table 3.3.6. Figure 3.3.7 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 ALE AD0 to AD15 Address Data Address Data RD WR Interrupt for release STOP mode Figure 3.3.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.6 Sample Warm-up Time after Clearance of STOP Mode at fOSCH = 25 MHz SYSCR0 0 (fc) SYSCR2 01 (2 ) 10 μs 8 10 (214) 0.655 ms 11 (216) 2.621 ms 91CW18A-25 2005-08-15 TMP91CW18A Table 3.3.7 Input Buffer State Table In HALT Mode (STOP) = 0 = 1 When Used When Used When Used When Used When Used When Used When Used When Used as Function as Input as Function as Input as Function as Input as Function as Input Pin Port Pin Port Pin Port Pin Port − − − − − − ON − ON − ON * * ON * ON ON ON ON − − − ON ON − ON ON ON ON ON ON ON ON ON ON ON ON ON OFF OFF OFF ON ON ON ON ON ON ON ON ON upon port read ON upon port read ON upon port read ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − − − − − − − − − OFF − ON − ON * * ON * ON ON ON − − − ON ON − ON ON ON ON ON ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF ON ON ON ON OFF OFF OFF ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − − − − − − − − − OFF − OFF OFF ON * * OFF * ON ON − − − ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF − − − − − − − − − − OFF − ON − ON * * ON * ON ON − − − ON ON − ON ON ON ON ON ON ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON OFF OFF OFF ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − − − When the CPU is Operating Input Buffer State In HALT Mode (IDLE1/IDLE2) Input Function Port Name Name During Reset P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 P20 to P27 AD16 to AD23 P30 − P31 − P32 − (Note 1) P33 WAIT (Note 1) P34 − P35 TA6IN P36 − P37 INT4 P40 to P42 AN8 to AN10 (Note 2) P43 AN11 (Note 2) ADTRG P50 to P57 AN0 to AN7 (Note 2) P60 INT0 INT1 P61 CTS P62 INT2 P70 − P71 − P72 − TB0IN0 P73 INT5 TB0IN1 P74 INT6 P75 − P76 INT3 P80 SDA0 SIO P81 SCL0 P82 − P83 RXD0 P84 SDA1 P85 SCL1 P86 SDA2 P87 SCL2 NMI − RESET − AM0, AM1 − X1 − ON ON ON ON ON: OFF: −: Note 1: Note 2: *: The buffer is always turned on. A current flows through the input buffer if the input pin is not driven. The buffer is always turned off. Not applicable Port having a pull-up/pull-down resistor. AIN input does not cause a current to flow through the buffer. AIN input is always enable. 91CW18A-26 2005-08-15 TMP91CW18A Table 3.3.8 Output Buffer State Table In HALT Mode (STOP) = 0 = 1 When Used When Used When Used When Used When Used When Used When Used When Used as Function as Output as Function as Output as Function as Output as Function as Output Pin Port Pin Port Pin Port Pin Port ON upon external write ON ON ON ON ON ON − − − ON − − − − ON − ON ON ON ON − − ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − − ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − OFF OFF ON ON ON ON ON ON − − − ON − − − − ON − ON ON ON ON − − ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − − ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − OFF OFF OFF OFF OFF OFF OFF OFF − − − OFF − − − − ON − ON ON ON ON − − ON ON ON ON ON ON ON ON ON ON ON “H” level output Output Function Port Name Name During reset When the CPU is Operating Output Buffer State In HALT Mode (IDLE1/IDLE2) P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 (Note 1) P33 (Note 1) P34 P35 P36 P37 P40 to P7 P43 P50 to P7 P60 P61 P62 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 ALE X2 AD0 to AD7 AD8 to AD15 A8 to A15 A0 to A7 A16 to A23 RD WR HWR − − − TA7OUT − − − − − − SCOUT TA1OUT TA3OUT TA5OUT − − TB0OUT0 SCK0 SDA0 SO0 SCL0 TXD0 − SDA1 SCL1 SDA2 SCL2 − − OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF − − − OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF − − OFF OFF ON ON ON ON ON ON − − − ON − − − − ON − ON ON ON ON − − ON ON ON ON ON ON ON ON ON ON ON “H” level output ON ON ON ON ON ON ON ON ON ON ON ON ON − − − ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON − − OFF ON ON: OFF: −: Note 1: A current flows through the output buffer since the buffer is always turned on. The buffer is always turned off. Not applicable Port having a pull-up/pull-down resistor. 91CW18A-27 2005-08-15 TMP91CW18A 3.4 Interrupts Interrupts are controlled by the CPU’s interrupt mask register (Bits 12 to 14 of the status register) and by the built-in interrupt controller. The TMP91CW18A has a total of 38 interrupts divided into the following five types: • • • Interrupts generated by CPU: 9 sources (Software interrupts, illegal instruction interrupt) Internal I/O interrupts: 21 sources External interrupts: 8 sources Interrupts on external pins ( NMI and INT0 to INT6) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of 6 levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller transmits the interrupt source’s priority value to the CPU. When more than one interrupt are generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU’s interrupt mask register . If the priority level of the interrupt is greater than or equal to the value in the interrupt mask register, the CPU accepts the interrupt. However, software interrupts and illegal instruction interrupts generated by the CPU are processed irrespective of the value in . The value in the interrupt mask register can be changed using the EI instruction; the command EI n sets the contents of to n. For example, the command EI 3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent to the command EI 1). The DI instruction (which sets to 7) is exactly equivalent to the EI 7 instruction. The DI instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 1 to 6). The EI instruction takes effect as soon as it is executed. (On the TLCS-90, the EI instruction takes effect after the execution of the instruction which follows it.) 91CW18A-28 2005-08-15 TMP91CW18A In addition to the general-purpose interrupt processing mode described above, there is also a micro DMA processing mode. In micro DMA mode the CPU automatically transfers data in 1-byte, 2-byte or 4-byte blocks, this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, the TMP91CW18A also has a soft start function in which micro DMA processing is requested in software rather than by an interrupt. Figure 3.4.1 is a flowchart showing an overview of interrupt processing. Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector? Yes No Clear interrupt request flag Interrupt vector value “V” read Interrupt request F/F clear Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 Count ← Count−1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA trasfer end interrupt (INTTC0 to INTTC3) PC ← (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST ← INTNEST − 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 91CW18A-29 2005-08-15 TMP91CW18A 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3) and executes only steps (2), (4) and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level have been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: The smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (Pointed to by XSP). (3) The CPU sets the value of the CPU’s interrupt mask register to the priority level for the accepted interrupt plus 1. However, if the priority level for the accepted interrupt is 7, the register’s value is set to 7. (4) The CPU increments the interrupt nesting counter INTNEST by 1. (5) The CPU jumps to the address given by adding the contents of address FFFF00H to the interrupt vector, then starts the interrupt processing routine. On completion of interrupt processing, the RETI instruction is used to return control to the main routine. RETI restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU’s interrupt mask register , the CPU will accept the interrupt. The CPU’s interrupt mask register is then set to the value of the priority level for the accepted interrupt plus 1. Thus, if during interrupt processing another interrupt is generated with a higher priority than the interrupt currently being processed, or if during the processing of a non-maskable interrupt, a non-maskable interrupt request is generated from another source, the CPU will suspend the routine which it is currently executing and accept the new interrupt. When processing of the new interrupt has been completed, the CPU will resume processing of the suspended interrupt. If the CPU receives another interrupt request while performing processing steps (1) to (5), the second interrupt will be sampled immediately after execution of the first instruction of its interrupt processing routine. Specifying DI as the first instruction disables nesting of maskable interrupts. (Note: On the TLCS-900 and 900/L, sampling is performed before execution of the first instruction.) A reset initializes the interrupt mask register to 111, disabling all maskable interrupts. Table 3.4.1 shows the TMP91CW18A interrupt vectors and micro DMA start vectors. FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area. 91CW18A-30 2005-08-15 TMP91CW18A Table 3.4.1 TMP91CW18A Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 − 11 12 13 14 15 16 17 − − 20 21 22 23 24 25 26 27 28 29 − − 32 － 34 35 36 37 38 − 40 41 42 43 44 − to − Maskable − Nonmaskable Type Interrupt Source or Source of Micro DMA Request Reset or instruction “SWI0” Instruction “SWI1” Illegal instruction or instruction “SWI2” Instruction “SWI3” Instruction “SWI4” Instruction “SWI5” Instruction “SWI6” Instruction “SWI7” NMI : NMI pin input Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H − 0028H 002CH 0030H 0034H 0038H 003CH 0040H − − 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H − − 007CH 0084H 0088H 008CH 0090H 0094H − 009CH 00A0H 00A4H 00A8H 00ACH 00B0H to 00FCH Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H − FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H − − FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H − − FFFF7CH FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H − FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H to FFFFFCH Micro DMA Start Vector − − − − − − − − − − − 0AH 0BH 0CH 0DH 0EH 0FH 10H − − 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH − − 1FH 21H 22H 23H 24H 25H − 27H 28H 29H 2AH 2BH − to − INTWD: Watchdog timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input INT5: INT5 pin input INT6: INT6 pin input − − INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INTTA6: 8-bit timer 6 INTTA7: 8-bit timer 7 INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) − − INTTBOF0: 16-bit timer 0 (Overflow) － INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTI2C2: I C bus interface interrupt INTI2C1: I C bus interface interrupt INTSBI0: Serial bus interface interrupt − INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) − (Reserved) 2 2 91CW18A-31 2005-08-15 TMP91CW18A 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91CW18A also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU is a state of standby mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored (Pending) and DMA trandfer is started after release HALT. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The four micro DMA channels allow micro DMA processing to be set for up to four types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC3) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number. The lower the channel number, the higher the priority (Channel 0 thus has the highest priority and channel 3 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general-purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (e.g., interrupt requests should be disabled). If micro DMA and general-purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels.(Note) In this case, edge-triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA start vector” (in the Table 3.4.1 ) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91CW18A-32 2005-08-15 TMP91CW18A Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: 1-byte transfers, 2-byte (One-word) transfers and 4-byte transfers. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (4) “Detailed description of the transfer mode register”. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (Provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 35 different interrupts – the 34 interrupts shown in the micro DMA start vectors in Table 3.4.1 or a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode. (Micro DMA transfers are the same in every mode except counter mode.) (The conditions for this cycle are as follows: External 16-bit bus, 0 waits, and even-numbered transfer source and transfer destination addresses.) One state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Transfer source address Transfer destination address D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1, 3: Instruction fetch cycle (Prefetch the next instruction) Once 3 or more bytes of code have been fetched into the instruction queue, dummy cycle is inserted into instruction fetch cycle. States 4, 5: Micro DMA read cycle State 6: Dummy cycle (The address bus remains unchanged from state 5) States 7, 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is incremented by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. Note 2: If the destination address area is an 8-bit bus, it is incremented by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is incremented by two states. 91CW18A-33 2005-08-15 TMP91CW18A (2) Soft start function The TMP91CW18A can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once (If write “0” to each bit, micro DMA doesn’t operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. DMA can only be requested for one channel at once. (Therefore, do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read 1, micro DMA transfer isn’t started yet. When a burst is specified by the register DMAB, data is transferred continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn’t change. Don’t use Read-modify write instruction to avoid writing to other bits by mistake. Symbol DMAR Name DMA request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 1 DMAR1 0 0 DMAR0 0 DMA request R/W (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form “LDC cr, r” can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0. DMA destination address register 0. DMA counter register 0. DMA mode register 0. Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3. DMA destination address register 3. DMA counter register 3. DMA mode register 3. 91CW18A-34 2005-08-15 TMP91CW18A (4) Detailed description of the transfer mode register 8 bits DMAM 0 to 3 0 0 0 Mode Note: Only values whose upper 3 bits are 000 should be set in this register. Number of Minimum Execution States Execution Time (*) at fc = 25 MHz 8 states 12 states 640 ns 960 ns Number of Transfer Bytes 000 (Fixed) 000 00 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Mode Description Transfer destination address INC mode .................................................I/O to memory (DMADn+) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode .................................................I/O to memory (DMADn−) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode .................................................Memory to I/O (DMADn) ← (DMASn+) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode .................................................Memory to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ......................................................... I/O to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. 8 states 12 states 640 ns 960 ns 8 states 12 states 640 ns 960 ns 8 states 12 states 640 ns 960 ns 8 states 12 states 640 ns 960 ns Counter mode ......................For counting number of times interrupt is generated DMASn ← DMASn + 1 DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. 5 states 400 ns *: External 16-bit bus, 0 waits, word transfer mode or 4-byte transfer mode, even-numbered transfer source and transfer destination addresses. Note: n stands for the micro DMA channel number (0 to 3) DMADn+/DMASn+: Post-increment (Register value is incremented after transfer) DMADn−/DMASn−: Post-decrement (Register value is decremented after transfer) “I/O” signifieds fixed memory addresses; “memory” signifies incremented or memory addresses. The trasnfer mode register should not be set to any value other than those listed above. 91CW18A-35 2005-08-15 TMP91CW18A 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 38 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: When a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by a 0 written to the clear bit in the interrupt priority setting register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt’s vector address to the CPU. The CPU compares the mask value set in of the status register (SR) with the priority level of the requested interrupt; if the latter is higher, the interrupt is accepted. Then, the CPU sets SR to the priority level of the accepted interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in SR (e.g., interrupts with a priority higher than the interrupt being processed) will be accepted. When interrupt processing has been completed (e.g., after execution of a RETI instruction), the CPU restores to SR the priority value which was saved on the stack before the interrupt was generated. The interrupt controller also includes four registers which are used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (See Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to micro DMA processing. 91CW18A-36 2005-08-15 Interrupt controller Interrupt request F/F S Reset R Interrupt vector read V = 20H V = 24H CPU 1 NMI Q Reset INTWD Interrupt mask F/F Priority encoder IFF2:0 3 Interrupt level detect 3 INTRQ 2 to 0 Priority setting register Dn A Dn + 1 Interrupt Decoder B EI1 to EI7 DI Interrupt request signal to CPU D CLR C Q 1 7 3 6 6 1 INT0 to INT6 control Dn + 2 Y1 Y2 Y3 Y4 Y5 Y6 Level/edge S Reset Interrupt request flag Q Interrupt request F/F read 38 Interrupt vector generator 7 INT0 selection R Interrupt vector read Micro DMA acknowledge Dn + 3 D0 D1 2 Highest A B 3 priority interrupt C 4 level 5 select 6 If INTRQ2 to 0 ≥ IFF 2 to 0 then 1. and Rising edge/ falling edge IDLE1 STOP INT1 INT2 INT3 INT4 INT5 INT6 * selection Figure 3.4.3 Block Diagram of Interrupt Controller V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 4CH V = 50H V = 54H D2 D3 D4 D5 D6 D7 91CW18A-37 Interrupt vector read V = 9CH V = A0H V = A4H V = A8H V = ACH Micro DMA start vector setting register INTTA0 INTTA1 INTTA2 Halt release RESET INT0, INT1, INT2, INT3, INT4 NMI 4-input OR 4 if IFF = 7 then 0 0 1 2 3 A 2 2 Micro DMA request Micro DMA counter zero interrupt Soft start INTAD INTTC0 INTTC1 INTTC2 INTTC3 D CLR INTTC0 D5 D4 D3 D2 D1 D0 Q 6 Selector 34 S Reset TMP91CW18A DMA0V DMA1V DMA2V DMA3V B Micro DMA channel priority encoder Micro DMA channel specification 2005-08-15 *: Only rising edge TMP91CW18A (1) Interrupt priority setting registers Symbol INTE0AD Name Address INT0 & INTAD enable INT1 & 90H 7 IADC R 0 I2C R 0 I4C R 0 I6C R 0 ITA1C R 0 ITA3C R 0 ITA5C R 0 ITA7C R 0 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 INT6 I6M2 0 ITA1M2 0 ITA3M2 0 ITA5M2 0 ITA7M2 0 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 I6M1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 ITA7M1 R/W 0 4 IADM0 0 I2M0 0 I4M0 0 I6M0 0 ITA1M0 0 ITA3M0 0 ITA5M0 0 ITA7M0 0 3 I0C R 0 I1C R 0 I3C R 0 I5C R 0 ITA0C R 0 ITA2C R 0 ITA4C R 0 ITA6C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 ITA0M2 0 ITA2M2 0 ITA4M2 0 ITA6M2 0 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 ITA6M1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 I5M0 0 ITA0M0 0 ITA2M0 0 ITA4M0 0 ITA6M0 0 INTE12 INT2 enable INT3& 91H INTE34 INT4 enable INT5 & 92H INTE56 INT6 enable INTTA0 93H INTTA1 (TMRA1) 95H INTTA0 (TMRA0) INTETA01 & INTTA1 enable INTTA2 & INTTA3 enable INTTA4 & INTTA5 enable INTTA6 & INTTA7 enable INTTA3 (TMRA3) 96H INTTA2 (TMRA2) INTETA23 INTTA5 (TMRA5) 97H INTTA4 (TMRA4) INTETA45 INTTA7 (TMRA7) 98H INTTA6 (TMRA6) INTETA67 lxxM2 0 0 0 0 1 1 1 1 Interrupt request flag lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91CW18A-38 2005-08-15 TMP91CW18A Symbol Name Address Interrupt INTETB0 enable TMRB0 Interrupt INTETB0 OV enable TMRB0 (Over flow) INTE UART Interrupt enable UART Interrupt INTES2 enable I C2 Interrupt INTES1 enable I C1 & SBI INTTC0 INTETC 01 & INTTC1 enable INTTC2 INTETC 23 & INTTC3 enable A1H A0H 2 2 7 ITB01C R 0 6 5 4 3 ITB00C R 0 ITF0C 2 1 0 INTTB01 (TMRB0) 99H ITB01M2 ITB01M1 ITB01M0 R/W 0 0 0 (Reserved) 9BH R 0 INTTX0 9CH ITX0C R 0 0 ITX0M2 ITX0M1 R/W 0 0 (Reserved) 9DH R 0 INTI2C1 9EH INTI2C1C II2C1M2 R 0 ITC1C R 0 ITC3C R 0 0 0 INTTC3 ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 0 INTTC1 ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 II2C1M1 R/W 0 0 II2C1M0 IS0C R 0 ITX0M0 IRX0C R 0 INTTB00 (TMRB0) ITB00M2 ITB00M1 ITB00M0 R/W 0 ITF0M2 0 INTRX0 IRX0M2 0 INTI2C2 INTI2C2C II2C2M2 0 INTSBI0 IS0M2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 ITC2M1 R/W 0 0 ITC2M0 ITC0M1 R/W 0 0 ITC0M0 IS0M1 R/W 0 0 IS0M0 II2C2M1 R/W 0 0 II2C2M0 IRX0M1 R/W 0 0 IRX0M0 0 ITF0M1 R/W 0 0 0 ITF0M0 INTTBOF0 (TMRB0) lxxM2 0 0 0 0 1 1 1 1 Interrupt request flag lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91CW18A-39 2005-08-15 TMP91CW18A (2) External interrupt control Symbol Name Address 7 − Interrupt IIMC input mode control 0 Always write 0 6 I4EDGE 0 0: Rising 1: Falling 5 I3EDGE 0 0: Rising 1: Falling 4 I2EDGE W 3 I1EDGE 0 0: Rising 1: Falling 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE 0 edge mode 1: INT0 level mode 0 NMIREE 0 1: Operates even on rising + falling edge of NMI 8CH (Prohibit RMW) 0 0: Rising 1: Falling INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 INT0 level enable 0 1 0 1 Edge detect INT High level INT INT request generation at falling edge INT request generation at rising/falling edge NMI rising edge enable Setting for external interruption inputs Interrupt Request Pin Pin Name NMI − Mode Falling edge Falling/rising edge Rising edge Falling edge High level Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Falling edge Rising edge Condition IIMC = 0 IIMC = 1 IIMC = 0, = 0 IIMC = 0, = 1 IIMC = 1 IIMC = 0 IIMC = 1 IIMC = 0 IIMC = 1 IIMC = 0 IIMC = 1 IIMC = 0 IIMC = 1 TB0MOD = 0, 0 or 0, 1 or 1, 1 TB0MOD = 1, 0 − INT0 P60 INT1 INT2 INT3 INT4 INT5 INT6 P61 P62 P76 P37 P73 P74 (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH INT0 Symbol Name Address Interrupt INTCLR clear control 88H (Prohibit RMW) Clears interrupt request flag. 5 CLRV5 0 7 6 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 Interrupt vector 91CW18A-40 2005-08-15 TMP91CW18A (4) Micro DMA start vector registers These registers assign micro DMA processing to an interrupt sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel’s micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) Symbol Name Address DMA0 DMA0V start vector DMA1 DMA1V start vector DMA2 DMA2V start vector DMA3 DMA3V start vector 83H 82H 81H 80H 7 6 5 DMA0V5 0 DMA1V5 0 DMA2V5 0 DMA3V5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 2 DMA0V2 0 DMA0V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0 start vector R/W DMA1 start vector R/W DMA2 start vector R/W DMA3 start vector R/W (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches 0. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name Address DMA DMAR software request register DMA DMAB burst register 8AH 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 0 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 1: DMA software request 1: DMA burst request 91CW18A-41 2005-08-15 TMP91CW18A (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid the above program, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (e.g., “NOP” × 1 times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, please note that the following two circuits are exceptional and demand special attention. INT0 level mode In level mode INT0 is not an edge-triggered interrupt, hence in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to ; edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. ; Wait EI instruction Note: INT0: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. (High → Low) INTRX: Instructions which read the receive buffer. 91CW18A-42 2005-08-15 TMP91CW18A 3.5 Port Functions The TMP91CW18A features 62-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 lists I/O registers and their specifications. Table 3.5.1 Port Functions (OD: ∆ = Open drain) (R: ↑ = with programmable pull-up resistor) (POD: ○ = Programmable open drain) Port Name Port 0 Port 1 Port 2 Pin Name P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 P33 P34 P35 P36 P37 Number of Pins 8 8 8 1 1 1 1 1 1 1 1 4 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R − − − − − ↑ ↑ − − − − − − − − − − − − − − − − − − − − − − − − POD OD Direction Setting Unit Bit Bit Bit Pin Name for Internal Function AD0 to AD7 AD8 to AD15/A8 to A15 A16 to A23/A0 to A7 RD WR HWR WAIT Port 3 ○ ○ ○ ○ ○ ○ ○ ○ Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit TA6IN TA7OUT INT4 AN8 to AN11, ADTRG (P40) AN0 to AN7 INT0 INT1/ CTS INT2/SCOUT TA1OUT TA3OUT TA5OUT TB0IN0/INT5 TB0IN1/INT6 TB0OUT0 INT3/SCK0 SDA0/SO0 SCL0/SIO TXD RXD SDA1 SCL1 SDA2 SCL2 Port 4 Port 5 Port 6 P40 to P43 P50 to P57 P60 P61 P62 P70 P71 P72 Port 7 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 Port 8 ○ ○ ○ ○ ∆ ∆ ∆ ∆ Bit Bit Bit Bit Bit Bit Bit Bit 91CW18A-43 2005-08-15 TMP91CW18A Table 3.5.2 I/O Registers and Their Specifications (1/2) Port Port 0 Name P00 to P07 Specification Input port Output port AD bus (AD0 to AD7) Input port Output port AD bus (AD8 to AD15) A output (A8 to A15) Input port Output port A output (A0 to A7) A output (A16 to A23) Input port Output port Outputs RD only when accessing an external area Always output RD Input port Output port Outputs WR only when accessing an external area Input port (without pull up) Input port (with pull up) Output port HWR output WAIT input (without pull up) WAIT input (with pull up) Output port Input port Output port Input port Output port TA6IN input Input port Output port TA7OUT output Input port Output port INT4 input Input port AN input (AN8 to AN11) (Note 1) ADTRG input (Note 2) Input port AN input (AN0 to AN7) (Note 1) Input port Output port INT0 input Input port Output port INT1 input CTS input Input port (SCOUT) Output port (SCOUT) INT2 input (SCOUT) SCOUT output (SCOUT) I/O registers Pn × × × × × × × × × × × × × 1 0 × × × 0 1 × × 0 1 × × × × × × × × × × × × × × × × × × × × × × × × × × × × PnCR 0 1 × 0 1 0 1 0 1 0 1 0 1 None 0 1 None 0 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 None None 0 1 0 0 1 0 0 0 1 0 1 PnFC None 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 0 1 None None None 0 0 1 0 0 1 Port 1 P10 to P17 Port 2 P20 to P27 P30 P31 P32 Port 3 P33 P34 P35 P36 P37 P40 to P43 P40 Port 5 P50 to P57 P60 Port 4 Port 6 P61 P62 (Note 4) 0 0 1 0 0 1 0 0 0 1 0 X: Don’t care 91CW18A-44 2005-08-15 TMP91CW18A Table 3.5.3 I/O Registers and Their Specifications (2/2) Port Port 7 Name P70 Input port Output port TA1OUT output P71 Input port Output port TA3OUT output P72 Input port Output port TA5OUT output P73 Input port Output port Specification I/O registers Pn × × × × × × × × × PnCR 0 1 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 PnFC 0 0 1 0 0 1 0 0 1 None (IIEC) (IIEC) (IIEC) (IIEC) (IIEC) (IIEC) × × × × × × × × × INT5/TB0IN0 input P74 Input port Output port INT6/TB0IN1 input P75 Input port Output port TB0OUT0 output P76 Input port Output port SCK0 input/output INT3 input Port 8 (Note 5) P80 Input port Output port SDA0 input SO0 output P81 Input port Output port SCL0 input/output SI0 input P82 Input port Output port TXD output P83 Input port Output port RXD input P84 Input port Output port SDA1 input/output P85 Input port Output port SCL1 input/output P86 Input port Output port SDA2 input/output P87 Input port Output port SCL2 input/output None 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 None 0 0 1 0 0 1 0 0 1 0 0 1 (IIEC) (IIEC) (IIEC) (IIEC) × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × X: Don’t care 91CW18A-45 2005-08-15 TMP91CW18A Note 1: When P50 to P57 are used as AD converter input channels, a 3-bit field in the AD mode control register ADMOD1 is used to select the channel. Note 2: When P40 is used as the ADTRG input, ADMOD1 is used to enable external trigger input. Note 3: When P30 to P37 are used as open-drain outputs, P3ODE are used to set open-drain output mode. Note 4: When P62 is used SCOUT, SCOUT is used to set SCOUT. Note 5: When P80 to P83 are used as open-drain outputs, P8ODE are used to set open-drain output mode. Note 6: When P73, P74, P76 are used as INT5/TB0IN0, INT6/TB0IN1 and INT3 are used to set IIEC. After a reset the port pins listed below function as general-purpose I/O port pins. A reset sets I/O pins which can be programmed for either input port pins. Setting the port pins for internal function use must be done in software. 91CW18A-46 2005-08-15 TMP91CW18A 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port each bit can be individually for input or output using the control register P0CR. Resetting resets all bits of P0CR to 0 and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 can also function as an address data bus (AD0 to AD7), allowing access to external memory. In this case, all bits in the control register P0CR are cleared to 0. Reset Direction control (on bit basis) P0CR write Internal data bus Output latch Output buffer P0 write Port 0 P00 to P07 (AD0 to AD7) P0 read Figure 3.5.1 Port 0 91CW18A-47 2005-08-15 TMP91CW18A 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and the function register P1FC. Resetting resets all bits of the output latch P1, the control register P1CR and the function register P1FC to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (AD8 to AD15) or an address bus (A8 to A15). Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch Output buffer P1 write Port 1 P10 to P17 (AD8 to AD15/A8 to A15) P1 read Figure 3.5.2 Port 1 91CW18A-48 2005-08-15 TMP91CW18A Port 0 Register 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Data from external port (Output latch register becomes undefined.) Port 1 Register 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 0: Input P07C 6 P06C 0 5 P05C 0 4 P04C W 0 3 P03C 0 2 P02C 0 1 P01C 0 0 P00C 0 1: Output (at external access, port 0 becomes AD7 to AD0 and P0CR is cleared to 0.) Port 0 I/O setting 0 Input 1 Output Port 1 Register 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 P17C 6 P16C 0 5 P15C 0 4 P14C W 0 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 Port 1 Function Register 7 P1FC (0005H) Bit symbol Read/Write After reset Function 0 P17F 6 P16F 0 5 P15F 0 4 P14F W 0 3 P13F 0 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8 Port 1 function setting P1FC P1CR 0 1 Read-modify-write instructions are prohibited for registers P0CR, P1CR and P1FC. 0 Input port Output port 1 Address data bus (AD15 to AD8) Address bus (A15 to A8) Note: is bit X in register P1FC: , in register P1CR. Figure 3.5.3 Registers for Ports 0 and 1 91CW18A-49 2005-08-15 TMP91CW18A 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and the function register P2FC. Resetting set all bits of the output latch P2 to “1”, the control register P2CR and the function register P2FC to 0 and sets port 2 to input mode. In addition to functioning as a general-purpose I/O port, port 2 can also function as an address bus (A0 to A7) or (A16 to A23). A16 to A23 A0 to A7 Reset Selector S B A Y Direction control (on bit basis) P2CR write Function control (on bit basis) Internal data bus P2FC write S Output latch A Selector B Y Output buffer Port 2 P20 to P27 (A0 to A7/A16 to A23) P2 write P2 read Figure 3.5.4 Port 2 91CW18A-50 2005-08-15 TMP91CW18A Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Data from external port (Output latch register is set to 1.) Port 2 Control Register 7 P2CR (0008H) Bit symbol Read/Write After reset Function 0 P27C 6 P26C 0 5 P25C 0 4 P24C W 0 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 Port 2 Function Register 7 P2FC (0009H) Bit symbol Read/Write After reset Function Note: Read-modify-write instructions are prohibited for P2CR and P2FC. 0 P27F 6 P26F 0 5 P25F 0 4 P24F W 0 3 P23F 0 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16 Port 2 function setting P2FC P2CR 0 1 0 Input port Output port 1 Address bus (A7 to A0) Address bus (A23 to A16) Note: is bit X in register P2FC; is bit X in register P2CR. When setting port 2 to function as the address bus A23 to A16, first set P2CR, then set P2FC. Figure 3.5.5 Registers for Port 2 91CW18A-51 2005-08-15 TMP91CW18A 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output. I/O is set using the control register P3CR and the function register P3FC. Resetting sets all bits of the output latch P3 and bit 0 and bit 1 of control register P3CR to 1. Bit 2 to bit 7 of P3CR are set to 0. All bits of the control register P3CR (P30C, P31C sets to 1, P32C to P37C resets to 0) and the function register P3FC (of which bits 3, 4 and 5 are unused) are cleared to 0. Resetting also causes P30 and P31 to output 1, sets P32 to P33 to input mode and turns on the pull-up resistor. And also, when output port is set, each bit is able to be set as open-drain port by P3ODE. In addition to functioning as a general-purpose I/O port, port 3 can also function as the I/O for the CPU’s control/status signal. When the P30 pin is set for RD signal output mode ( = 1), clearing the output latch register to 0 causes the RD strobe signal (used for the pseudo-static RAM) to be output from the P30 pin even while the internal address area is being accessed. If the output latch register remains set to 1, the RD strobe signal is output only while the external address area is being accessed. 91CW18A-52 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write RD , WR A S Selector P30 ( RD ), P31( WR ) B S Selector P3 read B A Figure 3.5.6 Port 3 (P30, P31) 91CW18A-53 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write HWR A S Selector P32 ( HWR ) B S Selector P3 read B A Figure 3.5.7 Port 3 (P32) 91CW18A-54 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write P33 ( WAIT ) S Selector P3 read B A WAIT Figure 3.5.8 Port 3 (P33) 91CW18A-55 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write P34 S Selector P3 read B A Figure 3.5.9 Port 3 (P34) 91CW18A-56 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus S Output latch P3 write P35 (TA6IN) S Selector P3 read B A TA6IN Figure 3.5.10 Port 3 (P35) 91CW18A-57 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write TA7OUT A S Selector P36 (TA7OUT) B S Selector P3 read B A Figure 3.5.11 Port 3 (P36) 91CW18A-58 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P3ODE write P3ODE read Direction control (on bit basis) P3CR write Internal data bus Function control (on bit basis) P3FC write S Output latch P3 write P37 (INT4) S Selector P3 read INT4 INT4 control B A Figure 3.5.12 Port 3 (P37) 91CW18A-59 2005-08-15 TMP91CW18A Port 3 Register 7 P3 (0007H) Bit symbol Read/Write After reset Function − 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 1 0 P30 1 P37 Data from external port (Output latch register is set to 1.) 0 (Output latch register) : Pull-up resistor OFF 1 (Output latch register) : Pull-up resistor ON − Port 3 Control Register 7 P3CR (000AH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input P37C 6 P36C 5 P35C 4 P34C W 0 1: Output I/O setting 0 Input 1 Output 0 1 1 3 P33C 2 P32C 1 P31C 0 P30C Port 3 Function Register 7 P3FC (000BH) Bit symbol Read/Write After reset Function 0 0: Port 1: INT4 P37F W 0 0: Port 1: TA7OUT 0 0: Port 1: HWR 6 P36F 5 4 3 2 P32F 1 P31F W 0 0: Port 1: WR 0 0: Port 1: RD 0 P30F P30 ( RD ) function setting 0 0 0 output RD is always 1 1 output RD is only TA7OUT setting 1 P3FC P3CR INT4 setting 1 1 output (for pseudo SRAM). output during external accesses. P31( WR ) function setting Note 1: Read-modify-write instructions are prohibited for registers P3CR and P3FC. Note 2: When port 3 is used in Input mode, the P3 register controls the built-in pull-up resistor. Read-modify-write instructions are prohibited in input mode or I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When the P33/ WAIT pin is to be use as the WAIT pin, P3CR must be set to 0 and in the chip select/wait control register must be set 010. 0 1 0 0 output 1 1 output P3FC P3CR 1 0 WR is only output during external accesses. HWR setting P3FC 1 P3CR 1 Figure 3.5.13 Register for Port 3 (1/2) 91CW18A-60 2005-08-15 TMP91CW18A 7 P3ODE (002DH) Bit symbol Read/Write After rest Function 0 P37ODE 6 P36ODE 0 5 P35ODE 0 4 P34ODE 0 0: Normal R/W 3 P33ODE 0 1: Open drain 2 P32ODE 0 1 P31ODE 0 0 P30ODE 0 Setting to open drain 0 Normal 1 Open drain Figure 3.5.14 Register for Port 3 (2/2) 91CW18A-61 2005-08-15 TMP91CW18A 3.5 3.5.5 Port 4 (P40 to P43) Port 4 is a 4-bit input port and can also be used as the analog input pins for the internal AD converter. P40 is also used as the AD trigger input pin of AD converter. Port 4 Internal data bus Port 4 read P40 to P43 (AN8 to AN11) AD read Conversion result register AD converter Channel selector ADTRG (for P40 only) Figure 3.5.15 Port 4 7 P4 Bit symbol After reset (000CH) Read/Write 6 5 4 3 P43 2 P42 R 1 P41 0 P40 Data from external port Note: The input channel selection of AD converter and the permission of ADTRG (P40) input are set by AD converter mode register ADMOD1. Figure 3.5.16 Register for Port 4 91CW18A-62 2005-08-15 TMP91CW18A 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. Port 5 Internal data bus Port 5 read P50 to P57 (AN0 to AN7) AD read Conversion result register AD converter Channel selector Figure 3.5.17 Port 5 7 P5 (000DH) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R 3 P53 2 P52 1 P51 0 P50 Data from external port Figure 3.5.18 Register for Port 5 91CW18A-63 2005-08-15 TMP91CW18A 3.5.7 Port 6 (P60 to P62) Port pins 60 to 62 constitute a 3-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 6 to be an input port. It also sets all bits of the output latch to 1. In addition to functioning as a general-purpose I/O port, port pins 60 to 62 can also function the external interrupt INT0 to INT2 input, CTS input, SCOUT output function. The various functions can each be enabled by writing a 1 to the corresponding bit of the Port 6 function register (P6FC) or SCOUT control register (SCOUTC). Resetting resets all bits of the registers P6CR and P6FC to 0 and sets all bits to be input port pins. (1) Port pin 60 (INT0) Port pin 60 is a general-purpose I/O port pin. It can also be used as the external interrupt INT0 input pin. Reset Direction control (on bit basis) P6CR write Direction function (on bit basis) Internal data bus P6FC write Output latch Output buffer P6 write P60 (INT0) P6 read INT0 INT0 control Figure 3.5.19 Port 60 91CW18A-64 2005-08-15 TMP91CW18A (2) Port pin 61 ( CTS /INT1) Port pin 61 is a general-purpose I/O port pin. It can also be used as the external INT1 input pin or as the CST input pin (in UART mode). Reset Direction control (on bit basis) P6CR write Direction control Internal data bus (on bit basis) P6FC write S Output latch P6 write P6 read INT1 control INT1 CTS0 P61 ( CTS /INT1) S B selector A Figure 3.5.20 Port 61 91CW18A-65 2005-08-15 TMP91CW18A (3) Port pin 62 (INT2/SCOUT) Port pin 62 is a general-purpose I/O port pin. It can also be used as the external interrupt INT2 input pin or SCOUT output pin function. Reset Direction control (on bit basis) P6CR write SCOUTC (on bit basis) Internal data bus SCOUTE SCOUTC write Direction control (on bit basis) P6FC write S Output latch P6 write S Y P6 read fFPH clock INT2 B Selector A S P62 (SCOUT/INT2) A Y Selector B INT2 control Figure 3.5.21 Port 62 91CW18A-66 2005-08-15 TMP91CW18A Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset 6 5 4 3 2 P62 1 P61 R/W 0 P60 Data from external port (Output latch register is set to 1.) Port 6 Control Register 7 P6CR (0014H) Bit symbol Read/Write After reset Function 0 6 5 4 3 2 P62C 1 P61C W 0 0: Input 1: Output 0 P60C 0 Port 6 I/O setting 0 1 Input Output Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 6 5 4 3 2 P62F W 0 0: Port 1: INT2 1 P61F W 0 0: Port 1: INT1 0 P60F W 0 0: Port 1: INT0 Note: Read-modify-write instructions are prohibited for the registers P6CR, P6FC and SCOUT. P60 INT0 input setting P6FC P6CR P61 INT1 input setting P6FC P6CR P62 INT2 input setting P6FC P6CR SCOUTC 1 0 0 1 0 1 0 SCOUT Control Register 7 SCOUTC (001DH) Bit symbol Read/Write After reset Function 6 5 4 3 2 SCOUTE W 0 0: Port 1: SCOUT 1 0 output P62 SCOUT output setting SCOUT P6FC P6CR 1 0 1 Figure 3.5.22 Registers for Port 6 91CW18A-67 2005-08-15 TMP91CW18A 3.5 3.5.8 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 7 to be an input port. And the output latch register P7 (All bit) set to 1. In addition to functioning as a general-purpose I/O port, P70, P71 and P72 also functions as an 1, 3, 5 output (TA1OUT, TA3OUT and TA5OUT) of the 8-bit timer A, and port pins 73 and 74 can function as the 16-bit timer clock input INT5 and INT6 input, TB0IN0/INT5 and TB0IN1/INT6. P75 as 16-bit timer output (TB0OUT0), P76 as I/O function of the serial interface 0 (SCK0). For each of the output pins, timer output can be enabled by writing a 1 to the corresponding bit in the port 7 function register (P7FC). SCK0 output function become available when a proper bit of port 7 function register P7FC is 1 and a proper bit of interrput control register IIEC is 0. To use TB0IN0/INT5, TB0IN1/INT6 and SCK0/INT3 pin as external interrupt input pins,a proper bit of interrupt enable register IIEC must be set 1. By reset, a value of P7CR, P7FC and IIEC become 0 and all bits become input mode. 91CW18A-68 2005-08-15 TMP91CW18A Reset Direction control (on bit basis) P7CR write IIEC (on bit basis) INT5E, INT6E IIEC write S Output latch P7 write P7 read INT5/TB0IN0 INT6/TB0IN1 Internal data bus INT5/TB0IN0 control lINT6/TB0IN1 control Reset Direction control (on bit basis) S B P73 (TB0IN0, INT5) P74 (TB0IN1, INT6) Selector A P7CR write IIEC (on bit basis) INT3E IIEC write Direction control (on bit basis) P7FC write S Output latch A P7 write SCK0 Timer F/F OUT TA1OUT: Timer A1 TA3OUT: Timer A3 TA5OUT: Timer A5 TB0OUT0: Timer B0 S P70 (TA1OUT) P71 (TA3OUT) P72 (TA5OUT) P75 (TB0OUT0) P76 (SCK0, INT3) Selector B B Selector P7 read SCK0 input INT3 S A INT3 control Figure 3.5.23 Port 7 91CW18A-69 2005-08-15 TMP91CW18A Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset 6 P76 5 P75 4 P74 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to 1.) Port 7 Control Register 7 P7CR (0016H) Bit symbol Read/Write After reset 0 0 0 6 P76C 5 P75C 4 P74C 3 P73C W 0 0: Input 2 P72C 0 1: Output 1 P71C 0 0 P70C 0 Port 7 I/O setting 0 1 Input Output Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 0 0: Port 1: SCK0 6 P76F W 5 P75F 0 0: Port 1: TB0OUT0 4 3 2 P72F 0 0: Port 1: TA5OUT 1 P71F W 0 0: Port 1: TA3OUT 0 P70F 0 0: Port 1: TA1OUT Note 1: Read-modify-write instructions are prohibited for the registers P7CR and P7FC. Setting P70 as TA1OUT P7FC P7CR Setting P71 as TA3OUT P7FC P7CR Setting P72 as TA5OUT P7FC P7CR Setting P75 as TMRB0 P7FC P7CR Setting P76 as output SCK0 P7FC P7CR IIEC 1 1 0 1 1 1 1 1 1 1 1 Note 2: P73/TB0IN1/INT5, P74/TB0IN/INT6 pin dose not have a register changing port/function. For example, when it is used as an input port, the timer B0 input 0,1 or INT5, INT6 are inputted to 16-bit timer B0. Figure 3.5.24 Port 7 Registers (1/2) 91CW18A-70 2005-08-15 TMP91CW18A Interrupt Enable Control Register 7 IIEC (001CH) Bit symbol Read/Write After reset Function 6 INT3E W 0 0: Port 1: INT3 5 4 INT6E W 0 0: Port 1: INT6 TB0IN1 3 INT5E 0 0: Port 1: INT5 TB0IN0 2 1 0 Note: Read-modify-write instruction is prohibited for the IIEC. Setting P73 as TB0IN0/INT5 input IIEC P7CR IIEC P7CR Setting P76 as INT3 input IIEC P7CR P7FC 1 0 0 1 0 1 0 Setting P74 as TB0IN1/INT6 input Figure 3.5.25 Port 7 Registers (2/2) 91CW18A-71 2005-08-15 TMP91CW18A 3.5.9 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port 8 to be an input port. It also sets all bits in the output latch register P8 to P1.Besides I/O function, each port can be used both as another function port as follows P80, P81 are used both as I/O pin SDA0/SO0, SCL0/SIO of I2C bus/SIO. P82, P83 are used both as I/O pin TXD, RXD of UART. P84 and P85 are used both as I/O pin of SDA1, SCL1 of I2C bus 1. P86, P87 are used both as I/O pin SDA2, SCL2 of I2C bus 2. These functions can be enabled by writing a 1 to the corresponding bits in the port 8 function register (P8FC). And also, when the output is set for each bit, open-drain is selectable by P8ODE. Resetting resets all bits of the registers P8CR and P8FC to 0, and sets all bits to be input port pins. Reset O.D. control (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write SDA0_out/SO0 A S P80 (SDA0/SO0) Selector B SB Selector P8 read SDA0_in A Figure 3.5.26 Port 8 (P80) 91CW18A-72 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write SCL0_out A S P81 (SCL0/SI0) Selector B SB Selector P8 read SCL0_in/SI0 A Figure 3.5.27 Port 8 (P81) 91CW18A-73 2005-08-15 TMP91CW18A Reset O.D. control (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write TXD A S P82 (TXD) Selector B SB Selector P8 read A Figure 3.5.28 Port 8 (P82) 91CW18A-74 2005-08-15 TMP91CW18A Reset O.D. contorl (on bit basis) P8ODE write P8ODE read Direction control (on bit basis) P8CR write Internal data bus S Output latch P8 write P83 (RXD) SB Selector P8 read RXD A Figure 3.5.29 Port 8 (P83) 91CW18A-75 2005-08-15 TMP91CW18A Reset Direction control (on bit basis) P8CR write Function control (on bit basis) Internal data bus P8FC write S Output latch P8 write SDA1_out SCL1_out SDA2_out SCL2_out A S Selector B P84 (SDA1) P85 (SCL1) P86 (SDA2) P87 (SCL2) SB Selector P8 read SDA1_in SCL1_in SDA2_in SCL2_in A Figure 3.5.30 Port 8 (P84 to P87) 91CW18A-76 2005-08-15 TMP91CW18A Port 8 Register 7 P8 Bit symbol (0018H) Read/Write After reset P87 6 P86 5 P85 4 P84 R/W 3 P83 2 P82 1 P81 0 P80 Data from external port (Output latch register is set to 1.) Port 8 Control Register 7 P8CR Bit symbol (001AH) Read/Write After reset Function Note: Read-modify-write instructions are prohibited for registers P8CR, P8FC and P8ODE. P87C 0 6 P86C 0 5 P85C 0 4 P84C W 0 3 P83C 0 2 P82C 0 1 P81C 0 0 P80C 0 0: Input 1: Output Port 8 I/O setting 0 1 Input Output Port 8 Function Register 7 P8FC Bit symbol (001BH) Read/Write After reset Function P87F 0 0: Port 1: SCL2 function 6 P86F W 0 0: Port 1: SDA2 function 5 P85F 0 0: Port 1: SCL1 function 4 P84F 0 0: Port 1: SDA1 function 3 2 P82F 0 0: Port 1 P81F W 0 0: Port function 0 P80F 0 0: Port 1: SDA0 function SO0 output 1: TXD output 1: SCL0 Setting P80 as SDA0/SO0 function P8FC P8CR Setting P81 as SCL0 function P8FC P8CR P8FC P8CR Setting P84 as SDA1 function P8FC P8CR Setting P85 as SCL1 function P8FC P8CR Setting P86 as SDA2 function P8FC P8CR Setting P87as SCL2 function P8FC P8CR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Setting P82 as TXD output function Figure 3.5.31 Port 8 Registers (1/2) 91CW18A-77 2005-08-15 TMP91CW18A Port 8 Open-drain Enable Register 7 P8ODE Bit symbol (002FH) Read/Write After reset Function 6 5 4 3 P83ODE 0 2 P82ODE R/W 0 0: Normal 1 P81ODE 0 1:Open drain 0 P80ODE 0 Setting to open drain 0 1 Normal Open drain Figure 3.5.32 Port 8 Registers (2/2) 91CW18A-78 2005-08-15 TMP91CW18A 3.6 Wait Controller On the TMP91CW18A, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). TMP91CW18A does not have the chip select signal for the specified address area. In using TMP91CW18A, if chip select signal is needed for each memory space, user have to generate chip select signals by making a external circuit (Address decoder circuit) in order to access external ROM/RAM. 4 blocks address areas are defined by memory start address register MSAR0 to MSAR3 and memory address mask register MAMR0 to MAMR3. The wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin which controls these states is the bus wait request pin ( WAIT ). (After this chapter, 4 block address spaces are described as CS0 space, CS1 space, CS2 space and CS3 space.) 3.6.1 Specifying an Address Area The address areas CS0 to CS3 are specified using the memory start address registers (MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3). During each bus cycle, a compare operation is performed to determine whether or not the address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the result of the comparison is a match, it indicates that the corresponding CS area is to be accessed. If so, the bus cycle proceeds according to the settings in the corresponding B0CS to B3CS wait control register. (See 3.6.2 “Wait Control Registers”.) 91CW18A-79 2005-08-15 TMP91CW18A (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The 8 most significant bits (A23 to A16) of the start address should be set in . The 16 least significant bits of the start address (A15 to A0) are fixed to 0. Thus the start address can only be set to lie on a 64-Kbyte boundary, starting from 000000H. Figure 3.6.2 shows the relationship between the value set in the start address register and the start address. Memory Start Address Registers (for areas CS0 to CS3) 7 MSAR0 (00C8H) MSAR2 (00CCH) MSAR1 (00CAH) MSAR3 (00CEH) Bit symbol Read/Write After reset Function 1 1 1 1 S23 6 S22 5 S21 4 S20 R/W 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Address 000000H Start address 64 Kbytes 000000H 010000H 020000H 030000H 040000H 050000H 060000H to FF0000H Value in start address register (MSAR0 to MSAR3) 00H 01H 02H 03H 04H 05H 06H to FFH FFFFFFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91CW18A-80 2005-08-15 TMP91CW18A (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0 to MAMR3) which is set to 1 masks the corresponding bit of the start address which has been set in the corresponding memory start address register (MSAR0 to MSAR3). The compare operation used to determine whether or not a bus address is in one of the areas CS0 to CS3 only compares address bits for which a 0 has been set in the corresponding bit position in the corresponding memory address mask register. Also, the address bits which each memory address mask register can mask vary from register to register; hence, the possible size settings for the areas CS0 to CS3 differ accordingly. Memory Address Mask Register (for CS0 area) 7 6 5 4 3 2 1 0 MAMR0 (00C9H) Bit symbol Read/Write After reset 1 1 1 1 V20 V19 V18 V17 R/W 1 1 1 1 V16 V15 V14 to V9 V8 Function Sets size of CS0 area 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) 7 6 5 4 3 MAMR1 (00CBH) Bit symbol Read/Write After reset 1 1 1 1 V21 V20 V19 V18 R/W 1 V17 2 V16 1 1 V15 to V9 1 0 V8 1 Function Sets size of CS1 area 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 6 5 4 3 MAMR2 (00CDH) MAMR3 (00CFH) Bit symbol Read/Write After reset 1 1 1 1 V22 V21 V20 V19 R/W 1 V18 2 V17 1 1 V16 1 0 V15 1 Function Sets size of CS2 or CS3 area 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91CW18A-81 2005-08-15 TMP91CW18A (3) Setting memory start addresses and address areas Figure 3.6.4 shows an example in which CS0 is specified to be a 64-Kbyte address area starting at 010000H. First, MSAR0, the 8 most significant bits of the start address register and which correspond to the memory start address, are set to 01H. Next, based on the desired CS0 area size, the difference between the start address and the end address (01FFFFH) is calculated. Bits 20 to 8 of this result constitute the mask value for the desired CS0 area size. Setting this value in MAMR0 (Bits 20 to 8 of the memory address mask register) sets the desired area size for CS0. In this example 07H is set in MAMR0, specifying an area size of 64 Kbytes. 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CS0 area size (64 Kbytes) S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H Memory start address V14 to V9 V8 V20 V19 V18 V17 V16 V15 MAMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area A reset sets MSAR0 to MSAR3 and MAMR0 to MAMR3 to FFH. In addition, B0CS, B1CS and B3CS are cleared to 0, disabling the CS0, CS1 and CS3 areas. However, since a reset clears B2CS to 0 and sets B2CS to 1, CS2 is enabled with the address range 002000H to FDFFFFH. When addresses outside the areas specified as CS0 to CS3 are accessed, the bus width and number of waits specified in BEXCS are used. (See 3.6.2 “Wait Control Registers”.) 91CW18A-82 2005-08-15 TMP91CW18A (4) Address area size specification Table 3.6.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A “Δ” indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register. If an area size for a CS area marked “Δ” in the table is to be set, the start address must either be set to 000000H or to a value that is greater than 000000H by an integer multiple of the desired area size. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the lowest-numbered CS area has highest priority (e.g., CS0 has a higher priority than any other area). Example: To set the area size for CS0 to 128 Kbytes: (1) Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. (2) Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.6.1 Valid Area Sizes for Each CS Area Size (Bytes) CS Area CS0 CS1 CS2 CS3 256 ○ ○ 512 ○ ○ 32 K ○ ○ ○ 64 K 128 K 256 K 512 K ○ ○ ○ ○ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ 1M Δ Δ Δ Δ 2M Δ Δ Δ Δ 4M 8M Δ Δ Δ Δ Δ 91CW18A-83 2005-08-15 TMP91CW18A 3.6.2 Wait Control Registers Figure 3.6.5 lists the wait control registers. The master enable/disable, data bus width and number of wait states for each address area (CS0 to CS3 plus any other) are set in the respective wait control registers, B0CS to B3CS or BEXCS. Wait Control Register 7 B0CS Bit symbol B0E (00C0H) Read/Write W Read-modify- After reset 0 write Function 0: Disable instructions 1: Enable are prohibited. 6 5 − 0 Always write 0 4 − 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 1 B0W1 0 100 0 B0W0 0 010: (1 + N) waits 110 111 B1W2 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 Invalid settings B1CS Bit symbol B1E − 0 Always write 0 − 0 B1BUS 0 Data bus width 0: 16 bits 1: 8 bits B1W1 0 B1W0 0 (00C1H) Read/Write W Read-modify- After reset 0 write Function 0: Disable instructions 1: Enable are prohibited. 010: (1 + N) waits 110 111 B2W2 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 Invalid settings B2CS Bit symbol B2E B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area − 0 Always write 0 − W 0 B2BUS 0 Data bus width 0: 16 bits 1: 8 bits B2W1 0 B2W0 0 (00C2H) Read/Write Read-modify- After reset 1 write Functions 0: Disable instructions 1: Enable are prohibited. 010: (1 + N) waits 110 111 B3W2 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 111 101 Invalid settings B3CS Bit symbol B3E − 0 Always write 0 − 0 B3BUS 0 Data bus width 0: 16 bits 1: 8 bits B3W1 0 B3W0 0 (00C3H) Read/Write W Read-modify- After reset 0 write Functions 0: Disable instructions 1: Enable are prohibited. 010: (1 + N) waits 110 BEXW2 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100 101 111 BEXW1 0 Invalid settings BEXCS Bit symbol BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits BEXW0 0 (00C7H) Read/Write Read modify After reset write Functions instructions are prohibited. 010: (1 + N) waits 110 Invalid settings Master enable bit 0 16-Mbyte area 1 CS area enable CS2 area selection 0 1 16-Mbyte area Specified address area Number of address area waits (See 3.6.2 (3) “Wait control”.) Data bus width selection 0 1 16-bit data bus 8-bit data bus Figure 3.6.5 Chip Select/Wait Control Registers 91CW18A-84 2005-08-15 TMP91CW18A (1) Master enable bits Bit7 (, , or ) of the wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables the settings. A reset disables , and (e.g., clears them to 0) and enables (e.g., sets it to 1). Hence after a reset only the CS2 area is enabled. (2) Data bus width selection Bit3 (, , , or ) of a wait control register specifies the width of the data bus. This bit should be clear to 0 when memory is to be accessed using a 16-bit data bus, and to 1 when an 8-bit data bus is to be used. This process of changing the data bus width according to the address being accessed is known as dynamic bus sizing. For details of this bus operation, see Figure 3.6.2. Table 3.6.2 Dynamic Bus Sizing Operand Data Bus Width Operand Start Address 2n + 0 8 bits (Even number) 2n + 1 (Odd number) 2n + 0 (Even number) 16 bits 2n + 1 (Odd number) Memory Data Bus Width 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 2n + 0 (Even number) 8 bits 16 bits 32 bits 8 bits 2n + 1 (Odd number) 16 bits 2n + 2 2n + 4 Input data in bit positions marked xxxxx is ignored during a read. During a write, the bus lines corresponding to these bit positions go high-impedance and the write strobe signal for the bus remains inactive. 91CW18A-85 2005-08-15 TMP91CW18A (3) Wait control Bits 0 to 2 (, , , or ) of a wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits. Bit settings other than those listed in the table should not be made. Table 3.6.3 Wait Operation Settings 000 001 010 Number of Waits 2 waits 1 wait (1 + N) waits Wait Operation Inserts a wait of two states, irrespective of the WAIT pin state. Inserts a wait of one state, irrespective of the WAIT pin state. Inserts one wait state, then continuously samples the state of the WAIT pin. While the WAIT pin remains low, the wait continues; the bus cycle is prolonged until the pin goes high. Ends the bus cycle without a wait, regardless of the WAIT pin state. 011 0 waits A Reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Clearing B2CS (Bit6 of the wait control register for CS2) to 0 designates the 16-Mbyte area 002000H to FDFFFFH as the CS2 area. Setting B2CS to 1 designates the address area specified by the start address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if B2CS = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are). A reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area. (6) Procedure for setting wait control When using the wait control function, set the registers in the following order. (1) Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. (2) Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. (3) Set the wait control registers B0CS to B3CS. Set the data bus width, number of waits and master enable/disable status for CS0 to CS3. If a CS0 to CS3 address is specified which is actually an internal I/O, RAM or ROM area address, the CPU accesses the internal address area. 91CW18A-86 2005-08-15 TMP91CW18A Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H ..............Start address: 010000H MAMR0 = 07H .............Address area: 64 Kbytes B0CS = 83H .................ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled 91CW18A-87 2005-08-15 TMP91CW18A 3.6.3 Connecting External Memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91CW18A. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. External decoder circuit 74AC573 TMP91CW18A A16 to A23 DQ LE CS Address bus DQ ALE AD8 to AD15 LE Upper byte ROM OE CS Lower byte ROM OE CS 8-bit RAM CS 8-bit I/O OE WE OE WE AD0 to AD7 RD WR Figure 3.6.6 Example of External Memory Connection (ROM uses 16-bit bus: RAM and I/O use 8-bit bus.) Since the MCU has no CS pins, user have to make chip select signals by making a external address decoder circuit in order to control external memory area which is decided by memory start address register and memory address mask register. 91CW18A-88 2005-08-15 TMP91CW18A 3.7 8-Bit Timer (TMRA) The TMP91CW18A features eight built-in 8-bit timer. These timers are paired into four modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of two channels and can operate in any of the following four operating modes. • • • • 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) 8-bit programmable square wave pulse generation output mode (PPG – variable duty cycle with variable period) (1 timer) 8-bit pulse width modulation output mode (PWM – variable duty cycle with constant period) (1 timer) Figure 3.7.1 to Figure 3.7.4 show block diagrams for TMRA01, TMRA23, TMRA45 and TMRA67. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (Special function registers). Each of the four modules (TMRA01, TMRA23, TMRA45 and TMRA67) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter is as follows. 3.7.1 3.7.2 3.7.3 3.7.4 Block Diagrams Operation of Each Circuit SFRs Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Setting for each mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for external clock Output pin for timer flip-flop Timer run register Timer register SFR (Address) Timer mode register Timer flip-flop control register TA1OUT (Shared with P70) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TA3OUT (Shared with P71) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TA5OUT (Shared with P72) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) TMRA01 TMRA23 TMRA45 TMRA67 TA6IN (Shared with P35) TA7OUT (Shared with P36) TA67RUN (0118H) TA6REG (011AH) TA7REG (011BH) TA67MOD (011CH) TA7FFCR (011DH) External pin 91CW18A-89 2005-08-15 3.7.1 Prescaler 2 φT1 Timer flip-flop TA1FF Selector φT1 φT4 φT16 8-bit up counter (UC0) overflow Prescaler clock: φT0 4 φT4 φT16 φT256 8 16 32 64 128 256 512 Block Diagrams Run/clear TA01RUN TA01RUN Selector φT1 φT16 φT256 8-bit up counter (UC1) TA01MOD TA01RUN TA1FFCR Timer flip-flop output: TA1OUT 2n Figure 3.7.1 TMRA01 Block Diagram TA01MOD TA01MOD 91CW18A-90 8-bit up counter (CP0) TA01MOD 8-bit timer register TA0REG Match detect TA0TRG TA01RUN Register buffer 0 Internal data bus TMRA0 interrupt output: INTTA0 Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG TMRA0 Internal data bus TMRA1 match output: interrupt output: TA0TRG INTTA1 TMP91CW18A 2005-08-15 Prescaler Prescaler clock: φT0 2 φT1 φT4 φT16 φT256 Timer flip-flop TA3FF Selector Selector φT1 φT16 φT256 TA23MOD φT1 φT4 φT16 8-bit up counter (UC2) TA23MOD 2n overflow TA23MOD TA23RUN TA23RUN 8/fc At prescaler clock = fc Figure 3.10.24 Maximum Data Transfer Frequency when External Clock Input Used 91CW18A-175 2005-08-15 TMP91CW18A 2. Shift edge Data is transmitted on the leading edge of the clock and received on the trailing edge. Leading edge shift Data is shifted on the leading edge of the serial clock (on the falling edge of the SCK pin input/output). Trailing edge shift Data is shifted on the trailing edge of the serial clock (on the rising edge of the SCK pin input/output). SCK pin output SO pin output Shift register Bit0 Bit1 Bit2 Bit3 Bit4 ****7654 Bit5 *****765 Bit6 ******76 Bit7 ******7 76543210 *7654321 **765432 ***76543 (a) Leading edge SCK pin SI pin Shift register *: Don’t care Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 ******** 0******* 10****** 210***** 3210**** 43210*** 543210** 6543210* 76543210 (b) Trailing edge Figure 3.10.25 Shift Edge 91CW18A-176 2005-08-15 TMP91CW18A (2) Transfer modes SBI0CR10 is used to select a transmit, receive or transmit/receive mode. 1. 8-bit transmit mode Set a control register to a transmit mode and write transmission data to SBI0DBR0. After the transmit data has been written, set SBI0CR10 to 1 to start data transfer. The transmitted data is transferred from SBI0DBR0 to the shift register and output, starting with the least significant bit (LSB), via the SO pin and synchronized with the serial clock. When the transmission data has been transferred to the shift register, the SBI0DBR0 becomes empty. An INTSBI0 (Buffer empty) interrupt request is generated to request new data. When the internal clock is used, the serial clock will stop and the automatic wait function will be initiated if new data is not loaded into the data buffer register after the specified 8-bit data has been transmitted. When new transmission data is written, the automatic-wait function is canceled. When an external clock is used, data should be written to SBI0DBR0 before new data is shifted. The transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and a data is written to SBI0DBR0 by the interrupt service program. When the transmission is started, after the SBISR0 goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK. Data transmission ends when is cleared to 0 by the buffer empty interrupt service program or when is set to 1. When is cleared to 0, the transmitted mode ends when all data is output. In order to confirm whether data is being transmitted properly by the program, set SBISR0 (Bit3 of SBISR0) to be sensed. SBISR0 is cleared to 0 when transmission has been completed. When is set to 1, data transmission stops. SBISR0 is then cleared to 0. When an external clock is used, it is also necessary to clear SBISR0 to 0 before new data is shifted; otherwise, dummy data will be transmitted and operation ends. 91CW18A-177 2005-08-15 TMP91CW18A Example: Program to stop data transmission (when an external clock is used) Clear SCK pin (Output) SO pin INTSBI0 interrupt request SBI0DBR0 a b (a) Internal clock Write transmitted data * a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Clear SCK pin (Input) SO pin INTSBI0 interrupt request SBI0DBR0 a b (b) External clock Write transmitted data * a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 Figure 3.10.26 Transfer Mode STEST1: STEST2: BIT JR BIT JR LD 2, (SBISR0) NZ, STEST1 0, (P7) Z, STEST2 (SBI0CR10), 00000111B ; If = 1 then loop. ; If SCK = 0 then loop. ; ← 0. 91CW18A-178 2005-08-15 TMP91CW18A 2. 8-bit receive mode SCK pin SIOF SO pin Bit6 Bit7 tSODH = 3.5/fFPH [s] (min) Figure 3.10.27 Transmitted Data Hold Time at End of Transmission Set the control register to receive mode and set SBI0CR10 to 1 for switching to receive mode. Data is received into the shift register via the SI pin and synchronized with the serial clock, starting from the least significant bit (LSB). When 8-bit data is received, the data is transferred from the shift register to SBI0DBR0. An INTSBI (Buffer full) interrupt request is generated to request that the received data be read. The data is then read from SBI0DBR0 by the interrupt service program. When an internal clock is used, the serial clock will stop and the automatic wait function will be in effect until the received data has been read from SBI0DBR0. When an external clock is used, since shift operation is synchronized with an external clock pulse, the received data should be read from SBI0DBR0 before the next serial clock pulse is input. If the received data is not read, any further data wich is to be received is canceled. The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when the received data is read. Receiving of data ends when is cleared to 0 by the buffer full interrupt service program or is set to 1. If is cleared to 0, received data is transferred to SBI0DBR0 in complete blocks. The received mode ends when the transfer is complete. In order to confirm whether data is being received properly by the program, set SBISR0 to be sensed. is cleared to 0 when receiving has been completed. When it is confirmed that receiving has been completed, the last data is read. When is set to 1, data receiving stops. is cleared to 0. (The received data becomes invalid, therefore no need to read it.) Note: When the transfer mode is changed, the contents of SBI0DBR0 will be lost. If the mode must be changed, conclude data receiving by clearing to 0, read the last data, then change the mode. 91CW18A-179 2005-08-15 TMP91CW18A 3. SCK pin (Output) SI pin INTSBI0 interrupt request SBI0DBR0 a Read receiver data b Read receiver data a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 8-bit transmit/receive mode Clear Figure 3.10.28 Receiver Mode (Example: Internal clock) Set a control register to a transmit/receive mode and write data to SBI0DBR0. After the data has been written, set SBI0CR10 to 1 to start transmitting/receiving. When data is transmitted, the data is output via the SO pin, starting from the least significant bit (LSB) and synchronized with the leading edge of the serial clock signal. When data is received, the data is input via the SI pin on the trailing edge of the serial clock signal. 8-bit data is transferred from the shift register to SBI0DBR0 and an INTSBI0 interrupt request is generated. The interrupt service program reads the received data from the data buffer register and writes the data which is to be transmitted. SBI0DBR0 is used for both transmitting and receiving. Transmitted data should always be written after received data has been read. When an internal clock is used, the automatic wait function will be in effect until the received data has been read and the next data has been written. When an external clock is used since the shift operation is synchronized with the external clock, received data is read and transmitted data is written before a new shift operation is executed. The maximum transfer speed when an external clock is used is determined by the delay time between the time when an interrupt request is generated and the time at which received data is read and transmitted data is written. When the transmit is started after the SBISR0 goes 1 output from the SO pin holds final bit of the last data until falling edge of the SCK. Transmitting/receiving data ends when is cleared to 0 by the INTSBI0 interrupt service program or SBI0CR10 is set to 1. When is cleared to 0, received data is transferred to SBI0DBR0 in complete blocks. The transmit/receive mode ends when the transfer is complete. In order to confirm whether data is being transmitted/received properly by the program, set SBISR0 to be sensed. is set to 0 when transmitting/receiving has been completed. When is set to 1, data transmitting/receiving stops. is then cleared to 0. Note: When the transfer mode is changed, the contents of SBI0DBR0 will be lost. If the mode must be changed, conclude data transmitting/receiving by clearing to 0, read the last data, then change the transfer mode. 91CW18A-180 2005-08-15 TMP91CW18A Clear SCK pin (Output) SO pin SI pin INTSBI0 interrupt request SBI0DBR0 a Write transmitted data (a) Read received data (c) c b Write transmitted data (b) d Read received data (d) * a0 c0 a1 c1 a2 c2 a3 c3 a4 c4 a5 c5 a6 c6 a7 c7 b0 d0 b1 d1 b2 d2 b3 d3 b4 d4 b5 d5 b6 d6 b7 d7 Figure 3.10.29 Transmit/Received Mode (Example: Using internal clock) SCK pin SIOF SO pin Bit6 Bit7 in last transmitted word tSODH = 4/fFPH [s] (Min) Figure 3.10.30 Transmitted Data Hold Time at End of Transmit/Receive 91CW18A-181 2005-08-15 TMP91CW18A 3.11 Serial Bus Interface 1 (I2C bus) The serial bus interface is connected to an external device through P84 (SDA) and P85 (SCL) in the I2C bus mode. Each pin is specified as follows. P8CR I C bus mode 2 P8FC 11 11 3.11.1 Configuration INTI2C1 interrupt request SCL1 P85 (SCL1) φT Divider Transfer control circuit I/O control Noise canceller I C bus clock sysn. + Control 2 Shift register I C bus data control 2 P84 (SDA1) Noise canceller SDA1 SBI0CR21/ SBISR1 SBI control register 2/ SBI status register 2 I2C0AR1 I C bus address register SBI0DBR1 SBI data buffer register SBI0CR11 SBI control register 1 SBI0BR01, 11 SBI baud rate register 0 and 1 Figure 3.11.1 Serial Bus Interface (I2C bus) 91CW18A-182 2005-08-15 TMP91CW18A 3.11.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. • • • • • • • Serial bus interface control register 1 (SBI0CR11) Serial bus interface control register 2 (SBI0CR21) Serial bus interface data buffer register (SBI0DBR1) I2C bus address register (I2C0AR1) Serial bus interface status register (SBISR1) Serial bus interface baud rate register 0 (SBI0BR01) Serial bus interface baud rate register 1 (SBI0BR11) 3.11.3 The Data Formats in The I2C Bus Mode The data formats in the I2C bus mode are shown below. (a) Addressing format 8 bits S Slave address 1 RA /C WK 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K 1 (b) Addressing format (with restart) 8 bits S Slave address 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CS K 8 bits Slave address 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CP K 1 1 (c) Free data format (Data transferred from master device to slave device) 8 bits S Data 1 A C K 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K 1 S: Start condition R/ W : Direction bit ACK: Acknowledge bit P: Stop condition Figure 3.11.2 Data Format in the I2C Bus Mode 91CW18A-183 2005-08-15 TMP91CW18A 3.11.4 I2C Bus Mode Control The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode. Seirial Bus Interface Conrol Register 1 7 SBI0CR11 Bit symbol (0250H) Read/Write After reset Function BC2 6 BC1 W 5 BC0 0 4 ACK R/W 0 Acknowledge mode specification 0: Not generate 1: Generate 3 2 SCK2 W 1 SCK1 0 SCK0/ SWRMON R/W 0 0 Number of transferred bits 0 0 0/1 (Note 3) Internal serial clock selection and software reset monitor (Note 2) Internal serial clock selection at write 000 n = 5 − (Note4) 001 n = 6 − (Note4) System clock: fc 010 n = 7 − (Note4) Clock gear: fc/1 011 n = 8 94.7 kHz fc = 25 MHz 100 n = 9 48.1 kHz (internal SCL output) fc 101 n = 10 24.2 kHz fscl = n [Hz ] 2 +8 110 n = 11 12.2 kHz 111 (Reserved) Software reset state monitor at read 0 1 0 1 During software reset Initial data Not generate clock pulse for acknowledge signal Generate clock pulse for acknowledge signal = 0 Number of Bits clock pulses 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 = 1 Number of Bits clock pulses 9 8 2 1 3 2 4 3 5 4 6 5 7 6 8 7 Acknowledge mode specification Number of bits transferred 000 001 010 011 100 101 110 111 Note 1: Note 2: Note 3: Note 4: Read-modify-write instruction is prohibited for SBI0CR11. For the frequency of the SCL line clock, See 3.11.5 (3) Serial clock. Initial data of SCK0 is 0, SWRMON is 1. This I C bus circuit does not support Fast mode, it supports standard mode only. Although the I C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I C specification is not guaranteed in that case. 2 2 2 Figure 3.11.3 Registers for the I2C Bus Mode 91CW18A-184 2005-08-15 TMP91CW18A Serial Bus Interface Control Register 21 7 SBI0CR21 Bit symbol (0253H) Read/Write After reset Function MST 0 6 TRX W 0 5 BB 0 Start/stop condition generation 4 PIN 1 Cancel INTI2C1 interrupt request 3 SBIM1 0 W (Note 2) 2 SBIM0 0 1 SWRST1 0 W (Note 2) 0 SWRST0 0 Master/slave Transmitter/ selection receiver selection Serial bus interface operating mode selection. (Note 2) 00: Port mode 01: (Reserved) 10: I2C bus mode 11: (Reserved) Software reset generate write 10 and 01, then an internal reset signal is generated. Serial bus interface operating mode selection (Note 3) 00 Port mode (Serial bus interface output disabled) 01 (Reserved) 2 10 I C bus mode 11 (Reserved) INTI2C1 interrupt request 0 1 Don’t care Cancel interrupt request Start/stop condition generation 0 1 Generates the stop condition Generates the start condition Transmitter/receiver selection 0 1 Receiver Transmitter Master/slave selection 0 1 Slave Master Note 1: Note 2: Note 3: Read-modify-write instruction is prohibited for SBI0CR21. Reading this register function as SBISR1. Switch a mode to port mode after confirming that the bus is free. Switch a mode between I C bus mode and clock synchronous 8-bit SIO mode after confirming that input signals via port are high level. 2 Figure 3.11.4 Registers for the I2C Bus Mode 91CW18A-185 2005-08-15 TMP91CW18A Serial Bus Interface Status Register 1 7 SBISR1 (0253H) Bit symbol Read/Write After reset Function 0 Master/ slave status monitor 0 0 2 Transmitter/ I C bus status receiver monitor status monitor 1 INTI2C1 interrupt request monitor MST 6 TRX 5 BB 4 PIN R 3 AL 0 Arbitration lost detection monitor 0: − 1: Detected 2 AAS 0 Slave address match detection monitor 1 AD0 0 GENERAL CALL detection monitor 0 LRB 0 Last received bit monitor 0: 0 0: Undetected 1: 1 0: Undetected 1: Detected 1: Detected Last received bit monitor 0 1 Last received bit was 0 Last received bit was 1 GENERAL CALL detection monitor 0 1 Undetected GENERAL CALL detected Slave address match detection monitor 0 1 Undetected Slave address match or GENERAL CALL detected Arbitration lost detection monitor 0 1 － Arbitration lost INTI2C1 interrupt request monitor 0 1 2 Interrupt requested Interrupt canceled I C bus status monitor 0 1 Free or waiting free Busy Transmitter/receiver status monitor 0 1 Receiver Transmitter Master/slave status monitor 0 1 Note 1: Note 2: Read-modify-write instruction is prohibited for SBISR1. Writing in this register functions as SBI0CR21. Slave Master Figure 3.11.5 Registers for the I2C Bus Mode 91CW18A-186 2005-08-15 TMP91CW18A Serial Bus Interface Baud Rate Register 0 7 SBI0BR01 Bit symbol − W 0 Always write 0 (0254H) Read/Write Read-modify- After reset write Function instructions are prohibited. Operation during IDLE2 mode 0 1 Stop Operation 6 I2SBI0 R/W 0 IDLE2 0: Stop 1: Run 5 4 3 2 1 0 Serial Bus Interface Baud Rate Register 1 7 SBI0BR11 (0255H) Bit symbol Read/Write P4EN W 6 − W 5 4 3 2 1 0 Read-modify- After reset write Function instructions are prohibited. 0 0 Internal Always clock write 0 0: Stop 1: Operate Baud rate clock control 0 1 Stop Operation Sirial Bus Interface Data Buffer Register 7 SBI0DBR1 (0251H) Bit symbol Read/Write After reset Note 1: Note 2: Note 3: Note 4: DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (Received)/W (Transfer) Undefined Read-modify-write instruction is prohibited for SBI0DBR1. When writing transmited data, start from the MSB (Bit7). Receiving data is placed from LSB (Bit0). SBI0DBR1 can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is prohibited. Written data in SBI0DBR1 is cleared by INTI2C1 signal. 7 I2C0AR1 (0252H) Bit symbol Read/Write After reset Function 0 SA6 I2C Bus Address Register 6 5 4 3 SA5 0 SA4 0 SA3 W 0 0 SA2 2 SA1 0 1 SA0 0 0 ALS 0 Address recognition mode specification Slave address selection for when device is operating as slave device. Address recognition mode specification 0 Note: Read-modify-write instruction is prohibited for I2C0AR1. 1 Slave address recognition Non slave address recognition Figure 3.11.6 Registers for the I2C Bus Mode 91CW18A-187 2005-08-15 TMP91CW18A 3.11.5 Control in I2C Bus Mode (1) Specifying acknowledge mode Set the SBI0CR11 to 1 for operation in the acknowledge mode. The TMP91CW18A generates an additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low in order to generate the acknowledge signal. Clear the to 0 for operation in the non-acknowledge mode, the TMP91CW18A does not generate a clock pulse for the acknowledge signal when operating in the master mode. (2) Number of transfer bits The SBI0CR11 is used to select a number of bits for next transmitting and receiving data. Since SBI0CR11 is cleared to 000 on start-up, a slave address and direction bit transmissions are executed in 8 bits. Other than these, the retains a specified value. (3) Serial clock 1. Clock source SBI0CR11 is used to specify the maximum transfer frequency for output on the SCL pin in master mode. Set a communication baud rate that meets the I2C bus specification, such as the shortest pulse width of tLOW, based on the equations shown below. tHIGH tLOW 1/fscl SBI0CR11 tLOW = 2 n−1 n 5 6 7 8 9 10 11 SBI tHIGH = 2 n−1 /fSBI + 8/fSBI fscl = 1/(tLow + tHIGH) fSBI = 2n + 8 000 001 010 011 100 101 110 Note 1: fSBI is the clock fFPH. Note 2: fSBI is the clock either fc/16 or fFPH which is selected SYSCR0 Figure 3.11.7 Clock Source 91CW18A-188 2005-08-15 TMP91CW18A 2. Clock synchronization In the I2C bus mode in order to wired-AND a bus, a master device which pulls down a clock line to low level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure. The TMP91CW18A has a clock synchronization function which allows normal data transfer even when more than one master exists on the bus. The following example explains the clock synchronization procedures used when there are two masters present on the bus. Wait counting high-level width of a clock pulse. Start couting high-level width of a clock pulse. Internal SCL output (Master A) Internal SCL output (Master B) SCL line a b c Reset a acounter of high-level width of a clock pulse. Figure 3.11.8 Clock Synchronization When master A pulls the internal SCL output low at point a, the bus’s SCL line goes low. After detecting this, master B resets a counter of high-level width of an own clock pulse and sets the internal SCL output low. Master A finishes counting low level width of an own clock pulse at point b and sets the internal SCL output high. Since master B is holding the bus’s SCL line low, master A waits for counting high level width of an own clock pulse. After master B has finished counting low level width of an own clock pulse at point c and master A detects the SCL line of the bus at the high level, and starts counting high level of an own clock pulse. The clock pulse on the bus is determined by the master device with the shortest high level width and the master device with the longest low-level width from among those master devices connected to the bus. (4) Slave address and address recognition mode specification When the TMP91CW18A is to be used as a slave device, set the slave address and in I2C0AR1. Clear to 0 for the address recognition mode. (5) Master/Slave selection To operate the TMP91CW18A as a master device set SBI0CR21 to 1. To operate it as a slave device clear SBI0CR21 to 0. SBI0CR21 is cleared to 0 in hardware when a stop condition is detected on the bus or when arbitration is lost. 91CW18A-189 2005-08-15 TMP91CW18A (6) Transmitter/receiver selection To operate the TMP91CW18A as a transmitter set SBI0CR21 to 1. To operate it as a receiver clear SBI0CR21 to 0. When data with an addressing format is transferred in slave mode, when a slave address with the same value that an I2C0AR1 or a GENERAL CALL is received (All 8-bit data are 0 after a start condition), SBI0CR21 is set to 1 in hardware if the direction bit (R/ W ) sent from the master device is 1, and is cleared to 0 in hardware if the bit is 0. In master mode, when an acknowledge signal is returned from the slave device, SBI0CR21 is cleared to 0 in hardware if the value of the transmitted direction bit is 1, and is set to 1 in hardware if the value of the bit is 0. If an acknowledge signal is not returned, the current state is maintained. SBI0CR21 is cleared to 0 in hardware when a stop condition is detected on the I2C bus or when arbitration is lost. (7) Start/stop condition generation When SBISR1 = 0, slave address and direction bit which are set in SBI0DBR1 are output on the bus after generating a start condition by writing 1 to the SBI0CR21. It is necessary to set transmitted data to the data buffer register (SBI0DBR1) and set 1 to beforehand. SCL line SDA line Start condition 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/ W 9 Slave address and the direction bit Acknowledge signal Figure 3.11.9 Start Condition Generation and Slave Address Generation When SBISR1 = 1, the sequence for generating a stop condition can be initiated by writing 1s to SBISR1 and writing 0 to SBISR1. Do not modify the contents of SBISR1 until a stop condition has been generated on the bus. SCL line SDA line Stop condition Figure 3.11.10 Stop Condition Generation The state of the bus can be ascertained by reading the contents of SBISR1. SBISR1 will be set to 1 if a start condition has been detected on the bus, and will be cleared to 0 if a stop condition has been detected. Refere to chapter 3.11.6 (4) “Stop condition generation”, where the restriction for the stop-condition in the master-mode is explained. 91CW18A-190 2005-08-15 TMP91CW18A (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTI2C1) is generated, SBI0CR21 is cleared to 0. The SCL line is pulled low while SBI0CR21 = 0. SBI0CR21 is cleared to 0 when a single word of data is transmitted or received. Either writing data to or reading data from SBI0DBR1 sets SBI0CR21 to 1. The time from SBI0CR21 being set to 1 until the release of the SCL line is tLOW. In address recognition mode (e.g., when SBI0CR21 = 0), SBI0CR21 is cleared to 0 when the slave address matches the value set in I2C0AR1 or when a GENERAL CALL is received (All 8-bit data are 0 after a start condition). Although SBI0CR21 can be set to 1 by a program, writing 0 to SBI0CR21 does not clear it to 0. (9) Serial bus interface operation mode selection SBI0CR21 is used to specify the serial bus interface operation mode. Set SBI0CR21 to 10 when the device is to be used in I2C bus mode after confirming pin condition of serial bus interface to H. Switch a mode to port after confirming a bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on the bus in I2C bus mode, a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data. Data on the SDA line is used for I2C bus arbitration. The following example illustrates the bus arbitration procedure when there are two master devices on the bus. Master A and master B output the same data until point a. After master A outputs L and master B, H, the SDA line of the bus is wire-AND and the SDA line is pulled low by master A. When the bus’s SCL line is pulled up at point b, the slave device reads the data on the SDA line, that is, data in master A. Data transmitted from master B becomes invalid. The master B state is known as arbitration lost. A master B device which loses arbitration releases the internal SDA output in order not to affect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word. SCL line Internal SDA output (Master A) Internal SDA output (Master B) SDA line a b Internal SDA output becomes 1 after arbitration has been lost. Figure 3.11.11 Arbitration Lost 91CW18A-191 2005-08-15 TMP91CW18A The TMP91CW18A compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBISR1 is set to 1. When SBISR1 is set to 1, SBISR1 are cleared to 00 and the mode is switched to slave receiver mode. Thus, clock output is stopped in data transfer after setting = 1. SBISR1 is cleared to 0 when data is written to or read from SBI0DBR1, when data is written to SBI0CR21. Internal SCL output Internal SDA output Internal SCL output Internal SDA output Accessed to SBI0DBR1 or SBI0CR21 1 D7A 2 D6A 3 D5A 4 D4A 5 D3A 6 D2A 7 D1A 8 D0A 9 1 2 3 4 Master A D7A’ D6A’ D5A’ D4A’ Stop the clock pulse. 1 D7B 2 D6B 3 4 Master B Keep internal SDA output to high-level as losing arbitration. Figure 3.11.12 Example of when TMP91CW18A is a Master Device B (D7A = D7B, D6A = D6B) (11) Slave address match detection monitor SBISR1 is set to 1 in slave mode, in address recognition mode (e.g., when I2C0AR1 = 0), when a GENERAL CALL is received or a slave address matches the value set in I2C0AR1. When I2C0AR1 = 1, SBISR1 is set to 1 after the first word of data has been received. SBISR1 is cleared to 0 when data is written to or read from the data buffer register SBI0DBR1. (12) GENERAL CALL detection monitor SBISR1 is set to 1 in slave mode, when a GENERAL CALL is received (All 8-bit received data is 0 after a start condition.) SBISR1 is cleared to 0 when a start condition or stop condition is detected on the bus. (13) Last received bit monitor The value on the SDA line detected on the rising edge of the SCL line is stored in SBISR1. In acknowledge mode, immediately after an INTI2C1 interrupt request has been generated, an acknowledge signal is read by reading the contents of SBISR1. 91CW18A-192 2005-08-15 TMP91CW18A (14) Software reset function The software reset function is used to initialize the SBI circuit, when SBI is locked by external noises, etc. An internal reset signal pulse can be generated by setting SBI0CR21 to 10 and 01. This initializes the SBI circuit internally. All command except SBI0CR21 registers and status registers are initialized as well. SBI0CR11 is automatically set to “1” after the SBI circuit has been initialized. (15) Serial bus interface data buffer register (SBI0DBR1) Received data can be read by reading SBI0DBR1 and transferred data can be written by writing to SBI0DBR1. When the start condition has been generated in master mode, the slave address and the direction bit are set in this register. (16) I2C bus address register (I2C0AR1) I2C0AR1 is used to set the slave address when the TMP91CW18A functions as a slave device. If the slave address output from the master device is recognized as matching the TMP91CW18A’s slave address, I2C0AR1 is cleared to 0. The data format is the addressing format. When the slave address output from the master does not match the TMP91CW18A’s slave address, I2C0AR1 is set to 1 and the data format is the free data format. (17) Baud rate register (SBI0BR11) Write 1 to SBI0BR11 before operation commences. (18) Setting register for IDLE2 mode operation (SBI0BR01) The setting of SBI0BR01 determines whether the device is operating or is stopped in IDLE2 mode. Hence, must be set before a HALT instruction is executed. 91CW18A-193 2005-08-15 TMP91CW18A 3.11.6 Data Transfer in I2C Bus Mode (1) Device initialization Set SBI0BR11 and SBI0CR11 to 1. Set SBI0BR11 to 1 and clear bits 7, 6, 5 and 3 of SBI0CR1 to 0. Set a slave address in I2C0AR1 and I2C0AR. (I2C0AR = 0 when an addressing format.) For specifying the default setting to a slave receiver mode, clear the to 0 and set the to 1, the to 10. (2) Start condition generation and slave address generation 1. Master mode In master mode, the start condition and the slave address are generated as follows. Check a bus free status (when = 0). Set SBI0CR11 to 1 (Acknowledge mode) and specify a slave address and a direction bit to be transmitted to the SBI0DBR1. If SBI0CR11 = 0, the start condition is generated by writing 1111 to SBI0CR21. Subsequently to the start condition, 9 clocks are output from the SCL pin. While 8 clocks are output, the slave address and the direction bit which are set to the SBI0DBR1. On the 9th clock pulse the SDA line is released and the acknowledge signal is received from the slave device. An INTI2C1 interrupt request occurs on the falling edge of the 9th clock pulse. SBI0CR21 is cleared to 0. In master mode the SCL pin is pulled low while SBI0CR21 is 0. When an interrupt request occurs, the value of SBI0CR21 is changed according to the direction bit setting only if the slave device returns an acknowledge signal. 2. Slave mode In slave mode the start condition and the slave address are received. After the start condition has been received from the master device, while 8 clocks are output from the SCL pin, the slave address and the direction bit which are output from the master device are received. When a GENERAL CALL or an address matching the slave address set in I2C0AR1 is received, the SDA line is pulled down low on the 9th clock pulse and an acknowledge signal is output. An INTI2C1 interrupt request occurs on the falling edge of the 9th clock pulse. SBI0CR21 is cleared to 0. In slave mode the SCL line is pulled low while SBI0CR21 = 0. When an interrupt request occurs, the value of SBI0CR21 is changed according to the direction bit setting only if the slave device returns an acknowledge signal. SCL SDA 1 A6 Start condition INTI2C1 interrupt request 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/ W 9 ACK Acknowledge signal from a slave device. Slave address + Direction bit. Output of master Output of slave Figure 3.11.13 Start Condition Generation and Slave Address Transfer 91CW18A-194 2005-08-15 TMP91CW18A (3) Single word data transfer Check the setting using an INTI2C1 interrupt process after the transfer of each word of data is completed and determine whether the device is in master mode or slave mode. 1. If = 1 (Master mode) Check the setting and determine whether the device is in transmitter mode or receiver mode. If = 1 (Transmitter mode) Check the setting. If = 1, there is no receiver requesting data. Implement the process for generating a stop condition (See section 3.10.6 (4)) and terminate data transfer. If = 0, the receiver is requesting new data. When the next transmitted data is 8 bits, write the transmitted data to SBI0DBR1. When the next transmitted data is other than 8 bits, set to 1, set to 1 and write the transmitted data to SBI0DBR1. After the data has been written, is set to 1, a serial clock pulse is generated to trigger transfer of the next word of data via the SCL pin, and the word is transmitted. After the data has been transmitted, INTI2C1 interrupt request is generated. is cleared to 0 and the SCL line is pulled low. If the length of the data to be transferred is greater than one word, repeat the latter steps of the procedure, starting from the check of the setting. Write to SBI0DBR1 SCL line SDA line INTI2C1 interrupt request 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK Acknowledge signal from a receive. Output from master Output from slave Figure 3.11.14 Example in which = 000 and = 1 in Transmitter Mode 91CW18A-195 2005-08-15 TMP91CW18A If = 0 (Receiver mode) When the next transmitted data is other than 8 bits, set again. Set to 1 and read the received data from SBI0DBR1 so as to release the SCL line (the value of data which is read immediately after a slave address is sent is undefined). After the data has been read, is set to 1. Serial clock pulse for transfering new 1 word of data is defined SCL and outputs “L” level from SDA pin with acknowledge timing. An INTI2C1 interrupt request is then generated and is cleared to 0. The TMP91CW18A then pulls the SCL pin low. From then on the TMP91CW18A outputs a clock pulse, so as to transfer a data word, and an acknowledge signal each time received data is read from SBI0DBR1. Read SBI0DBR1 SCL SDA 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK New D7 Acknowledge signal to a transmitter. INTI2C1 interrupt request Output from master Output from slave Figure 3.11.15 Example of when = 000, = 1 in Receiver Mode In order to terminate the transmission of data to a transmitter, clear to 0 before reading data which is 1 word before the last data to be received. The last data word does not generate a clock pulse as the acknowledge signal. After the data has been transmitted and an interrupt request has been generated, set to 001 and read the data. The TMP91CW18A generates a clock pulse for a 1-bit data transfer. Since the master device is a receiver, the SDA line on the bus remains high. The transmitter interprets the high signal as an ACK signal. The receiver indicates to the transmitter that data transfer is complete. After the 1 data bit has been received and an interrupt request been generated, the TMP91CW18A generates a stop condition (See section 3.10.6 (4)) and terminates data transfer. SCL line 9 SDA line 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 1 Acknowledge signal sent to a transmitter. INTI2C1 interrupt request Read SBI0DBR1 after is cleared to 0. Output of master Output of slave Read SBI0DBR1 after are set to 001. Figure 3.11.16 Termination of Data Transfer in Master Receiver Mode 91CW18A-196 2005-08-15 TMP91CW18A 2. If = 0 (Slave mode) In slave mode the TMP91CW18A operates either in normal slave mode or in slave mode after losing arbitration. In slave mode an INTI2C1 interrupt request is generated when the TMP91CW18A receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or when a matching slave address is received. The TMP91CW18A will enter slave mode from master mode if it loses arbitration. An INTI2C1 interrupt request is generated when a word data transfer terminates after arbitration has been lost. When an INTI2C1 interrupt request is generated, is cleared to 0 and the SCL pin is pulled low. Either reading data to or writing data from SBI0DBR1, or setting to 1 will release the SCL pin after tLOW. Check the SBISR1, , and and implements processes according to conditions listed in the next table. Table 3.11.1 Operation in the Slave Mode 1 1 1 0 Conditions Process The TMP91CW18A loses arbitration Set the number of bits a word in when transmitting a slave address and and write the transmitted data receives a slave address for which the to SBI0DBR1. value of the direction bit sent from another master is 1. In slave receiver mode the TMP91CW18A receives a slave address for which the value of the direction bit sent from the master is 1. In slave transmitter mode a single word of is transmitted. Set to the number of bits in a word. Check the setting. If is set to 1, set to 1 since the receiver win no request the data which follows. Then, clear to 0 to release the bus. If is cleared to 0 of and write the transmitted data to SBI0DBR1 since the receiver requests next data. 0 1 0 0 0 0 1 1 1/0 The TMP91CW18A loses arbitration Read the SBI0DBR1 for setting the when transmitting a slave address and to 1 (Reading dummy data) or set receives a slave address or GENERAL the to 1. CALL for which the value of the direction bit sent from another master is 0. The TMP91CW18A loses arbitration when transmitting a slave address or data and terminates word data transfer. In slave receiver mode the TMP91CW18A receives a slave address or GENERAL CALL for which the value of the direction bit sent from the master is 0. In slave receiver mode the TMP91CW18A terminates receiving word data. Set to the number of bits in a word and read the received data from SBI0DBR1. 0 0 0 1 1/0 0 1/0 91CW18A-197 2005-08-15 TMP91CW18A (4) Stop condition generation When SBISR1 = 1, the sequence for generating a stop condition start by writing 1 to SBI0CR21 and “0” to SBI0CR21. Do not modify the contents of SBI0CR21 until a stop condition has been generated on the bus. When the bus’s SCL line has been pulled low by another device, the TMP91CW18A generates a stop condition when the other device has released the SCL line and SDA pin rising. When SBI0CR21 are written 1 and is written 0 (Generate stop condition in master mode), changes to 0 by internal SCL changes to 1, without waiting stop condition. To check whether SCL and SDA pin are 1 by sensing their ports is needed to detect bus free condition. 1 → 1 → 0 → 1 → Internal SCL SCL pin Stop condition SDA pin (Read) Figure 3.11.17 Stop Condition Generation (Single master) 1 → 1 → 0 → 1 → Internal SCL SCL pin The case of pulled low by another device. Stop condition SDA pin (Read) Figure 3.11.18 Stop Condition Generation (Multi master) 91CW18A-198 2005-08-15 TMP91CW18A (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when the TMP91CW18A is in master mode. Clear SBI0CR21 to 0 and set SBI0CR21 to 1 to release the bus. The SDA line remains high and the SCL pin is released. Since a stop condition has not been generated on the bus, other devices assume the bus to be in busy state. And confirm SCL pin, that SCL pin is released and become bus-free state by SBISR1 = 0 or signal level 1 of SCL pin in port mode. Check the until it becomes 1 to check that the SCL line on a bus is not pulled down to the low-level by other devices. After confirming that the bus remains in a free state, generate a start condition using the procedure described in (2). In order to satisfy the setup time requirements when restarting, take at least 4.7 μs of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition. 0 → 0 → 0 → 1 → 1 → 1 → 1 → 1 → 4.7 [μs] (Min) SCL (Bus) SCL pin SDA pin 9 Start condition Figure 3.11.19 Timing Diagram for TMP91CW18A Restart 91CW18A-199 2005-08-15 TMP91CW18A 3.12 Serial Bus Interface 2 (I2C bus 2) The serial bus interface is connected to an external device through P86 (SDA) and P87 (SCL) in the I2C bus mode. Each pin is specified as follows. P8CR I C bus mode 2 P8FC 11 11 3.12.1 Configuration INTI2C2 interrupt request SCL2 P87 (SCL2) φT Divider Transfer control circuit I/O control Noise canceller I C bus clock sysn. + control 2 Shift register I C bus data control 2 P86 (SDA2) Noise canceller SDA2 SBI0CR22/ SBISR2 SBI control register 2/ SBI status register 2 I2C0AR2 I C bus address register SBI0DBR2 SBI data buffer register SBI0CR12 SBI control register 1 SBI0BR02, 12 SBI baud rate register 0 and 1 Figure 3.12.1 Serial Bus Interface (I2C bus) 91CW18A-200 2005-08-15 TMP91CW18A 3.12.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface control register 1 (SBI0CR12) • • • • • • Serial bus interface control register 2 (SBI0CR22) Serial bus interface data buffer register (SBI0DBR2) I2C bus address register (I2C0AR2) Serial bus interface status register (SBISR2) Serial bus interface baud rate register 0 (SBI0BR02) Serial bus interface baud rate register 1 (SBI0BR12) 3.12.3 The Data Formats in the I2C Bus Mode The data formats in the I2C bus mode are shown below. (a) Addressing format 8 bits S Slave address 1 RA /C WK 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K 1 (b) Addressing format (with restart) 8 bits S Slave address 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CS K 8 bits Slave address 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CP K 1 1 (c) Free data format (Data transferred from master device to slave device) 8 bits S Data 1 A C K 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K 1 S: Start condition R/ W : Direction bit ACK: Acknowledge bit P: Stop condition Figure 3.12.2 Data Format in the I2C Bus Mode 91CW18A-201 2005-08-15 TMP91CW18A 3.12.4 I2C Bus Mode Control The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I2C bus mode. Seirial Bus Interface Control Register 12 7 SBI0CR12 Bit symbol (0258H) Read/Write After reset Function BC2 6 BC1 W 5 BC0 0 4 ACK R/W 0 Acknowledge mode specification 0: Not generate 1: Generate 3 2 SCK2 W 1 SCK1 0 SCK0/ SWRMON R/W 0 0 Number of transferred bits 0 0 0/1 (Note 3) Internal serial clock selection and software reset monitor (Note 2) Internal serial clock selection at write 000 n = 5 − (Note4) 001 n = 6 − (Note4) System clock: fc 010 n = 7 − (Note4) Clock gear: fc/1 011 n = 8 94.7 kHz fc = 25 MHz 100 n = 9 48.1 kHz (internal SCL output) 101 n = 10 24.2 kHz fscl = nfc [ Hz ] 2 +8 110 n = 11 12.2 kHz 111 (Reserved) Software reset state monitor at read 0 1 During software reset Initial Data Acknowledge mode specification 0 1 Not generate clock pulse for acknowledge signal Generate clock pulse for acknowledge signal Number of bits transferred 000 001 010 011 100 101 110 111 = 0 Number of Bits clock pulses 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 = 1 Number of Bits clock pulses 9 8 2 1 3 2 4 3 5 4 6 5 7 6 8 7 Note 1: Note 2: Note 3: Note 4: Read-modify-write instruction is prohibited for SBI0CR12. For the frequency of the SCL line clock, See 3.12.5 (3) Serial clock. Initial data of SCK0 is 0, SWRMON is 1. This I C bus circuit does not support Fast mode, it supports standard mode only. Although the I C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I C specification is not guaranteed in that case. 2 2 2 Figure 3.12.3 Registers for the I2C Bus Mode (1/4) 91CW18A-202 2005-08-15 TMP91CW18A Serial Bus Interface Control Register 2 7 SBI0CR22 Bit symbol (025BH) Read/Write After reset Function MST 0 6 TRX W 0 5 BB 0 Start/stop condition generation 4 PIN 1 Cancel INTI2C2 interrupt request 3 SBIM1 0 W (Note 2) 2 SBIM0 0 1 SWRST1 0 W (Note 2) 0 SWRST0 0 Master/slave Transmitter/ selection receiver selection Serial bus interface operating mode selection (Note 3) 00: Port mode 01: (Reserved) 10: I2C bus mode 11: (Reserved) Software reset generate write 10 and 01, then an internal reset signal is generated. Serial bus interface operating mode selection (Note 3) 00 Port mode (Serial bus interface output disabled) 01 (Reserved) 2 10 I C bus mode 11 (Reserved) INTI2C2 interrupt request 0 1 Don’t care Cancel interrupt request Start/stop condition generation 0 1 Generates the stop condition Generates the start condition Transmitter/receiver selection 0 1 Receiver Transmitter Master/slave selection 0 1 Slave Master Note 1: Note 2: Note 3: Read-modify-write instruction is prohibited for SBI0CR22. Reading this register function as SBISR2 register. Switch a mode to port mode after confirming that the bus is free. Switch a mode between I C bus mode and clock synchronous 8-bit SIO mode after confirming that input signals via port are high level. 2 Figure 3.12.4 Registers for the I2C Bus Mode (2/4) 91CW18A-203 2005-08-15 TMP91CW18A Serial Bus Interface Status Register 7 SBISR2 (025BH) Bit symbol Read/Write After reset Function 0 Master/ slave status monitor 0 0 Transmitter/ I2C bus status receiver monitor status monitor 1 INTI2C2 interrupt request monitor MST 6 TRX 5 BB 4 PIN R 3 AL 0 Arbitration lost detection monitor 0: − 1: Detected 2 AAS 0 Slave address match detection monitor 1 AD0 0 GENERAL CALL detection monitor 0 LRB 0 Last received bit monitor 0: 0 0: Undetected 1: 1 0: Undetected 1: Detected 1: Detected Last received bit monitor 0 1 Last received bit was 0 Last received bit was 1 GENERAL CALL detection monitor 0 1 Undetected GENERAL CALL detected Slave address match detection monitor 0 1 Undetected Slave address match or GENERAL CALL detected Arbitration lost detection monitor 0 1 − Arbitration lost INTI2C2 interrupt request monitor 0 1 Interrupt requested Interrupt canceled I2C bus status monitor 0 1 Free or waiting free Busy Transmitter/receiver status monitor 0 1 Receiver Transmitter Master/slave status monitor 0 1 Note 1: Note 2: Read-modify-write instruction is prohibited for SBISR2. Writing in this register functions as SBI0CR22. Slave Master Figure 3.12.5 Registers for the I2C Bus Mode (3/4) 91CW18A-204 2005-08-15 TMP91CW18A Serial Bus Interface Baud Rate Register 02 7 SBI0BR02 (025CH) Bit symbol Read/Write − W 0 Always write 0 6 I2SBI0 R/W 0 IDLE2 0: Stop 1: Run 5 4 3 2 1 0 Read-modify- After reset write Function instructions are prohibited. Operation during IDLE2 mode 0 1 Stop Run Serial Bus Interface Baud Rate Register 12 7 SBI0BR12 (025DH) Bit symbol Read/Write P4EN W 0 Internal clock 0: Stop 1: Run Baud rate clock control 0 1 Stop Run 6 − W 0 Always write 0 5 4 3 2 1 0 Read-modify- After reset write Function instructions are prohibited. Sirial Bus Interface Data Buffer Register 2 7 SBI0DBR2 (0259H) Bit symbol Read/Write DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (Received)/W (Transfer) Read-modify- After reset Undefined write Note 1: When writing transmitted data, start from the MSB (Bit7). Receiving data is placed from LSB (Bit0). instruction is Note 2: SBI0DBR2 can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is prohibited. prohibited. Note 3: Written data in SBI0DBR2 is cleared by INTI2C2 signal. I2C Bus Address Register 2 7 I2C0AR2 Bit symbol SA6 0 (0254H) Read/Write Read-modify- After reset write Function instruction is prohibited. 6 SA5 0 5 SA4 0 4 SA3 W 0 3 SA2 0 2 SA1 0 1 SA0 0 0 ALS 0 Address recognition mode specification Slave address selection for when dePvice is operating as slave device. Address recognition mode specification 0 1 Slave address recognition Non-slave address recognition Figure 3.12.6 Registers for the I2C Bus Mode (4/4) 91CW18A-205 2005-08-15 TMP91CW18A 3.12.5 Control in I2C Bus Mode (1) Specifying acknowledge mode Set the SBI0CR12 to 1 for operation in the acknowledge mode. The TMP91CW18A generates an additional clock pulse for an acknowledge signal when operating in master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low in order to generate the acknowledge signal. Clear the to 0 for operation in the non-acknowledge mode, the TMP91CW18A does not generate a clock pulse for the acknowledge signal when operating in the master mode. (2) Number of transfer bits SBI0CR12 is used to select a number of bits for next transmitting and receiving data. Since SBI0CR12 is cleared to 000 on start-up, a slave address and direction bit transmissions are executed in 8 bits. Other than these, the retains a specified value. (3) Serial clock 1. Clock source SBI0CR12 is used to specify the maximum transfer frequency for output on the SCL pin in master mode. Set a communication baud rate that meets the I2C bus specification, such as the shortest pulse width of tLOW, based on the equations shown below. tHIGH tLOW 1/fscl SBI0CR12 tLOW = 2 n−1 n 5 6 7 8 9 10 11 /fSBI /fSBI + 8/fSBI tHIGH = 2 n−1 fscl = 1/(tLow + tHIGH) fSBI = 2n + 8 000 001 010 011 100 101 110 Note 1: fSBI is the clock fFPH. Note 2: fSBI is the clock either fc/16 or fFPH which is selected SYSCR0. Figure 3.12.7 Clock Source 91CW18A-206 2005-08-15 TMP91CW18A 2. Clock synchronization In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure. The TMP91CW18A has a clock synchronization function which allows normal data transfer even when more than one master exists on the bus. The following example explains the clock synchronization procedures used when there are two masters present on the bus. Wait counting high-level width of a clock pulse. Start couting high-level width of a clock pulse. Reset a acounter of high-level width of a clock pulse. Internal SCL output (Master A) Internal SCL output (Master B) SCL line a b c Figure 3.12.8 Clock Synchronization When master A pulls the internal SCL output low at point a, the bus’s SCL line goes low. After detecting this, master B resets a counter of high-level width of an own clock pulse and sets the internal SCL output low. Master A finishes counting low-level width of an own clock pulse at point b and sets the internal SCL output high. Since master B is holding the bus’s SCL line low, master A waits for counting high-level width of an own clock pulse. After master B has finished counting low-level width of an own clock pulse at point c and master A detects the SCL line of the bus at the high level, and starts counting high level of an own clock pulse. The clock pulse on the bus is determined by the master device with the shortest high-level width and the master device with the longest low-level width from among those master devices connected to the bus. (4) Slave address and address recognition mode specification When the TMP91CW18A is to be used as a slave device, set the slave address and in I2C0AR2. Clear to 0 for the address recognition mode. (5) Master/slave selection To operate the TMP91CW18A as a master device set SBI0CR22 to 1. To operate it as a slave device clear SBI0CR22 to 0. SBI0CR22 is cleared to 0 in hardware when a stop condition is detected on the bus or when arbitration is lost. 91CW18A-207 2005-08-15 TMP91CW18A (6) Transmitter/receiver selection To operate the TMP91CW18A as a transmitter set SBI0CR22 to 1. To operate it as a receiver clear SBI0CR22 to 0. When data with an addressing format is transferred in slave mode, when a slave address with the same value that an I2C0AR2 or a GENERAL CALL is received (All 8-bit data are 0 after a start condition), SBI0CR22 is set to 1 in hardware if the direction bit (R/ W ) sent from the master device is 1, and is cleared to 0 in hardware if the bit is 0. In master mode, when an acknowledge signal is returned from the slave device, SBI0CR22 is cleared to 0 in hardware if the value of the transmitted direction bit is 1, and is set to 1 in hardware if the value of the bit is 0. If an acknowledge signal is not returned, the current state is maintained. SBI0CR22 is cleared to 0 in hardware when a stop condition is detected on the I2C bus or when arbitration is lost. (7) Start/stop condition generation When SBISR2 = 0, slave address and direction bit which are set in SBI0DBR2 are output on the bus after generating a start condition by programming 1 to the SBI0CR22. It is necessary to set transmitted data to the data buffer register (SBI0DBR2) and set 1 to beforehand. SCL line SDA line Start condition 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 9 R/W Acknowledge signal. Slave address and the direction bit. Figure 3.12.9 Start Condition Generation and Slave Address Generation When SBISR2 = 1, the sequence for generating a stop condition can be initiated by writing 1s to SBI0SR22 and programming 0 to SBISR2. Do not modify the contents of SBI0SR22 until a stop condition has been generated on the bus. SCL line SDA line Stop condition Figure 3.12.10 Stop Condition Generation The state of the bus can be ascertained by reading the contents of SBISR2. SBISR2 will be set to 1 if a start condition has been detected on the bus, and will be cleared to 0 if a stop condition has been detected. Refere to chapter 3.12.6 (4) “Stop condition generation”, where the restriction for the stop condition in the master mode is explained. 91CW18A-208 2005-08-15 TMP91CW18A (8) Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTI2C2) is generated, SBI0CR22 is cleared to 0. The SCL line is pulled low while SBI0CR22 = 0. SBI0CR22 is cleared to 0 when a single word of data is transmitted or received. Either writing data to or reading data from SBI0DBR2 sets SBI0CR22 to 1. The time from SBI0CR22 being set to 1 until the release of the SCL line is tLOW. In address recognition mode (e.g., when SBI0CR22 = 0), SBI0CR22 is cleared to 0 when the slave address matches the value set in I2C0AR2 or a GENERAL CALL is received (All 8-bit data are 0 after a start condition). Although SBI0CR22 can be set to 1 by a program, programming 0 to SBI0CR22 does not clear it to 0. (9) Serial bus interface operation mode selection SBI0CR22 is used to specify the serial bus interface operation mode. Set SBI0CR22 to 10 when the device is to be used in I2C bus mode. After confirming pin condition of serial bus interface to high. Switch a mode to port after confirming a bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on the bus in I2C bus mode, a bus arbitration procedure has been implemented in order to guarantee the integrity of transferred data. Data on the SDA line is used for I2C bus arbitration. The following example illustrates the bus arbitration procedure when there are 2 master devices on the bus. Master A and master B output the same data until point a. After master A outputs L and master B, H, the SDA line of the bus is wire-AND and the SDA line is pulled low by master A. When the bus’s SCL line is pulled up at point b, the slave device reads the data on the SDA line, that is, data in master A. Data transmitted from master B becomes invalid. The master B state is known as arbitration lost. A master B device which loses arbitration releases the internal SDA output in order not to affect data transmitted from other masters with arbitration. When more than one master sends the same data at the 1st word, arbitration occurs continuously after the 2nd word. SCL line Internal SDA output (Master A) Internal SDA output (Master B) SDA line a b Internal SDA output becomes 1 after arbitration has been lost. Figure 3.12.11 Arbitration Lost 91CW18A-209 2005-08-15 TMP91CW18A The TMP91CW18A compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBISR2 is set to 1. When SBISR2 is set to 1, SBISR2 are cleared to 00 and the mode is switched to slave receiver mode. Thus, clock output is stopped in data transfer after setting = “1”. SBISR2 is cleared to 0 when data is written to or read from SBI0DBR2 or when data is written to SBI0CR22. Internal SCL output Internal SDA output Internal SCL output Master B Internal SDA output Accessed to SBI0DBR2 or SBI0CR22 D7B D6B Keep internal SDA output to high-level as losing arbitration. 1 D7A 2 D6A 3 D5A 4 D4A 5 D3A 6 D2A 7 D1A 8 D0A 9 1 2 3 4 Master A D7A’ D6A’ D5A’ D4A’ Stop the clock pulse 1 2 3 4 Figure 3.12.12 Example of when TMP91CW18A is a Master Device B (D7A = D7B, D6A = D6B) (11) Slave address match detection monitor SBISR2 is set to 1 in slave mode, in address recognition mode (e.g., when I2C0AR2 = 0), when a GENERAL CALL is received or a slave address matches the value set in I2C0AR2. When I2C0AR2 = 1, SBISR2 is set to 1 after 1st word of data has been received. SBISR2 is cleared to 0 when data is written to or read from the data buffer register SBI0DBR2. (12) GENERAL CALL detection monitor SBISR2 is set to 1 in slave mode when a GENERAL CALL is received (All 8-bit received data is 0 after a start condition). SBISR2 is cleared to 0 when a start condition or stop condition is detected on the bus. (13) Last received bit monitor The value on the SDA line detected on the rising edge of the SCL line is stored in SBISR2. In acknowledge mode, immediately after an INTI2C2 interrupt request has been generated, an acknowledge signal is read by reading the contents of SBISR2. 91CW18A-210 2005-08-15 TMP91CW18A (14) Software reset function The software reset function is used to initialize the SBI circuit when SBI is locked by external noises, etc. An internal reset signal pulse can be generated by setting SBI0CR22 to 10 and 01. This initializes the SBI circuit internally. All command except SBI0CR22 registers and status registers are initialized as well. SBI0CR12 is automatically set to 1 after the SBI circuit has been initialized. (15) Serial bus interface data buffer register (SBI0DBR2) Received data can be read by reading SBI0DBR2 and transferred data can be written by writing to SBI0DBR2. When the start condition has been generated in master mode, the slave address and the direction bit are set in this register. (16) I2C bus address register (I2C0AR2) I2C0AR2 is used to set the slave address when the TMP91CW18A functions as a slave device. If the slave address output from the master device is recognized as matching the TMP91CW18A’s slave address, I2C0AR2 is cleared to 0. The data format is the addressing format. When the slave address output from the master does not match the TMP91CW18A’s slave address, I2C0AR2 is set to 1 and the data format is the free data format. (17) Baud rate register (SBI0BR12) Write 1 to SBI0BR12 before operation commences. (18) Setting register for IDLE2 mode operation (SBI0BR02) The setting of SBI0BR02 determines whether the device is operating or is stopped in IDLE2 mode. Hence, must be set before a HALT instruction is executed. 91CW18A-211 2005-08-15 TMP91CW18A 3.12.6 Data Transfer in I2C Bus Mode (1) Device initialization Set SBI0BR12 and SBI0CR12 to 1. Set SBI0BR12 to 1 and clear bits 7, 6, 5 and 3 of SBI0CR12. Set a slave address in I2C0AR2 and I2C0AR2 (I2C0AR2 = 0 when an addressing format). For specifying the default setting to a slave receiver mode, clear the to 0 and set the to 1, the to 10. (2) Start condition generation and slave address generation 1. Master mode In master mode, the start condition and the slave address are generated as follows. Check a bus free status (when = 0). Set SBI0CR12 to 1 (Acknowledge mode) and specify a slave address and a direction bit to be transmitted to the SBI0DBR2. If SBI0CR22 = 0, the start condition is generated by writing 1111 to SBI0CR22. Subsequently to the start condition, 9 clocks are output from the SCL pin. While 8 clocks are output, the slave address and the direction bit which are set to the SBI0DBR2. On the 9th clock pulse the SDA line is released and the acknowledge signal is received from the slave device. An INTI2C2 interrupt request occurs on the falling edge of the 9th clock pulse. SBI0CR22 is cleared to 0. In master mode the SCL pin is pulled low while SBI0CR22 is 0. When an interrupt request occurs, the value of SBI0CR22 is changed according to the direction bit setting only if the slave device returns an acknowledge signal. 2. Slave mode In slave mode the start condition and the slave address are received. After the start condition has been received from the master device, while 8 clocks are output from the SCL pin, the slave address and the direction bit which are output from the master device are received. When a GENERAL CALL or an address matching the slave address set in I2C0AR2 is received, the SDA line is pulled down low on the 9th clock pulse and an acknowledge signal is output. An INTI2C2 interrupt request occurs on the falling edge of the 9th clock pulse. SBI0CR22 is cleared to 0. In slave mode the SCL line is pulled low while SBI0CR22 = 0. When an interrupt request occurs, the value of SBI0CR22 is changed according to the direction bit setting only if the slave device returns an acknowledge signal. SCL SDA 1 A6 Start condition INTI2C2 interrupt request 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 R/W 9 ACK Acknowledge signal from a slave device. Slave address + Direction bit. Output of master Output of slave Figure 3.12.13 Start Condition Generation and Slave Address Transfer 91CW18A-212 2005-08-15 TMP91CW18A (3) Single-word data transfer Check the setting using an INTI2C2 interrupt process after the transfer of each word of data is completed and determine whether the device is in master mode or slave mode. 1. If = 1 (Master mode) Check the setting and determine whether the device is in transmitter mode or receiver mode. If = 1 (Transmitter mode) Check the setting. If = 1, there is no receiver requesting data. Implement the process for generating a stop condition (See section 3.10.6 (4)) and terminate data transfer. If = 0, the receiver is requesting new data. When the next transmitted data is 8 bits, write the transmitted data to SBI0DBR2. When the next transmitted data is other than 8 bits, set to 1, set to 1 and write the transmitted data to SBI0DBR2. After the data has been written, is set to 1, a serial clock pulse is generated to trigger transfer of the next word of data via the SCL pin, and the word is transmitted. After the data has been transmitted, an INTI2C2 interrupt request is generated. is cleared to 0 and the SCL line is pulled low. If the length of the data to be transferred is greater than one word, repeat the latter steps of the procedure, starting from the check of the setting. Write to SBI0DBR2 SCL line SDA line INTI2C2 interrupt request 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK Acknowledge signal from a receive. Output from master Output from slave Figure 3.12.14 Example in which = 000 and = 1 in Transmitter Mode 91CW18A-213 2005-08-15 TMP91CW18A If = 0 (Receiver mode) When the next transmitted data is other than 8 bits, set again. Set to 1 and read the received data from SBI0DBR2 so as to release the SCL line. (The value of data which is read immediately after a slave address is sent is undefined.) After the data has been read, is set to 1. Serial clock pulse for transfering new 1 word of data is defined SCL and outputs “L” level from SDA pin with acknowledge timing. An INTI2C2 interrupt request is then generated and is cleared to 0. The TMP91CW18A then pulls the SCL pin low. From then on the TMP91CW18A outputs a clock pulse, so as to transfer a data word, and an acknowledge signal each time received data is read from SBI0DBR2. Read SBI0DBR2 SCL SDA 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK New D7 Acknowledge signal to a transmitter. INTI2C2 interrupt request Output from master Output from slave Figure 3.12.15 Example of when = “000”, = “1” in Receiver Mode In order to terminate the transmission of data to a transmitter, clear to 0 before reading data which is 1 word before the last data to be received. The last data word does not generate a clock pulse as the acknowledge signal. After the data has been transmitted and an interrupt request has been generated, set to 001 and read the data. The TMP91CW18A generates a clock pulse for a 1-bit data transfer. Since the master device is a receiver, the SDA line on the bus remains high. The transmitter interprets the high signal as an ACK signal. The receiver indicates to the transmitter that data transfer is completed. After the 1 data bit has been received and an interrupt request been generated, the TMP91CW18A generates a stop condition (See section 3.10.6 (4)) and terminates data transfer. SCL line 9 SDA line 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 1 Acknowledge signal sent to a transmitter. INTI2C2 interrupt request Read SBI0DBR2 after is cleared to 0. Read SBI0DBR2 after are set to 001. Output of master Output of slave Figure 3.12.16 Termination of Data Transfer in Master Receiver Mode 91CW18A-214 2005-08-15 TMP91CW18A 2. If = 0 (Slave mode) In slave mode the TMP91CW18A operates either in normal slave mode or in slave mode after losing arbitration. In slave mode an INTI2C2 interrupt request is generated when the TMP91CW18A receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or when a matching slave address is received. The TMP91CW18A will enter slave mode from master mode if it loses arbitration. An INTI2C2 interrupt request is generated when a word data transfer terminates after arbitration has been lost. When an INTI2C2 interrupt request is generated, is cleared to 0 and the SCL pin is pulled low. Either reading data to or writing data from SBI0DBR2, or setting to 1 will release the SCL pin after tLOW. Check the SBISR2, , and and implements processes according to conditions listed in the next table. Table 3.12.1 Operation in the Slave Mode 1 1 1 0 Conditions Process The TMP91CW18A loses arbitration Set the number of bits a word in when transmitting a slave address and and write the transmitted data receives a slave address for which the to SBI0DBR2. value of the direction bit sent from another master is 1. In slave receiver mode the TMP91CW18A receives a slave address for which the value of the direction bit sent from the master is 1. In slave transmitter mode a single word of is transmitted. Set to the number of bits in a word. Check the setting. If is set to 1, set to 1 since the receiver win no request the data which follows. Then, clear to 0 to release the bus. If is cleared to 0 of and write the transmitted data to SBI0DBR2 since the receiver requests next data. 0 1 0 0 0 0 1 1 1/0 The TMP91CW18A loses arbitration Read the SBI0DBR2 for setting the when transmitting a slave address and to 1 (Reading dummy data) or set receives a slave address or GENERAL the to 1. CALL for which the value of the direction bit sent from another master is 0. The TMP91CW18A loses arbitration when transmitting a slave address or data and terminates word data transfer. In slave receiver mode the TMP91CW18A receives a slave address or GENERAL CALL for which the value of the direction bit sent from the master is 0. In slave receiver mode the TMP91CW18A terminates receiving word data. Set to the number of bits in a word and read the received data from SBI0DBR2. 0 0 0 1 1/0 0 1/0 91CW18A-215 2005-08-15 TMP91CW18A (4) Stop condition generation When SBISR2 = 1, the sequence for generating a stop condition start by writing “1” to SBI0CR22 and “0” to SBI0CR22. Do not modify the contents of SBI0CR22 until a stop condition has been generated on the bus. When the bus’s SCL line has been pulled low by another device, the TMP91CW18A generates a stop condition when the other device has released the SCL line and SDA pin rising. When SBI0CR22 are written 1 and is written 0 (Generate stop condition in master mode), changes to 0 by internal SCL changes to 1, without waiting stop condition. To check whether SCL and SDA pin are 1 by sensing their ports is needed to detect bus free condition. 1 → 1 → 0 → 1 → Internal SCL SCL pin Stop condition SDA pin (Read) Figure 3.12.17 Stop Condition Generation (Single master) 1 → 1 → 0 → 1 → Internal SCL SCL pin The case of pulled low by another device. Stop condition SDA pin (Read) Figure 3.12.18 Stop Condition Generation (Multi master) 91CW18A-216 2005-08-15 TMP91CW18A (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when the TMP91CW18A is in master mode. Clear SBI0CR22 to 0 and set SBI0CR22 to 1 to release the bus. The SDA line remains high and the SCL pin is released. Since a stop condition has not been generated on the bus, other devices assume the bus to be in busy state. And confirm SCL pin, that SCL pin is released and become bus-free state by SBISR2 = 0 or signal level 1 of SCL pin in port mode. Check the until it becomes 1 to check that the SCL line on a bus is not pulled down to the low-level by other devices. After confirming that the bus remains in a free state, generate a start condition using the procedure described in (2). In order to satisfy the setup time requirements when restarting, take at least 4.7 μs of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition. 0 → 0 → 0 → 1 → 1 → 1 → 1 → 1 → 4.7 [μs] (Min) SCL (Bus) SCL pin SDA pin 9 Start condition Figure 3.12.19 Timing Diagram for TMP91CW18A Restart 91CW18A-217 2005-08-15 TMP91CW18A 3.13 Analog/Digital Converter The TMP91CW18A incorporates a 10-bit successive approximation-type analog/digital converter (AD converter) with 12-channel analog input. Figure 3.13.1 is a block diagram of the AD converter. The 12-channel analog input pins (AN0 to AN7) are shared with the input-only port 5 (AN8 to AN11) are shared with the input-only port 4 can thus be used as general-purpose input port. Note: When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timing the system may enter a standby mode even though the internal comparator is still enabled. Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed. Internal data bus AD mode control register 1 ADMOD1 ADMOD1 AD mode control register 0 ADMOD0 Decoder ADTRG Start AN11 AN10 AN9 ADREG /AN8 Channel select AD converter control circuit INTAD interrupt Multiplexer AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AD conversion result Sample and Hold + − Comparator register ADREGAL/H ADREGBL/H ADREGCL/H ADREGDL/H VREFH VREFL DA converter Figure 3.13.1 Block Diagram of AD Converter 91CW18A-218 2005-08-15 TMP91CW18A 3.13.1 Analog/Digital Converter Registers The AD converter is controlled by the two AD mode control registers; ADMOD0 and ADMOD1. The eight AD conversion data upper and lower registers (ADREGAH/L, ADREGBH/L, ADREGCH/L and ADREGDH/L) store the results of AD conversion. Figure 3.13.2 shows the registers related to the AD converter. AD Mode Control Register 0 7 ADMOD0 (02B0H) Bit symbol Read/Write After reset Function 0 AD conversion end flag 0: Conversion in progress 1: Conversion complete 6 ADBF R 0 AD conversion busy flag 0: Conversion stopped 1: Conversion in progress 5 − 0 Always write 0 4 − 0 Always write 0 3 ITM0 0 Interrupt specification in conversion channel fixed repeat mode 0: Every conversion 1: Every fourth conversion 2 REPEAT R/W 0 Repeat mode specification 0: Single conversion 1: Repeat conversion mode 1 SCAN 0 Scan mode specification 0: Conversion channel fixed mode 1: Conversion channel scan mode 0 ADS 0 AD conversion start 0: Don’t care 1: Start conversion Always 0 when read. EOCF AD conversion start 0 1 Don’t care Start AD conversion Note: Always read as 0. AD scan mode setting 0 1 AD conversion channel fixed mode AD conversion channel scan mode AD repeat mode setting 0 1 AD single conversion mode AD repeat conversion mode Specify AD conversion interrupt for channel fixed repeat conversion mode Channel fixed repeat conversion mode = 0, = 1 0 1 Generates interrupt every conversion Generates interrupt every fourth conversion AD conversion busy flag 0 1 AD conversion stopped AD conversion in progress AD conversion end flag 0 1 Before or during AD conversion AD conversion complete Figure 3.13.2 AD Converter Related Register 91CW18A-219 2005-08-15 TMP91CW18A AD Mode Control Register 1 7 ADMOD1 (02B1H) Bit symbol Read/Write After reset Function VREFON R/W 0 6 I2AD R/W 0 5 4 ADTRGE 0 AD external trigger start control. 0: Disable 1: Enable 3 ADCH3 0 2 ADCH2 R/W 0 1 ADCH1 0 0 ADCH0 0 IDLE2 VREF 0: Stop generation 1: Operation control 0: Not generated 1: Generated Analog input channel selection. Analog input channel selection 0000 0001 0010 0011 0100 0101 0110 0111 1000 (Note 1) 1001 1010 1011 1100 1101 1110 1111 0 Channel fixed AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 − − − − AN0 AN0 → AN1 AN0 → AN1 → AN2 AN0 → AN1 → AN2 → AN3 AN4 AN4 → AN5 AN4 → AN5 → AN6 AN4 → AN5 → AN6 → AN7 − − − − Reserved Reserved Reserved Reserved 1 Channel scan AD conversion start control by external trigger ( ADTRG input). 0 1 Disable Enable IDLE2 control 0 1 Stop Operation Control of reference voltage generation for AD converter. 0 1 Not generated Generated Before starting conversion (before writing 1 to ADMOD0), set the bit to 1. Note 1: As pin AN8 also functions as the ADTRG input pin, do not set = 1000, when using ADTRG with set to 1. Note 2: AN8 to AN11 dose not use scan mode. When using set to 1, ADMODO clear to 0. Figure 3.13.3 AD Converter Related Register 91CW18A-220 2005-08-15 TMP91CW18A AD Conversion Data Low Register 0/4/8 7 ADREGAL (02A0H) Bit symbol Read/Write After reset Function ADRA1 R Undefined Stores lower 2 bits of AD conversion result. 6 ADRA0 5 4 3 2 1 0 ADRARF R 0 AD conversion data storage flag. 1: Conversion result stored AD Conversion Data Upper Register 0/4/8 7 ADREGAH (02A1H) Bit symbol Read/Write After reset Function ADRA9 6 ADRA8 5 ADRA7 4 ADRA6 R Undefined 3 ADRA5 2 ADRA4 1 ADRA3 0 ADRA2 Stores upper 8 bits AD conversion result. AD Conversion Data Lower Register 1/5/9 7 ADREGBL (02A2H) Bit symbol Read/Write After reset Function ADRB1 R Undefined Stores lower 2 bits of AD conversion result. 6 ADRB0 5 4 3 2 1 0 ADRBRF R 0 AD conversion result flag. 1: Conversion result stored AD Conversion Data Upper Register 1/5/9 7 ADREGBH (02A3H) Bit symbol Read/Write After reset Function 9 Channel x conversion result ADREGxH 7 6 5 4 3 2 1 0 7 6 5 4 3 2 ADREGxL 1 0 8 7 ADRB9 6 ADRB8 5 ADRB7 4 ADRB6 R Undefined 3 ADRB5 2 ADRB4 1 ADRB3 0 ADRB2 Stores upper 8 bits of AD conversion result. 6 5 4 3 2 1 0 • Bits 5 to 1 are always read as 1. • Bit0 is the AD conversion data storage flag . When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.4 AD Converter Related Registers 91CW18A-221 2005-08-15 TMP91CW18A AD Conversion Result Lower Register 2/6/10 7 ADREGCL (02A4H) Bit symbol Read/Write After reset Function ADRC1 R Undefined Stores lower 2 bits of AD conversion result. 6 ADRC0 5 4 3 2 1 0 ADRCRF R 0 AD conversion data storage flag. 1: Conversion result stored AD Conversion Data Upper Register 2/6/10 7 ADREGCH (02A5H) Bit symbol Read/Write After reset Function ADRC9 6 ADRC8 5 ADRC7 4 ADRC6 R Undefined 3 ADRC5 2 ADRC4 1 ADRC3 0 ADRC2 Stores upper 8 bits of AD conversion result. AD Conversion Data Lower Register 3/7/11 7 ADREGDL (02A6H) Bit symbol Read/Write After reset Function ADRD1 R Undefined Stores lower 2 bits of AD conversion result. 6 ADRD0 5 4 3 2 1 0 ADRDRF R 0 AD conversion data storage flag. 1: Conversion result stored AD Conversion Result Upper Register 3/7/11 7 ADREGDH (02A7H) Bit symbol Read/Write After reset Function 9 Channel x conversion result ADREGxH 7 6 5 4 3 2 1 0 7 6 5 4 3 2 ADREGxL 1 0 8 7 ADRD9 6 ADRD8 5 ADRD7 4 ADRD6 R Undefined 3 ADRD5 2 ADRD4 1 ADRD3 0 ADRD2 Stores upper 8 bits of AD conversion result. 6 5 4 3 2 1 0 • Bits 5 to 1 are always read as 1. • Bit0 is the AD conversion data storage flag . When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.13.5 AD Converter Related Registers 91CW18A-222 2005-08-15 TMP91CW18A 3.13.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin, a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage, the difference between VREFH and VREFL are divided by 1024 using string resistance. The result of the division is then compared with the analog input voltage. To turn off the switch between VREFH and VREFL, program a 0 to ADMOD1 in AD mode control register 1. To start AD conversion in the OFF state, first write a 1 to ADMOD1, wait for 3 μs until the internal reference voltage stabilizes (This is not related to fc), then set ADMOD0 to 1. (2) Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter. • In analog input channel fixed mode (ADMOD0 = 0) Setting ADMOD1 selects one of the input pins AN0 to AN11 as the input channel. In analog input channel scan mode (ADMOD0 = 1) Setting ADMOD1 selects one of the eight scan modes. Table 3.13.1 illustrates analog input channel selection in each operation mode. On a reset, ADMOD0 is cleared to 0 and ADMOD1 is initialized to 0000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input channels can be used as standard input port pins. Table 3.13.1 Analog Input Channel Selection 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 • Channel Fixed = 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN0 Channel Scan = 1 AN0 → AN1 AN0 → AN1 → AN2 AN0 → AN1 → AN2 → AN3 AN4 AN4 → AN5 AN4 → AN5 → AN6 AN4 → AN5 → AN6 → AN7 − − − − 91CW18A-223 2005-08-15 TMP91CW18A (3) Starting AD conversion To start AD conversion, write a 1 to ADMOD0 in AD mode control register 0 or ADMOD1 in AD mode control register 1, pull the ADREG pin input from high to low. When AD conversion starts, the AD conversion busy flag ADMOD0 will be set to 1, indicating that AD conversion is in progress. Writing a 1 to ADMOD0 during AD conversion restarts conversion. At that time, to determine whether the AD conversion results have been preserved, check the value of the conversion data storage flag ADREGxL. During AD conversion, a falling edge input on the ADREG pin will be ignored. (4) AD conversion modes and the AD conversion end interrupt The four AD conversion modes are: • • • • Channel fixed single conversion mode Channel scan single conversion mode Channel fixed repeat conversion mode Channel scan repeat conversion mode The ADMOD0 and ADMOD0 settings in AD mode control register 0 determine the AD mode setting. Completion of AD conversion triggers an INTAD AD conversion end interrupt request. Also, ADMOD0 will be set to 1 to indicate that AD conversion has been completed. 1. Channel fixed single conversion mode Setting ADMOD0 and ADMOD0 to 00 selects conversion channel fixed single conversion mode. In this mode data on one specified channel is converted once only. When the conversion has been completed, the ADMOD0 flag is set to 1, ADMOD0 is cleared to 0, and an INTAD interrupt request is generated. 2. Channel scan single conversion mode Setting ADMOD0 and ADMOD0 to 01 selects conversion channel scan single conversion mode. In this mode data on the specified scan channels is converted once only. When scan conversion has been completed, ADMOD0 is set to 1, ADMOD0 is cleared to 0, and an INTAD interrupt request is generated. 91CW18A-224 2005-08-15 TMP91CW18A 3. Channel fixed repeat conversion mode Setting ADMOD0 and ADMOD0 to 10 selects conversion channel fixed repeat conversion mode. In this mode data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0 is set to 1 and ADMOD0 is not cleared to 0 but held at 1. INTAD interrupt request generation timing is determined by the setting of ADMOD0. Clearing to 0 generates an interrupt request every time an AD conversion is completed. Setting to 1 generates an interrupt request on completion of every fourth conversion. 4. Channel scan repeat conversion mode Setting ADMOD0 and ADMOD0 to 11 selects conversion channel scan repeat conversion mode. In this mode data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0 is set to 1 and an INTAD interrupt request is generated. ADMOD0 is not cleared to 0 but held at 1. To stop conversion in a repeat conversion mode (e.g., in cases 3. and 4.), program a 0 to ADMOD0. After the current conversion has been completed, the repeat conversion mode terminates and ADMOD0 is cleared to 0. Switching to a halt state (IDLE2 mode with ADMOD1 cleared to 0, IDLE1 mode or STOP mode) immediately stops operation of the AD converter even when AD conversion is still in progress. In repeat conversion modes (e.g., in cases 3. and 4.), when the halt is released, conversion restarts from the beginning. In single conversion modes (e.g., in cases 1. and 2.), conversion does not restart when the halt is released. (The converter remains stopped.) Table 3.13.2 shows the relationship between the AD conversion modes and interrupt requests. Table 3.13.2 Relationship between AD Conversion Modes and Interrupt Requests Mode Channel fixed single conversion mode Channel scan single conversion mode Channel fixed repeat conversion mode Channel scan repeat conversion mode Interrupt Request Generation After completion of conversion After completion of scan conversion Every conversion Every forth conversion After completion of every scan conversion ADMOD0 X X 0 1 X 0 0 1 1 0 1 0 1 X: Don’t care 91CW18A-225 2005-08-15 TMP91CW18A (5) AD conversion time 84 states (6.7 μs at fFPH = 25 MHz) are required for the AD conversion of one channel. (6) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREGAH/L to ADREGDH/L) store the results of AD conversion. (ADREGAH/L to ADREGDH/L are read only registers.) In channel fixed repeat conversion mode, the conversion results are stored successively in registers ADREGAH/L to ADRGDH/L. In other modes the AN0 and AN4, AN5 and AN9, AN2, and AN6, AN10 and AN10, AN7 and AN11 conversion results are stored in ADREGAH/L, ADREGBH/L, ADREGCH/L and ADREGDH/L respectively. Table 3.13.3 shows the correspondence between the analog input channels and the registers which are used to hold the results of AD conversion. Table 3.13.3 Correspondence between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog Input Channel (Port A) AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Conversion Modes Other than at Right ADREGAH/L ADREGBH/L ADREGCH/L ADREGDH/L ADREGAH/L ADREGBH/L ADREGCH/L ADREGDH/L ADREGAH/L ADREGBH/L ADREGCH/L ADREGDH/L Channel Fixed Repeat Conversion Mode (=1) ADREGAH/L ADREGBH/L ADREGCH/L ADREGDH/L , bit0 of the AD conversion data lower register is used as the AD conversion data storage flag. The storage flag indicates whether the AD conversion result register has been read or not. When a conversion result is stored in the AD conversion result register, the flag is set to 1. When either of the AD conversion result registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0. Reading the AD conversion result also clears the AD conversion end flag ADMOD0 to 0. 91CW18A-226 2005-08-15 TMP91CW18A Setting example: 1. Convert the analog input voltage on the AN3 pin and write the result to memory address 0800H using the AD interrupt (INTAD) processing routine. Main routine: 76543210 INTE0AD ADMOD1 ADMOD0 ←X100---←11XX0011 ←XX000001 Enable INTAD and set it to interrupt level 4. Set pin AN3 to be the analog input channel. Start conversion in channel fixed single conversion mode. Interrupt routine processing example: WA WA (0800H) ← ADREGD >>6 ← WA Read value of ADREGDL and ADREGDH into 16-bit general-purpose register WA. Shift contents read into WA 6 times to right and 0-fill upper bits. Write contents of WA to memory address 0800H. 2. This example repeatedly converts the analog input voltages on the three pins AN0, AN1 and AN2, using channel scan repeat conversion mode. INTE0AD ADMOD1 ADMOD0 ←X000---←11XX0010 ←XX000111 Disable INTAD. Set pins AN0 to AN2 to be the analog input channels. Start conversion in channel scan repeat conversion mode. X: Don’t care, −: No change 91CW18A-227 2005-08-15 TMP91CW18A 3.14 Watchdog Timer (Runaway detection timer) The TMP91CW18A features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset. (The level of external RESET pin is not changed.) 3.14.1 Configuration Note: It needs to care designing the total machine set, because watchdog timer can’t operate completely by external noise. Figure 3.14.1 is a block diagram of the watchdog timer (WDT). WDMOD RESET Reset control Internal reset INTWD interrupt WDMOD 2 fSYS (fFPH/2) 15 Selector 17 2 219 2 21 Binary counter (22 stage) Reset R Q S Internal reset Write 4EH Write B1H WDMOD WDT control register WDCR Internal data bus Note: It needs to care designing the total machine set, because watchdog timer can’t operate completely by external noise. Figure 3.14.1 Block Diagram of Watchdog Timer 91CW18A-228 2005-08-15 TMP91CW18A The watchdog timer consists of a 22-stage binary counter which uses the system clock (fSYS) as the input clock. The binary counter can output fSYS/215, fSYS/217, fSYS/219 and fSYS/221. WDT counter n Overflow 0 WDT interrupt Clear write code WDT clear (Software) Figure 3.14.2 Normal Mode The runaway is detected when an overflow occurs, and the watchdog timer can reset device. In this case, the reset time will be between 22 and 29 states (28.2 to 37.1 μs at fFPH = 25MHz, fOSCH = 1 state )is fFPH/2, where fFPH is generated by dividing the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function. Overflow WDT counter n WDT interrupt Internal reset 22 to 29 states (28.2 to 37.1 μs at fOSCH = 25 MHz, fFPH = 1 MHz) Figure 3.14.3 Reset Mode 91CW18A-229 2005-08-15 TMP91CW18A 3.14.2 Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) 1. Setting the detection time for the watchdog timer in This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. On a reset this register is initialized to WDMOD = 00. The detection times for WDT are shown in Figure 3.14.4. 2. Watchdog timer enable/disable control register On a reset WDMOD is initialized to 1, enabling the watchdog timer. To disable the watchdog timer, it is necessary to clear this bit to 0 and to write the disable code (B1H) to the Watchdog timer control register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting to 1. 3. Watchdog timer out reset connection This register is used to connect the output of the watchdog timer with the RESET terminal internally. Since WDMODis initialized to 0 on a reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear the binary counter for the watchdog timer. Disable control the watchdog timer can be disabled by clearing WDMOD to 0 and then writing the disable code (B1H) to the WDCR register. WDMOD WDCR ←0------←10110001 Clear WDMOD to 0. Write the disable code (B1H). • Enable control Set WDMOD to 1. • Watchdog timer clear control To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR register. WDCR ←01001110 Write the clear code (4EH). Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please refer to setting example.) Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once. 91CW18A-230 2005-08-15 TMP91CW18A 7 WDMOD (0300H) Bit symbol Read/Write After reset Function WDTE R/W 1 WDT control 0: Disabled 1: Enabled 6 WDTP1 R/W 0 5 WDTP0 0 4 3 2 I2WDT R/W 0 1 RESCR 0 0 − R/W 0 Always write 0 Select detecting time 15 00: 2 /fSYS 01: 2 /fSYS 10: 2 /fSYS 11: 2 /fSYS 21 19 17 IDLE2 1:Connects 0: Stop WDL out 1: Operation to a internally reset Watchdog timer out control 0 1 − Connects WDT out to a reset IDLE2 Control 0 1 Stop Operation Watchdog timer detection time SYSCR1 System Clcok Selection 1 (fs) SYSCR1 Gear Value 00 XXX 000 (fc) 001 (fc/2) 0 (fc) 010 (fc/4) 011 (fc/8) 100 (fc/16) 2.0 s 2.62 ms 5.24 ms 10.49 ms 20.97 ms 41.94 ms at fc = 25 MHz Watchdog Timer Detection Time WDMOD 01 8.0 s 10.49 ms 20.97. ms 41.94 ms 83.39 ms 167.77 ms 10 32.0 s 41.94 ms 83.89 ms 167.77 ms 335.54 ms 671.09 ms 11 128.0 s 128.00 ms 335.54 ms 671.09 ms 1342.18 ms 2684.35 ms Watchdog timer enable/disable control 0 1 Disabled Enabled Figure 3.14.4 Watchdog Timer Mode Register 7 WDCR (0301H) Bit symbol Read/Write B1H: WDT disable code 4EH: WDT clear code 6 5 4 − 3 W − 2 1 0 Read-modify After reset Function -write instructions are prohibited. Disable/clear WDT B1H 4EH Others Disable code Clear code Don’t care Figure 3.14.5 Watchdog Timer Control Register 91CW18A-231 2005-08-15 TMP91CW18A 3.14.3 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD＜WDTP1:0> has elapsed. The watchdog timer must be zero-cleared in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (Runaway) due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti-mulfunction program. By connecting the watchdog timer out pin to a peripheral device’s reset input, the occurrence of a CPU malfunction can also be relayed to other devices. The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter continues counting during bus release (when BUSAK goes low). When the device is in IDLE2 mode, the operation of WDT depends on the WDMOD setting. Ensure that WDMOD is set before the device enters IDLE2 mode. Example: 1. Clear the binary counter. WDCR ←01001110 Write the clear code (4EH). 2. Set the watchdog timer detection time to 217/fSYS. WDMOD ←101----←0------←10110001 3. Disable the watchdog timer. WDMOD WDCR Clear WDTE to 0. Write the disable code (B1H). Note: The watchdog timer cannot operate by disturbance noise in some case. Take care when design the device. 91CW18A-232 2005-08-15 TMP91CW18A 4. 4.1 Electrical Characteristics Maximum Ratings Parameter Power supply voltage Input voltage Output current Output current Output current (Total) Output current (Total) Power dissipation (Ta = 70°C) Soldering temperature (10 s) Storage temperature Operating temperature VIN IOL IOH ΣIOL ΣIOH PD TSOLDER TSTG TOPR Symbol VCC Rating −0.5 to 6.5 −0.5 to Vcc + 0.5 2 −2 80 −80 600 260 −65 to 150 −30 to 70 Unit V mA mW °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Parameter Symbol Condition Min Typ. (Note1) Max Unit Power supply voltage AVCC = DVCC AVSS = DVSS = 0 V P00 to P17 (AD0 to AD15) Input low voltage P20 to P87 RESET , NMI VCC VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH fc = 8 to 25 MHz VCC ≥ 4.5V 4.5 5.5 0.8 0.3 VCC V AM0, AM 1 X1 P00 to P17 (AD0 to AD15) P20 to P87 RESET , NMI VCC = 4.5 to 5.5 V −0.3 0.25 VCC 0.3 0.2 VCC VCC = 4.5 to 5.5 V 0.7 VCC 0.7 VCC 0.75 VCC VCC − 0.3 0.8 VCC VCC + 0.3 V Input high voltage AM0 to AM 1 X1 VCC = 4.5 to 5.5 V Output low voltage Output high voltage IOL = 1.6 mA (VCC = 4.5 to 5.5 V) IOH = − 400 μA (VCC = 5.0 V ± 10 %) 0.8VCC 0.45 V Note: Typical values are for when Ta = 25°C and VCC = 5.0 V uncles otherwise noted. 91CW18A-233 2005-08-15 TMP91CW18A DC Characteristics (2/2) Parameter Input leakage current Output leakage current Power down voltage (at STOP, RAM back up) RESET pull-up resistor Symbol ILI ILO VSTOP RRST CIO VTH RKH Condition 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 V IL2 = 0.2 VCC, V IH2 = 0.8 VCC VCC = 5 V ± 10% fc = 1 MHz Min Typ. (Note 1) 0.02 0.05 Max ±1 ±10 5.5 200 10 Unit μA V kΩ pF V 2.0 40 Pin capacitance Schmitt width RESET , NMI Programmable pull-up resistor NORMAL (Note 2) IDLE2 IDLE1 STOP 0.4 VCC = 5 V ± 10% VCC = 5 V ± 10 % fc = 25 MHz 40 1.0 200 22.5 8.6 3.5 0.2 35.0 13.0 7.0 20 kΩ mA ICC (Typ. VCC = 5.0 V) Ta ≤ 70°C VCC = 4.5 to 5.5 V μA Note 1: Typical values are for when Ta = 25°C and VCC = 5.0 V unless otherwise noted. Note 2: ICC measurement conditions (NORMAL): All functions are operational. Output pins are open and input pins are fixed. 91CW18A-234 2005-08-15 TMP91CW18A 4.3 AC Characteristics (1) VCC = 5.0 V ± 10 % Variable Min 40 0.5x − 15 0.5x − 15 x − 20 0.5x − 20 0.5x − 15 x − 15 x − 25 1.5x − 50 0.5x − 20 x − 20 3.0x − 45 3.5x − 35 2.0x − 40 2.0x − 20 0 x − 15 1.5x − 20 1.5x − 50 x − 15 3.5x − 90 3.0x − 80 2.0x + 0 3.5x − 120 3.5x 3.5x + 100 140 319 80 20 60 0 25 40 10 25 50 40 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Parameter fFPH period (= x) A0 to A15 vaild → ALE fall ALE fall → A0 to A15 hold ALE high width ALE fall → RD / WR fall RD rise → ALE rise WR rise → ALE rise Symbol tFPH tAL tLA tLL tLC tCLR tCLW tACL tACH tCAR tCAW tADL tADH tRD tRR tHR tRAE tWW tDW (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode fFPH = 25 MHz Min 40 5 5 20 0 5 25 15 10 0 20 75 105 40 Max 31250 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns A0 to A15 valid → RD / WR fall A0 to A23 valid → RD / WR fall RD rise → A0 to A23 hold WR rise → A0 to A23 hold A0 to A15 valid → D0 to D15 input A0 to A23 valid → D0 to D15 input RD fall → D0 to D15 input RD low width RD rise → D0 to D15 hold RD rise → A0 to A15 output WR low width D0 to D15 Valid → WR rise WR rise → D0 to D15 hold tWD tAWH tAWL tCW tAPH tAPH2 tAP A0 to A23 valid → WAIT input A0 to A15 valid → WAIT input RD / WR fall → WAIT hold A0 to A23 valid → Port input A0 to A23 valid → Port hold A0 to A23 valid → Port valid AC measuring conditions • Output level: High = 2.2 VCC/Low = 0.8 VCC, CL = 50 pF • Input level: High = 2.4 VCC/Low = 0.45 VCC (AD0 to AD15) High = 0.8 VCC/Low = 0.2 VCC (except AD0 to AD15) Note: Symbol x in the above table means the period of clock fFPH, it’s half period of the system clock fSYS for CPU core. The period of fFPH depends on the clock gear setting or the selection of high/low oscillator frequency. 91CW18A-235 2005-08-15 TMP91CW18A (2) VCC = 5.0 V ± 10 % 1. Read cycle tFPH fFPH A0 to A23 tAWH tAWL WAIT tCW tAP Port input (Note) tAPH2 tADH RD tCAR tRR tRAE tHR D0 to D15 tACH tAC tLC tRD tADL AD0 to AD15 A0 to A15 tAL tLA tCLR ALE tLL Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91CW18A-236 2005-08-15 TMP91CW18A 2. Write cycle fFPH A0 to A23 WAIT tAP Port output (Note) WR , HWR tWW tDW tCAW tWD AD0 to AD15 A0 to A15 D0 to D15 tCLW ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91CW18A-237 2005-08-15 TMP91CW18A 4.4 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Analog input voltage range (+) Analog input voltage range (−) Analog input voltage range Analog input voltage range = 1 = 0 Error (Not including quantizing errors) − Symbol VREFH VREFL VAIN IREF (VREFL = 0 V) Condition VCC = 5 V ± 10 % VCC = 5 V ± 10 % Min VCC − 1.5 V VSS VREFL Typ. VCC VSS Max VCC VSS + 0.2 V VREFH Unit V VCC = 5 V ± 10 % VCC = 5 V ± 10 % VCC = 5 V ± 10 % 1.44 0.02 ±1.0 2.00 5.0 ±4.0 mA μA LSB Note 1: 1 LSB = (VREFH − VREFL)/1024 [V] Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value for ICC includes the current which flows through the AVCC pin. 4.5 Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1) Parameter Clock perild Clock low level width Clock high level width Symbol tVCK tVCKL tVCKH Variable Min 8X + 100 4 X + 40 4 X + 40 25 MHz Max Min 420 200 200 Max Unit ns ns ns 4.6 Interrupt, Capture (1) NMI , INT0 to INT4 interrupts Parameter NMI , INT0 to INT4 low-level width NMI , INT0 to INT4 high-level width Symbol tINTAL tINTAH Variable Min 4 X + 40 4 X + 40 25 MHz Min 200 200 Max Max Unit ns ns (2) INT5 to INT6 interrupts, capture The INT5 to INT6 input width depends on the system clock and prescaler clock settings. tINTBL (INT5 to INT6 low-level width) tINTBH (INT5 to INT6 high-level width) System Clock Selected 0 (fc) Prescaler Clock Selected 00 (fFPH) 10 (fc/16) Variable fFPH = 25 MHz Min 8X + 100 128Xc + 0.1 Variable Min 8X + 100 128Xc + 0.1 fFPH = 25 MHz Max 420 5.22 Unit Max 420 5.22 ns μs Xc: Period of clock fc 91CW18A-238 2005-08-15 TMP91CW18A 4.7 SCOUT Pin AC Characteristics Variable Min 0.5T −15 0.5T − 15 Parameter Low-level width High-level width tSCH tSCL Symbol 25 MHz Min 5 5 Max Max Condition VCC = 5 V ± 10% VCC = 5 V ± 10% Unit ns ns T: Period of SCOUT tSCH tSCL SCOUT 91CW18A-239 2005-08-15 TMP91CW18A 5. Table of SFRs (SFR: Special function register) The SFRs include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) Wait control (5) Clock gear (6) 8-bit timer (7) 16-bit timer (8) UART (9) I2C bus/SIO (10) I2C bus 1 (11) I2C bus 2 (12) AD converter (13) Watchdog timer Table layout Symbol Name Address 7 6 1 0 Bit symbol Read/write Initial value after reset Remarks Note: “Prohibit RMW” in the table means that you cannot use RMW instructions on these register. Example: When setting bit0 only of the register PxCR, the instruction “SET 0, (PxCR)” cannot be used. The LD (Transfer) instruction must be used to write all eight bits. Read/write R/W: Both read and write are possible. R: W: W* : Prohibit RMW: Only read is possible. Only write is possible. Both read and write are possible (when this bit is read as1) Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are read-modify-write instructions.) Read-modify-write instruction is prohibited when controlling the pull-up resistor. R/W*: 91CW18A-240 2005-08-15 TMP91CW18A I/O Register Address Map [1] PORT Address 0000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [2] INTC P0 P1 Register Address 0010H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH P6 P7 Register Address 0020H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register P0CR P1CR P1FC P2 P3 P2CR P2FC P3CR P3FC P4 P5 P6CR P6FC P7CR P7FC P8 P8CR P8FC IIEC SCOUTC P3ODE P8ODE Address 0080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register DMA0V DMA1V DMA2V DMA3V Address 0090H 1H 2H 3H 4H 5H 6H 7H Register INTE0AD INTE12 INTE34 INTE56 INTETA01 INTETA23 INTETA45 INTETA67 INTETB0 INTETB0OV INTEUART INTES2 INTES1 Address 00A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register INTETC01 INTETC23 INTCLR DMAR DMAB (Reserved) IIMC 8H 9H AH BH CH DH EH FH 91CW18A-241 2005-08-15 TMP91CW18A [3] CS/WAIT Address 00C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [4] CGEAR Register B0CS B1CS B2CS B3CS BEXCS MSAR0 MAMR0 MSAR1 MAMR1 MSAR2 MAMR2 MSAR3 MAMR3 Address 00E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register SYSCR0 SYSCR1 SYSCR2 EMCCR0 EMCCR1 (Reserved) 91CW18A-242 2005-08-15 TMP91CW18A [5] TMR8 Address 0100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [6] TMR16 Register TA01RUN TA0REG TA1REG TA01MOD TA1FFCR Address 0110H 1H 2H 3H 4H 5H 6H 7H Register TA45RUN TA4REG TA5REG TA45MOD TA5FFCR TA23RUN TA2REG TA3REG TA23MOD TA3FFCR 8H 9H AH BH CH DH EH FH TA67RUN TA6REG TA7REG TA67MOD TA7FFCR Address 0180H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register TB0RUN TB0MOD TB0FFCR TB0RG0L TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H TB0CP1L TB0CP1H 91CW18A-243 2005-08-15 TMP91CW18A [7] UART [8] I C bus/SIO 2 [9] I C bus 2 Address 0200H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [10] 12-bit ADC Register SC0BUF SC0CR SC0MOD0 BR0CR BR0ADD SC0MOD1 Address 0240H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register SBI0CR10 SBI0DBR0 I2C0AR0 SBI0CR20/SBISR0 SBI0BR00 SBI0BR10 Address 0250H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register SBI0CR11 SBI0DBR1 I2C0AR1 SBI0CR21/SBISR1 SBI0BR01 SBI0BR11 SBI0CR12 SBI0DBR2 I2C0AR2 SBI0CR22/SBISR2 SBI0BR02 SBI0BR12 Address 02A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register ADREGAL ADREGAH ADREGBL ADREGBH ADREGCL ADREGCH ADREGDL ADREGDH Address 02B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register ADMOD0 ADMOD1 (Reserved) 91CW18A-244 2005-08-15 TMP91CW18A [11] WDT Address 0300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Register WDMOD WDCR 91CW18A-245 2005-08-15 TMP91CW18A (1) I/O port Symbol P0 Name Port 0 Address 00H P17 P1 Port 1 01H P27 P2 Port 2 06H P37 P3 Port 3 07H P36 P35 P34 P26 P25 P24 R/W Data from external port (Output latch register is set to 1) P33 P32 P31 1 − P41 R Data from external port P57 P5 Port 5 0DH P56 P55 P54 R Data from external port P62 P6 Port 6 12H P61 R/W Data from external port (Output latch register is set to 1) P76 P7 Port 7 13H P87 P8 Port 8 18H P86 P85 P84 R/W Data from external port (Output latch register is set to 1) P75 P74 P73 R/W Data from external port (Output latch register is set 1) P83 P82 P81 P80 P72 P71 P70 P60 P53 P52 P51 P50 P40 P30 1 R/W Data from external port (Output latch register is set to 1) − 0 (Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON 7 P07 6 P06 5 P05 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 Data from external port (Output latch register becomes undefined) P16 P15 P14 R/W Data from external port (Output latch register is cleared to 0) P23 P22 P21 P20 P13 P12 P11 P10 P43 P4 Port 4 0CH P42 91CW18A-246 2005-08-15 TMP91CW18A (2) I/O port control (1/2) Symbol Name Port 0 control Address 02H (Prohibit RMW) 04H (Prohibit RMW) 05H (Prohibit RMW) 0AH (Prohibit RMW) 7 P07C 0 P17C 0 P17F 0 P37C 0 P37F P3FC Port 3 function 0BH (Prohibit RMW) W 0 0: Port 1: INT4 Port 3 6 P06C 0 P16C 0 P16F 0 P36C 0 P36F W 0 0: Port 1: TA7OUT 5 P05C 0 P15C 0 P15F 0 P35C 0 4 P04C W 0 P14C W 0 P14F W 0 P34C W 0 3 P03C 0 P13C 0 P13F 0 P33C 0 2 P02C 0 P12C 0 P12F 0 P32C 0 P32F 0 0: Port 1: HWR 1 P01C 0 P11C 0 P11F 0 P31C 1 P31F W 0 0: Port 1: WR P31ODE 0 P61C W 0 0: Input 1: Output P61F W 0 0: Port 1: INT1 0 P00C 0 P10C 0 P10F 0 P30C 1 P30F 0 0: Port 1: RD P30ODE 0 P60C 0 P60F 0 0: Port 1: INT0 P0CR 0: Input 1: Output (When access to external, it is cleared to “0”) P1CR Port 1 control 0: Input 1: Output P1FC Port 1 function P1CR/P1FC = 00: Input port, 01: D8 to D15, 10: AD8 to AD15, 11: A8 to A15 P3CR Port 3 control 0: Input 1: Output 2DH P37ODE 0 P36ODE 0 P35ODE 0 P34ODE 0 P33ODE R/W 0 P32ODE 0 P62C 0 P62F P3ODE open-drain (Prohibit RMW) enable 14H (Prohibit RMW) 0: Normal 1: Opendrain P6CR Port6 control P6FC Port6 function 15H (Prohibit RMW) 0 0: Port 1: INT2 SCOUTE 1DH (Prohibit RMW) P76C 0 P76F P75C 0 P75F W 0 0: Port 1: SCK0 SCOUTC SCOUT control W 0 0: Port 1: SCOUT P74C W 0 0 0: Input 1: Output P72F 0 0: Port 1: TA5OUT P7CR Port 7 control 16H (Prohibit RMW) P73C P72C 0 P71C 0 P71F W 0 0: Port 1: TA3OUT P70C 0 P70F 0 0: Port 1: TA1OUT P7FC Port 7 function 17H (Prohibit RMW) 0 0: Port 1: TB0OUT0 INT3E Interrupt IIEC input enable control 1CH (Prohibit RMW) W 0 0: Port 1: INT3 INT6E W 0 0: Port 1: INT6 TB0IN1 INT5E 0 0: Port 1: INT5 TB0IN0 91CW18A-247 2005-08-15 TMP91CW18A I/O port control (2/2) Symbol Name Port 8 control Address 1AH (Prohibit RMW) 7 P87C 0 P87F Port 8 function 1BH (Prohibit RMW) 0 0: Port 1: SCL2 6 P86C 0 P86F W 0 0: Port 1: SDA2 0 0: Port 1: SCL1 0 0: Port 1: SDA1 P83ODE 2FH 0 0 0: Port 1: TXD0 P82ODE 0 5 P85C 0 P85F 4 P84C W 0 P84F 0 0 P82F 0 P81F W 0 0: Port 1: SCL0 P81ODE 0 0 0: Port 1: SDA0 1: SO0 Port 8 3 P83C 2 P82C 1 P81C 0 P80C 0 P80F P8CR 0: Input 1: Output P8FC P80ODE 0 P8ODE open-drain enable R/W 0: Normal 1: Opendrain 91CW18A-248 2005-08-15 TMP91CW18A (3) Interrupt control (1/4) Symbol Name Address 7 IADC 90H R 0 1: INTAD INT1 INTE12 INT2 enable 91H I2C R 0 1: INT2 INT3 INTE34 INT4 enable 92H I4C R 0 1: INT4 INT5 INTE56 INT6 enable 93H I6C R 0 1: INT6 0 0 INT6 I6M2 I6M1 R/W 0 0 Interrupt request level I6M0 I5C R 0 1: INT5 0 I5M2 0 INT4 I4M2 I4M1 R/W 0 0 Interrupt request level I4M0 I3C R 0 1: INT3 0 INT5 I5M1 R/W 0 0 Interrupt request level I5M0 I3M2 0 INT2 I2M2 I2M1 R/W 0 0 Interrupt request level I2M0 I1C R 0 1: INT1 0 INT3 I3M1 R/W 0 0 Interrupt request level I3M0 I1M2 6 INTAD INTE0AD INTAD enable IADM2 IADM1 R/W 0 0 Interrupt request level IADM0 I0C R 0 1: INT0 0 INT1 I1M1 R/W 0 0 Interrupt request level I1M0 I0M2 5 4 3 2 INT0 I0M1 R/W 0 0 Interrupt request level I0M0 1 0 91CW18A-249 2005-08-15 TMP91CW18A Interrupt control (2/4) Symbol Name INTTA0 INTETA01 INTTA1 enable 95H Address 7 IT1C R 0 1: INTT1 INTTA2 INTETA23 INTTA3 enable 96H IT3C R 0 1: INTT3 INTTA4 INTETA45 INTTA5 enable 97H IT5C R 0 1: INTT5 INTTA6 INTETA67 INTTA7 enable 98H IT7C R 0 1: INTT7 ITB01C 6 IT1M2 0 5 IT1M1 R/W 0 4 IT1M0 0 3 IT0C R 0 1: INTT0 IT2C R 0 1: INTT2 IT4C R 0 1: INTT4 IT6C R 0 1: INTT6 ITB00C 2 IT0M2 0 1 IT0M1 R/W 0 0 IT0M0 0 INTT1 (TMRA1) INTT0 (TMRA0) Interrupt request level INTT3 (TMRA3) IT3M2 0 IT3M1 R/W 0 0 Interrupt request level INTT5 (TMRA5) IT5M2 0 IT5M1 R/W 0 0 Interrupt request level INTT7 (TMRA7) IT7M2 0 IT7M1 R/W 0 0 Interrupt request level INTTB01 (TMRB0) ITB01M2 ITB01M1 ITB01M0 Interrupt request level INTT2 (TMRA2) IT2M2 R/W 0 0 0 Interrupt request level INTT4 (TMRA4) IT4M2 0 IT4M1 R/W 0 0 Interrupt request level INTT6 (TMRA6) IT6M2 0 IT6M1 R/W 0 0 Interrupt request level INTTB00 (TMRB0) ITB00M2 ITB00M1 ITB00M0 IT3M0 IT2M1 IT2M0 IT5M0 IT4M0 IT7M0 IT6M0 INTETB0 TMRB0 enable 99H R 0 1: INTTB01 R/W 0 0 Interrupt request level R 0 0 1: INTTB00 R/W 0 0 Interrupt request level 0 (Reserved) TMRB0 INTETB0OV INTTBOF0 (TMRB0 over flow) ITF0C ITF0M2 0 INTRX0 ITX0M0 0 IRX0C R 0 1: INTRX0 0 INTI2C2 INTI2C2C II2C2M2 II2C2M1 R/W 0 0 0 Interrupt request level II2C2M0 R 0 1: INTI2C2 IRX0N2 IRX0M1 R/W 0 0 Interrupt request level IRX0M0 ITF0M1 R/W 0 0 Interrupt request level ITF0M0 R 0 1: INTTO8 enable (Overflow) 9BH INTTX0 INTUART UART enable ITX0C 9CH R 0 1: INTTX0 0 ITX0M2 ITX0M1 R/W 0 (Reserved) INTES2 INTI2C2 enable 9DH Interrupt request level 91CW18A-250 2005-08-15 TMP91CW18A Interrupt control (3/4) Symbol Name INTI2C1 INTES1 SBI0 enable 9EH Address 7 INTI2C1C 6 INTI2C1 II2C1M2 5 II2C1M1 4 II2C1M0 3 IS0C 2 INTSBI0 IS0M2 1 IS0M1 0 IS0M0 R 0 1: INTI2C1 R/W 0 INTTC1 0 0 Interrupt request level ITC1M2 0 INTTC3 ITC1M1 R/W 0 0 Interrupt request level ITC3M2 0 ITC3M1 R/W 0 0 Interrupt request level ITC3M0 ITC1M0 R 0 1: INTSBI R/W 0 INTTC0 0 0 Interrupt request level ITC0M2 0 INTTC2 ITC0M1 R/W 0 0 Interrupt request level ITC2M2 0 ITC2M1 R/W 0 0 Interrupt request level ITC2M0 ITC0M0 INTTC0 INTETC01 INTTC1 enable A0H ITC1C R 0 1: INTTC1 ITC0C R 0 1: INTTC0 INTTC2 INTETC23 INTTC3 enable A1H ITC3C R 0 1: INTTC3 ITC2C R 0 1: INTTC2 91CW18A-251 2005-08-15 TMP91CW18A Interrupt control (4/4) Symbol Name DMA0 DMA0V request vector DMA1 DMA1V request vector DMA2 DMA2V request vector DMA3 DMA3V request vector Interrupt INTCLR clear control DMA DMAR software request register DMA DMAB burst request register − Input IIMC mode control 8CH (Prohibit RMW) 0 Always write 0 Address 7 6 5 4 3 R/W 2 1 0 DMA0V0 0 DMA1V0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 80H 0 DMA1V5 0 DMA1V4 0 DMA1V3 0 DMA1V2 0 DMA1V1 DMA0 start vector R/W 0 DMA2V5 81H 0 DMA2V4 0 DMA2V3 0 DMA2V2 0 DMA2V1 0 DMA2V0 DMA1 start vector R/W 0 DMA3V5 82H 0 DMA3V4 0 DMA3V3 0 DMA3V2 0 DMA3V1 0 DMA3V0 DMA2 start vector R/W 0 CLRV5 0 0 CLRV4 0 0 CLRV3 W 0 DMAR3 89H 0 DMAB3 8AH 0 I4EDGE 0 0: Rising 1: Falling 83H 0 CLRV2 0 DMAR2 0 DMAB2 0 I0EDGE 0 0: Rising 1: Falling 0 CLRV1 0 DMAR1 0 DMAB1 0 I0LE 0 0: Edge 1: Level 0 CLRV0 0 DMAR0 0 DMAB0 0 NMIREE 0 edge rising operation DMA3 start vector 88H (Prohibit RMW) Interrupt request clear by DMA start vector R/W 1: Soft request of DMA R/W 1: Burst transfer of DMA I3EDGE 0 0: Rising 1: Falling I2EDGE W 0 0: Rising 1: Falling I1EDGE 0 0: Rising 1: Falling INT4 edge INT3 edge INT2 edge INT1 edge INT0 edge INT0 edge 1: NMI 91CW18A-252 2005-08-15 TMP91CW18A (4) Wait control (1/2) Symbol Name Address 7 B0E W Block 0 B0CS WAIT control register (Prohibit 0: Disable RMW) 1: Enable C0H 0 0 Always write 0 0 0 Data bus width selection 0: 16 bits 1: 8 bits B1E W Block 1 B1CS WAIT control register (Prohibit 0: Disable RMW) 1: Enable C1H 0 − W 0 Always write 0 − W 0 B1BUS W 0 Data bus width selection 0: 16 bits 1: 8 bits B2E W Block 2 B2CS WAIT control register C2H 1 B2M W 0 − W 0 Always write 0 − W 0 B2BUS W 0 Data bus width selection 0: 16 bits 1: 8 bits B3E W Block 3 B3CS WAIT control register (Prohibit 0: Disable RMW) 1: Enable C3H 0 − W 0 Always write 0 − W 0 B3BUS W 0 Data bus width selection 0: 16 bits 1: 8 bits BEXBUS W External BEXCS WAIT control register C7H (Prohibit RMW) 0 Data bus width selection 0: 16 bits 1: 8 bits 6 5 − 4 − 3 B0BUS W 0 0 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits Others : Reserved B1W2 W 0 B1W1 W 0 B1W0 W 0 2 B0W2 1 B0W1 0 B0W0 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits Others : Reserved B2W2 W 0 B2W1 W 0 B2W0 W 0 (Prohibit 0: Disable 0: 16 M -area RMW) 1: Enable 1: Area setting 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits Others : Reserved B3W2 W 0 B3W1 W 0 B3W0 W 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits Others : Reserved BEXW2 W 0 BEXW1 W 0 BEXW0 W 0 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits Others : Reserved 91CW18A-253 2005-08-15 TMP91CW18A Chip select/wait control (2/2) Symbol Name Memory MSAR0 start address register 0 Memory MAMR0 address mask register 0 Memory MSAR1 start address register 1 Memory MAMR1 address mask register 1 Memory MSAR2 start address register 2 Memory MAMR2 address mask register 2 Memory MSAR3 start address register 3 Memory MAMR3 address mask register 3 CFH V22 1 V21 1 CEH S23 1 S22 1 CDH V22 1 V21 1 CCH S23 1 S22 1 CBH V21 1 V20 1 CAH S23 1 S22 1 C9H V20 1 V19 1 C8H Address 7 S23 1 6 S22 1 5 S21 1 V18 1 Set size of CS0 S21 1 V19 1 Set size of CS1 S21 1 V20 1 Set size of CS2 S21 1 V20 1 Set size of CS3 4 S20 R/W 1 V17 R/W 1 S20 R/W 1 V18 R/W 1 S20 R/W 1 V19 R/W 1 S20 R/W 1 V19 R/W 1 1 1 1 1 0: used for address compare 1 V18 1 V17 1 V16 1 V15 Determines A23 to A16 of start address 1 S19 1 S18 1 S17 1 S16 0: used for address compare 1 V18 1 V17 1 V16 1 V15 Determines A23 to A16 of start address 1 S19 1 S18 1 S17 1 S16 0: used for address compare 1 V17 1 V16 1 V15 to 9 1 V8 Determines A23 to A16 of start address 1 S19 1 S18 1 S17 1 S16 0: used for address compare 1 V16 1 V15 1 V14 to 9 1 V8 Determines A23 to A16 of start address 3 S19 2 S18 1 S17 0 S16 91CW18A-254 2005-08-15 TMP91CW18A (5) Clock gear Symbol Name Address 7 XEN 1 Highfrequency oscillator (fc) 6 − 0 Always write 0 5 RXEN 1 4 − R/W 0 3 − 0 Always write 0 2 WUEF 0 Warm-up timer 1 PRCK1 0 00: fFPH 0 PRCK0 0 System SYSCR0 clock control register 0 E0H 0: Stop 1: Oscillation HighAlways frequency write 0 oscillator (fc) after release of Stop mode 0: Stop 1: Oscillation Select prescaler clock 01: fc Write 0: Don’t care 10: fc/16 11: Reserved Write 1: start timer Read 0: end warm up Read 1: do not end warm up − 0 System SYSCR1 clock control register 1 E1H Always write 0 GEAR2 0 GEAR1 0 GEAR0 0 R/W Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) SCOSEL WUPTM1 WUPTM0 HALTM1 HALTM0 R/W 0 System SYSCR2 clock control register 2 E2H 0: fs 1: fFPH DRVE R/W 0 Pin state control in STOP mode 0: I/O off 1: Remain the state before HALT DRVOSCH R/W 1 Warm-up timer 00: Reserved 01: 28/inputted frequency 10: 214 11: 216 R/W 0 R/W 1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode PROTECT − R/W 0 write 0 − R/W 1 Always write 1 − R/W 0 Always write 0 ALEEN R/W 0 EXTIN R/W 0 − R/W 1 Always write 1 EMC EMCCR0 control register 0 E3H R 0 R/W 1 1: Protected Always ALE output fc external fc OSC enable clock 1: Normal 0: Weak EMC EMCCR1 control register 1 E4H Protection is turned OFF by writing 1FH. Protection is turned ON by writing any value other than 1FH. 91CW18A-255 2005-08-15 TMP91CW18A (6) 8-bit timer (1/4) (6-1) TMRA01 Symbol Name Address 7 TA0RDE R/W TA01RUN Timer RUN 100H 0 Double buffer 0: Disable 1: Enable 8-bit TA0REG timer register 0 8-bit TA1REG timer register 1 8-bit timer TA01MOD source CLK and mode 104H 102H (Prohibit RMW) 103H (Prohibit RMW) TA01M1 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM TA01M0 0 PWM01 0 00: Reserved 01: 2 PWM cycle 10: 2 11: 2 7 8 6 6 5 4 3 I2TA01 R/W 0 IDLE2 0: Stop 2 R/W 0 0:Stop and clear 1 R/W 0 0 TA0RUN R/W 0 TA01PRUN TA1RUN 8-bit timer run/stop control 1: Operate 1:Run (Count up) − W Undefined − W Undefined PWM00 0 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 0 00: TA0TRG 01: φT1 10: φT16 11: φT256 TA1FFC1 TA1FFC0 0 0 00: Reserved 01: φT1 10: φT4 11: φT16 TA1FFIE 0 1: TA1FF invert enable TA1FFIS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 R/W 0 R/W 8-bit TA1FFCR timer flip-flop control 105H (Prohibit RMW) 1 01: Set TA1FF 1 00: Invert TA1FF 10: Clear TA1FF 11: Don’t care 91CW18A-256 2005-08-15 TMP91CW18A 8-bit timer (2/4) (6-2) TMRA23 Symbol Name Address 7 TA2RDE R/W TA23RUN Timer RUN 108H 0 Double buffer 0: Disable 1: Enable 8-bit TA2REG timer register 0 8-bit TA2REG timer register 1 8-bit timer TA23MOD source CLK and mode 10CH 10AH (Prohibit RMW) 10BH (Prohibit RMW) TA23M1 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM TA23M0 0 PWM21 0 00: Reserved 01: 2 PWM cycle 10: 2 11: 2 7 8 6 6 5 4 3 I2TA23 R/W 0 IDLE2 0: Stop 2 R/W 0 1 R/W 0 0 TA2RUN R/W 0 TA23PRUN TA3RUN 8-bit timer run/stop control 0: Stop and clear 1: Operate 1: Run (Count up) － W Undefined － W Undefined PWM20 0 TA3CLK1 R/W 0 00: TA2TRG 01: φT1 10: φT16 11: φT256 TA3FFC1 TA3FFC0 1 0 0 00: Reserved 01: φT1 10: φT4 11: φT16 TA3FFIE 0 1: TA3FF invert enable TA3FFIS 0 TA1FF inversion select 0: TMRA2 1: TMRA3 R/W 0 TA3CLK0 TA2CLK1 TA2CLK0 8-bit TA3FFCR timer flip-flop control 10DH (Prohibit RMW) 1 01: Set TA3FF 00: Invert TA3FF 10: Clear TA3FF 11: Don’t care 91CW18A-257 2005-08-15 TMP91CW18A 8-bit timer (3/4) (6-3) TMRA45 Symbol Name Address 7 TA4RDE R/W TA45RUN Timer RUN 110H 0 Double buffer 0: Disable 1: Enable 8-bit TA4REG timer register 0 8-bit TA5REG timer register 1 8-bit timer TA45MOD source CLK and mode 114H 112H (Prohibit RMW) 113H (Prohibit RMW) TA45M1 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM TA45M0 0 PWM41 0 00: Reserved 01: 2 PWM cycle 10: 2 11: 2 7 8 6 6 5 4 3 I2TA45 R/W 0 IDLE2 0: Stop 2 R/W 0 1 R/W 0 0 TA4RUN R/W 0 TA45PRUN TA5RUN 8-bit timer run/stop control 0: Stop and clear 1: Operate 1: Run (Count up) − W Undefined − W Undefined PWM40 0 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0 0 00: TA4TRG 01: φT1 10: φT16 11: φT256 TA5FFC1 TA5FFC0 0 0 00: Reserved 01: φT1 10: φT4 11: φT16 TA5FFIE 0 1: TA5FF invert enable TA5FFIS 0 TA5FF inversion select 0: TMRA4 1: TMRA5 R/W 0 R/W 8-bit TA5FFCR timer flip-flop control 115H (Prohibit RMW) 1 01: Set TA5FF 1 00: Invert TA5FF 10: Clear TA5FF 11: Don’t care 91CW18A-258 2005-08-15 TMP91CW18A 8-bit timer (4/4) (6-4) TMRA67 Symbol Name Address 7 TA6RDE R/W TA67RUN Timer RUN 118H 0 Double buffer 0: Disable 1: Enable 8-bit TA6REG timer register 0 8-bit TA7REG timer register 1 8-bit timer TA67MOD source CLK and mode 11CH 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 00: Reserved 01: 2 PWM cycle 10: 2 11: 2 7 8 6 6 5 4 3 R/W 0 IDLE2 0: Stop 2 R/W 0 1 R/W 0 0 TA6RUN R/W 0 I2TA67 TA67PRUN TA7RUN 8-bit timer run/stop control 0: Stop and clear 1: Operate 1: Run (Count up) － W Undefined － W Undefined 11AH (Prohibit RMW) 11BH (Prohibit RMW) TA67M1 TA67M0 PWM61 PWM60 0 TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0 0 00: TA6TRG 01: φT1 10: φT16 11: φT256 TA7FFC1 TA7FFC0 0 0 (TA6IN) 01: φT1 10: φT4 11: φT16 TA7FFIE 0 1: TA7FF invert enable TA7FFIS 0 TA7FF inversion select 0: TMRA6 1: TMRA7 R/W 0 R/W 00: External input 8-bit TA7FFCR timer flip-flop control 11DH (Prohibit RMW) 1 01: set TA7FF 1 00: Invert TA7FF 10: Clear TA7FF 11: Don’t care 91CW18A-259 2005-08-15 TMP91CW18A (7) 16-bit timer (7-1) TMRB0 Symbol Name Address 7 TB0RDE R/W TB0RUN Timer control 180H 0 Double buffer 0: Disable 1: Enable TB0CT1 16-bit timer TB0MOD source CLK and mode CAP1 TREG1 matching W* 1 16-bit TB0FFCR timer flip-flop control 183H (Prohibit RMW) 01: Set 10: Clear 11: Don't care “Always read as 0 1 0 0 00: Invert TB0FF1 182H (Prohibit RMW) 0 TB0ET1 0 TB0CP0I TB0CPM1 TB0CPM0 W* 1 0: Softcapture 1: Undefined 6 － R/W 0 Always write 0 5 4 3 I2TB0 R/W 0 IDLE2 0: Stop 2 TB0PRUN R/W 0 1 0 TB0RUN R/W 0 16-bit timer run/stop control 0: Stop and clear 1: Operate 1: Run (Count up) TB0CLE R/W 0 Capture timing (TB0IN0, TB0IN1) 00: Disable 01: ↑, ↓ 10: ↑, ↓ 11: ↑, ↓ (TA1OUT) TB0E1T1 0 TB0E0T1 TB0FF0C1 TB0FF0C0 W* 0 1 01: Set 10: Clear Invert when the UC value matches the value in TB0RG1. Invert when 11: Don't care the UC value “Always read as 0 matches the value in TB0RG0. TB0CLK1 TB0CLK0 0 Source clock 00: TB0IN0 input 01: φT1 10: φT4 11: φT16 0 R/W TB0FF1 INV TRG 0: TRG disable 1: TRG enable 0 0 1: TB0UC clear enable TB0FF1C1 TB0FF1C0 TB0C1T1 TB0C0T1 R/W TB0FF0 inversion trigger 0: Disable trigger 1: Enable trigger Invert when the UC value is loaded in to TB0CP1. Invert when the UC value is loaded in to TB0CP0. 1 00: Invert TB0FF0 16-bit TB0RG0L timer register 0 L 16-bit TB0RG0H timer register 0 H 16-bit TB0RG1L timer register 1 L 16-bit TB0RG1H timer register 1 H TB0CP0L Capture register 0 L Capture register 0 H Capture register 1 L Capture register 1 H 188H (Prohibit RMW) 189H (Prohibit RMW) 18AH (Prohibit RMW) 18BH (Prohibit RMW) 18CH − W Undefined − W Undefined − W Undefined − W Undefined − R Undefined − TB0CP0H 18DH R Undefined − TB0CP1L 18EH R Undefined − TB0CP1H 18FH R Undefined 91CW18A-260 2005-08-15 TMP91CW18A (8) UART (8-1) UART Symbol Name Serial SC0BUF channel 0 buffer Address 200H (Prohibit RMW) RB8 Serial SC0CR channel 0 control 201H R Undefined Receive data bit TB8 0 Serial SC0MOD0 channel 0 mode 0 202H bit8 0 Parity 0: Odd 1: Even CTSE 0 shake 0: CTS disable 1: CTS enable － 0 BR0CR Baud rate control 203H Always write 0 BR0ADDE BR0CK1 0 divided frequency 0: Disable 1: Enable Serial BR0ADD channel 0 K setting register I2S0 Serial SC0MOD1 channel 0 mode 1 205H R/W 0 IDLE2 0: Stop 1: Run − R/W 0 Always write 0 204H BRA0K3 0 BRA0K2 0 BRA0K1 0 BRA0K0 0 R/W Sets the frequency divisor “K” (Divided by N + (16 − K)/16) 0 01: φT2 (16/fc) 10: φT8 (64/fc) 11: φT32 (256/fc) BR0CK0 R/W 0 0 0 (0 to F) 0 0 (16 − K)/16 00: φT0 (4/fc) Setting the dividied frequency “N” BR0S3 BR0S2 BR0S1 BR0S0 RXE 0 WU R/W 0 0 0 0 0 Send data Hand 1: Receive 1: Wakeup 00: Reserved enable enable 01: UART 7 bits 10: UART 8 bits 11: UART 9 bits 00: TA0OUT trigger 01: Baud rate generator 10: Internal clock fSYS 11: Reserved SM1 SM0 SC1 SC0 EVEN PE R/W 0 1: Parity enable Overrun 0 7 RB7/TB7 6 RB6/TB6 5 RB5/TB5 4 RB4/TB4 3 RB3/TB3 2 RB2/TB2 1 RB1/TB1 0 RB0/TB0 R (Receiving)/W (Transmission) Undefined OERR PERR 0 1:Error Parity Framing FERR 0 − R/W 0 Always write 0 − R/W 0 Always write 0 R (Cleared to 0 by reading) 91CW18A-261 2005-08-15 TMP91CW18A (9) I2C bus/SIO (1/2) Symbol Name Address 7 BC2 6 BC1 5 BC0 4 ACK 3 2 SCK2 1 SCK1 0 SCK0/ SWRMON W W R/W 0 0 0/1 Selection of Serial clock frequency 000: 5 100: 9 001: 6 101: 10 010: 7 110: 11 011: 8 111: Reserved SCK2 SCK1 SCK0 W W W 0 0 0 Selection of serial clock frequency 000: 4 100: 8 001: 5 101: 9 010: 6 110: 10 011: 7 111: Reserved DB1 DB0 240H W R/W 2 (I C bus 0 0 0 0 mode) Number of transferred bit Acknowledge (Prohibit 000: 8, 100: 4 mode 001: 1, 101: 5 Serial bus RMW) 0: Disable 010: 2, 110: 6 interface 1: Enable 011: 3, 111: 7 SBI0CR10 control SIOS SIOINH SIOM1 SIOM0 register 10 W W W W 240H 0 0 0 0 (SIO Transfer Continue/ Transfer mode select mode) start aboard 00: 8-bit transmit (Prohibit 0: End transfer 10: 8-bit transmit/ RMW) 1: Start 0: Continue receive 1: Stop 11: 8-bit receive SBI0DBR0 SBI buffer register 0 241H (Prohibit RMW) DB7 DB6 DB5 DB4 DB3 DB2 R (Receiving)/W (Transmission) Undefined SA1 W 0 SA6 W 0 I C Bus I2C0AR0 address register 0 2 SA5 W 0 SA4 W 0 242H (Prohibit RMW) SA3 SA2 W W 0 0 Set of slave address SA0 W 0 ALS W 0 Address recognition mode 1: No 0: Slave address Serial bus 243H 2 interface (I C bus Write control mode) SBI0CR20 register (Prohibit 20 RMW) MST W 0 Master/ Slave selection 0: Slave 1: Master TRX W 0 Transfer/ receiver selection 0: Receive 1: Transfer BB W 0 Start/stop condition generation 0: Stop 1: Start PIN W 1 INTSBI0 interrupt request cancel 0: Don’t care 1: Cancel PIN R 1 INTSBI0 request monitor 0: Request 1: Cancel SBIM1 W 0 SBIM0 W 0 SWRST1 W 0 SWRST0 W 0 Serial bus interface operating mode selection 00: Port mode 01: SIO mode 2 10: I C bus mode 11: Reserved AL R 0 Arbitration lost detection monitor 1: Detect AAS R 0 Slave address match detection monitor 1: Detect Software reset generate write 10 and 01, then an internal reset signal is generated 243H Serial bus 2 (I C bus 0: Slave Read interface mode) 1: Master SBISR0 status (Prohibit register 0 RMW) MST R 0 TRX R 0 2 BB R 0 AD0 R 0 General call detection monitor 1: Detect 0: Receive I C bus 1: Transfer status monitor 0: Free 1: Busy LRB R 0 End bit monitor 0: “0” 1: “1” 91CW18A-262 2005-08-15 TMP91CW18A I2C bus/SIO (2/2) Symbol Name Address 7 6 5 4 3 SBIM1 W Serial bus interface Write SBI0CR20 control register 2 243H (SIO mode) (Prohibit RMW) 1 1 Serial bus interface operating mode selection 00: Port mode 01: SIO mode 2 10: I C bus mode 11: Reserved SIOF R 0 Transfer monitor 0: End 1: Transfer − 244H (Prohibit RMW) W 0 Always write 0 P4EN Serial bus interface SBI0BR10 baud rate register 10 245H W 0 (Prohibit Internal RMW) clock 0: Disable 1: Enable I2SBI0 R/W 0 IDLE2 0: Stop 1: Operate − W 0 Always write 0 SEF R 0 Shift operate monitor 0: End 1: Shift 2 SBIM0 1 − W 0 Always write 0 0 − W 0 Always write 0 Read SBISR0 Serial bus interface status register 00 243H (SIO mode) (Prohibit RMW) Serial bus interface SBI0BR00 baud rate register 00 91CW18A-263 2005-08-15 TMP91CW18A (10) I2C bus 1 (1/2) Symbol Name Address 7 BC2 Serial bus SBI0CR11 interface control register 11 250H (Prohibit RMW) 0 000: 8 001: 1 010: 2 011: 3 6 BC1 W 0 100: 4 101: 5 110: 6 111: 7 0 mode 0: Disable 1: Enable 5 BC0 4 ACK R/W 0 Acknowledge 3 2 SCK2 W 0 000: 5 001: 6 010: 7 011: 8 1 SCK1 W 0 100: 9 101: 10 110: 11 0 SCK0/ SWRMON R/W 0/1 Number of transferred bit Selection of serial clock frequency 111: Reserved 91CW18A-264 2005-08-15 TMP91CW18A I2C bus 1 (2/2) Symbol SBI0DBR1 Name SBI buffer register 1 Address 251H (Prohibit RMW) SA6 W I C Bus I2C0AR1 address register 1 2 7 DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (Receiving)/W (Transmission) Undefined SA5 W 0 SA4 W 0 SA3 W 0 SA2 W 0 SA1 W 0 SA0 W 0 ALS W 0 Address recognition mode 1: No 0: Slave address 0 252H (Prohibit RMW) Set of slave address MST W Serial bus Write SBI0CR21 interface control register 21 253H (I C bus mode) (Prohibit RMW) 2 TRX W 0 Transfer/ receiver selection 0: Receive 1: Transfer BB W 0 Start/stop condition generation 0: Stop 1: Start PIN W 1 INTI2C1 interrupt request cancel 0: Don’t care 1: Cancel PIN R 1 INTI2C1 request monitor 0: Request 1: Cancel SBIM1 W 0 SBIM0 W 0 SWRST1 W 0 SWRST0 W 0 0 Master/ slave selection 0: Slave 1: Master Serial bus interface operating mode selection 00: Port mode 01: Reserved 2 10: I C bus mode 11: Reserved AL R 0 Arbitration lost detection monitor 1: Detect AAS R 0 Slave address match detection monitor 1: Detect Software reset generate write 10 and 01, then an internal reset signal is generated MST R Serial Read SBISR1 bus interface status register 1 253H (I C bus mode) (Prohibit RMW) 2 TRX R 0 2 BB R 0 AD0 R 0 General call detection monitor 1: Detect LRB R 0 End bit monitor 0: “0” 1: “1” 0 0: Slave 1: Master 0: Receive I C bus 1: Transfer status monitor 0: Free 1: Busy I2SBI0 R/W 0 IDLE2 0: Stop 1: Operate − W Serial bus interface SBI0BR01 baud rate register 01 254H (Prohibit RMW) − W 0 Always write 0 P4EN Serial bus interface SBI0BR11 baud rate register 11 W 255H 0 0 (Prohibit Internal Always RMW) clock write 0 0: Disable 1: Enable 91CW18A-265 2005-08-15 TMP91CW18A (11) I2C bus 2 (1/2) Symbol Name Address 7 BC2 6 BC1 W 258H (Prohibit RMW) 0 000: 8 001: 1 010: 2 011: 3 0 100: 4 101: 5 110: 6 111: 7 0 mode 0: Disable 1: Enable 5 BC0 4 ACK R/W 0 Acknowledge 3 2 SCK2 W 0 frequency 000: 5 001: 6 010: 7 011: 8 1 SCK1 W 0 0 SCK0/ SWRMON R/W 0/1 Serial bus interface SBI0CR12 control register 12 Number of transferred bit Selection of serial clock 100: 9 101: 10 110: 11 111: Reserved 91CW18A-266 2005-08-15 TMP91CW18A I2C bus 2 (2/2) Symbol SBI0DBR2 Name SBI buffer register 2 Address 259H (Prohibit RMW) SA6 W 0 I C Bus I2C0AR2 address register 2 2 7 DB7 6 DB6 5 DB5 4 DB4 3 DB3 2 DB2 1 DB1 0 DB0 R (Receiving)/W (Transmission) Undefined SA5 W 0 SA4 W 0 SA3 W 0 SA2 W 0 SA1 W 0 SA0 W 0 ALS W 0 Address recognition mode 1: No 0: Slave address MST W TRX W 0 Transfer/ receiver selection 0: Receive 1: Transfer BB W 0 Start/Stop condition generation 0: Stop 1: Start PIN W 1 INTI2C2 interrupt request cancel 0: Don’t care 1: Cancel PIN R 1 INTI2C2 request monitor 0: Request 1: Cancel SBIM1 W 0 operating mode selection 00: Port mode 01: Reserved 2 10: I C bus mode 11: Reserved AL R 0 Arbitration lost detection monitor 1: Detect AAS R 0 Slave address match detection monitor 1: Detect SBIM0 W 0 SWRST1 W 0 SWRST0 W 0 25AH (Prohibit RMW) Set of slave address Serial bus Write SBI0CR22 interface control register 22 Master/ (I C bus slave mode) selection (Prohibit 0: Slave RMW) 1: Master 2 25BH 0 Serial bus interface Software reset generate write “10” and “01”, then an internal reset signal is generated MST R Serial Read SBISR2 bus interface status register 2 25BH (I C bus mode) (Prohibit RMW) 2 TRX R 0 2 BB R 0 AD0 R 0 General call detection monitor 1: Detect LRB R 0 End bit monitor 0: “0” 1: “1” 0 0: Slave 1: Master 0: Receive I C bus 1: Transfer status monitor 0: Free 1: Busy I2SBI0 R/W 0 IDLE2 0: Stop 1: Operate − W 0 Always write 0 Serial bus SBI0BR02 interface baud rate register 02 Serial bus SBI0BR12 interface baud rate register 12 25DH (Prohibit RMW) 25CH (Prohibit RMW) − W 0 Always write 0 P4EN W 0 Internal clock 0: Disable 1: Enable 91CW18A-267 2005-08-15 TMP91CW18A (12) AD converter (1/2) Symbol Name Address 7 EOCF R AD ADMOD0 mode register 0 2B0H AD conversion end flag 1: End 6 ADBF 0 AD conversion bust flag 1: Busy 5 − R/W 0 4 − R/W 0 3 ITM0 R/W 0 repeat mode 2 REPEAT R/W 0 mode specific -ation 1: Repeat 1 SCAN R/W 0 Scan mode Specific -ation 1: Scan AD 0 ADS R/W 0 conversion start 1: Start 0 Always write 0 Interrupt in Repeat VREFON R/W 0 VREF control 1: VREF on AD ADMOD1 mode register 1 2B1H I2AD R/W 0 IDLE2 0: Abort 1: Operate ADTRGE R/W 0 1: Enable for start ADCH3 0 ADCH2 0 ADCH1 0 ADCH0 0 R/W AD control Input channel 0000: AN0 AN0 0001: AN1 AN0 → AN1 0011: AN3 AN0 → AN1 → AN2 → AN3 0100: AN4 AN4 0101: AN5 AN4 → AN5 0110: AN6 AN4 → AN5 → AN6 0111: AN7 AN4 → AN5 → AN6 1000: AN8 AN8 1001: AN9 AN9 1010: AN10 AN10 1011: AN11 AN11 1100: Reserved 1101: Reserved 1110: Reserved 1111: Reserved external 0010: AN2 AN0 → AN1 → AN2 91CW18A-268 2005-08-15 TMP91CW18A AD converter (2/2) Symbol Name Address 7 ADRA1 R 6 ADRA0 5 4 3 2 1 0 ADRARF R 0 1: Conversion result stored AD result ADREGAL register A low 2A0H Undefined Stores lower 2 bits of AD conversion result ADRA9 ADRA8 ADRA7 ADRA6 ADRA5 R Undefined Stores upper 8 bits of AD conversion result ADRB1 ADRB0 R ADRA4 ADRA3 AD result ADREGAH register A high 2A1H ADRA2 ADRBRF R 0 1: Conversion result stored ADRB7 ADRB6 ADRB5 R Undefined Stores upper 8 bits of AD conversion result ADRB4 ADRB3 ADRB2 AD result ADREGBL register B low 2A2H Undefined Stores lower 2 bits of AD conversion result ADRB9 ADRB8 AD result ADREGBH register B high 2A3H ADRC1 AD result ADREGCL register C low 2A4H R ADRC0 ADRCRF R 0 1: Conversion result stored ADRC7 ADRC6 ADRC5 R Undefined Stores upper 8 bits of AD conversion result ADRC4 ADRC3 ADRC2 Undefined Stores lower 2 bits of AD conversion result ADRC9 ADRC8 AD result ADREGCH register C high 2A5H ADRD1 AD result ADREGDL register D low 2A6H R ADRD0 ADRDRF R 0 1: Conversion result stored ADRD7 ADRD6 ADRD5 R Undefined Stores upper 8 bits of AD conversion result ADRD4 ADRD3 ADRD2 Undefined Stores lower 2 bits of AD conversion result ADRD9 ADRD8 AD result ADREGDH register D high 2A7H 91CW18A-269 2005-08-15 TMP91CW18A (13) Watchdog timer Symbol Name Address 7 WDTE R/W 1 WDT WDMOD mode register 300H 1: WDT 6 WDTP1 R/W 0 00: 2 /fSYS 10: 2 /fSYS 11: 2 /fSYS 21 19 15 5 WDTP0 R/W 0 4 3 2 I2WDT R/W 0 IDLE2 0: Abort 1: Operate 1 RESCR R/W 0 1: RESET connect internally WDT out to reset pin 0 − R/W 0 Always write 0 enable 01: 217/fSYS − WD control 301H (Prohibit RMW) W − B1H: WDT disable 4EH: WDT clear WDCR 91CW18A-270 2005-08-15 TMP91CW18A 6. Port Section Equivalent Circuit Diagrams • Reading the circuit diagrams The gate symbols used are essentially the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active (1) when the HALT mode setting register is set to STOP mode (e.g., when SYSCR2 = 0, 1) and the CPU executes the HALT instruction. When the drive enable bit SYSCR2 is set to 1, however, STOP will remains at 0. • The input protection resistances ranges from several tens of ohms to several hundreds of ohms. ■ P0 (AD0 to AD7), P1 (AD8 to AD15, A8 to A15), P2 (A16 to A23, A0 to A7), P6 and P7 VCC Output data P-ch Output enable STOP Input data N-ch I/O Input enable ■ P32 and P33 VCC Output data VCC Programmable pull-up resistance Output enable STOP Input data I/O Input enable 91CW18A-271 2005-08-15 TMP91CW18A ■ P4 (AN8 to AN11) and P5 (AN0 to AN7) Analog input channel select Analog input Input Input data Input enable ! P80 (SDA0/SO0), P81 (SCL0/SI0), P82 (TXD), P83 (RXD), P30 (RD), P31 (WR), P34, P35 (TA6IN), P36 (TA7OUT) and P37 (INT4) VCC Output data Open-drain output enable STOP Input data Input enable I/O ■ P84 (SDA1), P85 (SCL1), P86 (SDA2) and P87 (SCL2) Output data STOP Input data Input enable I/O ■ NMI NMI Schmitt trigger Input ■ AM0 to AM1 Input data Input 91CW18A-272 2005-08-15 TMP91CW18A ■ ALE VCC Internal ALE P-ch Output Output enable N-ch ■ RESET VCC P-ch Reset Schmitt trigger WDTOUT Reset enable Input ■ X1 and X2 Oscillator X2 High-frequency oscillation enable P-ch N-ch X1 Clock ■ VREFH and VREFL VREFON P-ch VREFH String resistance VREFL 91CW18A-273 2005-08-15 TMP91CW18A 7. Points of Note and Restrictions (1) Notation 1. 2. The notation for built-in I/O registers is as follows. Register symbol Example: TA01RUN denotes bit TA0RUN of register TA01RUN. Read-modify-write instructions An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. Example 1: SET Example 2: INC • Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# SUB (mem), R/# INC #3, (mem) Logic operations AND (mem), R/# XOR (mem), R/# OR (mem), R/# 3, (TA01RUN) ... Set bit3 of TA01RUN. 1, (100H) ... Increment the data at 100H. Examples of read-modify-write instructions on the TLCS-900 ADC (mem), R/# SBC (mem), R/# DEC #3, (mem) Bit manipulation operations STCF #3/A, (mem) RES #3, (mem) SET #3, (mem) CHG #3, (mem) TSET #3, (mem) Rotate and shift operations RLC RL SLA SLL RLD 3. (mem) (mem) (mem) (mem) (mem) RRC RR SRA SRL RRD (mem) (mem) (mem) (mem) (mem) fc, fFPH, fSYS and one state The clock frequency input on ins X1 and 2 is called fOSCH. The clock selected by DFMCR0 is called fc. The clock selected by SYSCR1 is called fFPH. The clock frequency give by fFPH divided by 2 is called fSYS. One cycle of fSYS is referred to as one state. 91CW18A-274 2005-08-15 TMP91CW18A (2) Points of note and restrictions 1. 2. 3. 4. AM0 and AM1 pins Fix these pins to VCC unless changing voltage. EMU0 and EMU1 Open pins. Reserved address areas The TMP91CW18A does not have any reserved areas. Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request and output of the system clock. 5. Programmable pull-up resistance The programmable pull-up resistor can be turned ON/OFF by a program when the ports are set for use as input ports. When the ports are set for use as output ports, they cannot be turned ON/OFF by a program. The data registers (e.g., P3) are used to turn the pull-up/pull-down resistors ON/OFF. Consequently read-modify-write instructions are prohibited. 6. Watchdog timer The watchdog timer starts operation immediately after a reset is released. When the watchdog timer is not to be used, disable it. When the bus is released, neither internal memory nor internal I/O can be accessed. However, the internal I/O continues to operate. Hence the watchdog timer continues to run. Therefore be careful about the bus releasing time and set the detection timer of watchdog timer. 7. AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption. When STOP mode is used, disable the resistor using the program before the HALT instruction is executed. 8. CPU (Micro DMA) Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers in the CPU (e.g., the transfer source address register (DMASn)). 9. Undefined SFR The value of an undefined bit in an SFR is undefined when read. 10. POP SR instruction Please execute the POP SR instruction during DI condition. 11. Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0 to INT4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is applicable to this case.) (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally and the interrupt with higher priority is handled first followed by the other interrupt. 91CW18A-275 2005-08-15 TMP91CW18A 8. Package Dimensions P-QFP80-1420-0.80B Unit: mm 91CW18A-276 2005-08-15