TMP91FU62DFG

16 Bit Microcontroller TLCS-900/L1 Series TMP91FU62FG TMP91FU62DFG Revision 1.1 TOSHIBA CORPORATION The information contained herein is subject to change without notice. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. Please contact your sales representative for product-by-product details in this document regarding RoHS comaptibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate ths inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. © 2007 TOSHIBA CORPORATION All Rights Reserved TMP91FU62 Revision History Date 2007/01/18 Revision 0.2 TENTATIVE Table 1-1 Pin Names and Functions ・WAIT pin deletion. ・HV-monitor → EMU0 ・P00-P07 large-current port 2.1 RESET 10 system clocks　 16us → 1us 2.3.4 Prescaler Clock Controller Table 4-1 Port Functions Table 4-2 I/O Port Setting List 4.3 Port3 (P30 to P33) Deleted The input function of wait control(WAIT) Deleted Note2. P40 to P43 function Table. 4.9.1 Port 90 (TXD0/RXD0), 93 (TXD1/RXD0) 4.9.2 Port91(RXD0/TXD0), 94 (RXD1/TXD1) PB0 to PB2 function Table. 4.12 Open-drain Control 4.13 Serial channel pin change Control 14.1 Absolute Maximum Ratings Table 2-7 Source of Halt State Clearance and Halt Clearance Operation Table 4-2 I/O Port Setting List (Port B) 4.1 Port 0 (P00 to P07) 4.2 Port 1 (P10 to P17) 4.4 Port 4 (P40 to P43) Figure 4-12 Port72 4.13 Serial channel pin change/ Open-drain output Control Table 6-1 Registers and Pins for TMRB 9. 10-bit AD Converter (ADC) VREFH → AVCC 2007/04/27 0.4 Figure 9-4 Analog Input Voltage and AD Conversion Result (Typ.) 13.6.10 Programming the Flash Memory by the Internal CPU ･ Read Values in Product ID Mode ･ Example: Program to be loaded and executed in RAM 14.2 DC Electrical Characteristics Low-level output current 14.3 AD Conversion Characteristics Deleted Analog current for analog reference voltage 15.Table of SFR’s Deleted P4FC register TMP91FU62 Date 2007/06/07 Revision 0.5 14.1 Absolute Maximum Ratings IOL, IOH is corrected 14.2 DC Electrical Characteristics ICC, IDDP-P is corrected 2007/8/27 1.0 DMAR register (89H) is corrected by RWM prohibition. 17.2 Points of note j. Releasing the HALT mode by requesting an interruption is deleted. 2.3.2 Note3 is added 7.2.1 Plescaler is corrected, and Table 7-2 is corrected 7.3 Note2 and Note3 are added 17.2 Points of note 　j.Clocks for serial channels (SIO)　is added 6.3 SFR 15. Table of SFR’s TB0FFCR, TB1FFCR, TB2FFCR and TB3FFCR register is corrected. 2007/10/10 1.1 TMP91FU62 CMOS 16 Bit Microcontroller TMP91FU62FG/DFG Product No. TMP91FU62FG 96K bytes TMP91FU62DFG 4K bytes QFP80-P-1420-0.80B ROM (Flash ROM) RAM Package LQFP80-P-1212-0.50E 1.1 Features • High-speed 16-bit CPU (900/L1 CPU) - Instruction mnemonics are upward-compatible with TLCS-900,900/H,900/L - 16 Mbytes of linear address space - General-purpose registers and register banks - 16-bit multiplication and division instructions; bit transfer and arithmetic instructions - Micro DMA: 4 channels (800ns/2 bytes at 20MHz) • Minimum instruction execution time:200ns (at 20MHz) • Built-in memory - ROM: 96K bytes (Flash ROM) - RAM: 4K bytes • 8-bit timers: 4 channels • 16-bit timers: 4 channels • General-purpose serial interface: 4 channels - UART/Synchronous mode: 3 channels - I2C bus mode: 1 channels • 10-bit AD converter (Built-in Sample hold circuit): 16 channels • Special timer for CLOCK • Watchdog timer • Program patch logic: 6 banks This product uses the Super Flash® technology under the licence of Silicon Storage Technology, Inc. Super Flash® is registered trademark of Silicon Storage Technology, Inc. 20070701-EN • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. • Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occuuring as a result of noncompliance with applicable laws and regulations. Page 1 2007-10-10 TMP91FU62 • Interrupts: 48 interrupts - 9 CPU interrupts: Software interrupt instruction and illegal instruction - 30 internal interrupts: 7 priority levels are selectable - 9 external interrupts: 7 priority levels are selectable (among 1 interrupts are selectable edge mode) • Input/output ports: 69 pins • Standby function: Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP • Clock controller - Clock gear function: Select a High-frequency clock fc/1 to fc/16 - Oscillator for CLOCK (fs = 32.768 kHz) • Operating voltage Flash read operation > Vcc=4.5 V - 5.5 V (fc max = 20MHz) Flash write/erase operation > Vcc=4.75 V - 5.25 V (fc max = 20MHz) • Package - LQFP80-P-1212-0.50E (TMP91FU62FG) - QFP80-P-1420-0.80B (TMP91FU62DFG) Page 2 2007-10-10 TMP91FU62 1.2 Pin Assignment Diagram P67/AN15 P66/AN14 P65/AN13 P64/AN12 P63/AN11 P62/AN10 P61/AN9 P60/AN8 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 PB2 PB1 PB0 P33/TB3OUT1 75 80 70 30 Figure 1-1 Pin Assignment(TMP91FU62FG) AM0 DVCC X2 DVSS X1 AM1 RESET P94/RXD1/TXD1 P95/SCLK1/CTS1 P96/XT1 P97/XT2 PA0/TB2IN0/INT1 PA1/TB2IN1/INT2 PA2/TB2OUT0 PA3/TB2OUT1 P40/SCOUT P41/TXD2/RXD2 P42/RXD2/TXD2 P43/SCLK2/CTS2 EMU0 25 35 40 AVSS AVCC P70/TA0IN P71/TA1OUT P72 P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0/RXD0 P91/RXD0/TXD0 P92/SCLK0/CTS0 P93/TXD1/RXD1 1 65 60 5 55 TMP91FU62FG 10 LQFP80 TOPVIEW 15 50 45 20 P32/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 P17 P16 P15 P14 P13 P12 P11 P10 DVSS P07 P06 P05 P04 P03 P02 P01 P00 Page 3 2007-10-10 PB1 PB2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/AN8 P61/AN9 P62/AN10 P63/AN11 P64/AN12 P65/AN13 65 75 80 70 1 5 60 10 55 QFP80 TOPVIEW TMP91FU62DFG Figure 1-2 Pin Assignment(TMP91FU62DFG) 15 Page 4 20 50 P66/AN14 P67/AN15 AVSS AVCC P70/TA0IN P71/TA1OUT P72 P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0/RXD0 P91/RXD0/TXD0 P92/SCLK0/CTS0 P93/TXD1/RXD1 AM0 DVCC 45 40 PB0 P33/TB3OUT1 P32/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 P17 P16 P15 P14 P13 P12 P11 P10 DVSS P07 P06 P05 P04 P03 P02 P01 P00 EMU0 P43/SCLK2/CTS2 30 35 25 P42/RXD2/TXD2 P41/TXD2/RXD2 P40/SCOUT PA3/TB2OUT1 PA2/TB2OUT0 PA1/TB2IN1/INT2 PA0/TB2IN0/INT1 P97/XT2 P96/XT1 P95/SCLK1/CTS1 P94/RXD1/TXD1 RESET AM1 X1 DVSS X2 TMP91FU62 2007-10-10 TMP91FU62 1.3 Block Diagram Figure 1-3 Block Diagram Page 5 2007-10-10 TMP91FU62 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/3) Input / Output IO IO IO I I IO IO I I IO IO O IO O IO O IO O I IO I O IO IO I IO I IO I IO I IO O IO IO I IO O IO I IO I I Pin Name Pin Number Functions P00-P07 P10-P17 P30 TB3IN0 INT3 SDA0 P31 TB3IN1 INT4 SCL0 P32 TB3OUT0 P33 TB3OUT1 P40 SCOUT P41 TXD2 RXD2 P42 RXD2 TXD2 P43 SCLK2 CTS2 P50-57 AN0-AN7 P60-67 AN8-AN15 P70 TA0IN P71 TA1OUT P72 P73 TA4IN P74 TA5OUT P75 INT0 P80 TB0IN0 INT5 8 8 Port 0: I/O port that allows I/O to be selected at the bit level (large-current port) Port 1: I/O port that allows I/O to be selected at the bit level Port 30: I/O port 16-bit timer 3 input 0:Timer B3 count/capture trigger Input 0 Interrupt Request Pin 3: Interrupt request pin with programmable rising edge / falling edge. Serial bus interface data 0 in I2C bus Mode. Port 31: I/O port 16-bit timer 3 input 1:Timer B3 count/capture trigger Input 1 Interrupt Request Pin 4: Interrupt request on rising edge Serial bus interface clock 0 in I2C bus Mode. Port 32: I/O port 16-bit timer 3 output 0: Timer B3 Output 0 Port 33: I/O port 16-bit timer 3 output 1: Timer B3 Output 1 Port 40: I/O port (with pull-up resistor) System Clock Output: Outputs fSYS or fs clock. Port 41: I/O port (with pull-up resistor) Serial Send Data 2 Serial Receive Data 2 Port 42: I/O port (with pull-up resistor) Serial Receive Data 2 Serial Send Data 2 Port 43: I/O port (with pull-up resistor) Serial Clock I/O 2 Serial Data Send Enable 2 (Clear to Send) Port 5: I/O port Analog input: Pin used to input to AD converter Port 6: I/O port Analog input: Pin used to input to AD converter Port 70: I/O port 8-bit timer 0 input: Timer A0 Input Port 71: I/O port 8-bit timer 1 output:Timer A1 Output Port 72: I/O port Port 73: I/O port 8-bit timer 4 input: Timer A4 Input Port 74: I/O port 8-bit timer 5 output:Timer A5 Output Port 75: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge. Port 80: I/O port 16-bit timer 0 input 0:Timer B0 count/capture trigger Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. 1 1 1 1 1 1 1 1 8 8 1 1 1 1 1 1 1 Page 6 2007-10-10 TMP91FU62 Table 1-1 Pin Names and Functions(2/3) Input / Output IO I I IO O IO O IO I I IO I I IO O IO O IO O I IO I O IO IO I IO O I IO I O IO IO I IO I IO O IO I I IO I I IO O IO O Pin Name Pin Number Functions P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 TXD0 RXD0 P91 RXD0 TXD0 P92 SCLK0 CTS0 P93 TXD1 RXD1 P94 RXD1 TXD1 P95 SCLK1 CTS1 P96 XT1 P97 XT2 PA0 TB2IN0 INT1 PA1 TB2IN1 INT2 PA2 TB2OUT0 PA3 TB2OUT1 1 Port 81: I/O port 16-bit timer 0 input 1:Timer B0 count/capture trigger Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port 16-bit timer 0 output 0: Timer B0 Output 0 Port 83: I/O port 16-bit timer 0 output 1: Timer B0 Output 1 Port 84: I/O port 16-bit timer 1 input 0:Timer B1 count/capture trigger Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port 16-bit timer 1 input 1:Timer B1 count/capture trigger Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port 16-bit timer 1 output 0: Timer B1 Output 0 Port 87: I/O port 16-bit timer 1 output 1: Timer B1 Output 1 Port 90: I/O port Serial Send Data 0 Serial Receive Data 0 Port 91: I/O port Serial Receive Data 0 Serial Send Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 Serial Receive Data 1 Port 94: I/O port Serial Receive Data 1 Serial Send Data 1 Port 95: I/O port Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port Low-frequency oscillator connection pin Port 97: I/O port Low-frequency oscillator connection pin Port A0: I/O port 16-bit timer 2 input 0:Timer B2 count/capture trigger Input 0 Interrupt Request Pin 1: Interrupt request pin with programmable rising edge / falling edge. Port A1: I/O port 16-bit timer 2 input 1:Timer B2 count/capture trigger Input 1 Interrupt Request Pin 2: Interrupt request on rising edge Port A2: I/O port 16-bit timer 2 output 0: Timer B2 Output 0 Port A3: I/O port 16-bit timer 2 output 1: Timer B2 Output 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Page 7 2007-10-10 TMP91FU62 Table 1-1 Pin Names and Functions(3/3) Input / Output IO Pin Name Pin Number Functions PB0-PB2 3 Port B: I/O port that allows I/O to be selected at the bit level Operation mode:Fixed to AM1 "1", AM0 "1". Single Boot mode:Fixed to AM1 "0", AM0 "1". Programmer mode:Fixed to AM1 "1", AM0 "0". Open pin Reset: initializes TMP91FU62. (with pull-up resistor) Power supply pin for AD converter GND pin for AD converter (0 V) AM0-1 2 I EMU0 RESET AVCC AVSS X1/X2 DVCC DVSS 1 1 1 1 2 3 3 O I IO High frequency oscillator connection pins Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.) Note: All pins that have built-in pull-up resistors (other than the RESET pin) can be disconnected from the built-in pull-up resistor by software. Page 8 2007-10-10 TMP91FU62 2. CPU The TMP91FU62 incorporates a high-performance 16-bit CPU (The 900/L1-CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91FU62; these functions are not covered in the TLCS-900/L1 CPU section. 2.1 RESET When resetting the TMP91FU62 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (1us at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. It means that the system clock mode fSYS is set to fc/2. When the reset is accept, the CPU: 1. Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: - PC (7:0) - PC (15:8)