TMP92CH21FG

TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CH21FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. TMP92CH21 CMOS 32-bit Microcontroller TMP92CH21FG/JTMP92CH21 1. Outline and Device Characteristics The TMP92CH21 is a high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. The TMP92CH21 has a high-performance CPU (900/H1 CPU) and various built-in I/Os. The TMP92CH21FG is housed in a 144-pin flat package. The JTMP92CH21 is a chip form product. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU) • • • • Compatible with TLCS-900/L1 instruction code 16 Mbytes of linear address space General-purpose register and register banks Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at fSYS = 20 MHz) RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D 070208EBP • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C • The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 92CH21-1 2007-02-28 TMP92CH21 (3) Internal memory • • Internal RAM: 16 Kbytes (can be used for program, data and display memory) Internal ROM: 8 Kbytes (used as boot program) Possible downloading of user program through either USB, UART or NAND flash. Expandable up to 512 Mbytes (shared program/data area) Can simultaneously support 8,- 16- or 32-bit width external data bus ... dynamic data bus sizing Separate bus system Chip select output: 4 channels (4) External memory expansion • • • • (5) Memory controller (6) 8-bit timers: 4 channels (7) 16-bit timer/event counter: 1 channel (8) General-purpose serial interface: 2 channels • • • • • UART/synchronous mode: 2 channels (channel 0 and 1) IrDA ver.1.0 (115 kbps) mode selectable: 1 channel (channel 0) Compliant with USB ver.1.1 Full-speed (12 MHz) (Low-speed is not supported.) Endpoints spec Endpoint 0: Control 64 bytes* 1-FIFO Endpoint 1: BULK (out) 64 bytes* 2-FIFO Endpoint 2: BULK (in) 64 bytes* 2-FIFO Endpoint 3: Interrupt (in) 8 bytes* 1-FIFO • • • • • • • Descriptor RAM: 384 bytes I2S bus mode/SIO mode selectable (Master, transmission only) 32-byte FIFO buffer Supports up to 4096 color for TFT, 256 color, 16, 8, 4 gray levels and B/W for STN Shift register/built-in RAM LCD driver Supports 16 M, 64 M, 128 M, 256 M, and up to 512-Mbit SDR (Single Data Rate)-SDRAM Possible to execute instruction on SDRAM (10) I2S (Inter-IC sound) interface: 1 channel (9) USB (universal serial bus) controller: 1 channel (11) LCD controller (12) SDRAM controller: 1 channel (13) Timer for real-time clock (RTC) (14) Key-on wakeup (Interrupt key input) (15) 10-bit AD converter: 4 channels 92CH21-2 2007-02-28 TMP92CH21 (16) Touch screen interface • Available to reduce external components (17) Watchdog timer (18) Melody/alarm generator • • • • • • • Melody: Output of clock 4 to 5461 Hz Alarm: Output of 8 kinds of alarm pattern and 5 kinds of interval interrupt Expandable up to 512 Mbytes (3 local area/8 bank method) Independent bank for each program, read data, write data and LCD display data 9 CPU interrupts: Software interrupt instruction and illegal instruction (19) MMU (20) Interrupts: 50 interrupt 34 internal interrupts: Seven selectable priority levels 7 external interrupts: Seven selectable priority levels (6-edge selectable) RD (21) Input/output ports: 82 pins (Except Data bus (16bit), Address bus (24bit) and (22) NAND flash interface: 2 channels • • • • • • • • • • • Direct NAND flash connection capability ECC calculation (for SLC- type) Three HALT modes: IDLE2 (programmable), IDLE1, STOP Each pin status programmable for stand-by mode pin) (23) Stand-by function (24) Triple-clock controller Clock doubler (PLL) supplies 48 MHz for USB, 36 MHz system-clock for others Clock gear function: Select high-frequency clock fc to fc/16 RTC (fs = 32.768 kHz) VCC = 3.0 V to 3.6 V (fc max = 40 MHz) VCC = 2.7 V to 3.6 V (fc max = 27 MHz) 144-pin QFP (P-LQFP144 -1616-0.40C) 144-pin chip form is also available. For details, contact your local Toshiba sales representative. (25) Operating voltage: (26) Package: 92CH21-3 2007-02-28 TMP92CH21 PG0 to PG1 (AN0 to AN1) AN2/MX (PG2) AN3/MY/ ADTRG (PG3) AVCC, AVSS VREFH, VREFL (PX, INT4) P96 (PY, INT5) P97 (TXD0, TXD1) PF0 (RXD0, RXD1) PF1 (SCLK0,SCLK1) PF2 10-bit 4-channel AD converter Touch screen I/F (TSI) Serial I/O SIO0 Serial I/O SIO1 900/H1 CPU XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR F PC DVCC [4] DVSS [3] PLL H-OSC Clock gear L-OSC X1 X2 TEST XT1 XT2 RESET AM0 AM1 Interrupt controller D0 to D7 Port 1 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23, KO0 to KO7) P30 to P37 (D24 to D31) P40 to P47 (A0 to A7) P50 to P57 (A8 to A15) P60 to P67 (A16 to A23) P70 ( RD ) P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) P73 (EA24) P74 (EA25) P75 (R/ W , NDR/B) P76 ( WAIT ) D+ D− (I2SCKO, TXD0) P90 (I2SDO, RXD0) P91 (I2SWS, SCLK0, CTS0 ) P92 (LGOE0) P93 (LGOE1) P94 (LGOE2, CLK32KO) P95 USB controller Watchdog timer IS 2 Port 2 MMU Port 3 Port 4 Port 5 8-bit timer (TIMERA0) Port 6 Port 9 (TA1OUT, INT0) PC0 8-bit timer (TIMERA1) 8-bit timer (TIMERA2) Port 7 (TA3OUT, INT1) PC1 8-bit timer (TIMERA3) 16-bit timer (TIMERB0) NAND flash I/F (2 channel) (TB0OUT0, INT2) PC2 (INT3) PC3 Port 8 (LCP0) PK0 (LLP) PK1 (LFR) PK2 (LBCD) PK3 PL0 to PL7 (LD0 to LD7) ( SDRAS , SRLLB ) PJ0 ( SDCAS , SRLUB ) PJ1 ( SDWE , SRWR ) PJ2 (SDLLDQM) PJ3 (SDLUDQM) PJ4 (NDALE, SDULDQM) PJ5 (NDCLE, SDUUDQM) PJ6 (SDCKE) PJ7 (SDCLK) PF7 LCD controller 16-KB RAM Keyboard I/F RTC 8-KB mask ROM (Boot program) Melody/ Alarm out P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA , SDCS ) P83 ( CS3 ) P84 ( CSZB , WRUL , ND0CE ) P85 ( CSZC , WRUU , ND1CE ) P86 ( CSZD , SRULB ) P87 ( CSZE , SRUUB ) PC7 ( CSZF , LCP1) PA0 to PA7 (KI0 to KI7, LD8 to LD11) PC6 (KO8, LDIV) PM2 ( ALARM , MLDALM ) SDRAM controller PM1 (MLDALM) Figure 1.1 TMP92CH21 Block Diagram 92CH21-4 2007-02-28 TMP92CH21 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CH21FG, their names and functions are as follows: 2.1 Pin Assignment AVCC AVSS PA2, KI2 PA1, KI1 PA0, KI0 PJ7, SDCKE PJ6, SDUUDQM, NDCLE PJ5, SDULDQM, NDALE PJ4, SDLUDQM PJ3, SDLLDQM PJ2, SDWE, SRWR PJ1, SDCAS, SRLUB PJ0, SDRAS, SRLLB PF7, SDCLK PC1, TA3OUT, INT1 PC0, TA1OUT, INT0 PF2, SCLK0, CTS0, SCLK1, CTS1 PF1, RXD0, RXD1 PF0, TXD0, TXD1 PC7, CSZF, LCP1 P87, CSZE, SRUUB P86, CSZD, SRULB P85, CSZC, WRUU, ND1CE P84, CSZB, WRUL, ND0CE P83, CS3 P82, CS2, CSZA, SDCS P81, CS1, SDCS PC6, KO8, LDIV P80, CS0 P76, WAIT P75, R/W, NDR/B P74, EA25 P73, EA24 P72, WRLU, NDWE P71, WRLL, NDRE P70, RD 140 135 130 125 120 115 VREFL VREFH PG0, AN0 PG1, AN1 PG2, AN2, MX PG3, AN3, ADTRG , MY P96, PX, INT4 P97, PY, INT5 PA3, KI3, LD8 PA4, KI4, LD9 PA5, KI5, LD10 PA6, KI6, LD11 PA7, KI7 P90, TXD0, I2SCKO P91, RXD0, I2SDO P92, SCLK0, CTS0 , I2SWS P93, LGOE0 P94, LGOE1 P95, CLK32KO, LGOE2 PC2, TB0OUT0, INT2 PL0, LD0 PL1, LD1 PL2, LD2 PL3, LD3 PL4, LD4 PL5, LD5 PL6, LD6 PL7, LD7 PK0, LCP0 PK1, LLP PK2, LFR PK3, LBCD PM2, ALARM , MLDALM PM1, MLDALM XT1 XT2 1 110 105 5 100 10 15 TMP92CH21FG QFP144 95 90 20 Top View 85 25 80 30 75 35 40 45 50 55 60 65 70 P67, A23 P66, A22 P65, A21 P64, A20 DVCC3 P63, A19 P62, A18 P61, A17 P60, A16 P57, A15 P56, A14 P55, A13 P54, A12 P53, A11 P52, A10 P51, A9 P50, A8 P47, A7 P46, A6 P45, A5 P44, A4 P43, A3 P42, A2 P41, A1 P40, A0 P37, D31 P36, D30 DVSS3 P35, D29 P34, D28 P33, D27 P32, D26 P31, D25 P30, D24 P27, D23, KO7 P26, D22, KO6 Figure 2.1.1 Pin Assignment Diagram (144-pin QFP) PC3, INT3 DVSS2 DVCC2 D0 D1 D2 D3 D4 D5 D6 D7 P10, D8 P11, D9 P12, D10 P13, D11 P14, D12 P15, D13 P16, D14 P17, D15 P20, D16, KO0 P21, D17, KO1 P22, D18, KO2 P23, D19, KO3 P24, D20, KO4 P25, D21, KO5 TEST D+ D− DVCC1 X1 DVSS1 X2 AM0 AM1 DVCC4 RESET 92CH21-5 2007-02-28 TMP92CH21 2.2 PAD Assignment (Chip size 5.98 mm × 6.42 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: μm Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name VREFL VREFH PG0 PG1 PG2 PG3 X Point −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2852 −2465 −2339 −2062 −1875 −1598 −1472 −1347 −1126 −1001 −876 −750 −625 Y Point 2671 2546 2421 2296 2171 2045 1920 1795 1270 1145 1020 895 769 644 519 394 269 144 18 −106 −231 −356 −481 −606 −732 −857 −982 −1107 −1232 −1357 −1482 −1608 −1892 −2017 −2142 −2444 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 Pin No 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Name DVSS2 DVCC2 D0 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 DVSS3 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 P53 P54 X Point −488 −338 −200 −75 49 174 300 425 550 675 800 925 1050 1176 1301 1426 1551 1676 1801 1927 2052 2177 2303 2460 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 Y Point −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −3072 −2279 −2138 −1982 −1831 −1687 −1562 −1437 −1311 −1186 −1061 −936 −811 −686 −560 −435 −310 −185 −60 65 190 315 440 565 690 Pin No 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name P55 P56 P57 P60 P61 P62 P63 DVCC3 P64 P65 P66 P67 P70 P71 P72 P73 P74 P75 P76 P80 PC6 P81 P82 P83 P84 P85 P86 P87 PC7 PF0 PF1 PF2 PC0 PC1 PF7 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PA0 PA1 PA2 AVSS AVCC X Point 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2460 2295 2127 1964 1807 1654 1506 1361 1226 1101 976 851 726 600 475 350 225 100 −24 −150 −275 −400 −525 −650 −775 −901 −1026 −1151 −1276 −1401 −1526 −1652 −1777 −1902 −2275 −2400 Y Point 815 941 1066 1191 1316 1441 1566 1692 1823 1974 2130 2292 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 P96 P97 PA3 PA4 PA5 PA6 PA7 P90 P91 P92 P93 P94 P95 PC2 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PK0 PK1 PK2 PK3 PM2 PM1 XT1 XT2 DVCC4 TEST D+ D− DVCC1 X1 DVSS1 X2 AM0 AM1 RESET PC3 92CH21-6 2007-02-28 TMP92CH21 2.3 Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Pin Name D0 to D7 P10 to P17 D8 to D15 P20 to P27 D16 to D23 KO0 to KO7 P30 to P37 D24 to D31 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70 RD Number of Pins 8 8 I/O I/O I/O I/O I/O I/O Output I/O I/O Output Output Output Output I/O Output Output Output I/O Output Output I/O Data: Data bus 0 to 7 Function Port 1: I/O port input or output specifiable in units of bits Data: Data bus 8 to 15 Port 2: I/O port input or output specifiable in units of bits Data: Data bus 16 to 23 Key output 0 to 7: Pins used of key-scan strobe (Open-drain output programmable) Port 3: I/O port input or output specifiable in units of bits Data24: Data bus 24 to 31 Port 4: Output port Address: Address bus 0 to 7 Port 5: Output port Address: Address bus 8 to 15 Port 6: I/O port input or output specifiable in units of bits Address: Address bus 16 to 23 Port70: Output port Read: Outputs strobe signal to read external memory Port 71: I/O port Write: Output strobe signal for writing data on pins D0 to D7 NAND flash read: Outputs strobe signal to read external NAND flash Port 72: I/O port Write: Output strobe signal for writing data on pins D8 to D15 Write Enable for NAND flash Port 73: Output port Extended Address 24 Port 74: Output port Extended Address 25 Port 75: I/O port Read/Write: 1 represents read or dummy cycle; 0 represents write cycle NAND flash ready (1)/Busy (0) input Port 76: I/O port Wait: Signal used to request CPU bus wait 8 8 8 8 8 1 P71 WRLL NDRE 1 P72 WRLU NDWE 1 Output Output Output Output Output Output I/O Output Input I/O Input P73 EA24 P74 EA25 P75 R/ W 1 1 1 NDR/B P76 WAIT 1 92CH21-7 2007-02-28 TMP92CH21 Table 2.3.2 Pin Names and Functions (2/5) Pin Name P80 CS0 Number of Pins 1 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Output Output I/O Input Output I/O I/O Input Output Function Port80: Output port Chip select 0: Outputs “low” when address is within specified address area Port81: Output port Chip select 1: Outputs “low” when address is within specified address area Chip select for SDRAM: Outputs “0” when address is within SDRAM address area Port82: Output port Chip select 2: Outputs “Low” when address is within specified address area Expand chip select: ZA: Outputs “0” when address is within specified address area Chip select for SDRAM: Outputs “0” when address is within SDRAM address area Port83: Output port Chip select 3: Outputs “low” when address is within specified address area Port84: Output port Write: Output strobe signal for writing data on pins D16 to D23 Expand chip select: ZB: Outputs “0” when address is within specified address area Chip select for NAND flash 0: Outputs “0” when NAND flash 0 is enabled Port85: Output port Write: Output strobe signal for writing data on pins D24 to D31 Expand chip select: ZC: Outputs “0” when address is within specified address area Chip select for NAND flash 1: Outputs “0” when NAND flash 1 is enabled Port86: Output port Expand chip select: ZD: outputs “0” when address is within specified address area Data enable for SRAM on pins D16 to D23 Port87: Output port Expand chip select: ZE: Outputs “0” when address is within specified address area Data enable for SRAM on pins D24 to D31 Port90: I/O port Serial 0 send data: Open-drain output programmable 2 I S clock output Port91: I/O port (Schmitt-input) Serial 0 receive data 2 I S data output Port92: I/O port (Schmitt-input) Serial 0 clock I/O Serial 0 data send enable (Clear to send) 2 I S word select output P81 CS1 SDCS 1 P82 CS2 CSZA SDCS 1 P83 CS3 1 P84 WRUL CSZB ND0CE 1 P85 WRUU CSZC ND1CE 1 P86 CSZD SRULB 1 P87 CSZE SRUUB 1 P90 TXD0 I2SCKO P91 RXD0 I2SDO P92 SCLK0 CTS0 1 1 1 I2SWS P93 LGOE0 P94 LGOE1 P95 CLK32KO LGOE2 P96 INT4 PX P97 INT5 PY PA0 to PA2 KI0 to KI2 PA3 to PA6 KI3 to KI6 LD8 to LD11 PA7 KI7 1 1 1 1 1 3 4 1 I/O Port93: I/O port Output Output enable-0 for external TFT-LCD driver I/O Port94: I/O port Output Output enable-1 for external TFT-LCD driver Output Port95: Output port Output Output fs (32.768 kHz) clock Output Output enable-2 for external TFT-LCD driver Input Port 96: Input port (Schmitt-input) Input Interrupt request pin4: Interrupt request with programmable rising/falling edge Output X-Plus: Pin connectted to X+ for touch screen panel Input Port 97: Input port (Schmitt-input) Input Interrupt request pin5: Interrupt request with programmable rising/falling edge Output Y-Plus: Pin connectted to Y+ for touch screen panel Input Port: A0 to A2 port: Pin used to input ports (Schmitt input, with pull-up resistor) Input Key input 0 to 2: Pin used for key-on wakeup 0 to 2 Input Port: A3 to A6 port: Pin used to input ports (Schmitt input, with pull-up resistor) Input Key input 3 to 6: Pin used for key-on wakeup 3 to 6 Output Data bus 8 to 11for LCD driver Input Port: A7 port: Pin used to input ports (Schmitt input, with pull-up resistor) Input Key input 7: Pin used for key-on wakeup 7 92CH21-8 2007-02-28 TMP92CH21 Table 2.3.3 Pin Names and Functions (3/5) Pin Name PC0 INT0 TA1OUT PC1 INT1 TA3OUT PC2 INT2 TB0OUT0 PC3 INT3 PC6 KO8 LDIV PC7 CSZF Number of Pins 1 I/O I/O Input Output I/O Port C0: I/O port (Schmitt-input) Function Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge 8-bit timer 1 output: Timer 1 output Port C1: I/O port (Schmitt-input) Interrupt request pin 1: Interrupt request pin with programmable rising/falling edge 8-bit timer 3 output: Timer 3 output Port C2: I/O port (Schmitt-input) Interrupt request pin 2: Interrupt request pin with programmable rising/falling edge Timer B0 output Port C3: I/O port (Schmitt-input) Interrupt request pin 3: Interrupt request pin with programmable rising/falling edge Port C6: I/O port Key Output 8: Pin used of key-scan strobe (Open-drain output programmable) Data invert enable for external TFT-LCD driver Port C7: I/O port Expand chip select: ZF: Outputs “0” when address is within specified address area Shift-clock-1 for external TFT-LCD driver Port F0: I/O port (Schmitt-input) Serial 0 send data: Open-drain output programmable Serial 1 send data: Open-drain output programmable Port F1: I/O port (Schmitt-input) Serial 0 receive data Serial 1 receive data Port F2: I/O port (Schmitt-input) Serial 0 clock I/O Serial 0 data send enable (Clear to send) Serial 1 clock I/O Serial 1 data send enable (Clear to send) Port F7: Output port Clock for SDRAM (When SDRAM is not used, SDCLK can be used as system clock) Port G0 to G1 port: Pin used to input ports Analog input 0 to 1: Pin used to Input to AD conveter Port G2 port: Pin used to input ports Analog input 2: Pin used to Input to AD conveter X-Minus: Pin connectted to X− for touch screen panel Port G3 port: Pin used to input ports Analog input 3: Pin used to input to AD conveter Y-Minus: Pin connectted to Y− for touch screen panel AD trigger: Signal used to request AD start 1 Input Output I/O 1 Input Output I/O Input I/O Output Output I/O 1 1 1 Output Output I/O LCP1 PF0 TXD0 TXD1 PF1 RXD0 RXD1 PF2 SCLK0 CTS0 1 Output Output I/O 1 Input Input I/O I/O 1 Input I/O Input Output Output Input Input Input Input Output Input Input Output Intput SCLK1 CTS1 PF7 SDCLK PG0 to PG1 AN0 to AN1 PG2 AN2 MX PG3 AN3 MY ADTRG 1 2 1 1 92CH21-9 2007-02-28 TMP92CH21 Table 2.3.4 Pin Names and Functions (4/5) Pin Name PJ0 SDRAS SRLLB Number of Pins 1 I/O Output Output Output Output Port J0: Output port Row address strobe for SDRAM Data enable for SRAM on pins D0 to D7 Port J1: Output port Column address strobe for SDRAM Function PJ1 SDCAS SRLUB 1 Output Output Output Data enable for SRAM on pins D8 to D15 Port J2: Output port Write enable for SDRAM Write for SRAM: Strobe signal for writing data Port J3: Output port Data enable for SDRAM on pins D0 to D7 Port J4: Output port Data enable for SDRAM on pins D8 to D15 Port J5: I/O port Data enable for SDRAM on pins D16 to D23 Address latch enable for NAND flash Port J6: I/O port Data enable for SDRAM on pins D24 to D31 Command latch enable for NAND flash Port J7: Output port Clock enable for SDRAM Port K0: Output port LCD driver output pin Port K1: Output port LCD driver output pin Port K2: Output port LCD driver output pin Port K3: Output port LCD driver output pin Port L0 to L3: Output port Data bus for LCD driver Port L4 to L7: I/O port Data bus for LCD driver Connect to VCC. Port M1: Output port Melody/alarm output pin Port M2: Output port RTC alarm output pin Melody/alarm output pin (inverted) PJ2 SDWE SRWR 1 Output Output Output Output Output Output I/O Output Output I/O PJ3 SDLLDQM PJ4 SDLUDQM PJ5 SDULDQM NDALE PJ6 SDUUDQM NDCLE PJ7 SDCKE PK0 LCP0 PK1 LLP PK2 LFR PK3 LBCD PL0 to PL3 LD0 to LD3 PL4 to PL7 LD4 to LD7 TEST 1 1 1 1 Output Output Output Output Output Output Output Output Output Output Output Output Output Output I/O Output Input Output Output Output Output Output 1 1 1 1 1 4 4 1 1 PM1 MLDALM PM2 ALARM MLDALM 1 Note: The output functions SDULDQM, NDALE of PJ5-pin and SDUUDQM, NDCLE of PJ6-pin cannot be used simultaneously. Therefore, 32-bit SDRAM and NAND-Flash cannot be used at the same time. 92CH21-10 2007-02-28 TMP92CH21 Table 2.3.5 Pin Names and Functions (5/5) Pin Name D+, D− Number of Pins 2 I/O I/O USB-data connecting pin Function Connect pull-up resistor to both pins to avoid through current when USB is not in use. Operation mode: Fix to AM1 = “0”, AM0 = “1” for 16-bit external bus starting Fix to AM1 = “1”, AM0 = “0” for 32-bit external bus starting Fix to AM1 = “1”, AM0 = “1” for BOOT (32-bit internal MROM) starting High-frequency oscillator connection pins Low-frequency oscillator connection pins Reset: Initializes TMP92CH21 (with pull-up resistor, Schmitt input) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) Power supply pins (All VCC pins should be connected to the power supply pin) GND pins (0 V) (All pins should be connected to GND (0 V)) AM0, AM1 2 Input X1/X2 XT1/XT2 RESET 2 2 1 1 1 1 1 4 3 I/O I/O Input Input Input − − − − VREFH VREFL AVCC AVSS DVCC DVSS Note: Use a 9.0 MHz oscillator at pins X1/X2 when USB is used. 92CH21-11 2007-02-28 TMP92CH21 3. 3.1 Operation This section describes the basic components, functions and operation of the TMP92CH21. CPU The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process instructions more quickly. The following is an outline of the CPU: Table 3.1.1 TMP92CH21 Outline Parameter Width of CPU address bus Width of CPU data bus Internal operating frequency Minimum bus cycle Internal RAM Internal boot ROM Internal I/O TMP92CH21 24 bits 32 bits Max 20 MHz 1-clock access (50 ns at fSYS = 20MHz) 32-bit 1-clock access 32-bit 2-clock access 8- or 16-bit 2-clock access or 8- or 16-bit 5 to 6-clock access 8- or 16- or 32-bit 2-clock access (waits can be inserted) 16- or 32-bit min. 1-clock access 8-bit min. 4-clock access (waits can be inserted) 1-clock (50 ns at fSYS =20MHz) 2-clock (100 ns at fSYS =20MHz) 12 bytes Compatible with TLCS-900/L1 (LDX instruction is deleted) Maximum mode only 8 channels External SRAM, Masked ROM External SDRAM External NAND flash Minimum instruction execution cycle Conditional jump Instruction queue buffer Instruction set CPU mode Micro DMA 92CH21-12 2007-02-28 TMP92CH21 3.1.2 Reset Operation When resetting the TMP92CH21, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input low for at least 20 system clocks (16 µs at fc = 40 MHz). At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the system clock operates at 1.25 MHz (fc = 40 MHz). When the reset has been accepted, the CPU performs the following: • Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC PC PC • • • ← data in location FFFF00H ← data in location FFFF01H ← data in location FFFF02H Sets the stack pointer (XSP) to 00000000H. Sets bits of the status register (SR) to 111 (thereby setting the interrupt level mask register to level 7). Clears bits of the status register to 00 (there by selecting register bank 0). When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows. • • Initializes the internal I/O registers as shown in the “Special Function Register” table in section 5. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Internal reset is released as soon as external reset is released. Memory controller operation cannot be ensured until the power supply becomes stable after power-on reset. External RAM data provided before turning on the TMP92CH21 may be corrupted because the control signals are unstable until the power supply becomes stable after power on reset. VCC (3.3 V) RESET High-frequency oscillation stabilized time +20 system clock 0 s (Min) Figure 3.1.1 Power on Reset Timing Example 92CH21-13 2007-02-28 fsys Sampling RESET fsys×(13.5~14.5) clock 0FFFF00H A23∼A0 CS0,1, 3 CS2 D0∼D31 DATA-IN DATA-IN Read RD SRxxB ((After reset released, starting 1 wait read cycle) Figure 3.1.2 TMP92CH21 Reset Timing Chart 92CH21-14 (Output mode) (Output mode) (Input mode) (Input mode) Pull up (Internal) High-Z D0∼D31 DATA-OUT WRxx Write SRWR SRxxB PF7 PJ3~PJ4, PJ7 PM1~PM2 P40~P47,P50~P57 P74~P72, PK0~PK3, PL0~PL3 PA0~PA7 TMP92CH21 2007-02-28 P71~P72, P75~P76, P90~P94, P96~P97, PC0~PC3, PC6~PC7, PF0~PF1, PG0~PG3, PJ5~PJ6, PL4~PL7, Note: This chart shows timing for a reset using a 32-bit external bus (AM1:0=10). TMP92CH21 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Operation Mode 16-bit external bus starting (MULTI 16 mode) 32-bit external bus starting (MULTI 32 mode) Boot (32-bit internal MROM) starting (BOOT mode) Mode Setup Input Pin RESET AM1 0 1 1 AM0 1 0 1 92CH21-15 2007-02-28 TMP92CH21 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP92CH21. 000000H Internal I/O (8 Kbytes) 000100H 001D00H 002000H Internal RAM (16 Kbytes) Direct area (n) 64-Kbyte area (nn) 006000H 010000H 3FE000H Boot (Internal MROM) (8 Kbytes) 400000H (Note 1) External memory F00000H Provisional emulator control (64 Kbytes) F10000H (Note 2) 16-Mbyte area (R) (−R) (R+) (R + R8/16) (R + d8/16) (nnn) External memory FFFF00H Vector table (256 bytes) FFFFFFH ( = Internal area) (Note 3) Figure 3.2.1 Memory Map Note 1: Boot program (Internal MROM) is mapped only for BOOT mode. For other starting modes, its area (3FE000H to 3FFFFFH) is mapped to external-memory. Note 2: The Provisional emulator control area, mapped F00000H to F0FFFFH after reset, is for emulator use and so is not available. When emulator WR signal and RD signal are asserted, this area is accessed. Ensure external memory is used. Note 3: Do not use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved for an emulator. 92CH21-16 2007-02-28 TMP92CH21 3.3 Clock Function and Stand-by Function The TMP92CH21 contains (1) clock gear, (2) clock doubler (PLL), (3) stand-by controller and (4) noise reduction circuits. They are used for low power, low noise systems. This chapter is organized as follows: 3.3.1 Block diagram of system clock 3.3.2 SFR 3.3.3 System clock controller 3.3.4 Clock doubler (PLL) 3.3.5 Noise reduction circuits 3.3.6 Stand-by controller 92CH21-17 2007-02-28 TMP92CH21 The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) Release reset Instruction NORMAL mode Interrupt Interrupt Instruction Interrupt STOP mode (Stops all circuits) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) (fOSCH/gear value/2) STOP mode (Stops all circuits) Instruction SLOW mode (fs/2) Dual clock mode transition figure Reset (fOSCH/32) Release reset NORMAL mode (fOSCH/gear value/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Instruction Note IDLE2 mode (I/O operate) Instruction Interrupt NORMAL mode (4 × fOSCH/gear value/2) Interrupt Instruction Interrupt Instruction SLOW mode (fs/2) Interrupt Instruction Interrupt IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) STOP mode (Stops all circuits) Instruction Instruction Note IDLE1 mode Instruction (Operate oscillator and PLL) Interrupt Using PLL (c) Triple clock mode transition figure Note 1: It is not possible to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with use of PLL. (PLL start up/stop/change write to PLLCR0, PLLCR1 register) Note 2: When shifting from NORMAL mode with use of PLL to NORMAL mode, execute the following setting in the same order. 1) Change CPU clock (PLLCR0 ← “0”) 2) Stop PLL circuit (PLLCR1 ← “0”) Note 3: It is not possible to shift from NORMAL mode with use of PLL to STOP mode directly. NORMAL mode should be set once before shifting to STOP mode. (Sstop the high-frequency oscillator after stopping PLL.) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 is called the clock fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is defined as one state. 92CH21-18 2007-02-28 TMP92CH21 3.3.1 Block Diagram of System Clock SYSCR0 SYSCR2 Warm-up timer (High/low-frequency oscillator) Lock up timer (PLL) SYSCR0 XT1 XT2 Low-frequency oscillator fs PLLCR1, PLLCR0 fc fPLL = fOSCH × 4 SYSCR0 X1 X2 Clock doubler (PLL) Selector ÷2 ÷4 φT φT0 fFPH ÷4 ÷8 fs ÷2 fc/2 fc/4 fc/8 fc/16 ÷8 ÷16 fSYS ÷2 fIO SYSCR1 High-frequency oscillator fOSCH SYSCR1 Clock-gear PLLCR0 USB Controller CPU TMRA0 to 3,TMRB0 Prescaler fUSB (48 MHz) = fOSCH × 16/3 USBCR1 fSYS fIO φT0 LCDC Memory controller NAND flash controller RAM, ROM Interrupt controller SIO0 to SIO1 Prescaler IS I/O ports TSI 2 RTC fs MLD/ALM SDRAMC ADC WDT Figure 3.3.2 Block Diagram of System Clock Table 3.3.1 Selection Example for fOSCH High-frequency Oscillation: fOSCH (a) USB in use, with PLL (b) USB not in use, with PLL (c) USB not in use, without PLL 9.0 MHz 10.0 MHz (max) 40.0 MHz (max) System Clock: fSYS 18 MHz 20 MHz (max) 20 MHz (max) USB Clock: fUSB 48 MHz − − Note: When using USB, the high-frequency oscillator should be 9.0 MHz. 92CH21-19 2007-02-28 TMP92CH21 3.3.2 SFR 7 SYSCR0 (10E0H) Bit symbol Read/Write After reset Function 1 Highfrequency oscillator (fc) 0: Stop 1: Oscillation 6 XTEN R/W 1 Lowfrequency oscillator (fs) 0: Stop 1: Oscillation 5 4 3 2 WUEF R/W 0 Warm-up timer 0: Write don’t care 1: Write 1 0 XEN start timer 0: Read end warm-up 1: Read do not end warm-up 7 SYSCR1 (10E1H) Bit symbol Read/Write After reset Function 6 5 4 3 SYSCK R/W 0 2 GEAR2 1 1 GEAR1 R/W 0 0 GEAR0 0 Select Select gear value of high-frequency (fc) system clock 000: fc 0: fc 001: fc/2 1: fs 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (10E2H) Bit symbol Read/Write After reset Function − 6 5 WUPTM1 R/W 1 Warm-up timer 00: Reserved 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 R/W 0 Always write “0” 01: 2 /input frequency 10: 2 /input frequency 11: 2 /input frequency 16 14 8 Note 1: The unassigned registers, SYSCR0, SYSCR0, SYSCR1, and SYSCR2 are read as undefined value. Note 2: Low-frequency oscillator is enabled on reset. Figure 3.3.3 SFR for System Clock 92CH21-20 2007-02-28 TMP92CH21 7 EMCCR0 (10E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON EMCCR1 (10E4H) Bit symbol Read/Write After reset Function EMCCR2 (10E5H) Bit symbol Read/Write After reset Function 6 5 4 3 2 EXTIN R/W 0 1: External clock 1 DRVOSCH R/W 1 fc oscillator driver ability 1: Normal 0: Weak 0 DRVOSCL R/W 1 fs oscillator driver ability 1: Normal 0: Weak Switch the protect ON/OFF by writing the following to 1st-KEY, 2nd-KEY 1st-KEY: write in sequence EMCCR1 = 5AH, EMCCR2 = A5H 2nd-KEY: write in sequence EMCCR1 = A5H, EMCCR2 = 5AH Note: When restarting the oscillator from the stop oscillation state (e.g. restarting the oscillator in STOP mode), set EMCCR0, =”1”. Figure 3.3.4 SFR for System Clock 92CH21-21 2007-02-28 TMP92CH21 7 PLLCR0 (10E8H) Bit symbol Read/Write After reset Function 6 FCSEL R/W 0 Select fc clock 0: fOSCH 1: fPLL 5 LUPFG R 0 Lock up timer status flag 0: Not end 1: End 4 3 2 1 0 Note: Ensure that the logic of PLLCR0 is different from 900/L1’s DFM. 7 PLLCR1 (10E9H) Bit symbol Read/Write After reset Function PLLON R/W 0 Control on/off 0: OFF 1: ON 6 5 4 3 2 1 0 Figure 3.3.5 SFR for PLL 7 PxDR (xxxxH) Bit symbol Read/Write After reset Function 1 Px7D 6 Px6D 1 5 Px5D 1 4 Px4D R/W 1 3 Px3D 1 2 Px2D 1 1 Px1D 1 0 Px0D 1 Output/input buffer drive-register for stand-by mode (Purpose and use) This register is used to set each pin status at stand-by mode. All ports have registers of the format shown above. (“x” indicates the port name.) For each register, refer to “3.5 Function of ports”. Before “Halt” instruction is executed, set each register according to the expected pin-status. They will be effective after the CPU has executed the “Halt” instruction. This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). The output/input buffer control table is shown below. OE 0 0 1 1 Note 1: PxnD 0 1 0 1 Output Buffer OFF OFF OFF ON Input Buffer OFF ON OFF OFF OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: “n” in PxnD denotes the bit number of PORTx. Figure 3.3.6 SFR for Drive Register 92CH21-22 2007-02-28 TMP92CH21 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 changes the system clock to either fc or fs, SYSCR0 and SYSCR0 control enabling and disabling of each oscillator, and SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings = 1, = 0 and = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after reset. For example, fSYS is set to 1.25 MHz when the 40 MHz oscillator is connected to the X1 and X2 pins. (1) Switching from normal mode to slow mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. Table 3.3.2 shows the warm-up time. Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.2 Warm-up Times at fOSCH = 40 MHz, fs = 32.768 kHz Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to Normal Mode 6.4 (μs) 409.6 (μs) 1.638 (ms) Change to Slow Mode 7.8 (ms) 500 (ms) 2000 (ms) 92CH21-23 2007-02-28 TMP92CH21 Example 1: Setting the clock Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR SET RES 10E0H 10E1H 10E2H (SYSCR2), 0 X 1 1 − − X X B ; 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) ; ; ; ; ; ; Sets warm-up time to 2 /fs. Enables low-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. 16 X: Don’t care, −: No change X1, X2 pins XT1, XT2 pins Warm-up timer End of warm-up timer System clock fSYS Clears and starts Enables low-frequency warm-up timer Chages fSYS from fc to fs End of warm-up timer Disabiles high-frequency fc fs Counts up by fSYS Counts up by fs 92CH21-24 2007-02-28 TMP92CH21 Example 2: Setting the clock Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR RES RES 10E0H 10E1H 10E2H (SYSCR2), 0 X 1 0 − − X X B ; 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) ; ; ; ; ; ; Sets warm-up time to 2 /fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. 14 X: Don’t care, −: No change X1, X2 pins XT1, XT2 pins Warm-up timer End of warm-up timer System Clock fSYS Enables Clears and starts high-frequency warm-up timer Changes fSYS from fs to fc End of warm-up timer Disables low-frequency fs fc Counts up by fSYS Counts up by fc 92CH21-25 2007-02-28 TMP92CH21 (2) Clock gear controller fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Example 3: Changing to a high-frequency gear SYSCR1 EQU LD LD X: Don’t care 10E1H (SYSCR1), XXXX0000B (DUMMY), 00H ; ; Changes fSYS to fc/2. Dummy instruction (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 register.It is necessary for the warm-up time to elapse before the change occurs after writing the register value. There is the possibility that the instruction following the clock gear changing instruction is executed by the clock gear before changing.To execute the instruction following the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (instruction to execute the write cycle). Example: SYSCR1 EQU LD LD 10E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed 92CH21-26 2007-02-28 TMP92CH21 3.3.4 Clock Doubler (PLL) PLL outputs the fPLL clock signal, which is four times as fast as fOSCH. A low-speed-frequency oscillator can be used, even though the internal clock is high-frequency. A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed before use. As with an oscillator, this circuit requires time to stabilize. This is called the lock up time and it is measured by a 16-stage binary counter. Lock up time is about 1.6 ms at fOSCH = 10 MHz. Note 1: Input frequency range for PLL The input frequency range (High-frequency oscillation) for PLL is as follows: fOSCH = 6 to 10 MHz (VCC = 3.0 to 3.6 V) Note 2: PLLCR0 The logic of PLLCR0 is different from 900/L1’s DFM. Exercise care in determining the end of lock up time. The following is an example of settings for PLL starting and PLL stopping. Example 1: PLL starting PLLCR0 PLLCR1 LUP: EQU EQU LD BIT JR LD X: Don’t care 10E8H 10E9H (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), 1XXXXXXXB ; ; ; X1XXXXXXB ; Enables PLL operation and starts lock up. Detects end of lock up. Changes fc from 10 MHz to 40 MHz. PLL output: fPLL Lock up timer System clock fSYS Starts PLL operation and starts lock up Changes from 10 MHz to 40 MHz Lock up ends Counts up by fOSCH During lock up After lock up 92CH21-27 2007-02-28 TMP92CH21 Example 2: PLL stopping PLLCR0 PLLCR1 EQU EQU LD LD X: Don’t care PLL output: fPLL System clock fSYS Changes from 40 MHz to 10 MHz Stops PLL operation 10E8H 10E9H (PLLCR0), X0XXXXXXB (PLLCR1), 0XXXXXXXB ; ; Changes fc from 40 MHz to10 MHz. Stop PLL. 92CH21-28 2007-02-28 TMP92CH21 Limitations on the use of PLL 1. It is not possible to execute PLL enable/disable control in the SLOW mode (fs) (writing to PLLCR0 and PLLCR1). PLL should be controlled in the NORMAL mode. 2. When stopping PLL operation during PLL use, execute the following settings in the same order. LD LD (PLLCR0), 00H (PLLCR1), 00H ; ; Change the clock fPLL to fOSCH PLL stop 3. When stopping the high-frequency oscillator during PLL use, stop PLL before stopping the high-frequency oscillator. Examples of settings are shown below: (1) Start up/change control (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) → High-frequency oscillator start up → High-frequency oscillator operation mode (fOSCH) → PLL start up → PLL use mode (fPLL) (SYSCR0), 2, (SYSCR0) NZ, WUP (SYSCR1), (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), 11−−−1−−B; ; ; −−−−0−−−B; LD WUP: BIT JR LD LD LUP: BIT JR LD High-frequency oscillator start/warm-up start Check for warm-up end flag Change the system clock fs to fOSCH PLL start-up/lock up start Check for lock up end flag Change the system clock fOSCH to fPLL 1−−−−−−−B; ; ; −1−−−−−−B; (OK) Low-frequency oscillator operation mode (fs) (high-frequency oscillator Operate) → High-frequency oscillator operation mode (fOSCH) → PLL start up → PLL use mode (fPLL) LD LD LUP: BIT JR LD (SYSCR1), (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), −−−−0−−−B; Change the system clock fs to fOSCH PLL start-up/lock up start Check for lock up end flag Change the system clock fOSCH to fPLL 1−−−−−−−B; ; ; −1−−−−−−B; (Error) Low-frequency oscillator operation mode (fs) (high-frequency oscillator STOP) → High-frequency oscillator start up → PLL start up → PLL use mode (fPLL) LD WUP: BIT JR LD LUP: BIT JR LD LD (SYSCR0), 2, (SYSCR0) NZ, WUP (PLLCR1), 5, (PLLCR0) Z, LUP (PLLCR0), (SYSCR1), 11−−−1−−B; ; ; 1−−−−−−−B; ; ; −1−−−−−−B; −−−−0−−−B; High-frequency oscillator start/warm-up start Check for warm-up end flag PLL start-up/lock up start Check for lock up end flag Change the internal clock fOSCH to fPLL Change the system clock fs to fPLL 92CH21-29 2007-02-28 TMP92CH21 (2) Change/stop control (OK) PLL use mode (fPLL) → High-frequency oscillator operation mode (fOSCH) → PLL Stop → Low-frequency oscillator operation mode (fs) → High-frequency oscillator stop (PLLCR0), (PLLCR1), (SYSCR1), (SYSCR0), −0−−−−−−B; LD LD LD LD Change the system clock fPLL to fOSCH PLL stop Change the system clock fOSCH to fs High-frequency oscillator stop 0−−−−−−−B; −−−−1−−−B; 0−−−−−−−B; (Error) PLL use mode (fPLL) → Low-frequency oscillator operation mode (fs) → PLL stop → High-frequency oscillator stop LD LD LD LD (SYSCR1), (PLLCR0), (PLLCR1), (SYSCR0), − − − − 1 − − − B ; Change the system clock fPLL to fs − 0 − − − − − − B ; Change the internal clock (fC) fPLL to fOSCH 0 − − − − − − − B ; PLL stop 0 − − − − − − − B ; High-frequency oscillator stop (OK) PLL use mode (fPLL) → Set the STOP mode → High-frequency oscillator operation mode (fOSCH) → PLL stop → Halt (High-frequency oscillator stop) LD LD LD HALT (SYSCR2), (PLLCR0), (PLLCR1), −−−−01−−B; −0−−−−−−B; Set the STOP mode (This command can be executed before use of PLL) Change the system clock fPLL to fOSCH PLL stop Shift to STOP mode 0−−−−−−−B; ; (Error) PLL use mode (fPLL) → Set the STOP mode → Halt (High-frequency oscillator stop) LD HALT (SYSCR2), −−−−01−−B; Set the STOP mode (This command can execute before use of PLL) Shift to STOP mode ; 92CH21-30 2007-02-28 TMP92CH21 3.3.5 Noise Reduction Circuits Noise reduction circuits are built-in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator X1 pin Enable oscillation EMCCR0 C2 X2 pin (Setting method) The drive ability of the oscillator is reduced by writing “0” to EMCCR0 register. At reset, is initialized to “1” and the oscillator starts oscillation by normal drivability when the power-supply is on. Note: This function (EMCCR0 = “0”) is available when fOSCH = 6 to 10 MHz. 92CH21-31 2007-02-28 TMP92CH21 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 Resonator EMCCR0 C2 XT2 pin fS XT1 pin Enable oscillation (Setting method) The drive ability of the oscillator is reduced by writing 0 to the EMCCR0 register. At reset, is initialized to “1”. (3) Single drive for high-frequency oscillator (Purpose) Remove the need for twin drives and prevent operational errors caused by noise input to X2 pin when an external oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing “1” to EMCCR0 register. X2 pin’s output is always “1”. At reset, is initialized to “0”. 92CH21-32 2007-02-28 TMP92CH21 (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (memory controller, MMU) which prevent fetch operations. Runaway error handling is also facilitated by INTP0 interruption. Specified SFR list 1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, BROMCR 2. MMU LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 4. PLL PLLCR0, PLLCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 registers. (Double key) 1st KEY: writes in sequence, 5AH at EMCCR1 and A5H at EMCCR2 2nd KEY: writes in sequence, A5H at EMCCR1 and 5AH at EMCCR2 Protection state can be confirmed by reading EMCCR0. At reset, protection becomes OFF. INTP0 interruption also occurs when a write operation to the specified SFR is executed with protection in the ON state. 92CH21-33 2007-02-28 TMP92CH21 3.3.6 Stand-by Controller (1) HALT modes and port drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register and each pin-status is set according to the PxDR register, as shown below: 7 PxDR (xxxxH) Bit symbol Read/Write After reset Function (Purpose and use) • • • • • • 6 Px6D 1 5 Px5D 1 4 Px4D R/W 1 3 Px3D 1 2 Px2D 1 1 Px1D 1 0 Px0D 1 Px7D 1 Output/input buffer drive register for stand-by mode This register is used to set each pin status at stand-by mode. All ports have this registers of the format shown above. (“x” indicates the port name.) For each register, refer to 3.5 function of ports. Before “Halt” instruction is executed, set each register according to the expected pin status. They will be effective after the CPU has executed the “Halt” instruction. This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP). The Output/Input buffer control table is shown below. OE 0 0 1 1 Note 1: PxnD 0 1 0 1 Output Buffer OFF OFF OFF ON Input Buffer OFF ON OFF OFF OE denotes an output enable signal before stand-by mode. Basically, PxCR is used as OE. Note 2: “n” in PxnD denotes the bit number of PORTx The subsequent actions performed in each mode are as follows: 1. IDLE2: only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.3 shows the register setting operation during IDLE2 mode. Table 3.3.3 SFR Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRB0 SIO0 SIO1 AD converter WDT SFR TA01RUN TA23RUN TB0RUN SC0MOD1 SC1MOD1 ADMOD1 WDMOD 2. 3. IDLE1: Only the oscillator, RTC (real-time clock) and MLD continue to operate. STOP: All internal circuits stop operating. 92CH21-34 2007-02-28 TMP92CH21 The operation of each of the different HALT modes is described in Table 3.3.4. Table 3.3.4 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB SIO Block AD converter WDT I2S, LCDC, SDRAMC, Interrupt controller, USBC, RTC, MLD Operate Operate Available to select operation block Stop IDLE2 11 Stop IDLE1 10 Depend on PxDR register setting STOP 01 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination of the states of the interrupt mask register and the HALT modes. The details for releasing the halt status are shown in Table 3.3.5. Release by interrupt requesting The HALT mode release method depends on the status of the enabled interrupt .When the interrupt request level set before executing the HALT instruction exceeds the value of the interrupt mask register, the interrupt is processed depending on its status after the HALT mode is released, and the CPU status executing the instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, HALT mode release is not executed. (in non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT4, INTKEY, INTRTC, INTALM and INTUSB interrupts, even if the interrupt request level set before executing the halt instruction is less than the value of the interrupt mask register, HALT mode release is executed. In this case, the interrupt is processed, and the CPU starts executing the instruction following the HALT instruction, but the interrupt request flag is held at “1”. Release by resetting Release of all halt statuses is executed by resetting. When the STOP mode is released by RESET, it is necessary to allow enough resetting time (see Table 3.3.6) for operation of the oscillator to stabilize. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the HALT instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the HALT instruction is executed.) 92CH21-35 2007-02-28 TMP92CH21 Table 3.3.5 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode INTWD INT0 to INT4 (Note 1) Source of Halt State Clearance Interrupt Enabled (Interrupt level) ≥ (Interrupt mask) IDLE2 ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Interrupt Disabled (Interrupt level) < (Interrupt mask) IDLE2 − IDLE1 × ♦ ♦ × × × × ♦ ♦ ♦*2 × STOP × ♦*1 × × × × × ♦*1 ♦*1 × × IDLE1 − STOP − INTALM0 to INTALM4 INTTA0 to INTTA3, INTTB0 to INTTB1 Interrupt ○ ○ × × × × ○ ○ × × × × ○* 1 × × × × × INTRX0 to INTRX1, TX0 to TX1 INTTBO0, INTI2S INTAD, INT5 INTKEY INTRTC INTUSB INTLCD RESET ○ ○ ○ × ○ ○ ○* 2 × ○* 1 ○* 1 × × Initialize LSI ♦: After clearing the HALT mode, CPU starts interrupt processing. ○: After clearing the HALT mode, CPU resumes executing starting from the instruction following the HALT instruction. ×: Cannot be used to release the HALT mode. −: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. This combination is not available. *1: Release of the HALT mode is executed after warm-up time has elapsed. *2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode, allowing for the construction of low power dissipation systems. However, the method of use is limited as below. Shift to IDLE1 mode : Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state ) Release from IDLE1 mode : Release Halt state by INT_RESUME or INT_CLKON request (release SUSPEND request) Release Halt state by INT_URST_STR or INT_URST_END request (RESET request) Example: Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH LD LD LD EI LD HALT (PCFC), 01H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; ; ; ; ; ; Sets PC0 to INT0. Selects INT0 interrupt rising edge. Sets INT0 interrupt level to 6. Sets interrupt level to 5 for CPU. Sets HALT mode to IDLE1 mode. Halts CPU. INT0 INT0 interrupt routine RETI 820FH LD XX, XX 92CH21-36 2007-02-28 TMP92CH21 (3) Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D31 RD Data Data WR Interrupt for release IDLE2 mode Figure 3.3.7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC and MLD continue to operate. The system clock stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. Figure 3.3.8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D31 RD Data Data WR Interrupt for release IDLE1 mode Figure 3.3.8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 92CH21-37 2007-02-28 TMP92CH21 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.3.9 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D31 RD Data Data WR Interrupt for release STOP mode Figure 3.3.9 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.6 Example of Warm-up Time after Releasing STOP Mode at fOSCH = 40 MHz, fs = 32.768 kHz SYSCR1 0 (fc) 1 (fs) SYSCR2 01 (2 ) 6.4 μs 7.8 ms 8 10 (214) 409.6 μs 500 ms 11 (216) 1.638 ms 2000 ms 92CH21-38 2007-02-28 TMP92CH21 Table 3.3.7 Input Buffer State Table Input Buffer State Input Function Name When the CPU is operating When used as Function pin When used as Input pin In HALT mode (IDLE1/2/STOP) = 1 When used as Function pin When used as Input pin Port Name During Reset = 0 When used as Function pin When used as Input pin D0 to D7 P10 to P17 P20 to P27 P30 to P37 P60 to P67 P71 to P72 P75 P76 P90 P91 P92 P93 to P94 P96 * P97 PA0 to PA7* 1 1 D0 to D7 D8 to D15 D16 to D23 D24 to D31 − − NDRB WAIT OFF 16bit start : OFF 32bit start : OFF Boot start : ON 16bit start : ON 32bit start : OFF Boot start : ON 16bit start : OFF 32bit start : OFF Boot start : ON ON upon external read − OFF − OFF − OFF OFF − − − ON − ON − OFF − − RXD0 CTS0, SCLK0 − ON − ON ON − ON OFF − INT4 INT5 KI0-KI7 INT0 INT1 INT2 INT3 − − − − − OFF ON ON ON OFF PC0 PC1 PC2 PC3 PC6 to PC7 PF0 PF1 PF2 PG0 to PG2* 2 RXD0/1 CTS0/1 SCLK0/1 − ON − ON ON upon port read ON − OFF − PG3 *2 OFF ON OFF ON ADTRG − − ON − ON − ON − PJ5 to PJ6 PL4 to PL7 ON: The buffer is always turned on. A current flows through the input buffer if the input pin is not driven. *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the buffer. OFF: The buffer is always turned off. −: Not applicable 92CH21-39 2007-02-28 TMP92CH21 Table 3.3.8 Output Buffer State Table (1/2) Output Buffer State Output Function Name When the CPU is operating When used as Function pin When used as Output pin In HALT mode (IDLE1/2/STOP) =1 When used as Function pin When used as Output pin Port Name During Reset =0 When used as Function pin When used as Output pin D0~D7 P10~P17 P20~P27 P30~P37 P40~P47 P50~P57 P60~P67 P70 P71 P72 P73 P74 P75 P76 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96* 1 D0~D7 D8~D15 D16~D23, KO0~KO7 D24~D31 A0-A7 A8~A15 A16~A23 − − − OFF ON upon external write OFF ON OFF RD WRLL , NDRE OFF ON OFF ON ON WRLU , NDWE EA24 EA25 R/W − CS0 − − − CS1 , SDCS ON ON OFF CS2 , CSZA , SDCS CS3 CSZB , WRUL , ND0CE CSZC , WRUU , ND1CE CSZD , SRULB CSZE , SRUUB ON ON ON OFF TXD0, I2SCKO I2SDO SCLK0, I2SWS LGOE0 LGOE1 LGOE2, CLK32KO PX PY OFF ON OFF − − − P97 ON: The buffer is always turned on. OFF: The buffer is always turned off. −: Not applicable *1: Port having a pull-up/pull-down resistor. 92CH21-40 2007-02-28 TMP92CH21 Table 3.3.9 Output Buffer State Table (2/2) Output Buffer State Port Name Output Function Name When the CPU is operating When used as Function pin PA3~PA6 PC0 PC1 PC2 PC3 PC6 PC7 PF0 PF1 PF2 PF7 PG2 PG3 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 *1 In HALT mode (IDLE1/2/STOP) =1 When used as Function pin When used as Output pin During Reset =0 When used as Function pin When used as Output pin When used as Output pin LD8~LD11 TA1OUT TA3OUT TB0OUT0 − − − ON ON OFF − KO8, LDIV CSZF , LCP1 OFF − − − ON − ON ON − ON OFF − OFF TXD0, TXD1 − SCLK0, SCLK1 SDCLK MX MY SDRAS , SRLLB SDCAS , SRLUB SDWE , SRWR ON OFF − − − ON SDLLDQM SDLUDQM SDULDQM, NDALE SDUUDQM, NDCLE SDCKE LCP0 LLP LFR LBCD LD0~LD3 LD4~LD7 MLDALM MLDALM , ALARM OFF OFF ON ON ON ON OFF PJ6 PJ7 PK0 PK1 PK2 PK3 PL0~PL3 PL4~PL7 PM1 PM2 X2 ON OFF − − ON − − IDLE2/1:ON, STOP: output ”H” IDLE2/1:ON, STOP: output ”HZ” *1: Port having a pull-up/pull-down resistor. XT2 ON: The buffer is always turned on. OFF: The buffer is always turned off. −: Not applicable 92CH21-41 2007-02-28 TMP92CH21 3.4 Interrupts Interrupts are controlled by the CPU Interrupt mask register (bits12 to 14 of the status register) and by the built-in interrupt controller. The TMP92CH21 has a total of 50 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources Software interrupts: 8 sources Illegal instruction interrupt: 1 source Internal interrupts: 34 sources Internal I/O interrupts: 26 sources Micro DMA transfer end interrupts: 8 sources External interrupts: 7 sources Interrupts on external pins (INT0 to INT5, INTKEY) A fixed individual interrupt vector number is assigned to each interrupt source. Any one of six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority level of 7, the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the CPU. (The highest priority level is 7, the level used for non-maskable interrupts.) The CPU compares the interrupt priority level which it receives with the value held in the CPU interrupt mask register . If the priority level of the interrupt is greater than or equal to the value in the interrupt mask register, the CPU accepts the interrupt. However, software interrupts and illegal instruction interrupts generated by the CPU are processed irrespective of the value in . The value in the interrupt mask register can be changed using the EI instruction (EI num sets to num). For example, the command EI 3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. The commands EI and EI 0 enable the acceptance of all non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence both are equivalent to the command EI 1). The DI instruction (sets to 7) is exactly equivalent to the EI 7 instruction. The DI instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 1 to 6). The EI instruction takes effect as soon as it is executed. In addition to the general purpose interrupt processing mode described above, there is also a micro DMA processing mode. In micro DMA mode the CPU automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transfer to and from internal and external memory and internal I/O ports. In addition, the TMP92CH21 also has a software start function in which micro DMA processing is requested in software rather than by an interrupt. Figure 3.4.1 is a flowchart showing overall interrupt processing. 92CH21-42 2007-02-28 TMP92CH21 Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector ? YES Clear interrupt request flag NO Interrupt vector calue “V” read interrupt request F/F clear Data transfer by micro DMA Micro DMA processing General-purpose interrupt processing PUSH PC PUSH SR SR ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 COUNT ← COUNT − 1 COUNT = 0 NO YES Clear vector register generating micro DMA transfer end interrupt (INTTC0 to 7) PC ← (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST ← INTNEST − 1 End Figure 3.4.1 Interrupt and Micro DMA Processing Sequence 92CH21-43 2007-02-28 TMP92CH21 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4) and (5). (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt requests. (The default priority is determined as follows: the smaller the vector value, the higher the priority.) (2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the stack (pointed to by XSP). (3) The CPU sets the value of the CPU’s interrupt mask register to the priority level for the accepted interrupt plus 1. However, if the priority level for the accepted interrupt is 7, the register’s value is set to 7. (4) The CPU increments the interrupt nesting counter INTNEST by 1. (5) The CPU jumps to the address given by adding the contents of address FFFF00H + the interrupt vector, then starts the interrupt processing routine. On completion of interrupt processing, the RETI instruction is used to return control to the main routine. RETI restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter INTNEST by 1. Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request is received for an interrupt with a priority level equal to or greater than the value set in the CPU interrupt mask register , the CPU will accept the interrupt. The CPU interrupt mask register is then set to the value of the priority level for the accepted interrupt plus 1. If during interrupt processing, an interrupt is generated with a higher priority than the interrupt currently being processed, or if, during the processing of a non-maskable interrupt processing, a non-maskable interrupt request is generated from another source, the CPU will suspend the routine which it is currently executing and accept the new interrupt. When processing of the new interrupt has been completed, the CPU will resume processing of the suspended interrupt. If the CPU receives another interrupt request while performing processing steps (1) to (5), the new interrupt will be sampled immediately after execution of the first instruction of its interrupt processing routine. Specifying DI as the start instruction disables nesting of maskable interrupts. A reset initializes the interrupt mask register to 111, disabling all maskable interrupts. Table 3.4.1 shows the TMP92CH21 interrupt vectors and micro DMA start vectors. FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area. 92CH21-44 2007-02-28 TMP92CH21 Table 3.4.1 TMP92CH21 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 − 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Maskable Nonmaskable Type Interrupt Source and Source of Micro DMA Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction (Reserved) INTWD: Watchdog Timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input (TSI) INTALM0: ALM0 (8 kHz) INTALM1: ALM1 (512 Hz) INTALM2: ALM2 (64 Hz) INTALM3: ALM3 (2 Hz) INTALM4: ALM4 (1 Hz) INTP0: Protect0 (Write to special SFR) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTB0: 16-bit timer 0 INTTB1: 16-bit timer 0 INTKEY: Key-on wakeup INTRTC: RTC (Alarm interrupt) INTTBO0: 16-bit timer 0 (Overflow) INTLCD: LCDC/LP pin INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial transmission (Channel 1) (Reserved) (Reserved) INT5: INT5 pin input INTI2S: I S (Channel 0) INTNDF0 (NAND flash controller channel 0) INTNDF1 (NAND flash controller channel 1) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) INTUSB: USB (Reserved) (Reserved) 2 Vector Value 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H − 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H Micro Address Refer DMA Start to Vector Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H − FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H − (Note1) 0AH (Note 2) 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H (Note 2) 21H 22H (Note 2) 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 92CH21-45 2007-02-28 TMP92CH21 Interrupt Source and Source of Micro DMA Request (Reserved) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) Maskable INTTC4: Micro DMA end (Channel 4) INTTC5: Micro DMA end (Channel 5) INTTC6: Micro DMA end (Channel 6) INTTC7: Micro DMA end (Channel 7) (Reserved) Default Priority 51 52 53 54 55 56 57 58 59 60 − to − Type Vector Value 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H : 00FCH Micro Address Refer DMA Start to Vector Vector FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H : FFFFFCH 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH − to − Note 1: Micro DMA default priority. Micro DMA initiation takes priority over other maskable interrupts. Note 2: When initiating micro DMA, set at edge detect mode. 92CH21-46 2007-02-28 TMP92CH21 3.4.2 Micro DMA Processing In addition to general purpose interrupt processing, the TMP92CH21 also includes a micro DMA function. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (level 6), regardless of the priority level of the interrupt source. Because the micro DMA function is implemented through the CPU, when the CPU is placed in a stand-by state by a Halt instruction, the requirements of the micro DMA will be ignored (pending). Micro DMA supports 8 channels and can be transferred continuously by specifying the micro DMA burst function as below. Note: When using the micro DMA transfer end interrupt, always write “1” to bit 7 of SIMC register. (1) Micro DMA operation When an interrupt request is generated by an interrupt source specified by the micro DMA start vector register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request. The eight micro DMA channels allow micro DMA processing to be set for up to eight types of interrupt at once. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. Data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented by 1. If the value of the counter after it has been decremented is not 0, DMA processing ends with no change in the value of the micro DMA start vector register. If the value of the decremented counter is 0, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from the CPU to the interrupt controller. In addition, the micro DMA start vector register is cleared to 0, the next micro DMA operation is disabled and micro DMA processing terminates. If micro DMA requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (channel 0 thus has the highest priority and channel 7 the lowest). If an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro DMA start vector is cleared and the next setting, general purpose interrupt processing is performed at the interrupt level set. Therefore, if the interrupt is only being used to initiate micro DMA (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e., interrupt requests should be disabled). If micro DMA and general purpose interrupts are being used together as described above, the level of the interrupt which is being used to initiate micro DMA processing should first be set to a lower value than all the other interrupt levels. (Note) In this case, edge triggered interrupts are the only kinds of general interrupts which can be accepted. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA start vector” (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 92CH21-47 2007-02-28 TMP92CH21 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (the upper eight bits of a 32-bit address are not valid). Three micro DMA transfer modes are supported: one-byte transfers, two-byte (one-word) transfer and four-byte transfer. After a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. This simplifies the transfer of data from memory to memory, from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various transfer modes, see section 3.4.2 (1), detailed description of the transfer mode register. Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000H). Micro DMA processing can be initiated by any one of 34 different interrupts – the 33 interrupts shown in the micro DMA start vectors in Table 3.4.1 and a micro DMA soft start. Figure 3.4.2 shows a 2-byte transfer carried out using a micro DMA cycle in transfer destination address INC mode (micro DMA transfers are the same in every mode except counter mode). (The conditions for this cycle are as follows: Both source and destination memory are internal RAM and multiples by 4 numbered source and destination addresses.) 1 state (1) fSYS A23 to A0 (2) (3) (4) (5) src dst Note: In fact, src and dst address are not output to A23 to A0 pins because they are internal RAM address. Figure 3.4.2 Timing for Micro DMA Cycle State (1), (2): Instruction fetch cycle (Prefetches the next instruction code) State (3): State (4): State (5): Micro DMA read cycle Micro DMA write cycle (The same as in state (1), (2)) 92CH21-48 2007-02-28 TMP92CH21 (2) Soft start function The TMP92CH21 can initiate micro DMA either with an interrupt or by using the micro DMA soft start function, in which micro DMA is initiated by a write cycle which writes to the register DMAR. Writing 1 to any bit of the register DMAR causes micro DMA to be performed once. (If write “0” to each bit, micro DMA doesn’t operate). On completion of the transfer, the bits of DMAR which support the end channel are automatically cleared to 0. Only one channel can be set for DMA request at once. (Do not write “1” to plural bits.) When writing again 1 to the DMAR register, check whether the bit is “0” before writing “1”. If read “1”, micro DMA transfer isn’t started yet. When a burst is specified by the DMAB register, data is transferred continuously from the initiation of micro DMA until the value in the micro DMA transfer counter is 0. If execatee soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid writign to other bits by mistake. Symbol Name DMA Request Address 109H (Prohibit RMW) 7 DREQ7 0 6 DREQ6 0 5 DREQ5 0 4 DREQ4 0 R/W 3 DREQ3 0 2 DREQ2 0 1 DREQ1 0 0 DREQ0 0 DMAR 1: DMA request in software (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. An instruction of the form LDC cr, r can be used to set these registers. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0 DMA destination address register 0 DMA counter register 0 DMA mode register 0 Channel 7 DMAS7 DMAD7 DMAC7 DMAM7 8 bits 16 bits 32 bits DMA source address register 7 DMA destination address register 7 DMA counter register 7 DMA mode register 7 92CH21-49 2007-02-28 TMP92CH21 (4) Detailed description of the transfer mode register 0 0 0 Mode DMAM0 to DMAM7 DMAMn[4:0] 000zz Mode Description Destination INC mode (DMADn+) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn Destination DEC mode (DMADn−) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn Source INC mode (DMADn) ← (DMASn+) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn Source DEC mode (DMADn) ← (DMASn−) DMACn ← DMACn − 1 if DMACn = 0 then INTTCn Source and destination INC mode (DMADn+) ← (DMASn+) DMACn ← DMACn − 1 If DMACn = 0 then INTTCn Source and destination DEC mode (DMADn−) ← (DMASn−) DMACn ← DMACn − 1 If DMACn = 0 then INTTCn Source and destination Fixed mode (DMADn) ← (DMASn) DMACn ← DMACn − 1 If DMACn = 0 then INTTCn Counter mode DMASn ← DMASn + 1 DMACn ← DMACn − 1 if DMACn = 0 then INTTCn Execution State Number 5 states 001zz 5 states 010zz 5 states 011zz 5 states 100zz 6 states 101zz 6 states 110zz 5 states 11100 5 states ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (Reserved) Note1: N stands for the micro DMA channel number (0 to 7) DMADn+/DMASn+: Post-increment (register value is incremented after transfer) DMADn−/DMASn−: Post-decrement (register value is decremented after transfer) “I/O” signifies fixed memory addresses; “memory” signifies incremented or decremented memory addresses. Note2: The transfer mode register should not be set to any value other than those listed above. Note3: The execution state number shows number of best case (1-state memory access). 92CH21-50 2007-02-28 TMP92CH21 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left hand side of the diagram shows the interrupt controller circuit. The right hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 52 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when a reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when a micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro DMA start vector to the INTCLR register). An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupt (watchdog timer interrupts) is fixed at 7. If more than one interrupt request with a given priority level are generated simultaneously, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bit of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. If several interrupts are generated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt’s vector address to the CPU. The CPU compares the mask value set in of the status register (SR) with the priority level of the requested interrupt; if the latter is higher, the interrupt is accepted. Then the CPU sets SR to the priority level of the accepted interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in SR (e.g., interrupts with a priority higher than the interrupt being processed) will be accepted. When interrupt processing has been completed (e.g., after execution of a RETI instruction), the CPU restores to SR the priority value which was saved on the stack before the interrupt was generated. The interrupt controller also includes eight registers which are used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (see Table 3.4.1), enables the corresponding interrupts to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to micro DMA processing. 92CH21-51 2007-02-28 Interrupt controller Interrupt request F/F S R V = 20H V = 24H CPU 1 Q Interrupt mask F/F RESET Interrupt request RESET interrupt vector read Decoder Priority encoder signal to CPU IFF2 to 0 3 3 INTRQ2 to 0 3 Interrupt level detect 1 7 6 6 A B C INTWD Priority setting register D Q CLR Interrupt request F/F Dn + 3 Interrupt request F/F 45 Interrupt vector generator Dn Dn + 1 EI 1 t o 7 DI Interrupt request signal Dn + 2 Y1 Y2 Y3 Y4 Y5 Y6 If INTRQ2 to 0 ≥ IFF 2 to 0 then 1. INT0 Reset SQ R D0 D1 Interrupt vector read Micro DMA acknowledge D2 D3 D4 D5 D6 D7 1 A 2 Highest priority B 3 interrupt 4 level select C 5 6 7 INT1 INT2 INT3 INT4 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller Interrupt vector read V = D0H V = D4H V = D8H V = DCH V = E0H V = E4H V = E8H V = ECH 92CH21-52 8 input OR Soft start 8 51 S Selector Halt release Micro DMA counter zero interrupt RESET INT01 to INT4, INTKEY,INTRTC, INTALM, INTUSB Micro DMA request INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Micro DMA start vector setting register D5 D4 D3 D2 D1 D0 DQ CLR 6 INTTC0 DMA0V DMA1V : DMA7V if IFF = 7 then 0 3 3 RESET 0 1 2 3 4 5 6 7 A B C Micro DMA channel priority decoder Micro DMA channel specification TMP92CH21 2007-02-28 TMP92CH21 (1) Interrupt level setting registers Symbol Name INT0 & INTAD enable INT1 INTE12 & INT2 enable INT3 INTE34 & INT4 enable INT5 INTE5I2S & INTI2S enable INTTA0 INTETA01 & INTTA1 enable INTTA2 INTETA23 & INTTA3 enable INTTB0 INTETB01 & INTTB1 enable INTTBO0 INTETBO0 Address 7 IADC R 0 I2C R 0 I4C R 0 II2SC R 0 ITA1C R 0 ITA3C R 0 ITB1C R 0 − 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 INTI2S II2SM2 0 ITA1M2 0 ITA3M2 0 ITB1M2 0 − − 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 II2SM1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 ITB1M1 R/W 0 − 4 IADM0 0 I2M0 0 I4M0 0 II2SM0 0 ITA1M0 0 ITA3M0 0 ITB1M0 0 − 3 I0C R 0 I1C R 0 I3C R 0 I5C R 0 ITA0C R 0 ITA2C R 0 ITB0C R 0 ITBO0C 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 ITA0M2 0 ITA2M2 0 ITB0M2 0 INTTBO0 ITBO0M2 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITB0M1 R/W 0 ITBO0M1 0 I0M0 0 I1M0 0 I3M0 0 I5M0 0 ITA0M0 0 ITA2M0 0 ITB0M0 0 ITBO0M0 INTE0AD F0H D0H D1H EBH INTTA1 (TMRA 1) D4H INTTA0 (TMRA 0) INTTA3 (TMRA 3) D5H INTTA2 (TMRA 2) INTTB1 (TMRA 4) D8H INTTB0 (TMRA 4) (Overflow) enable DAH R Note: Always write 0 0 ITX0M0 0 ITX1M0 0 − IRX0C R 0 IRX1C R 0 IUSB0C R Note: Always write 0 INTALM1 0 0 0 INTTX0 R/W 0 INTRX0 IRX0M2 IRX0M1 R/W 0 INTRX1 IRX1M2 IRX1M1 R/W 0 INTUSB IUSBM1 R/W 0 INTALM0 0 IUSBM0 IRX1M0 0 IRX0M0 0 INTRX0 INTES0 & INTTX0 enable INTRX1 INTES1 & INTTX1 enable DCH ITX1C R 0 − 0 DBH ITX0C R 0 0 ITX0M2 ITX0M1 R/W 0 INTTX1 ITX1M2 ITX1M1 R/W 0 − − INTEUSB INTUSB enable E3H − IUSBM2 INTEALM01 INTALM0 & INTALM1 enable E5H IA1C R 0 IA1M2 0 IA1M1 R/W 0 IA1M0 0 IA3M0 0 IA0C R 0 IA2C R 0 IA0M2 0 IA0M1 R/W 0 IA0M0 0 IA2M0 0 INTALM3 INTEALM23 INTALM2 IA2M2 0 IA2M1 R/W 0 INTALM2 & INTALM3 enable E6H IA3C R 0 IA3M2 0 IA3M1 R/W 0 92CH21-53 2007-02-28 TMP92CH21 Symbol Name INTALM4 enable Address 7 − 6 − − 5 − 4 − 3 IA4C R 0 2 INTALM4 IA4M2 0 INTRTC IRM2 0 INTKEY IKM2 0 INTLCD ILCDM2 0 INTNDF0 IN0M2 0 INTP0 IP0M2 0 1 IA4M1 R/W 0 IRM1 R/W 0 IKM1 R/W 0 ILCDM1 R/W 0 IN0M1 R/W 0 IP0M1 R/W 0 0 IA4M0 0 IRM0 0 IKM0 0 ILCDM0 0 IN0M0 0 IP0M0 0 INTEALM4 E7H Note: Always write 0 − INTERTC INTRTC enable E8H − − − − IRC R 0 Note: Always write 0 − INTEKEY INTKEY enable E9H − − − − IKC R 0 Note: Always write 0 − INTELCD INTLCD enable EAH − − − − ILCD1C R 0 Note: Always write 0 INTNDF0 & INTNDF1 enable INTNDF1 ECH IN1C R 0 − 0 − INTEP0 INTP0 enable EEH − − − IN1M2 IN1M1 R/W 0 0 IN1M0 INTEND01 IN0C R 0 IP0C R 0 Note: Always write 0 lxxM2 0 0 0 0 Interrupt request flag 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 92CH21-54 2007-02-28 TMP92CH21 Symbol Name INTTC0 & INTTC1 enable INTTC2 & INTTC3 enable INTTC4 & INTTC5 enable INTTC6 & INTTC7 enable Address 7 ITC1C R 0 ITC3C R 0 ITC5C R 0 ITC7C R 0 6 ITC1M2 0 ITC3M2 0 ITC5M2 0 ITC7M2 0 − − 5 ITC1M1 R/W 0 ITC3M1 R/W 0 ITC5M1 R/W 0 ITC7M1 R/W 0 − 4 ITC1M0 0 ITC3M0 0 ITC5M0 0 ITC7M0 0 − 3 ITC0C R 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 ITCWD R 0 2 ITC0M2 0 ITC2M2 0 ITC4M2 0 ITC6M2 0 INTWD − − 1 ITC0M1 R/W 0 ITC2M1 R/W 0 ITC4M1 R/W 0 ITC6M1 R/W 0 − − 0 ITC0M0 0 ITC2M0 0 ITC4M0 0 ITC6M0 0 − − INTTC1 (DMA1) F1H INTTC0 (DMA0) INTETC01 INTTC3 (DMA3) F2H INTTC2 (DMA2) INTETC23 INTTC5 (DMA5) F3H INTTC4 (DMA4) INTETC45 INTTC7 (DMA7) INTETC67 F4H INTTC6 (DMA6) INTWDT INTWD enable F7H − Note: Always write 0 lxxM2 0 0 0 0 Interrupt request flag 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 92CH21-55 2007-02-28 TMP92CH21 (2) External interrupt control Symbol Name Address 7 I5EDGE W Interrupt input mode control 0 F6H 6 I4EDGE W 0 5 I3EDGE W 0 4 I2EDGE W 0 3 I1EDGE W 0 2 I0EDGE W 0 1 I0LE R/W 0 0 − R/W 0 Always write “0” IIMC INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE 0: INT0 (Prohibit edge 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising RMW) mode 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: Falling 1: INT0 level mode *INT0 level enable 0 Edge detect INT 1 “H” level INT Note 1: Disable INT0 request before changing INT0 pin mode from level sense to edge sense. Setting example: DI LD LD NOP NOP NOP EI (IIMC), XXXXXX00B ; Switches from level to edge. (INTCLR), 0AH ; Clears interrupt request flag. ; Wait EI execution X: Don’t care, −: No change. Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. Settings of External Interrupt Pin Function Interrupt Pin Name Mode Rising edge INT0 PC0 Falling edge High level Rising edge INT1 PC1 Falling edge Rising edge INT2 PC2 Falling edge Rising edge INT3 PC3 Falling edge Rising edge INT4 P96 Falling edge Rising edge INT5 P97 Falling edge = 0, = 0 = 0, = 1 = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 Setting Method 92CH21-56 2007-02-28 TMP92CH21 (3) SIO receive interrupt control Symbol Name Address 7 − W SIO SIMC interrupt mode control F5H (Prohibit RMW) 0 Always write “0” (Note) 6 5 4 3 2 1 IR1LE W 1 0 IR0LE W 1 0: INTRX1 0: INTRX0 edge edge mode mode 1: INTRX1 1: INTRX0 level level mode mode Note: When using the micro DMA transfer end interrupt, always write “1”. INTRX1 level enable 0 Edge detect INTRX1 1 “H” level INTRX1 INTRX0 rising edge enable 0 Edge detect INTRX0 1 “H” level INTRX0 92CH21-57 2007-02-28 TMP92CH21 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH Symbol Name Interrupt clear control Clears interrupt request flag INT0. 6 CLRV6 0 Address F8H (Prohibit RMW) 7 CLRV7 5 CLRV5 0 4 CLRV4 W 0 3 CLRV3 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 INTCLR 0 Interrupt vector (5) Micro DMA start vector registers These registers assign micro DMA processing to sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel’s micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) 92CH21-58 2007-02-28 TMP92CH21 Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 DMA4V4 0 DMA5V4 0 DMA6V4 0 DMA7V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 DMA4V3 0 DMA5V3 0 DMA6V3 0 DMA7V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 DMA4V2 0 DMA5V2 0 DMA6V2 0 DMA7V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 DMA4V1 0 DMA5V1 0 DMA6V1 0 DMA7V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA4V0 0 DMA5V0 0 DMA6V0 0 DMA7V0 0 DMA0V start vector 100H 0 DMA1V5 101H 0 DMA2V5 102H 0 DMA3V5 103H 0 DMA4V5 104H 0 DMA5V5 105H 0 DMA6V5 106H 0 DMA7V5 107H 0 DMA0 start vector DMA1 DMA1V start vector R/W DMA1 start vector DMA2 DMA2V start vector R/W DMA2 start vector DMA3 DMA3V start vector R/W DMA3 start vector DMA4 DMA4V start vector R/W DMA4 start vector DMA5 DMA5V start vector R/W DMA5 start vector DMA6 DMA6V start vector R/W DMA6 start vector DMA7 DMA7V start vector R/W DMA7 start vector 92CH21-59 2007-02-28 TMP92CH21 (6) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Symbol Name DMA burst Address 7 DBST7 6 DBST6 0 5 DBST5 0 4 DBST4 R/W 0 3 DBST3 0 2 DBST2 0 1 DBST1 0 0 DBST0 0 DMAB 108H 0 1: DMA burst request 92CH21-60 2007-02-28 TMP92CH21 (7) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0004H and jump to interrupt vector address FFFF04H. To avoid this, an instruction which clears an interrupt request flag should always be placed after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3−instructions (e.g., “NOP” × 3 times). If it placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enabled before request flag is cleared. In the case of changing the value of the interrupt mask register by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, please note that the following two circuits are exceptional and demand special attention. INT0 level mode In level mode INT0 is not an edge triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H NOP NOP NOP EI ; Switches from level to edge. ; Wait EI execution LD (INTCLR), 0AH ; Clears interrupt request flag. INTRX In level mode (the register SIMC set to “0”), the interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input changes from high to low after an interrupt request has been generated in level mode. (“H” → “L”) INTRX: Instructions which read the receive buffer. INTRX: Instructions which read the receive buffer. 92CH21-61 2007-02-28 TMP92CH21 3.5 Function of Ports The TMP92CH21 I/O port pins are shown in Table 3.5.1 and Table 3.5.2. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.5.3 to Table 3.5.5 list the I/O registers and their specifications. Table 3.5.1 Port Functions (1/2) (R: PD = with programmable pull-down resistor, U = with pull-up resistor) Port Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Pin Name P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 P71 P72 P73 P74 P75 P76 Number of Pins 8 8 8 8 8 8 1 1 1 1 1 1 1 I/O I/O I/O I/O O O I/O Output I/O I/O Output Output I/O I/O R − − − − − − − − − − − − − − − − − − − I/O Setting Bit Bit Bit (Fixed) (Fixed) Bit (Fixed) Bit Bit (Fixed) (Fixed) Bit Pin Name for Built-in Function D8 to D15 D16 to D23, KO0 to KO7 D24 to D31 A0 to A7 A8 to A15 A16 to A23 RD WRLL , NDRE WRLU , NDWE EA24 EA25 R/ W , NDR/ B WAIT CS0 CS1 , SDCS CS2 , CSZA , SDCS CS3 CSZB , WRUL , ND0CE CSZC , WRUU , ND1CE CSZD , SRULB CSZE , SRUUB TXD0, I2SCKO Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Port 8 Port 9 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 to PA2 PA3 to PA6 PA7 PC0 PC1 PC2 PC3 PC6 PC7 PF0 PF1 PF2 PF7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 4 1 1 1 1 1 1 1 1 1 1 1 Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O Output Input Input Input I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O Output − − − − − − − − RXD0, I2SDO SCLK0, CTS0 , I2SWS LGOE0 LGOE1 LGOE2, CLK32KO INT4, PX INT5, PY KI0 to KI2 LD8 to LD11, KI3 to KI6 KI7 INT0, TA1OUT INT1, TA3OUT INT2, TB0OUT0 INT3 KO8, LDIV CSZF , LCP1 TXD0, TXD1 RXD0, RXD1 SCLK0, CTS0 , SCLK1, CTS1 SDCLK PD − Port A Port C Port F U U U − − − − − − − − − − 92CH21-62 2007-02-28 TMP92CH21 Table 3.5.2 Port Functions (2/2) (R: PD = with programmable pull-down resistor, U = with pull-up resistor) Port Name Port G Pin Name PG0 to PG1 PG2 PG3 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PK0 PK1 PK2 PK3 PL0 to PL3 PL4 to PL7 PM1 PM2 Number of Pins 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 1 1 I/O Input Input Input Output Output Output Output Output I/O I/O Output Output Output Output Output Output I/O Output Output R − − − − − − − − − − − − − − − − − − − I/O Setting (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit (Fixed) (Fixed) Pin Name for Built-in Function AN0 to AN1 AN2, MX AN3, ADTRG , MY SDRAS , SRLLB SDCAS , SRLUB SDWE , SRWR SDLLDQM SDLUDQM SDULDQM, NDALE SDUUDQM, NDCLE SDCKE LCP0 LLP LFR LBCD LD0 to LD3 LD4 to LD7 MLDALM ALARM , MLDALM Port J Port K Port L Port M 92CH21-63 2007-02-28 TMP92CH21 Table 3.5.3 I/O Registers and Specifications (1/3) X: Don’t care Port Port 1 Pin Name P10 to P17 Input port Output port Specification I/O Register Pn X X X X X X X X X X X X X X X X X X X X 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X None PnCR 0 1 X 0 1 X 1 0 1 X None PnFC PnFC2 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 X 1 0 1 1 1 0 1 1 0 1 1 X 1 X 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 1 None None None None 0 0 0 1 None D8 to D15 bus Port 2 P20 to P27 Input port Output port D16 to D23 bus KO0 to KO7 Port 3 P30 to P37 Input port Output port D24 to D31 bus Port 4 P40 to P47 Output port A0 to A7 output Port 5 P50 to P57 Output port A8 to A15 output Port 6 P60 to P67 Input port Output port A16 to A23 output Port 7 P71 to P72 P75 to P76 P70 to P76 P70 P71 Input port Output port RD output WRLL output NDRE output None 0 1 X 0 1 None 1 1 1 1 None 1 0 0 None P72 WRLU output NDWE output P73 P74 P75 P76 Port 8 P80 to P87 P80 P81 P82 EA24 output EA25 output R/ W output NDR/ B input WAIT input Output Port CS0 output CS1 output SDCS output CS2 output CSZA Output SDCS output P83 P84 CS3 output CSZB output WRUL output ND0CE output P85 CSZC output WRUU output ND1CE output P86 P87 CSZD output SRULB output CSZE output SRUUB output 92CH21-64 2007-02-28 TMP92CH21 Table 3.5.4 I/O Registers and Specifications (2/3) X: Don’t care Port Port 9 Pin Name P90 to P94, P96 to P97 P90 to P94 P95 P90 Input port Output port Specification Pn X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X I/O Register PnCR 0 1 0 1 0 1 0 0 1 0 0 0 0 0 1 None None 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1/0 0 0 1 0 0 0 None PnFC PnFC2 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 None 0 0 1 0 None None None None None None None None None 0 0 0 0 0 1 TXD0 output I2SCKO output TXD0 output (Open drain) P91 RXD0 input I2SDO output P92 SCLK0 output I2SWS output SCLK0, CTS0 input (Note1) P93 P94 P95 LGOE0 output LGOE1 output LGOE2 output CLK32KO output P96 P97 Port A PA0 to PA7 PA3 to PA6 Port C PC0 to PC3 PC6 to PC7 PC0 PC1 PC2 INT4 input INT5 input Input port KI0 to KI7 input LD8 to LD11 output Input port Output port INT0 input TA1OUT output INT1 input TA3OUT output INT2 input TB0OUT0 output PC3 PC6 PC7 Port F PF0 to PF2 PF0 to PF2, PF7 INT3 input LDIV output KO8 output (Open drain) LCP1 output CSZF output Input port Output port TXD0 output TXD1 output TXD0/TXD1 output (Open drain) PF0 PF1 PF2 RXD0 input RXD1 input SCLK0 output SCLK1 output SCLK0, CTS0 input SCLK1, CTS1 input PF7 SDCLK output Note: To use P92-pin as SCLK0 input or CTS0 input, set “1” to PF 92CH21-65 2007-02-28 TMP92CH21 Table 3.5.5 I/O Registers and Specifications (3/3) X: Don’t care Port Port G Pin Name PG0 to PG3 PG3 PG2 PG3 Input port Specification I/O Register Pn PnCR PnFC PnFC2 AN0 to AN3 input ADTRG input X None None None MX output MY output Output port Input port SDRAS , SRLLB output SDCAS , SRLUB output SDWE , SRWR output Port J PJ0 to PJ7 PJ5 to PJ6 PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 X X X X X X 1 1 0 1 0 X X X X X X X X X X X 0 1 1 0 0 0 1 1 None 1 1 1 None SDLLDQM output SDLUDQM output SDULDQM output NDALE output SDUUDQM output NDCLE output SDCKE output Output port LCP0 output LLP output LFR output LBCD output Input Port Output Port LD0 to LD7 output Output Port MLDALM output MLDALM output ALARM output 1 1 1 1 None 1 1 1 1 1 0 1 Port K PK0 to PK3 PK0 PK1 PK2 PK3 None 1 1 1 None Port L PL4 to PL7 PL0 to PL7 PL0 to PL7 0 1 1 0 0 1 0 1 1 1 None Port M PM1 to PM2 PM1 PM2 None None 92CH21-66 2007-02-28 TMP92CH21 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15). AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting Data bus (D8 to D15) Data bus (D8 to D15) Input port P1CR register P1FC register External write enable P1 register S 0 D8 to D15 S Port read data 1 0 Selector 1 Selector P10 to P17 (D8 to D15) D8 to D15 External read enable Figure 3.5.1 Port 1 92CH21-67 2007-02-28 TMP92CH21 Port 1 register 7 P1 (0004H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to “0”) Port 1 Control register 7 P1CR (0006H) Bit symbol Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 2 P12C 0 1 P11C 0 0 P10C 0 0: Input 1: Output Port 1 Function register 7 P1FC (0007H) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 P1F W 0/1 Note 2 0: Port 1: Data bus (D8 to D15) Port 1 Drive register 7 P1DR (0081H) Bit symbol Read/Write After reset Function 1 1 1 1 P17D 6 P16D 5 P15D 4 P14D W 3 P13D 1 2 P12D 1 1 P11D 1 0 P10D 1 Input/Output buffer drive register for standby mode Note1: Read-modify-write is prohibited for P1CR and P1FC. Note2: It is set to “Port” or “Data bus” by AM pin setting. Figure 3.5.2 Register for Port 1 92CH21-68 2007-02-28 TMP92CH21 3.5.2 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P2CR and function register P2FC. In addition to functioning as a general-purpose I/O port, port 2 can also function either as a data bus (D16 to D23) or keyboard interface pin KO0 to KO7 which can be set to open-drain output buffer. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting Input port Data bus (D16 to D23) Input port P2CR register P2FC2 register P2FC register External write enable P2 register S 0 D16 to D23 S Port read data 1 0 Selector 1 Open-drain Selector enable P20 to P27 (D16 to D23, KO0 to KO7) D16 to D23 External read enable Figure 3.5.3 Port 2 92CH21-69 2007-02-28 TMP92CH21 Port 2 register 7 P2 (0008H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Data from external port (Output latch register is cleared to “0”) Port 2 Control register 7 P2CR (000AH) Bit symbol Read/Write After reset Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 3 P23C 0 2 P22C 0 1 P21C 0 0 P20C 0 0: Input 1: Output Port 2 Function register 7 P2FC (000BH) Bit symbol Read/Write After reset Note 2 Function 6 5 4 3 2 1 0 P2F W 0/1 0: Port 1: Data bus (D16to D23) Port 2 Function register 2 7 P2FC2 (0009H) Bit symbol Read/Write After reset Function 0 0 0 0 P27F2 6 P26F2 5 P25F2 4 P24F2 W 3 P23F2 0 2 P22F2 0 1 P21F2 0 0 P20F2 0 0: CMOS output 1: Open-drain output Port 2 Drive register 7 P2DR (0082H) Bit symbol Read/Write After reset Function 1 1 1 1 P27D 6 P26D 5 P25D 4 P24D W 3 P23D 1 2 P22D 1 1 P21D 1 0 P20D 1 Input/Output buffer drive register for standby mode Note 1: Read-modify-write instruction is prohibited for P2CR, P2FC and P2FC2. Note 2: It is set to “Port” or “Data bus” by AM pin setting. Figure 3.5.4 Register for Port 2 92CH21-70 2007-02-28 TMP92CH21 3.5.3 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P3CR and function register P3FC. In addition to functioning as a general-purpose I/O port, port 3 can also function as a data bus (D24 to D31). AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting Input port Data bus (D24 to D31) Input port P3CR register P3FC register External write enable P3 register S 0 D24 to D31 S Port read data 1 0 Selector 1 Selector P30 to P37 (D24 to D31) D24 to D31 External read enable Figure 3.5.5 Port 3 92CH21-71 2007-02-28 TMP92CH21 Port 3 register 7 P3 (000CH) Bit symbol Read/Write After reset P37 6 P36 5 P35 4 P34 R/W 3 P33 2 P32 1 P31 0 P30 Data from external port (Output latch register is cleared to “0”) Port 3 Control register 7 P3CR (000EH) Bit symbol Read/Write After reset Function 0 0 0 0 P37C 6 P36C 5 P35C 4 P34C W 3 P33C 0 2 P32C 0 1 P31C 0 0 P30C 0 0: Input 1: Output Port 3 Function register 7 P3FC (000FH) Bit symbol Read/Write After reset Function 0 6 5 4 3 − 2 − 1 − 0 P3F W 0/1 Note 2 0: Port 1: Data bus (D24 to D31) W 0 Always write “0” 0 Port 3 Drive register 7 P3DR (0083H) Bit symbol Read/Write After reset Function 1 1 1 1 P37D 6 P36D 5 P35D 4 P34D W 3 P33D 1 2 P32D 1 1 P31D 1 0 P30D 1 Input/Output buffer drive register for standby mode Note 1: Read-modify-write instruction is prohibited for P3CR, P3FC and P3FC2. Note 2: It is set to “Port” or “Data bus” by AM pin setting. Figure 3.5.6 Register for Port 3 92CH21-72 2007-02-28 TMP92CH21 3.5.4 Port 4 (P40 to P47) Port 4 is an 8-bit general-purpose output port. In addition to functioning as a general-purpose output port, port 4 can also function as an address bus (A0 to A7). AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting Address bus (A0 to A7) Address bus (A0 to A7) Output port P4FC register P4 register S 0 A0 to A7 Port read data 1 Selector P40 to P47 (A0 to A7) Figure 3.5.7 Port 4 92CH21-73 2007-02-28 TMP92CH21 Port 4 register 7 P4 (0010H) Bit symbol Read/Write After reset 0 0 0 0 P47 6 P46 5 P45 4 P44 R/W 3 P43 0 2 P42 0 1 P41 0 0 P40 0 Port 4 Function register 7 P4FC (0013H) Bit symbol Read/Write After reset Note 2 Function 0/1 0/1 0/1 0/1 P47F 6 P46F 5 P45F 4 P44F W 3 P43F 2 P42F 1 P41F 0 P40F 0/1 0/1 0/1 0/1 0: Port 1: Address bus (A0 to A7) Port 4 Drive register 7 P4DR (0084H) Bit symbol Read/Write After reset Function 1 1 1 1 P47D 6 P46D 5 P45D 4 P44D W 3 P43D 1 2 P42D 1 1 P41D 1 0 P40D 1 Input/Output buffer drive register for standby mode Note 1: Read-modify-write is prohibited for P4FC. Note 2: It is set to “Port” or “Address bus” by AM pin setting. Figure 3.5.8 Register for Port 4 92CH21-74 2007-02-28 TMP92CH21 3.5.5 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose output port. In addition to functioning as a general-purpose I/O port, port 5 can also function as an address bus (A8 to A15). AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting Address bus (A8 to A15) Address bus (A8 to A15) Output port P5FC register P5 register S 0 A8 to A15 Port read data 1 Selector P50 to P57 (A8 to A15) Figure 3.5.9 Port 5 92CH21-75 2007-02-28 TMP92CH21 Port 5 register 7 P5 (0014H) Bit symbol Read/Write After reset 0 0 0 0 P57 6 P56 5 P55 4 P54 R/W 3 P53 0 2 P52 0 1 P51 0 0 P50 0 Port 5 Function register 7 P5FC (0017H) Bit symbol Read/Write After reset Note 2 Function 0/1 0/1 0/1 0/1 P57F 6 P56F 5 P55F 4 P54F W 3 P53F 2 P52F 1 P51F 0 P50F 0/1 0/1 0/1 0/1 0: Port 1: Address bus (A8 to A15) Port 5 Drive register 7 P5DR (0085H) Bit symbol Read/Write After reset Function 1 1 1 1 P57D 6 P56D 5 P55D 4 P54D W 3 P53D 1 2 P52D 1 1 P51D 1 0 P50D 1 Input/Output buffer drive register for standby mode Note 1: Read-modify-write is prohibited for P5FC. Note 2: It is set to “Port” or “Address bus” by AM pin setting. Figure 3.5.10 Register for Port 5 92CH21-76 2007-02-28 TMP92CH21 3.5.6 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port 6 can also function as an address bus (A16 to A23). AM1 0 0 1 1 AM0 0 1 0 1 P6CR register Function Setting after Reset is Released Don’t use this setting Address bus (A16 to A23) Address bus (A16 to A23) Input port P6FC register (Reserved) P6 register S 0 A16 to A23 S Port read data 1 0 Selector 1 Selector P60 to P67 (A16 to A23) Figure 3.5.11 Port 6 92CH21-77 2007-02-28 TMP92CH21 Port 6 register 7 P6 (0018H) Bit symbol Read/Write After reset P67 6 P66 5 P65 4 P64 R/W 3 P63 2 P62 1 P61 0 P60 Data from external port (Output latch register is cleared to “0”) Port 6 Control register 7 P6CR (001AH) Bit symbol Read/Write After reset Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 3 P63C 0 2 P62C 0 1 P61C 0 0 P60C 0 0: Input 1: Output Port 6 Function register 7 P6FC (001BH) Bit symbol Read/Write After reset Note 2 Function 0/1 0/1 0/1 0/1 P67F 6 P66F 5 P65F 4 P64F W 3 P63F 2 P62F 1 P61F 0 P60F 0/1 0/1 0/1 0/1 0: Port 1: Address bus (A16 to A23) Port 6 Drive register 7 P6DR (0086H) Bit symbol Read/Write After reset Function 1 1 1 1 P67D 6 P66D 5 P65D 4 P64D W 3 P63D 1 2 P62D 1 1 P61D 1 0 P60D 1 Input/Output buffer drive register for standby mode Note 1: Read-modify-write is prohibited for P6CR and P6FC. Note 2: It is set to “Port” or “Address bus” by AM pin setting. Figure 3.5.12 Register for Port 6 92CH21-78 2007-02-28 TMP92CH21 3.5.7 Port 7 (P70 to P76) Port 7 is a 7-bit general-purpose I/O port (P70, P73 and P74 are used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function as interface pins for external memory. A reset initializes P70, P73 and P74 pins to output port mode, and P71, P72, P75 and P76 pin to input port mode. AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting RD pin RD pin P70 output port P7FC register P7 register 0 RD , EA24, EA25 S 1 Selector P70( RD ) P73(EA24) P74(EA25) Port read data P7CR register P7FC register S 0 S NDRE , NDWE WRLL , WRLU P7 register 0 1 S 1 0 Selector 1 Selector P71 ( WRLL , NDRE ) P72 ( WRLU , NDWE ) Port read data Figure 3.5.13 Port 7 92CH21-79 2007-02-28 TMP92CH21 P7CR register P7FC register S 0 1 Selector S Port read data 1 0 NDR/ B P75 (R/ W , NDR/ B ) P7 register R/ W P7CR register P7FC register P7 register P76 ( WAIT ) Port read data WAIT Figure 3.5.14 Port 7 92CH21-80 2007-02-28 TMP92CH21 Port 7 register 7 P7 (001CH) Bit symbol Read/Write After reset Data from external port (Output latch register is set to “1”) 0 6 P76 5 P75 4 P74 3 P73 R/W 0 2 P72 1 P71 0 P70 Data from external port (Output latch register is set to “1”) 1 Port 7 Control register 7 P7CR (001EH) Bit symbol Read/Write After reset Function 0 6 P76C W 5 P75C 0 4 3 2 P72C W 0 1 P71C 0 0 0: Input port, 0: Input port, WAIT NDR/ B 1:Output port 1:Output port, R/ W Refer to following table Port 7 Function register 7 P7FC (001FH) Bit symbol Read/Write After reset Function 0 0 0 0: port 1: EA25 Refer to following table 6 P76F 5 P75F 4 P74F 3 P73F W 0 0: port 1: EA24 2 P72F 0 1 P71F 0 0 P70F 0/1 Note 2 0: port 1: RD Refer to following table Port 7 Drive register 7 P7DR (0087H) Bit symbol Read/Write After reset Function P72 Setting 0 0 Input port 1 Output port NDWE output 6 P76D 1 5 P75D 1 4 P94D 1 3 P73D R/W 1 2 P72D 1 1 P71D 1 0 P70D 1 Input/Output buffer drive register for standby mode P71 Setting 0 0 Input port 1 Output port NDRE output 1 (Reserved) (at = 0) WRLH output (at = 1) 1 (Reserved) at ( = 0) WRLL output (at = 1) P76 Setting 0 1 0 Input port WAIT input P75 Setting 1 Output port (Reserved) 0 1 0 Input port NDR/ B input 1 Output port R/ W output Note 1: Read-modify-write is prohibited for P7CR and P7FC. Note 2: It is set to “Port” or “ RD ” by AM pin setting. Note 3: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch. Order (1) (2) (3) Register P7 P7FC P7CR Bit2 0 1 1 Bit1 0 1 1 Figure 3.5.15 Register for Port 7 92CH21-81 2007-02-28 TMP92CH21 3.5.8 Port 8 (P80 to P87) Ports 80 to 87 are 8-bit output ports. Resetting sets the output latch of P82 to “0” and the output latches of P80 to P81, P83 to P87 to “1”. Port 8 can also be set to function as an interface pin for external memory using function register P8FC. Writing “1” in the corresponding bit of P8FC and P8FC2 enables the respective functions. Resetting to of P8FC to “0” and P8FC2 to “0”, sets all bits to output ports. Port 82 Initial State AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset is Released Don’t use this setting “0” Output port “0” Output port “1” Output port Reset Function control 2 P8FC2 write Internal data bus Function contol P8FC write Ouptut latch Selector P8 write P80 ( CS0 ) P81 ( CS1 , SDCS ) P82 ( CS2 , CSZA , SDCS ) P83 ( CS3 ) P84 ( CSZB , WRUL , ND0CE ) P85 ( CSZC , WRUU , ND1CE ) P86 ( CSZD , SRULB ) P87 ( CSZE , SRUUB ) P8 read “1”, “1”, SDCS , “1”, ND0CE , ND1CE , “1”, “1”, “1”, SDCS , CSZA , “1”, WRUL , WRUU , SRULB , SRUUB CS0 , CS1 , CS2 , CS3 , CSZB , CSZC , CSZD , CSZE Figure 3.5.16 Port 8 92CH21-82 2007-02-28 TMP92CH21 Port 8 Register 7 P8 (0020H) Bit symbol Read/Write After reset 1 1 1 1 P87 6 P86 5 P85 4 P84 R/W 3 P83 1 2 P82 0/1 Note2 1 P81 1 0 P80 1 Port 8 Function Register 7 P8FC (0023H) Bit symbol Read/Write After reset Function 0 0: Port 1: CSZE 0 0: Port 1: CSZD 0 Refer to following table 0 Refer to following table P87F 6 P86F 5 P85F 4 P84F W 3 P83F 0 0: Port 1: CS3 2 P82F 0 Refer to following table 1 P81F 0 0: Port 1: CS1 0 P80F 0 0: Port 1: CS0 Port 8 Function Register 2 7 P8FC2 (0021H) Bit symbol Read/Write After reset Function 0 0: 1: SRUUB 0 0: 1: SRULB 0 Refer to following table 0 Refer to following table P87F2 6 P86F2 5 P85F2 4 P84F2 W 3 P83F2 0 Always write “0” 2 P82F2 0 1 P81F2 0 0 P80F2 0 Always write “0” Refer to 0: table below 1: SDCS Port 8 Drive Register 7 P8DR (0088H) Bit symbol Read/Write After reset Function 1 1 1 1 P87D 6 P86D 5 P85D 4 P84D R/W 3 P83D 1 2 P82D 1 1 P81D 1 0 P80D 1 Input/Output buffer drive register for standby mode P85 Setting 0 0 1 Output port WRUU output CSZC output ND1CE output P84 Setting 1 0 1 Output port CSZB output WRUL output ND0CE output P82 Setting 0 1 0 1 Output port CS2 output CSZA output SDCS output 0 1 Note 1: Read-modify-write is prohibited for P8FC and P8FC2. Note 2: It is set to “0” or “1” by AM pin setting. Note 3: In MULTI16 or MULTI32 mode, do not write “1” to P8 register before setting P82 pin to CS2 or CSZA because, on reset, P82 pin outputs “0” as CE for program memory. Figure 3.5.17 Register for Port 8 92CH21-83 2007-02-28 TMP92CH21 3.5.9 Port 9 (P90 to P97) P90 to P94 are 5-bit general-purpose I/O ports. I/O can be set on a bit basis using the control register. Resetting sets P90 to P94 to input port and all bits of output latch to“1”. P95 is 1-bit general-purpose output port and P96 to P97 are 2-bit general-purpose input ports. P90 to P92 function as SIO or I2S, P93 to 95 as output pins for an LCD controller and P96 to P97 as input pins for external interruption (INT4, INT5). In addition, P95 functions as the output pin for a low frequency oscillator, P96 to P97 as PX and PY pins for a touch screen interface. Setting the corresponding bits of P9CR and P9FC enables the respective functions. Resetting resets the P9FC to “0”, and sets all bits except P95 to input ports. (1) Port 90 (TXD0, I2SCKO), Port91 (RXD0, I2SDO), Port 92 (SCLK0, CTS0 I2SWS) Ports 90 to 92 are general-purpose I/O ports. They also function as either SIO0 or I2S. Each pin is detailed below. SIO mode (SIO0 module) P90 P91 P92 TXD0 (Data output) RXD0 (Data input) SCLK0 (Clock input or output) UART, IrDA mode (SIO0 module) TXD0 (Data output) RXD0 (Data input) CTS0 I2S mode (I S module) I2SCKO (Clock output) I2SDO (Data output) I2SWS (Word select output) 2 SIO mode (I2S module) I2SCKO (Clock output) I2SDO (Data output) (No use) (Clear to send) Reset Direction control P9CR write Internal data bus Function control P9FC write S Output latch S A Selector B S B Selector A P90 (TXD0, I2SCKO) Open-drain enable P9FC2 P9 write TXD0, I2SCKO output P9 read Figure 3.5.18 P90 92CH21-84 2007-02-28 TMP92CH21 Reset Direction control P9CR write Internal data bus Function control P9FC write S Output latch S A Selector B S B Selector A (to Port F1) P91RXD0 input (to Port F2) P92SCLK0 input P91 (RXD0, I2SDO) P92 (SCLK0, CTS0 , I2SWS) P9 write I2SDO output SCLK0,I2SWS output P9 read Figure 3.5.19 P91 and P92 (2) P93 (LGOE0), P94 (LGOE1) Reset Direction control P9CR write Internal data bus Function control P9FC write S Output latch S A Selector B P93(LGOE0), P94(LGOE1) P9 write LGOE0, LGOE1 S B Selector A P9 read Figure 3.5.20 Port 93 and 94 92CH21-85 2007-02-28 TMP92CH21 (3) P95 (CLK32KO, LGOE2) Reset Direction control P9CR write Internal data bus Function control P9FC write Output latch P9 write LGOE2 fs S A Selector B C P95 (LGOE2, CLK32KO) P9 read Figure 3.5.21 Port 95 (4) P96 (INT4, PX), P97 (INT5, PY) Internal data bus Reset Function control TSICR0 P9FC write TSICR0 AVCC Switch for TSI Typ.20Ω P9 read P96 (INT4, PX) P97 (INT5, PY) TSICR1 S Rising/Falling edge detection IIMC A Selector B De-bounce circuit Only for P96 INT4 INT5 TSICR0 TSICR0 TSICR0 Pull-down resistor typ.200kΩ Figure 3.5.22 Port 96, 97 92CH21-86 2007-02-28 TMP92CH21 Port 9 Register 7 P9 (0024H) Bit symbol Read/Write After reset P97 R Data from external port 0 6 P96 5 P95 4 P94 3 P93 R/W 2 P92 1 P91 0 P90 Data from external port (Output latch register is set to “1”) Port 9 Function Register 7 P9FC (0026H) Bit symbol Read/Write After reset Function 0 0 0 6 5 P95C 4 P94C 3 P93C W 2 P92C 0 1 P91C 0 0 P90C 0 Refer to following table Port 9 Function Register 7 P9FC (0027H) Bit symbol Read/Write After reset Function 0 0: Input port 1: INT5 6 P96F 0 0: Input port 1: INT4 5 P95F 0 4 P94F W 0 3 P93F 0 2 P92F 0 1 P91F 0 0 P90F 0 P97F Refer to following table P92 Setting 0 0 1 P95 Setting 0 0 1 Output port LGOE2 output CLK32KO output P91 Setting 1 Input port SCLK0, CTS0 input P90 Setting 0 Input port RXD0 input I2SDO output 1 Output port (Reserved) 0 1 P93 Setting 0 Input port I2SCKO output 1 Output port TXD0 output Output port SCLK0 output 0 1 P94 Setting I2SWS output 1 0 1 0 Input port LGOE1 output 1 Output port (Reserved) 0 1 0 Input port LGOE0 output 1 Output port (Reserved) (Reserved) Port 9 Function Register 2 7 P9FC2 (0025H) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 P90F2 W 0 0:CMOS 1:Opendrain Port 9 Drive Register 7 P9DR (0089H) Bit symbol Read/Write After reset Function 1 1 1 1 P97D 6 P96D 5 P95D 4 P94D R/W 3 P93D 1 2 P92D 1 1 P91D 1 0 P90D 1 Output/Input buffer drive register for standby mode Note: Read-modify-write is prohibited for P9CR, P9FC and P9FC2. Figure 3.5.23 Register for Port 9 92CH21-87 2007-02-28 TMP92CH21 3.5.10 Port A (PA0 to PA7) Ports A0 to A7 are 8-bit input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also, as a keyboard interface, operate a key-on wakeup function. The various functions can each be enabled by writing a “1” to the corresponding bit of the port A function register (PAFC). Resetting resets all bits of the register PAFC to “0” and sets all pins to be input port. INTKEY Edge detection PA0 to PA7 8-input OR Reset Pull-up resistor Internal data bus PAFC PAFC write PA read Reset PACR LD8 to LD11 PA0 (KI0) PA1 (KI1) PA2 (KI2) PA3 (KI3, LD8) PA4 (KI4, LD9) PA5 (KI5, LD10) PA6 (KI6, LD11) PA7 (KI7) PACR write Only for PA3 to PA6 Figure 3.5.24 Port A When PAFC = “1”, if the input of any of KI0 to KI7 pins fall down, an INTKEY interrupt is generated. An INTKEY interrupt can be used to release all HALT modes. 92CH21-88 2007-02-28 TMP92CH21 Port A Register 7 PA (0028H) Bit symbol Read/Write After reset PA7 6 PA6 5 PA5 4 PA4 R/W 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port Port A Function Register 7 PAFC (002BH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Key input disable PA7F 6 PA6F 5 PA5F 4 PA4F W 3 PA3F 0 2 PA2F 0 1 PA1F 0 0 PA0F 0 1: Key input enable Port A Control Register 7 PACR (002AH) Bit symbol Read/Write After reset Function 0 0 6 PA6C 5 PA5C W 4 PA4C 0 3 PA3C 0 2 1 0 0: Input port or Key input 1: LD11 to LD8 output Port A Drive register 7 PADR (008AH) Bit symbol Read/Write After reset Function 1 1 1 1 PA7D 6 PA6D 5 PA5D 4 PA4D W 3 PA3D 1 2 PA2D 1 1 PA1D 1 0 PA0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for PACR and PAFC. Figure 3.5.25 Register for Port A 92CH21-89 2007-02-28 TMP92CH21 3.5.11 Port C (PC0 to PC3, PC6 to PC7) PC0 to PC3, PC6 and PC7 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port C to an input port. In addition to functioning as a general-purpose I/O port, port C can also function as an output pin for timers (TA1OUT, TA3OUT and TB0OUT0), input pin for external interruption (INT0 to INT3), output pin for memory ( CSZF ), output pin for key (KO8) and output pin for LCD driver (LDIV, LCP1). These settings are made using the function register PCFC. The edge select for external interruption is determined by the IIMC register in the interruption controller. (1) PC0 (INT0, TA1OUT) Reset Direction control PCCR write Internal data bus Function control PCFC write S Output latch S A Selector B PC0 (INT0, TA1OUT) PC write TA1OUT S B Selector A Level/edge select and Rising/falling select IIMC PC read INT0 Figure 3.5.26 Port C0 92CH21-90 2007-02-28 TMP92CH21 (2) PC1 (INT1, TA3OUT), PC2 (INT2, TB0OUT0), PC3 (INT3, TB0OUT1) Reset Direction control PCCR write Function control Internal data bus PCFC write S Output latch S A Selector B PC1 (INT1, TA3OUT) PC2 (INT2, TB0OUT0) PC3 (INT3) PC write TA3OUT TB0OUT0 S B Selector A PC read INT1 to INT3 Rising/falling edge detection IIMC Figure 3.5.27 Port C1, C2, C3 92CH21-91 2007-02-28 TMP92CH21 (3) PC6 (KO8, LDIV) Reset Direction control PCCR write Internal data bus Function control PCFC write S Output latch S A Selector B PC6 (KO8, LDIV) Open drain possible PC write LDIV S B Selector A PC read Figure 3.5.28 Port C6 (4) PC7 ( CSZF , LCP1) Reset Direction control PCCR write Internal data bus Funtcion control PFFC write S Output latch S A Selector B C S B Selector A PC7 ( CSZF , LCP1) PC write CSZF LCP1 PC read Figure 3.5.29 Port C7 92CH21-92 2007-02-28 TMP92CH21 Port C Register 7 PC (0030H) Bit symbol Read/Write After reset PC7 R/W Data from external port (Output latch register is set to “1”) 6 PC6 5 4 3 PC3 2 PC2 R/W 1 PC1 0 PC0 Data from external port (Output latch register is set to “1”) Port C Control Register 7 PCCR (0032H) Bit symbol Read/Write After reset Function 0 PC7C W 0 0 0 Refer to following table 6 PC6C 5 4 3 PC3C 2 PC2C W 1 PC1C 0 0 PC0C 0 Refer to following table Port C Function Register 7 PCFC (0033H) Bit symbol Read/Write After reset Function PC2 Setting 0 0 1 PC7 Setting 0 0 1 Input port Output port CSZF Output LCP1 Output 6 PC6F W 0 5 4 3 PC3F 0 2 PC2F W 0 1 PC1F 0 0 PC0F 0 PC7F 0 Refer to following table PC1 Setting 1 Output port TB0OUT 0 1 PC6 Setting 1 0 1 Input port Output port KO8 LDIV Output (Open drain) 0 1 0 Input port INT1 1 Refer to following table PC0 Setting 0 Output port TA3OUT 0 1 PC3 Setting 0 0 1 Input port INT3 Output port (Reserved) 1 Input port INT0 Output port TA1OUT 1 Input port INT2 Port C Drive Register 7 PCDR (008CH) Bit symbol Read/Write After reset Function 1 PC7D R/W 1 1 1 Input/Output buffer drive register for standby mode 6 PC6D 5 4 3 PC3D 2 PC2D R/W 1 PC1D 1 0 PC0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the registers PCCR and PCFC. Figure 3.5.30 Register for Port C 92CH21-93 2007-02-28 TMP92CH21 3.5.12 Port F (PF0 to PF2, PF7) Ports F0 to F2 are 3-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF2 to be input ports. It also sets all bits of the output latch register to “1”. In addition to functioning as general-purpose I/O port pins, PF0 to PF2 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing a “1” to the corresponding bit of the port F function register (PFFC). Port F7 is a 1-bit general-purpose output port. In addition to functioning as a general-purpose output port , PF7 can also function as the SDCLK output. Resetting sets PF7 to be an SDCLK output port. (1) Port F0 (TXD0, TXD1), F1 (RXD0, RXD1), F2 (SCLK0, CTS0 SCLK1, CTS1 ) Ports F0 to F2 are general-purpose I/O ports. They also function as either SIO0 or SIO1. Each pin is detailed below. SIO mode (SIO0 module) PF0 PF1 PF2 TXD0 (Data output) RXD0 (Data input) SCLK0 (Clock input or output) UART, IrDA mode (SIO0 module) TXD0 (Data output) RXD0 (Data input) CTS0 SIO mode (SIO1 module) TXD1 (Data output) RXD1 (Data input) SCLK1 (Clock input or output) UART mode (SIO1 module) TXD1 (Data output) RXD1 (Data input) CTS1 (Clear to send) (Clear to send) Reset Direction control PFCR write Internal data bus Function control PFFC write S Output latch Selector PF write TXD0 TXD1 Open drain set possible PFFC2 S PF0 (TXD0, TXD1) S B Selector A PF read Figure 3.5.31 Port F0 92CH21-94 2007-02-28 TMP92CH21 Reset Direction control Internal data bus PFCR write S Output latch PF1 (RXD0,RXD1) PF write S B Selector A PFFC S A Selector B PF read RXD0 P91RXD0 input RXD1 Figure 3.5.32 Port F1 Reset Direction control PFCR write Internal data bus S Output latch SCLK0 output SCLK1 output Selector S PF2 (SCLK0, CTS0 , SCLK1, CTS1 ) PF write Function control PFFC write S B Selector A S PF read A Selector B SCLK0 input, CTS0 input P92SCLK0 input SCLK1 input, CTS1 input Figure 3.5.33 Port F2 92CH21-95 2007-02-28 TMP92CH21 Reset Internal data bus Function control PFFC write S Output latch SDCLK PF write S A Selector B PF7 (SDCLK) PF read Figure 3.5.34 Port F7 92CH21-96 2007-02-28 TMP92CH21 Port F Register 7 PF (003CH) Bit symbol Read/Write After reset PF7 R/W 1 6 5 4 3 2 PF2 1 PF1 R/W 0 PF0 External data (Output latch register is set to “1”) Port F Control Register 7 PFCR (003EH) Bit symbol Read/Write After reset Function 0 6 5 4 3 2 PF2C 1 PF1C W 0 Refer to following table 0 PF0C 0 Port F Functon Register 7 PFFC (003FH) Bit symbol Read/Write After reset Function PF7F W 1 0: Output 1: SDCLK 0 Refer to following table 6 5 4 3 2 PF2F 1 PF1F W 0 RXD0 pin selection 0: Port F1 1: Port 91 0 PF0F 0 Refer to following table PF2 Setting 0 Input port or SCLK1, CTS1 input or PF1 Setting 1 0 Output port 1 Input port or RXD0/RXD1 input Output port 0 1 PF0 Setting 0 0 1 Input port Output port TXD1 output TXD0 output 1 0 SCLK0, CTS0 input From PF2 pin at = 0 From P92 pin at = 1 1 SCLK1 output SCLK0 output Port F Functon Register 2 7 PFFC2 (003DH) Bit symbol Read/Write After reset Function 6 5 4 3 2 1 0 PF0F2 W 0 Output buffer 0: CMOS 1: Open drain Port F Drive Register 7 PFDR (008FH) Bit symbol Read/Write After reset Function PF7D R/W 1 Input/Output buffer drive register for standby mode 1 6 5 4 3 2 PF2D 1 PF1D R/W 1 0 PF0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the registers PFCR, PFFC and PFFC2. Figure 3.5.35 Register for Port F 92CH21-97 2007-02-28 TMP92CH21 3.5.13 Port G (PG0 to PG3) PG0 to PG3 are 4-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD converter. PG2 and PG3 can also be used as the MX and MY pins for a touch screen interface. Internal data bus Port G read Conversion result register PG0 (AN0), PG1 (AN1), PG2 (AN2, MX), PG3 (AN3, MY, ADTRG ) AD converter Channel selector AD read ADTRG (only for PG3) (Only for PG2, PG3) TSICR0 Switch for TSI typ. 20Ω TSICR0 Figure 3.5.36 Port G Port G Register 7 PG (0040H) Bit symbol Read/Write After reset 6 5 4 3 PG2 2 PG2 R 1 PG1 0 PG0 Data from external port Note: The input channel selection of the AD converter and the permission for ADTRG input are set by AD converter mode register ADMOD1. Port G Drive Register 7 PGDR (0090H) Bit symbol Read/Write After reset Function 1 6 5 4 3 PG3D R/W 2 PG2D 1 1 0 Input/Output buffer drive register for standby mode Figure 3.5.37 Register for Port G 92CH21-98 2007-02-28 TMP92CH21 3.5.14 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output ports. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit I/O ports. In addition to functioning as a port, port J also functions as output pins for SDRAM ( SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM and SDCKE), SRAM ( SRWR , SRLLB SRLUB ) and NAND flash (NDALE and NDCLE). The above settings are made using the function register PJFC. However, H either SDRAM or SRAM output signals for PJ0 to PJ2 are selected automatically according to the setting of the memory controller. Reset PJFC2 write Function control Internal data bus S PJFC write Selector Output latch PJ0 ( SDRAS , SRLLB ) PJ1 ( SDCAS , SRLUB ) PJ2 ( SDWE , SRWR ) PJ3 (SDLLDQM) PJ4 (SDLUDQM) PJ7 (SDCKE) PJ write SRLLB , SRLUB , SRWR SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDCKE PJ read Figure 3.5.38 Port J0, J1, J2, J3, J4 and J7 Reset Direction control PJCRwrite Internal data bus Function control PJFC write S Output latch Selector PJ write SDULDQM, SDUUDQM NDALE, NDCLE S PJ5 (SDULDQM, NDALE), PJ6 (SDUUDQM, NDCLE) S B Selector A PJ read Figure 3.5.39 Port J5 and J6 92CH21-99 2007-02-28 TMP92CH21 Port J Register 7 PJ (004CH) Bit symbol Read/Write After reset 1 Data from external port (Output latch register is set to “1”) 1 PJ7 6 PJ6 5 PJ5 4 PJ4 R/W 3 PJ3 2 PJ2 1 PJ1 0 PJ0 1 1 1 1 Port J Control Register 7 PJCR (004EH) Bit symbol Read/Write After reset Function 0 6 PJ6C W 5 PJ5C 0 4 3 2 1 0 0: Input 1: Output Port J Function Register 7 PJFC (004FH) Bit symbol Read/Write After reset Function 0 0: Port 1: SDCKE 6 PJ6F 0 0: Port 1: NDCLE at = 0, SDUUDQM 5 PJ5F 0 0: Port 4 PJ4F W 0 0: Port 3 PJ3F 0 0: Port 2 PJ2F 0 0: Port 1 PJ1F 0 0: Port 1: SDCAS , SRLUB 0 PJ0F 0 0: Port 1: SRRAS , SRLLB PJ7F 1: NDALE at 1: SDLUDQM 1: SDLLDQM 1: SDWE , SDWR = 0, SDULDQM at = 1 at = 1 Port J Drive Register 7 PJDR (0093H) Bit symbol Read/Write After reset Function 1 1 1 1 PJ7D 6 PJ6D 5 PJ5D 4 PJ4D R/W 3 PJ3D 1 2 PJ2D 1 1 PJ1D 1 0 PJ0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the registers PJCR and PJFC. Figure 3.5.40 Register for Port J 92CH21-100 2007-02-28 TMP92CH21 3.5.15 Port K (PK0 to PK3) Port K is a 4-bit output port. Resetting sets the output latch PK to “0”, and PK0 to PK3 pins output “0”. In addition to functioning as an output port, port K also functions as output pins for an LCD controller (LCP0, LLP, LFR and LBCD). The above settings are made using the function register PKFC. Reset Function control Internal data bus PKFC write S Output latch A Selector PK write B LCP0, LLP, LFR, LBCD Output buffer PK0 (LCP0) PK1(LLP) PK2 (LFR) PK3 (LBCD) PK read Figure 3.5.41 Port K Port K Register 7 PK (0050H) Bit symbol Read/Write After reset 0 0 6 5 4 3 PK3 2 PK2 R/W 1 PK1 0 0 PK0 0 Port K Function Register 7 PKFC (0053H) Bit symbol Read/Write After reset Function 0 0: Port 1: LBCD 0 0: Port 1: LFR 6 5 4 3 PK3F 2 PK2F W 1 PK1F 0 0: Port 1: LLP 0 PK0F 0 0: Port 1: LCP0 Port K Drive Register 7 PKDR (0094H) Bit symbol Read/Write After reset Function Note: Read-modify-write is prohibited for the register PKFC. 1 1 6 5 4 3 PK3D 2 PK2D R/W 1 PK1D 1 0 PK0D 1 Input/Output buffer drive register for standby mode Figure 3.5.42 Register for Port K 92CH21-101 2007-02-28 TMP92CH21 3.5.16 Port L (PL0 to PL7) PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL3 pins output “0”. PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output using the control register PLCR. Resetting resets the control register PLCR to “0” and sets PL4 to PL7 to input ports. In addition to functioning as a general-purpose I/O port, port L can also function as a data bus for an LCD controller (LD0 to LD7). The above settings are made using the function register PLFC. Reset Function control Internal data bus PLFC write R Output latch S A PL write LD0 to LD3 Selector B PL0 to PL3 (LD0 to LD3) PL read Figure 3.5.43 Register for Port L0 to L3 Reset Direction control PLCR write Internal data bus Function control PLFC write S Output latch S A Selector B S B Selector A PL4 to PL7 (LD4 to LD7) PL write LD4 to LD7 PL read Figure 3.5.44 Register for Port L4 to L7 92CH21-102 2007-02-28 TMP92CH21 Port L Register 7 PL (0054H) Bit symbol Read/Write After reset Data from external port (Output latch register is cleared to “0”) PL7 6 PL6 5 PL5 4 PL4 R/W 3 PL3 2 PL2 1 PL1 0 PL0 0 0 0 0 Port L Control Register 7 PLCR (0056H) Bit symbol Read/Write After reset Function 0 0 PL7C 6 PL6C W 5 PL5C 0 4 PL4C 0 3 2 1 0 0: Input 1: Output Port L Function Register 7 PLFC (0057H) Bit symbol Read/Write After reset Function 0 0 0 0 PL7F 6 PL6F 5 PL5F 4 PL4F W 3 PL3F 0 2 PL2F 0 1 PL1F 0 0 PL0F 0 0: Port 1: Data bus for LCDC (LD7 to LD0) Port L Drive Register 7 PLDR (0095H) Bit symbol Read/Write After reset Function 1 1 1 1 PL7D 6 PL6D 5 PL5D 4 PL4D R/W 3 PL3D 1 2 PL2D 1 1 PL1D 1 0 PL0D 1 Input/Output buffer drive register for standby mode Note: Read-modify-write is prohibited for the registers PLCR and PLFC. Figure 3.5.45 Port L Register 92CH21-103 2007-02-28 TMP92CH21 3.5.17 Port M (PM1 to PM2) PM1 and PM2 are 2-bit output ports. Resetting sets the output latch PM to “1”, and PM1 and PM2 pins output “1”. In addition to functioning as a port, port M also functions as output pins for the RTC alarm ( ALARM ), and as the output pin for the melody/alarm generator (MLDALM, MLDALM ). The above settings are made using the function register PMFC. Only PM2 has two output functions - ALARM and MLDALM . These are selected using PM. Reset Function control Internal data bus PMFC write S Output latch S A Selector B PM write PM1 (MLDALM) PM read MLDALM Figure 3.5.46 Port M1 Reset Function control PMFC write Internal data bus S Output latch A S Selector PM2 ( ALARM , MLDALM ) PM write B PM read S MLDALM A Selector ALARM B Figure 3.5.47 Port M2 92CH21-104 2007-02-28 TMP92CH21 Port M Register 7 PM (0058H) Bit symbol Read/Write After reset 1 6 5 4 3 2 PM2 R/W 1 PM1 1 0 Port M Function Register 7 PMFC (005BH) Bit symbol Read/Write After reset Function 0 0: Port 1: ALARM at = “1” 1: MLDALM at = “0” 6 5 4 3 2 PM2F W 1 PM1F 0 0: Port 1: MLDALM output 0 Port M Drive Register 7 PMDR (0096H) Bit symbol Read/Write After reset Function Note: Read-modify-write is prohibited for the register PMFC. 1 6 5 4 3 2 PM2D R/W 1 PM1D 1 0 Input/Output buffer drive register for standby mode Figure 3.5.48 Register for Port M 92CH21-105 2007-02-28 TMP92CH21 3.6 Memory Controller Functions The TMP92CH21 has a memory controller with a variable 4-block address area that controls as follows. (1) 4-block address area support Specifies a start address and a block size for the 4-block address area (block 0 to 3). • • • • SRAM or ROM: All CS blocks (CS0 to CS3) are supported. SDRAM Page ROM NAND flash : Only either CS1 or CS2 blocks are supported. : Only CS2 blocks are supported. : CS0 is recommended for NAND flash (ND0/1FDTR, 001D00H to 001EFFH), RAM built-in LCD driver (001FE0H to 001FEFH). (Regarding NAND flash area, refer to 3.6.6 (2).) (2) Connecting memory specifications Specifies SRAM, ROM and SDRAM as memories that connect with the selected address areas. (3) Data bus width selection Whether 8 bits, 16 bits or 32 bits is selected as the data bus width of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in the 6 modes listed below. 0 waits, 1 wait, 2 waits, 3 waits, 4 waits N waits (controls with WAIT pin) 3.6.1 3.6.2 Control Register and Operation after Reset Release This section describes the registers that control the memory controller, the state following reset release and the necessary settings. (1) Control register The control registers of the memory controller are as follows and in Table 3.6.1 and Table 3.6.2. • Control register: BnCSH/BnCSL (n = 0 to 3, EX) Sets the basic functions of the memory controller; the memory type that is connected, the number of waits which are read and written. Memory start address register: MSARn (n = 0 to 3) Sets a start address in the selected address areas. Memory address mask register: MAMR (n = 0 to 3) Sets a block size in the selected address areas. Page ROM control register: PMEMCR Sets the method of accessing page ROM. Internal boot ROM controls register: BROMCR Sets the method of accessing boot ROM. • • • • 92CH21-106 2007-02-28 TMP92CH21 Table 3.6.1 Control Register 7 B0CSL (0140H) Bit symbol Read/Write After reset B0CSH (0141H) Bit symbol Read/Write After reset MAMR0 (0142H) Bit symbol Read/Write After reset MSAR0 (0143H) Bit symbol Read/Write After reset B1CSL (0144H) Bit symbol Read/Write After reset B1CSH (0145H) Bit symbol Read/Write After reset MAMR1 (0146H) Bit symbol Read/Write After reset MSAR1 (0147H) Bit symbol Read/Write After reset B2CSL (0148H) Bit symbol Read/Write After reset B2CSH (0149H) Bit symbol Read/Write After reset MAMR2 (014AH) Bit symbol Read/Write After reset MSAR2 (014BH) Bit symbol Read/Write After reset B3CSL (014CH) Bit symbol Read/Write After reset B3CSH (014DH) Bit symbol Read/Write After reset MAMR3 (014EH) Bit symbol Read/Write After reset MSAR3 (014FH) Bit symbol Read/Write After reset 1 1 1 1 1 M3S23 1 M3S22 1 M3S21 1 M3S20 R/W 1 1 1 1 0 M3V22 0 (Note) M3V21 0 (Note) M3V20 0 M3V19 R/W 1 M3S19 1 M3S18 1 M3S17 1 M3S16 B3E 0 − 1 1 B3WW2 1 B3WW1 W 1 − 0 B3REC W 0 M3V18 0 M3V17 0 M3V16 0 M3V15 B3OM1 0 B3OM0 1 B3WW0 1 M2S23 1 M2S22 1 M2S21 1 M2S20 R/W 1 1 B3WR2 1 B3WR1 W 1 B3BUS1 0 B3BUS0 1 B3WR0 1 M2V22 0 M2V21 0 (Note) M2V20 0 M2V19 R/W 1 M2S19 1 M2S18 1 M2S17 1 M2S16 B2E 0 B2M 1 1 B2WW2 1 B2WW1 W 1 − 0 B2REC W 0 M2V18 0 M2V17 0 M2V16 0 M2V15 B2OM1 0 B2OM0 1 B2WW0 1 M1S23 1 M1S22 1 M1S21 1 M1S20 R/W 1 1 B2WR2 1 B2WR1 W 1 B2BUS1 0 B2BUS0 1 B2WR0 0 M1V21 0 (Note) M1V20 0 (Note) M1V19 0 M1V18 R/W 1 M1S19 1 M1S18 1 M1S17 1 M1S16 B1E 0 − 1 1 B1WW2 1 B1WW1 W 1 − 0 B1REC W 0 M1V17 0 M1V16 0 M1V15 to M1V9 0 M1V8 B1OM1 0 B1OM0 1 B1WW0 1 M0S23 1 M0S22 1 M0S21 1 M0S20 R/W 1 1 B1WR2 1 B1WR1 W 1 B1BUS1 0 B1BUS0 1 B1WR0 0 M0V20 0 (Note) M0V19 0 (Note) M0V18 0 M0V17 R/W 1 M0S19 1 M0S18 1 M0S17 1 M0S16 B0E 0 − 6 B0WW2 5 B0WW1 W 1 − 4 B0WW0 0 B0REC W 3 2 B0WR2 0 1 B0WR1 W 1 B0BUS1 0 M0V14 to M0V9 0 B0WR0 0 B0BUS0 0 M0V8 B0OM1 0 M0V16 B0OM0 0 M0V15 Note 1: Always write “0”. Note 2:Read-modify-write is prohibited for BnCS0 and BnCSH (n = 0 to 3) registers. 92CH21-107 2007-02-28 TMP92CH21 Table 3.6.2 Control Register 7 BEXCSH (0159H) Bit symbol Read/Write After reset BEXCSL (0158H) Bit symbol Read/Write After reset PMEMCR Bit symbol (0166H) Read/Write After reset BROMCR Bit symbol (0167H) Read/Write After reset Note: Read-modify-write is prohibited for BEXCSH and BEXCSL registers. 0 BEXWW2 BEXWW1 W 1 0 OPGE 0 OPWR1 0 0 OPWR0 R/W 0 1 ROMLESS R/W 0/1 1/0 0 VACE BEXWW0 0 0 BEXWR2 6 5 4 3 BEXOM1 2 BEXOM0 W 1 BEXBUS1 0 BEXWR1 W 1 PR1 0 BEXBUS0 0 BEXWR0 0 PR0 (2) Operation after reset release The start data bus width is determined by the state of AM1/AM0 pins just after reset release. The external memory is then accessed as follows AM1 0 0 1 1 AM0 0 1 0 1 Start Mode Don’t use this setting Start with 16-bit data bus (Note) Start with 32-bit data bus (Note) Start with boot (32-bit internal MROM) Note: The memory to be used on starting after reset must be either NOR flash or masked ROM. NAND flash and SDRAM cannot be used. AM1/AM0 pins are valid only just after reset release. In other cases, the data bus width is set by the control register . On reset, only the control register (B2CSH/B2CSL) of the block address area 2 becomes effective automatically (B2CSH is set to “1” on reset). The data bus width which is specified by AM1/AM0 pins is loaded to the bit for specification of the bus width of the control register in the block address area 2. The block address area 2 is set to 000000H to FFFFFFH address on reset (B2CSH is reset to “0”). After reset release, the block address areas are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The control register (BnCS) is then set. Set the enable bit (BnE) of the control register to “1” to enable the setting. 92CH21-108 2007-02-28 TMP92CH21 3.6.3 Basic Functions and Register Setting This section describes the setting of the block address area, the connecting memory and the number of waits out of the memory controller’s functions. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas. The memory controller compares the register value and the address every bus cycle. The address bit which is masked by the memory address mask register (MAMRn) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The value that is set to the register is compared with the block address area on the bus. If the result is a match, the memory controller sets the chip select signal (CSn) to “low”. (i) Memory start address register setting The MS23 to MS 16 bits of the memory start address register correspond with addresses A23 to A16 respectively. The lower start addresses A15 to A0 are always set to address 0000H. Therefore the start addresses of the block address area are set to all 64 Kbytes of addresses 000000H to FF0000H. (ii) Memory address mask register setting The memory address mask register determines whether an address bit is compared or not. In register setting, “0” is “compare”, and “1” is “do not compare”. The address bits that can be set depends on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 3: A22 to A15 The upper bits are always compared. The block address area size is determined by the result of the comparison. The size to be set depending on the block address area is as follows. Size (bytes) CS area CS0 CS1 CS2 to CS3 256 ○ ○ 512 ○ ○ 32 K ○ ○ 64 K ○ ○ ○ 128 K 256 K 512 K ○ ○ ○ ○ ○ ○ ○ ○ ○ 1M ○ ○ ○ 2M ○ ○ ○ 4M ○ ○ 8M ○ Note: After reset release, only the control register of the block address area 2 is valid. The control register of block address area 2 has the bit. If the bit is set to “0”, block address area 2 is set to addresses 000000H to FFFFFFH. (This is the state following reset release .) If the bit is set to “1”, the start address and the address area size are set, as in the other block address areas. 92CH21-109 2007-02-28 TMP92CH21 (iii) Example of register setting To set the block address area 64 Kbytes from address 110000H, set the register as follows. MSAR1 Register Bit Bit symbol Specified value 7 M1S23 0 6 M1S22 0 5 M1S21 0 4 M1S20 1 3 M1S19 0 2 M1S18 0 1 M1S17 0 0 M1S16 1 M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with address A23 to A16. A15 to A0 are set to “0”. Therefore, if MSAR1 is set to the above mentioned value, the start address of the block address area is set to address 110000H. MAMR1 Register Bit Bit symbol Specified value 7 M1V21 0 6 M1V20 0 5 M1V19 0 4 M1V18 0 3 M1V17 0 2 M1V16 0 1 M1V15 to M1V9 0 M1V8 1 0 M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 are set whether addresses A21 to A16 and A8 are compared or not. In register setting, “0” is “compare”, and “1” is “do not compare”. M1V15 to M1V9 bits determine whether addresses A15 to A9 are compared or not with bit 1. A23 and A22 are always compared. When set as above, A23 to A9 are compared with the value that is set as the start addresses. Therefore, 512 bytes (addresses 110000H to 1101FFH) are set as block address area 1, and if it is compared with the addresses on the bus, the chip select signal CS1 is set to “low”. The other block address area sizes are specified in the same way. A23 and A22 are always compared with block address area 0. Whether A20 to A8 are compared or not is determined by the register. Similarly, A23 is always compared with block address areas 2 to 5. Whether A22 to A15 are compared or not is determined by the register. Note 1: When the set block address area overlaps with the built-in memory area, or both two address areas overlap, the block address area is processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3 Note 2: If an address area other than CS0 to CS3 is accessed, this area is regarded as CSEX . Therefore, wait number and data bus width controls follow the setting of CSEX (BEXCSH, BEXCSL register). 92CH21-110 2007-02-28 TMP92CH21 (2) Connection memory specification Setting the bit of the control register (BnCSH) specifies the memory type that is connected with the block address areas. The interface signal is outputted according to the set memory as follows. Bit (BnCSH Register) 0 0 1 1 0 1 0 1 (Reserved) (Reserved) SDRAM Function SRAM/ROM (Default) Note 1: SDRAM should be set to block either 1 or 2. Note 2: Set “00” for NAND flash, RAM built-in LCDD. (3) Data bus width specification The data bus width is set for every block address area. The bus size is set by setting the control register (BnCSH) as follows. bit (BnCSH Register) BnBUS 1 0 0 1 1 BnBUS 0 0 1 0 1 Function 8-bit bus mode (Default) 16-bit bus mode 32-bit bus mode Don’t use this setting Note: SDRAM should be set to either “01” (16-bit bus) or “10” (32-bit bus). This method of changing the data bus width depending on the accessing address is called “dynamic bus sizing”. The part of the data bus to which the data is output depends on the data size, baus width and start address. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive addresses, do not execute an access to both memories with one command. 92CH21-111 2007-02-28 TMP92CH21 Operand Data Size (bit) Operand Start Address 4n + 0 4n + 1 Memory Data Size (bit) 8/16/32 8 16/32 8/16 32 8 16 32 8 16/32 8 16 32 8 16 32 8 16 32 CPU Address 4n + 0 4n + 1 4n + 1 4n + 2 4n + 2 4n + 3 4n + 3 4n + 3 (1) 4n + 0 (2) 4n + 1 4n + 0 (1) 4n + 1 (2) 4n + 2 (1) 4n + 1 (2) 4n + 2 4n + 1 (1) 4n + 2 (2) 4n + 1 4n + 2 4n + 2 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 (1) 4n + 0 (2) 4n + 2 4n + 0 (1) 4n + 0 (2) 4n + 1 (3) 4n + 2 (4) 4n + 3 (1) 4n + 1 (2) 4n + 2 (3) 4n + 4 (1) 4n + 1 (2) 4n + 4 (1) 4n + 2 (2) 4n + 3 (3) 4n + 4 (4) 4n + 5 (1) 4n + 2 (2) 4n + 4 (1) 4n + 2 (2) 4n + 4 (1) 4n + 3 (2) 4n + 4 (3) 4n + 5 (4) 4n + 6 (1) 4n + 3 (2) 4n + 4 (3) 4n + 6 (1) 4n + 3 (2) 4n + 4 xxxxx CPU Data D31 to D24 D23 to D16 D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 b15 to b8 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx xxxxx b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b31 to b24 b23 to b16 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b23 to b16 b15 to b8 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b31 to b24 D7 to D0 b7 to b0 b7 to b0 xxxxx b7 to b0 xxxxx b7 to b0 xxxxx xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 xxxxx b7 to b0 b15 to b8 b7 to b0 xxxxx b7 to b0 b15 to b8 xxxxx b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 xxxxx b31 to b24 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 xxxxx b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 xxxxx b15 to b8 8 4n + 2 4n + 3 4n + 0 4n + 1 16 4n + 2 4n + 3 4n + 0 8 16 32 8 4n + 1 16 32 32 4n + 2 8 16 32 4n + 3 8 16 32 xxxxx: During a read, data input to the bus ignored. At write, the bus is at high impedance and the write strobe signal remains non active. 92CH21-112 2007-02-28 TMP92CH21 (4) Wait control The external bus cycle completes a wait of at least two states (100 ns at fSYS = 20 MHz). Setting the and of BnCSL specifies the number of waits in the read cycle and the write cycle. is set using the same method as . / (BnCSL Register) 0 0 1 1 1 0 0 1 0 1 1 1 Others 1 0 1 0 1 1 Function 2 states (0 waits) access fixed mode 3 states (1 wait) access fixed mode (Default) 4 states (2 waits) access fixed mode 5 states (3 waits) access fixed mode 6 states (4 waits) access fixed mode WAIT pin input mode (Reserved) Note 1: For SDRAM, the above setting is ineffective. Refer to 3.16 SDRAM controller. Note 2: For NAND flash, this setting is ineffective. For RAM built-in LCDD, this setting is effective. (i) Waits number fixed mode The bus cycle is completed following the number of states set. The number of states is selected from 2 states (0 waits) to 6 states (4 waits). (ii) WAIT pin input mode This mode samples the WAIT input pins. In this mode, a wait is inserted continuously while the signal is active. The bus cycle is a minimum 2 states. The bus cycle is completed if the wait signal is non active (“High” level) at the second state. The bus cycle continues if the wait signal is active after 2 states or more. 92CH21-113 2007-02-28 TMP92CH21 (5) Recovery (Data hold) cycle control Some memory is defined by AC specification about data hold time by CE or OE for read cycle. Therefore, a data conflict problem may occur. To avoid this problem, 1-dummy cycle can be inserted after CSm-block access cycle by setting “1” to BmCSH register. This 1-dummy cycle is inserted when the next cycle is for another CS-block. (BnCSH register) 0 1 No dummy cycle is inserted (Default). Dummy cycle is inserted. • When no dummy cycle is inserted (0 waits) SDCLK A23 to A0 CSm CSn RD • When inserting a dummy cycle (0 waits) Dummy SDCLK A23 to A0 CSm CSn RD 92CH21-114 2007-02-28 TMP92CH21 (6) Basic bus timing (a) External read/write cycle (0 waits) SDCLK (20 MHz) CSn T1 T2 A23 to A0 RD , SRxxB Read D31 to D0 SRWR , SRxxB WRxx Input Write Output D31 to D0 (b) External read/write cycle (1 wait) SDCLK (20 MHz) CSn T1 TW T2 A23 to A0 RD , SRxxB Read D31 to D0 SRWR , SRxxB WRxx Input Write Output D31 to D0 92CH21-115 2007-02-28 TMP92CH21 (c) External read/write cycle (0 waits at WAIT pin input mode) SDCLK (20 MHz) CSn T1 T2 A23 to A0 RD , SRxxB Read D31 to D0 SRWR , SRxxB WRxx Input Write Output D31 to D0 WAIT Sampling (d) External read/write cycle (n waits at WAIT pin input mode) SDCLK (20 MHz) CSn T1 TW T2 A23 to A0 RD , SRxxB Read D31 to D0 SRWR , SRxxB WRxx Input Write Output D31 to D0 WAIT Sampling Sampling 92CH21-116 2007-02-28 TMP92CH21 Example of wait input cycle (5 waits) FF0 D CK Q FF1 D CK Q FF2 D CK Q FF3 D CK Q FF4 D CK Q WAIT RES RES RES RES RES SDCLK CSn RD SRWR SDCLK (20 MHz) CSn RD 1 2 3 4 5 6 7 FF_RES FF0_D FF0_Q FF1_Q FF2_Q FF3_Q WAIT 92CH21-117 2007-02-28 TMP92CH21 (7) Connecting external memory Figure 3.6.1 shows an example of how to connect an external 16-bit SRAM and 16-bit NOR flash to the TMP92CH21. TMP92CH21 RD SRLLB SRLUB SRWR CS0 16-bit SRAM OE LDS UDS R/W CE D [15:0] A0 A1 A2 A3 Not connect I/O [16:1] A0 A1 A2 16-bit NOR flash OE WE CS2 CE DQ [15:0] A0 A1 A2 Figure 3.6.1 Example of External 16-Bit SRAM and NOR Flash Connection 92CH21-118 2007-02-28 TMP92CH21 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers The TMP92CH21 supports ROM access of the page mode. ROM access of the page mode is specified only in block address area 2. ROM page mode is set by the page ROM control register (PMEMCR). Setting of the PMEMCR register to “1” sets the memory access of the block address area to ROM page mode access. The number of read cycles is set by the of the PMEMCR register. (PMEMCR register) 0 0 1 1 0 1 0 1 Number of Cycle in a Page 1 state (n-1-1-1 mode) (n ≥ 2) 2 state (n-2-2-2 mode) (n ≥ 3) 3 state (n-3-3-3 mode) (n ≥ 4) (Reserved) Note: Set the number of waits (“n”) using the control register (BnCSL) in each block address area. The page size (the number of bytes) of ROM in the CPU size is set by the of the PMEMCR register. When data is read out up to the border of the set page, the controller completes the page reading operation. The start data of the next page is read in the normal cycle. The following data is set to page read again. Bit (PMEMCR register) 0 0 1 1 0 1 0 1 64 bytes 32 bytes ROM Page Size 16 bytes (Default) 8 bytes SDCLK tCYC A0 to A23 +0 +1 +2 +3 CS2 tAD3 RD tAD2 tAD2 tAD2 tHA tRD3 D0 to D31 Data input tHA Data input tHA Data input tHA Data input tHR Figure 3.6.2 Page mode access Timing (8-byte example) 92CH21-119 2007-02-28 TMP92CH21 3.6.5 Internal Boot ROM Control This section describes the built-in boot ROM. For the specification of S/W in boot ROM, refer to 3.20 boot ROM sections. (1) BOOT mode BOOT mode is started by following AM1 and AM0 pins condition with reset. AM1 0 0 1 1 AM0 0 1 0 1 Start mode Don’t use this setting Start with 16-bit data bus Start with 32-bit data bus Start with boot (32-bit internal MROM) (2) Boot ROM memory map Boot ROM consists of an 8-Kbyte masked ROM and is assigned to address 3FE000H to 3FFFFFH. 000000H Internal I/O, RAM 006000H 3FE000H Internal boot ROM (8 Kbytes) 3FFF00H 400000H (B) Reset/interrupt vector area (256 bytes) FFFF00H (A) Reset/interrupt vector area (256 bytes) (3) Reset/interrupt address conversion circuit The Reset/interrupt vector area is assigned to FFFF00H to FFFFEFH ((A) area) in the TLCS-900/H1. Since the boot ROM is assigned to another area, a reset/interrupt vector address conversion circuit is provided. In BOOT mode, the reset/interrupt vector area is assigned to 3FFF00H to 3FFFEFH ((B) area). Following boot sequence, the area can be changed to (A) area by setting BROMCR to “0”. Therefore, (A) area can be used only for the application system program. This is initialized to “1” in BOOT mode. In any other starting mode, this register has no effect. Note: As the last 16-byte area (FFFFF0H to FFFFFFH) is reserved for an emulator, this area is not changed by the register. 92CH21-120 2007-02-28 TMP92CH21 (4) Clearing boot ROM After boot sequence in BOOT mode, an application system program may continue to run without reset asserting. In this case, an external memory which is mapped to address 3FE000H to 3FFFFFH cannot be accessed because the boot ROM is assigned. To solve this, the internal BROMCR to “1”. boot ROM can be cleared by setting This is initialized to “0” in BOOT mode. In any other starting mode, this register is initialized to “1”. If this register has been set to “1”, writing “0” is disabled. 7 BROMCR Bit symbol (0167H) Read/Write After reset Function 6 5 4 3 2 1 ROMLESS R/W 0/1 Boot ROM 0: Use 1: No use 0 VACE 1/0 Vector address conversion 0: Disable 1: Enable 92CH21-121 2007-02-28 TMP92CH21 3.6.6 Cautions (1) Note on timing between CS and RD If the parasitic capacitance of the RD (Read signal) is greater than that of the CS (Chip select signal), it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a problem, as in the case of (a) in Figure 3.6.3. SDCLK (20 MHz) A23 to A0 CSm CSn RD (a) Figure 3.6.3 Read Signal Delay Read Cycle Example: When using an externally connected NOR flash which uses JEDEC standard commands, note that the toggle bit may not be read out correctly. If the read signal in the cycle immediately preceding the access to the NOR flash does not go high in time, as shown in Figure 3.6.4, an unintended read cycle like the one shown in (b) may occur. Memory access SDCLK (20 MHz) A23 to A0 NOR flash chip select RD Toggle bit RD cycle Toggle bit (b) Figure 3.6.4 NOR Flash Toggle Bit Read Cycle When the toggle bit is reversed by this unexpected read cycle, the CPU cannot read the toggle bit correctly since it always reads same value for the toggle bit. To avoid this phenomenon, data polling function control is recommended. 92CH21-122 2007-02-28 TMP92CH21 (2) Note on NAND flash area setting Figure 3.6.5 shows a memory map for a NAND flash and RAM built-in LCD driver. Ssince it is recommended that CS3 area be assigned to the address 000000H to 3FFFFFH, the following explanation is given. In this case, the NAND flash and RAM built-in LCD driver overlap with CS3 area. However, each access control circuit in the TMP92CH21 operates independently. So, if a program on CS3 area accesses NAND flash, both CS3 and NAND flash will be accessed at the same time and a problem such as data conflict will occur. To avoid this phenomenon, it is recommended that CS0 area be assigned to the 32 Kbytes of address 000000H to 007FFFH as the CS0 pin will not be needed. Since CS0 has priority over CS3, only NAND flash will be accessed correctly by this setting. Note: In this case, the 32 Kbytes of address 000000H to 007FFFH in CS3’s memory cannot be used. 000000H Internal I/O 001D00H NAND flash (512 bytes) (Not assigned) RAM built-in LCDD (16 bytes) 001F00H 001FE0H 001FF0H 002000H CS0 area setting 000000H to 007FFFH (32 Kbytes) Internal RAM (16 Kbytes) 006000H 008000H COMMON X (2 Mbytes) 200000H CS3 area setting 000000H to 3FFFFFH (4 Mbytes) LOCAL X (2 Mbytes) 400000H Figure 3.6.5 Recommended CS3 and CS0 Setting 92CH21-123 2007-02-28 TMP92CH21 (3) The cautions at the time of the functional change of a CSn . A chip select signal output has the case of a combination terminal with a general-purpose port function. In this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output (“1” or “0”) by it. Functional change Although an object terminal is changed from a port to a chip select signal output by setting up a function control register (PnFC register), the short pulse for several ns may be outputted to the changing timing. Although it does not become especially a problem when using the usual memory, it may become a problem when using a special memory. * XX is a function register address.(When an output port is initialized by “0”) A port is set as CSn . Internal Signal Internal address bus Function control signal Output port External Signal Pxx A23 to A0 n n+2 Output pulse tAD3 CSn n XX n+2 The measure by software The countermeasures in S/W for avoiding this phenomenon are explained. Since CS signal decodes the address of the access area and is generated, an unnecessary pulse is outputted by access to the object CS area immediately after setting it as a CSn function. Then, if internal area is accessed also immediately after setting a port as CS function, an unnecessary pulse will not output. 1. The ban on interruption under functional change (DI command) 2. 3. A dummy command is added in order to carry out continuous internal access. (Access to a functional change register is corresponded by 16-bit command. (LDW command)) A port is set as CSn . Internal Internal address bus Function control signal Output port signal Pxx A23 to A0 n n+2 CSn Dummy access n+2 External signal XX XX+1 92CH21-124 2007-02-28 TMP92CH21 3.7 8-Bit Timers (TMRA) The TMP92CH21 features 4 built-in 8-bit timers (TMRA0-TMRA3). These timers are paired into two modules: TMRA01 and TMRA23. Each module consists of two channels and can operate in any of the following four operating modes. • • • • 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 and Figure 3.7.2 show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by a five-byte SFR (special function register). Each of the two modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 Block Diagrams 3.7.2 Operation of Each Circuit 3.7.3 SFR 3.7.4 Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (programmable pulse generation) output mode (4) 8-bit PWM (pulse width modulation) output mode (5) Mode settings Table 3.7.1 Registers and Pins for Each Module Module Input pin for external clock Output pin for timer flip-flop Timer run register SFR (Address) Timer register Timer mode register Timer flip-flop control register TMRA01 No TA1OUT (Shared with PC0) TA01RUN (1100H) TA0REG (1102H) TA1REG (1103H) TA01MOD (1104H) TA1FFCR (1105H) TMRA23 No TA3OUT (Shared with PC1) TA23RUN (1108H) TA2REG (110AH) TA3REG (110BH) TA23MOD (110CH) TA3FFCR (110DH) External pin 92CH21-125 2007-02-28 3.7.1 Prescaler 16 32 64 128 256 512 φT16 Timer flip-flop TA1FF TA01RUN Selector TA1FFCR 8-bit up counter (UC1) 8-bit up counter (UC0) 2 Over flow TA01MOD TA01MOD n Prescaler clock: φT0 TA01RUN φT256 2 4 8 Run/clear φT1 φT4 Block Diagrams Timer flip-flop output: TA1OUT TA01RUN Selector φT1 φT16 φT256 φT1 φT4 φT16 Figure 3.7.1 TMRA01 Block Diagram 92CH21-126 8-bit up counter (CP0) TA01MOD 8-bit timer register TA0REG 8-bit timer register TA1REG Match detect TA0TRG TA01MOD 8-bit comparator (CP1) Match detect TA01RUN Register buffer 0 TMP92CH21 2007-02-28 Internaldata bus TMRA0 Interrupt output: INTTA0 TMRA0 Internal data bus Interrupt output: TA0TRG TMRA1 Interrupt output: INTTA1 Prescaler 8 φT4 Timer flip-flop TA3FF TA23RUN Selector TA3FFCR 8-bit up counter (UC2) 2 Over flow TA23MOD TA23MOD n Prescaler clock: φT0 16 32 64 128 256 512 φT16 φT256 TA23RUN 2 4 Run/clear φT1 Timer flip-flop output: TA3OUT TA23RUN Selector φT1 φT16 φT256 8-bit up comparator (UC3) φT1 φT4 φT16 Figure 3.7.2 TMRA23 Block Diagram 92CH21-127 8-bit comparator (CP2) TA23MOD 8-bit timer register TA2REG Match detect TA2TRG TA23MOD 8-bit comparator (CP3) Match detect 8-bit timer register TA3REG TA23RUN Register buffer 2 TMP92CH21 2007-02-28 Internal data bus TMRA2 Interrupt output: INTTA2 TMRA2 Internal data bus Interrupt output: TA2TRG TMRA3 Interrupt output: INTTA3 TMP92CH21 3.7.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The clock φT0 is divided into 8 by the CPU clock fSYS and input to this prescaler. The prescaler operation can be controlled using TA01RUN in the timer control register. Setting to “1” starts the count; setting to “0” clears the prescaler to “0” and stops operation. Table 3.7.2 shows the various prescaler output clock resolutions. Table 3.7.2 Prescaler Output Clock Resolution System clock selection SYSCR1 1(fs) Clock gear selection SYSCR1 − 000 (1/1) 001 (1/2) 0(fc) 010 (1/4) 011 (1/8) 100 (1/16) 1/8 Timer counter input clock TMRA prescaler − φT1(1/2) fs/16 fc/16 fc/32 fc/64 fc/128 fc/256 TAxMOD φT4(1/8) fs/64 fc/64 fc/128 fc/256 fc/512 fc/1024 φT16(1/32) φT256(1/512) fs/256 fc/256 fc/512 fc/1024 fc/2048 fc/4096 fs/4096 fc/4096 fc/8192 fc/16384 fc/32768 fc/65536 xxx: Don’t care (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is specified by the value set in TA01MOD. The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the overflow output from UC0 is used as the input clock. In any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks φT1, φT16 or φT256, or the comparator output (the match detection signal) from TMRA0. For each interval timer the timer operation control register bits TA01RUN and TA01RUN can be used to stop and clear the up counters and to control their count. A reset clears both up counters, stopping the timers. 92CH21-128 2007-02-28 TMP92CH21 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes Active. If the value set in the timer register is 00H, the signal goes Active when the up counter overflows. TA0REG has a double buffer structure, making a pair with the register buffer. The setting of the bit TA01RUN determines whether TA0REG’s double buffer structure is enabled or disabled. It is disabled if = “0” and enabled if = “1”. When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2n overflow occurs in PWM mode, or at the start of the PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode. A reset initializes to “0”, disabling the double buffer. To use the double buffer, write data to the timer register, set to “1”, and write the following data to the register buffer. Figure 3.7.3 show the configuration of TA0REG. Timer registers 0 (TA0REG) B Shift trigger Register buffers 0 Write Internal data bus TA01RUN Selector S A Write to TA0REG Matching detection PPG cycle n 2 overflow of PWM Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When = 0, the same value is written to the register buffer and the timer register; when = 1, only the register buffer is written to. The address of each timer register is as follows. TA0REG: 001102H TA2REG: 00110AH TA1REG: 001103H TA3REG: 00110BH All these registers are write only and cannot be read. 92CH21-129 2007-02-28 TMP92CH21 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to “0” and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detect signals (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR in the timer flip-flops control register. A reset clears the value of TA1FF to “0”. Writing “01” or “10” to TA1FFCR sets TA1FF to “0” or “1”. Writing “00” to these bits inverts the value of TA1FF (this is known as software inversion). The TA1FF signal is output via the TA1OUT pin (which can also be used as PC0). When this pin is used as the timer output, the timer flip-flop should be set beforehand using the port C function register PCCR and PCFC. Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fSYS × 6) before the next overflow occurs by using an overflow interrupt. When using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) n Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 92CH21-130 2007-02-28 TMP92CH21 3.7.3 SFR TMRA01 Run Register 7 TA01RUN Bit symbol (1100H) Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 1 Disable Enable 0 IDLE2 0: Stop 1: Operate 0 TMRA01 prescaler 6 5 4 3 I2TA01 2 TA01PRUN R/W 1 TA1RUN 0 UP counter (UC1) 0 TA0RUN 0 UP counter (UC0) 0: Stop and clear 1: Run (Count up) Timer run/stop control 0 1 Stop and clear Run (Count up) Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN Bit symbol (1108H) Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable TA2REG double buffer control 0 1 Disable Enable 0 IDLE2 0: Stop 1: Operate 0 TMRA23 prescaler 6 5 4 3 I2TA23 2 TA23PRUN R/W 1 TA3RUN 0 UP counter (UC3) 0 TA2RUN 0 UP counter (UC4) 0: Stop and clear 1: Run (Count up) Timer run/stop control 0 1 Stop and clear Run (Count up) Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.7.4 TMRA01 Run Register and TMRA23 Run Register 92CH21-131 2007-02-28 TMP92CH21 TMRA01 Mode Register 7 TA01MOD (1104H) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 2 6 7 8 6 TA01M0 5 PWM01 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 01: φT1 10: φT16 11: φT256 2 TA1CLK0 0 1 TA0CLK1 0 00: Reserved 01: φT1 10: φT4 11: φT16 0 TA0CLK0 0 TA01M1 Source clock for TMRA1 Source clock for TMRA0 10: 2 11: 2 TMRA0 source clock selection 00 01 10 11 (Reserved) φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler) TMRA1 source clock selection TA01MOD ≠ 01 00 01 10 11 Comparator output from TMRA0 φT1 φT16 φT256 (16-bit timer mode) TA01MOD = 01 Overflow output from TMRA0 PWM cycle selection 00 01 10 11 Reserved 2 × Source clock 6 7 8 2 × Source clock 2 × Source clock TMRA01 operation mode selection 00 01 10 11 8-bit timers × 2ch 16-bit timer 8-bit PPG 8-bit PWM (TMRA0) 8-bit timer (TMRA1) Figure 3.7.5 TMRA Mode Register 92CH21-132 2007-02-28 TMP92CH21 TMRA23 Mode Register 7 TA23MOD (110CH) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 2 10: 2 11: 2 6 7 8 6 TA23M0 5 PWM21 4 PWM20 0 R/W 3 TA3CLK1 0 00: TA2TRG 01: φT1 10: φT16 11: φT256 2 TA3CLK0 0 1 TA2CLK1 0 00: Reserved 01: φT1 10: φT4 11: φT16 0 TA2CLK0 0 TA23M1 Source clock for TMRA3 Source clock for TMRA2 TMRA2 source clock selection 00 01 10 11 (Reserved) φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler) TMRA3 source clock selection TA23MOD ≠ 01 00 01 10 11 Comparator output from TMRA2 φT1 φT16 φT256 (16-bit timer mode) TA23MOD = 01 Overflow output from TMRA2 PWM cycle selection 00 01 10 11 Reserved 2 × Source clock 6 7 8 2 × Source clock 2 × Source clock TMRA23 operation mode selection 00 01 10 11 8-bit timers × 2ch 16-bit timer 8-bit PPG 8-bit PWM (TMRA2) 8-bit timer (TMRA3) Figure 3.7.6 TMRA23 Mode Register 92CH21-133 2007-02-28 TMP92CH21 TMRA1 Flip-Flop Control Register 7 TA1FFCR (1105H) Bit symbol Read/Write After reset Read-modify- Function write instruction is prohibited. 6 5 4 3 TA1FFC1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care 2 TA1FFC0 R/W 1 1 TA1FFIE 0 TA1FF control for inversion 0: Disable 1: Enable 0 TA1FFIS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flop-flop 1 (TA1FF) (Don’t care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 Inversion of TA1FF 0 1 Disabled Enabled Control of TA1FF 00 01 10 11 Inverts the value of TA1FF Sets TA1FF to “1” Clears TA1FF to “0” Don’t care Note: The values of bits4 to 6 of TA1FFCR are undefined when read. Figure 3.7.7 TMRA Flip-Flop Control Register 92CH21-134 2007-02-28 TMP92CH21 TMRA3 Flip-Flop Control Register 7 TA3FFCR Bit symbol (110DH) Read/Write After reset Readmodifywrite instruction is prohibited. 6 5 4 3 TA3FFC1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care 2 TA3FFC0 R/W 1 1 TA3FFIE 0 TA3FF control for inversion 0: Disable 1: Enable 0 TA3FFIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Function Inverse signal for timer flip-flop 3 (TA3FF) (Don’t care except in 8-bit timer mode) 0 1 Inversion by TMRA2 Inversion by TMRA3 Inversion of TA3FF 0 1 Disabled Enabled Control of TA3FF 00 01 10 11 Inverts the value of TA3FF Sets TA3FF to “1” Clears TA3FF to “0” Don’t care Note: The values of bits4 to 6 of TA3FFCR are undefined when read. Figure 3.7.8 TMRA3 Flip-Flop Control Register 92CH21-135 2007-02-28 TMP92CH21 TMRA Register Symbol TA0REG Address 1102H 7 6 5 4 − W Undefined − 3 2 1 0 TA1REG 1103H W Undefined − TA2REG 110AH W Undefined − TA3REG 110BH W Undefined Note: Read-modify-write instruction is prohibited. Figure 3.7.9 8-Bit Timers Register 92CH21-136 2007-02-28 TMP92CH21 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. 1. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 40 μs at fC = 40 MHz, set each register as follows: MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN ←− ←0 ←0 ←X ←– 6 X 0 1 1 X 5 X X 1 0 X 4 X X 0 1 X 3 − 0 0 − − 2 − 1 1 − 1 LSB 1 0 − 0 − 1 0 − − 0 − − Stop TMRA1 and clear it to “0”. Select 8-bit timer mode and select φT1 (=(16/fc)s at fC = 40 MHz) as the input clock. Set TREG1 to 40 μs ÷ φT1 = 100 = 64H. Enable INTTA1 and set it to level 5. Start TMRA1 counting. X: Don’t care, −: No change Select the input clock using Table 3.7.3. Table 3.7.3 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer Input Clock φT1 φT4 φT16 (8/fSYS) (32/fSYS) (128/fSYS) Interrupt Interval (at fSYS = 20 MHz) 0.4 μs to 102.4 μs 1.6 μs to 409.6 μs 6.4 μs to 1.638 ms 102.4 μs to 26.21 ms Resolution 0.4 μs 1.6 μs 6.4 μs 102.4 μs φT256 (2048/fSYS) Note: The input clocks for TMRA0 and TMRA1 differ as follows: TMRA0: Uses TMRA0 input (TA0IN) and can be selected from φT1, φT4 or φT16 TMRA1: Matches output of TMRA0 (TA0TRG) and can be selected from φT1, φT16, φT256 92CH21-137 2007-02-28 TMP92CH21 2. Generating a 50 % duty ratio square wave pulse The state of the timer flip-flop (TA1FF1) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4-μs square wave pulse from the TA1OUT pin at fC = 40 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. 7 TA01RUN TA01MOD TA1REG TA1FFCR PCCR PCFC TA01RUN ←− ←0 ←0 ←X ←− ←− ←− 6 X 0 0 X − − X 5 X X 0 X − − X 4 X X 0 X − − X 3 − 0 0 1 − − − 2 − 1 0 0 − − 1 1 0 − 1 1 − − 1 0 − − 1 1 1 1 − Stop TMRA1 and clear it to “0”. Select 8-bit timer mode and select φT1 (=(16/fc)s at fC = 40 MHz) as the input clock. Set the timer register to 2.4 μs ÷ φT1 ÷ 2 = 3 Clear TA1FF to “0” and set it to invert on the match detect signal from TMRA1. Set PC0 to function as the TA1OUT pin. Start TMRA1 counting. X: Don’t care, −: No change φT1 TA01RUN Bit7 to Bit2 Up counter Bit1 Bit0 Comparator timing Comparator output (Match detect) INTTA1 UC1 clear TA1FF TA1OUT 1.2 μs at fC = 40 MHz 0 1 2 3 0 1 2 3 0 1 2 3 0 Figure 3.7.10 Square Wave Output Timing Chart (50 % Duty) 92CH21-138 2007-02-28 TMP92CH21 3. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 TMRA1 Count Up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD to “01”. In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of the value set in TA01MOD. Table 3.7.2 shows the relationship between the timer (interrupt) cycle and the input clock selection. To set the timer interrupt interval, set the lower eight bits in timer register TA0REG and the upper eight bits in TA1REG. Be sure to set TA0REG first (as entering data in TA0REG temporarily disables the compare, while entering data in TA1REG starts the compare). Setting example: To generate an INTTA1 interrupt every 0.4 s at fC = 40 MHz, set the timer registers TA0REG and TA1REG as follows: If φT16 (=(256/fc)s at fC = 40 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s ÷ =(256/fc)s = 62500 = F424H; e.g. set TA1REG to F4H and TA0REG to 24H. 92CH21-139 2007-02-28 TMP92CH21 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparator TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to “0” and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTA0 Interrupt INTTA1 Timer output TA1OUT 0080H 0180H 0280H 0380H 0480H 0080H Inversion Figure 3.7.12 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin (which can also be used as PC0). tH = “10” t tL = “01” t Example: = “01” TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interrupt INTTA1) TA1OUT tL tH TA0REG TA1REG Figure 3.7.13 8-Bit PPG Output Waveforms 92CH21-140 2007-02-28 TMP92CH21 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN should be set to “1” so that UC1 is set for counting. Figure 3.7.14 shows a block diagram representing this mode. TA01RUN Selector φT1 φT4 φT16 TA01MOD 8-bit up counter (UC0) TA1FF TA1FFCR TA1OUT Inversion INTTA0 Comparator Comparator INTTA1 Selector TA0REG Shift trigger TA0REG-WR TA01RUN Register buffer TA1REG Internal data bus Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low duty waves (when duty is varied). Match with TA0REG and up counter Match with TA1REG TA0REG (Value to be compared) Register buffer Shift from register buffer Q1 Q2 Q2 Q3 TA0REG (Register buffer) write (Up counter = Q1) (Up counter = Q2) Figure 3.7.15 Operation of Register Buffer 92CH21-141 2007-02-28 TMP92CH21 Example: To generate 1/4 duty 62.5 kHz pulses (at fC = 40 MHz) 16 μs Calculate the value which should be set in the timer register. To obtain a frequency of 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 μs φT1 (=(16/fc)s (at fC = 40 MHz); 16 μs ÷ (16/fc)s = 40 Therefore set TA1REG to 40 (28H) The duty is to be set to 1/4: t × 1/4 = 16 μs × 1/4 = 4 μs 4 μs ÷ (16/fc)s = 10 Therefore, set TA0REG = 10 = 0AH. 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR PCCR PCFC TA01RUN ←0 ←1 ←0 ←0 ←X ←− ←− ←1 6 X 0 0 0 X − − X 5 X X 0 1 X − − X 4 X X 0 0 X − − X 3 − X 1 1 0 − − − 2 0 X 0 0 1 − − 1 1 0 0 1 0 1 − − 1 0 0 1 0 0 X 1 1 1 Stop TMRA0 and TMRA1 and clear it to “0”. Set the 8-bit PPG mode, and select φT1 as input clock. Write 0AH. Write 28H. Set TA1FF, enabling both inversion and the double buffer. 10 generates a negative logic pulse. Set PC0 as the TA1OUT pin. Start TMRA0 and TMRA1 counting. X: Don't care, −: No change 92CH21-142 2007-02-28 TMP92CH21 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as PC1). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD). The up counter UC0 is cleared when 2n counter overflow occurs. The following conditions must be satisfied before this PWM mode can be used. Value set in TA0REG < value set for 2n counter overflow Value set in TA0REG ≠ 0 TA0REG and UC0 match 2 overflow (INTTA0 interrupt) n TA1OUT tPWM (PWM cycle) Figure 3.7.16 8-Bit PWM Waveforms Figure 3.7.17 shows a block diagram representing this mode. TA01RUN φT1 φT4 φT16 8-bit up counter (UC0) TA1OUT TA1FFCR Selector Clear TA1FF Inversion TA01MOD 2 overflow control n TA01MOD Comparator Overflow INTTA0 TA0REG Selector TA0REG-WR TA01RUN Register buffer Shift trigger Internal data bus Figure 3.7.17 Block Diagram of 8-Bit PWM Mode 92CH21-143 2007-02-28 TMP92CH21 In this mode the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 overflow Shift into TA0REG TA0REG (Value to be compared) Register buffer Q1 Q2 Q2 Q3 TA0REG (Register buffer) write n Up counter = Q2 Figure 3.7.18 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin (at fC = 40 MHz). 36.0 μs 51.2 μs To achieve a 51.2-μs PWM cycle by setting φT1 (= (16/fc)s (@fC = 40 MHz): 51.2 μs ÷ (16/fc)s = 128 n 2 = 128 Therefore n should be set to 7. Since the low level period is 36.0 μs when φT1 = (16/fc)s, set the following value for TREG0: 36.0 μs ÷ (16/fc)s = 90 = 5AH MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR PCCR PCFC TA01RUN ←− ←1 ←0 ←X ←− ←− ←1 6 X 1 1 X − − X 5 X 1 0 X − − X 4 X 0 1 X − − X 3 − − 1 1 − − − 2 − − 0 0 − − 1 LSB 1 − 0 1 1 − − − 0 0 1 0 X 1 1 1 Stop TMRA0 and clear it to 0 Select 8-bit PWM mode (cycle: 2 ) and select φT1 as the input clock. 7 Write 5AH. Clear TA1FF to 0, enable the inversion and double buffer. Set PC0 as the TA1OUT pin. Start TMRA0 counting. X: Don't care, −: No change 92CH21-144 2007-02-28 TMP92CH21 Table 3.7.4 PWM Cycle PWM cycle System clock SYSCR0 Clock gear SYSCR1 TAxxMOD − φT1(x2) 2 (x64) TAxxMOD φT4(x8) 4096/fs 4096/fc 8192/fc 16384/fc 32768/fc 65536/fc 6 2 (x128) TAxxMOD φT1(x2) 2048/fs 2048/fc 4096/fc 8192/fc 16384/fc 32768/fc 7 2 (x256) TAxxMOD φT1(x2) 4096/fs 4096/fc 8192/fc 16384/fc 32768/fc 65536/fc 8 φT16(x32) 16384/fs 16384/fc 32768/fc 65536/fc 131072/fc 262144/fc φT4(x8) 8192/fs 8192/fc 16384/fc 32768/fc 65536/fc 131072/fc φT16(x32) 32768/fs 32768/fc 65536/fc 131072/fc 262144/fc 524288/fc φT4(x8) 16384/fs 16384/fc 32768/fc 65536/fc 131072/fc 262144/fc φT16(x32) 65536/fs 65536/fc 131072/fc 262144/fc 524288/fc 1048576/fc 1(fs) − 000(x1) 001(x2) 1024/fs 1024/fc 0(fc) 010(x4) 011(x8) 100(x16) ×8 2048/fc 4096/fc 8192/fc 16384/fc (5) Settings for each mode Table 3.7.5 shows the SFR settings for each mode. Table 3.7.5 Timer Mode Setting Registers Register name Function Timer Mode TA01MOD PWM Cycle Upper Timer Input Clock Lower timer match, φT1, φT16, φT256 (00, 01, 10, 11) − Lower Timer Input Clock External clock, φT1, φT4, φT16 (00, 01, 10, 11) External clock, φT1, φT4, φT16 (00, 01, 10, 11) External clock, φT1, φT4, φT16 (00, 01, 10, 11) External clock, φT1, φT4, φT16 (00, 01, 10, 11) − TA1FFCR Timer F/F Invert Signal Select 0: Lower timer output 1: Upper timer output 8-bit timer × 2 channels 00 − 16-bit timer mode 01 − − 8-bit PPG × 1 channel 10 − − − 8-bit PWM × 1 channel 8-bit timer × 1 channel 11 2 ,2 ,2 (01, 10, 11) − 6 7 8 − φT1, φT16, φT256 (01, 10, 11) − 11 Output disabled −: Don’t care 92CH21-145 2007-02-28 TMP92CH21 3.8 External Memory Extension Function (MMU) By providing 3 local areas, the MMU function allows for the expansion of the program/data area up to 512 Mbytes. The recommended address memory map is shown in Figure 3.8.1 and Figure 3.8.2. However, when the memory used is less than 16 Mbytes, it is not necessary to set the MMU register. In this case, please refer to the Memory Controller section. An area which can be set as a bank is called a local area. Since the address for local areas is fixed, it cannot be changed. It is not possible for a program to branch between different banks of the same local area. The TMP92CH21 has the following external pins for memory LSI connection. Address bus: EA25, EA24 and A23 to A0 Chip select: CS0 to CS3 , CSZA to CSZF , SDCS ND0CE and ND1CE Data bus: D31 to D0 3.8.1 Recommended Memory Map Figure 3.8.1 shows one recommended address memory map. This is for maximum expanded memory size and for a system in which an internal boot ROM with NAND flash is not needed. Figure 3.8.3 also shows a recommended address memory map for a simple memory system such as an internal boot ROM with NAND flash and SDRAM. 92CH21-146 2007-02-28 TMP92CH21 Memory controller setting Address Memory Map 000000H Internal I/O, RAM COMMON-X (2 Mbytes) 200000H LOCAL-X (2 Mbytes) 400000H LOCAL-Y (2 Mbytes) 600000H COMMON-Y (2 Mbytes) 800000H SDCS or CS1 pin 64 Mbytes(2 Mbytes × 32) ND0CE pin (128 Mbytes) ND1CE pin (128 Mbytes) CS3 pin 64 Mbytes(2 Mbytes × 32) CS0 area 32 Kbytes CS3 area 4 Mbytes Bank 0 1 2 3 15 31 Bank 0 1 2 3 15 31 CS1 area 4 Mbytes LOCAL-Z (4 Mbytes) Bank 0 1 2 3 15 16 31 80 95 C00000H CSZA pin (Note) 64 Mbytes(4 Mbytes × 16) CSZB pin CSZF pin CS2 area 8 Mbytes COMMON-Z (4 Mbytes) FFFF00H FFFFFFH Vector area : Internal area : Overlapped with COMMON area and disabled setting as LOCAL area. Note: CSZA is a chip select for not only bank 0 to 15 of LOCAL-Z but also COMMON-Z. Figure 3.8.1 Recommended Memory Map for Maximum Specification (Logical address) 92CH21-147 2007-02-28 TMP92CH21 TMP92CH21 LOCAL-X CS3 LOCAL-Y SDCS or CS1 LOCAL-Z CSZA to CSZF , EA24, EA25 128 Mbytes 64 Mbytes 64 Mbytes × 6 = 384 Mbytes CSZA CSZD 000000H BANK 0 BANK 0 BANK 0 BANK 48 Internal I/O and RAM 31 31 15 63 CSZB CSZE BANK 16 BANK 64 31 79 CSZC CSZF BANK 32 BANK 80 47 95 Figure 3.8.2 Recommended Memory Map for Maximum Specification (Physical address) 92CH21-148 2007-02-28 TMP92CH21 Memory controller setting Address Memory Map 000000H Internal I/O, RAM COMMON-X (2 Mbytes) 200000H LOCAL-X (2 Mbytes) 3FE000H 400000H LOCAL-Y (2 Mbytes) 600000H COMMON-Y (2 Mbytes) 800000H Internal boot ROM (8 Kbytes) ND0CE pin (128 Mbytes) ND1CE pin (128 Mbytes) CS0 area 32 Kbytes LOCAL-Z (4 Mbytes) Bank 0 1 2 3 15 C00000H SDCS pin 64 Mbytes (4 Mbytes × 16) CS2 area 8 Mbytes COMMON-Z (4 Mbytes) FFFF00H FFFFFFH Vector area : Internal area : Overlapped with COMMON area Figure 3.8.3 Recommended Memory Map for Simple System (Logical address) TMP92CH21 LOCAL-Z 4 Mbytes × 16 = 64 Mbytes SDCS SDCS 000000H BANK 0 Internal I/O and RAM 3FE000H Internal boot ROM BANK 15 Figure 3.8.4 Recommended Memory Map for Simple System (Physical address) 92CH21-149 2007-02-28 TMP92CH21 3.8.2 Control Registers There are 12 MMU registers, covering 4 functions (program, data read, data write and LCDC display data), in each of 3 local areas (Local-X, Y and Z), providing easy data access. (Instructions for use) First, set the enable register and bank number for each LOCAL register. The relevant pin and memory settings should then be set to the ports and memory controller. When the CPU or LCDC outputs a local area logical address, the MMU converts and outputs this to the physical address according to the bank number. The physical address bus is output to the external address bus pin, thereby enabling access to external memory. Note 1: Since the common area cannot be used as local area, do not set a bank number to LOCAL register which overlaps with the common area. Note 2: Changing program BANK number (LOCALPX, Y or Z) is disabled in the LOCAL area. The program bank setting for each local area must be changed in the common area. (But bank setting of read data, write data and data for LCD display can be changed in the local area.) Note 3: After data bank number register (LOCALRn, LOCALWn or LOCALLn; where “n” means X, Y or Z) is set by an instruction, do not access its memory by the following instruction because several clocks are required for effective MMU setting. For this reason, insert between them a dummy instruction which accesses SFR or another memory, as in the following example. (Example) ld ld ld ld xix, 200000H (localrx), 81H wa, (localrx) wa, (xix) ; ; ; ; Data bank number is set ← Inserted dummy instruction which accesses SFR Instruction which reads BANK 1 of LOCAL-X area. Note 4: When LOCAL-Z area is used, chip select signal CSZA should be assigned to P82 pin. In this case, CSZA works as chip select signal for not only BANK 0 to 15 but also COMMON-Z. The following setting after reset is required before setting Port82. ld ld ld ld ld ld (*1) (*2) (localpz), 80H (localrz), 80H (localwz), 80H (locallz), 80H (p8fc), ; ; ; ; LOCAL-Z bank enable for program LOCAL-Z bank enable for data read LOCAL-Z bank enable for data write Set P82 pin to CSZA output (*1) LOCAL-Z bank enable for LCD display memory (*2) −−−−−0−−B ; (p8fc2), − − − − − 1 − − B ; If COMMON-Z area is not used as data write memory, this setting is not required. If COMMON-Z area is not used as LCD display memory, this setting is not required. 92CH21-150 2007-02-28 TMP92CH21 (1) Program bank register The bank number used as program memory is set to these registers. It is not possible to change program bank number in the same local area. LOCAL-X Register for Program 7 LOCALPX Bit symbol (01D0H) Read/Write After reset Function LXE R/W 0 Use BANK for LOCAL-X 0: Not use 1: Use 0 0 6 5 4 X4 3 X3 2 X2 R/W 0 1 X1 0 0 X0 0 Set wBANK number for LOCAL-X (“0” is disabled because of overlap with COMMON area.) LOCAL-Y Register for Program 7 LOCALPY Bit symbol (01D1H) Read/Write After reset Function LYE R/W 0 Use BANK for LOCAL-Y 0: Not use 1: Use 0 0 6 5 4 Y4 3 Y3 2 Y2 R/W 0 1 Y1 0 0 Y0 0 Set BANK number for LOCAL-Y (“3” is disabled because of overlap with COMMON area.) LOCAL-Z Register for Program 7 LOCALPZ Bit symbol (01D3H) Read/Write After reset Function LZE R/W 0 Use BANK for LOCAL-Z 0: Disable 1: Enable 0 0 0 6 Z6 5 Z5 4 Z4 3 Z3 R/W 0 2 Z2 0 1 Z1 0 0 Z0 0 Set BANK number for LOCAL-Z (“3” is disabled because of overlap with COMMON area.) 92CH21-151 2007-02-28 TMP92CH21 (2) LCD Display bank register The bank number used as LCD display memory is set to these registers. Since the bank registers for CPU and LCDC are prepared independently, the bank number for CPU (Program, Read data or Write data) can be changed during LCD display. LOCAL-X Register for LCDC Display Data 7 LOCALLX Bit symbol (01D4H) Read/Write After reset Function LXE R/W 0 Use BANK for LOCAL-X 0: Not use 1: Use 0 0 6 5 4 X4 3 X3 2 X2 R/W 0 1 X1 0 0 X0 0 Set BANK number for LOCAL-X (“0” is disabled because of overlap with COMMON area.) LOCAL-Y Register for LCDC Display Data 7 LOCALLY (01D5H) Bit symbol Read/Write After reset Function LYE R/W 0 Use BANK for LOCAL-Y 0: Not use 1: Use 0 0 6 5 4 Y4 3 Y3 2 Y2 R/W 0 1 Y1 0 0 Y0 0 Set BANK number for LOCAL-Y (“3” is disabled because of overlap with COMMON area.) LOCAL-Z Register for LCDC Display Data 7 LOCALLZ (01D7H) Bit symbol Read/Write After reset Function LZE R/W 0 Use BANK for LOCAL-Z 0: Disable 1: Enable 0 0 0 6 Z6 5 Z5 4 Z4 3 Z3 R/W 0 2 Z2 0 1 Z1 0 0 Z0 0 Set BANK number for LOCAL-Z (“3” is disabled because of overlap with COMMON area.) 92CH21-152 2007-02-28 TMP92CH21 (3) Read data bank register The bank register number used as read data memory is set to these registers. The following is an example where the read data bank register of LOCAL-X is set to “1”. When “ld wa, (xix)” instruction is executed, the bank becomes effective only at the read cycle for xix address. (Example) ld ld ld SFR ld wa, (xix) ; Read bank1 of LOCAL-X area xix, 200000h (localrx), 81h wa, (localrx) ; ; Set Read data bank. ; B > C. If the A area is set to enable while the panel area is defined as all C area (A and B areas are disabled), C area is shifted below the LCD panel and A area is inserted from the top of the LCD panel. Similarly if the B area is set to enable while the panel area is defined as all C area, B area is inserted from the bottom of the C area overlapping. Memory map image Logic address 400000H Ya A area Vertical pan B area Yb Row address C area Yc Horizontal pan 2X 600000H B area Yb A area C area Yc Column address Reserved area for horizontal pan of C area * Display data cannot input closely when pan function is not used. LCD Panel image X Ya Figure 3.14.1 Memory Mapping from Physical Memory to LCD Panel 92CH21-339 2007-02-28 TMP92CH21 3.14.3.3 Display Memory Mapping and Panning Function (Common spec. SR mode and TFT mode) The LCDC can only change the panel window if you change each start address of A, B and C areas. The display area can be panned vertically and horizontally by changing the row address and column address. This LCDC can select many display modes: 1 bpp (monochrome), 2 bpp (4 grayscales), 3 bpp (8 grayscales), 4 bpp (16 grayscales), 8 bpp (256 colors) and 12 bpp (4096 colors) and 1-line (row). Data volume is different for each display mode. When using the panning function, care must be exercised in calculating the address for each display mode. For details, refer to Figure 3.14.2 to Figure 3.14.5, “Relation of memory map image and output data”. This LCDC can also support external SDRAM, SRAM and internal SRAM for display RAM. When using SDRAM for display RAM, data from one line to the next line cannot be input continuously in display RAM, even if the panning function is not used. One row address of display SDRAM corresponds to the first line of the display panel. Second line display data cannot now be set within the first row address of the display RAM even if the necessary data for the size you want to display does not fill the capacity of first row address of the display SDRAM. Adding one line to the display panel is equal to adding one address to the row address of the display SDRAM. In other words, when using SDRAM for display RAM, address calculation for panning is simple. When using SRAM for display RAM, data from one line to the next line must be input continuously to the display RAM. However, address calculation for panning is complex and horizontal panning function is not supported. 3.14.3.4 Data Transmission This LSI has an LD bus (LD7 to LD0): a special data bus for LCD driver. Bus width of 4-or 8-bits can be supported, and 2 formats selected for each bus width . The 2 formats of 8-bit bus width can support only STN color mode (256, 4096 colors). The 12-bit bus width supports only TFT mode. LD bus data invert function is also supported. By setting LCDMODE2 = 1, all LD bus data is inverted. There is bit in this LCDMODE2 register, but this automatic data invert function is only for TFT mode. 92CH21-340 2007-02-28 TMP92CH21 • Monochrome: 1 bpp (bit per pixel) Display memory image LSB D0 0 1 2 Address 0 3 4 5 6 7 8 Address 1 Address 2 Address 3 MSB D31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LD bus output sequence 4-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 0 1 2 3 → → → → 4 5 6 7 → → 8 9 → 12 ... → 13 ... 4-bit width B type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 4 5 6 7 → → → → 0 1 2 3 → 12 → → 13 → 8 9 ... ... 8-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 0 1 2 3 4 5 6 7 → → → → → → → → 8 9 ... ... → 10 → 14 ... → 11 → 15 ... → 14 → 10 ... → 15 → 11 ... 10 ... 11 ... 12 ... 13 ... 14 ... 15 ... Not use Not use Not use Not use Not used Not used Not used Not used Note: This mode is not supported by 8 bit width B type. • 4 grayscales (2 bpp) Display memory image LSB D0 0 1 2 Address 0 3 4 5 6 7 8 Address 1 Address 2 Address 3 MSB D31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 pixel LD bus output sequence 4-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 1-0 3-2 5-4 7-6 → 9-8 → 17-16 ... → 11-10 → 19-18 ... → 13-12 → 21-20 ... → 15-14 → 23-22 ... 4-bit width B type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 9-8 → 1-0 → 25-24 ... → 27-26 ... → 29-28 ... → 31-30 ... 11-10 → 3-2 13-12 → 5-4 15-14 → 7-6 Not used Not used Not used Not used 8-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 1-0 3-2 5-4 7-6 9-8 11-10 13-12 15-14 → 17-16 ... → 19-18 ... → 21-20 ... → 23-22 ... → 25-24 ... → 27-26 ... → 29-28 ... → 31-30 ... Not use Not use Not use Not use Note: This mode is not supported by 8 bit width B type. Figure 3.14.2 Relation of Memory Map Image and Output Data (1) 92CH21-341 2007-02-28 TMP92CH21 • 8/16 grayscales (4 bpp: 8 grayscales case, valid data is 3 bits but data space needs 4 bits) Display memory image LSB D0 0 1 2 Address 0 3 4 5 6 7 8 Address 1 Address 2 Address 3 MSB D31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 pixel LSB D0 Address 4 Address 5 Address 6 Address 7 MSB D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 LD bus output sequence 4-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 3-0 7-4 11-8 15-12 Not use Not use Not use Not use → 19-16 ... → 23-20 ... → 27-24 ... → 31-28 ... 8-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 3-0 7-4 11-8 15-12 19-16 23-20 27-24 31-28 → 35-32 ... → 39-36 ... → 43-40 ... → 47-44 ... → 51-48 ... → 55-52 ... → 59-56 ... → 63-60 ... * 8 grayscales data format is the same as 16 grayscales, 1 pixel needs 4-bit space. LSB bit is invalid data. This mode is not supported by 4-bit width B type and 8-bit width B type. Figure 3.14.3 Relation of Memory Map Image and Output Data (2) 92CH21-342 2007-02-28 TMP92CH21 • 256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits) Display memory image LSB D0 0 1 R1 LSB D0 2 Address 0 3 4 G1 Address 4 5 6 7 8 Address 1 Address 2 Address 3 MSB D31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R2 G2 Address 5 B2 R3 G3 Address 6 B3 R4 G4 Address 7 B4 MSB D31 B1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 LD bus output sequence 4-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 2-0 (R1) 5-3 (G1) 7-6 (B1) 10-8 (R2) Not used Not used Not used Not used → 13-11 (G2) ... → 15-14 (B2) ... → 18-16 (R3) ... → 21-19 (G3) ... LD bus output sequence 8-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 2-0 (R1) 5-3 (G1) 7-6 (B1) 10-8 (R2) 15-14 (B2) → 23-22 (B3) ... → 26-24 (R4) ... → 29-27 (G4) ... → 31-30 (B4) ... 8-bit width B type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 2-0 (R1) 5-3 (B1) 13-11 (G2) 18-16 (R3) 23-22 (B3) 29-27 (G4) 34-32 (R5) 39-38 (B5) → 7-6 (G1) → 10-8 (R2) → 15-14 (B2) → 21-19 (G3) → 26-24 (R4) → 31-30 (B4) → 37-35 (G5) → 42-40 (R6) → → → → → → → → 45-43 (G6) 50-48 (R7) 55-54 (B7) 61-59 (G8) 66-64 (R9) 71-70 (B9) → 47-46 (B6) → 53-51 (G7) → 58-56 (R8) → 63-62 (B8) → 69-67 (G9) ... ... ... ... ... 13-11 (G2) → 34-32 (R5) ... → 37-35 (G5) ... ... 18-16 (R3) → 39-38 (B5) → 74-72 (R10) ... 77-75 (G10) → 79-78 (B10) ... 82-80 (R11) → 85-83 (G11) ... 21-19 (G3) → 42-40 (R6) ... * This mode is not supported by 4-bit width B type. Figure 3.14.4 Relation of Memory Map Image and Output Data (3) 92CH21-343 2007-02-28 TMP92CH21 • 4096 colors (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits) Display memory image LSB D0 0 1 2 Address 0 3 4 5 6 7 8 Address 1 Address 2 Address 3 MSB D31 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B1 Address 5 R2 G2 Address 6 B2 R3 Address 7 G3 MSB D31 R1 LSB D0 Address 4 G1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 B3 LD bus output sequence 4-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 3-0 (R1) 7-4 (G1) 11-8 (B1) Not use Not use Not use Not use → 19-16 (G2) ... → 23-20 (B2) ... → 27-24 (R3) ... 8-bit width A type LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 3-0 (R1) 7-4 (G1) 11-8 (B1) → 35-32 (B3) ... → 39-36 (R4) ... → 43-40 (G4) ... ... R4 G4 B4 R5 G5 B5 R6 15-12 (R2) → 31-28 (G3) ... 15-12 (R2) → 47-44 (B4) 23-20 (B2) 27-24 (R3) 19-16 (G2) → 51-48 (R5) ... → 55-52 (G5) ... → 59-56 (B5) ... 31-28 (G3) → 63-60 (R6) ... * 8 grayscales data format is the same as 16 grayscales, 1 pixel needs 4-bit space. LSB bit is invalid data. This mode is not supported by 4-bit width B type and 8-bit width B type. Figure 3.14.5 Relation of Memory Map Image and Output Data (4) 92CH21-344 2007-02-28 TMP92CH21 3.14.3.5 Refresh Rate Setting Frame cycle (refresh rate) is generated from setting of LSCC (LCDSCC) and FP [9:0] (LCDCTL0, LCDFFP). The LBCD terminal outputs one pulse every cycle and the LFR normally outputs an inverted signal every cycle. But when the DIVIDE FRAME function is used, the LFR signal changes to a special signal for high quality display. (1) Basic clock setting This LSI has a special clock generator for basic source clock used in the LCD controller. This generator can set details of the refresh rate for the LCDC. This generator is made by dividing the system clock by 16 and an 8-bit counter. The following shows the method of setting and calculation. fBCD[Hz]: Frame rate (Refresh rate: Frequency of LBCD signal) FP: FP [9:0] setting value of FFP register SCC: setting value of LSCC register fBCD [Hz] = fSYS [Hz] / ((SCC+1) × 16 × FP) Example: fSYS [Hz] = 20MHz, 480COM (FP = 480), target refresh rate = 140Hz 140 [Hz] = 20000000 [Hz]/((SCC+1) × 16 × 480) (SCC+1) = 20000000/(140 ×16 × 480) = 18.60 Value of setting to register is only integer, SCC = 17. The floating value is disregarded. In this case, the refresh rate comes to 144.6 [Hz] LCDC Source Clock Counter Register 7 LCDSCC (0287H) Bit symbol Read/Write After reset Function 0 0 0 0 SCC7 6 SCC6 5 SCC5 4 SCC4 R/W 3 SCC3 0 2 SCC2 0 1 SCC1 0 0 SCC0 0 LCDC Source Clock Counter bit7 to bit0 * Data should be written from 1-hex to FFFF-hex in the above register. It cancannot operate if set to “0”. * If the refresh rate is set too fast, it may not be in time with the display data. tLP time is determined by SCC. tLP [s] = (1/fSYS [Hz]) × 16 × (SCC + 1) tLP is shown in 1-line (ROW) display time. 1-line data transmission must be completed during tLP cycle time. AboutRefer to “Data transmission and bus occupation” for details of data transmission time. 92CH21-345 2007-02-28 TMP92CH21 (2) Refresh rate adjust function (Correct function) In this function, the LBCD frequency: refresh rate is generated by setting LCDSCC and FP [9:0] register. The FFP value is normally set at the same value as the ROW number, but this value can be used for correction of BCD frequency: refresh rate. This function always uses a value greater than the ROW number, set to slower frequency. The LCDC cannot operate correctly if a value smaller than the ROW number is set. The following is an example of settings:. Example: fSYS [Hz] = 20 MHz, 480COM ( FP = 480 ), Target refresh rate = 140 Hz 140 [Hz] = 20000000 [Hz]/((SCC+1) × 16 × 480) (SCC+1) = 20000000/(140 × 16 × 480) = 18.60 Value of setting to register is only integer, SCC = 17. The floating value is disregarded. In this case, refresh rate comes to 144.6 [Hz] fBCD [Hz] = fSYS [Hz]/((SCC+1) × 16 × FP) FP value is adjusted to set SCC=17 in above equation again. 140 [Hz] = 20000000/(18 × 16 × FP) FP = 496.03 Value of setting to register is only integer, FP = 496. In this case, refresh rate comes to 140.0 [Hz] LCD fFP Register 7 LCDFFP (0282H) Bit symbol Read/Write After reset Function 0 0 0 0 FP7 6 FP6 5 FP5 4 FP4 R/W 3 FP3 0 2 FP2 0 1 FP1 0 0 FP0 0 Setting bit7 to bit0 for fFP Reference) We recommend refresh rate values in the region of:… Monochrome: 70 [Hz] 4, 8, 16 grayscales and color: 140 to 200 [Hz] 92CH21-346 2007-02-28 TMP92CH21 (3) Divide frame adjust function The DIVIDE FRAME function allows for adjustments to reduce uneven display in large LCD panels. When this function is enabled by setting = 1, the LFR signal alternates between high and low level with each LLP cycle for the LCDDVM register values given below. When this function is disabled by setting = 0, the LFR signal alternates between high and low level with each LBCD cycle. This function is not affected by the LBCD timing. Note: Availability of this function depends on the actual LCD driver or LCD panel used. We recommend checking that register’s value when used in the proposed environment. Divide Frame Register 7 LCDDVM (0283H) Bit symbol Read/Write After reset Function 0 0 0 0 FMN7 6 FMN6 5 FMN5 4 FMN4 R/W 3 FMN3 0 2 FMN2 0 1 FMN1 0 0 FMN0 0 Setting DVM bit7 to bit0 (Reference) In general, prime numbers (3, 5, 7, 11, 13 ...) are best for the value of the LCDDVM register. 92CH21-347 2007-02-28 TMP92CH21 fFP = 78.02 Hz (at = 120) LFR 1-picture display time LBCD 1 2 3 120 1 2 3 120 1 2 LLP LCP LD7 to LD0 (8-bit case) Use internal signal to CPU (Interrupt) Data transmission (1 row data) Figure 3.14.6 Whole Timing Diagram of SR Mode LFR tLP: LLP cycle tOPR: CPU opration time LBCD LLP Use internal signal (Internal) BUSRQ LCP0 LD7 to LD0 (8 bits) LCP0 N tSTOP: Stop time tLPH = fSYS × 4 tCP = 2 states N+1 Single CP N + 28 N + 29 Double CP LCP1 LD7 to LD0 (8 bits) N N+1 N + 28 N + 29 Note: XT = 1/32768 [s] 1 state = 1/fSYS [s] Figure 3.14.7 Detailed Timing Diagram of SR Mode Condition: FP [9:0] setting = 240 (COM) + 63, LCDDVM = 0BH LP1 LLP LP2 LP3 LP10 LP11 LP301 LP302 LP303 LP304 LFR DVM disable DVM enable Figure 3.14.8 Waveform of LLP, LFR 92CH21-348 2007-02-28 TMP92CH21 3.14.3.6 LCD Data Transmission Speed and Data Bus Occupation Rate After setting start register, the LCDC outputs a bus release request to the CPU and reads data from source memory. The LCDC then transmits LCD size data to the external LCD driver through the special LCDC data bus (LD11 to LD0). At this time, the control signals connected to the LCD driver output the specified waveform which is synchronized with the data transmission. After data reading from RAM for display is completed, the LCDC cancels the bus release request and the CPU will restart. During data read from source memory (during DMA operation), the CPU is stopped by the internal BUSREQ signal. When using SR mode LCDC, programmers must monitor CPU performance. The occupation rate of the data bus depends on data size, transmission speed (CPU clock speed) and display RAM type used. Valid Data Reading Time tLRD (ns/Byte) at fSYS = 20 MHz 50 25 12.5 *25 *12.5 Display RAM External SRAM Internal RAM External SDRAM Bus Width 16 bits 32 bits 32 bits 16 bits 32 bits Valid Data Reading Time (fSYS Clock/Byte) 2/2 2/4 1/4 *1/2 *1/4 Note: When using SDRAM for display RAM, overhead time (+ 8 clocks) is required for every 1 row data reading. tSTOP refers to the CPU stoppage time during transmission of 1 row data. tSTOP is calculated by the equation below for each display mode. tSTOP = (SegNum × K/8) × tLRD SegNum K : Number of segment : bit number per pixel (bpp) Monochrome 4 Grayscales 8/16 Grayscales 256 colors 4096 colors K=1 K=2 K=4 K=8 K = 12 ; Except SDRAM use When SDRAM is used, more overhead time is required. tSTOP = (SegNum × K/8) × tLRD + ((1/fSYS) × 8) ; SDRAM use Data bus occupation rate equals the percentage of tSTOP time in tLP time. Data bus occupation rate = tSTOP/tLP Note: For tLP time, refer to “refresh rate setting”. 92CH21-349 2007-02-28 TMP92CH21 3.14.3.7 Timing Diagram of LD Bus The TMP92CH21 can select to display RAM for external SRAM: Available to set WAIT, internal SRAM and external SDRAM: 16, 32, 64, 128, 256 and 512 Mbits. As a 480-byte FIFO buffer is built into this LCDC, the LD bus speed can be controlled. The speed can be selected from 3 kinds of cycle: (fSYS/2, fSYS/4, and fSYS/8) LD bus data: LD11 to LD0 is out at rising edge of LCP0, LCD driver receives at falling edge of LCP0. Note: If the LCP cycle is too slow it may not transfer correctly. fSYS LCP0 CP 2-clock LD7 to LD0 LCP0 CP 4-clock LD7 to LD0 LCP0 CP 8-clock LD7 to LD0 Figure 3.14.9 Selection of LCP Cycle If LCP cycle is not set at a suitable speed with respect to the refresh rate, LD bus data will not transfer correctly. tLP time is shown in the equation below. tLP [s] = (1/fSYS [Hz]) × 16 × (SCC+1) Data transmission must finish in tLP time. Set SCC clock and LCP0 speed to be less than tLP time. For setting of SCC, refer to “basic clock setting” of “refresh rate setting”. The kind of display memory and display mode determine LCP speed. In other words, when the setting is too fast , there will be not enough transmission data in FIFO, and LCD data will not transfer correctly. 92CH21-350 2007-02-28 TMP92CH21 Internal system clock (fSYS) A23 to A0 RD N N+1 N+2 N+3 N+4 N+5 D32 to D0 or D15 to D0 IN IN + 1 IN + 2 IN + 3 IN + 4 IN + 5 8-bit bus LCP0 (2CP) LD7 to LD0 OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4 32-bit bus width, monochrome /4 grayscales/256 colors OUT OUT LCP0 (4CP) 16-bit bus width, monochrome /4 grayscales/256 colors OUT OUT + 1 OUT + 2 OUT + 3 LD7 to LD0 LCP0 (8CP) 16-bit bus, 16 grayscales LD7 to LD0 OUT 4-bit bus LCP0 (2CP) LD3 to LD0 OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4 32-bit bus, monochrome /4/16 grayscales/256 colors OUT OUT LCP0 (4CP) 16-bit bus, monochrome 4/16 grayscales/256 colors LD3 to LD0 OUT OUT + 1 OUT + 2 OUT + 3 Figure 3.14.10 Fastest Timing Diagram for External SRAM, 0 waits 4-/8-bit bus LCP0 (2CP) Monochrome/4/16 grayscales LD7 to LD0 OUT OUT OUT + 1 OUT + 1 OUT + 2 OUT + 2 OUT + 3 OUT + 3 OUT + 4 OUT + 4 /256 colors ∗ When using internal SRAM, always select 32-bit bus width and 0 waits, 1 clocks access. Figure 3.14.11 Timing Diagram for Internal SRAM 92CH21-351 2007-02-28 TMP92CH21 fSYS A23 to A0 RD 227 Row Column D31 to D0 or D16 to D0 IN IN + 1 IN + 2 IN + 3 IN + 4 IN + 5 IN + 6 IN +7 8-bit bus LCP0 (2CP) LD7 to LD0 OUT + 1 OUT + 2 OUT + 3 OUT + 4 OUT + 5 OUT + 6 16-bit bus, monochrome /4 grayscales/256 colors 32-bit bus, monochrome OUT /4 grayscales/256 colors LCP0 (4CP) 16-bit bus, 16 grayscales LD7 to LD0 OUT OUT + 1 OUT + 2 4-bit bus LCP0 (2CP) LD3 to LD0 OUT + 1 OUT + 2 OUT + 3 OUT + 4 OUT + 5 OUT + 6 16-bit bus, monochrome /4/16 grayscales/256 colors OUT 32-bit bus, monochrome /4/16 grayscales/256 colors Figure 3.14.12 Timing Diagram of SDRAM Burst Run 92CH21-352 2007-02-28 TMP92CH21 3.14.3.8 Setting of Color Palette This LSI can support monochrome, 4-, 8-, 16-level grayscales and color STN panels, and color TFT panels. The following shows the settings for each mode. • Monochrome No need for special setting, simply select monochrome mode by LCDMODE1 register. • 4, 8, 16 grayscales No need for special setting, as with monochrome mode, simply select monochrome mode by LCDMODE1 register. For 8- and 16-level grayscale modes, both settings need 4-bit data per 1 pixel. Even if set to 8 grayscales mode, the LSB bit of the display data is invalid. • 256 colors STN Firstly, select STN256 color mode by LCDMODE1 and next set the detail contrast adjustment. In 256STN color mode, 8-bit display data is divided into 3 bits (red), 3 bits (green) and 2 bits (blue). Red and green are 8-level contrast and blue is 4 level contrast. Each level can be adjusted from 16-level contrast. Red contrast level can be selected by LCDRP10, LCDRP32, LCDRP54 and LCDRP76registers, green by LCDGP10, LCDGP32, LCDGP54 and LCDGP76, and blue by LCDBP10, and LCDBP32. As a result, support is given for for 8 bpp: 256 colors out of a palette of 4096 colors. • Color palette setting (Red) Selectable > 8-bit data 0 1 2 3 4 5 6 7 8 9 A B C D E F 7 6 5 4 3 2 1 0 * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * * * @ * * * * * * * * * * * * ∗ * * • Color palette setting (Green) Selectable 8-bit data 7 6 5 4 3 2 1 0 > 9 * * * * * * * * 2 * * * * * * @ * 3 * * * * * * * * 4 * * * * * @ * * 5 * * * * * * * * 6 * * * * @ * * * 7 * * * * * * * * 8 * * * @ * * * * A * * @ * * * * * B * * * * * * * * C * @ * * * * * * D * * * * * * * * E @ * * * * * * * F * * * ∗ * * * * • Color palette setting (Blue) Selectable 8-bit data 3 2 1 0 > 9 * * * * 2 * * * * 3 * * * * 4 * * @ * 5 * * * * 6 * * * * 7 * * * * 8 * @ * * A * * * * B * * * * C @ * * * D * * * * E * * * * F * * * * *: Selectable contrast point @: Initial setting point Figure 3.14.13 Palette Setting of Each Basic Color (RGB) 92CH21-353 2007-02-28 TMP92CH21 • 4096 colors STN STN4096 color mode is selected by LCDMODE1. This LCDC has a maximum 4096-color palette. If STN4096 color mode is selected, individual color contrast levels cannot be adjusted. 92CH21-354 2007-02-28 TMP92CH21 3.14.3.9 Example of SR Type LCD driver connection COM001 240 commons × 80 segments LCD (Color) SEG001 SEG240 T6C13B (240-column driver selection) Note: Other circuit is necessary for LCD drive power supply for LCD driver display. VSS TEST DUAL VCCLR V0LR,V2LR, VSSLR,V3LR V5LR O240 SEG240 COM240 TMP92CH21 VDD T6C13B (240-row driver selection) VDD VSS DIR TEST DI7 to DI0 DUAL SCP S/C VCCL/R, V0L/R, V1L/R, V4L/R, V5L/R O240 DSPOF FR LP EIO2 EIO1 O001 COM001 VSS 240 commons × 240 segments LCD (Monochrome) SEG001 DIR VDD S/C O001 COM240 LBCD LCP0 LLP LFR Port LD7 to LD0 Open Open SCP LP FR DSPOF DI7 to DI0 EIO1 EIO2 VSS VDD VSS Figure 3.14.14 Interface Example for Shift Register Type LCD Driver 92CH21-355 2007-02-28 TMP92CH21 3.14.3.10 Program Example (4 K colors STN) ; ********PORT settings ********* ld ld ld (PLFC), 0ffh (PLCR), 0f0h (PKFC), 0fh ; LD7 to LD0 set ; Output mode ; LBCD, LLP, LCP0 ; ********LCD settings********* ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld (LCDSCC), 51 (LCDCCR0), 01h (LCDCCR1), 01h (LCDCCR2), 02h (LCDSIZE), 64h (LCDFFP), 240 (LCDMODE0), 096h (LCDMODE1), 02h (LSARCL), 00h (LSARCM), 00h (LSARCH), 40h (LSARAL), 00h (LSARAM), 00h (LSARAH), 00h (LSARBL), 00h (LSARBM), 00h (LSARBH), 00h (CMNAL), 00h (CMNAH), 00h (CMNBL), 00h (CMNBH), 00h (LCDCTL1), 0e0h (LCDDVM), 3 (LCDCTL0), 01h ; START (FP bit8 = 0) ; B area Row number ; ; SCP0, SCP1: Negative edge, BCD: ; Counter set (Refresh rate: 100 Hz at fc = 40 MHz) ; ; SCP Negative edge ; ; 240 com × 256 seg ; 240 com ; SDRAM, STN: 4 K ; 8-bit width A type ; C area (enable) ; ; ; A area (disable) ; ; ; B area (disable) ; ; ; A area Row number 92CH21-356 2007-02-28 TMP92CH21 3.14.4 TFT Color Display Mode This is basically the same setting as for SR mode. Set the mode of operation, start address of source data save memory, color level and LCD size to control registers before setting start register. After setting start register, the LCDC outputs a bus release request to the CPU and reads data from source memory. After data reading from source data is completed, the LCDC cancels the bus release request and the CPU will restart. The LCDC then transmits LCD size data to the external LCD driver through the LD bus (the special data bus only for LCD driver). At this time, the control signals (LCP0 etc.) connected to the LCD driver output the specified waveform which is synchronized with the data transmission. In TFT mode LCDC, the CPU is stopped by the internal BUSREQ signal during data read from source memory (during DMA operation). The LCD controller generates control signals (LFR, LBCD, LLP etc.) from base clock LCDSCC. LCDSCC is the base clock for the LCD controller, which is generated by system clock fSYS. For TFT source driver, the following signals are supported: 8-bit RGB or 4-bit × RGB special data bus and LCP0, LFR, LLP and LDIV. And for TFT gate driver control, LCP1, LBCD and LGOE2 to LGOE0. 3.14.4.1 Description of Operation 3.14.4.2 Memory Space Memory space setting is the same as for SR mode. Refer to SR mode section. 3.14.4.3 Mapping of Display Memory and Panning Function Panning function and display memory mapping are the same as for SR mode. Refer to SR mode section. 3.14.4.4 Data Transmission This LSI outputs display data form special bus for LCD driver. The LCD driver input width can be selected. 8-bit and 12-bit widths are supported. 92CH21-357 2007-02-28 TMP92CH21 Relation of memory map image and output data • 256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits) Display memory image Address 1 5 6 7 8 Address 2 Address 3 MSB D31 LSB D0 0 1 R1 LSB D0 2 Address 0 3 4 G1 Address 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R2 G2 Address 5 B2 R3 G3 Address 6 B3 R4 G4 Address 7 B4 MSB D31 B1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R5 G5 B5 R6 G6 B6 R7 G7 B7 R8 G8 B8 LD bus output sequence 8 bits (TFT) LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 0 (R1) → 8 (R2) 1 (R1) → 9 (R2) ... ... 2 (R1) → 10 (R2) ... 3 (G1) → 11 (G2) ... 4 (G1) → 12 (G2) ... 5 (G1) → 13 (G2) ... 6 (B1) → 14 (B2) ... 7 (B1) → 15 (B2) ... * When using 256-color TFT mode, 8-bit LD bus width must be used. LD8, LD9, LD10 and LD11 terminals are available for use as general ports. Figure 3.14.15 Relation of Memory Map Image and Output Data (5) 92CH21-358 2007-02-28 TMP92CH21 Relation of memory map image and output data • 4096 colors (12 bpp; R: 4 bits, G: 4 bits, B: 4 bits) Display memory image Address 1 5 6 7 8 Address 2 Address 3 MSB D31 LSB D0 0 1 2 Address 0 3 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 B1 Address 5 R2 G2 Address 6 B2 R3 Address 7 G3 MSB D31 R1 LSB D0 Address 4 G1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 B3 R4 G4 B4 R5 G5 B5 R6 LD bus output sequence 12 bits (TFT) LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 0 (R1) 1 (R1) 2 (R1) 3 (R1) 4 (G1) 5 (G1) 6 (G1) 7 (G1) 8 (B1) 9 (B1) 10 (B1) 11 (B1) → 12 (R2) … → 13 (R2) … → 14 (R2) … → 15 (R2) … → 16 (G2) … → 17 (G2) … → 18 (G2) … → 19 (G2) … → 20 (B2) … → 21 (B2) … → 22 (B2) … → 23 (B2) … Figure 3.14.16 Relation of Memory Map Image and Output Data (6) 92CH21-359 2007-02-28 TMP92CH21 3.14.4.5 Setting Each Control Signals The TFT source driver is controlled by base clock (LCP0), data start clock (LFR) and load pulse (LLP). Special data bus LD11 to LD0 uses 8 bits or 12 bits for suitable LCD driver. The timing of each signal can be finely adjusted using the relevant control register. When using the TFT driver a large amount of data is required. So, when using wide bus and high speed transmission, some noise may be generated. This LSI has an LDIV function. This function automatically sets the minimum data change method, from inverting data and LDIV signal, to comparing current data with the previous data. If the TFT LCD driver supports the data inverting function, it is possible to decrease the noise. The following shows basic timings. LFR (Support to DVM setting) 1 LCP1 (Rise up) LBCD (Low Enable setting) LLP Vertical Back Porch (No control counter) Horizontal Back Porch (No control counter) 2 3 4 5 6 7 8 9 COM Gate driver control Horizontal Front Porch (LCDCCR0) Horizontal Front Porch (LCDCCR1) (fSYS: 8 clocks × 5-bit counter) This example shows register value “0”. (Counter LCP1: 3-bit) This example shows register value “0”. LLP (Mode1) Offset time is fsys(14 to 16 Source driver control LLP (Mode2) 123456789 SEG LCP0 (Rise up) LD11 to LD0 High Width Control(LCDCCR2) (fSYS: 8 clocks × 8-bit counter) When register is set “0”, high level width is out when LD bus data is valid. Figure 3.14.17 Timing Diagram of TFT Driver Control 92CH21-360 2007-02-28 TMP92CH21 LCD Clock Counter Register 0 7 LCDCCR0 Bit symbol (0288H) Read/Write After reset Function 6 5 4 3 2 PCPV2 R/W 0 1 PCPV1 R/W 0 0 PCPV0 R/W 0 Pre LCP1 CLK: LCP1 pulse number Dummy clock number until valid clock of gate driver LCP1 Delay control 1 is set by LCDCCR0. Delay of Dummy clock is controlled by pulse number derived by subtracting common number and from LCDFFP (refer to SR mode section). LCD Clock Counter Register 1 7 LCDCCR1 Bit symbol (0289H) Read/Write After reset Function 6 5 4 TLDE4 R/W 0 3 TLDE3 R/W 0 2 TLDE2 R/W 0 1 TLDE1 R/W 0 0 TLDE0 R/W 0 LLP_Set-up time: fSYS pulse × 8 Set up time for TFT source driver LLP signal (Offset of fSYS 14∼16 pulse) Set up time of LLP (horizontal front porch) is set in LCDCCR1. This is called “Delay control 2”. 1 pulse of this set up time in LCDCCR1 register is equal to 8 times of fsys regardless of LCP0 and LCP1. The set up time has offset time; fsys*14 to 16(fSYS × 14.5 or more). If “0” is written in LCDCCR1 register, fsys*14 to 16 of time is delayed. This offset time changes according to the setting conditions. The cycle of LCP1 is determined by (the value of LCDSCC register +1) * fsys * 16, thus horizontal back porch is the time when offset time and set up time are subtracted from the cycle of LCP1. LCD Clock Counter Register 2 7 LCDCCR2 Bit symbol (028AH) Read/Write After reset Function LLPSU7 R/W 0 6 LLPSU6 R/W 0 5 LLPSU5 R/W 0 4 LLPSU4 R/W 0 3 LLPSU3 R/W 0 2 LLPSU2 R/W 0 1 LLPSU1 R/W 0 0 LLPSU0 R/W 0 TFT source driver, LLP_Enable signal: fSYS × 8 High width time for LLP signal The pulse number of LCP0 in LCDCCR2 means enable time of LLP. This register determines “High width” time as mentioned above. 1 pulse of this time in LCDCCR2 register is equal to 8 times of fsys regardless of LCP0 and LCP1. If “0” is written in LCDCCR2 register, High level is output during the period that the valid data is output from LD bus. (In Mode1, high level is kept during one more LCP0 than valid data.) 92CH21-361 2007-02-28 TMP92CH21 3.14.5 Source Driver Control Data shift clock; LCP0 , Data; LD11 to LD0 and LLP signals become valid after the time ( offset time + set up time set in (LCDCCR1) ) from LCP1. LLP signal has 2 modes ; Mode1 ( LLP rises 1 LCP0 clock before valid data ) and Mode2 ( LLP rises at the same time as valid data ) 1. The cycle of LCP1 is determined by (LCDSCC+1) × fSYS × 16 2. The number of LCP0 in the cycle of LCP1 is determined by the cycle of LCP0 clock. LCP1 (Rising up) LLP Offset 14×fSYS or more LLP Set up LCDCCR1 Enable width of LCP1 is fixed at 4 fSYS × 1 LCP0 (Rising up, LCP0 = 2×fSYS) LLP Mode1 2 8 12 13 14 15 16 332 333 334 1 2 3 Segments LD11~LD0 (RGB) LDIV 1st Last Setting of High width of LLP LCDCCR2（Mode1/Mode2） LLP Mode2 LD11~LD0 (RGB) LDIV 1st Segments Last * Condition: Segment = 320, LCDCCR1 = 1, LCP0 = 2×fSYS , LCDSCC = 41 Figure 3.14.18 Timing Example for TFT Driver Note: The above figure and explanation are under the following condition. CPHP = 1, CPVP = 0 When CPHP = 0, CPVP = 1 , the alignment of LCP0/LCP1 inverts. 92CH21-362 2007-02-28 TMP92CH21 3.14.5.1 Gate Driver Control The TFT gate driver is controlled bybase clock LCP1and vertical shift data signal LBCD. This LSI has 3-bit output enable signals LGOE2 to LGOE0which can be controlled individually. The TFT gate driver’s output can be controlled by this timing and is available for blanking adjustment and zoom function. The LBCD signal begins output from rising of LCP1 and the TFT gate driver recognizes the start point of the vertical direction. LGOE0 then outputs from rising of LCP1 and repeats. LGOE1 outputs one LCP1 clock delayed. LGOE2 delay one LCP1 clock from LGOE1. By LCDCTL1 setting, the width of LBCD can be selected from 1, 2, or 3 clocks of LCP1. 1. The cycle of LBCD is determined by the setting of (LCDFFP) register. 2. Enable width of LBCD is selectable from (1×LCP1) to (3×LCP1). LCP1 counter LCP1 (Rising up) LBCD 1 2 3 4 5 6 7 8 9 com + m 1 2 LGOE0 LGOE1 LGOE2 *Pre LCP1_SET LCDCCR0 LLP 1 2 Note 1: LCP1 counter (LCDFFP) : 1024 clocks maximum Note 2: Pre_LCP1_SET (LCDCCR0) : 8 clocks (3bits) of LCP1 maximum Figure 3.14.19 Example of TFT Gate Driver Timing Control 92CH21-363 2007-02-28 TMP92CH21 (Notes on settings) 1. LCP0 cycle: LCP0=fSYS × n (n=2, 4, 8: transmission speed of LD bus) LCP0 cycle is generated by system clock and value of LCDMODE0 2. LCP1 cycle: LCP1= fSYS × 16 × (SCC + 1) LCP1 cycle is generated by value of LCDSCC register. High level width of LCP1 is fixed to fSYS × 4 times. (Positive edge) As indicated above, the cycles of LCP0 and LCP1 are able to set each other. There are some limitations to settings of LD bus speed and LCDSCC. Segment Size Transmission Speed of LD bus 2 Minimum LCDSCC value 9 17 33 17 33 65 21 41 81 33 65 129 41 81 161 64 4 8 2 128 4 8 2 160 4 8 2 256 4 8 2 320 4 8 High level width of LLP is adjusted every fSYS × 8 cycle. However, LLP is adjusted every 2-clock of LLP when transmission speed of the LD bus is set to 2-Clock. LLP is also adjusted every 4-clock of LLP when transmission speed of the LD bus is set to 4-clock of LCP0. Setting method is the same as in the STN case, following the calculation below. fBCD [Hz] FP SCC : Frame frequency (Refresh rate: LBCD cycle) : FP [9:0] FFP register setting value : SCC [7:0] LSCC register setting value fBCD [Hz] = fSYS [Hz] / ((SCC+1) × 16 × FP) Frame correction function is the same as in the STN case. 3. LCP1 Setting : Vertical front porch is determined by LCDCCR0. Vertical front porch is determined by the above 3bits; LCDCCR0. Vertical back porch is controlled by the pulse number which is subtracted from LCDFFP as explained in the SR mode section. 92CH21-364 2007-02-28 TMP92CH21 4. LLP Setting : Set up time is determined by LCDCCR1. Set up time of LLP (horizontal front porch) is set in LCDCCR1 register. This is called “Delay control 2”. 1 pulse of this set up time in LCDCCR1 register is equal to 8 times of fsys regardless of LCP0 and LCP1. The set up time has offset time; fsys×14 or more. If “0” is written in LCDCCR1 register, fsys×14.5 or more of time is delayed. This offset time changes according to the setting conditions. The cycle of LCP1 is determined by (the value of LCDSCC register +1) × fsys × 16, thus horizontal back porch is the time where offset time and set up time are subtracted from the cycle of LCP1. 5. LLP High width : High width of LLP is determined by LCDCCR2. The pulse number of LCP0 in LCDCCR2 means enable time of LLP. This register determines “High width” time as mentioned above. 1 pulse of this time in LCDCCR2 register is equal to 8 times of fsys regardless of LCP0 and LCP1. If “0” is written in LCDCCR2 register, High level is output during the period that the valid data is output from the LD bus. (In Mode1, high level is kept during one more LCP0 than valid data.) 6. LDIV: Enable/disable of Auto Invert function is determined by LCDMODE1. If “1” is written in LCDMODE1 bit, the LCD controller monitors the status of the LD bus. The LCDC compares the value of previous data with the data supposed to be sent. If more than a majority of all the LD bus change, LDIV outputs “1” and the LCDC inverts the LD bus value that was supposed to be sent. For example, if 4096 color(12bit ： LD11 to LD0) and the data changes from 000000000000→111111111111, the data remains 000000000000→000000000000 and only LDIV changes 0→1. This is effective in reducing noise or power consumption where the LCD driver has an LDIV pin. 92CH21-365 2007-02-28 TMP92CH21 7. LGOE0 to 2 : Programmable waveform LGOE0 is output on the rising edge of the first LCP1 and repeats every 3 pulses of LCP1. LGOE1 is the 2nd LCP1 and LGOE2 the 3rd, and they also repeat every 3 pulses of LCP1. LGOE0 to LGOE2 can be generated by 1/16 clocks of LCP1 cycle set in control registers (48bits × 3) respectively. These signals can finely adjust the gate output signal and this will enables fine adjustment of gate bias (the setting of blanking) or zoom function without modification of data etc. 1 LCP1 2 3 4 5 6 7 8 9 LGOEn Various waveforms can be made ; minimum resolution is 1/16 of LCP1 clock (total 1/48) repeat portion LGOEn (example) LSB← 100000000000000110000000000000111100000000000111 →MSB repeat portion * Various waveforms can be generated by writing LCDOEn5 to LCDOEn0 registers (48bits for each signal). (When “1” is written, output is High level. When “0” is written, output is Low level. The direction of data is from LSB to MSB. ) Figure 3.14.20 Details of waveform of LGOEn for gate driver Note1) The above explanation and figures are given for the setting below. Condition: CPHP = 1, CPVP = 0 For CPHP = 0, CPVP = 1 setting, LCP0 and LCP1 phases are inverted. Note2) The minimum resolution of LGOEn is 1/16 of LCP1 cycle. LCP1= (LCDSCC+1 ) × fSYS ×16 Thus, the minimum resolution of LGOEn is (LCDSCC +1) × fSYS. 92CH21-366 2007-02-28 TMP92CH21 3.14.5.2 Example of TFT LCD driver connection TMP92CH21 VDD VSS JBT6L78-AS (162-gate driver) VDD U/D TEST1 TEST2 VSS OE3 to OE1 G1 G1 160 SEG × 3 (RGB) × 162 COM LCD G162 G162 SA160 SB160 SC160 SA80 SB80 SC80 CPH LOAD DO/I DA5 to 2 DB5 to 2 DC5 to 2 LGOE2 to LGOE0 SA80 SB80 SC80 SA80 SB80 SC80 DA5 to DA2 DB5 to DB2 DC5 to SC2 U/D VDD VSS DA1 to DA0 DB1 to DB0 DC1 to DC0 Control D31 to D0 A0 to A23 Axx to Axx D31 to D0 Control Display memory (SDRAM/SRAM) VDD VSS JBT6L77-AS × 2 (80 × RGB-source driver) Note: Other circuit is required for power supply for driving LCD driver. Figure 3.14.21 Example of TFT Type LCD Driver Interface VSS DA1 to DA0 DB1 to DB0 DC1 to DC0 LBCD LCP0 LLP LFR LCP1 LD11 to LD0 Open CPV DO/I DI/O CPH LOAD DI/O SA1 SB1 SC1 SA1 SB1 SC1 SA81 SB81 SC81 SA1 SB1 SC1 Open DO/I DI/O U/D VDD 92CH21-367 2007-02-28 TMP92CH21 3.14.5.3 Program sample (4K color TFT) ; ********PORT settings ********* ld ld ld ld ld ld (PACR), 78h (PLFC), 0ffh (PLCR), 0f0h (PKFC), 0bh (PCCR), 0c0h (PCFC), 0c0h ; LD11-LD8 set ; LD7-LD0 set ; Output mode ; LBCD, LLP, LCP0 ; PC6: LDIV (for TFT) PC7: LCP1 ; PC6: LDIV ; ********LCD settings********* ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld ld (LCDSCC), 100 (LCDCCR0), 00h (LCDCCR1), 00h (LCDCCR2), 00h (LCDSIZE), 74h (LCDFFP), 49h (LCDMODE0), 059h (LCDMODE1), 01h (LCDCTL0), 02h (LCDCTL1), 00h (LSARCL), 00h (LSARCM), 00h (LSARCH), 40h (LSARAL), 00h (LSARAM), 00h (LSARAH), 00h (LSARBL), 00h (LSARBM), 00h (LSARBH), 00h (CMNAL), 00h (CMNAH), 00h (CMNBL), 00h (CMNBH), 00h ; B area Row number ; ; Counter set (refresh rate:50Hz at fc = 40MHz) ; ; ; ; 320 com × 256 seg ; 320 com ; SRAM, TFT 4096 color ; Invalid 8bit A type ; (FP bit8=1) ; SCP0,SCP1:negedge, BCD:↓ ; C area (enable) ; ; ; A area (disable) ; ; ; B area (disable) ; ; ; A area Row number ld (LCDCTL0), 03h ; START (FP bit8 = 1) 92CH21-368 2007-02-28 TMP92CH21 3.14.6 Built-in RAM Type LCD driver Mode Data transmission to the LCD driver is executed by a transmit instruction from the CPU. After setting operation mode of to the control register, when a CPU transmit instruction is executed the LCDC outputs a chip select signal to the LCD driver connected externally by the control pin (LCP0...). Therefore control of data transmission numbers corresponding to LCD size is controlled by CPU instruction . There are 2 kinds of LCD driver address in this case, which are selected by the LCDCTL register. 3.14.6.1 Description of Operation 3.14.6.2 Random Access Type This corresponds to address direct writing type LCD driver when = “1”. The transmission address can also assign the memory area 3C0000H − 3FFFFF, the four areas each being 64 Kbytes. Interface and access timing are the same as for normal memory. Refer to the memory access timing section. Table 3.14.2 Racdom Access Type Built-in RAM Type LCD driver Address 3C0000H to 3CFFFFH 3D0000H to 3DFFFFH 3E0000H to 3EFFFFH 3F0000H to 3FFFFFH Function Built-in RAM LCDD1 Built-in RAM LCDD2 Built-in RAM LCDD3 Built-in RAM LCDD4 Chip Enable Terminal LCP0 LLP LFR LBCD 92CH21-369 2007-02-28 TMP92CH21 3.14.6.3 Sequential Access Type Data transmission to the LCD driver is executed by a transmit instruction from the CPU. After setting operation mode to the control register, when a CPU transmit instruction is executed the LCDC outputs a chip select signal to the LCD driver connected externally by the control pin (LCP0...). Therefore control of data transmission numbers corresponding to LCD size is controlled by CPU instruction . There are 2 kinds of LCD driver address in this case, which are selected by the LCDCTL register. This corresponds to a LCD driver which has each 1 byte of instruction register and display data register in LCD driver when = “0”. Please select the transmission address at this time from 1FE0H to 1FE7H. LCDC0L/LCDC0H/LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDR0L/LCDR0H Register 7 Bit symbol Read/Write After reset Function D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Depends on external LCDD specification Depends on external LCDD specification Depends on external LCDD specification [Write cycle] T1 System clock: fSYS A23 to A0 TW T2 T1 [Read cycle] TW T2 R/ W LCP0, LLP, LFR, LBCD D7 to D0 Data out Data in WAIT sampling Note 1: Note 2: This waveform is in the case of 3-state access. Rising timing of chip enable signal (e.g LCP0) is different. Figure 3.14.22 Example of Access Timing for Built-in RAM Type LCD Driver (Wait = 0) 92CH21-370 2007-02-28 TMP92CH21 3.14.6.4 Example of Built-in RAM LCD driver connection TMP92CH21 VDD VSS T6B66A (65-row driver) VDD VSS VLC1, VLC2, VLC3, VLC4, VLC5 LE DB0 to DB5 COM065 SEG001 SEG080 VSS VLC2, VLC3, VLC5 T6B65A (80-column driver) Note: Other circuit is required for power supply for LCD driver display. COM065 WR COM001 COM001 65 COM × 80 SEG LCD SEG001 R/W CE WR A0 D0 to D7 Open D/I DB0 to DB7 EIO1 EIO2 VDD VDD VSS Figure 3.14.23 Interface Example for Built-in RAM and Sequential Access Type LCD Driver 92CH21-371 2007-02-28 SEG080 LLP LCP0 TMP92CH21 3.14.6.5 Program Example • Setting example: when using 80 segments × 65 commons LCD driver. Assign external column driver to LCDC1 and row driver to LCDC4. This example uses LD instruction in setting of instruction and micro DMA burst function for soft start in setting of display data. When storing 650-byte transfer data to LCD driver. ; ********Setting for LCDC********* ld ld (lcdmode0), 00h (lcdctl0), 00h ; Select RAM mode ; MMULCD = 0 (Sequential access mode) ; ********Setting for mode of LCDC0/LCDR0********* ld ld (lcdc1l), xx (lcdc4l), xx ; Setting instruction for LCDC1 ; Setting instruction for LCDC4 ; ********Setting for micro DMA and INTTC (ch0)********* ld ldc ld ldc ld ldc ld ldc ld ei ld ld a, 08h dmam0, a wa, 650 dmac0, wa xwa, 002000h dmas0, xwa xwa, 1fe1h dmad0, xwa (intetc01), 06H 6 (dmab), 01h (dmar), 01h ; Source address INC mode ; ; Count = 650 ; ; Source address = 002000H ; ; Destination address = 1FE1H (LCDC0H) ; ; INTTC0 level = 6 ; ; Burst mode ; Soft start 92CH21-372 2007-02-28 TMP92CH21 3.15 Melody/Alarm Generator (MLD) The TMP92CH21 contains a melody function and alarm function, both of which are output from the MLDALM pin. Five kinds of fixed cycle interrupt are generated using a 15-bit counter for use as the alarm generator. The features are as follows. 1) Melody generator The Melody function generates signals of any frequency (4 Hz to 5461 Hz) based on a low-speed clock (32.768 kHz), and outputs the signals from the MLDALM pin. The melody tone can easily be heard by connecting an external loudspeaker. 2) Alarm generator The alarm function generates eight kinds of alarm waveform having a modulation frequency (4096 Hz) determined by the low-speed clock (32.768 kHz). This waveform can be inverted by setting a value to a register. The alarm tone can easily be heard by connecting an external loudspeaker. Five kinds of fixed cycle interrupts are generated (1 Hz, 2 Hz, 64 Hz, 512 Hz, and 8192 Hz) by using a counter which is used for the alarm generator. This section is constituted as follows. 3.15.1 3.15.2 Block Diagram Control Registers 3.15.3 Operational description 3.15.3.1 Melody Generator 3.15.3.2 Alarm Generator 92CH21-373 2007-02-28 TMP92CH21 3.15.1 Block Diagram [Melody Generator] Internal data bus Reset MELFH, MELFL register MELOUT MELFH Stop and clear Clear Low-speed clock 12-bit counter (UC0) Invert Comparator (CP0) F/F INTALM0 (8192 Hz) INTALM1 (512 Hz) Edge detector INTALM2 (64 Hz) INTALM3 (2 Hz) INTALM4 (1 Hz) 15-bit counter (UC1) 4096 Hz MELALMC 8-bit counter (UC2) ALMINT INTALMH (HALT release) MELOUT Alarm wave form generator Selector Invert ALMOUT MELALMC MELALMC MLDALM pin ALM register [Alarm Generator] Internal data bus Reset Figure 3.15.1 MLD Block Diagram 92CH21-374 2007-02-28 TMP92CH21 3.15.2 Control Registers ALM Register 7 ALM (1330H) Bit symbol Read/Write After reset Function 0 0 0 0 AL8 6 AL7 5 AL6 4 AL5 R/W 3 AL4 0 2 AL3 0 1 AL2 0 0 AL1 0 Setting alarm pattern MELALMC Register 7 MELALMC Bit symbol (1331H) Read/Write After reset Function FC1 R/W 0 00: Hold 01: Restart 10: Clear 11: Clear and start Note 1: Note 2: MELALMC is always read “0”. When setting MELALMC register except while the free-run counter is running, is kept “01”. 0 Free-run counter control 6 FC0 5 ALMINV R/W 0 Alarm waveform invert 1: Invert 4 − 0 3 − R/W 0 2 − 0 1 − 0 0 MELALM R/W 0 Output waveform select 0: Alarm 1: Melody Always write “0” MELFL Register 7 MELFL (1332H) Bit symbol Read/Write After reset Function 0 0 0 0 ML7 6 ML6 5 ML5 4 ML4 R/W 3 ML3 0 2 ML2 0 1 ML1 0 0 ML0 0 Setting melody frequency (Lower 8 bits) MELFH Register 7 MELFH (1333H) Bit symbol Read/Write After reset Function MELON R/W 0 Control melody counter 0: Stop and clear 1: Start Setting melody frequency (Upper 4 bits) 0 0 6 5 4 3 ML11 2 ML10 R/W 1 ML9 0 0 ML8 0 ALMINT Register 7 ALMINT (1334H) Bit symbol Read/Write After reset Function 6 5 − R/W 0 Always write “0” 4 IALM4E 0 3 IALM3E 0 2 IALM2E R/W 0 1 IALM1E 0 0 IALM0E 0 1: Interrupt enable for INTALM4 to INTALM0 92CH21-375 2007-02-28 TMP92CH21 3.15.3 Operational description The Melody function generates signals of any frequency (4 Hz to 5461 Hz) based on a low-speed clock (32.768 kHz) and outputs the signals from the MLDALM pin. The melody tone can easily be heard by connecting an external loud speaker. (Operation) MELALMC must first be set as 1 in order to select the melody waveform to be output from MLDALM. The melody output frequency must then be set to 12-bit registers MELFH and MELFL. The following are examples of settings and calculations of melody output frequency. (Formula for calculating melody waveform frequency) at fs = 32.768 [kHz] Melody output waveform Setting value for melody fMLD [Hz] = 32768/(2 × N + 4) N = (16384/ fMLD) − 2 3.15.3.1 Melody Generator (Note: N = 1 to 4095 (001H to FFFH), 0 is not acceptable.) (Example program) When outputting an “A” musical note (440 Hz) LD LD LD (MELALMC), − − X X X X X 1 B (MELFL), 23H (MELFH), 80H ; Select melody waveform ; N = 16384/440 − 2 = 35.2 = 023H ; Start to generate waveform Reference) Basic musical scale setting table Scale Frequency [Hz] C D E F G A B C 264 297 330 352 396 440 495 528 Register Value: N 03CH 035H 030H 02DH 027H 023H 01FH 01DH 92CH21-376 2007-02-28 TMP92CH21 3.15.3.2 Alarm Generator The alarm function generates eight kinds of alarm waveform having a modulation frequency of 4096 Hz determined by the low-speed clock (32.768 kHz). This waveform is reversible by setting a value to a register. The alarm tone can easily be heard by connecting an external loud speaker . Five kinds of fixed cycle (interrupts can be generated 1 Hz, 2 Hz, 64 Hz, 512 Hz, 8 192 Hz) by using a counter which is used for the alarm generator. (Operation) MELALMC must first be set as 0 in order to select the alarm waveform to be output from MLDALMC. The “10” must be set on the MELALMC register, and clear internal counter. Finally the alarm pattern must then be set on the 8-bit register of ALM. If it is inverted output-data, set as invert. The following are examples of program, setting value of alarm pattern and waveform of each setting value. (Setting value of alarm pattern) Setting Value for ALM Register 00H 01H 02H 04H 08H 10H 20H 40H 80H Others Alarm Waveform Write “0” AL1 pattern AL2 pattern AL3 pattern AL4 pattern AL5 pattern AL6 pattern AL7 pattern AL8 pattern Undefined (Do not set) (Example program) When outputting AL2 pattern (31.25 ms/8 times/1 s) LD LD (MELALMC), C0H (ALM), 02H ; Set output alarm waveform ; Free-run counter start ; Set AL2 pattern, start 92CH21-377 2007-02-28 TMP92CH21 Example: Waveform of alarm pattern for each setting value (Not inverted) AL1 pattern (Continuous output) 1 AL2 pattern (8 times/1 s) 31.25 ms 1 AL3 pattern (Once) 500 ms 1 AL4 pattern (Twice/1 s) 62.5 ms 1 AL5 pattern (3 times/1 s) 62.5 ms 1 2 3 2 2 Modulation frequency (4096 Hz) 8 1 1s 1 1s 1 1s AL6 pattern (Once) 62.5 ms AL7 pattern (Twice) 1 2 62.5 ms AL8 pattern (Once) 250 ms 92CH21-378 2007-02-28 TMP92CH21 3.16 SDRAM Controller (SDRAMC) The TMP92CH21 includes an SDRAM controller which supports SDRAM access by CPU/LCDC. The features are as follows. (1) Support SDRAM Data rate type: Bulk of memory: Number of banks: Width of data bus: Read burst length: Write mode: Only SDR (Single data rate) type 16/64/128/256/512 Mbits 2/4 banks 16/32 1 word/full page Single/burst (2) Initialize function All banks precharge command 8 times auto refresh command Set the mode register command (3) Access mode CPU Access Read burst length Addressing mode CAS latency (clock) Write mode 1 word/full page selectable Sequential 2 Single/burst selectable LCDC Access Full page Sequential 2 − (4) Access cycle CPU Access (Read/write) Read cycle: Write cycle: Access data width: 1 word− 4 states/full page − 1 state Single − 3 states/burst − 1 state 8 bits/16 bits/32 bits LCDC Burst Access (Read only) Read cycle: Over head: Access data width: 1 word (50 ns at fSYS = 20 MHz) 4 states (200 ns at fSYS = 20 MHz) 16 bits/32 bits (5) Refresh cycle auto generate Auto-refresh is generated while another area is being accessed. Refresh interval is programmable. Self-refresh is supported Note 1: Note 2: Display data for LCDC must be set from the head of each page. Condition of SDRAM’s area set by CS1 or CS2 setting of memory controller. 92CH21-379 2007-02-28 TMP92CH21 3.16.1 Control Registers Figure 3.16.1 shows the SDRAMC control registers. Setting these registers controls the operation of SDRAMC. SDRAM Access Control Register 1 7 SDACR1 (0250H) Bit symbol Read/Write After reset Function 0 Always write “0” 0 Always write “0” 0 Mode register set delay time 0: 1 clock 1: 2 clocks 0 Write recover time 0: 1 clock 1: 2 clocks − 6 − 5 SMRD 4 SWRC R/W 3 SBST 0 Burst stop command 0: Precharge all 1: Burst stop 2 SBL1 1 1 SBL0 0 0 SMAC 0 SDRAM controller 0: Disable 1: Enable Selecting burst length (Note 1) 00: Reserved 01: Full-page read, burst write 10: 1-word read, single write 11: Full-page read, single write Note 1: Issue mode register set command after changing . Exercise care in settings when changing from “full-page read” to “1-word read”. Please refer to “3.16.3 Limitations arising when using SDRAM”. SDRAM Access Control Register 2 7 SDACR2 (0251H) Bit symbol Read/Write After reset Function 0 Number of banks 0: 2 banks 1: 4 banks 0 6 5 4 SBS 3 SDRS1 2 SDRS0 R/W 0 1 SMUXW1 0 Selecting address multiplex type 00: TypeA (A9-) 01: TypeB (A10-) 10: TypeC (A11-) 11: Reserved 0 SMUXW0 0 Selecting ROW address size 00: 2048 rows (11 bits) 01: 4096 rows (12 bits) 10: 8192 rows (13 bits) 11: Reserved SDRAM Refresh Control Register 7 SDRCR (0252H) Bit symbol Read/Write After reset Function 0 Refresh interval 000: 47 states 001: 78 states 010: 97 states 011: 124 states 100: 156 states 101: 195 states 110: 249 states 111: 312 states 0 6 5 4 3 SRS2 2 SRS1 R/W 1 SRS0 0 0 SRC 0 Auto refresh 0: Disable 1: Enable 92CH21-380 2007-02-28 TMP92CH21 SDRAM Command Register 7 SDCMM (0253H) Bit symbol Read/Write After reset Function 0 Command issue (Note 1) (Note 2) 000: Not execute 001: Initialization sequence a. Precharge All command b. Eight Auto Refresh commands c. Mode Register Set command 100: Mode Register Set command 101: Self Refresh Entry command 110: Self Refresh Exit command Others: Reserved Note 1: is automatically cleared to “000” after the specified command is issued. Before writing the next command, make sure that is “000”. In the case of the Self Refresh Entry command, however, is not cleared to “000” by execution of this command. Thus, this register can be used as a flag for checking whether or not Self Refresh is being performed. Note 2: The Self Refresh Exit command can only be specified while Self Refresh is being performed. 6 5 4 3 2 SCMM2 1 SCMM1 R/W 0 0 SCMM0 0 Figure 3.16.1 SDRAM Control Registers 92CH21-381 2007-02-28 TMP92CH21 3.16.2 Operation Description (1) Memory access control SDRAM controller is enabled when SDACR1 = 1. And then SDRAM control signals ( SDCS , SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM, SDCLK and SDCKE) are operating during the time CPU or LCDC accesses CS1 or CS2 area. 1. Address multiplex function In the access cycle, outputs row/column address through A0 to A15 pin. And multiplex width is decided by setting SDACR2 of use memory size. The relation between multiplex width and Row/Column address is shown in Table 3.16.3. Table 3.16.1 Address Multiplex Address of SDRAM Accessing Cycle TMP92CH21 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Row Address Column Address TypeA TypeB TypeC 16-Bit Data Bus Width 32-Bit Data Bus Width “00” “01” “10” B1CSH = “01” B1CSH = “10” A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 EA24 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 EA24 EA25 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 EA24 EA25 EA26 Row address A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP * A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 AP * * AP: Auto Precharge 2. Burst length When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write. When the LCDC accesses the SDRAM, the burst length is fixed to full page. SDRAM access cycle is shown in Figure 3.16.2 and Figure 3.16.3. SDRAM access cycle number does not depend on the settings of B1CSL and B2CSL registers. In the full page burst read cycle, a mode register set cycle and a precharge cycle are automatically inserted at the beginning and end of a cycle. (2) Instruction executing on SDRAM The CPU can execute instructions on SDRAM. However, the following functions do not operate. a) b) Executing HALT instruction Execute instructions that write to SDCMM register These operations must be executed by another memory such as the built-in RAM. 92CH21-382 2007-02-28 TMP92CH21 85 states (320-byte read) SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A10 A15 to A0 D31 to D0 RA RA CA (n) CA (n + 4) CA (n + 8) CA (n + 12) D (n) D (n + 4) D (n + 8) (n + 312) D (n + 12) (n + 316) D (n + 312) D (n + 316) Bank active Read All banks precharge Figure 3.16.2 Timing of Burst Read Cycle 3 states SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A10 A15 to A0 D31 to D0 RA RA OUT Bank active Write with precharge Internal precharge CA CA Figure 3.16.3 Timing of CPU Write Cycle (Structure of Data Bus: 32 bits × 1, operand Size: 4 bytes, address: 4 n + 0) 92CH21-383 2007-02-28 TMP92CH21 (3) Refresh control This LSI supports two refresh commands: auto-refresh and self-refresh. (a) Auto-refresh The auto-refresh command is automatically generated at intervals set by SDRCR by setting SDRCR to “1”. The generation interval can be set from between 47 to 312 states (2.4 μs to 15.6 μs at fSYS = 20 MHz). CPU operation (instruction fetch and execution) stops while performing the auto-refresh command. The auto-refresh cycle is shown in Figure 3.16.4 and the auto-refresh generation interval is shown in Table 3.16.2. The Auto-Refresh function cannot be used in IDLE1 and STOP modes. In these modes, use the SelfRefresh function to be explained next. Note: A system reset disables the Auto-Refresh function. 2 states SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE Auto-refresh Figure 3.16.4 Timing of Auto-Refresh Cycle Table 3.16.2 Refresh Cycle Insertion Interval SDRCR SRS2 0 0 0 0 1 1 1 1 (Unit: μs) SRS1 0 0 1 1 0 0 1 1 SRS0 0 1 0 1 0 1 0 1 Insertion Interval (State) 47 78 97 124 156 195 249 312 fSYS Frequency (System clock) 6 MHz 7.8 13.0 16.2 20.7 26.0 32.5 41.5 52.0 10 MHz 12.5 MHz 15 MHz 17.5 MHz 20 MHz 4.7 7.8 9.7 12.4 15.6 19.5 24.9 31.2 3.8 6.2 7.8 9.9 12.5 15.6 19.9 25.0 3.1 5.2 6.5 8.3 10.4 13.0 16.6 20.8 2.7 4.5 5.5 7.1 8.9 11.1 14.2 17.8 2.4 3.9 4.9 6.2 7.8 9.8 12.4 15.6 92CH21-384 2007-02-28 TMP92CH21 (b) Self-refresh The self-refresh ENTRY command is generated by setting SDCMM to “101”. The self-refresh cycle is shown in Figure 3.16.5. During self-refresh Entry, refresh is performed within the SDRAM (an auto-refresh command is not needed). The auto-refresh command is automatically executed once when self-refresh is released, following which, refresh is executed according to the setting of the autorefresh command. Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is exited. Note that the Auto Refresh function is also disabled at this time. Note 2: The SDRAM cannot be accessed while it is in the Self Refresh state. Note 3: To execute the HALT instruction after the Self Refresh Entry command, insert at least 10 bytes of NOP or other instructions between the instruction to set SDCMM to “101” and the HALT instruction. SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE Self-refresh entry Self-refresh exit Auto-refresh Figure 3.16.5 Timing of Self-Refresh Cycle 92CH21-385 2007-02-28 TMP92CH21 (4) SDRAM initialize This LSI can generate the following SDRAM initialize routine after introduction of power supply to SDRAM. The command is shown in Figure 3.16.6. 1. Precharge all commnad 2. Eight Auto Refresh commands 3. Mode Register set command The above commands are issued by setting SDCMM to “001”. While these commands are issued, the CPU operation (an instruction fetch, command execution) is halted. Before executing the initialization sequence, appropriate port settings must be made to enable the SDRAM control signals and address signals (A0 to A15). After the initialization sequence is completed, SDCMM is automatically cleared to “000”. Eight Auto Refresh commands SDCLK SDCKE SDUUDQM SDULDQM SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A10 A15 to A0 627 227 Precharge Auto -refresh All Auto -refresh Auto -refresh Auto -refresh Auto -refresh Mode Register set Figure 3.16.6 Timing of Initialization command 92CH21-386 2007-02-28 TMP92CH21 (5) Connection example Figure 3.14.7-Figure 3.14.10 shows an example of connections between the TMP92CH21 and SDRAM Table 3.16.3 Connection with SDRAM TMP92CH21 Pin Name 16 M 64 M 128 M 256 M 512 M Data Bus Width: 16 Bits SDRAM Pin Name Data Bus Width 32 Bits 16 M 64 M 128 M 64 M 128 M × 32 bits × 16 bits × 2 × 16 bits × 2 × 16 bits × 2 × 32 bits A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A6 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A7 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A8 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A9 A10 A10 A10 A10 A10 A10 A10 A10 A10 A10 A10 A10 A10 A11 BS A11 A11 A11 A11 BS BS A11 A11 A11 A11 BS0 A12 − BS0 BS0 A12 A12 − − BS0 BS0 BS0 BS0 BS1 A13 − BS1 BS1 BS0 BS0 − − BS1 BS1 BS1 BS1 − A14 − − − BS1 BS1 − − − − − − − A15 − − − − − − − − − − − − CS CS CS CS CS CS CS CS CS CS CS CS SDCS SDUUDQM − − − − − UDQM UDQM UDQM DQM3 SDULDQM − − − − − LDQM LDQM LDQM DQM2 SDLUDQM UDQM UDQM UDQM UDQM UDQM UDQM UDQM UDQM DQM1 SDLLDQM LDQM LDQM LDQM LDQM LDQM LDQM LDQM LDQM DQM0 RAS RAS RAS RAS RAS RAS RAS RAS RAS RAS RAS RAS SDRAS CAS CAS CAS CAS CAS CAS CAS CAS CAS CAS CAS CAS SDCAS SDWE WE WE WE WE WE WE WE WE WE WE WE WE SDCKE CKE CKE CKE CKE CKE CKE CKE CKE CKE CKE CKE CKE SDCLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK SDACR 00: 00: 01: 01: 10: 01: 01: 10: 01: TypeA TypeA TypeB TypeB TypeC TypeB TypeB TypeC TypeB : Command address pin of SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BS0 BS1 − − CS DQM3 DQM2 DQM1 DQM0 RAS CAS WE CKE CLK 01: TypeB TMP92CH21 SDCLK SDCKE A13 to A12 A11 to A0 D15 to D0 SDRAS SDCAS SDWE SDCS CLK CKE BS1 to BS0 A11 to A0 D15 to D0 RAS CAS WE CS SDLUDQM SDLLDQM UDQM LDQM 1 M word × 4 Banks × 16 bits Figure 3.16.7 Connection with SDRAM (4 M word × 16 bits) 92CH21-387 2007-02-28 TMP92CH21 TMP92CH21 SDCLK SDCKE A13 A12 A11 to A0 D15 to D0 D31 to D16 SDRAS SDCAS SDWE SDCS CLK CKE BS1 BS0 A11 to A0 D15 to D0 RAS CAS WE CS SDLUDQM SDLLDQM SDUUDQM SDULDQM UDQM LDQM CLK CKE BS1 BS0 A11 to A0 D15 to D0 RAS CAS WE CS UDQM LDQM Figure 3.16.8 Connection with SDRAM (1 M word × 16 bits × 2) TMP92CH21 SDCLK SDCKE A12 A11 A10 to A0 D31 to D0 SDRAS SDCAS SDWE SDCSL CLK CKE BS1 BS0 A10 to A0 D31 to D0 RAS CAS WE CS SDUUDQM SDULDQM SDLUDQM SDLLDQM DQM3 DQM2 DQM1 DQM0 512 K word × 4 banks × 32 bits Figure 3.16.9 Connection with SDRAM (512 K word × 32 bits) 1M word × 4 banks × 16 bits 1 M word × 4 banks × 16 bits 92CH21-388 2007-02-28 TMP92CH21 3.16.3 Limitations arising when using SDRAM Take care to note the following points when using SDRAMC. 1. WAIT access When using SDRAM, some limitation is added when accessing memory other than SDRAM. In WAIT-pin input setting of the Memory Controller, if the setting time is inserted as an external WAIT, set a time less than the Auto-Refresh cycle × 14 (AutoRefresh function controlled by SDRAM controller). Execution of SDRAM command before HALT instruction (SR (Self refresh)-Entry, Initialize, Mode-set) When a SDRAM controller command (SR-Entry, Initialize and Mode-set) is issued, several states are required for execution time after the SDCMM register is set. Therefore, when a HALT instruction is executed after the SDRAM command, please insert a NOP of more than 10 bytes or 10 other instructions before executing the HALT instruction. AR (Auto-Refresh) interval time When using SDRAM, set the system clock frequency to satisfy the minimum operation frequency for the SDRAM and minimum refresh cycle. In a system in which SDRAM is used and the clock is geared up and down,exercise care in AR cycle for SDRAM. When AR cycle is changed, set to disable by writing “0” to SDRCR. The AR cycle may also not correspond to the SDRAM A.C specification when stopping Auto-Refresh. Therefore, set Auto-Refresh cycle after adding 10 states to distibuted Auto-Refresh cycle. (Example of calculation) Condition: fSYS=12MHz, SDRAM specification of distributed Auto-Refresh interval time =4096times/64ms 64ms/ 4096times = 15.625us/1time = 187.5state/1time 187.5 − 10 = 177.5state/less than 1 time is needed → 156 state is needed 4. Self-Refresh ENTRY method In order to prevent a conflict between a Self-Refresh ENTRY command and an Auto-Refresh, please stop Auto-Refresh once. A) Disable Auto Refresh before writing Self Refresh ENTRY command. B) Enable Auto Refresh after writing Self Refresh ENTRY command. Because the above instruction should be executed continuously, a 16-bit instruction must be used as below. (Example of recommended settings) *DI LDW LD (SDRCR),0000010100000010B (SDRCR),0000---1B ; ; Disable AR → SR-ENTRY Enable AR 2. 3. Note : * When using SDRAM as a stack pointer, it is necessary to disable SDRAM access by, for example, a “DI” instruction. 92CH21-389 2007-02-28 TMP92CH21 5. Note when changing access mode If changing access mode from “full page read” to “1 word read”, execute the following program. This program must not be executed on the SDRAM. di ld ld ld ei a,(optional external memory address) (sdacr1),00001101b (sdcmm),0x04 ; Interrupt Disable (Added) ; Dummy read instruction (Added) ; Change to “1-word read” ; Execute MRS (mode register setting) ; Interrupt enable (Added) 92CH21-390 2007-02-28 TMP92CH21 6. “Auto Exit” problem when exiting from SDRAM Self-Refresh Mode The SDRAM specification may not be satisfied when using the Self-Refresh function together with CPU stand-by function or changing clock,. because when the CPU releases HALT mode, the Self-Refresh Auto Exit function automatically operates. The following figure shows an example of how to avoid this problem using S/W. (Control Outline) Gear-down or Change to Low clock fSYS 20MHz ｜ ｜ 32KHz CPU SR ENTRY Change Change to port CLK HALT Gear-up or Change to High clock Interrupt SR ENTRY HALT condition Change Change to port CLK SR EXIT Port condition SDRAM control pin General port setting SDRAM control pin SDRAM controller internal condition AR condition SR condition AR condition SR condition AR condition Auto EXIT SDRAM condition AR condition SR condition AR condition *The target ports to change are SDCKE pin and SDCS pin. *The method of Self-refresh Entry includes the condition 4). * SR : Self-refresh , AR : Auto-refresh 92CH21-391 2007-02-28 TMP92CH21 ; ********Sample program ********* LOOP1: LDB ANDB J A, (SDCMM) A, 00000111B NZ, LOOP1 ; ; ; Check the command register clear LD LD NOP×10 RES LD SET LD LD LD HALT NOP LOOP2: LDB ANDB J LDW LD (SDRCR), 0000010100000010B (SDRCR), 0000---1B ; ; ; AR stop → SR-ENTRY AR operation Wait for execution of self-refresh entry PJ7 (SDCKE)=Low PJ7=PORT P81 ( SDCS ) P81 = PORT fs Self-refresh Exit (Internal signal only) 7, (PJ) (PJFC), 0-------B 1, (P8) (P8FC), ------0-B (P8FC2), ------0-B (SYSCR1), 00001---B ; ; ; ; ; ; ; ; A, (SDCMM) A, 00000111B NZ, LOOP2 (SDRCR), 0000010100000010B (SDRCR), 0000----1B ; ; ; ; ; Check the command register clear AR stop → SR-ENTRY Enable auto-refresh NOP × 10 LD LD LD LD (SYSCR1), 00000---B (PJFC), 1-------B (P8FC2), ------1-B (SDCMM), 00000110B ; ; ; ; ; Wait for execution of self-refresh entry fc PJ7 = SDCKE P81 = SDCS Self-refresh Exit (command) 92CH21-392 2007-02-28 TMP92CH21 3.17 NAND-Flash Controller 3.17.1 Characteristics The NAND-Flash controller (NDFC) is provided with dedicated pins for connecting with NAND-Flash memory. The NDFC also has an ECC calculation function for error correction. Although the NDFC has two channels (channel 0, channel 1), all pins except for Chip Enable are shared between the two channels. Only the operation of channel 0 is explained here. The NDFC has the following features: 1) Controlled NAND-Flash interface by setting registers. 2) ECC calculating circuits. (for SCL-type) Note 1: The WP (Write Protect) pin of NAND Flash is not supported. If this function is needed, prepare it on an external circuit. Note 2: The two channels cannot be accessed simultaneously. It is necessary to switch between the two channels. 92CH21-393 2007-02-28 TMP92CH21 3.17.2 Block Diagram NAND-Flash Controller Channel 0 (NDFC0) Internal bus bus I/F Registers Register address NAND-Flash I/F timing control ND_CE* ND_ALE ND_CLE ND_RE* ND_WE* ND_RB* A Y B S NDCLE, NDALE, NDRE , NDWE , D7 to D0 ND0CE Host I/F timing control DATA_OUT [7:0] DATA_IN [7:0] D7 to D0, NDR/ B NAND-Flash Controller Channel 1 (NDFC1) ND1CE (Same as NDFC0 ) NDCR register D Q Figure 3.17.1 NAND-Flash Controller Block Diagram 92CH21-394 2007-02-28 TMP92CH21 3.17.3 Operation Description The NDFC accesses data on NAND Flash memory indirectly through its internal registers.It also contains the ECC calculating circuits. Please see 3.17.3.2 for details of the ECC. This section explains the operations for accessing the NAND Flash. Basically, set the command in ND0FMCR and then read or write to ND0FDTR. The read cycle for ND0FDTR is completed after the external read cycle for the NAND-Flash is finished. Likewise, the write cycle for ND0FDTR is completed after the external write cycle for the NAND-Flash is finished. 1) Initialize The initialize sequence is as follows. (1) ND0FSPR: Set the low pulse width. (2) ND0FIMR: Set 0x81 if interrupt is required. (Release interrupt mask) 2) Write The write sequence is as follows. (1) ND0FMCR: (2) Write 512 bytes ND0FMCR: ND0FDTR: ND0FMCR: ND0FDTR: ND0FMCR: ND0FDTR: (3) Read ECC data ND0FMCR: NDECCRD: First data: Second data: Third data: Fourth data: Fifth data: Sixth data: Set 0xDC for the ECC data read mode. Read 6 bytes ECC data. LPR [7:0] LPR [15:8] CPR [5:0], 2’b11 LPR [23:16] LPR [31:24] CPR [11:6], 2’b11 Set 0x9D for NDCLE signal enable and command mode. Set 0x80 for the serial data input command. Set 0x9E for NDALE signal enable and address mode. Write address. Set A [7:0], A [16:9], and A [24:17]. If it is required, set A [25]. Set 0xBC for the data mode. Write 512 bytes data. Set 0x7C for ECC data reset. 3.17.3.1 Accessing NAND-Flash Memory 92CH21-395 2007-02-28 TMP92CH21 (4) Write 16-byte redundant data ND0FMCR: ND0FDTR: D520: D521: D522: D525: D526: D527: (5) Run page program ND0FMCR: ND0FDTR: ND0FMCR: Set 0x9D for NDCLE signal enable and command mode. Set 0x10 for the page program command. Set 0x1C for NDALE signal disable. Set 0x9C for the data mode without ECC calculation. Write 16-byte redundant data. LPR [23:16] LPR [31:24] CPR [11:6], 2’b11 LPR [7:0] LPR [15:8] CPR [5:0], 2’b11 Wait several states (e.g., “NOP” × 10) ND0FSR: (6) Read status ND0FMCR: ND0FDTR: ND0FMCR: ND0FDTR: Set 0x1D for NDCLE signal and command mode. Set 0x70 for Status read command. Set 0x1C for NDCLE signal disable. Read the Status data from the NAND-Flash. Check BUSY flag. If it is 0, go to the next. If it is 1, wait until it becomes 0. (7) Repeat 1 to 6 for all other pages if required. 92CH21-396 2007-02-28 TMP92CH21 3) Read The read sequence is as follows. (1) ND0FMCR: (2) Read 512 bytes ND0FMCR: ND0FDTR: ND0FMCR: ND0FDTR: ND0FMCR: Set 0x1D for NDCLE signal enable and command mode. Set 0x00 for the read command. Set 0x1E for NDALE signal enable and address mode. Set A [7:0], A [16:9], and A [24:17]. If it is required, set A [25]. Set 0x1C for NDALE signal disable. Set 0x7C for ECC data reset. Wait several states (e.g., “NOP” × 10) ND0FSR: ND0FMCR: ND0FDTR: ND0FMCR: ND0FDTR: (3) Read ECC data ND0FMCR: NDECCRD: First data: Second data: Third data: Fourth data: Fifth data: Sixth data: (4) Software routine: Compare ECC data and redundant data, run the error routine if error is generated. (5) Read other pages ND0FMCR: ND0FSR: Set 0x1C. Check BUSY flag. If it is 0, go to the next. If it is 1, wait until it becomes 0. Set 0x5C for the ECC data read mode. Read 6-byte ECC data. LPR [7:0] LPR [15:8] CPR [5:0], 2’b11 LPR [23:16] LPR [31:24] CPR [11:6], 2’b11 Check BUSY flag. If it is 0, go to the next. If it is 1, wait until it becomes 0. Set 0x3C for the data mode with ECC calculation. Read 512-byte data. Set 0x1C for the data mode without ECC calculation. Read 16-byte redundant data. 92CH21-397 2007-02-28 TMP92CH21 4) ID read The ID read sequence is as follows. (1) ND0FMCR: (2) ND0FDTR: (3) ND0FMCR: (4) ND0FDTR: (5) ND0FMCR: (6) ND0FDTR: (7) ND0FDTR: Set 0x1D for NDCLE signal enable and command mode. Set 0x90 for the ID Read command. Set 0x1E for NDALE signal enable and the address mode. Set 0x00. Set 0x1C for the data mode without ECC calculation. Read Maker code. Read Device code. 3.17.3.2 ECC Control The NDFC contains the ECC calculating circuits. The circuits are controlled by ND0FMCR. This circuit executes ECC data calculation. However, ECC comparison and error correction is not executed. This must be executed using software. The calculated ECC data can be read from the NDECCRD register when ND0FMCR is 0xD0 (write mode) or 0x50 (read mode). This is 6-byte data, and six NDECCRD read operations are required. The order of the data is as follows. First data: Second data: Third data: Fourth data: Fifth data: Sixth data: LPR [7:0] LPR [15:8] CPR [5:0], 2’b11 LPR [23:16] LPR [31:24] CPR [11:6], 2’b11 92CH21-398 2007-02-28 TMP92CH21 3.17.4 Registers Table 3.17.1 NAND-Flash Control Registers for Channel 0 Address 1D00H (1D00H to 1EFFH) 1CC4H 1CC8H 1CCCH 1CD0H 1CD4H 1CD8H Register ND0FDTR ND0FMCR ND0FSR ND0FISR ND0FIMR ND0FSPR ND0FRSTR Register Name NAND-Flash data transfer register NAND-Flash ECC-code read register NAND-Flash mode control register NAND-Flash status register NAND-Flash interrupt status register NAND-Flash interrupt mask register NAND-Flash strobe pulse width register NAND-Flash reset register 1CB0H (1CB0H to 1CB5H) ND0ECCRD Table 3.17.2 NAND-Flash Control Registers for Channel 1 Address 1D00H (1D00H to 1EFFH) 1CE4H 1CE8H 1CECH 1CF0H 1CF4H 1CF8H Register ND1FDTR ND1FMCR ND1FSR ND1FISR ND1FIMR ND1FSPR ND1FRSTR Register Name NAND-Flash data transfer register NAND-Flash ECC-code read register NAND-Flash mode control register NAND-Flash status register NAND-Flash interrupt status register NAND-Flash interrupt mask register NAND-Flash strobe pulse width register NAND-Flash reset register 1CB0H (1CB0H to 1CB5H) ND1ECCRD Table 3.17.3 NAND-Flash Control Registers Address 01C0H Register NDCR Register Name NAND-Flash control register 92CH21-399 2007-02-28 TMP92CH21 3.17.4.1 NAND-Flash Data Transfer Register (ND0FDTR and ND1FDTR) 7 DATA R/W − : Type : Default 0 Bit (s) 7:0 Mnemonic DATA Field Name DATA Description NAND-Flash data. Read: Read the data that was read from the NAND-Flash. Write: Write data to the NAND-Flash. Note 1: This register has a 512-address window from 1D00H to 1EFFH since a NAND-Flash page size is either 256 or 512 bytes. When the CPU reads from or writes to the NAND-Flash , and if the block transfer instruction (“LDIR” instruction) is used, the following restriction applies to the 900/H1 CPU. [Restriction for using the block transfer instruction] 1) The source address for “LDIR” instruction should be set to (1F00H – read (or write) byte number) Example 1) In case of 512-byte read ld ld ld ldir ld ld ld ldir Note 2: bc, 512 xix, 2000H xiy, 1D00H (xix + ), (xiy + ) bc, 16 xix, 2000H xiy, 1EF0H (xix + ), (xiy + ) ; 512 bytes ; dst = 2000H ; src = (1F00H − 512) = 1D00H ; Block transfer instruction ; 16 bytes ; dst = 2000H ; src = (1F00H − 16) = 1EF0H ; Block transfer instruction Example 2) In case of 16-byte read Both ND0FDTR and ND1FDTR are assigned to the same address. The NDCR register determines which channel is accessed. Figure 3.17.2 NAND-Flash Data Transfer Register (ND0FDTR and ND1FDTR) 92CH21-400 2007-02-28 TMP92CH21 3.17.4.2 NAND-Flash ECC-code Read Register (ND0ECCRD and ND1ECCRD) 7 ECC-code R − : Type : Default 0 Bit (s) 7:0 Mnemonic ECC-code Note 1: Field Name ECC-code Read calculated ECC data. Description Both ND0ECCRD and ND1ECCRD are assigned to the same address. The NDCR register determines which channel is accessed. Figure 3.17.3 NAND-Flash ECC-code Read Register (ND0ECCRD and ND1ECCRD) 92CH21-401 2007-02-28 TMP92CH21 3.17.4.3 NAND-Flash Mode Control Register (ND0FMCR and ND1FMCR) 7 WE R/W 0 6 5 4 CE R/W 0 3 5 1 0 CLE R/W 0 : Type : Default ECC1 ECC0 R/W 0 R/W 0 PCNT1 PCNT0 ALE R/W 0 R/W 0 R/W 0 Bits 7 Mnemonic WE Field Name Write enable Write enable (Default: 0) Description This bit enables the data write operation. When writing the data to the NAND-Flash, set this bit to “1”. When writing command or address, this bit need not be set to “1”. 0: Disable write operation 1: Enable write operation 6 ECC1 ECC control ECC control (Default: 00) Control the ECC calculating circuits with (bit4) register. 11 (at = X): Reset ECC circuits 00 (at = 1): ECC circuits are disabled. 5 ECC0 01 (at = 1): ECC circuits are enabled. 10 (at = 1): Read ECC data calculated by NDFC 10 (at = 0): Read ID data 4 CE Chip enable Chip enable (Default: 0) Enable NAND-Flash access. Set “1” to this bit when accessing the NAND-Flash. 0: Disable ( NDCE is High.) 1: Enable ( NDCE is Low.) 3 2 1 PCNT1 PCNT0 ALE Power control Address latch enable Power control (Default: 00) Always write “11” Address latch enable (Default: 0) This bit specifies the value of the NDALE signal. 0: Low 1: High 0 CLE Command latch enable Command latch enable (Default: 0) This bit specifies the value of the NDCLE signal. 0: Low 1: High Figure 3.17.4 NAND-Flash Mode Control Register (ND0FMCR and ND1FMCR) 92CH21-402 2007-02-28 TMP92CH21 3.17.4.4 NAND-Flash Status Register (ND0FSR and ND1FSR) 7 BUSY R − : Type : Default 6 0 Bits 7 Mnemonic BUSY Field Name BUSY BUSY (Default: Undefined) Description This bit shows the status of the NAND-Flash. 0: Ready 1: Busy 6:0 − − Reserved Note: A noise-filter for some states is built into the NDFC, so when the NDR/ B pin changes, a flag is not renewed at the same time. Therefore, insert several delays (e.g., “NOP” instruction × 10) using software before starting this flag check. Read command Address input Delay time Sensing flag NDWE pin NDCLE pin NDALE pin NDR/ B pin flag Figure 3.17.5 NAND-Flash Status Register (ND0FSR and ND1FSR) 92CH21-403 2007-02-28 TMP92CH21 3.17.4.5 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR) 7 6 5 4 3 2 1 0 RDY : Type : Default Bits 7:1 0 Mnemonic − RDY Field Name − Ready Reserved Ready (Default: 0) Description When NDR/ B signal changes from low (BUSY) to High ( READY) and NDFIMR is “1”, this bit is set to “1”. By writing “1”, this bit is cleared to 0. Read: 0: None 1: Change NDR/ B signal from BUSY to READY. Write: 0: No change 1: Clear to “0” Figure 3.17.6 NAND-Flash Interrupt Status Register (ND0FISR and ND1FISR) 3.17.4.6 NAND-Flash Interrupt Mask Register (ND0FIMR and ND1FIMR) 7 INTEN R/W 0 6 4 0 3 2 1 0 MRDY R/W 0 : Type : Default Bits 7 Mnemonic INTEN Field Name Interrupt enable Interrupt enable (Default: 0) Description When and are set “1” and NDFISR becomes “1”, INTNDFC occurs. 0: Disable 1: Enable 6:1 0 − MRDY − Mask RDY interrupt Reserved Mask RDY interrupt (Default: 0) This bit masks the NDFISR. If is “1” and NDR/ B signal changes from Low to High, NDFISR is set to “1”. 0: Disable to set NDFISR 1: Enable to set NDFISR Figure 3.17.7 NAND-Flash Interrupt Mask Register (ND0FIMR and ND1FIMR) 92CH21-404 2007-02-28 TMP92CH21 3.17.4.7 NAND-Flash Strobe Pulse Width Register (ND0FSPR and ND1FSPR) 7 6 5 4 3 2 SPW R/W 0000 : Type : Default 1 0 Bits 7:4 3:0 Mnemonic − SPW Field Name − Strobe pulse width Reserved Strobe pulse width (Default: 0000) Description These bits set the Low pulse width of the NDRE and NDWE signals. The Low pulse width is ((value set to SPW) +1 )× fSYS clock Figure 3.17.8 NAND-Flash Strobe Pulse Width Register (ND0FSPR and ND1FSPR) 92CH21-405 2007-02-28 TMP92CH21 3.17.4.8 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR) 7 6 5 4 3 2 1 0 RST R/W 0 : Type : Default Bits 7:1 0 Mnemonic − RST Field Name − Reset Reserved Reset (Default: 0) Description By setting this bit, reset the NDFC (except NDCR register). By reset, this bit is automatically cleared to “0”. 0: Don’t care 1: Reset Note: After writing register, several waits are required (about 10 states) before accessing the NDFC. Figure 3.17.9 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR) 3.17.4.9 NAND-Flash Control Register (NDCR) 7 NDCR (01C0H) Bit symbol Read/Write After reset Function CHSEL R/W 0 0: Channel 0 1: Channel 1 6 5 4 3 2 1 0 92CH21-406 2007-02-28 TMP92CH21 3.17.5 Timing Diagrams 3.17.5.1 Command and Address Cycle ND0FMCR = 0 ND0FMCR = 0 ND0FMCR = 1 ND0FMCR = 1 ND0FMCR = 1 Figure 3.17.10 Command and Address Cycle D7 to D0 NDCLE NDALE NDR/B NDWE NDCE NDRE 92CH21-407 2007-02-28 TMP92CH21 3.17.5.2 Data Read Cycle Figure 3.17.11 shows a timing chart example for a Data Read cycle from the NAND-Flash at ND0FSPR = 02H. Program memory read (1 wait) FF1238H NAND-Flash read 001D00H Program memory read (1 wait) FF1234H NDCE NDCLE NDRE CS2 A23 to A0 NDWE Figure 3.17.11 Data Read Cycle Example (ND0FSPR = 02H) 92CH21-408 2007-02-28 D31 to D0 SDCLK NDALE NDR/B SRWR RD IN (Program) IN (NAND-Flash) IN (Program) TMP92CH21 3.17.5.3 Data Write Cycle Figure 3.17.12 shows a timing chart example for a Data Write cycle to the NAND-Flash at ND0FSPR = 02H. Program memory read (1 wait) FF1238H NAND-Flash write Program memory read (1 wait) FF1234H NDCE NDRE CS2 A23 to A0 NDWE Figure 3.17.12 Data Write Cycle (ND0FSPR = 02H) 92CH21-409 2007-02-28 D31 to D0 SDCLK NDCLE NDALE NDR/B SRWR RD IN (Program) OUT (NAND-Flash) 001D00H IN (Program) TMP92CH21 3.17.6 Example of NAND-Flash Use TMP92CH21 100 kΩ NDCLE NDALE NDRE NDWE NAND-Flash 0 CLE ALE RE WE NAND-Flash 1 CLE ALE RE WE 2 kΩ NDR/ B D [7:0] ND0CE ND1CE R/B (Open drain) I/O [7:0] CE WP R/B (Open drain) I/O [7:0] CE WP External circuits for write protect Note 1: By reset, both NDRE and NDWE pins become input ports (Port 71 and Port 72) And so require pull-up resistors. Note 2: Use the NAND-Flash memory and board capacitance to set the correct value for the NDR/ B pin pull-up resistor . 2 kΩ is a typical value. Note 3: The NAND-Flash WP (write protect) pin is not supported by the TMP92CH21. It must be provided by an external circuit if required. Figure 3.17.13 Example of NAND-Flash Connection 92CH21-410 2007-02-28 TMP92CH21 3.18 16-Bit Timer/Event Counters (TMRB0) The TMP92CH21 incorporates one multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: • • • 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) mode The timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (one of them with a double buffer structure), a 16-bit capture register, two comparators, a capture input controller, a timer flip-flop and a control circuit. The timer/event counter is controlled by an 11-byte control SFR. This chapter includes the following sections: 3.18.1 Block Diagrams 3.18.2 Operation of Each Block 3.18.3 SFRs 3.18.4 Operation in Each Mode (1) 16-bit interval timer mode (2) 16-bit programmable pulse generation (PPG) output mode Table 3.18.1 Pins and SFR of TMRB0 Channel Spec. External pins External clock/capture trigger input pins Timer flip-flop output pins Timer run register Timer mode register Timer flip-flop control register TMRB0 None TB0OUT0 (also used as PC2) TB0RUN (1180H) TB0MOD (1182H) TB0FFCR (1183H) TB0RG0L (1188H) TB0RG0H (1189H) TB0RG1L (118AH) TB0RG1H (118BH) TB0CP0L (118CH) TB0CP0H (118DH) TB0CP1L (118EH) TB0CP1H (118FH) SFR (Address) Timer register Capture register 92CH21-411 2007-02-28 Interrupt output 3.18.1 Internal data bus Internal data bus INTTB00 INTTB01 Prescaler clock: φT0 TB0RUN Capture register 0 TB0CP0H/L Timer flip-flop Timer TB0RUN flip-flop control Slelector Count clock 16-bit up counter (UC10) TB0MOD TB0FF0 Caputure register 1 TB0CP1H/L φT16 TB0MOD 2 4 8 16 32 Run/ clear φT1 φT4 Timer flip-flop output Block Diagrams TA1OUT (from TMRA01) Capture, external interrupt input control TB0OUT0 TB1MOD φT1 φT4 φT16 Figure 3.18.1 Block Diagram of TMRB0 TB0MOD 16-bit comparator (CP10) Match detection 16-bit comparator (CP11) 16-bit timer register TB0RG0H/L 16-bit time register TB0RG1H/L Register buffer 10 Internal data bus Intenal data bus 92CH21-412 Overflow interrupt INTTBOF0 Match detection TB0RUN TMP92CH21 2007-02-28 TMP92CH21 3.18.2 Operation of Each Block (1) Prescaler The 5-bit prescaler generates the source clock for timer 0. The prescaler clock (φT0) is a divided clock (divided by 8) from the fFPH. This prescaler can be started or stopped using TB0RUN. Counting starts when is set to 1; the prescaler is cleared to 0 and stops operation when is cleared to 0. Table 3.18.2 Prescaler Clock Resolution System clock selection SYSCR1 1 (fs) Clock gear selection SYSCR1 − 000 (1/1) 001 (1/2) 0 (fc) 010 (1/4) 011 (1/8) 100 (1/16) XXX: Don't care 1/8 Timer counter input clock TMRB prescaler − TB0MOD φT1(1/2) fs/16 fc/16 fc/32 fc/64 fc/128 fc/256 φT4(1/8) fs/64 fc/64 fc/128 fc/256 fc/512 fc/1024 φT16(1/32) fs/256 fc/256 fc/512 fc/1024 fc/2048 fc/4096 (2) Up counter (UC10) UC10 is a 16-bit binary counter which counts up pulses input from the clock specified by TB0MOD. Any one of the prescaler internal clocks φT1, φT4 and φT16 can be selected as the input clock. Counting or stopping and clearing of the counter is controlled by TB0RUN. When clearing is enabled, the up counter UC10 will be cleared to 0 each time its value matches the value in the timer register TB0RG1H/L. If clearing is disabled, the counter operates as a free-running counter. Clearing can be enabled or disabled using TB0MOD. A timer overflow interrupt (INTTBOF0) is generated when UC10 overflow occurs. 92CH21-413 2007-02-28 TMP92CH21 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both Upper and Lower timer registers is always needed. For example, either using a 2-byte data transfer instruction or using a 1-byte data transfer instruction twice for the lower 8 bits and upper 8 bits in order. The TB0RG0H/L timer register has a double-buffer structure, which is paired with a register buffer. The value set in TB0RUN determines whether the double-buffer structure is enabled or disabled: it is disabled when = 0, and enabled when = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when the values in the up counter (UC10) and the timer register TB0RG1H/L match. After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to be used after a reset, data should be written to it beforehand. On a reset is initialized to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set to 1, then write data to the register buffer as shown below. TB0RG0H/L and the register buffer both have the same memory addresses (001188H and 001189H) allocated to them. If = 0, the value is written to both the timer register and the register buffer. If = 1, the value is written to the register buffer only. The addresses of the timer registers are as follows: TMRB0 TB0RG0H/L Upper 8 bits Lower 8 bits (TB0RG0H) (TB0RG0L) 001189H 001188H TB0RG1H/L Upper 8 bits Lower 8 bits (TB0RG1H) (TB0RG1L) 00118BH 00118AH The timer registers are write-only registers and thus cannot be read. 92CH21-414 2007-02-28 TMP92CH21 (4) Capture registers (TB0CP0H/L and TB0CP1H/L) These 16-bit registers are used to latch the values in the up counters. All 16 bits of data in the capture registers should be read. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. The addresses of the capture registers are as follows: TMRB0 TB0CP0H/L Upper 8 bits Lower 8 bits (TB0CPH) (TB0CP0L) 00118DH 00118CH TB0CP1H/L Upper 8 bits Lower 8 bits (TB0CP1H) (TB0CP1L) 00118FH 00118EH The capture registers are read-only registers and thus cannot be written to. (5) Capture input control This circuit controls the timing to latch the value of the up counter UC10 into TB0CP0H/L and TB0CP1H/L. The value in the up counter can be loaded into a capture register by software. Whenever 0 is programmed to TB0MOD, the current value in the up counter is loaded into capture register TB0CP0H/L. It is necessary to keep the prescaler in run mode (i.e., TB0RUN must be held at a value of 1). (6) Comparators (CP10 and CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). (7) Timer flip-flops (TB0FF0) These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers. Inversion can be enabled and disabled for each element using TB0FFCR. After a reset the value of TB0FF0 is undefined. If “00” is programmed to TB0FFCR , TB0FF0 will be inverted. If “01” is programmed to the capture registers, the value of TB0FF0 will be set to “1”. If “10” is programmed to the capture registers, the value of TB0FF0 will be cleared to “0”. The values of TB0FF0 can be output via the timer output pin TB0OUT0 (which is shared with PC6). Timer output should be specified using the port B function register. 92CH21-415 2007-02-28 TMP92CH21 3.18.3 SFRs TMRB0 Run Register 7 TB0RUN (1180H) Bit symbol Read/Write After reset Function TB0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 − R/W 0 Always write “0” 5 4 3 I2TB0 R/W 0 IDLE2 0: Stop 1: Operate 2 TB0PRUN R/W 0 TMRB0 Prescaler 0: Stop and clear 1: Run (Count up) 1 0 TB0RUN R/W 0 Up counter UC10 Count operation 0 1 Stop and clear Count Note: 1, 4 and 5 of TB0RUN are read as undefined values. Figure 3.18.2 The Registers for TMRB 92CH21-416 2007-02-28 TMP92CH21 TMRB0 Mode Register 7 TB0MOD (1182H) Read-modify -write instruction is prohibited. Bit symbol Read/Write After reset Function 0 Always write “0” − R/W 0 6 − 5 TB0CP0I W* 1 Execute software capture 4 TB0CPM1 0 Capture timing 00: Disable 01: Reserved 3 TB0CPM0 0 2 TB0CLE R/W 0 Control up counter 0: Disable clearing 1: Enable clearing 1 TB0CLK1 0 00: Reserved 01: φT1 10: φT4 11: φT16 0 TB0CLK0 0 TMRB0 source clock 0: Software 10: Reserved capture 11: TA1OUT↑ 1: TA1OUT↓ Undefined TMRB0 source clock 00 01 10 11 Reserved φT1 φT4 φT16 Up counter clear control 0 1 Disable Enable clearing on match with TB0RG1H/L Capture/interrupt timing 00 01 10 11 Disable Reserved Reserved Capture to TB0CP0H/L at rising edge of TA1OUT Capture to TB0CP1H/L at falling edge of TA1OUT Software capture 0 1 The value in the up counter is captured to TB0CP0H/L. Undefined Figure 3.18.3 The Registers for TMRB0 92CH21-417 2007-02-28 TMP92CH21 TMRB0 Flip-Flop Control Register 7 TB0FFCR (1183H) Bit symbol Read/Write After reset Function Read-modify -write instruction is prohibited. 1 − W* 1 0 0: Disable trigger 1: Enable trigger Invert when the UC value is loaded into TB0CP1H/L. Invert when the UC value is loaded into TB0CP0H/L. Invert when the UC value matches the value in TB0RG1H/L. Invert when the UC value matches the value in TB0RG0H/L. 6 − 5 TB0C1T1 4 TB0C0T1 0 R/W 3 TB0E1T1 0 2 TB0E0T1 0 1 TB0FF0C1 1 Control TB0FF0 00: Invert 01: Set 10: Clear 11: Don’t care W* 0 TB0FF0C0 1 Always write “11”. TB0FF0 inversion trigger * Always read as 11. Timer flip-flop control (TB0FF0) 00 01 10 11 Invert Set to 1 Clear to 0 Don’t care Inverted when the UC10 value matches the value in TB0RG0H/L. 0 1 Disable trigger Enable trigger Inverted when the UC10 value matches the value in TB0RG1H/L. 0 1 Disable trigger Enable trigger Inverted when the UC10 value is loaded into TB0CP0. 0 1 Disable trigger Enable trigger Inverted when the UC10 value is loaded into TB0CP1H/L. 0 1 Disable trigger Enable trigger Figure 3.18.4 The Registers for TMRB 92CH21-418 2007-02-28 TMP92CH21 TMRB0 register 7 TB0RG0L (1188H) bit Symbol Read/Write After reset TB0RG0H (1189H) bit Symbol Read/Write After reset TB0RG1L (118AH) bit Symbol Read/Write After reset TB0RG1H (118BH) bit Symbol Read/Write After reset TB0CP0L (118CH) bit Symbol Read/Write After reset TB0CP0H (118DH) bit Symbol Read/Write After reset TB0CP1L (118EH) bit Symbol Read/Write After reset TB0CP1H (118FH) bit Symbol Read/Write After reset 6 5 4 － W Undefined － W Undefined － W Undefined － W Undefined － W Undefined － W Undefined － W Undefined － W Undefined 3 2 1 0 Note: All registers are prohibited to execute read-modify-write instruction. Figure 3.18.5 The Registers for TMRB 92CH21-419 2007-02-28 TMP92CH21 3.18.4 Operation in Each Mode (1) 16-bit interval timer mode Generating interrupts at fixed intervals. In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. 7 TB0RUN INTETB01 TB0FFCR TB0MOD TB0RG1 TB0RUN ← 0 ←X ← ← ← ← 1 0 * * 0 6 0 1 1 0 * * 0 5 X 0 0 1 * * X 4 X 0 0 0 * * X 3 − X 0 0 * * − 2 0 0 0 1 * * 1 1 X 0 1 * * * X 0 0 0 1 * * * 1 Stop TMRB0. Enable INTTB01 and set interrupt level 4. Disable INTTB00. Disable the trigger. Select internal clock for input and disable the capture function. (** = 01, 10, 11) Set the interval time (16 bits). Start TMRB0. X: Don't care, −: No change (2) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and is output to TB0OUT0. In this mode the following conditions must be satisfied. (Value set in TB0RG0H/L) < (Value set in TB0RG1H/L) Match with TB0RG0H/L (INTTB00 inerrupt) Match with TB0RG1H/L (INTTB01 interrupt) TB0OUT0 pin Figure 3.18.6 Programmable Pulse Generation (PPG) Output Waveforms When the TB0RG0H/L double buffer is enabled in this mode, the value of register buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature facilitates the handling of low duty waves. Match with TB0RG0H/L Up counter = Q1 Match with TB0RG1H/L Shift into TB0RG1H/L TB0RG0H/L (Value to be compared) Register buffer Q1 Q2 Q2 Q3 Write TB0RG0H/L Up counter = Q2 Figure 3.18.7 Operation of Register Buffer 92CH21-420 2007-02-28 TMP92CH21 The following block diagram illustrates this mode. TB0RUN TB0OUT0 (PPG output) φT1 φT4 φT16 Selector 16-bit up counter UC10 Clear F/F (TB0FF0) 16-bit comparator Match 16-bit comparator Selector TB0RG0H/L TB0RG0-WR TB0RUN Register buffer 10 TB0RG1H/L Internal data bus Figure 3.18.8 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: 7 TB0RUN TB0RG0H/L TB0RG1H/L TB0RUN TB0FFCR TB0MOD PCCR PCFC TB0RUN ← ← ← ← ← ← ← ← ← 0 * * * * 1 1 0 − − 1 6 0 * * * * 0 1 0 1 1 0 5 X * * * * X 0 1 X X X 4 X * * * * X 0 0 X X X 3 − * * * * − 1 0 − − − 2 0 * * * * 0 1 1 − − 1 1 X * * * * X 1 * − − X 0 0 * * * * 0 0 * − − 1 Disable the TB0RG0H/L double buffer and stop TMRB0. Set the duty ratio (16 bits). Set the frequency (16 bits). Enable the TB0RG0H/L double buffer. (The duty and frequency are changed on an INTTB01 interrupt.) Set the mode to invert TB0FF0 at the match with TB0RG0H/L/TB0RG1H/L. Set TB0FF0 to 0. Select the Prescaler output clock as the input clock and disable the capture function. Set PC6 to function as TB0OUT0. Start TMRB0. (** = 01, 10, 11) X: Don't care, −: No change 92CH21-421 2007-02-28 TMP92CH21 3.19 Touch Screen Interface (TSI) The TMP92CH21 has an interface for a 4-terminal resistor network touch screen. This interface supports two procedures: an X/Y position measurement and touch detection. Each procedure is executed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter. 3.19.1 Touch Screen Interface Module Internal/External Connection TMP92CH21 Y− MY X+ Touch screen X− MX PY Y+ PX External capacitors Figure 3.19.1 External Connection of TSI AVCC Touch screen control PXEN AVSS SPY SPX Dec. PYEN MXEN INT4 PTST Internal data bus P97 (PY) P96/INT4 (PX) PXD (typ.200 kΩ) PG3/AN3 (MY) PG2/AN2 (MX) SMX VREFH SM Y MYEN TSI7 AD converter AN3 AN2 AVCC AVSS VREFH VREFL VREFL Figure 3.19.2 Internal Block Diagram of TSI 92CH21-422 2007-02-28 TMP92CH21 3.19.2 Touch Screen Interface (TSI) Control Register TSI Control Register 7 TSICR0 (01F0H) Bit symbol Read/Write After reset Function TSI7 R/W 0 0: Disable 1: Enable 6 5 PTST R 0 Detection condition 0: no touch 1: touch 4 TWIEN R/W 0 INT4 interrupt control 0: Disable 1: Enable SPY 3 PYEN R/W 0 SPX 0 : OFF 1 : ON 2 PXEN R/W 0 SMY 0 : OFF 1 : ON 1 MYEN R/W 0 SMX 0 : OFF 1 : ON 0 MXEN R/W 0 0 : OFF 1 : ON PXD (Internal Pull-down resistance) ON/OFF setting 0 OFF ON 1 OFF OFF 0 1 Debounce Time Setting Register 7 TSICR1 (01F1H) Bit symbol Read/Write After reset Function DBC7 R/W 0 0: Disable 1: Enable 6 DB1024 R/W 0 1024 5 DB256 R/W 0 256 4 DB64 R/W 0 64 3 DB8 R/W 0 8 2 DB4 R/W 0 4 1 DB2 R/W 0 2 0 DB1 R/W 0 1 Debounce time is set by the formula “(N × 64 − 16)/fSYS”. “N” is the number of bits between bit6 and bit0 which are set to “1”. Note2) Note1: Since an internal clock is used for the debounce circuit, when IDLE1, STOP mode, the de-bounce circuit don’t operate and also interrupt which through this circuit is not generated. When IDLE1, STOP mode, set this circuit to disable (Write “0” to TSICR1) before entering HALT state. Note2: Ex: TSICR1=95H →N = 64 + 4 + 1 = 69 92CH21-423 2007-02-28 TMP92CH21 3.19.3 Touch Detection Procedure The Touch detection procedure shows procedure until a pen is touched by the screen and it is detected. By touching, TSI generates interrupt (INT4) and this procedure terminates. After an X/Y position measuring procedure is terminated, return to this procedure and wait for the next touch. When the waiting state, make ON only the SPY switch ON and OFF the other 3 switches (SMY, SPX and SMX). The pull-down resistor that is connected to the P96/INT4/PX pin is ON when the SPX switch is OFF. During this waiting state, P96/INT4/PX pin’s level is L because the internal Pull-down resistors (PXD) between the X and Y directions in the touch screen are not connected and INT4 is not generated. When the pen touches the screen, P96/INT4/PX pin’s level is H because the internal resistors between the X and Y directions in the touch screen are connected and INT4 is generated. In order to avoid the generation of several interrupts from one touch, a debounce circuit is used, as below. This can ignore the pulse under the time which is set to TSICR1 register. The circuit detects the rising of signal, counts-up the time of the counter which is set, after count, receive the signal internal. During counting, when the signal is set to Low, counter is cleared. And the state become to state of waiting a rising edge. TSICR1 TSICR0, IIMC, P9FC Enables INT4 and selects the Rising edge or Falling edge of INT4 P96/INT4/PX pin Debounce circuit INT4 F/F TSICR0 Figure 3.19.3 Block Diagram of Debounce Circuit 92CH21-424 2007-02-28 TMP92CH21 Reset counter for debounce time Start counter for debounce time Debounce Debounce time time INT4 Debounce time INT4 is generated by matching counter and specified debounce time. After pen is released, INT4 can be issued again. IINT4 is not generated by matching counter and specified debounce period because it is an edge-type interrupt. Figure 3.19.4 Timing Diagram of Debounce Circuit 92CH21-425 2007-02-28 TMP92CH21 3.19.4 X/Y Position Measuring Procedure During the INT4 routine, execute an X/Y position measuring procedure as below. Make both the SPX and SMX switches ON, and the SPY and SMY switches OFF. With this setting, an analog voltage which shows the X position will be input to the PG3/MY/AN3 pin. The X position can be measured by converting this voltage to digital code using the AD converter. Next, make both the SPY and SMY switches ON and the SPX and SMX switches OFF. With this setting, an analog voltage which shows the Y position will be input to the PG2/MX/AN2 pin. The Y position can be measured by converting this voltage to digital code using the AD converter. The above analog voltage which is inputted to AN3 or AN2 pin can be calculated as follows. It is the ratio between the resistance value in the TMP92CH21F and the resistance value in the touch screen as shown in Figure 3.19.5. Therefore, if the pen touches an area on the touch screen, the analog voltage will be neither 3.3 V nor 0.0 V. Please remember to take into consideration the variation in the rate of resistance. It is also recommended that an average taken from several AD conversions be adopted as the correct code. [Formula to calculate analog voltage (E1) to AN2 or AN3 pin] SPY (SPX) ON resistor: Rpy (Rpx) 20 Ω (typ.) Touch screen resistor: Rty (Rtx) The value depends on the touch screen. SMY (SMX) ON resistor: Rmy (Rmx) 20 Ω (typ.) AVCC = 3.3 V E1 = ((R2 + Rmy)/(Rpy + Rty + Rmy)) × AVCC [V] Example: AN2 (AN3) pin R2 R1 Touch point Note 1: Note 2: When AVCC = 3.3 V, Rpy = Rmy = 20 Ω, R1 = 400 Ω and R2 = 100 Ω E1 = ((100 + 20)/(20 + 400 + 100 + 20)) × 3.3 = 0.733 V An X position can be calculated in the same way though the above formula is for Y position. Rty = R1 + R2. Figure 3.19.5 Calculation Analog Voltage 92CH21-426 2007-02-28 TMP92CH21 3.19.5 Flow Chart for TSI (2) X/Y position measurement procedure INT4 routine: TSICR0 ← 98H TSICR1 ← XXH (Voluntary) ･TSICR0 ← 85H ･AD conversion for AN3 ･Store the result (1) Touch detection procedure Main routine: Execute main routine ･TSICR0 ← 8AH ･AD conversion for AN2 ･Store the result Execute an operation by using X/Y position Yes Still touched ? TSICR0 = 1? No Return to main routine Figure 3.19.6 Flow Chart for TSI 92CH21-427 2007-02-28 TMP92CH21 3.20 I2S (Inter-IC Sound) An I2S format compatible serial output circuit is built-in. This product can be used in digital audio system applications by connecting LSI for sound generation (e.g., a DA converter). This circuit has both I2S mode and general SIO mode. But both modes have only clock output and data transmitting functions. Figure 3.20.1 shows an outline for each mode. Table 3.20.1 Outline for Each Mode I2S mode 1) Format I S-format compatible (Only master and transmitting) 2) Used pin 1. I2SCKO (Clock output) 2. I2SDO (Clock output) 3. I2SWS (Word select output) 3) WS frequency 4) Baud rate (at fc = 40 MHz) 5) Transmittion buffer 6) Direction of data 7) Data length 8) Edge of clock 9) Interrupt Selectable either fs/4 or TA1OUT (TMRA1 output) − 2 SIO mode General (Only master and transmitting) 1. I2SCKO (Clock output) 2. I2SDO (Data output) Selectable either 20, 10, 5, or 2.5 Mbps 16 bytes × 2 channels (Right, left) 32 bytes Selectable either MSB first or LSB first Selectable either 8 bits or 16 bits Selectable either rising edge or falling edge INTI2S (FIFO empty interrupt) 92CH21-428 2007-02-28 TMP92CH21 3.20.1 Block Diagram fSYS Prescaler 248 Selector I2SCKO control I2SCKO fS TA1OUT ÷4 Selector I2SWS control I2SWS I2SBUFR 0 1 7 Shifter Data 16 bits 16-byte FIFO (Right) (2 bytes × 8) selector, FIFO control 0 1 7 Write pointer Read pointer Internal data bus I2SBUFL interrupt control I2SDO INTI2S 16 bits 16-byte FIFO (Left) (2 bytes × 8) Write pointer Read pointer FIFO control 16 bits I2SCTL0 2 Figure 3.20.1 I S Block Diagram 92CH21-429 2007-02-28 TMP92CH21 3.20.2 SFR The following tables show the SFR for I2S. This I2S is connected to the CPU by the 16-bit data bus. When the CPU accesses the SFR, use a 2-byte load instruction. I2SCTL0 Register 7 I2SCTL0 (080EH) Bit symbol Read/Write After reset Function 0 Transmit 0: Stop 1: Start 2 6 FMT R/W 0 Mode 0: I S 1: SIO 5 BUSY R 0 Status 0: Stop 4 DIR 0 First bit 0: MSB 3 BIT 0 Bit number 0: 8 bits 1: 16 bits 2 MCK1 R/W 0 Baud rate 00: fSYS 1 MCK0 0 10: fSYS/4 0 I2SWCK 0 WS clock 0: fs/4 1: TA1OUT TXE 1: Under 1: LSB transmitting 2 01: fSYS/2 11: fSYS/8 Note: is effective only for I S mode. 15 (080FH) Bit symbol Read/Write After reset Function 0 WS level 0: Low left 1: High left I2SWLVL 14 EDGE R/W 0 Clock edge 0: Falling 1: Rising 13 I2SFSEL 0 Select for 0: Stereo 12 I2SCLKE 0 Clock enable 11 10 9 8 SYSCKE R/W 0 System clock 0: Disable 1: Enable for data out stereo (After (2 channels) transmit) (1 channel) 1: Stop 2 1: Monaural 0: Operation Note: , and are effective only in I S mode. I2SBUFR Register 15 I2SBUFR (0800H) Read-modifywrite instruction is prohibited Bit symbol Read/Write After reset Function R15 14 R14 13 R13 12 R12 11 R11 10 R10 9 R9 8 R8 W 7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0 Undefined Register for transmitting buffer (FIFO) (Right channel) I2SBUFL Register 15 I2SBUFL (0808H) Bit symbol Read/Write L15 14 L14 13 L13 12 L12 11 L11 10 L10 9 L9 8 L8 W 7 L7 6 L6 5 L5 4 L4 3 L3 2 L2 1 L1 0 L0 Read-modify- After reset write instruction is Function prohibited Undefined Register for transmitting buffer (FIFO) (Left channel) Figure 3.20.2 I2S SFR 92CH21-430 2007-02-28 TMP92CH21 3.20.3 Explanation of I2S Mode (1) Connection example Figure 3.20.3 shows an example with external LSI. TMP92CH21 (Transmitter) P92/I2SWS P90/I2SCKO P91/I2SDO WS CK DATA (Receiver) Example: DA converter Note: After reset, P90 to P92 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor as necessary. Figure 3.20.3 Example with External LSI (2) Procedure A 32-byte FIFO is built-in. If the FIFO’s data becomes empty, an INTI2S interrupt is generated. In the interrupt routine, write the next transmission data to the FIFO. The following shows a setting example and timing diagram. Transmitting by I2S mode, I2SWS = 8.192 kHz, I2SCKO = 10 MHz, synchronous with rising edge (at fSYS = 20 MHz) 6 0 − − 0 1 5 0 − − − 0 4 1 − − 0 1 3 X − − 0 0 2 − 0 1 0 0 1 − 0 1 1 0 0 − 0 1 0 1 Set I S mode, MSB first, 8 bits, fSYS/2 clocks. Set rising edge, clock stop. Write 16-byte data to FIFO for right (8 times). Write 16-byte data to FIFO for left (8 times). Start transmitting. 2 (Setting example) (Main routine) 7 INTE5I2S P9CR P9FC I2SCTL0 I2SBUFR I2SBUFL I2SCTL0 X − − 0 0 Set interrupts level. Set pins to P90 (I2SCKO), P91 (I2SDO), and P92 (I2SWS). ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** 1 0 0 1 − 0 0 1 0 0 0 0 1 0 0 1 (INTI2S interrupt routine) I2SBUFR I2SBUFL ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** Write 16-byte data to FIFO for right (8 times). Write 16-byte data to FIFO for left (8 times). X: Don't care, −: No change 92CH21-431 2007-02-28 TMP92CH21 Write to FIFO 1 I2SWS pin I2SCKO pin I2SDO pin INTI2S 2 16 1 Figure 3.20.4 Whole Timing Diagram I2SWS pin I2SCKO pin I2SDO pin LSB MSB Bit7 Bit6 LSB Bit0 MSB Bit7 Bit6 LSB Bit0 MSB Bit7 10 MHz Figure 3.20.5 Detail Timing Diagram (3) Notes 1) INTI2S timing INTI2S is generated after the last data of FIFO is loaded to the internal shifter. FIFO is now empty and it is possible to write the next data. 2) I2SCTL0 A transmission is started by programming “1” to the register and stopped by writing “0”. After is programmed “1” once, the transmission automatically from right to left in order, alternately. is repeated If a transmission should be stopped, program “0” to after changes to “0” in the INTI2S interrupt routine. When is programmed “0” during transmitting, transmitting stops immediately. 3) FIFO size A 16-byte FIFO is provided for both right and left channels. It is not necessary to use all data, but please use the even numbers (2, 4 ... 16). 4) I2SCTL0 Write “1” to and use the right channel FIFO for monaural. It is not necessary to write data to the left channel FIFO. Channel transmission data is fixed at “0”. 5) Address for I2SBUFR and I2SBUFL If writing data to I2SBUFR or I2SBUFL, use “word or long word data load instruction”. A “byte data load instruction” cannot be used. The address of I2SBUFR selectable from 0800H to 0803H, and I2SBUFL is selectable from 0808H to 080BH. 92CH21-432 2007-02-28 TMP92CH21 3.20.4 Explanation of SIO Mode (1) Connection example Figure 3.20.6 shows an example with external LSI. TMP92CH21 (Transmitter) (Receiver) P90/I2SCKO P91/I2SDO Port SCK SI RCK Example: Shift register Note: Since P90 to P91 become high impedance by reset, connect a pull-up or pull-down resistor if necessary. Figure 3.20.6 Example with External LSI (2) Procedure A 32-byte FIFO is built-in. If the FIFO’s data becomes empty, an INTI2S interrupt is generated. In the interrupt routine, write the next transmission data to the FIFO. The following shows a setting example and timing diagram. (Setting example) Transmitting by SIO mode, I2SCKO = 10 MHz, synchronous with rising edge (at fSYS = 20 MHz) (Main routine) 7 INTE5I2S P9CR P9FC I2SCTL0 I2SBUFR I2SCTL0 X − − 0 − 1 − 6 0 − − 1 1 1 1 5 0 − − − − − − 4 1 − − 1 1 1 1 3 X − − 0 0 0 0 2 − − − 0 0 0 0 1 − 0 1 1 0 1 0 0 − 0 1 − 1 − 1 Set SIO mode, LSB first, 8 bits, fSYS/2 clocks. Set rising edge. Write 32-byte data to FIFO (16 times). Start transmitting. Set interrupts level. Set pins to P90 (I2SCKO) and P91 (I2SDO). ** ** ** ** ** ** ** ** (INTI2S interrupt routine) I2SBUFR I2SCTL0 ** ** ** ** ** ** ** ** 1 − 1 1 − − 1 1 0 0 0 0 1 0 − 1 Write 32-byte data to FIFO (16 times). Confirm termination of the 32-byte data transfer. Start transmitting. If = “1” then WAIT else NEXT X: Don't care, −: No change 92CH21-433 2007-02-28 TMP92CH21 Write to FIFO 1 I2SCKO pin I2SDO pin INTI2S 2 31 32 1 2 Figure 3.20.7 Whole Timing 10 MHz I2SCKO pin I2SDO pin LSB Bit0 Bit1 MSB Bit7 LSB Bit0 Bit1 MSB Bit7 Figure 3.20.8 Detail Timing (3) Notes 1) INTI2S timing INTI2S is generated after the last data of FIFO is loaded to the internal shifter. FIFO is now empty and it is possible to write the next data. 2) I2SCTL0 A transmission is started by programming “1” to the register and stopped by programming “0”. register is cleared to “0” when changes from “1” to “0”. When is programmed “0” during transmitting, transmitting stops immediately. 3) FIFO size A 32-byte FIFO is provided for SIO mode. It is not necessary to use all data but please use even numbers ( 2, 4 ... 32). The will be changed to “0” and will be cleared to “0” automatically after transmitting all programmed data to FIFO. In case of continuous transmitting, program “1” to after programming data to FIFO. The number of data programmed to FIFO is counted automatically and held by programming “1” to . 4) Address for I2SBUFR and I2SBUFL If writing data to I2SBUFR (I2SBUFL cannot be written), use “word or long word data load instruction”. A “byte data load instruction” cannot be used. The address of I2SBUFR is selectable from 0800H to 0803H. 92CH21-434 2007-02-28 TMP92CH21 3.21 Boot ROM A boot ROM is built-in to download user’s boot program. Three downloading methods are supported. 3.21.1 Operation Mode There are 2 operation modes: MULTI mode and BOOT mode. Each mode is set according to the status of the AM1 and AM0 pins when RESET is asserted. (1) MULTI mode: After reset, the CPU fetches and executes instructions from an external memory. (2) BOOT mode: After reset, the CPU fetches and executes instructions from the internal boot ROM. A user program which executes programming to on-board memory (e.g., NOR flash) is loaded from either NAND flash, UART or USB to internal RAM, and then branched to the internal RAM. This operation will initiate a user program boot. Table 3.21.2 shows an outline of boot operation. Table 3.21.1 Operation Mode Mode Setting Pins RESET Operation Mode 1 0 1 0 AM1 0 1 1 0 AM0 Start from external 16-bit bus memory MULTI Start from external 32-bit bus memory BOOT (Start from internal boot ROM) TEST (Disabled to set) Table 3.21.2 Outline of Boot Operation Name (a) (b) (c) Order of Setting 1 2 3 Loading Source NAND flash PC PC Operation after Destination Internal RAM Loading Branch to internal RAM I/F Data bus UART USB 92CH21-435 2007-02-28 TMP92CH21 3.21.2 Hardware Specification for Internal Boot ROM (1) Memory map Figure 3.21.1 shows a memory map of BOOT mode. An 8-Kbyte ROM is built-in and it is mapped to address 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and its area is mapped as an external area. 000000H Internal I/O 001D00H 002000H Internal RAM (16 Kbytes) 006000H 3FE000H Internal boot ROM (8 Kbytes) 3FFF00H 400000H (B) Reset/interrupt vector area (256 bytes) FFFF00H (A) Reset/interrupt vector area (256 bytes) Figure 3.21.1 Memory Map of BOOT Mode (2) Reset/interrupt address conversion circuit A reset/interrupt vector address conversion circuit is included. This function allows for individual reset/interrupt vector areas. For details, refer to section 3.6.5, Internal Boot ROM Control. (3) Clearing boot ROM After boot sequence in BOOT mode, the application system program may continue to run without reset asserting. In this case, any external memory which is mapped to address 3FE000H to 3FFFFFH cannot be accessed because the boot ROM is assigned here. So, an internal boot ROM can be cleared by setting BROMCR to “1”. For the details, refer to section 3.6.5, Internal Boot ROM Control. 92CH21-436 2007-02-28 TMP92CH21 3.21.3 Outline of Boot Operation There are 3 downloading methods: NAND flash, UART and USB. After reset, a boot program in the boot ROM operates as shown in the Figure 3.21.2 flow chart. Internal RAM use is the same regardless of downloading method, and is shown in Figure 3.21.3. Start Clock setting ･ fFPH = fOSCH ･ fUSB = fOSCH ∗ 16/3 (a) Check NAND flash OK ? (b) No (c) Check UART OK ? No No Yes Yes Download from NAND flash Download with UART Check USB OK ? Yes Download with USB Branch to internal RAM Note 1: When USB downloading is used, a special USB device driver and application software are needed on the PC. Note 2: Note 3: When UART downloading is used, special application software is needed on the PC. (a), (b) and (c) on the flow chart show the points at which external port pins are set. Refer to Table 3.21.3 for details. Figure 3.21.2 Flow Chart Outline of Internal Boot ROM 92CH21-437 2007-02-28 TMP92CH21 002000H Work area for boot program (4 Kbytes) 003000H Download area for user program (10 Kbytes) 005800H Stack area for boot program (2 Kbytes) Figure 3.21.3 Internal RAM Use 92CH21-438 2007-02-28 TMP92CH21 (1) Port setting The boot program port settings are shown in Table 3.21.3, and Table 3.21.4 shows PCB design. These port settings must be carefully noted when designing an application system. The remaining ports are not set, so they maintain their status after reset. Table 3.21.3 Port Setting Port NAND flash P71 P72 P75 P84 PJ5 PJ6 − UART PF0 PF1 USB − − PC6 Function NDRE I/O (a) Output Output Input Output Output Output I/O Output Input I/O I/O Output Port Setting by Boot Program (b) (c) NDWE NDR/ B ND0CE Set to the function pin shown left No change from (a) No change from (a) NDALE NDCLE D7 to D0 TXD1 RXD1 D+ D− PUCTL No change No change to input port status after reset Set to the RXD1 input pin No change No change to input port status after reset Set to the output port pin No change from (b) No change from (a) Set to the TXD1 output pin No change from (a) 92CH21-439 2007-02-28 TMP92CH21 Table 3.21.4 How to Design PCB Port NAND flash P71 P72 Function NDRE I/O NAND flash Output Connect to NAND flash and Output pull-up by 100 kΩ resistor because this pin is changed to input port by reset. Input Connect to NAND flash and pull-up by 2 kΩ resistor because R/B pin of NAND flash has open-drain output buffer. Boot Method UART Not affected by UART boot. If the NAND flash is not used in the system, ensure no conflict with the I/O direction shown left. USB Not affected by USB boot. If the NAND flash is not used in the system, ensure no conflict with the I/O direction shown left. NDWE P75 NDR/ B P84 PJ5 PJ6 − UART PF0 PF1 USB − ND0CE Output Connect to NAND flash. Output Output I/O Output Not affected by NAND flash Input boot. I/O Connect to level shifter. Not affected by USB boot. Pull-up by 100 kΩ to avoid UART executing. Connect to USB connector, add dumping resistor (27Ω) and 1.5 kΩ pull-up which can be switched ON/OFF. Connect to USB connector and add dumping resistor (27Ω). Used to control ON/OFF pull-up resistor of D + pin. The switch should be ON by “1”. As this pin changes to input port by reset, add100 kΩ pull-down. NDALE NDCLE D7 to D0 TXD1 RXD1 D+ Not affected NAND flash boot. Not affected by UART boot. − D− I/O PC6 PUCTL Output Note 1: When booting method is either NAND flash or UART and USB is used in the system, ensure the D + pin pull-up resistor is not on in the BOOT mode. Note 2: When booting method is USB, do not start UART application software on the PC. Note 3: When booting method is UART, do not connect the USB connector. 92CH21-440 2007-02-28 TMP92CH21 (2) I/O registers setting by boot program Table 3.21.5 shows I/O register setting by boot program. Take particular note of these set values when using an application system program which continues to run without asserting a reset after a boot sequence is executed . Also take note of the status of the CPU registers and internal RAM following execution of a boot sequence. Table 3.21.5 I/O Register Setting by Boot Program Symbol WDMOD WDCR SYSCR0 SYSCR1 SYSCR2 PLLCR0 Set Value 00H B1H 80H 00H 2CH 40H 00H Set Content Stop watchdog timer. Disable watchdog timer. Set system clock. Set system clock. Set system clock. Where USB is used for boot, set to use PLL output clock for fFPH. Where USB is not used for boot, set not to use PLL output clock for fFPH. PLLCR1 INTEUSB INTETC01 80H 04H 44H Set to PLL ON. Not affected by boot method. Set USB interrupt level. Set INTTC interrupt level. Note: The setting values for NAND flash, UART and USB are not shown. Set each register where these functions are used in the system. 92CH21-441 2007-02-28 TMP92CH21 3.21.4 Download from NAND flash (1) Connection example Figure 3.21.4 shows an example of NAND flash. (A 16-bit SDRAM is used as program memory). 100 kΩ 100 kΩ P84, ND0CE PJ6, NDCLE PJ5, NDALE P71, NDRE P72, NDWE P75, NDR/ B PF7, SDCLK PJ7, SDCKE PJ2, SDCS PJ0, SDRAS PJ1, SDCAS PJ2, SDWE PJ3, SDLLDQM PJ4, SDLUDQM AM0 A0 to A12 AM1 D0 to D15 D0 to D15 CLK CKE CS RAS CAS WE 2 kΩ CE CLE ALE RE WE WP TMP92CH21 R/B NAND flash LLDQM LUDQM SDRAM A0 to A11, BS0 IO0 to IO7 Note 1: The values of the pull-up resistors are recommended values. Note 2: The WP (Write protect) pin of NAND flash is not supported by the TMP92CH21. If necessary, it must be prepared on an external circuit. Figure 3.21.4 Example of NAND Flash Connection (2) Supported NAND flash The boot program is designed based on SmartMediaTM physical format specification Ver1.20. Table 3.21.6 shows supported memory devices and device codes. Table 3.21.6 Supported Memory Memory Size [Mbyte] 1 2 4 8 16 32 64 128 OK (E3H) OK (E6H) OK (73H) OK (75H) OK (76H) OK (79H) NAND Flash 3.3 V Model Not supported Masked ROM 3.3 V Model OK (D5H) OK (D6H) OK (57H) OK (58H) OK (D9H) OK (DAH) 92CH21-442 2007-02-28 TMP92CH21 (3) Data format The download data consists of the boot identification code (4 bytes), user program size (2 bytes) and user program (max 10 Kbytes). These should be assigned (programmed) to NAND flash as shown in Figure 3.21.5. Also program the ECC code in the redundant area of the NAND flash, the block status area and thedata status area . Address: 01 Page 0 Block 0 Page 1 Page end Page 0 Block 1 Page 1 Page end User program (Max 10 Kbytes) User program size (2 bytes) 511 (or 255) Boot identification code (4 bytes) Page 0 Block end Page 1 Page end NAND flash program image (Physical) Download data assignment image : Download data Figure 3.21.5 Download Data Image a) Boot identification code (4 bytes) The boot program initially checks the boot identification code. If the boot characters in ASCII code are read from the first 4 bytes in page 0, block 1 of the NAND flash, the boot program will recognize the boot method as NAND flash. 42H (“B”) 4FH (“O”) 4FH (“O”) 54H (“T”) Figure 3.21.6 Boot Identification Code b) User program size (2 bytes) The program size should be programmed to the next 2 bytes. The first byte is the lower 8 bits and the second is the upper 8 bits. This size indicates only the user program size; it does not include the boot identification code (4 bytes) and user program size (2 bytes). This must be less than or equal to 10 Kbytes. So, the maximum number is 2800H. Size (Lower 8 bits) Size (Upper 8 bits) Figure 3.21.7 User Program Size 92CH21-443 2007-02-28 TMP92CH21 c) User program (max 10 Kbytes) This refers to a user program that is loaded to internal RAM. When creating a user program, note the following points. • Set start address to 3000H Beforehand, program (write) the user program to NAND flash in binary format. An example explaining how to make a binary format file is given below. Example: How to convert from Intel Hex format file to binary format file The following is an example of display in text editor when an Intel Hex format file is opened. : 103000000607F100030000F201030000B1F16010B7 : 00000001FF In fact, their data are as below because ASCII code is used for Intel Hex format files. 3A3130333030303030303630374631303030333030303046323031303330303030 423146313630313042370D0A3A303030303030303146460D0A So, first convert the above data to binary format using the table below. Before (ASCII) 3A 30 to 39 41 or 61 42 or 62 43 or 63 44 or 64 45 or 65 46 or 66 0D0A After (Binary) 3A (Only 3A should not be converted.) 0 to 9 A B C D E F Delete Next, delete characters other than data (Start mark, data number, address, record type and checksum). The Intel Hex format and its meaning are given below. Data record 3A 10 3000 00 0607F100030000F201030000B1F16010 B7 Data Record type Address Data number : (Start mark) End record 3A 00 0000 01 FF Data Record type Address Data number : (Start mark) Checksum 92CH21-444 2007-02-28 TMP92CH21 (4) Error check item The items checked by the boot program are given below. If an error occurs in any check, the boot program will cancel downloading from NAND flash and skip to the next operation (recognizing UART or USB). a) Supported NAND flash The boot program reads a device code from NAND flash and checks whether it is supported or not. b) c) d) Boot identification code User program size The boot program checks whether it is less than or equal to 10 Kbytes. Block status area The boot program checks whether each block is normal or not. If the block status area on first page of any block has 2-bit or more “0” data, it is an error. e) Data status area The boot program checks whether each data status is correct or not. If the data status area has 4-bit or more “0” data, it is an error. f) ECC error The boot program reads both calculated code from NDFC and ECC code in NAND flash and checks whether they are correctable or not. g) NAND flash R/B The boot program checks whether NDR/B pin is normal or not in each action. If the busy status is longer than 70 [μs] at fFPH = 40 MHz, it is an error. (5) ECC error check a) b) Calculation ECC code The NDFC (NAND flash controller) is used for calculation of ECC code. ECC code correction The boot program operates as below. 1. 2. Compares both calculated ECC code from NDFC and ECC code in NAND flash. Evaluates and corrects according to the following cases. Case (a): No data error Case (b): 1-bit data error Case (c): 2-bit or more data error Case (d): ECC code 1-bit error → (OK) Next operation → (OK) Error correction and next operation → (Error) Termination → (OK) Next operation Case (e): ECC code 2-bit or more error → (Error) Termination 92CH21-445 2007-02-28 TMP92CH21 For reference, details of calculation flow are given below. 1) Make XOR data by calculating exclusive OR after both ECC code from NDFC and NAND flash are placed to 4-byte data as below. Lower 2 bytes: Line parity Upper 2 bytes: Column parity (Valid data of column parity is lower 6-bit in upper 2 bytes) 2) 3) 4) If XOR data equals “0”, it will terminate normally because the ECC code is the same, but if not, they are checked as to whether they are correctable or not. If XOR data does not have 2-bit or more “1” data, it will terminate normally because of the ECC code 1-bit error. If the effective data (2-bit width from bit0 to bit21 in XOR data) equals either 01B or 10B, it corrects data because they are correctable. If the effective data has either 00B or 11B, it terminates abnormally because they are not correctable. Example 1: If the XOR data equals 0026A65AH, shown below in binary, 0000000000 10 01 10 10 10 01 10 01 01 10 10B all effective data (2-bit width from bit0 to bit21) equals either 01B or 10B. So, this is evaluated as being correctable. Example 2: If the XOR data equals 002EA65AH, shown below in binary, 0000000000 10 11 10 10 10 01 10 01 01 10 10B bit18 and bit19 are 11B, so this is evaluated as being uncorrectable. 5) Data correcting takes error line information from line parity in XOR data and error bit information from column parity and inverts the bit. Example: If the XOR data equals 0026A65AH, line parity is shown below in binary. 10 10 01 10 01 01 10 10B If 10B is converted to 1B and 01B is converted to 0B, they become 1 1 0 1 0 0 1 1B and meaning the 212th byte. In the same manner, error bit information becomes bit5. As a result, it inverts bit5 of 212th byte. 92CH21-446 2007-02-28 TMP92CH21 3.21.5 Download with UART (1) Connection example Figure 3.21.8 shows an example of UART. (A 16-bit NOR flash is used as program memory.) UART 3 pins Level shifter TXD RXD RTS PC TXD1, PF0 (output) RXD1, PF1 (input) P82, CS2 P70, RD PJ2, SRWR CE OE WE AM0 TMP92CH21 D0 to D15 NOR flash D0 to D15 AM1 A1 to A20 A0 to A19 Figure 3.21.8 Example of UART (2) UART interface specification SIO channel 1 is used to download. The following shows the UART communication format in BOOT mode. Before booting, the PC side must also be setup in the same way. The default baud rate is 9600 bps, but it can be changed to other values as shown in Table 3.21.9. Serial transfer mode Data length Parity bit STOP bit Handshake Baud rate (Default) : UART (Asynchronous communication) mode, full duplex communication : 8 bits : None : 1 bit : None : 9600 bps 92CH21-447 2007-02-28 TMP92CH21 (3) UART data transfer format Table 3.21.7 to Table 3.21.12 show the supported frequency, data transfer format, baud rate modification commands, operation commands, version management information, and frequency measurement result with data storing location, respectively. Please also refer to the description of boot program operation in the following pages. Table 3.21.7 Supported Frequency (fOSCH) 6.00 MHz 8.00 MHz 9.00 MHz 10.00 MHz 16.00 MHz 20.00 MHz 22.579 MHz 25.00 MHz 32.00 MHz 33.868 MHz 36.00 MHz 40.00 MHz Note: Internal PLL (Clock multiplier) is not used. Table 3.21.8 Transfer Format Byte Number to Transfer Boot ROM 2nd byte 3rd byte to 6th byte 7th byte 8th byte 9th byte 10th byte to n’th − 4 byte n’th − 3 byte n’th − 2 byte n’th − 1 byte − − User program start command (C0H) (Refer to Table 3.21.10) n’th byte RAM − − Branch to user program start address OK: SUM (High) (Refer (6) − c) OK: SUM (Low) − OK: Echo back data (C0H) Error: Error code × 3 − Baud rate modification command (Refer to Table 3.21.9) − User program Intel Hex format (binary) New baud rate Frequency information (Refer to Table 3.21.12) − OK: Echo back data Error: Error code × 3 Error: Stop operation by checksum error − − 1st byte Transfer Data from PC to TMP92CH21 Matching data (5AH) Baud Rate Transfer Data from TMP92CH21 to PC 9600 bps − (Frequency measurement and baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted Version management information (Refer to Table 3.21.11) “Error code × 3” means sending error code 3 times. For example, when error code is 62H, TMP92CH21 sends 62H 3 times. (For error code, refer to (4)-b.) 92CH21-448 2007-02-28 TMP92CH21 Table 3.21.9 Baud Rate Modification Command Baud Rate (bps) Modification Command 9600 28H 19200 18H 38400 07H 57600 06H 115200 03H Note 1:If fOSCH is either 16.0, 20.0, 20.58 or 25.0 MHz, 115200 bps is not supported. Note 2: If fOSCH is 10.0 MHz, both 57600 and 115200 bps are not supported. Note 3: If fOSCH is 6.00, 8.00 or 9.00 MHz, then 38400, 57600 and 115200 bps are not supported. Table 3.21.10 Operation Command Operation Command C0H Operation Start user program Table 3.21.11 Version Management Information Version Information FRM1 ASCII Code 46H, 52H, 4DH, 31H Table 3.21.12 Frequency Measurement Result Data fOSCH [MHz] 2000H (RAM storing address) 6.000 09H 22.579 02H 8.000 0AH 25.000 03H 9.000 08H 32.000 04H 10.000 0BH 33.868 05H 16.000 00H 36.000 06H 20.000 01H 40.000 07H (4) Description of UART boot program operation The boot program receives data that is sent from the PC by UART, and loads it to internal RAM. If the transferring terminates normally, it calculates SUM and sends the result to the PC before staring to execute the user program. The starting address to execute is the address received first . This boot program enables user’s own on-board programming. a) Operation procedure 1. 2. 3. Connect the serial cable . Make sure to perform connection before resetting the micro controller. Set both AM1 and AM0 pins to “1” and reset the micro controller. The receive data in the first byte is the matching data. When the boot program starts, it goes to a state in which it waits for the matching data to be received. Upon receiving the matching data, it automatically adjusts the serial channels’ initial baud rate to 9600 bps. The matching data is 5AH. The second byte is used to echo back 5AH to the PC upon completion of the automatic baud rate setting in the first byte. If the device fails in automatic baud rate setting, it goes to an idle state. The third through sixth bytes are used to send the boot program’s version management information in ASCII code. The PC should check that the correct version of the boot program is used. 4. 5. 92CH21-449 2007-02-28 TMP92CH21 6. The seventh byte is used to send information of the measured frequency. The PC should check that the frequency of the resonator is measured correctly. The receive data in the eighth byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table 3.21.9 are available. Even when you do not change the baud rate, be sure to send the initial baud rate data (28H: 9600 bps). Baud rate modification becomes effective after the echo back transmission is completed. The ninth byte is used to echo back the received data to the PC when the data received in the eighth byte is one of the baud rate modification data corresponding to the device’s operating frequency. Then the baud rate is changed. If the received baud rate data does not correspond to the device’s operating frequency, the device goes to an idle state after sending 3 bytes of baud rate modification error code (62H). The receive data in the 10th byte through n’th − 4 bytes is received as binary data in Intel Hex format. No received data is echoed back to the PC. The boot program processing routine ignores the received data until it receives the start mark (3AH for “ : ”) in Intel Hex format. Nor does it send error code to the PC. After receiving the start mark, the routine receives a range of data from the data length to checksum and writes the received data to the specified RAM addresses successively. After receiving one record of data from start mark to checksum, the routine goes to a start mark waiting state again. If a receive error or checksum error of Intel Hex format occurs, the device goes to an IDLE state without returning error code to the PC. Because the boot program processing routine executes a SUM calculation routine upon detecting the end record, the controller should be placed in a SUM waiting state after sending the end record to the device. 7. 8. 9. 10. The n’th − 3 bytes and the n’th − 2 bytes are the SUM value that is sent to the PC in order of upper byte and lower byte. For details on how to calculate the SUM, refer to “notes on SUM” in the latter pages of this manual. The SUM calculation is performed only when no write error, receive error, or Intel Hex format error has been encountered after detecting the end record. Soon after calculation of SUM, the device sends the SUM data to the PC. The PC should determine whether writing to the RAM has terminated normally depending on whether the SUM value is received after sending the end record to the device. 11. After sending the SUM, the device goes to a state waiting for the user program start code. If the SUM value is correct, the PC should send the user program start command to the n’th − 1 byte. The user program start command is C0H. 12. The n’th byte is used to echo back the user program start code to the PC. After sending the echo back to the PC, the stack pointer is set to 5FFFH and the boot program jumps to the 1st address that is received as data in Intel Hex format. 13. If the user program start code is wrong or a receive error occurs, the device goes to an idle state after returning 3 bytes of error code to the PC. 92CH21-450 2007-02-28 TMP92CH21 b) Error code The boot program sends the processing status to the PC using various codes. The error codes are listed in the table below. Table 3.21.13 Error Codes Error Code 62H 64H A1H A3H Meaning of Error Code Baud rate modification error occurred. Operation command error occurred. Framing error in received data occurred. Overrun error in received data occurred Note 1: When a receive error occurs when receiving the user program, the device does not send the error code to the PC. Note 2: After sending the error code, the device goes to an IDLE state. c) Notes on SUM 1. Calculation method SUM consists of byte + byte... + byte, the sum of which is returned in words as the result. Namely, data is read out in bytes, the sum of which is calculated, with the result returned in words. Example: If the data to be calculated consists of the 4 bytes A1H B2H C3H D4H shown to the left, SUM of the data is: A1H + B2H + C3H + D4H = 02EAH SUM (HIGH) = 02H SUM (LOW) = EAH 2. Calculation data The data from which SUM is calculated is the RAM data from the first address received to the last address received. The received RAM write data is not the only data to be calculated for SUM. Even when the received addresses are noncontiguous and there are some unwritten areas, data in the entire memory area is calculated. The user program should not contain unwritten gaps. 92CH21-451 2007-02-28 TMP92CH21 d) Notes on Intel Hex format (Binary) 1. After receiving the checksum of a record, the device waits for the start mark (3AH for “ : ”) of the next record. Therefore, the device ignores all data received between records during that time unless the data is 3AH. Make sure that once the PC program has finished sending the checksum of the end record, it does not send anything and waits for 2 bytes of data to be received (upper and lower bytes of SUM). This is because after receiving the checksum of the end record, the boot program calculates the SUM and returns the calculated SUM in 2 bytes to the PC. Writing to areas outside the device’s internal RAM causes incorrect operation. Therefore, when an extended record is transmitted, be sure to set a paragraph address to 0000H. Always make sure the first record type is an extended record, because the initial value of the address pointer is 00H. The user program is assigned to the address from 3000H to 57FFH and it should be within 10 Kbytes. Transmit a user program not by the ASCII code but by binary. An example explaining how to make binary format file is given below. 2. 3. 4. 5. 6. Example: How to convert from Intel Hex format file to binary format file. The following is an example of display in text editor where an Intel Hex format file is opened. : 103000000607F100030000F201030000B1F16010B7 : 00000001FF In fact, their data are as below because ASCII code is used for Intel Hex format files. 3A3130333030303030303630374631303030333030303046323031303330303030 423146313630313042370D0A3A303030303030303146460D0A So, first convert the above data to binary format using the table below. Before (ASCII) 3A 30 to 39 41 or 61 42 or 62 43 or 63 44 or 64 45 or 65 46 or 66 0D0A After (Binary) 3A (Only 3A should not be converted.) 0 to 9 A B C D E F Delete it The Intel Hex format and its meaning are given below. Data record 3A 10 3000 00 0607F100030000F201030000B1F16010 B7 Data Record type Address Data number : (Start mark) End record 3A 00 0000 01 FF Data Record type Address Data number : (Start mark) Checksum 92CH21-452 2007-02-28 TMP92CH21 e) Error when receiving user program If the following errors occur in Intel Hex format when receiving the user program, the device goes to an idle state. When the record type is not 00H, 01H, and 02H When a checksum error occurs f) Error between frequency measurement and baud rate The boot program measures the resonator frequency when receiving matching data. If the error is under 3%, the boot program decides on that frequency. Since there is an overlap between the margin of 3% for 32.000 MHz and 33.868 MHz, the boundary is set at the intermediate value between the two. The baud rate is set based on the measured frequency. Each baud rate includes a set error shown in Table 3.21.14. For example, in the case of 20.000 MHz and 9600 bps, the baud rate is actually set at 9615.38 bps with an error of 0.2%. To establish communication, the sum of the baud rate set error shown in Table 3.21.14 and frequency error must be under 3%. Table 3.21.14 Setting Error of Each Baud Rate (%) 9600 bps 19200 bps 0.2 0.2 −0.7 0.2 0.2 0.2 −0.7 −0.8 0.2 0.3 −0.7 0.2 38400 bps − − − −1.4 0.2 0.2 −0.7 0.5 0.2 0.3 0.2 0.2 57600 bps − − − − −0.8 1.0 0.1 0.5 0.7 −0.7 0.2 −0.3 115200 bps − − − − − − − − −0.8 −0.7 0.2 1.0 6.000 MHz 8.000 MHz 9.000 MHz 10.000 MHz 16.000 MHz 20.000 MHz 22.579 MHz 25.000 MHz 32.000 MHz 33.868 MHz 36.000 MHz 40.000 MHz 0.2 0.2 0.2 0.2 0.2 0.2 −0.7 0.5 0.2 0.3 0.2 0.2 −: Not supported 92CH21-453 2007-02-28 TMP92CH21 (5) Further notes a) b) Handshake function The TMP92CH21 has a CTS pin, but boot programs do not use it. RS-232C connector When the boot program is running, do not connect or disconnect an RS-232C connector. c) Software on PC Special application software is needed on the PC. 92CH21-454 2007-02-28 TMP92CH21 3.21.6 Download with USB (1) Connection example Figure 3.21.9 shows an example of USB. (16-bit NOR flash is used as program memory.) PUCTL R4 = 100 kΩ R2 = 27 Ω R3 = 27 Ω PC6, KO8, LDIV P82, CS2 P70, RD PJ2, SRWR TMP92CH21 D0 to D15 CE OE WE R1 = 1.5 kΩ PC R5 = 100 kΩ Note3 D+ D− AM0 AM1 NOR flash D0 to D15 A1 to A20 A0 to A19 Note 1: The values of pull-up / pull-down resistors are recommended values. Note 2: The PC6 (KO8, LDIV) pin is assigned as PUCTL (Control to pull-up) for USB. So, note whether it is used as KO8 or LDIV. Note 3: Pull-down resistor R2 is used only to fix the level for the flow current. If there is no ON/ OFF control by port for example, confirm operation by actual setting, and set the value to ensure the USB connection is not cut. Figure 3.21.9 USB Connecting Example (2) USB interface specification outline For USB booting, make sure the oscillator is 9 MHz. The baud rate is fixed at full speed (12 MHz). The boot function is employed using the following 2 transfer types. Table 3.21.15 Transfer Types Used by Boot Program Transfer Type Control Bulk Purpose Used as transmitting for standard request or vendor request Used as transmitting for vendor request or user program 92CH21-455 2007-02-28 TMP92CH21 An outline flowchart is given below. (Legend) Control type Bulk type Host (PC) Recognition for connection Transmit GET_DESCRIPTOR TMP92CH21 Transmit DESCRIPTOR information Transmit MICON information command Transmit MICON information data Preparing MICON information data Confirming data Transmitting data Converting Intel Hex format Transmit MICON information command Transmit MICON information data Preparing MICON information data Confirming data Transmit load starting command of user program Transmit user program Loading received data to the specified internal RAM address and preparing MICON information data. (If any trouble has occurred, the received data are discard.) Transmitting data Terminating Transmit load result command after the user program has finished transmitting and wait 2 s. Transmit load result command Transmit received result data Preparing received result data Confirming data Branch to internal RAM Figure 3.21.10 Outline Flowchart 92CH21-456 2007-02-28 TMP92CH21 The vendor request command table is shown below. Table 3.21.16 Vendor Request Command Table Command Name MICON (Microcomputer) information command Value of Request 00H Outline Transmit microcomputer information Notes This is transmitted after a setup stage is terminated by bulk in transfer type. Substitute size of user program to wIndex. The user program should be received after a setup stage is terminated by bulk out transfer type. Load starting command of user program 02H Receive user program Transmit result command 04H Transmit the result This is transmitted after a setup stage is terminated by bulk in transfer type. The data structure of setup command is shown below. Table 3.21.17 Data Structure of Setup Command Field Name bmRequestType 40H Value D7 D6-D5 D4-D0 2: Vender 0: Device Meaning 0: Host to device bRequest 00H, 02H, 04H 00H: MICON information 02H: Start to transmit user program 04H: Result for user program received wValue 00H to FFFFH Own data number (Not used by boot program) wIndex 00H to FFFFH Size of user program (Used when a user program starts to be transmitted.) wLength 0000H Fixed 92CH21-457 2007-02-28 TMP92CH21 The standard request command table is shown below. Table 3.21.18 The Standard Request Command Table Standard Request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DISCRIPTOR SET_DISCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME Response Medthod By hardware, automatically Not supported By hardware, automatically Ignored The information transmitted by GET_DISCRIPTOR is shown below. Table 3.21.19 Information Transmitted by GET_DISCRIPTOR Device Descriptor Field Name Blength BdescriptorType BcdUSB BdeviceClass BdeviceSubClass BdeviceProtocol BmaxPacketSize0 IdVendor IdProduct BcdDevice Imanufacturer Iproduct IserialNumber BnumConfigurations 12H 01H 0110H 00H 00H 00H 40H 0930H 6504H 0001H 00H 00H 00H 01H Value 18 bytes Meaning Device descriptor USB Version 1.1 Device class is not used Sub command is not used Protocol is not used EP0 max packet size 64 bytes Vendor ID Product ID (0) Device version (v 0.1) Index value of string descriptor in which producer is shown Index value of string descriptor in which product name is shown Index value of string descriptor in which product number is shown Configuration is 1 92CH21-458 2007-02-28 TMP92CH21 Configuration Descriptor Field Name bLength bDescriptorType wTotalLength 09H 02H 0020H Value 9 bytes Meaning Configuration descriptor Total length (32 bytes) in which each descriptor of configuration descriptor, interface and endpoint is added. Interface is 1 Configuration number 1 Index value of string descriptor in which this configuration name is shown (Not used). Bus power Maximum power consumption (49 mA) bNumInterfaces bConfigurationValue iConfiguration bmAttributes MaxPower 01H 01H 00H 80H 31H Interface Descriptor Field Name bLength bDescriptorType bInterfaceNumber bAlternateSetting bNumEndpoints bInterfaceClass bInterfaceSubClass bInterfaceProtocol iIinterface 09H 04H 00H 00H 02H FFH 00H 50H 00H Value 9 bytes Meaning Interface descriptor Interface number 0 Alternate setting number 0 Endpoint is 2 Specified device Bulk only protocol Index value of string descriptor in which this interface name is shown (Not used). Endpoint Descriptor Field Name blength bDescriptorType bEndpointAddress bmAttributes wMaxPacketSize bInterval bLength bDescriptor bEndpointAddress bmAttributes wMaxPacketSize bInterval 07H 05H 82H 02H 0040H 00H 7 bytes 07H 05H 01H 02H 0040H 00H 7 bytes Value Meaning Endpoint descriptor EP1 is OUT Bulk transfer Payload 64 bytes (Ignored for bulk transfer) Endpoint descriptor EP2 is IN Bulk transfer Payload 64 bytes (Ignored for bulk transfer) 92CH21-459 2007-02-28 TMP92CH21 The information transmitted by the MICON information command is shown below. Table 3.21.20 Information Transmitted by MICON Information Command Micon Information “TMP92CH21FG” ASCII Code 54H, 4DH, 50H, 39H, 32H, 43H, 48H, 32H, 31H, 46H, 47H, 20H, 20H, 20H, 20H The information transmitted by the result information command is shown below. Table 3.21.21 Information Transmitted by Result Information Command Result No error Not received user program error Received except Intel Hex format error Over user program size error Received incorrect address error Protocol error or other error Value 00H 02H 04H 06H 08H 0AH Error Condition When a user program is received without receiving user program starting command. When the first data of the user program is not “ : ” (3AH). When more than the value of wIndex is received. When the user program address is incorrect. When the user program size is over 10 Kbytes When start or result of user program is received first. When check SUM is incorrect in Intel Hex file. When record type is incorrect in Intel Hex file. When address length is more than 2 in Intel Hex file. When end record length is not 0 in Intel Hex file. 92CH21-460 2007-02-28 TMP92CH21 (3) Description of USB boot program operation The boot program provides the following RAM loader function. The data, which is transmitted by the PC in Intel Hex format, is loaded to the internal RAM. After loading normally, the user program will begin to execute. The first received address is set as the starting address. By this function, this boot program enables the user’s own on-board programming. a. Operational procedure 1. 2. 3. 4. Connect the USB cable. Set both AM1 and AM0 pin to “1” and reset the micro controller. On the PC side, recognize USB connection and confirm sub information by GET_DISCRIPTOR. On the PC side, transmit MICON information command by vendor request and confirm MICON information data by Bulk IN after a setup stage is finished. The boot program prepares MICON information in ASCII code after MICON information command is received. On the PC side, convert user program into binary format. On the PC side, transmit load-starting command by vendor request and transmit user program by Bulk OUT after a setup stage is finished. On the PC side, wait 2 seconds and transmit load result command by vendor request. Confirm the result by bulk in after a setup stage is finished. The boot program prepares the result after load result command is received. 5. 6. 7. 8. 9. 10. If the result is not normal, the boot program cannot be returned normally. In this case, terminate device driver on the PC and retry from step 2. 92CH21-461 2007-02-28 TMP92CH21 b. Notes on user program format (Binary) 1. After receiving the checksum of a record, the device waits for the start mark (3AH for “: ”) of the next record.The device therefore ignores all data received between records during that time unless the data is 3AH. The first record type is not needed as an address record because the initial value of the address pointer is 00H. The user program is assigned to the address from 3000H to 57FFH and it should be within 10 Kbytes. In the user program, change the Intel Hex format file (usually ASCII code) to binary format and transfer it. The example below explains how to make a binary format file. (This is the same as with UART.) Make sure that the maximum data number of 1 record is FAH for the user program. 2. 3. 4. Example: Transfer data case of writing 16 bytes data from address 3000H by Intel Hex format file. The following is an example of display in text editor where an Intel Hex format file is opened. : 103000000607F100030000F201030000B1F16010B7 : 00000001FF In fact, their data are as below because ASCII code is used for Intel Hex format files. 3A3130333030303030303630374631303030333030303046323031303330303030 423146313630313042370D0A3A303030303030303146460D0A So, first convert the above data to binary format using the table below. Before (ASCII) 3A 30 to 39 41 or 61 42 or 62 43 or 63 44 or 64 45 or 65 46 or 66 0D0A After (Binary) 3A (Only 3A should not be converted.) 0 to 9 A B C D E F Delete it The Intel Hex format and its meaning are given below. Data record 3A 10 3000 00 0607F100030000F201030000B1F16010 B7 Data Record type Address Data number : (Start mark) End record 3A 00 0000 01 FF Data Record type Address Data number : (Start mark) Checksum 92CH21-462 2007-02-28 TMP92CH21 (4) Further notes a) USB connector When the boot program is running, do not connect or disconnect the USB connector. b) Software on PC Special USB device driver and application software is needed on the PC. 92CH21-463 2007-02-28 TMP92CH21 4. 4.1 Electrical Characteristics Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Output Current Output Current (MX, MY pin) Output Current Output Current (PX, PY pin) Output Current (Total) Output Current (Total) Power Dissipation (Ta = 85°C) Soldering Temperature (10 s) Storage Temperature Operation Temperature Symbol VCC VIN IOL IOL IOH IOH Σ IOL Σ IOH PD TSOLDER TSTG TOPR Rating −0.5 to 4.0 −0.5 to VCC + 0.5 2 15 −2 −15 80 −80 600 260 −65 to 150 −20 to 70 Unit V V mA mA mA mA mA mA mW °C °C °C Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, the device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Solderability of lead-free products Test parameter Solderability (1) Use of Sn-37Pb solder Bath Solder bath temperature =230°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature =245°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (use lead-free) Pass: solderability rate until forming ≥ 95% Test condition Note 92CH21-464 2007-02-28 TMP92CH21 4.2 DC Electrical Characteristics (1/2) VCC = 3.3 ± 0.3V/X1 = 6 to 40 MHz/Ta = −20 to 70°C VCC = 2.7 − 3.6V/X1 = 6 to 27 MHz/Ta = −20 to 70°C Parameter Power supply voltage (DVCC = AVCC) (DVSS = AVSS = 0 V) Input low voltage for D0 to D7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) Input low voltage for P60 to P67, P71 to P72, P75 to P76, P90, P93 to P94, PC6 to PC7, PG0 to PG3, PJ5 to PJ6, PL4 to PL7 Input low voltage for P91 to P92, P96 to P97, PA0 to PA7, PC0 to PC3, PF0 to PF2, RESET Symbol VCC Min 3.0 Typ. Max 3.6 Unit V Condition X1 = 6 to 40 MHz X1 = 6 to 27 MHz XT1 = 30 to 34 kHz 2.7 VIL0 0.6 VIL1 −0.3 0.3 × VCC V VIL2 0.25 × VCC Input low voltage for AM0 to AM1 Input low voltage for X1, XT1 Input high voltage for D0 to D7 P10 to P17 (D8 to D15) P20 to P27 (D16 to D23) P30 to P37 (D24 to D31) Input high voltage for P60 to P67, P71 to P72, P75 to P76, P90, P93 to P94, PC6 to PC7, PG0 to PG3, PJ5 to PJ6, PL4 to PL7 Input high voltage for P91 to P92, P96 to P97, PA0 to PA7, PC0 to PC3, PF0 to PF2, RESET VIL3 VIL4 0.3 0.2 × VCC VIH0 2.0 VIH1 0.7 × VCC VCC + 0.3 V VIH2 0.75 × VCC Input high voltage for AM0 to AM1 Input high voltage for X1, XT1 VIH3 VIH4 VCC − 0.3 0.8 × VCC 92CH21-465 2007-02-28 TMP92CH21 DC Electrical Characteristics (2/2) Parameter Output low voltage Output high voltage Internal resistor (ON) MX, MY pins Internal resistor (ON) PX, PY pins Input leakage current Output leakage current Power down voltage at STOP (for internal RAM backup) Pull-up resistor for RESET , PA0 to PA7 Programmable pull down resistor for P96 Pin capacitance Schmitt width for P91 to P92, P96 to P97, PA0 to PA7,PC0 to PC3, PF0 to PF2, RESET NORMAL (Note 2) IDLE2 IDLE1 SLOW (Note 2) IDLE2 IDLE1 STOP ICC Symbol VOL VOH1 VOH2 IMon IMon ILI ILO VSTOP RRST Min 2.4 0.9 × VCC Typ. Max 0.45 Unit IOL = 1.6 mA V IOH = −400 μA IOH = −20 μA VOL = 0.2V Ω Condition 30 30 0.02 0.05 1.8 ±5 ±10 3.6 μA μA V VCC = 3.0 to 3.6 V VOH = VCC −0.2V 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 V VIL2 = 0.2 × VCC, VIH2 = 0.8 × VCC 80 RKH CIO VTH 0.4 1.0 500 kΩ 10 pF fc = 1 MHz V VCC = 3.6 V, fc = 40 MHz mA Ta ≤ 70°C Ta ≤ 50°C Ta ≤ 70°C μA Ta ≤ 50°C Ta ≤ 70°C Ta ≤ 50°C Ta ≤ 70°C Ta ≤ 50°C VCC = 3.6 V VCC = 3.6 V, fs = 32 kHz 33 16 4.3 25.2 15.1 4.3 0.2 65 26 8.7 110 70 80 30 60 20 50 15 Note 1: Typical values are for when Ta = 25°C and VCC = 3.3 V unless otherwise noted. Note 2: ICC measurement conditions (NORMAL, SLOW): All functions are operational; output pins are opened and input pins are fixed. CL = 30 pF is loaded to data and address bus. 92CH21-466 2007-02-28 TMP92CH21 4.3 AC Characteristics Basic Bus Cycle Read cycle Variable Min 1 2 3 4 OSC period (X1/X2) System clock period ( = T) SDCLK low width SDCLK high width A0 to A23 valid → D0 to D31 Input at 0 waits A0 to A23 valid → D0 to D31 Input at 1 wait RD falling 4.3.1 No. Parameter Symbol tOSC tCYC tCL tCH tAD (3.0 V) tAD (2.7 V) tAD3 (3.0 V) tAD3 (2.7 V) tRD tRD3 tRR tRR3 tAR tRK tHA tHR tTK tKT tSBA tRRH 40 MHz 36 MHz 27 MHz 25 50 10 10 70 − 120 − 45 95 55 105 5 5 0 0 15 5 27.7 55.5 12.7 12.7 81 − 136.5 − 53.3 108.8 63.2 118.8 7.7 7.7 0 0 15 5 53.3 12.7 37.0 74.0 22 22 − 113 − 187 81 155 91 165 17 17 0 0 15 5 81 22 Unit Max 166.7 333.3 25 50 0.5 T − 15 0.5 T − 15 5-1 5-2 6-1 6-2 7-1 7-2 8 9 10 11 12 13 14 15 2.0 T − 30 2.0 T − 35 3.0 T − 30 3.0 T − 35 1.5 T − 30 2.5 T − 30 1.5 T − 20 2.5 T − 20 0.5 T − 20 0.5 T − 20 0 0 15 5 1.5 T − 30 0.5 T − 15 → D0 to D31 Input at 0 waits RD falling → D0 to D31 Input at 1 wait RD low width at 0 waits RD low width at 1 wait A0 to A23 valid → RD falling RD falling → SDCLK rising A0 to A23 valid → D0 to D31 hold RD rising → D0 to D31 hold WAIT setup time WAIT hold time Data byte control access time for SRAM RD high width ns 45 10 Write cycle No. 16-1 16-2 17-1 17-2 18 19 20 21 Parameter D0 to D31 valid → WRxx rising at 0 waits D0 to D31 valid → WRxx rising at 1 wait WRxx low width at 0 waits WRxx low width at 1 wait A0 to A23 valid → WR falling WRxx falling → SDCLK rising WRxx rising → A0 to A23 hold WRxx rising → D0 to D31 hold → D0 to D31 output Symbol tDW tDW3 tWW tWW3 tAW tWK tWA tWD Variable Min 1.25T − 35 2.25T − 35 40 MHz 36 MHz 27 MHz 27.5 77.5 32.5 82.5 5 5 7.5 7.5 20 − 32.5 32.5 5 7.5 27.5 7.5 34.3 89.8 34.3 89.8 7.7 7.7 8.8 8.8 22.7 − 39.3 39.3 7.7 8.8 34.3 8.8 57.5 131.5 62.5 136.5 17 17 13.5 13.5 − 30 62.5 62.5 17 13.5 57.5 13.5 Unit Max 22 RD rising 23 Write pulse width for SRAM Data byte control to end of write 24 for SRAM 25 Address setup time for SRAM 26 Write recovery time for SRAM 27 Data setup time for SRAM 28 Data hold time for SRAM AC measuring condition 1.25T − 30 2.25T − 30 0.5T − 20 0.5T − 20 0.25T − 5 0.25T − 5 tRDO (3.0 V) 0.5T − 5 tRDO (2.7 V) 0.5T − 7 tSWP 1.25T − 30 tSBW tSAS tSWR tSDS tSDH 1.25T − 30 0.5T − 20 0.25T − 5 1.25T − 35 0.25T − 5 ns • Output: High = 0.7 VCC, Low = 0.3 VCC, CL = 50 pF • Input: High = 0.9 VCC, Low = 0.1 VCC Note: The figures in the “Variable” column cover the whole VCC range (2.7 V to 3.6 V). Exceptions are shown by the VCC (min), “(3.0 V)” or “(2.7 V)”, added to the “Symbol” column. 92CH21-467 2007-02-28 TMP92CH21 (1) Read cycle (0 waits) tOSC X1 tCYC tCH SDCLK tCL tTK WAIT tKT A0~A23 tAD CSn tHA R/ W tAR RD tRK tHR tRR tRD Data input tRRH D0~D31 tSBA SRxxB SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The above timing chart is an example. 92CH21-468 2007-02-28 TMP92CH21 (2) Write cycle (0 waits) tOSC X1 tCYC tCH SDCLK tCL tTK WAIT tKT A0~A23 CSn R/ W tAW WRxx tWK tWA tWW tDW D0~D31 Data output tSWR tWD tRDO RD tSDH tSBW SRxxB tSDS tSAS tSWP SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The above timing chart is an example. 92CH21-469 2007-02-28 TMP92CH21 (3) Read cycle (1 wait) SDCLK WAIT A0 to A23 tAD3 CSn R/ W RD tRR3 tRD3 D0 to D31 Data input (4) Write cycle (1 wait) SDCLK WAIT A0 to A23 CSn R/ W WRxx tWW3 tDW3 D0 to D31 Data output RD 92CH21-470 2007-02-28 TMP92CH21 4.3.2 Page ROM Read Cycle (1) 3-2-2-2 mode No. 1 2 3 4 5 6 Parameter System clock period ( = T) A0, A1 → D0 to D31 input A2 to A23 → D0 to D31 input RD falling → D0 to D31 input A0 to A23 Invalid → D0 to D31 hold RD rising → D0 to D31 hold Symbol tCYC tAD2 tAD3 tRD3 tHA tHR 50 Variable Min Max 166.7 2.0T − 50 3.0T − 50 2.5T − 45 40 MHz 36 MHz 27 MHz Unit 50 50 100 80 0 0 55.5 61 116.5 93.8 0 0 74 98 172 140 0 0 ns 0 0 AC measuring condition • Output: High = 0.7 VCC, Low = 0.3 VCC, CL = 50 pF • Input: High = 0.9 VCC, Low = 0.1 VCC SDCLK tCYC A0 to A23 +0 +1 +2 +3 CS2 tAD3 RD tAD2 tAD2 tAD2 tHA tRD3 D0 to D31 Data input tHA Data input tHA Data input tHA Data input tHR 92CH21-471 2007-02-28 TMP92CH21 4.3.3 No. SDRAM Controller AC Characteristics Parameter Symbol tRC tRAS tRCD tRP tRRD tWR tCK tCH tCL tAC tOH tDS tDH tAS tAH tCKS tCMS tCMH tRSC 2T 2T T T 3T T T 0.5T − 15 0.5T − 15 T − 30 0 T − 35 T−5 0.75T − 30 0.25T − 9 0.5T − 15 0.5T − 15 0.5T − 15 T Variable Min Max 12210 40 MHz 36 MHz 27 MHz 100 100 50 50 150 50 50 10 10 20 0 15 45 7.5 3.5 10 10 10 50 111 111 55.5 55.5 166.5 55.5 55.5 12.7 12.7 25.5 0 20.5 50.5 11.6 4.8 12.7 12.7 12.7 55.5 148 148 74 74 222 74 74 22 22 44 0 39 69 25.5 9.5 22 22 22 74 Unit 1 Ref/active to ref/active command period 2 Active to precharge command period 3 Active to read/write command delay time 4 Precharge to active command period 5 Active to active command period 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Write recovery time (CL* = 2) Clock cycle time (CL* = 2) Clock high level width Clock low level width Access time from clock (CL* =2) Output data hold time Data in setup time Data in hold time Address setup time Address hold time CKE setup time Command setup time Command hold time Mode register set cycle time ns CL*: CAS latency. AC measuring conditions • Output level: High = 0.7 VCC, Low = 0.3 VCC, CL = 50 pF • Input level: High = 0.9 VCC, Low = 0.1 VCC 92CH21-472 2007-02-28 TMP92CH21 (1) SDRAM read timing (CPU access or LCDC normal access) tCK SDCLK tCH SDxxDQM tCMS SDCS tCL tRP tRCD tRAS tRP tCMS tCMH tCMH SDRAS tRRD SDCAS SDWE 16-bit data bus A1 to A10 tAS Row tAH Column tAS tAH Column A11 Row A12 to A15 Row Column tAC tOH Data input D0 to D15 32-bit data bus A1 to A11 tAS Row tAH Column tAS tAH Column A12 Row A13 to A15 Row Column tAC tOH D0 to D31 Data input 92CH21-473 2007-02-28 TMP92CH21 (2) SDRAM write timing (CPU access) tCK SDCLK tCH SDxxDQM tCMS SDCS tCL tRP tRCD tCMS tWR tRP tRRD tCMH SDRAS tCMH SDCAS tRAS SDWE 16-bit data bus A1 to A12 tAS Row tAH Column tAS tAH Column A11 Row A12 to A15 Row tDS Column tDH Data output D0 to D15 32-bit data bus A1 to A11 tAS Row tAH Column tAS tAH Column A12 Row A13 to A15 Row tDS Column tDH Data output D0 to D31 92CH21-474 2007-02-28 TMP92CH21 (3) SDRAM burst read timing (Start of burst cycle) tCK SDCLK tCMS SDxxDQM tRP SDCS tRCD tCMS SDRAS tCMH tCMS tCMH SDCAS tCMH SDWE tAS A1 to A11 or A1 to A10 227 tAH tAS Row tAH tAS Column A12 or A11 Row Column A13 to A15 or A12 to A15 0 Row tAC tAC Data input tOH tAC Data input tOH Data input D0 to D31 92CH21-475 2007-02-28 TMP92CH21 (4) SDRAM burst read timing (End of burst cycle) tCK SDCLK tCMH SDxxDQM tCMS SDCS tCMS tRSC tRC tCMH SDRAS tCMS SDCAS tCMH SDWE tAS A1 to A11 or A1 to A10 Column 220 Column A12 or A11 Column Column A13 to A15 or A12 to A15 Row tAC 0 tAC Data input tOH Data input tOH Column D0 to D31 Data input tOH 92CH21-476 2007-02-28 TMP92CH21 (5) SDRAM initialize timing tCK SDCLK tCH SDxxDQM tCMS SDCS tCL tRSC tRC tCMS SDRAS tCMS SDCAS tCMH tCMH tCMH SDWE tAS A1 to A12 tAH tAS 220 A20 to A23 (BS0 and BS1) 92CH21-477 2007-02-28 TMP92CH21 (6) SDRAM refresh timing tCK SDCLK tRC SDxxDQM tCMS SDCS tRC tCMH SDRAS SDCAS SDWE (7) SDRAM self refresh timing tCK SDCLK tCKS SDCKE tCKS tRC SDxxDQM tCMS SDCS tCMH SDRAS SDCAS SDWE 92CH21-478 2007-02-28 TMP92CH21 4.3.4 No. 1 2 3 4 5 6 NAND Flash Controller AC Characteristics Parameter Symbol Min Variable Max (1 + n) T − 25 (1 + n) T − 30 38 25 − 0 17.5 132.5 10.5 43.5 30.5 − 0 21.6 150.3 11.8 62 − 44 0 35.5 210.5 16.5 40 MHz 36 MHz 27 MHz Unit NDRE low width NDRE data access time Read data hold time NDWE low width Write data setup time Write data hold time AC measuring conditions tRP (1 + n) T − 12 tREA (3.0 V) tREA (2.7 V) 0 tOH tWP (0.75 + n) T − 20 tDS tDH (3.25 + n) T − 30 0.25 T − 2 ns • Output level: High = 0.7 VCC, Low = 0.3 VCC, CL = 50 pF • Input level: High = 0.9 VCC, Low = 0.1 VCC Note 1: The “n” shown in “Variable” refers to the wait number which is set to NDnFSPR register. Example: When NDnFSPR = “0001”, tRP = (1 + n) T − 12 = 2T − 12 Note 2: The figures in the “Variable” column cover the whole VCC range (2.7 to 3.6V). Exceptions are shown by the VCC (min), “(3.0 V)” or “ (2.7 V)”, added to the ”Symbol” column. SDCLK A0 to A23 NDRE Read cycle NDWE tRP D0 to D7 Data input tREA NDRE tOH tWP Write cycle NDWE tDS D0 to D7 Data output tDH 92CH21-479 2007-02-28 TMP92CH21 4.3.5 Serial Channel Timing (1) SCLK input mode (I/O interface mode) Parameter Symbol Min tSCY tOSS tOHS tHSR tSRD tRDS Variable Max 16T tSCY/2 − 4T − 110 tSCY/2 + 2T + 0 3 T + 10 tSCY − 0 0 40 MHz 36 MHz 27 MHz Unit 0.8 90 500 160 800 0 0.888 114 554 175 888 0 1.184 186 740 232 1184 0 μs SCLK cycle Output data → SCLK rising/falling SCLK rising/falling → Output data hold SCLK rising/falling → Input data hold SCLK rising/falling → Input data valid Input data valid → SCLK rising/falling ns (2) SCLK output mode (I/O Interface mode) Parameter SCLK cycle (Programmable) Output data → SCLK rising/falling SCLK rising/falling → Output data hold SCLK rising/falling → Input data hold SCLK rising/falling → Input data valid Input data valid → SCLK rising/falling Symbol Min tSCY tOSS tOHS tHSR tSRD tRDS Variable Max 8192T 16 T tSCY/2 − 40 tSCY/2 − 40 0 1 T + 180 40 MHz 36 MHz 27 MHz Unit 0.8 360 360 0 570 230 0.888 404 404 0 654 233 1.184 552 552 0 967 253 μs ns tSCY − 1T − 180 tSCY SCLK Output mode/ Input rising mode SCLK (Input falling mode) tOSS Output data TXD 0 tSRD Input data RXD 0 Valid tRDS tHSR 1 Valid 2 Valid 3 Valid tOHS 1 2 3 4.3.6 Interrupt Operation Parameter Symbol Min tINTAL tINTAH 4 T + 40 4 T + 40 Variable Max 40 MHz 36 MHz 27 MHz Unit 240 240 262 262 336 336 ns INT0 to INT5 low width INT0 to INT5 high width 92CH21-480 2007-02-28 TMP92CH21 4.3.7 LCD Controller (SR mode) Parameter LCP0 clock period ( = tm) LCP0 high width LCP0 low width Data valid → LCP0 falling LCP0 falling → Data hold Symbol Min tCW tCWH tCWL tDSU tDHD Variable Max 2T 0.5 tm − 12 0.5 tm − 12 0.5 tm − 20 0.5 tm − 5 40 MHz 36 MHz 27 MHz Unit 100 38 38 30 45 111 43.5 43.5 35.5 50.5 148 62 62 54 69 ns tCW tCWH LCP0 tDSU LD0 to LD11 tDHD tCWL LD0 to LD11 output 92CH21-481 2007-02-28 TMP92CH21 4.3.8 I2S Timing (I2S, SIO Mode) Parameter Symbol Min tCR tHB tLB tSD tHD Variable Max T 0.5 tCR − 15 0.5 tCR − 15 0.5 tCR − 15 0.5 tCR − 5 40 MHz 36 MHz 27 MHz Unit 50 10 10 10 20 55 12 12 12 22 74 22 22 22 32 I2SCKO clock period I2SCKO high width I2SCKO low width I2SDO, I2SWS setup time I2SDO, I2SWS hold time AC measuring conditions ns • Output level: High = 0.7 VCC, Low = 0.3 VCC, CL = 10 pF tCR tLB I2SCKO tHD I2SDO tSD tHD tHB I2SWS 4.3.9 USB Timing (Full-speed) VCC = 3.3 ± 0.3 V/fUSB = 48 MHz/Ta = −20 to 70°C Parameter Rising time for D+, D− Falling time for D+, D− Output signal crossover voltage AC measuring conditions Symbol tR tF VCRS Min 4 4 1.3 Max 20 20 2.0 Unit ns V TMP92CH21 D+ D− R1 = 27 Ω R1 = 27 Ω Test point VCC R3 = 1.5 kΩ R2 = 15 kΩ CL = 50 pF D+, D− VCRS tR 90% 90% 10% tF 92CH21-482 2007-02-28 TMP92CH21 4.4 AD Conversion Characteristics Parameter Symbol VREFH VREFL AVCC AVSS AVIN Min VCC − 0.2 VSS VCC VSS VREFL Typ. VCC VSS VCC VSS Max VCC VSS + 0.2 VCC VSS VREFH Unit Analog reference voltage (+) Analog reference voltage (−) AD converter power supply voltage AD converter ground Analog input voltage Analog current for analog reference voltage = 1 Analog current for analog reference voltage = 0 Total error (Quantize error of ± 0.5 LSB is included.) V 0.8 IREF 0.02 ET ±1.0 1.35 5.0 ±4.0 mA μA LSB Note 1: 1LSB = (VREFH – VREFL) / 1024 [V] Note 2: Minimum frequency for operation AD converter operation is guaranteed only when using fc (high-frequency oscillator). fs is not guaranteed. However, operation is guaranteed if the clock frequency selected by the clock gear is over 4MHz. Note 3: The value for Icc includes the current which flows through the AVCC pin. 92CH21-483 2007-02-28 TMP92CH21 4.5 Recommended Oscillation Circuit The TMP92CH21 has been evaluated by the oscillator vender below. Use this information when selecting external parts. Note: The total load value of the oscillator is the sum of external loads (C1 and C2) and the floating load of the actual assembled board. There is a possibility of operating error when using C1 and C2 values in the table below. When designing the board, design the minimum length pattern around the oscillator. We also recommend that oscillator evaluation be carried out using the actual board. (1) Connection example X1 Rf Rd Rd X2 XT1 XT2 C1 C2 C1 C2 High-frequency oscillator Low-frequency oscillator (2) Recommended ceramic oscillator: Murata Manufacturing Co., Ltd. Oscillation MCU Frequency [MHZ] 2.00 4.00 6.00 9.00 CSTCC2M00G56-R0 CSTCR4M00G55-R0 CSTLS4M00G56-B0 CSTCR6M00G55-R0 CSTLS6M00G56-B0 CSTCE9M00G55-R0 CSTLS9M00G56-B0 CSTCE10M0G52-R0 10.00 CSTCE10M0G55-R0 CSTLS10M0G53-B0 CSTLS10M0G56-B0 12.00 20.00 CSTCE12M5G52-R0 CSTCE20M0V53-R0 Oscillator Product Number Parameter of Elements C1 [pF] (47) (39) (47) (39) (47) (33) (47) (10) (33) (15) (47) (10) (15) C2 [pF] (47) (39) (47) (39) (47) (33) (47) (10) (33) (15) (47) (10) (15) 0 Open 1.8 ∼ 2.7 2.7 ∼ 3.6 1.8 ∼ 2.7 2.7 ∼ 3.6 1.8 ∼ 2.7 2.7 ∼ 3.6 -20 ∼ +80 2.7 ∼ 3.6 Rd [Ω] Running Condition Voltage [V] 1.8 ∼ 2.7 TC [°C] Rf [Ω] TMP92CH21FG Note 1: The figure in parentheses ( ) under C1 and C2 is the built-in condenser type. Note 2: The product numbers and specifications of the oscillators made by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL: http://www.murata.co.jp 92CH21-484 2007-02-28 TMP92CH21 (3) Recommended ceramic oscillator: TDK Co., Ltd. Oscillation MCU Frequency [MHZ] 4.00 6.00 TMP92CH21FG Parameter of Elements Oscillator Product Number C1 [pF] FCR4.0MC5 FCR6.0MC5 FCR10.MC5 CCR20.0MXC7 CCR40.0MXC7 − − − − − C2 [pF] − − − − − Rf [Ω] − − − − − Rd [Ω] − − − − − Running Condition Voltage [V] TC [°C] 10.00 20.00 40.00 2.7 ~ 3.6 −20 ~ 70 Note: The product numbers and specifications of the oscillators made by TDL Co.,Ltd. are subject change. For up-to-date information, please refer to the following URL; http://www.tdk.co.jp 92CH21-485 2007-02-28 TMP92CH21 5. Table of Special function registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 001FFFH. (1) I/O Port (2) Interrupt control (3) Memory controller (4) MMU (5) Clock gear, PLL (6) LCD controller (7) Touch screen I/F (8) SDRAM controller (9) 8-bit timer (10) 16-bit timer (11) UART/serial channel (12) USB controller (13) AD converter (14) Watchdog timer (15) RTC (Real time clock) (16) Melody/alarm generator (17) NAND flash controller (18) I2S Table layout Symbol Name Address 7 6 1 0 Bit symbol Read/Write Initial value after reset Remarks Note: “Prohibit RMW” in the table means that you cannot use RMW instructions on these registers. Example: When setting bit0 only of the register P0CR, the instruction “SET 0, (PxCR)” cannot be used. The LD (transfer) instruction must be used to write all eight bits. Read/Write R/W: R: W: W* : Prohibit RMW: Both read and write are possible. Only read is possible. Only write is possible. Both read and write are possible (when this bit is read as1) Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instructions are read-modify-write instructions.) Read-modify-write is prohibited when controlling the pull-up resistor. R/W*: 92CH21-486 2007-02-28 TMP92CH21 Table 5.1 I/O Register Address Map [1] Port Address 0000H 1H 2H 3H 4H P1 5H 6H P1CR 7H P1FC 8H P2 9H P2FC2 AH P2CR BH P2FC CH P3 DH EH P3CR FH P3FC Name Address 0010H P4 1H 2H Name Address 0020H P8 Name Address 0030H PC 1H Name 1H P8FC2 2H 3H P8FC 4H P9 5H P9FC2 6H P9CR 7H P9FC 8H PA 9H AH PACR BH PAFC CH DH EH FH 2H PCCR 3H PCFC 4H 5H 6H 7H 8H 9H AH BH CH PF DH PFFC2 EH PFCR FH PFFC 3H P4FC 4H P5 5H 6H 7H P5FC 8H P6 9H AH P6CR BH P6FC CH P7 DH EH P7CR FH P7FC Address 0040H PG 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH PJ DH Name Address 0050H PK 1H 2H Name Address 0080H Name Address 1H 2H Name 0090H PGDR 1H P1DR 2H P2DR 3H P3DR 4H P4DR 5H P5DR 6H P6DR 7H P7DR 8H P8DR 9H P9DR AH PADR BH CH PCDR DH EH FH PFDR 3H PKFC 4H PL 5H 6H PLCR 7H PLFC 8H PM 9H AH BH PMFC CH DH EH FH 3H PJDR 4H PKDR 5H PLDR 6H PMDR 7H 8H 9H AH BH CH DH EH FH EH PJCR FH PJFC Note: Do not access un-named addresses. 92CH21-487 2007-02-28 TMP92CH21 [2] INTC Address Name Address Name Address Name Address Name 00D0H INTE12 1H INTE34 2H 3H 4H INTETA01 5H INTETA23 6H 7H 8H INTETB01 9H AH INTETBO0 BH INTES0 CH INTES1 DH EH FH 00E0H Reserved 1H Reserved 2H Reserved 3H INTEUSB 4H Reserved 5H INTALM01 6H INTALM23 7H INTALM4 8H INTERTC 9H INTEKEY AH INTLCD BH INTE5I2S CH INTEND01 DH Reserved EH INTEP0 FH Reserved 00F0H INTE0AD 1H INTETC01 2H INTETC23 3H INTETC45 4H INTETC67 5H SIMC 6H IIMC 7H INTWDT 8H INTCLR 9H AH BH CH DH EH FH 0100H DMA0V 1H DMA1V 2H DMA2V 3H DMA3V 4H DMA4V 5H DMA5V 6H DMA6V 7H DMA7V 8H DMAB 9H DMAR AH Reserved BH CH DH EH FH [3] MEMC Address Name Address 0150H 1H 2H 3H 4H 5H 6H 7H 8H BEXCSL 9H BEXCSH AH BH CH DH EH FH [4] MMU Name Address 0160H 1H 2H 3H 4H 5H 6H PMEMCR 7H BROMCR 8H 9H AH BH CH DH EH FH Name Address Name 0140H B0CSL 1H B0CSH 2H MAMR0 3H MSAR0 4H B1CSL 5H B1CSH 6H MAMR1 7H MSAR1 8H B2CSL 9H B2CSH AH MAMR2 BH MSAR2 CH B3CSL DH B3CSH EH MAMR3 FH MSAR3 01D0H LOCALPX 1H LOCALPY 2H 3H LOCALPZ 4H LOCALLX 5H LOCALLY 6H 7H LOCALLZ 8H LOCALRX 9H LOCALRY AH BH LOCALRZ CH LOCALWX DH LOCALWY EH FH LOCALWZ Note: Do not access un-named addresses. 92CH21-488 2007-02-28 TMP92CH21 [5] CGEAR, PLL Address Name 10E0H SYSCR0 1H SYSCR1 2H SYSCR2 3H EMCCR0 4H EMCCR1 5H EMCCR2 6H Reserved 7H 8H PLLCR0 9H PLLCR1 AH BH CH DH EH FH [6] LCDC1 Address Name Address 0290H 1H LCDRP10 2H LCDRP32 3H LCDRP54 4H LCDRP76 5H LCDGP10 6H LCDGP32 7H LCDGP54 8H LCDGP76 9H LCDBP10 AH LCDBP32 BH CH DH EH FH Name 0280H LCDMODE0 1H LCDMODE1 2H LCDFFP 3H LCDDVM 4H LCDSIZE 5H LCDCTL0 6H LCDCTL1 7H LCDSCC 8H LCDCCR0 9H LCDCCR1 AH LCDCCR2 BH CH DH EH FH [6] LCDC2 Address Name Address Name Address Name Address Name 02A0H LSARAL 1H LSARAM 2H LSARAH 3H CMNAL 4H CMNAH 5H 6H LSARBL 7H LSARBM 8H LSARBH 9H CMNBL AH CMNBH BH CH LSARCL DH LSARCM EH LSARCH FH 02B0H LCDOE00 1H LCDOE01 2H LCDOE02 3H LCDOE03 4H LCDOE04 5H LCDOE05 6H 7H 8H 9H AH BH CH DH EH FH 02C0H LCDOE10 1H LCDOE11 2H LCDOE12 3H LCDOE13 4H LCDOE14 5H LCDOE15 6H 7H 8H 9H AH BH CH DH EH FH 02D0H LCDOE20 1H LCDOE21 2H LCDOE22 3H LCDOE23 4H LCDOE24 5H LCDOE25 6H 7H 8H 9H AH BH CH DH EH FH Note: Do not access un-named addresses. 92CH21-489 2007-02-28 TMP92CH21 [7] TSI Address Name 01F0H TSICR0 1H TSICR1 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [8] SDRAMC Address Name 0250H SDACR1 1H SDACR2 2H SDRCR 3H SDCMM 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [9] 8-bit timer Address 1H 2H TA0REG 3H TA1REG 4H TA01MOD 5H TA01FFCR 6H 7H 8H TA23RUN 9H AH TA2REG BH TA3REG CH TA23MOD DH TA3FFCR EH FH [10] 16-bit timer Address 1H 2H TB0MOD 3H TB0FFCR 4H 5H 6H 7H 8H TB0RG0L 9H TB0RG0H AH TB0RG1L BH TB0RG1H CH TB0CP0L DH TB0CP0H EH TB0CP1L FH TB0CP1H Name Name 1100H TA01RUN 1180H TB0RUN [11] SIO Address Name 1200H SC0BUF 1H SC0CR 2H SC0MOD0 3H BR0CR 4H BR0ADD 5H SC0MOD1 6H 7H SIRCR 8H SC1BUF 9H SC1CR AH SC1MOD0 BH BR1CR CH BR1ADD DH SC1MOD1 EH FH Note: Do not access un-named addresses. 92CH21-490 2007-02-28 TMP92CH21 [12] USB controller (1/2) Address to Name RAM Address Name Address Name Address 07A0H Name 0500H Descriptor067FH (384 bytes) 0780H ENDPOINT0 1H ENDPOINT1 2H ENDPOINT2 3H ENDPOINT3 4H 5H 6H 7H 8H 9H EP1_MODE AH EP2_MODE BH EP3_MODE CH DH EH FH 0790H EP0_STATUS 1H EP1_STATUS 2H EP2_STATUS 3H EP3_STATUS 4H 5H 6H 7H 8H EP0_SIZE_L_A 9H EP1_SIZE_L_A AH EP2_SIZE_L_A BH EP3_SIZE_L_A CH DH EH FH 1H EP1_SIZE_L_B 2H EP2_SIZE_L_B 3H EP3_SIZE_L_B 4H 5H 6H 7H 8H 9H EP1_SIZE_H_A AH EP2_SIZE_H_A BH EP3_SIZE_H_A CH DH EH FH Address 07B0H Name Address Name Address Name 07C0H bmRequest Type 1H bRequest 2H wValue_L 3H wValue_H 4H wIndex_L 5H wIndex_H 6H wLength_L 7H wLength_H 8H Setup Received 9H Current_Config AH Standard Request BH Request CH DATASET1 DH DATASET2 EH USB_STATE FH EOP 07D0H COMMAND 1H EPx_SINGLE1 2H 3H EPx_BCS1 4H 5H 6H INT_Control 7H 8H Standard Request Mode 9H Request Mode AH BH CH DH EH ID_CONTROL FH ID_STATE 1H EP1_SIZE_H_B 2H EP2_SIZE_H_B 3H EP3_SIZE_H_B 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Note: Do not access un-named addresses. 92CH21-491 2007-02-28 TMP92CH21 [12] USB controller (2/2) Address Name Address Name 07E0H Port_Status 1H FRAME_L 2H FRAME_H 3H ADDRESS 4H 5H 6H USBREADY 7H 8H Set Descriptor STALL 9H AH BH CH DH EH FH 07F0H USBINTFR1 1H USBINTFR2 2H USBINTFR3 3H USBINTFR4 4H USBINTMR1 5H USBINTMR2 6H USBINTMR3 7H USBINTMR4 8H USBCR1 9H AH BH CH DH EH FH Note: Do not access un-named addresses. 92CH21-492 2007-02-28 TMP92CH21 [13] 10-bit ADC Address Name Address 12B0H 1H 2H 3H 4H 5H 6H 7H 8H ADMOD0 9H ADMOD1 AH ADMOD2 BH Reserved CH DH EH FH [14] WDT Name Address Name 1300H WDMOD 1H WDCR 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 12A0H ADREG0L 1H ADREG0H 2H ADREG1L 3H ADREG1H 4H ADREG2L 5H ADREG2H 6H ADREG3L 7H ADREG3H 8H Reserved 9H Reserved AH Reserved BH Reserved CH Reserved DH Reserved EH Reserved FH Reserved [15] RTC Address Name 1320H SECR 1H MINR 2H HOURR 3H DAYR 4H DATER 5H MONTHR 6H YEARR 7H PAGER 8H RESTR 9H AH BH CH DH EH FH [16] MLD Address Name 1330H ALM 1H MELALMC 2H MELFL 3H MELFH 4H ALMINT 5H 6H 7H 8H 9H AH BH CH DH EH FH Note: Do not access un-named addresses. 92CH21-493 2007-02-28 TMP92CH21 [17] NAND flash controller Address 1CC0H 1H 2H 3H 4H ND0FMCR 5H 6H 7H 8H ND0FSR 9H AH BH CH ND0FISR DH EH FH Name Address 1H 2H 3H Name Address 1CE0H 1H 2H 3H Name Address 1H 2H 3H Name 1CD0H ND0FIMR 1CF0H ND1FIMR 4H ND0FSPR 5H 6H 7H 8H ND0FRSTR 9H AH BH CH DH EH FH 4H ND1FMCR 5H 6H 7H 8H ND1FSR 9H AH BH CH ND1FISR DH EH FH 4H ND1FSPR 5H 6H 7H 8H ND1FRSTR 9H AH BH CH DH EH FH Address to 1EFFH Name ND1FDTR Address to 1CB5H Name ND1ECCRD Address 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Name 1D00H ND0FDTR, 1CB0H ND0ECCRD 01C0H NDCR Note: Do not access un-named addresses. 92CH21-494 2007-02-28 TMP92CH21 [18] I2S Address 1H 2H 3H 4H 5H 6H 7H 8H I2SBUFL 9H AH BH CH DH EH I2SCTL0 FH Name 0800H I2SBUFR Note: Do not access un-named addresses. 92CH21-495 2007-02-28 TMP92CH21 (1) I/O ports (1/7) Symbol P1 Name Port 1 Address 0004H 7 P17 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 P2 Port 2 0008H P3 Port 3 000CH P4 Port 4 0010H P5 Port 5 0014H P6 Port 6 0018H P7 Port 7 001CH P8 Port 8 0020H P9 Port 9 0024H PA Port A 0028H PC Port C 0030H PF Port F 003CH R/W Data from external port (Output latch register is cleared to “0”) P27 P26 P25 P24 P23 P22 P21 P20 R/W Data from external port (Output latch register is cleared to “0”) P37 P36 P35 P34 P33 P32 P31 P30 R/W Data from external port (Output latch register is cleared to “0”) P47 P46 P45 P44 P43 P42 P41 P40 R/W 0 0 0 0 0 0 0 0 P57 P56 P55 P54 P53 P52 P51 P50 R/W 0 0 0 0 0 0 0 0 P67 P66 P65 P64 P63 P62 P61 P60 R/W Data from external port (Output latch register is cleared to “0”) P76 P75 P74 P73 P72 P71 P70 R/W Data from external port Data from external 1 port (Output latch 0 0 (Output latch register is register is set to “1”) set to “1”) P87 P86 P85 P84 P83 P82 P81 P80 R/W 1 1 1 1 1 0/1 1 1 P97 P96 P95 P94 P93 P92 P91 P90 R/W R Data from 0 Data from external port (Output latch register is set to “1”) external port PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R Data from external port PC7 PC6 PC3 PC2 PC1 PC0 R/W R/W Data from external Data from external port port (Output latch (Output latch register is set to “1”) register is set to “1”) PF7 PF2 PF1 PF0 R/W R/W 1 PG3 Data from external port (Output latch register is set to “1”) PG2 PG1 PG0 R Data from external port PJ2 PJ1 PJ0 PG Port G 0040H PJ7 PJ6 PJ5 PJ4 R/W PJ3 PJ Port J 004CH 1 Data from external port (Output latch register is set to “1”) 1 1 PK3 1 PK2 R/W 0 PL2 0 PM2 R/W 1 1 PK1 0 PL1 0 PM1 1 1 PK0 0 PL0 0 PK Port K 0050H PL7 PL6 PL5 PL4 R/W Data from external port (Output latch register is set to “0”) 0 0 PL3 PL Port L 0054H PM Port M 0058H 92CH21-496 2007-02-28 TMP92CH21 (1) I/O ports (2/7) Symbol P1CR Name Port 1 control register Address 0006H (Prohibit RMW) 7 P17C 0 6 P16C 0 5 P15C 0 4 P14C W 0 0: Input 3 P13C 0 1: Output 2 P12C 0 1 P11C 0 0 P10C 0 P1F W 0/1 0:Port 1:Data bus (D8 to D15) P1FC Port 1 function register 0007H (Prohibit RMW) P27C P2CR Port 2 control register 000AH (Prohibit RMW) 0 P26C 0 P25C 0 P24C W 0 0: Input P23C 0 1: Output P22C 0 P21C 0 P20C 0 P2F W 0/1 0:Port 1:Data bus (D16 to D23) P2FC Port 2 function register 000BH (Prohibit RMW) P27F2 P2FC2 Port 2 function register2 0009H (Prohibit RMW) 0 P37C 0 P26F2 0 P36C 0 P25F2 0 P24F2 W 0 P23F2 0 P22F2 0 P21F2 0 P31C 0 − W 0 P20F2 0 P30C 0 P3F 0/1 0:Port 1:Data bus (D24 to D31) P3CR Port 3 control register 000EH (Prohibit RMW) 0: CMOS output P35C P34C W 0 0 0: Input 1: Open-drain output P33C P32C 0 1: Output − 0 0 − 0 Always write “0” P3FC Port 3 function register 000FH (Prohibit RMW) P47F P4FC Port 4 function register 0013H (Prohibit RMW) 0/1 P57F P5FC Port 5 function register 0017H (Prohibit RMW) 0/1 P67C 0 P67F P6FC Port 6 function register 001BH (Prohibit RMW) 0/1 P46F 0/1 P56F 0/1 P66C 0 P66F 0/1 P45F 0/1 0: Port P55F 0/1 0: Port P65C 0 P65F 0/1 0: Port P44F W 0/1 P43F 0/1 P42F 0/1 P41F 0/1 P51F 0/1 P61C 0 P61F 0/1 P40F 0/1 P50F 0/1 P60C 0 P60F 0/1 1: Address bus (A0 to A7) P54F P53F P52F W 0/1 0/1 0/1 1: Address bus (A8 to A15) P64C P63C P62C W 0 0 0 0: Input 1: Output P64F P63F P62F W 0/1 0/1 0/1 1: Address bus (A16 to A23) P6CR Port 6 control register 001AH (Prohibit RMW) 92CH21-497 2007-02-28 TMP92CH21 (1) I/O ports (3/7) Symbol Name Address 7 6 P76C W 0 P7CR Port 7 control register 001EH (Prohibit RMW) 0: Input port, WAIT 5 P75C W 0 0: Input port, NDR/ B 1: Output port, R/ W 4 3 2 P72C W 0 1 P71C W 0 0 1: Output port 0: Input port, 0: Input port 1: Output 1: Output port, port, NDWE @ NDRE @ = 0, = 0, WRLH @ WRLL @ = 1 = 0 P76F P7FC Port 7 function register 001FH (Prohibit RMW) 0 0: Port 1: WAIT P75F 0 0: Port 1: NDR/ B , R/ W P74F 0 0: Port 1: EA25 P73F W 0 0: Port 1: EA24 P72F 0 0: Port 1: NDWE , WRLU P71F 0 0: Port 1: NDRE , WRLL P70F 0/1 0: Port 1: RD P87F Port 8 function register 0023H (Prohibit RMW) 0 0: Port 1: CSZE P86F 0 0: Port 1: CSZD P85F 0 0: Port, P84F W 0 0: Port, WRUL 1: CSZB , ND0CE P83F 0 0: Port 1: CS3 P82F 0 0: Port, CSZA 1: CS2 , SDCS P81F 0 0: Port 1: CS1 P80F 0 0: Port 1: CS0 P8FC WRUU 1: CSZC , ND1CE P87F2 Port 8 function register2 0021H (Prohibit RMW) 0 0: 1: SRUUB P86F2 0 0: 1: SRULB P85F2 0 0: Port, CSZC 1: WRUU , ND1CE P84F2 W 0 0: Port, CSZB 1: WRUL , ND0CE − 0 P82F2 0 P81F2 0 0: 1: SDCS − 0 Always write “0” P8FC2 Always write 0: Port “0” 1: CSZA P95C 0 P9CR Port 9 control register 0026H (Prohibit RMW) 0: Output port, LGOE2 1: CLK32KO P94C 0 0: Input port, LGOE1 1: Output port P93C W 0 0:Input port, LGOE0 1: Output port P92C 0 0:Input port, SCLK0, CTS0 1: I2SWS, SCLK0 P91C 0 0: Input port, RXD0, I2SDO 1: Output port P90C 0 0: Input port, I2SCKO 1: Output port, TXD0 P97F Port 9 function register 0027H (Prohibit RMW) 0 P96F 0 P95F 0 P94F W 0 0: Port 1: LGOE1 P93F 0 0: Port 1: LGOE0 P92F 0 0: Port, SCLK0, CTS0 1: I2SWS, SCLK0 P91F 0 0: Port, RXD0 1: I2SDO P90F 0 0: Port 1: I2SCKO, TXD0 P9FC 0: Input port 0: Input port 0: Output 1: INT5 1: INT4 port, CLK32KO 1: LGOE2 P9FC2 Port 9 function register2 0025H (Prohibit RMW) P90FC2 W 0 0: CMOS 1: Open drain 92CH21-498 2007-02-28 TMP92CH21 (1) I/O ports (4/7) Symbol Name Port A control register Address 002AH (Prohibit RMW) 7 6 PA6C 5 PA5C 4 PA4C 3 PA3C 0 2 1 0 PACR 0 W 0 0 0: Input port or key-in 1: LD11 to LD8 output PA5F PA4F W PAFC Port A function register 002BH (Prohibit RMW) PA7F 0 PC7C W 0 PA6F 0 PC6C 0 0: Input port, KO8 1: Output port, LDIV PA3F PA2F PA1F 0 PC1C W 0 PA0F 0 PC0C 0 0: Input port, INT0 1: Output port, TA1OUT 0 0 0: Key-in disable 0 0 1: Key-in enable PC3C 0 0: Input port, INT3 1: Output port PC2C 0 PCCR Port C control register 0032H (Prohibit RMW) 0: Input port, CSZF 1: Output port, LCP1 0: Input 0: Input port, port, INT2 INT1 1: Output 1: Output port, port, TB0OUT0 TA3OUT PC7F Port C function register 0033H (Prohibit RMW) W 0 0: Port 1: CSZF , LCP1 PC6F 0 0: 3states 1: KO8, LDIV PC3F 0 0: Port 1: INT3 PC2F W 0 0: Port 1: INT2, TB0OUT0 PC1F 0 0: Port 1: INT1, TA3OUT PC0F 0 0: Port 1: INT0, TA1OUT PCFC PF2C 0 Port F control register 003EH (Prohibit RMW) 0: Input port, SCLK1, CTS1 , SCLK0, CTS0 1: Output port, SCLK0 PF1C W 0 0: Input port, RXD0, RXD1, 1: Output port PF0C 0 0: Input port, TXD1 1: Output port, TXD0 PFCR PF7F W 1 PFFC Port F function register 003FH (Prohibit RMW) 0: Port 1: SDCKE PF2F 0 0: Port, SCLK1, CTS1 , SCLK0, CTS0 1: SCLK0, SCLK1 PF1F W 0 Select RXD0 pin 0: Port F1 1: Port 91 PF0F 0 0: Port 1: TXD1, TXD0 PF0F2 W PFFC2 Port F function register2 003DH (Prohibit RMW) 0 Output buffer 0: CMOS 1: Open-drain 92CH21-499 2007-02-28 TMP92CH21 (1) I/O ports (5/7) Symbol PJCR Name Port J control register Address 004EH (Prohibit RMW) 7 6 PJ6C W 0 5 PJ5C 0 PF5F 0 4 3 2 1 0 0:Input 1: Output PF7F Port J function register 004FH (Prohibit RMW) 0 0: Port 1: SDCKE PF6F 0 PF4F W 0 0: Port 1: SDLUDQM PF3F 0 0: Port 1: SDLLDQM PF2F 0 0: Port 1: SDWE , SDWR PF1F 0 PF0F 0 PJFC 0: Port 0: Port 1: NDCLE, 1: NDALE, SDUUDQM SDULDQM 0: Port 0: Port 1: SDCAS , 1: SRRAS , SRLUB SRLLB PK3F PKFC Port K function register 0053H (Prohibit RMW) 0 0: Port 1: LBCD PK2F W 0 0: Port 1: LFR PK1F 0 0: Port 1: LLP PK0F 0 0: Port 1: LCP0 PL7C PLCR Port L control register 0056H (Prohibit RMW) 0 PL7F PLFC Port L function register 0057H (Prohibit RMW) 0 PL6C W 0 PL6F 0 PL5C 0 PL5F 0 0: Port PL4C 0 PL4F W 0 0 0 PM2F 0 PM1F W 0 0: Port 1: ALARM MLDALM 0: Input 1: Output PL3F PL2F PL1F PL0F 0 1: Data bus for LCDC (LD7 to LD0) PMFC Port M function register 005BH (Prohibit RMW) 0 0: Port 1: MLDALM output 92CH21-500 2007-02-28 TMP92CH21 (1) I/O ports (6/7) Symbol P1DR Name Port 1 drive register Address 0081H 7 P17D 1 P27D 6 P16D 1 P26D 1 P36D 1 P46D 1 P56D 1 P66D 1 P76D 5 P15D 1 4 P14D R/W 1 3 P13D 1 2 P12D 1 1 P11D 1 P21D 1 P31D 1 P41D 1 P51D 1 P61D 1 P71D 1 P81D 1 P91D 1 0 P10D 1 P20D 1 P30D 1 P40D 1 P50D 1 P60D 1 P70D 1 P80D 1 P90D 1 PA0D 1 PC0D 1 Input/Output buffer drive register for standby mode P25D P24D P23D P22D R/W 1 1 1 1 P2DR Port 2 drive register 0082H 1 P37D Input/Output buffer drive register for standby mode P35D P34D P33D P32D R/W 1 1 1 1 P3DR Port 3 drive register 0083H 1 P47D Input/Output buffer drive register for standby mode P45D P44D P43D P42D R/W 1 1 1 1 P4DR Port 4 drive register 0084H 1 P57D Input/Output buffer drive register for standby mode P55D P54D P53D P52D R/W 1 1 1 1 P5DR Port 5 drive register 0085H 1 P67D Input/Output buffer drive register for standby mode P65D P64D P63D P62D R/W 1 P75D 1 P85D 1 P95D 1 1 P74D 1 P84D R/W 1 P94D R/W 1 1 P73D R/W 1 P83D 1 P93D 1 1 P72D 1 P82D 1 P92D 1 P6DR Port 6 drive register 0086H 1 Input/Output buffer drive register for standby mode Port 7 drive register P7DR 0087H 1 P87D P86D 1 P96D 1 PA6D 1 PC6D R/W 1 Input/Output buffer drive register for standby mode Port 8 drive register P8DR 0088H 1 P97D Input/Output buffer drive register for standby mode Port 9 drive register P9DR 0089H 1 PA7D Input/Output buffer drive register for standby mode PA5D PA4D PA3D PA2D PA1D R/W 1 1 1 1 1 PADR Port A drive register 008AH 1 PC7D Input/Output buffer drive register for standby mode PC3D PC2D PC1D R/W 1 1 1 PCDR Port C drive register 008CH 1 Input/Output buffer drive register for standby mode Input/Output buffer drive register for standby mode 92CH21-501 2007-02-28 TMP92CH21 (1) I/O ports (7/7) Symbol Name Address 7 PF7D R/W 1 PFDR Port F drive register 008FH Input/Outp ut buffer drive register for standby mode 1 1 6 5 4 PF4D 3 PF3D 2 PF2D R/W 1 1 PF1D 1 0 PF0D 1 Input/Output buffer drive register for standby mode PG3D Port G drive register R/W 0090H 1 PG2D 1 PGDR Input/Output buffer drive register for standby mode PJ7D PJ6D 1 PJ5D 1 PJ4D R/W 1 1 1 PK3D 1 PK2D R/W 0094H 1 1 1 1 Input/Output buffer drive register for standby mode PL3D PL2D PL1D PL0D 1 1 PK1D 1 PK0D Input/Output buffer drive register for standby mode PJ3D PJ2D PJ1D PJ0D PJDR Port J drive register 0093H PKDR Port K drive register PLDR Port L drive register PL7D 0095H 1 PL6D 1 PL5D PL4D R/W 1 1 1 1 1 Input/Output buffer drive register for standby mode PM2D PM1D R/W 1 1 PMDR Port M drive register 0096H Input/Output buffer drive register for standby mode 92CH21-502 2007-02-28 TMP92CH21 (2) Interrupt control (1/4) Symbol INTE12 Name INT1 & INT2 enable Address 00D0H 7 I2C R 0 I4C R 0 ITA1C R 0 ITA3C R 0 ITB1C R 0 − 6 INT2 I2M2 0 INT4 I4M2 5 I2M1 R/W 0 4 I2M0 0 I4M0 0 ITA1M0 0 ITA3M0 0 ITB1M0 0 − 3 I1C R 0 I3C R 0 ITA0C R 0 ITA2C R 0 ITB0C R 0 ITBO0C R 0 IRX0C R 0 IRX1C R 0 IUSBC R 0 IA0C R 0 IA2C R 0 2 INT1 I1M2 0 INT3 I3M2 1 I1M1 R/W 0 0 I1M0 0 I3M0 0 ITA0M0 0 ITA2M0 0 ITB0M0 0 ITBO0M0 0 IRX0M0 0 IRX1M0 0 IUSBM0 0 IA0M0 0 IA2M0 0 INTE34 INT3 & INT4 enable 00D1H INTETA01 INTTA0 & INTTA1 enable INTTA2 & INTTA3 enable INTTB0 & INTTB1 enable INTTBO0 (Overflow) enable INTRX0 & INTTX0 enable INTRX1 & INTTX1 enable 00D4H INTETA23 00D5H INTETB01 00D8H I4M1 R/W 0 0 INTTA1 (TMRA1) ITA1M2 ITA1M1 R/W 0 0 INTTA3 (TMRA3) ITA3M2 ITA3M1 R/W 0 0 INTTB1 (TMRB1) ITB1M2 ITB1M1 R/W 0 0 − − − I3M1 R/W 0 0 INTTA0 (TMRA0) ITA0M2 ITA0M1 R/W 0 0 INTTA2 (TMRA2) ITA2M2 ITA2M1 R/W 0 0 INTTB0 (TMRB0) ITB0M2 ITB0M1 R/W 0 0 INTTBO0 ITBO0M2 ITBO0M1 R/W 0 0 INTRX0 IRX0M2 IRX0M1 R/W 0 0 INTRX1 IRX1M2 0 IUSBM2 0 IA0M2 0 IA2M2 0 IRX1M1 R/W 0 IUSBM1 R/W 0 IA0M1 R/W 0 INTALM2 IA2M1 R/W 0 INTETBO0 00DAH INTES0 00DBH ITX0C R 0 ITX1C R 0 − Always write “0” INTTX0 ITX0M2 ITX0M1 R/W 0 0 INTTX1 ITX1M2 0 − − ITX1M1 R/W 0 − ITX0M0 0 ITX1M0 0 − INTES1 00DCH INTUSB INTEUSB INTUSB enable 00E3H Always write “0” INTALM1 INTEALM01 INTALM0 IA1M0 0 IA3M0 0 INTALM0 & INTALM1 enable 00E5H IA1C R 0 IA3C R 0 IA1M2 0 IA3M2 0 IA1M1 R/W 0 INTEALM23 INTALM2 & INTALM3 enable INTALM3 00E6H IA3M1 R/W 0 92CH21-503 2007-02-28 TMP92CH21 (2) Interrupt control (2/4) Symbol INTEALM4 Name INTALM4 enable Address 00E7H 7 − 6 − − 5 − 4 − 3 IA4C R 0 IRC R 0 IKC R 0 ILCD1C R 0 I5C R 0 IND0C R 0 IP0C R 0 2 1 0 IA4M0 0 IRM0 0 IKM0 0 ILCDM0 0 I5M0 0 IND0M0 0 IP0M0 0 INTERTC INTRTC enable 00E8H − Always write “0” − − − Always write “0” − − − Always write “0” − − − Always write “0” INTI2S II2SM2 II2SM1 R/W 0 0 INTNDF1 IND1M2 IND1M1 R/W 0 0 − − − Always write “0” − INTEKEY INTKEY enable 00E9H − − INTELCD INTLCD enable 00EAH − − INTE5I2S INT5 & INTI2S enable INTNDF0 & INTNDF1 enable 00EBH II2SC R 0 IND1C R 0 − II2SM0 0 IND1M0 0 − INTEND01 00ECH INTEP0 INTP0 enable 00EEH INTALM4 IA4M2 IA4M1 R/W 0 0 INTRTC IRM2 IRM1 R/W 0 0 INTKEY IKM2 IKM1 R/W 0 0 INTLCD ILCDM2 ILCDM1 R/W 0 0 INT5 I5M2 I5M1 R/W 0 0 INTNDF0 IND0M2 IND0M1 R/W 0 0 INTP0 IP0M2 IP0M1 R/W 0 0 92CH21-504 2007-02-28 TMP92CH21 (2) Interrupt control (3/4) Symbol INTE0AD Name INT0 & INTAD enable INTTC0 & INTTC1 enable INTTC2 & INTTC3 enable INTTC4 & INTTC5 enable INTTC6 & INTTC7 enable Address 00F0H 7 IADC R 0 ITC1C R 0 ITC3C R 0 ITC5C R 0 ITC7C R 0 − W 0 Always write “0”. 6 5 4 IADM0 0 ITC1M0 0 ITC3M0 0 ITC5M0 0 ITC7M0 0 3 I0C R 0 ITC0C R 0 ITC2C R 0 ITC4C R 0 ITC6C R 0 2 INT0 I0M2 1 0 I0M0 0 ITC0M0 0 ITC2M0 0 ITC4M0 0 INTETC01 00F1H INTETC23 00F2H INTAD IADM2 IADM1 R/W 0 0 INTTC1 (DMA1) ITC1M2 ITC1M1 R/W 0 0 INTTC3 (DMA3) ITC3M2 ITC3M1 R/W 0 0 INTTC5 (DMA5) ITC5M2 ITC5M1 R/W 0 0 INTTC7 (DMA7) ITC7M2 ITC7M1 R/W 0 0 I0M1 R/W 0 0 INTTC0 (DMA0) ITC0M2 ITC0M1 R/W 0 0 INTTC2 (DMA2) ITC2M2 ITC2M1 R/W 0 0 INTTC4 (DMA4) ITC4M2 ITC4M1 R/W 0 0 INTETC45 00F3H INTETC67 00F4H SIMC SIO interrupt mode control 00F5H (Prohibit RMW) INTTC6 (DMA6) ITC6M2 ITC6M1 ITC6M0 R/W 0 0 0 IR1LE IR0LE W W 1 1 0: INTRX1 0: INTRX0 edge edge mode mode 1: INTRX1 1: INTRX0 level level mode mode I0EDGE 0 INT0 edge 0: Rising 1: Falling I0LE R/W 0 0: INT0 edge mode 1:INT0 level mode − − CLRV1 0 − 0 Always write “0”. I5EDGE 0 INT5 edge 0: Rising 1: Falling I4EDGE 0 INT4 edge 0: Rising 1: Falling I3EDGE W 0 INT3 edge 0: Rising 1: Falling I2EDGE 0 INT2 edge 0: Rising 1: Falling I1EDGE 0 INT1 edge 0: Rising 1: Falling IIMC Interrupt input mode control 00F6H (Prohibit RMW) − INTWDT INTWD enable 00F7H − − − − ITCWD R 0 CLRV3 − − INTWD − − CLRV0 0 Always write “0” Interrupt clear control 00F8H (Prohibit RMW) CLRV7 0 CLRV6 0 CLRV5 0 CLRV4 CLRV2 0 INTCLR W 0 0 Interrupt vector 92CH21-505 2007-02-28 TMP92CH21 (2) Interrupt control (4/4) Symbol DMA0V Name DMA0 start vector Address 0100H 7 6 5 DMA0V5 0 DMA1V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 3 2 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 DMA4V1 0 DMA5V1 0 DMA6V1 0 DMA7V1 0 DBST1 0 DREQ1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA4V0 0 DMA5V0 0 DMA6V0 0 DMA7V0 0 DBST0 0 DREQ0 0 DMA0V3 DMA0V2 R/W 0 0 DMA0 start vector DMA1V3 DMA1V2 R/W 0 0 DMA1 start vector DMA1V DMA1 start vector 0101H 0 DMA2V5 DMA2V DMA2 start vector 0102H DMA3V DMA3 start vector 0103H DMA4V DMA4 start vector 0104H DMA5V DMA5 start vector 0105H DMA6V DMA6 start vector 0106H DMA7V DMA7 start vector 0107H DBST7 DMAB DMA burst 0108H 0 DREQ7 0 DBST6 0 DREQ6 0 DMAR DMA request 0109H (Prohibit RMW) DMA2V3 DMA2V2 R/W 0 0 0 0 DMA2 start vector DMA3V5 DMA3V4 DMA3V3 DMA3V2 R/W 0 0 0 0 DMA3 start vector DMA4V5 DMA4V4 DMA4V3 DMA4V2 R/W 0 0 0 0 DMA4 start vector DMA5V5 DMA5V4 DMA5V3 DMA5V2 R/W 0 0 0 0 DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 R/W 0 0 0 0 DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 R/W 0 0 0 0 DMA7 start vector DBST5 DBST4 DBST3 DBST2 R/W 0 0 0 0 1: DMA request on burst mode DREQ5 DREQ4 DREQ3 DREQ2 R/W 0 0 0 0 1: DMA request in software 92CH21-506 2007-02-28 TMP92CH21 (3) Memory controller (1/3) Symbol Name Address 7 6 B0WW2 BLOCK0 CS/WAIT control register low 5 B0WW1 W 1 4 B0WW0 3 2 B0WR2 1 B0WR1 W 1 0 B0WR0 B0CSL 0140H (Prohibit RMW) B0E BLOCK0 CS/WAIT control register high 0141H (Prohibit RMW) 0 0 Write waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1+ N) waits 111: 4 waits Others: Reserved − − B0REC W 0 Always write “0”. 0 Dummy cycle 0:No insert 1: Insert B1WW0 B0OM1 0 0 Read waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1+ N) waits 111: 4 waits Others: Reserved B0OM0 B0BUS1 B0BUS0 0/1 0/1 Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved B1WR1 B1WR0 W 1 0 B0CSH 0 0 CS select Always 0: Disable write “0”. 1: Enable 0 0 00: ROM/SRAM 01: Reserved 10: Reserved 11: Reserved B1WR2 B1WW2 BLOCK1 CS/WAIT control register low B1CSL 0144H (Prohibit RMW) B1E BLOCK1 CS/WAIT control register high 0145H (Prohibit RMW) 0 0 Write waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1+ N) waits 111: 4 waits Others: Reserved − − B1REC W 0 Always write “0”. 0 Dummy cycle 0:No insert 1: Insert B2WW0 B1WW1 W 1 B1OM1 0 Read waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1+ N) waits 111: 4 waits Others: Reserved B1OM0 B1BUS1 B1BUS0 0/1 0/1 Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved B2WR1 B2WR0 W 1 0 B1CSH 0 0 CS select Always 0: Disable write “0”. 1: Enable 0 0 00: ROM/SRAM 01: Reserved 10: Reserved 11: SDRAM B2WR2 B2WW2 BLOCK2 CS/WAIT control register low B2CSL 0148H (Prohibit RMW) B2E BLOCK2 CS/WAIT control register high 0149H (Prohibit RMW) 0 0 Write waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1+ N) waits 111: 4 waits Others: Reserved B2M − B2REC W 0 Always write “0”. 0 Dummy cycle 0:No insert 1: Insert B2WW1 W 1 B2OM1 0 Read waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1+ N) waits 111: 4 waits Others: Reserved B2OM0 B2BUS1 B2BUS0 0/1 0/1 Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved B2CSH 1 0 CS select 0: 16 MB 0: Disable 1: Sets 1: Enable area 0 0 00: ROM/SRAM 01: Reserved 10: Reserved 11: SDRAM 92CH21-507 2007-02-28 TMP92CH21 (3) Memory controller (2/3) Symbol Name Address 7 6 B3WW2 BLOCK3 CS/WAIT control register low 5 B3WW1 W 1 4 B3WW0 3 2 B3WR2 1 B3WR1 W 1 0 B3WR0 B3CSL 014CH (Prohibit RMW) B3E BLOCK3 CS/WAIT control register high 014DH (Prohibit RMW) 0 0 Write waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1 + N) waits 111: 4 waits Others: Reserved − − B3REC W 0 Dummy cycle 0:No insert 1: Insert BEXWW2 BEXWW1 BEXWW0 W 0 1 0 Write waits 001: 2 waits 010: 1 wait 101: 2 waits 110: 2 waits 011: (1 + N) waits Others: Reserved 0 Always write “0”. B3OM1 0 0 Read waits 001: 0 waits 010: 1 wait 101: 2 waits 110: 3 waits 011: (1 + N) waits 111: 4 waits Others: Reserved B3OM0 B3BUS1 B3BUS0 B3CSH 0 0 CS select Always 0: Disable write “0”. 1: Enable BEXCSL BLOCK EX CS/WAIT control register low 0158H (Prohibit RMW) BEXCSH BLOCK EX CS/WAIT control register high 0159H (Prohibit RMW) PMEMCR Page ROM control register 0166H 0/1 0/1 Data bus width 00: 8 bits 01: 16 bits 10: 32 bits 11: Reserved BEXWR2 BEXWR1 BEXWR0 W 0 1 0 Read waits 001: 2 waits 010: 1 wait 101: 2 waits 110: 2 waits 011: (1 + N) waits Others: Reserved BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 W 0 0 0/1 0/1 00: ROM/SRAM 00: 8 bits 01: Reserved 01: 16 bits 10: Reserved 10: 32 bits 11: Reserved 11: Reserved OPGE OPWR1 OPWR0 PR1 PR0 R/W 0 0 0 1 0 ROM Wait number on page Byte number in page page 00: 1 CLK (n-1-1-1 mode) 00: 64 bytes 01: 2 CLK (n-2-2-2 mode) 01: 32 bytes access 0: Disable 10: 3 CLK (n-3-3-3 mode) 10: 16 bytes 1: Enable 11: Reserved 11: 8 bytes 0 0 00: ROM/SRAM 01: Reserved 10: Reserved 11: Reserved 92CH21-508 2007-02-28 TMP92CH21 (3) Memory controller (3/3) Symbol MAMR0 Name Memory address mask register 0 Memory start address register 0 Memory address mask register 1 Memory start address register 1 Memory address mask register 2 Memory start address register 2 Memory address mask register 3 Memory start address register 3 Address 0142H 7 M0V20 1 M0S23 6 M0V19 1 M0S22 1 M1V20 1 M1S22 1 M2V21 1 M2S22 1 M3V21 1 M3S22 1 5 M0V18 4 M0V17 R/W 3 M0V16 2 M0V15 1 M0V14-9 1 M0S17 1 MV15-9 1 M1S17 1 M2V16 1 M2S17 1 M3V16 1 M3S17 1 0 M0V8 1 M0S16 1 M1V8 1 M1S16 1 M2V15 1 M2S16 1 M3V15 1 M3S16 1 1 1 0: Compare enable M0S21 M0S20 MSAR0 0143H 1 M1V21 MAMR1 0146H 1 M1S23 MSAR1 0147H 1 M2V22 MAMR2 014AH 1 M2S23 MSAR2 014BH 1 M3V22 MAMR3 014EH 1 M3S23 MSAR3 014FH 1 1 1 1: Compare disable M0S19 M0S18 R/W 1 1 1 1 Set start address A23 to A16 M1V19 M1V18 M1V17 M1V16 R/W 1 1 1 1 0: Compare enable 1: Compare disable M1S21 M1S20 M1S19 M1S18 R/W 1 1 1 1 Set start address A23 to A16 M2V20 M2V19 M2V18 M2V17 R/W 1 1 1 1 0: Compare enable 1: Compare disable M2S21 M2S20 M2S19 M2S18 R/W 1 1 1 1 Set start address A23 to A16 M3V20 M3V19 M3V18 M3V17 R/W 1 1 1 1 0:Compare enable 1:Compare disable M3S21 M3S20 M3S19 M3S18 R/W 1 1 1 1 Set start address A23 to A16 BROMCR Boot ROM control register 0167H ROMLESS VACE R/W 0/1 1/0 Boot Vector ROM address 0: Use 0: Disable 1: No use 1: Enable 92CH21-509 2007-02-28 TMP92CH21 (4) MMU Symbol Name LOCALX register for program Address 7 LXE R/W 6 5 4 X4 0 3 X3 0 2 X2 R/W 0 1 X1 0 0 X0 0 LOCALPX 01D0H LOCALPY LOCALY register for program 0 LOCALX 1: Enable LYE R/W 0 LOCALY 1: Enable LZE R/W 0 LOCALZ 1: Enable LXE R/W 0 LOCALX 1: Enable LYE R/W 0 LOCALY 1: Enable LZE R/W 0 LOCALZ 1: Enable LXE R/W 0 LOCALX 1: Enable LYE R/W 0 LOCALY 1: Enable LZE R/W 0 LOCALZ 1: Enable LXE R/W 0 LOCALX 1: Enable LYE R/W 0 LOCALY 1: Enable LZE R/W 0 LOCALZ 1: Enable BANK number for LOCALX Setting Y4 0 Y3 0 Y2 R/W 0 Y1 0 Y0 0 01D1H BANK number for LOCALY Setting Z6 0 Z5 0 Z4 0 Z3 R/W 0 Z2 0 Z1 0 Z0 0 LOCALPZ LOCALZ register for program 01D3H BANK number for LOCALZ Setting X4 0 X3 0 X2 R/W 0 X1 0 X0 0 LOCALLX LOCALX register for LCDC 01D4H BANK number for LOCALX Setting Y4 0 Y3 0 Y2 R/W 0 Y1 0 Y0 0 LOCALLY LOCALY register for LCDC 01D5H BANK number for LOCALY Setting Z6 0 Z5 0 Z4 0 Z3 R/W 0 Z2 0 Z1 0 Z0 0 LOCALLZ LOCALZ register for LCDC 01D7H BANK number for LOCALZ Setting X4 0 X3 0 X2 R/W 0 X1 0 X0 0 LOCALRX LOCALX register for read 01D8H BANK number for LOCALX Setting Y4 0 Y3 0 Y2 R/W 0 Y1 0 Y0 0 LOCALRY LOCALY register for read 01D9H BANK number for LOCALY Setting Z6 0 Z5 0 Z4 0 Z3 R/W 0 Z2 0 Z1 0 Z0 0 LOCALRZ LOCALZ register for read 01DBH BANK number for LOCALZ Setting X4 0 X3 0 X2 R/W 0 X1 0 X0 0 LOCALWX LOCALX register for write 01DCH BANK number for LOCALX Setting Y4 0 Y3 0 Y2 R/W 0 Y1 0 Y0 0 LOCALY LOCALWY register for write 01DDH BANK number for LOCALY Setting Z6 0 Z5 0 Z4 0 Z3 R/W 0 Z2 0 Z1 0 Z0 0 LOCALWZ LOCALZ register for write 01DFH BANK number for LOCALZ Setting 92CH21-510 2007-02-28 TMP92CH21 (5) Clock gear, PLL Symbol Name System clock control register 0 Address 7 XEN R/W 1 H-OSC (fc) 0: Stop 1: Oscillation 6 XTEN 1 L-OSC (fs) 0: Stop 1: Oscillation 5 4 3 2 WUEF R/W 0 Warm-up timer 1 0 SYSCR0 10E0H SYSCR1 System clock control register 1 10E1H SYSCK R/W 0 Select system clock 0: fc 1: fs − R/W 0 Always write “0” SYSCR2 System clock control register 2 10E2H PROTECT EMCCR0 EMC control register 0 10E3H R 0 Protect flag 0: OFF 1: ON WUPTM1 WUPTM0 HALTM1 R/W 1 0 1 1 HALT mode Warm-up timer 00: Reserved 00: Reserved 01: 28/Inputted frequency 01: STOP mode 10: 214/Inputted frequency 10: IDLE1 mode 11: 216/Inputted frequency 11: IDLE2 mode EXTIN R/W 0 GEAR1 GEAR0 R/W 1 0 0 Select gear value of high frequency (fc) 000: fc 101: (Reserved) 001: fc/2 110: (Reserved) 010: fc/4 111: (Reserved) 011: fc/8 100: fc/16 HALTM0 GEAR2 DRVOSCH DRVOSCL 1: External clock R/W 1 High frequency oscillator driver ability R/W 1 Low frequency oscillator driver ability 1: NORMAL 1: NORMAL 0: WEAK 0: WEAK EMCCR1 EMCCR2 EMC control register 1 EMC control register 2 10E4H Switching the protect ON/OFF by write to following 1st KEY, 2nd KEY 1st KEY: EMCCR1=5AH, EMCCR2=A5H in succession write 2nd KEY: EMCCR1=A5H, EMCCR2=5AH in succession write FCSEL R/W 0 Select fc clock 0: fOSCH 1: fPLL PLLON R/W 0 Control on/off 0: OFF 1: ON LUPFG R 0 Lock up timer status flag 10E5H PLLCR0 PLL control register 0 10E8H PLLCR1 PLL control register 1 10E9H 92CH21-511 2007-02-28 TMP92CH21 (6) LCD controller (1/6) Symbol Name Address 7 6 5 SCPW1 4 SCPW0 3 MODE3 2 MODE2 1 MODE1 0 MODE0 RAMTYPE1 RAMTYPE0 R/W 0 LCDMODE0 0 1 0 0 0 0 0 LCD mode 0 register Display RAM 0280H 00: Internal SRAM 01: External SRAM 10: SDRAM 11: Reserved LD bus transmission speed 00: Reserved 01: 2 × fSYS 10: 4 × fSYS 11: 8 × fSYS LLPMODE LDINV Mode setting 0000: Built-in RAM type 0001: SR 1bpp (mono) 0010: SR 2bpp (4gray) 0011: SR 3bpp (8gray) 0100: SR 4bpp (16gray) AUTOINV INTMODE 0101: STN 8bpp (256) 0110: STN 12bpp (4096) 0111: Reserved 1000: TFT 8bpp (256) 1001: TFT 12bpp (4096) Others: Reserved LDO1 LDO0 R/W 0 LCDMODE1 0 LD bus inversion 0: Normal 1: Inversion 0 Auto LD bus inversion 0: Disable 1: Enable (Valid in TFT mode) 0 Select interrupt 0: LP 1: BCD 0 0 LCD mode 1 register 0281H LLP mode 0: mode1 1: mode2 LD bus width control 00: 4bit width A_type 01: 4bit width B_type 10: 8bit width A_type 11: 8bit width B_type Others: Reserved LCDFFP LCD frame frequency register FP7 0282H 0 FMN7 0283H 0 COM3 FP6 0 FMN6 0 COM2 FP5 0 FMN5 0 COM1 FP4 R/W FP3 FP2 0 FMN2 0 SEG2 FP1 0 FMN1 0 SEG1 FP0 0 FMN0 0 SEG0 LCDDVM LCD divide FRM register 0 0 Setting bit7 to bit0 fFP FMN4 FMN3 R/W 0 0 Setting DVM bit7 to bit0 COM0 SEG3 R/W 0 LCDSIZE LCD size register 0284H 0 0 0 Common setting 0000: Reserved 0101: 200 0001: 64 0110: 240 0010: 120 0111: 320 0011: 128 1000: 480 0100: 160 Others: Reserved ALL0 0 FRMON 0 FR divide setting 0: Disable 1: Enable 0 0 0 0 Segment setting 0000: Reserved 0101: 320 0001: 64 0110: 480 0010: 128 0111: 640 0011: 160 1000: 768 0100: 256 1001: 960 Others: Reserved FP9 R/W 0 fFP setting bit 9 − 0 Always write “0” MMULCD 0 FP8 0 START 0 LCDC start 0: STOP 1: START LCDCTL0 LCD control 0 register 0285H Column Data setting 0: Normal 1: All display data “0” fFP setting Built-in RAM LCDD bit 8 setting 0: Sequential access 1: Random access LCDCTL1 LCD control 1 register LCP0P R/W 1 0286H LCP0 phase 0: Rising 1: Falling LCP1P R/W 0 LCP1 phase 0: Rising 1: Falling LBCDP R/W 0 LBCD phase 0: Low 1: High LBCDW1 R/W 0 LBCDW0 R/W 0 LBCD width control 00: LCP1_1CLK 01: LCP1_2CLK 10: LCP1_3CLK 11: Reserved 92CH21-512 2007-02-28 TMP92CH21 (6) LCD controller (2/6) Symbol LCDSCC Name LCD source clock counter register Address 0287H 7 SCC7 0 6 SCC6 0 5 SCC5 0 4 SCC4 R/W 0 3 SCC3 0 2 SCC2 0 1 SCC1 0 0 SCC0 0 LCDC source clock counter bit7 to bit0 PCPV1 PCPV0 R/W 0 0 0 Pre LCP1 CLK: LCP1 pulse number Dummy clock number until valid clock of gate driver LCP1 TLDE4 TLDE3 TLDE2 R/W 0 TLDE1 0 TLDE0 0 PCPV2 LCDCCR0 LCD clock counter register 0 0288H LCDCCR1 LCD clock counter register 1 0289H 0 0 Set up time of LCP: SYSCLK pulse number × 8 Set up time of TFT source driver LLP signal (Offset time is 14 to 16 SYSCLK) LLPSU7 028AH 0 LLPSU6 0 LLPSU4 LLPSU3 LLPSU2 R/W 0 0 0 0 TFT source driver, LLP_Enable signal: fSYS × 8 High width time for LLP signal 1R3 1R2 R/W 0291H 0 0 1 256 color STN mode RED1 level setting 3R2 3R1 R/W 1 1 256 color STN mode RED3 level setting 5R2 5R1 R/W 0 1 256 color STN mode RED5 level setting 7R2 7R1 R/W 1 1 256 color STN mode RED7 level setting 0 0 1R1 1R0 0R3 0R2 R/W 0 0 256 color STN mode RED0 level setting 2R2 2R1 R/W 1 0 256 color STN mode RED2 level setting 4R2 4R1 R/W 0 0 256 color STN mode RED4 level setting 6R2 6R1 R/W 1 0 256 color STN mode RED6 level setting 0 0R1 0R0 LLPSU5 LLPSU1 0 LLPSU0 0 LCDCCR2 LCD clock counter register 2 LCDRP10 LCD red palette register 10 3R3 LCDRP32 LCD red palette register 32 0292H 0 3R0 0 2R3 0 2R0 0 5R3 LCDRP54 LCD red palette register 54 0293H 1 5R0 0 4R3 1 4R0 0 7R3 LCDRP76 LCD red palette register 76 0294H 1 7R0 0 6R3 1 6R0 0 92CH21-513 2007-02-28 TMP92CH21 (6) LCD controller (3/6) Symbol LCDGP10 Name LCD green palette register 10 LCD green palette register 32 LCD green palette register 54 LCD green palette register 76 Address 0295H 7 1G3 0 6 1G2 5 1G1 4 1G0 0 3 0G3 0 2 0G2 1 0G1 0 0G0 0 3G3 0296H 0 LCDGP32 5G3 0297H 1 LCDGP54 7G3 0298H 1 LCDGP76 1B3 LCDBP10 LCD blue palette register 10 0299H 0 3B3 LCDBP32 LCD blue palette register 32 029AH 1 R/W 0 1 256 color STN mode GREEN1 level setting 3G2 3G1 R/W 1 1 256 color STN mode GREEN3 level setting 5G2 5G1 R/W 0 1 256 color STN mode GREEN5 level setting 7G2 7G1 R/W 1 1 256 color STN mode GREEN7 level setting 1B2 1B1 R/W 1 0 256 color STN mode BLUE1 level setting 3B2 3B1 R/W 1 0 256 color STN mode BLUE3 level setting 3G0 0 2R3 0 5G0 0 4G3 1 7G0 0 6G3 1 1B0 0 0B3 0 3B0 0 2B3 1 R/W 0 0 256 color STN mode GREEN0 level setting 2G2 2G1 R/W 1 0 256 color STN mode GREEN2 level setting 4G2 4G1 R/W 0 0 256 color STN mode GREEN4 level setting 6G2 6G1 R/W 1 0 256 color STN mode GREEN6 level setting 0B2 0B1 R/W 0 0 256 color STN mode BLUE0 level setting 2B2 2B1 R/W 0 0 256 color STN mode BLUE2 level setting 2G0 0 4G0 0 6G0 0 0B0 0 2B0 0 92CH21-514 2007-02-28 TMP92CH21 (6) LCD controller (4/6) Symbol LSARAL Name Start address register A area (L) Start address register A area (M) Start address register A area (H) Common number register A area (L) Common number register A area (H) Start address register B area (L) Start address register B area (M) Start address register B area (H) Common number register B area (L) Common number register B area (H) Start address register C area (L) Start address register C area (M) Start address register C area (H) Address 02A0H 7 SA7 0 SA15 6 SA6 0 SA14 0 SA22 1 CA6 0 5 SA5 4 SA4 3 SA3 2 SA2 1 SA1 0 SA9 0 SA17 0 CA1 0 0 SA0 0 SA8 0 SA16 0 CA0 0 CA8 R/W 0 A area (bit8) LSARAM 02A1H 0 SA23 LSARAH 02A2H 0 CA7 CMNAL 02A3H 0 R/W 0 0 0 0 Start address for A area (bit7 to bit0) SA13 SA12 SA11 SA10 R/W 0 0 0 0 Start address for A area (bit15 to bit8) SA21 SA20 SA19 SA18 R/W 0 0 0 0 Start address for A area (bit23 to bit16) CA5 CA4 CA3 CA2 R/W 0 0 0 0 Common number setting for A area (bit7 to bit0) CMNAH 02A4H SB7 02A6H 0 SB15 02A7H 0 SB23 02A8H 0 CB7 02A9H 0 SB6 0 SB14 0 SB22 1 CB6 0 SB5 SB4 R/W SB3 SB2 SB1 0 SB9 0 SB17 0 CB1 0 SB0 0 SB8 0 SB16 0 CB0 0 CB8 R/W 0 B area (bit8) LSARBL LSARBM LSARBH CMNBL 0 0 0 0 Start address for B area (bit7 to bit0) SB13 SB12 SB11 SB10 R/W 0 0 0 0 Start address for B area (bit15 to bit8) SB21 SB20 SB19 SB18 R/W 0 0 0 0 Start address for B area (bit23 to bit16) CB5 CB4 CB3 CB2 R/W 0 0 0 0 Common number setting for B area (bit7 to bit0) CMNBH 02AAH SC7 02ACH 0 SC15 02ADH 0 SC23 02AEH 0 SC6 0 SC14 0 SC22 1 SC5 SC4 R/W SC3 SC2 SC1 0 SC9 0 SC17 0 SC0 0 SC8 0 SC16 0 LSARCL LSARCM LSARCH 0 0 0 0 Start address for C area (bit7 to bit0) SC13 SC12 SC11 SC10 R/W 0 0 0 0 Start address for C area (bit15 to bit8) SC21 SC20 SC19 SC18 R/W 0 0 0 0 Start address for C area (bit23 to bit16) 92CH21-515 2007-02-28 TMP92CH21 (6) LCD controller (5/6) Symbol Name Address 02B0H 7 OE007 0 OE017 6 OE006 0 OE016 0 OE026 0 OE036 0 OE046 0 OE056 0 OE106 0 OE116 0 OE126 0 OE136 0 OE146 0 OE156 0 5 OE005 4 OE004 3 OE003 2 OE002 1 OE001 0 OE011 0 OE021 0 OE031 0 OE041 0 OE051 0 OE101 0 OE111 0 OE121 0 OE131 0 OE141 0 OE151 0 0 OE000 0 OE010 0 OE020 0 OE030 0 OE040 0 OE050 0 OE100 0 OE110 0 OE120 0 OE130 0 OE140 0 OE150 0 LCD LCDOE00 OE0 control register 0 LCD LCDOE01 OE0 control register 1 LCD LCDOE02 OE0 control register 2 LCD LCDOE03 OE0 control register 3 LCD LCDOE04 OE0 control register 4 LCD LCDOE05 OE0 control register 5 LCD LCDOE10 OE1 control register 0 LCD LCDOE11 OE1 control register 1 LCD LCDOE12 OE1 control register 2 LCD LCDOE13 OE1 control register 3 LCD LCDOE14 OE1 control register 4 LCD LCDOE15 OE1 control register 5 02B1H 0 OE027 02B2H 0 OE037 02B3H 0 OE047 02B4H 0 OE057 02B5H 0 OE107 02C0H 0 OE117 02C1H 0 OE127 02C2H 0 OE137 02C3H 0 OE147 02C4H 0 OE157 02C5H 0 R/W 0 0 0 0 OE0 control gate driver of TFT panel OE015 OE014 OE013 OE012 R/W 0 0 0 0 OE0 control gate driver of TFT panel OE025 OE024 OE023 OE022 R/W 0 0 0 0 OE0 control gate driver of TFT panel OE035 OE034 OE033 OE032 R/W 0 0 0 0 OE0 control gate driver of TFT panel OE045 OE044 OE043 OE042 R/W 0 0 0 0 OE0 control gate driver of TFT panel OE055 OE054 OE053 OE052 R/W 0 0 0 0 OE0 control gate driver of TFT panel OE105 OE104 OE103 OE102 R/W 0 0 0 0 OE1 control gate driver of TFT panel OE115 OE114 OE113 OE112 R/W 0 0 0 0 OE1 control gate driver of TFT panel OE125 OE124 OE123 OE122 R/W 0 0 0 0 OE1 control gate driver of TFT panel OE135 OE134 OE133 OE132 R/W 0 0 0 0 OE1 control gate driver of TFT panel OE145 OE144 OE143 OE142 R/W 0 0 0 0 OE1 control gate driver of TFT panel OE155 OE154 OE153 OE152 R/W 0 0 0 0 OE1 control gate driver of TFT panel 92CH21-516 2007-02-28 TMP92CH21 (6) LCD controller (6/6) Symbol Name Address 02D0H 7 OE207 0 OE217 6 OE206 0 OE216 0 OE226 0 OE236 0 OE246 0 OE256 0 5 OE205 4 OE204 3 OE203 2 OE202 1 OE201 0 OE211 0 OE221 0 OE231 0 OE241 0 OE251 0 0 OE200 0 OE210 0 OE220 0 OE230 0 OE240 0 OE250 0 LCD LCDOE20 OE2 control register 0 LCD LCDOE21 OE2 control register 1 LCD LCDOE22 OE2 control register 2 LCD LCDOE23 OE2 control register 3 LCD LCDOE24 OE2 control register 4 LCD LCDOE25 OE2 control register 5 02D1H 0 OE227 02D2H 0 OE237 02D3H 0 OE247 02D4H 0 OE257 02D5H 0 R/W 0 0 0 0 OE2 control gate driver of TFT panel OE215 OE214 OE213 OE212 R/W 0 0 0 0 OE2 control gate driver of TFT panel OE225 OE224 OE223 OE222 R/W 0 0 0 0 OE2 control gate driver of TFT panel OE235 OE234 OE233 OE232 R/W 0 0 0 0 OE2 control gate driver of TFT panel OE245 OE244 OE243 OE242 R/W 0 0 0 0 OE2 control gate driver of TFT panel OE255 OE254 OE253 OE252 R/W 0 0 0 0 OE2 control gate driver of TFT panel 92CH21-517 2007-02-28 TMP92CH21 (7) Touch screen I/F Symbol Name Address 7 TSI7 R/W 0 0: Disable 1: Enable 6 5 PTST R 0 Detection condition 4 TWIEN R/W 0 INT4 interrupt control 3 PYEN R/W 0 SPY 0 : OFF 2 PXEN R/W 0 SPX 0 : OFF 1 MYEN R/W 0 SMY 0 : OFF 0 MXEN R/W 0 SMX 0 : OFF 1 : ON TSICR0 Touch screen I/F control register 0 01F0H TSICR1 Touch screen I/F control register 1 01F1H DBC7 R/W 0 0: Disable 1: Enable DB1024 R/W 0 1024 0: no 1 : ON 1 : ON 1 : ON 0: Disable touch 1: Enable 1: touch DB256 DB64 DB8 DB4 DB2 R/W R/W R/W R/W R/W 0 0 0 0 0 256 64 8 4 2 De-bounce time is set by “(N × 64 − 16)/fSYS” − formula. “N” is sum of number which is set to “1” in bit6 to bit0. DB1 R/W 0 1 (8) SDRAM controller Symbol Name Address 7 − 0 Always write “0” 0250H 6 − 0 Always write “0” 5 SMRD 0 Mode register set delay time 0:1 clock 1:2 clocks 4 SWRC 3 SBST 2 SBL1 1 SBL0 0 SMAC SDACR1 SDRAM access control register 1 R/W 0 0 Write Burst stop recovery command time 0: recharge 0:1 clock all 1:2 clocks 1:Burst SBS SDRAM access control register 2 0 Number of banks SDACR2 0251H 1 0 0 Select read burst SDRAM length controller 00: Reserved 0: Disable 01: Full page read, 1: Enable Burst write stop 10: 1 word read, Single write 11: Full page read Single write SDRS1 SDRS0 SMUXW1 SMUXW0 R/W 0 0 0 0 Selecting ROW Selecting address address size Multiplex type SRS2 SDRAM refresh control register SRS1 R/W SRS0 SRC 0 Auto refresh 0: Disable 1: Enable SCMM0 0 SDRCR 0252H SDCMM SDRAM command register 0253H 0 0 0 Refresh interval 000: 47 states 100: 156 states 001: 78 states 101: 295 states 010: 97 states 110: 249 states 011: 124 states 111: 312 states SCMM2 SCMM1 R/W 0 0 Issuing command 92CH21-518 2007-02-28 TMP92CH21 (9) 8-bit timer Symbol Name Address 7 TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 5 4 3 I2TA01 0 IDLE2 0: Stop 1: Operate 2 1 0 TA0RUN 0 UP counter (UC0) TA01RUN TMRA01 RUN register TA01PRUN TA1RUN R/W 0 0 TMRA01 prescaler UP counter (UC1) 1100H 0: Stop and clear 1: Run (Count up) TA0REG 8-bit timer register 0 8-bit timer register 1 1102H (Prohibit RMW) 1103H (Prohibit RMW) TA01M1 TA01M0 PWM01 TA1REG TA01MOD TMRA01 mode register 1104H 0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 − W Undefined − W Undefined PWM00 TA1CLK1 TA1CLK0 R/W 0 0 0 Source clock for TMRA1 TA0CLK1 TA0CLK0 0 0 Source clock for TMRA0 TA1FFCR TMRA1 flip-flop control register 1105H (Prohibit RMW) 00: TA0TRG 01: φT1 10: φT16 11: φT256 TA1FFC1 TA1FFC0 W 1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care I2TA23 0 IDLE2 0: Stop 1: Operate TA23RUN TMRA23 RUN register 1108H TA1RDE R/W 0 Double buffer 0: Disable 1: Enable 00: Reserved 01: φT1 10: φT4 11: φT16 TA1FFIE TA1FFIS R/W 0 0 TA1FF TA1FF control for Inversion inversion select 0: Disable 0: TMRA0 1: Enable 1: TMRA1 TA23PRUN TA3RUN TA2RUN R/W 0 0 0 TMRA23 prescaler UP counter (UC3) UP counter (UC4) 0: Stop and clear 1: Run (Count up) TA2REG 8-bit timer register 2 8-bit timer register 3 110AH (Prohibit RMW) 110BH (Prohibit RMW) TA23M1 TA23M0 PWM21 TA3REG TA23MOD TMRA23 mode register 110CH 0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 PWM cycle 00: Reserved 6 01: 2 7 10: 2 8 11: 2 − W Undefined − W Undefined PWM20 TA3CLK1 TA3CLK0 R/W 0 0 0 Source clock for TMRA3 TA2CLK1 TA2CLK0 0 0 Source clock for TMRA2 TA3FFCR TMRA3 flip-flop control register 110DH (Prohibit RMW) 00: TA2TRG 01: φT1 10: φT16 11: φT256 TA3FFC1 TA3FFC0 W 1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care 00: Reserved 01: φT1 10: φT4 11: φT16 TA3FFIE TA3FFIS R/W 0 0 TA3FF TA1FF control for inversion inversion select 0: Disable 0: TMRA2 1: Enable 1: TMRA3 92CH21-519 2007-02-28 TMP92CH21 (10) 16-bit timer Symbol Name Address 7 6 5 4 3 I2TB0 R/W 0 IDLE2 0: Stop 1: Operate 2 TB0PRUN R/W 0 TMRB0 prescaler 1 0 TB0RUN R/W 0 UP counter (UC10) TB0RUN TMRB0 RUN register 1180H TB0RDE − R/W R/W 0 0 Double Always buffer write “0” 0: Disable 1: Enable − R/W − 0: Stop and clear 1: Run (Count up) TB0CLE TB0CLK1 TB0CLK0 R/W 0 0 0 TMRB0 source clock Control up counter 00: Reserved 0: Disable 01: φT1 clearing 10: φT4 1: Enable 11: φT16 clearing TB0MOD TMRB0 mode register 1182H (Prohibit RMW) 0 0 Always write “0”. − − TB0FFCR TMRB0 flip-flop control register W* 1 1 Always write “11”. 1183H (Prohibit RMW) TB0E0T1 TB0FF0C1 TB0FF0C0 W* 0 1 1 Control TB0FF0 00: Invert 01: Set Invert when Invert when Invert when Invert when 10: Clear the UC value the UC value the UC value the UC value 11: Don’t care is loaded in is loaded in matches the matches the * Always read as “11” to to value in value in TB0CP1H/L. TB0CP0H/L. TB0RG1H/L TB0RG0H/L TB0CP0I TB0CPM1 TB0CPM0 W* 1 0 0 Capture timing Execute 00: Disable software 01: Reserved capture 0: capture 10: Reserved 1: Undefined 11: TA1OUT↑ TA1OUT↓ TB0CT1 TB0C0T1 TB0E1T1 R/W 0 0 0 TB0FF0 inversion trigger 0: Disable trigger 1: Enable trigger TB0RG0L 16-bit timer register 0 low 16-bit timer register 0 high 16-bit timer register 1 low 16-bit timer register 1 high Capture register 0 low Capture register 0 high Capture register 1 low Capture register 1 high 1188H (Prohibit RMW) 1189H (Prohibit RMW) 118AH (Prohibit RMW) 118BH (Prohibit RMW) 118CH TB0RG0H TB0RG1L TB0RG1H TB0CP0L TB0CP0H 118DH TB0CP1L 118EH TB0CP1H 118FH − W Undefined − W Undefined − W Undefined − W Undefined − R Undefined − R Undefined − R Undefined − R Undefined 92CH21-520 2007-02-28 TMP92CH21 (11) UART/serial channel (1/2) Symbol SC0BUF Name Serial channel 0 buffer register Address 1200H (Prohibit RMW) 7 RB7 TB7 6 RB6 TB6 5 4 3 2 1 RB1 TB1 0 RB0 TB0 SC0CR Serial channel 0 control register 1201H RB5 RB4 RB3 RB2 TB5 TB4 TB3 TB2 R (Receiving)/W (Transmission) Undefined RB8 EVEN PE OERR PERR FERR R R/W R (Clear 0 after reading) Undefined 0 0 0 0 0 Receive Parity 1: Error Parity data bit8 0: Odd 0: Disable Overrun Parity Framing 1: Even 1: Enable SCLKS R/W 0 IOC 0 0: SCLK0↑ 0: Baud 1: SCLK0↓ rate generator 1: SCLK0 pin input TB8 Serial channel 0 mode 0 register 0 Transmission data bit8 CTSE 0 0: CTS disable 1: CTS enable RXE WU R/W SM1 SM0 SC1 SC0 SC0MOD0 1202H 0 0 0: Receive Wake-up disable 0: Disable 1: Receive 1: Enable enable 0 0 00: I/O Interface mode 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode − Serial channel 0 baud rate control register 0 Always write “0” BR0ADDE 0 (16-K)/16 divided 0: Disable 1: Enable BR0CK1 0 00: φT0 01: φT2 10: φT8 11: φT32 BR0CK0 0 BR0S3 R/W 0 BR0S2 0 0 0 00: TA0TRG 01: Baud rate generator 10: Internal clock fIO 11: External clock (SCLK0 input) BR0S1 BR0S0 0 0 BR0CR 1203H Divided frequency setting BR0K3 BR0K2 R/W BR0K1 BR0K0 0 BR0ADD Serial channel 0 K setting register 1204H 0 0 0 Sets frequency divisor “K” (divided by N + (16 − K)/16). SC0MOD1 Serial channel 0 mode 1 register 1205H I2S0 R/W 0 IDLE2 0: Stop 1: Operate FDPX0 R/W 0 Duplex 0: Half duplex 1: Full duplex PLSEL 0 Select transmit pulse width 0: 3/16 1: 1/16 SIRCR IrDA control register 1207H SIRWD3 SIRWD2 SIRWD1 SIRWD0 R/W 0 0 0 0 0 0 0 Transmit Receive Receive Select receive pulse width 0: Disable 0: Disable Set effective pulse width for equal or more data 0: “H” pulse 1: Enable 1: Enable than 2x × (value + 1) + 100ns 1: “L” pulse RXSEL TXEN RXEN Can be set: 1 to 14 Can not be set: 0,15 92CH21-521 2007-02-28 TMP92CH21 (11) UART/Serial channel (2/2) Symbol SC1BUF Name Serial channel 1 buffer register Address 1208H (Prohibit RMW) 7 RB7 TB7 6 RB6 TB6 5 4 3 2 1 RB1 TB1 0 RB0 TB0 SC1CR Serial channel 1 control register 1209H RB5 RB4 RB3 RB2 TB5 TB4 TB3 TB2 R (Receiving) /W (Transmission) Undefined RB8 EVEN PE OERR PERR FERR R R/W R (Clear 0 after reading) Undefined 0 0 0 0 0 1: Error Receive Parity Parity data bit8 0: Odd 0: Disable Overrun Parity Framing 1: Even 1: Enable SCLKS R/W 0 0: SCLK1↑ 1: SCLK1↓ IOC 0 0: Baud rate generator 1: SCLK1 pin input TB8 Serial channel 1 mode 0 register 0 Transmission data bit 8 CTSE 0 0: CTS disable 1: CTS enable RXE WU R/W SM1 SM0 SC1 SC0 SC1MOD0 120AH 0 0 0: Receive Wake-up disable 0: Disable 1: Receive 1: Enable enable − Serial channel 1 baud rate control register 0 Always write “0” BR1ADDE 0 (16 - K)/16 divided 0: Disable 1: Enable BR1CK1 0 00: φT0 01: φT2 10: φT8 11: φT32 0 0 0 0 00: I/O interface mode 00: TA0TRG 01: 7-bit UART mode 01: Baud rate 10: 8-bit UART mode generator 11: 9-bit UART mode 10: Internal clock φ1 11: External clock (SCLK1 input) BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 R/W 0 0 0 0 0 Divided frequency setting BR1K3 BR1K2 R/W BR1K1 BR1K0 0 BR1CR 120BH BR1ADD Serial channel 1 K setting register 120CH 0 0 0 Sets frequency divisor “K” (divided by N + (16 − K)/16). SC1MOD1 Serial channel 1 mode 1 register 120DH I2S1 R/W 0 IDLE2 0: Stop 1: Operate FDPX1 R/W 0 Duplex 0: Half duplex 1: Full duplex 92CH21-522 2007-02-28 TMP92CH21 (12) USB controller (1/6) Symbol Descriptor RAM0 Name Descriptor RAM 0 register Descriptor RAM 1 register Descriptor RAM 2 register Descriptor RAM 3 register Address 0500H 7 D7 Undefined 6 D6 Undefined 5 D5 Undefined 4 D4 R/W Undefined 3 D3 Undefined 2 D2 Undefined 1 D1 Undefined 0 D0 Undefined D7 0501H Undefined D6 Undefined D5 Undefined D4 R/W Undefined D3 Undefined D2 Undefined D1 Undefined D0 Undefined Descriptor RAM1 D7 0502H Undefined D6 Undefined D5 Undefined D4 R/W Undefined D3 Undefined D2 Undefined D1 Undefined D0 Undefined Descriptor RAM2 D7 0503H Undefined D6 Undefined D5 Undefined D4 R/W Undefined D3 Undefined D2 Undefined D1 Undefined D0 Undefined Descriptor RAM3 Descriptor Descriptor RAM381 RAM 381 register Descriptor Descriptor RAM382 RAM 382 register Descriptor Descriptor RAM383 RAM 383 register Endpoint0 Endpoint 0 register Endpoint 1 register Endpoint 2 register Endpoint 3 register Endpoint 1 mode register Endpoint 2 mode register Endpoint 3 mode register D7 067DH Undefined D6 Undefined D5 Undefined D4 R/W Undefined D3 Undefined D2 Undefined D1 Undefined D0 Undefined D7 067EH Undefined D6 Undefined D5 Undefined D4 R/W Undefined D3 Undefined D2 Undefined D1 Undefined D0 Undefined D7 067FH Undefined D6 Undefined D5 Undefined D4 R/W Undefined D3 Undefined D2 Undefined D1 Undefined D0 Undefined EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0 0780H Undefined Undefined Undefined R/W Undefined Undefined Undefined Undefined Undefined EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DATA1 EP1_DATA0 Endpoint1 0781H Undefined Undefined Undefined Undefined R/W Undefined Undefined Undefined Undefined EP2_DATA7 EP2_DATA6 EP2_DATA5 EP2_DATA4 EP2_DATA3 EP2_DATA2 EP2_DATA1 EP2_DATA0 Endpoint2 0782H Undefined Undefined Undefined R/W Undefined Undefined Undefined Undefined Undefined EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0 Endpoint3 0783H Undefined Undefined Undefined R/W Undefined Undefined Undefined Undefined Undefined EP1_MODE 0789H EP2_MODE 078AH Payload[2] Payload[1] Payload[0] Mode[1] R/W 0 0 0 0 Payload[2] Payload[1] Payload[0] Mode[1] R/W 0 0 0 0 Payload[2] Payload[1] Payload[0] Mode[1] R/W 0 0 0 0 Mode[0] 0 Mode[0] 0 Mode[0] 0 Direction 0 Direction 0 Direction 0 EP3_MODE 078BH 92CH21-523 2007-02-28 TMP92CH21 (12) USB controller (2/6) Symbol EP0_STATUS Name Endpoint 0 status register Endpoint 1 status register Endpoint 2 status register Endpoint 3 status register Endpoint 0 size register Low A Endpoint 0 size register Low A Endpoint 2 size register Low A Endpoint 3 size register Low A Endpoint 1 size register Low B Endpoint 2 size register Low B Endpoint 3 size register Low B Endpoint 1 size register High A Endpoint 2 size register High A Endpoint 3 size register High A Address 0790H 7 6 TOGGLE 5 SUSPEND 4 STATUS[2] 3 STATUS[1] 2 STATUS[0] 1 0 FIFO_DISABLE STAGE_ERR R 0 TOGGLE 0 SUSPEND 1 STATUS[2] 1 STATUS[1] 1 STATUS[0] 0 0 FIFO_DISABLE STAGE_ERR EP1_STATUS 0791H 0 TOGGLE R 0 SUSPEND 1 STATUS[2] 1 STATUS[1] 1 STATUS[0] 0 0 FIFO_DISABLE STAGE_ERR EP2_STATUS 0792H 0 TOGGLE R 0 SUSPEND 1 STATUS[2] 1 STATUS[1] 1 STATUS[0] 0 0 FIFO_DISABLE STAGE_ERR EP3_STATUS 0793H 0 PKT_ACTIVE DATASIZE6 R 0 DATASIZE5 1 DATASIZE4 1 DATASIZE3 1 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP0_SIZE_L_A 0798H 1 PKT_ACTIVE R 0 DATASIZE6 0 DATASIZE5 0 DATASIZE4 1 DATASIZE3 0 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP1_SIZE_L_A 0799H 1 PKT_ACTIVE R 0 DATASIZE6 0 DATASIZE5 0 DATASIZE4 1 DATASIZE3 0 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP2_SIZE_L_A 079AH 1 PKT_ACTIVE R 0 DATASIZE6 0 DATASIZE5 0 DATASIZE4 1 DATASIZE3 0 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP3_SIZE_L_A 079BH 1 PKT_ACTIVE R 0 DATASIZE6 0 DATASIZE5 0 DATASIZE4 1 DATASIZE3 0 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP1_SIZE_L_B 07A1H 0 PKT_ACTIVE R 0 DATASIZE6 0 DATASIZE5 0 DATASIZE4 1 DATASIZE3 0 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP2_SIZE_L_B 07A2H 0 PKT_ACTIVE R 0 DATASIZE6 0 DATASIZE5 0 DATASIZE4 1 DATASIZE3 0 DATASIZE2 0 DATASIZE1 0 DATASIZE0 EP3_SIZE_L_B 07A3H 0 0 0 0 R 1 0 DATASIZE9 0 DATASIZE8 0 DATASIZE7 EP1_SIZE_H_A 07A9H 0 DATASIZE9 R 0 DATASIZE8 0 DATASIZE7 EP2_SIZE_H_A 07AAH 0 DATASIZE9 R 0 DATASIZE8 0 DATASIZE7 EP3_SIZE_H_A 07ABH 0 R 0 0 92CH21-524 2007-02-28 TMP92CH21 (12) USB controller (3/6) Symbol Name Address 07B1H 0 DATASIZE9 7 6 5 4 3 2 DATASIZE9 1 DATASIZE8 0 DATASIZE7 Endpoint 1 size EP1_SIZE_H_B register High B Endpoint 2 size EP2_SIZE_H_B register High B Endpoint 0 size EP3_SIZE_H_B register High B bmRequestType bmRequestType register R 0 DATASIZE8 0 DATASIZE7 07B2H 0 DATASIZE9 R 0 DATASIZE8 0 DATASIZE7 07B3H 0 DIRECTION REQ_TYPE1 REQ_TYPE0 RECIPIENT4 RECIPIENT3 RECIPIENT2 R 0 RECIPIENT1 0 RECIPIENT0 07C0H 0 REQUEST7 R 0 REQUEST6 0 REQUEST5 0 REQUEST4 0 REQUEST3 0 REQUEST2 0 REQUEST1 0 REQUEST0 bRequest bRequest register wValue register Low wValue register High wIndex register Low wIndex register High wLength register Low wLength register High 07C1H 0 VALUE_L7 R 0 VALUE_L6 0 VALUE_L5 0 VALUE_L4 0 VALUE_L3 0 VALUE_L2 0 VALUE_L1 0 VALUE_L0 wValue_L 07C2H 0 VALUE_H7 R 0 VALUE_H6 0 VALUE_H5 0 VALUE_H4 0 VALUE_H3 0 VALUE_H2 0 VALUE_H1 0 VALUE_H0 wValue_H 07C3H 0 INDEX_L7 R 0 INDEX_L6 0 INDEX_L5 0 INDEX_L4 0 INDEX_L3 0 INDEX_L2 0 INDEX_L1 0 INDEX_L0 wIndex_L 07C4H 0 INDEX_H7 R 0 INDEX_H6 0 INDEX_H5 0 INDEX_H4 0 INDEX_H3 0 INDEX_H2 0 INDEX_H1 0 INDEX_H0 wIndex_H 07C5H 0 LENGTH_L7 R 0 LENGTH_L6 0 LENGTH_L5 0 LENGTH_L4 0 LENGTH_L3 0 LENGTH_L2 0 LENGTH_L1 0 LENGTH_L0 wLength_L 07C6H 0 LENGTH_H7 R 0 LENGTH_H6 0 LENGTH_H5 0 LENGTH_H4 0 LENGTH_H3 0 LENGTH_H2 0 LENGTH_H1 0 LENGTH_H0 wLength_H 07C7H 0 0 0 0 R 0 0 0 0 92CH21-525 2007-02-28 TMP92CH21 (12) USB controller (4/6) Symbol SetupReceived Name Address SetupRece ived register Current_ Config register 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 07C8H 0 REMOTEWAKEUP W 0 0 0 0 R 0 G_INTERFACE S_CONFIG 0 0 CONFIG[1] 0 CONFIG[0] ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0] Current_Config 07C9H R 0 S_INTERFACE 0 G_CONFIG 0 G_DESCRIPT 0 S_FEATURE 0 C_FEATURE 0 G_STATUS StandardStandard Request Request register Request register 07CAH 0 07CBH 0 EP3_DSET_B EP3_DSET_A R 0 0 0 0 VENDOR 0 CLASS 0 ExSTANDARD 0 STANDARD SOFT_RESET G_PORT_STS G_DEVICE_ID Request R 0 EP2_DSET_B 0 EP2_DSET_A 0 EP1_DSET_B 0 EP1_DSET_A 0 0 EP0_DSET_A DATASET1 DATASET 1 register 07CCH 0 EP7_DSET_B R 0 EP7_DSET_A R 0 EP6_DSET_A 0 EP6_DSET_B 0 EP5_DSET_B 0 EP5_DSET_A EP4_DSET_B 0 EP4_DSET_A DATASET2 DATASET 2 register 07CDH 0 0 0 0 R 0 0 Configured 0 Addressed 0 Default USB_STATE USB state register EOP register 07CEH EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB R/W 0 EP2_EOPB R 0 EP1_EOPB 1 EP0_EOPB EOP 07CFH 1 1 EP[2] W 1 EP[1] 1 EP[0] 1 W 1 1 1 Command[3] Command[2] Command[1] Command[0] COMMAND Command register 07D0H 0 0 0 EP3_SELECT EP2_SELECT EP1_SELECT 0 0 R/W 0 0 EPx_SINGLE1 Endpoint 1 single register Endpoint 1 BCS register Interrupt control register EP3_SINGLE EP2_SINGLE EP1_SINGLE 07D1H 0 EP3_SELECT R/W 0 R/W 0 0 0 0 0 0 EP3_BCS EP2_SELECT EP1_SELECT 0 EP2_BCS 0 EP1_BCS EPx_BCS1 07D3H R/W 0 0 Status_nak INT_Control 07D6H S_Interface G_Interface S_Config G_Config G_Descript S_Feature C_Feature R/W 0 G_Status Standard Standard Request Request Mode mode register Request Mode 07D8H 0 0 Soft_Reset R/W 0 G_Port_Sts 0 G_DeviceId 0 0 0 0 Request mode register 07D9H 0 R/W 0 0 92CH21-526 2007-02-28 TMP92CH21 (12) USB controller (5/6) Symbol Port Status Name Port status register Frame register Low Frame register H Address 07E0H 7 Reserved7 6 Reserved6 5 PaperError 4 Select 3 NotError 2 Reserved2 1 Reserved1 0 Reserved0 W 0 − 0 T[6] 0 T[9] 0 T[5] 0 T[8] 1 T[4] R 0 T[7] 1 T[3] 0 0 T[2] 0 CREATE 0 T[1] 0 R 0 T[0] 0 FRAME_L 07E1H 0 T[10] FRAME_STS1 FRAME_STS0 FRAME_H 07E2H 0 0 A6 R 0 A5 0 0 A4 R 0 0 0 0 A3 0 A2 1 A1 0 0 A0 0 USBREADY ADDRESS Address register USB ready register 07E3H USBREADY 07E6H R/W 0 S_D_STALL SetSet Descriptor Descriptor STALL stall register 07E8H W 0 INT_URST_STR INT_URST_END INT_SUS INT_RESUME INT_CLKSTOP INT_CLKON USB interrupt USBINTFR1 flag register 1 R/W 07F0H 0 0 0 0 1: − EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B 0 0: Clear flag 0 When read 0: Not generate interrupt When write 1: Generate interrupt EP1_FULL_A EP1_Empty_A EP1_FULL_B USB interrupt USBINTFR2 flag register 2 R/W 07F1H 0 0 0 0 0 1: − 0 0 0 When read 0: Not generate interrupt When write 0: Clear flag 1: Generate interrupt EP3_FULL_A EP3_Empty_A R/W USB interrupt USBINTFR3 flag register 3 0 07F2H When read 0 0:Not generate interrupt 1:Generate interrupt When write 0: Clear flag 1: − INT_SETUP INT_EP0 INT_STAS INT_STASN INT_EP1N INT_EP2N INT_EP3N EP2_Empty_B USB interrupt USBINTFR4 flag register 4 R/W 07F3H 0 0 0 0 0 When write 0 0: Clear flag 1: − 0 0 When read 0: Not generate interrupt 1: Generate interrupt 92CH21-527 2007-02-28 TMP92CH21 (12) USB controller (6/6) Symbol Name Address USB interrupt mask register 1 7 6 5 MSK_SUS 4 R/W 3 2 MSK_CLKON 1 0 MSK_URST_STR MSK_URST_END MSK_RESUME MSK_CLKSTOP USBINTMR1 07F4H 1 1 1 1: Be masked 1 1: − EP1_MSK_EB 1 1 When read 0: Be not masked When write 0: Clear flag EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB USB interrupt USBINTMR2 mask register 2 R/W 07F5H 1 1 1 1: Be masked EP3_MSK_FA EP3_MSK_EA 1 1 1: − 1 1 1 When read 0: Be not masked When write 0: Clear flag R/W USB interrupt USBINTMR3 mask register 3 1 07F6H When read When write 1 0: Be not masked 1: Be masked 0: Clear flag 1: − MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N USB interrupt USBINTMR4 mask register 4 R/W 07F7H 1 1 1 1: Be masked 1 1 1: − 1 1 When read 0: Be not masked When write 0: Clear flag TRNS_USE WAKEUP − SPEED USBCLKE USBCR1 USB control register 1 R/W R/W 0 07F8H 0 0 Always write “0” 1 0 92CH21-528 2007-02-28 TMP92CH21 (13) AD converter (1/2) Symbol Name Address 7 EOCF R 0 ADMOD0 AD mode control register 0 12B8H AD conversion end flag 1:END 6 ADBF 0 AD conversion BUSY flag 1: Busy 5 − 0 Always write “0” 4 − 0 Always write “0” 3 ITM0 0 0: Every 1 time 1: Every 4 times 2 REPEAT R/W 0 Repeat mode 0: Single mode 1: Repeat mode − R/W 0 Always write “0” 1 SCAN 0 Scan mode 0: Fixed channel mode 1: Channel scan mode 0 ADS 0 AD conversion start 1: Start always read as “0” ADMOD1 AD mode control register 1 VREFON R/W 0 12B9H Ladder resistance 0: Off 1: On I2AD − R/W 0 0 IDLE2 Always 0: Stop write “0” 1: Operate − 0 Always write “0” − 0 Always write “0” ADCH1 ADCH0 − 0 Always write “0” − 0 Always write “0” − 0 Always write “0” − 0 Always write “0” ADMOD2 AD mode control register 1 12BAH 0 0 Input channel 000: AN0 001: AN1 010: AN2 011: AN3 − ADTRGE R/W 0 0 Always AD write “0” external trigger start control 0: Disable 1: Enable ADREG0L AD result register 0 low AD result register 0 high AD result register 1 low AD result register 1 high AD result register 2 low AD result register 2 high AD result register 3 low AD result register 3 high ADR01 12A0H ADR00 R Undefined ADR09 ADR08 ADR07 ADR06 ADREG0H 12A1H ADR11 12A2H ADR10 R Undefined ADR19 ADR18 ADR05 R Undefined ADR04 ADR03 ADR0RF R 0 ADR02 ADREG1L ADR17 ADR16 ADREG1H 12A3H ADR21 12A4H ADR20 R Undefined ADR29 ADR28 ADR15 R Undefined ADR14 ADR13 ADR1RF R 0 ADR12 ADREG2L ADR27 ADR26 ADREG2H 12A5H ADR31 12A6H ADR30 R Undefined ADR39 ADR38 ADR25 R Undefined ADR24 ADR23 ADR2RF R 0 ADR22 ADREG3L ADR37 ADR36 ADREG3H 12A7H ADR35 R Undefined ADR34 ADR33 ADR3RF R 0 ADR32 92CH21-529 2007-02-28 TMP92CH21 (14) Watchdog timer Symbol Name Address 7 WDTE WDT mode register 1 WDT control 1: Enable 6 5 4 3 − 0 Always write “0” 2 I2WDT 0 IDLE2 1 RESCR R/W 0 1: Internally connects WDT out to the reset pin 0 − 0 Always write “0” WDMOD 1300H WDTP1 WDTP0 R/W 0 0 Select detecting time 15 00: 2 /fIO 17 01: 2 /fIO 19 10: 2 /fIO 21 11: 2 /fIO 0: Stop 1: Operate WDCR WDT control register 1301H (Prohibit RMW) − W − B1H: WDT disable code 4E: WDT clear code 92CH21-530 2007-02-28 TMP92CH21 (15) RTC (Real time clock) Symbol SECR Name Second register Address 1320H 7 6 SE6 5 SE5 4 SE4 3 2 1 SE1 0 SE0 “0” is read MINR Minute register 1321H “0” is read 40 sec. MI6 20 sec. MI5 10 sec. MI4 40 min. 20 min. HO5 10 min. HO4 HOURR Hour register 1322H “0” is read 20 hours (PM/AM) 10 hours SE3 SE2 R/W Undefined 8 sec. 4 sec. MI3 MI2 R/W Undefined 8 min. 4 min. HO3 HO2 R/W Undefined 8 hours 4 hours WE2 2 sec. MI1 1 sec. MI0 2 min. HO1 1 min. HO0 2 hours WE1 R/W Undefined W1 DA1 1 hour WE0 DAYR Day register 1323H “0” is read DA5 W2 DA2 DA4 DA3 W0 DA0 DATER Date register 1324H “0” is read 1325H PAGE0 “0” is read 10 month 20 days 10 days MO4 R/W Undefined 8 days 4 days MO3 MO2 R/W Undefined 8 month 4 month 2 days MO1 1 day MO0 2 month 1 month 0: Indicator for 12 hours 1: Indicator for 24 hours MONTHR Month register PAGE1 “0” is read YE7 1326H Year register PAGE0 PAGE1 80 years YE6 YE5 40 years 20 years YE3 R/W Undefined 10 years 8 years YE4 YE2 YE1 YE0 4 years YEARR “0” is read PAGER Page register 1327H (Prohibit RMW) INTENA R/W 0 INTRTC 0:disable 1:enable DIS1HZ RESTR Reset register 1328H (Prohibit RMW) 1 Hz 0:disable 1:enable ENATMR ENAALM R/W Undefined Undefined Clock Alarm 0:Don’t “0” is read care 0:disable 0:disable “0” is read 1:Adjust 1:enable 1:enable DIS16HZ RSTTMR RSTALM − − − W Undefined 16 Hz 1: Reset 1: Reset clock alarm Always write “0” 0:disable 1:enable ADJUST W 2 years 1 year Leap year setting 00: Leap year 01: One year after 10: Two years after 11: Three years after PAGE R/W Undefined PAGE setting − 92CH21-531 2007-02-28 TMP92CH21 (16) Melody/alarm generator Symbol ALM Name Alarm pattern register Address 1330H 7 AL8 0 FC1 6 AL7 0 FC0 5 AL6 0 ALMINV 0 Alarm frequency invert 1: Invert 4 AL5 R/W 3 AL4 2 AL3 0 − 0 1 AL2 0 − 0 0 AL1 0 MELALM 0 Output frequency 0: Alarm 1: Melody MELALMC Melody/ alarm control register 1331H MELFL Melody frequency L-register 0 0 Free run counter control 00: Hold 01: Restart 10: Clear 11: Clear and start ML7 ML6 0 MELON R/W 0 0 0 Alarm pattern set − − R/W 0 0 Always write “0” ML5 0 ML4 R/W ML3 ML2 ML1 0 ML9 R/W 0 ML0 0 ML8 0 1332H 0 0 0 Melody frequency set (Low 8bit) ML11 ML10 0 0 MELFH Melody frequency H-register 1333H 0 Melody counter control 0: Stop and clear 1: Start − IALM4E 0 Melody frequency set (Upper 4 bits) ALMINT Alarm interrupt enable register IALM3E IALM2E R/W 0 0 IALM1E 0 IALM0E 0 1334H 0 Always write “0” INTALM4 to INTALM0 alarm interrupt enable 92CH21-532 2007-02-28 TMP92CH21 (17) NAND flash controller (1/2) Symbol ND0FDTR Name NAND flash data transfer register Address 1D00H 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 WE 0 NAND flash mode ND0FMCR control register 0: Disable write operation 1: Enable write operation 1CC4H R/W Undefined Data window to read/write NAND flash ECC1 ECC0 CE PCNT1 PCNT0 R/W 0 0 0 0 0 Chip Power Control ECC circuit enable 11 (at =X): Reset 00 (at =1): Disable 0: Disable Always write “11” 01 (at =1): Enable ( NDCE is high) 10 (at =1): Read ECC data calculated 1: Enable by NDFC ( NDCE is 10 (at =0): Read ID low) data ALE 0 Address Latch Enable 0: Low 1: High CLE 0 Command Latch Enable 0: Low 1: High ND0FSR NAND flash status register 1CC8H BUSY R Undefined 0: Ready 1: Busy RDY R/W 0 ND0FISR NAND flash interrupt status register 1CCCH Read: 1: Change NDR/ B Write: 1: Clear to “0” ND0FIMR NAND flash interrupt mask register NAND flash strobe pulse width register 1CD0H INTEN R/W 0 0: Disable 1: Enable SPW3 SPW2 R/W 0 SPW1 0 MRDY R/W 0 Mask for RDY SPW0 0 ND0FSPR 1CD4H 0 Pulse width for NDRE , NDWE = fSYS × (This register’s value + 1) RST R/W 0 Reset controller CHSEL R/W 0 Channel selection 0: Channel 0 1: Channel 1 NAND ND0FRSTR flash reset register 1CD8H NDCR NAND flash control register 01C0H NAND flash ECC ND0ECCRD code register D7 1CB0H D6 D5 D4 R D3 D2 D1 D0 Data window to read ECC code 92CH21-533 2007-02-28 TMP92CH21 (17) NAND flash controller (2/2) Symbol ND1FDTR Name NAND flash data transfer register Address 1D00H 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 ND1FMCR NAND flash mode control register 1CE4H R/W Undefined Data window to read/write NAND flash WE ECC1 ECC0 CE PCNT1 PCNT0 R/W 0 0 0 0 0 0 Chip Power Control 0: Disable ECC circuit enable write 11 (at =X): Reset operation 00 (at =1): Disable 0: Disable Always write “11” 1: Enable 01 (at =1): Enable ( NDCE is write 10 (at =1): Read high) operation ECC data calculated 1: Enable by NDFC ( NDCE is 10 (at =0): Read ID low) data ALE 0 Address Latch Enable 0: Low 1: High CLE 0 Command Latch Enable 0: Low 1: High ND1FSR NAND flash status register 1CE8H BUSY R Undefined 0: Ready 1: Busy RDY R/W 0 ND1FISR NAND flash interrupt status register 1CECH Read: 1: Change NDR/ B Write: 1: Clear to “0” ND1FIMR NAND flash interrupt mask register NAND flash strobe pulse width register 1CF0H INTEN R/W 0 0: Disable 1: Enable SPW3 SPW2 R/W 0 SPW1 0 MRDY R/W 0 Mask for RDY SPW0 0 ND1FSPR 1CF4H 0 Pulse width for NDRE , NDWE = fSYS × (This register’s value +1) RST R/W 0 Reset controller D0 NAND ND1FRSTR flash reset register NAND flash ECC ND1ECCRD code register 1CF8H D7 1CB0H D6 D5 D4 R D3 D2 D1 Data window to read ECC code 92CH21-534 2007-02-28 TMP92CH21 (18) I2S Symbol I2SBUFR Name I S FIFO buffer (R) 2 Address 0800H (Prohibit RMW) 0808H (Prohibit RMW) 7 R15/R7 6 R14/R6 5 R13/R5 4 R12/R4 3 R11/R3 2 R10/R2 1 R9/R1 0 R8/R0 I2SBUFL I S FIFO buffer (L) 2 080EH I2SCTL0 IS control register 0 080FH 2 W Undefined Register for transmitting buffer (FIFO) L15/L7 L14/L6 L13/L5 L12/L4 L11/L3 W Undefined Register for transmitting buffer (FIFO) TXE FMT BUSY DIR BIT R/W R/W R R/W R/W 0 0 0 0 0 Status First bit Bit Transmit Mode 2 0: Stop 0: MSB number 0: Stop 0: I S 1: SIO 1: Under 1: LSB 0: 8 bits 1: Start transmitting 1: 16 bits I2SWLVL EDGE I2SFSEL I2SCKE R/W R/W R/W R/W 0 0 0 0 WS level Clock Select for Clock 0: Low left edge enable stereo 1: High left 0: Falling 0: Stereo (After 1: Rising transmit) (2 channel) 1: Monaural 0: Operation (1 channel) 1: Stop (Right channel) L10/L2 L9/L1 L8/L0 (Left channel) MCK1 MCK0 R/W R/W 0 0 Baud rate 00: fSYS 10: fSYS/4 01: fSYS/2 11: fSYS/8 I2SWCK R/W 0 WS clock 0: fs/4 1: TA1OUT SYSCKE R/W 0 System clock 0: Disable 1: Enable 92CH21-535 2007-02-28 TMP92CH21 6. 6.1 Notes and Restrictions Notation (1) The notation for built-in I/O registers is as follows: Register symbol Example: TA01RUN denotes bit TA0RUN of register TA01RUN. (2) Read-modify-write instructions (RMW) An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. Example 1: Example 2: • SET INC 3, (TA01RUN); Set bit3 of TA01RUN. 1, (100H); Increment the data at 100H. Examples of read-modify-write instructions on the TLCS-900: Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# SUB (mem), R/# INC #3, (mem) Logic operations AND (mem), R/# XOR (mem), R/# Bit manipulation operations STCF #3/A, (mem) SET #3, (mem) TSET #3, (mem) Rotate and shift operations RLC (mem) RL (mem) SLA (mem) SLL (mem) RLD (mem) RRC RR SRA SRL (mem) (mem) (mem) (mem) RES #3, (mem) CHG #3, (mem) OR (mem), R/# ADC (mem), R/# SBC (mem), R/# DEC #3, (mem) RRD (mem) (3) fOSCH, fc, fFPH, fSYS, fIO and one state The clock frequency input on pins X1 and 2 is referred to as fOSCH. The clock selected by PLLCR0 is referred to as fc. The clock selected by SYSCR1 is referred to as fFPH. The clock frequency give by fFPH divided by 2 is referred to as system clock fSYS. The clock frequency given by fSYS divided by 2 is referred to as fIO. One cycle of fSYS is referred to as one state. 92CH21-536 2007-02-28 TMP92CH21 6.2 Notes (1) AM0 and AM1 pins These pins are connected to the VCC (Power supply level) or the VSS (Grand level) pin. Do not alter the level when the pin is active. (2) Reserved address areas The 16 bytes area (FFFFF0H ∼ FFFFFFH) cannot be used since it is reserved for use as internal area. If using an emulator, an optional 64 Kbytes of the 16M bytes area is used for emulator control. Therefore, if using an emulator, this area cannot be used. (3) Standby mode (IDLE1) When the HALT instruction is executed in IDLE1 mode (in which only the oscillator operates), the internal USB controller, RTC (Real-time-clock) and MLD (Melody-alarm-generator) operate. When necessary, stop the circuit before the HALT instruction is executed. (4) Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator. As a result, a time equivalent to the warm-up time elapses between input of the release request and output of the system clock. (5) Watchdog timer The watchdog timer starts operation immediately after a reset is released. Disable the watchdog timer when it is not to be used. (6) AD converter The string resistor between the VREFH and VREFL pins can be cut by program so as to reduce power consumption. When STOP mode is used, disable the resistor using the program before the HALT instruction is executed. (7) CPU (Micro DMA) Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control registers in the CPU (e.g., the transfer source address register (DMASn).). (8) Undefined SFR The value of an undefined bit in an SFR is undefined when read. (9) POP SR instruction Please execute the POP SR instruction during DI condition. 92CH21-537 2007-02-28 TMP92CH21 7. Package Dimensions Package Name: P-LQFP144-1616-0.40C Unit: mm Note: Palladium plating 92CH21-538 2007-02-28