TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93CS32
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93CS32
Low Voltage/Low Power
CMOS 16-Bit Microcontrollers
TMP93CS32F 1. Outline and Device Characteristics
The TMP93CS32 is high-speed, advanced 16-bit microcontroller developed for controlling medium to large-scale equipment. The TMP93CS32 is housed in 64-pin flat package (P-QFP64-1414-0.80A). The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) • • • • • TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions Micro DMA: 4 channels (1.6 µs per 2 bytes at 20 MHz)
(2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 2 Kbytes Internal ROM: 64 Kbytes (4) External memory expansion • • • Can be expanded up to16 Mbytes (for both programs and data). AM8/ AM16 pin (Select the external data bus width) Can mix 8- and 16-bit external data buses. (Dynamic bus sizing)
(5) 8-bit timer: 4 channels (6) 16-bit timer: 2 channels (7) Serial interface: 2 channels (8) 10-bit AD converter: 6 channels (9) High current output: 2 ports
030619EBP1
• The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions.
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(10) Watchdog timer (11) Bus width/wait controller: 3 blocks (12) Interrupt functions: 31 • • • 9 CPU interrupts (SWI instruction, and Illegal instruction) 16 internal interrupts 6 external interrupts 7-level priority can be set. (except NMI , INTWD)
(13) I/O ports 49 pins for TMP93CS32 (14) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (15) Clock-gear function • • • Clock can be changed from fc to fc/16. VCC = 2.7 to 5.5 V P-QFP64-1414-0.80A (16) Wide range of operating voltage
(17) Package
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AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4, AN5 (P54, P55) AVCC AVSS VREFH VREFL
900/L CPU 10-bit 6-ch AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Interrupt controller F
VCC [1] VSS [2] OSC X1 X2
Clock controller CLK AM8/ AM16
EA RESET
TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65)
Serial I/O (Channel 0) Serial I/O (Channel 1)
ALE INT0 (P35)
NMI
WAIT (P70)
P71 Port 7 Watchdog timer 2-Kbyte RAM Port 0 8-bit timer (Timer 0) 8-bit timer (Timer 1) 8-bit timer (Timer 2) 8-bit timer (Timer 3) 64-Kbyte ROM INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (Timer 4) 16-bit timer (Timer 5) Port 2 AD0 to AD7 (P00 to P07)
Port 1
AD8 to AD15/A8 to A15 (P10 to P17)
A0 to A7/A16 to A23 (P20 to P27)
RD (P30) WR (P31) HWR (P32)
Port 3
TO3 (P41)
Wait controller (3-block)
Note: The items in parentheses ( ) are the initial setting after reset.
Figure 1.1 TMP93CS32 Block Diagram
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2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP93CS32, their names and functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93CS32.
47
(TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
2
48
46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P35 (INT0) P32 (HWR) P31(WR) P30 (RD) P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12)
TMP93CS32F QFP64 Top view
P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC
RESET
Figure 2.1.1 Pin Assignment (64-Pin QFP)
(TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS CLK AM8/AM16 X1 X2
(AN5) P55
NMI
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2.2
Pin Names and Functions
The names of input/output pins and their functions are described below Table 2.2.1 to Table 2.2.2 Pin Names and Functions. Table 2.2.1 Pin Names and Functions (1/2) Pin Name Number of Pins
8 8
I/O
I/O 3-state I/O 3-state Output
Functions
Port 0: I/O port that allows selection of I/O on a bit basis Address/Data (lower): Bits 0 to 7 for address/data bus Port 1: I/O port that allows selection of I/O on a bit basis Address/Data (upper): Bits 8 to 15 for address/data bus Address: Bits 8 to 15 for address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Address: Bits 0 to 7 for address bus Address: Bits 16 to 23 for address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Port 35: I/O port Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 41: I/O port PWM output 3: 8-bit PWM timer 3 output Port 42: I/O port Timer input 4: Timer 4 input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 43: I/O port Timer input 5: Timer 4 input Interrupt request pin 5: Interrupt request pin with rising edge Port 44: I/O port Timer output 4: Timer 4 output pin Port 45: I/O port Timer input 6: Timer 5 input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 46: I/O port Timer input 7: Timer 5 input Interrupt request pin 7: Interrupt request pin with rising edge Port 47: I/O port Timer output 6: Timer 5 output pin Port 50 to Port 52, Port 54, Port 55: Input port Analog input: Analog signal input for AD converter Port 53: Input port Analog input: Analog signal input for AD converter AD converter external start trigger input
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
8
I/O Output Output
1 1 1 1
Output Output Output Output I/O Output I/O Input
P31
WR
P32
HWR
P35 INT0 P41 TO3 P42 TI4 INT4 P43 TI5 INT5 P44 TO4 P45 TI6 INT6 P46 TI7 INT7 P47 TO6 P50 to P52, P54, P55 AN0 to AN2, AN4, AN5 P53 AN3
ADTRG
1 1
I/O Output I/O Input Input
1
I/O Input Input
1 1
I/O Output I/O Input Input
1
I/O Input Input
1 5
I/O Output Input Input
1
Input Input Input
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Table 2.2.2 Pin Names and Functions (2/2) Pin Name
P60 TXD0 P61 RXD0 P62 SCLK0
CTS0
Number of Pins
1 1 1
I/O
I/O Output I/O Input I/O I/O Input
Functions
Port 60: I/O port (with pull-up resistor) Serial send data 0 Port 61: I/O port (with pull-up resistor) Serial receive data 0 Port 62: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to Send) Serial Clock I/O 0 Port 63: I/O port (with pull-up resistor) Serial send data 1 Port 64: I/O port (with pull-up resistor) Serial receive data 1 Port 65: I/O port (with pull-up resistor) Serial data send enable 1 (Clear to send) Serial clock I/O 1 Port 70: I/O port (High current output available) WAIT: Pin used to request CPU bus wait (It is active in (1 + N) waits mode. Set by the bus-width/wait control register.) Port 71: I/O port (high current output available) Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. Clock output: Outputs “fSYS ÷ 2” clock. Pulled up during reset. Can be disabled for reducing noise. “1” should be inputted with TMP93CS32. Address mode: Selects external data bus width. “1” should be inputted. The data bus width for external access is set by chip select/wait control register, port 1 control register. Address latch enable Can be disabled for reducing noise. Reset: Initializes TMP93CS32. (with pull-up resistor) Pin for high level reference voltage input to AD converter Pin for low level reference voltage input to AD converter Power supply pin for AD converter GND pin for AD converter (0 V) Oscillator connecting pin Oscillator connecting pin Power supply pin GND pin (All VSS pins are connected to the GND (0 V).)
P63 TXD1 P64 RXD1 P65
CTS1
1 1 1
I/O Output I/O Input I/O Input I/O
SCLK1 P70
WAIT
1
I/O Input
P71
NMI
1 1
I/O Input
CLK
1
Output
EA
1 1
Input Input
AM8/ AM16
ALE
RESET
1 1 1 1 1 1 1 1 1 2
Output Input Input Input Input Input Input Output Input Input
VREFH VREFL AVCC AVSS X1 X2 VCC VSS
Note:
Built-in pull-up resistors can be released from the pins other than the RESET pin by software.
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3.
Operation
This section describes the functions and basic operational blocks of TMP93CS32 devices. See the 7. Points of Concern and Restriction for the using notice and restrictions for each block.
3.1
CPU
The TMP93CS32 device has a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section). This section describes CPU functions unique to the TMP93CS32 that are not described in the previous section.
3.1.1
Reset
When resetting the TMP93CS32 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to Low level at least for 10 system clocks (16 µs at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by Reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 × 1/2). When reset is accepted, the CPU sets as follows: • Program Counter (PC) according to Reset Vector that is stored FFFF00H to FFFF02H. PC ← Data in location FFFF00H PC ← Data in location FFFF01H PC ← Data in location FFFF02H Stack pointer (XSP) for system mode to 100H. IFF2 to 0 bits of status register to 111. (Sets mask register to interrupt level 7.) MAX bit of status register to 1. (Sets to maximum mode) Bits RFP2 to 0 of status register to 000. (Sets register banks to 0.)
• • • •
When reset is released, instruction execution starts from PC (reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins is as follows: • • • • Initializes built-in I/O registers as per specifications. Sets port pins (Including pins also used as built-in I/Os) to general-purpose input/output port mode. Pulls up the CLK pin to “High” level. Sets the ALE pin to high impeadance (High-Z).
Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed. Note 2: The CLK pin is pulled up to “High” level during reset. When the voltage is put down externally, there is possible to cause malfunctions. Figure 3.1.1 shows the reset timing chart of TMP93CS32.
3.1.2
AM8/ AM16 Pin
Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by bus width/wait control registers and the registers of Port 1. (The value “H”of this pin is ignored and the value set by register is active.) For details, see the bus width/wait control registers in section 3.6.3.
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45 × 1 cycles omitted Total of 220 × 1 cycles omitted
X1
CLK Sampling Sampling
RESET
A16 to A23 (P20 to P27 input mode)
ALE Address Read
AD0 to AD15
Address
Figure 3.1.1 TMP93CS32 Reset Timing Chart
Data output Address (P32 input mode) (Input mode) (Input mode) Internal pull up High impedance
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RD
AD0 to AD15
Address
Write
WR
HWR
P20 to P27 P60 to P65
P35, P41 to P47, P50 to P55, P70, P71
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3.2
Memory Map
Figure 3.2.1 is a memory map of the TMP93CS32.
000000H 000080H 000100H Internal RAM (2 Kbytes) 000880H Internal I/O (128 bytes)
256-byte direct area (n)
64-Kbyte area (nn)
External memory
010000H
FF0000H
Internal ROM (64 Kbytes) FFFF00H Vector table (256 bytes) FFFFFFH = Internal area)
16-Mbyte area (r32) (−r32) (r32+) (r32 + r8/16) (r32 + d8/16) (nnn)
(
Figure 3.2.1 Memory Map
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3.3
Standby Function
Standby control circuits consist of (1) System clock controller, (2) Prescaler clock controller and (3) Standby controller. Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram. Figure 3.3.3 shows I/O registers. Table 3.3.1 shows the internal operation and system clock.
Reset RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) IDLE1 mode
(Operates only oscillator)
Instruction Interrupt Instruction Interrupt Instruction Interrupt
Release reset Instruction NORMAL mode (fc/gear value/2) Interrupt STOP mode (Stops all circuits)
Figure 3.3.1 Transition Figure The clock frequency input from X1, X2 pin is called fc. The clock frequency selected by SYSCR1 is called system clock fFPH. The devided clock of fFPH is called system clock fSYS, and the 1 cycle of fSYS is called 1 state operating mode.
Table 3.3.1 Internal Operation and System Clock Operating Mode
RESET NORMAL RUN IDLE2 IDLE1 STOP Stop Oscillation Stop
Oscillator fc
CPU
Reset Operate
Internal I/O
Reset Operate Stop only AD Stop
System Clock fSYS
fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Stop
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• Warm-up … fFPH • Watchdog timer … fSYS
Watchdog timer/ Warm-up timer
TRUN fc/16 Selector ÷4
Run & stop 9-bit prescaler
8-bit timer 0, 1, 2, 3 16-bit timer 4, 5 Serial interface 0, 1
Figure 3.3.2 Block Diagram of Standby Circuits
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fFPH SYSCR0 System clock fSYS Selector WDMOD fc/2 Highfrequency oscillator fc ÷2 ÷4 ÷8 fc/4 fc/8 fc/16 ÷16 SYSCR1 ÷2
Internal I/O ROM, RAM
CPU
÷2
CLK
X2
X1
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7
SYSCR0 (006EH) Bit symbol Read/Write After reset Function 1
Always write “1” (This bit is read as “1”.)
6
− 0
Always write “0” (This bit is read as “0”.)
5
− 1
Always write “1” (This bit is read as “1”.)
4
− R/W 0
Always write “0” (This bit is read as “0”.)
3
− 0
Always write “0” (This bit is read as “0”.)
2
− 0
Always write “0” (This bit is read as “0”.)
1
PRCK1 0
0
PRCK0 0
−
Select prescaler clock 00: fFPH 01: (Reserved) 10: fc/16 11: (Reserved)
7
SYSCR1 (006FH) Bit symbol Read/Write After reset Function
6
5
4
3
− 0
Always write “0” (This bit is read as “0”.)
2
GEAR2 R/W 1
Select gear value 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved)
1
GEAR1 0
0
GEAR0 0
7
CKOCR (006DH) Bit symbol Read/Write After reset Function
6
5
4
3
2
1
ALEEN R/W 0
0
CLKEN 0
ALE pin CLK pin output control output control 0: High-Z output 0: High-Z output
1: ALE output 1: CLK output
7
WDMOD (005CH) Bit symbol Read/Write After reset Function 1
WDT control 0: Disable 1: Enable
6
WDTP1 0
WDT detection time 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS
5
WDTP0 0
4
WARM R/W 0
Warm-up timer 0: 214/clock frequency input 1: 216/clock frequency input
3
HALTM1 0
HALT mode 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode
2
HALTM0 0
1
RESCR 0
0: Don’t care
0
DRVE 0
Pin state control in STOP mode
WDTE
1: Connects WDT 0: I/O off output to 1: Remains RESET pin the state internally. before HALT
Note 1: SYSCR1 are read as “1”. Note 2: Resetting clears , bit to “0”. The CLK pin is internally pulled up during reset. Figure 3.3.3 I/O Registers about Standby
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TMP93CS32 3.3.1 System Clock Controller
The system clock controller generates system clock (fSYS) for CPU core and internal I/O. It contains a oscillation circuit and clock gear circuit. The register SYSCR1 changes clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16), and these functions can reduce the power consumption of the equipment in which the device is installed. The system clock (fSYS) is set to fc/32 (fc/16 × 1/2) because of = “100” by resetting. For example, fSYS is set to 0.625 MHz by resetting the case of 20 MHz oscillator is connected to X1, X2 pins. The fc clock can be easily obtained by connecting a resonator to the X1/X2 pins respectively. Clock input from an external oscillator is also possible.
X1 X2 X1 X2
74HCU04
(a) Crystal/Ceramic resonator
(b) External oscillator
Figure 3.3.4 Examples of Resonator Connection * Accurate adjustment of the oscillation frequency The CLK pin outputs at 1/2 the system clock frequency (fSYS/2) is used to monitor the oscillation clock. With a system requiring adjustment of the oscillation frequency, an adjusting program must be written.
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(1) Clock gear controller The clock gear select register SYSCR1 sets fFPH to any one of fc, fc/2, fc/4, fc/8, fc/16. Switching fFPH with the clock gear reduces the power consumption. Clock setting example: Changing gear value of the high-frequency clock
SYSCR1 EQU LD LD 006FH (SYSCR1), XXXX0000B (SYSCR1), XXXX0100B ; ; Changes fSYS to fc/2. Changes fSYS to fc/32.
X: Don’t care
(High-frequency clock gear changing) To change the frequency of the clock gear, write the value to SYSCR1 register. It is necessary to continue the warm-up time until changing after writing the register value. There is a possibility that the instruction next to the clock-gear-changing instruction is executed by the clock gear before changing. To execute the instruction next to the clock-gear-changing instruction by the clock gear after changing, input the dummy instruction (instruction to execute the write cycle) as follows.
Example: SYSCR1
EQU 006FH LD (SYSCR1), XXXX 0001B ; Changes fSYS to fc/4. LD (Dummy), 00H ; Dummy instruction. Instruction to be executed by the clock gear after changing X: Don’t care
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TMP93CS32 3.3.2 Prescaler Clock Controller
The 9-bit prescaler provides a clock to 8-bit Timer 0, 1, 2, 3, 16-bit Timer 4, 5, and serial interface 0, 1. The clock input to the 9-bit prescaler is selected either fFPH or fc/16 by SYSCR0 register. register is initialized to “00” by resetting. When the IDLE1 mode (Operates only oscillator) is used, set TRUN to “0” to reduce the power consumption of 9-bit prescaler before “HALT” instruction is executed.
3.3.3
Internal Clock Pin Output Function
CLK pin outputs fSYS divided by 2 internal clocks. Outputs are specified by the clock output control register CKOCR. Writing “1” sets clock output, and writing “0” sets high impedance. During reset, CLK pin is internally pulled up regardless of the value of register. See TMP93CS32 reset timing chart in Figure 3.1.1. Note: To set = “0” and set CLK pin to high impedance, pull up externally to prevent through current which follows to the input buffer of CLK pin.
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3.3.4
Standby Controller
(1) HALT mode When the HALT instruction is executed, the operating mode changes RUN, IDLE2, IDLE1, or STOP mode depending on the contents of the HALT mode setting register WDMOD. Figure 3.3.5 shows the alternative states of the watchdog timer mode registers. Watchdog Timer Mode Register 7 6
WDTP1 0
5
WDTP0 0
4
WARM R/W 0 Warm-up timer 0: 214/clock frequency selection 1: 216/clock frequency selection
3
HALTM1 0
2
HALTM0 0
1
RESCR 0
0
DRVE 0
WDMOD (005CH)
Bit symbol Read/Write After reset Function
WDTE 1 Watchdog timer control 0: Disable 1: Enable
Watchdog timer detect time selection 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS
Halt mode selection 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode
STOP Runaway mode pin detection control internal reset 1: Drive control pins in 1: Executes STOP mode internal reset by runaway detection
Pin state control in STOP mode 0 1 00 01 10 11 I/O off Retains the state before halt RUN mode (only CPU stop) STOP mode (all circuits stop) IDLE1 mode (only oscillator operating) IDLE2 mode (partial I/O operating)
HALT mode setting
Warm-up time selection at returning from the stop mode (see Table 3.3.4) 0 1 214/select clock frequency 216/select clock frequency
Figure 3.3.5 Watchdog Timer Mode Register The futures of RUN, IDLE2, IDLE1, and STOP modes are as follows. 1. 2. RUN: Only the CPU halts; power consumption remains unchanged. IDLE2: The built-in oscillator and the specified I/O operates. The power consumption is redced to 1/2 than that during NORMAL operation. IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop. The power consumption is reduced to 1/5 or less than that during NORMAL operation. STOP: All internal circuits including the built-in oscillator stop. This greatly reduces power consumption. The operations in the halt state is described in Table 3.3.2.
3.
4.
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Table 3.3.2 I/O Operation during HALT Mode HALT Mode W DMOD
CPU I/O port 8-Bit timer Block 16-Bit timer Serial channel AD converter W atchdog timer Interrupt controller Operate Stop
RUN 00
IDLE2 11
Stop
IDLE1 10
STOP 01
See Table 3.3.5
Keep the state when the “HALT” instruction was executed.
(2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combinations between the states of interrupt mask register and the HALT modes. The details for releasing the halt status are shown in Table 3.3.3. • Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of the interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU starts executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is executed. In this case, interrupt processing is not processed, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at “1”. Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case) (In this case, an interrupt request is kept on hold internally) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. Release by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessary enough resetting time (3 ms or more) to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the HALT instruction is executed. However the other setting contents are initialized. (Releasing due to interrupts keep the state before the HALT instruction is executed.)
•
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Table 3.3.3 Halt Releasing Source and Halt Releasing Operation Interrupt Receiving Status HALT Mode
NMI INTWDT INT0 INT4 to INT7 Halt releasing source Interrupt INTT0 to INTT3 INTTR4 to INTTR7 INTO4, INTO5 INTRX0, TX0 INTRX1, TX1 INTAD RESET ♦:
Interrupt Enable
(Interrupt level) ≥ (Interrupt mask)
Interrupt Disable
(Interrupt level) < (Interrupt mask)
RUN
♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦
IDLE2
♦ × ♦ ♦ ♦ ♦ ♦ ♦ ♦ × ♦
IDLE1
♦ × ♦ × × × × × × × ♦
STOP
♦*1 × ♦*1 × × × × × × × ♦
RUN
− −
IDLE2
− −
IDLE1
− −
STOP
− −
○
× × × × × × × ♦
○
× × × × × × × ♦
○
× × × × × × × ♦
○*1
× × × × × × × ♦
After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.) After releasing the HALT mode, CPU starts executing an instruction that follows the HALT instruction. It can not be used to release the HALT mode. This combination type does not exist because the priority level (interrupt request level) of non-maskable interrupts is fixed to highest priority level “7”. Releasing the HALT mode is executed after passing the warm-up time. “H” until starting interrupt processing. If level “L” is set, interrupt processing is correctly started.
○:
×: −: *1:
Note: When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt enabled status, hold level
(Example releasing “RUN” mode) INT0 interrupt releases halt state when the RUN mode is on.
Address 8203H 8206H 8209H 820BH 820EH INT0
LD LD EI LD HALT
(IIMC), 00H (INTE0AD), 06H 5 (WDMOD), 00H
; ; ; ; ;
Selects INT0 interrupt rising edge. Sets interrupt level to “6” for INT0. Sets interrupt level to “5” for CPU. Sets HALT mode to “RUN”. Halts CPU. INT0 Interrupt routine RETI
820FH
LD
XX, XX
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(3) Operation 1. RUN mode In the RUN mode, the system clock continues to operate even after a HALT instruction is executed. Only the CPU stops executing the instruction. In the halt state, an interrupt request is sampled with the falling edge of the “CLK” signal. Releasing the RUN mode is executed by the external/internal interrupts. (See Table 3.3.3 Halt Releasing Source and Halt Releasing Operation.) Figure 3.3.6 shows the interrupt timing for releasing the halt state by interrupts in the RUN/IDLE2 mode.
X1 CLK A0 to A23 ALE AD0 to AD15
RD WR NMI
Address Data Address Address Data Address Address + 2
INT0 (Level) INT4 to INT7 (Rising edge) INT4, INT6 (Falling edge) Internal INT RUN/IDLE2 mode
Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes 2. IDLE2 mode In the IDLE2 mode, the system clock is supplied to only specific internal I/O devices, and the CPU stops executing the current instruction. In the IDLE2 mode, the halt state is released by an interrupt with the same timing as in the RUN mode. The IDLE2 mode is released by external/internal interrupt, except INTWDT/INTAD interrupts. (See Table 3.3.3 Halt Releasing Source and Halt Releasing Operation.) In the IDLE2 mode, the watchdog timer should be disabled before entering the halt status to prevent the watchdog timer interrupt occurring just after releasing the HALT mode.
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3. IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, the CLK pin is fixed at the level “H” in the output enable (CKOCR = “1”). In the halt state, and interrupt request is sampled aynchronunsly with the system clock, however the halt release (restart of operation) is performed synchronously with it. IDLE1 mode is released by external interrupts ( NMI , INT0). (See Table 3.3.3 Halt Releasing Source and Halt Releasing Operation.) When the IDLE1 mode is used, setting TRUN to “0” to stop 9, 5-bit prescaler before “HALT” instruction reduces the power consumption. Figure 3.3.7 illustrates the timing for releasing the halt state by interrupts in the IDLE1 mode.
X1 CLK A0 to A23 ALE AD0 to AD15
RD WR NMI
Address Data Address Data Address Address + 2
INT0 (Level) INT0 (Rising edge) IDLE1 mode
Figure 3.3.7 Timing Chart of Halt Released by Interrupts in IDLE1 Mode
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4. STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode depends on setting of a bit in the watchdog timer mode register WDMOD. (See Figure 3.3.5 for setting of WDMOD.) Table 3.3.5 summarizes the state of these pins in the STOP mode. The STOP mode is released by external interrupts ( NMI , INT0). When the STOP mode is released, the system clock output starts after the warm-up time required to attain stable oscillation. The warm-up time can be set using WDMOD. See the example of warm-up time (Table 3.3.4). In a system which supplies stable clock generated by an external oscillator, the warm-up time can be reduced by using the setting of T45CR. Figure 3.3.8 illustrates the timing for releasing the halt state by interrupts during the STOP mode.
Warm-up time X1 CLK A0 to A23 ALE AD0 to AD15
RD WR NMI
Address Data Address Data Address Address + 2
INT0 (Level) INT0 (Rising edge) STOP mode
Figure 3.3.8 Timing Chart of Halt State Release by Interrupts in STOP Mode Table 3.3.4 The Example of Warm-up Time after Releasing the STOP Mode Clock Operation Frequency after the STOP Mode
fc fc/2 fc/4 fc/8 fc/16
Warm-up Time [ms] WDMOD = 0
0.8192 1.6384 3.2768 6.5536 13.1072
W DMOD = 1
3.2768 6.5536 13.1072 26.2144 52.4288
Remark
fc = 20 MHz
How to calculate the warm-up time 14 WDMOD = “0”: 2 /(Clock operation frequency after releasing the HALT in STOP mode) 16 WDMOD = “1”: 2 /(Clock operation frequency after releasing the HALT in STOP mode)
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Table 3.3.5 Pin States in STOP Mode Pin Name
P00 to P07 Input mode Output mode AD0 to AD7 Input mode Output mode/A8 to A15 AD8 to AD15 Input mode Output mode, A0 to A7/A16 to A23 Output Input mode Output mode Input mode Output mode Input mode Output mode Input Input mode Output mode Input mode Output mode Input Output ( = 1) Output ( = 1) Input Input Input Input Output Input: Invalid: PU: PU*: ∆:
I/O
= 0
∆ High-Z High-Z ∆ High-Z High-Z ∆ ∆ High-Z PU* PU* Invalid High-Z Invalid High-Z ∆ PU* PU* Invalid High-Z Input “L” level output High-Z Input “H” level fix “H” level fix Invalid “H” level output
= 1
∆ Output High-Z ∆ Output High-Z ∆ Output Output PU Output Invalid Output Invalid Output ∆ PU Output Invalid Output Input “L” level output “H” level output Input “H” level fix “H” level fix Invalid “H” level output
P10 to P17
P20 to P27 P30 ( RD ), P31 ( WR ) P32 ( HWR ) P35 P41 to P47 P50 to P55 P60 to P65 P70, P71
NMI
ALE CLK
RESET EA
AM8/ AM16 X1 X2
Input gate in operation. Fix input voltage to 0 or 1 so that the input pin stays constant. Input is not accepted. Programmable pull-up pin in input gate in operation. Fix the pin to avoid through current since the input gate operates when a pull-up pin resistance is not set. Programmable pull-up pin in input gate disable state. No through current even if the pin is set to high impedance. When a HALT instruction is executed and the CPU stops at the address of the port register, an input gate operates. Fix the pin to avoid through current, and change the program. In all other cases, input is not accepted.
Output: Output state High-Z: Output is at high impedance.
Note:
Port registers are used for controlling programmable pull up. If a pin is also used for an output function (e.g. TO3) and the output function is specified, whether pull up is selected depends on the output function data. If a pin is also used for an input function, whether pull up is selected depends on the port register setting value only.
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3.4
Interrupts
TLCS-900 interrupts are controlled by the CPU interrupt mask flip-flop (IFF2 to IFF0) and the built-in interrupt controller. Altogether the TMP93CS32 has the following 31 interrupt sources: • • • Internal interrupts … 9 SWI instruction, Illegal instruction execution Interrupts from external pins ( NMI , INT0, INT4 to INT7) … 6 Interrupts from built-in I/Os … 16
A fixed individual interrupt vector number is assigned to each interrupt source; six levels of priority can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7. When an interrupt is generated, the interrupt controller sends the value of the priority of the interrupt source to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the CPU. The CPU compares the value of the priority sent with the value in the CPU interrupt mask register . If the value is greater than that the CPU interrupt mask register, the interrupt is accepted. The value in the CPU interrupt mask register can be changed using the EI instruction (Executing EI n changes the contents of to n). For example, programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater, and non-maskable interrupts which are set in the interrupt controller. The DI instruction ( = 7) operates in the same way as the EI 7 instruction. Since the priority values for maskable interrupts are 0 to 6, the DI instruction is used to disable acceptance of maskable interrupts. The EI instruction becomes effective immediately after execution (With the TLCS-90, the EI instruction becomes effective after execution of the subsequent instruction). In addition to the general-purpose interrupt processing mode described above, there is also a Micro DMA processing mode. Micro DMA is a mode used by the CPU to automatically transfer byte or word data. It enables the CPU to process interrupts such as data saves to built-in I/Os at high speed. Figure 3.4.1 is a flowchart showing overall interrupt processing.
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Interrupt processing
Read interrupt vector V. Clear interrupt request F/F.
Start vector match of vector V and micro DMA No PUSH PC PUSH SR SR ← Accepted interrupt level + 1 INTNEST ← INTNEST + 1
Yes
Data transfer by micro DMA
General-purpose interrupt processing
COUNT ← COUNT − 1
Micro DMA processing
Yes PC ← (FFFF00H + V)
COUNT = 0
No Interrupt processing program
RETI instruction POP SR POP PC INTNEST ← INTNEST − 1
End
Figure 3.4.1 Interrupt Processing Flowchart
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2004-02-10
TMP93CS32 3.4.1 General-Purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows. In the cases of software interrupts or interrupts generated by the CPU because of attempts to execute illegal instructions, the following steps (1) and (3) are not executed. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority (which is fixed as follows: the smaller the vector value, the higher the priority), then clears the interrupt request. (2) The CPU pushes the program counter and the status register to the system stack area (Area indicated by the system mode stack pointer (XSP)). (3) The CPU sets a value in the CPU interrupt mask register that is higher by 1 than the value of the accepted interrupt level. However, if the value is 7, 7 is set without an increment. (4) The CPU increments the INTNEST (Interrupt nesting counter). (5) The CPU jumps to address stored at FFFF00H + interrupt vector, then starts the interrupt processing routine. The following diagram shows all the above processing state number. Bus Width of Stack Area
8 bits 16 bits
Bus Width of Interrupt Vector Area
8 bits 16 bits 8 bits 16 bits
Interrupt Processing State Number
35 31 29 25
To return to the main routine after completion of the interrupt processing, the “RETI” instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers and decrements INTNEST (Interrupt nesting counter). Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register . The CPU mask register is set to a value higher by 1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. The interrupt request with a priority higher than the accepted now interrupt during the CPU is processing above (1) to (5) is accepted before the 1’st instruction in the interrupt processing routine, causing interrupt processing to nest. (This is the same case of over lapped each Non-maskable interrupt (level 7).) (Non-maskable interrupts (level 7) can be accepted, causing interrupt processing to rest.) The CPU does not accept an interrupt request of the same level as that of the interrupt being processed.
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Resetting initializes the CPU mask registers to 7; therefore, maskable interrupts are disabled. The following (1) to (5) show a flowchart of interrupt processing. (1) Maskable
(Main) EI 1 [1] INTT0 (Level 1) [5] [4] IFF ← 1 (INTT0 interrupt routine) IFF ← 2 [2] [3] RETI
(2) Non-maskable interrupt
(Main) DI [1]
NMI
(NMI interrupt routine) IFF ← 7 [2] [3] [4] IFF ← 7 RETI
(Level 7) [5]
During execution of the main program, the CPU accepts an interrupt request. The CPU increments the IFF so that the interrupts of level 1 are not accepted during processing the interrupt routine.
DI instruction is executed in the main program, so that the interrupts of only level 7 are accepted. The CPU does not increment the IFF even if the CPU accepts an interrupt request of level 7.
(3) Interrupt nesting
(Main) EI 3 [1] INTT0 (Level 3) [9] [8] IFF ← 3
(INTT0 interrupt routine) (INTT1 interrupt routine)
(4) Software interrupt
(Main) DI [1] [5] RETI [6] IFF ← 4 SWI3 [3] [5] [4] RETI (SWI3 routine)
IFF ← 4 [2]
[3] INTT1 (Level 4) [7] RETI
IFF ← 5 [4]
[2]
During processing the interrupts of level 3, the IFF is set to 4. When an interrupt with a level higher than level 4 is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest.
The CPU accepts the software interrupt request during DI status(IFF = 7) because of the level 7. The IFF is not changed by the software interrupts.
(5) Interrupt sampling timing
(INTT0 interrupt routine) (Main) EI 3 [1] INTT0 (Level 3) [8] [7] INTT1 (Level 4) [2] XXX [6] [5] [4] [3] Example: (Underline): Instruction [1], [2] …: Execution flow
RETI
RETI
If an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level. The program counter which returns at e is the start address of INTT0 interrupt routine.
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The addresses FFFF00H to FFFFFFH (256 bytes) of the TMP93CS32 are assigned for interrupt vector area. Table 3.4.1 TMP93CS32 Interrupt Table
Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 − to − Type Interrupt Source Reset or SWI0 instruction SWI 1 instruction Illegal instruction or SWI2 SWI 3 instruction SWI 4 instruction SWI 5 instruction SWI 6 instruction SWI 7 instruction NMI: NMI pin input INTWD: Watchdog timer INT0 : INT0 pin input (Reserved) INT4: INT4 pin input INT5: INT5 pin input INT6: INT6 pin input INT7: INT7 pin input INTT0: 8-bit timer 0 INTT1: 8-bit timer 1 INTT2: 8-bit timer 2 INTT3: 8-bit timer 3 INTTR4: 16-bit timer4 (TREG4) INTTR5: 16-bit timer 4 (TREG5) INTTR6: 16-bit timer 5 (TREG6) INTTR7: 16-bit timer 5 (TREG7) INTTO4: 16-bit timer 4 (Overflow) INTTO5: 16-bit timer 5 (Overflow) INTRX0: Serial receive (Channel 0) INTTX0: Serial send (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial send (Channel 1) INTAD: AD conversion completion (Reserved) to (Reserved) Vector Value “V” 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH to 00FCH Address Refer to Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH to FFFFFCH Micro DMA Start Vector − − − − − − − − 08H 09H 0AH − 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH − to −
Nonmaskable
Maskable
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Setting to reset/interrupt vector 1. Reset vector
FFFF00H FFFF01H FFFF02H FFFF03H PC PC PC XX
The vector base addresses are depended on the products. Type No. Vector Base Address PC Setting Sequence after Reset
PC ← Address FFFF00H PC ← Address FFFF01H PC ← Address FFFF02H
Notes
P27 to P20/A23 to A16 pins input ports with pull-up due to reset. The logic data is “FFH”. When Port 2 is used as A23 to A16 pins to access the program ROM, set PC to “FFH” and the reset vector to “FF0000H to FFFFFFH” (for mainly products without ROM).
TMP93CS32 TMP93PW32
FFFF00H
2.
Interrupt vector (Except reset vector)
+0 +1 +2 +3 PC PC PC XX XX: Don’t care
Address refer to vector
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(Setting Example) Sets the RESET vector: FF0000H, NMI vector: FF9ABCH, INTAD vector: 123456H.
ORG DL ORG DL ORG DL ORG LD ORG LD ORG LD FFFF00H FF0000H FFFF20H FF9ABCH FFFF78H 123456H FF0000H A, B FF9ABCH B, C 123456H C, A ; ; ; RESET = FF0000H NMI = FF9ABCH INTAD = 123456H
Note: ORG, DL are assembler directives. ORG: Control location counter DL: Defines long word (32-bit) data
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2004-02-10
TMP93CS32 3.4.2 Micro DMA
In addition to the conventional interrupt processing, the TLCS-900 also has a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processing is micro DMA mode or general-purpose interrupt. If micro DMA mode is requested, the CPU performs micro DMA processing. The TLCS-900 can process at very high speed because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC instruction. (1) Micro DMA operation Micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value. The micro DMA has four channels so that it can be set for up to four types of interrupt source. When a micro DMA interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than 0, micro DMA processing is completed; if the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. 32-bit control registers are used for setting transfer source/destination addresses. However, the TLCS-900 has only 24 address pins for output. A 16-Mbyte space is available for the micro DMA. There are two data transfer modes: one-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source/destination address after transfer can be done in both modes. Therefore data can easily be transferred between I/O and memory and between I/Os. For details of transfer modes, see the description of transfer mode registers. The transfer counter has 16 bits, so up to 65536 transfers (The maximum when the initial value of the transfer counter is 0000H.) can be performed for one interrupt source by micro DMA processing. When the transfer counter is decremented to “0” after data is transferred with micro DMA, general-purpose interrupt processing is performed. After processing the generalpurpose interrupt, starting the interrupts of the same channel restarts the transfer counter from 65536. If necessary, reset the transfer counter. Interrupt sources processed by micro DMA processing are those with the Micro DMA start vectors listed in Table 3.4.1. The following timing chart is a micro DMA cycle of the transfer address INC (increment) mode (Condition: MAX mode, 16-bit bus width for 16 Mbytes, 0 waits).
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1 state DM2 DM3 DM4 DM5 DM6 DM7 DM8 DM9 DM10 DM11 DM12
(Note 1)
(Note 2)
(Note 3)
(Note 3)
(Note 3)
DM1
DM13
DM14
DM15
DM16
X1
ALE A0 to 15 D0 to 15
A0 to 15
AD0 to AD15 D0 to 15 Dummy Dummy Source address Destination address
A0 to 15
D0 to 15 Address
A0 to 15
D0 to 15 Address + 2
A0 to 15
D0 to 15 Address + 4
A16 to A23
Dummy
Figure 3.4.2 Micro DMA Cycle (COUNT ≠ 0)
This may be a dummy cycle with an instruction queue buffer.
93CS32-31
RD
WR, HWR
Note 1:
These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number. These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number.
Note 2:
Note 3:
TMP93CS32
2004-02-10
(Note 1)
(Note 2)
(Note 3)
(Note 3)
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DM9
DM10
DM11
DM12
DM13
DM14
DM15
DM16
X1
ALE A0 to 15 D0 to 15
A0 to 15
AD0 to AD15 D0 to 15 Dummy Address A0 to 15 D0 to 15 A0 to 15 Dummy Source address Destination address
D0 to 15 Dummy
A16 to A23
Dummy
Address + 2
RD
WR, HWR
(Note 4) (Note 4) (Note 4)
DM17
DM18
DM19
DM20
DM21
DM22
DM23
DM24
DM25
DM26
DM27
DM28
DM29
DM30
DM31
DM32
X1
ALE XSP − 6 XSP − 4 XSP − 2 Dummy FFFF00H + V FFFF02H + V Dummy
Figure 3.4.3 Micro DMA Cycle (COUNT = 0)
DM35 DM36 DM37 Address Address + 2
93CS32-32
AD0 to AD15
Dummy
RD
WR, HWR
DM33
DM34
X1
ALE
AD0 to AD15
Dummy
RD
WR, HWR
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2004-02-10
Note 1: These 2 states are added in the case that the bus width of the source address area is 8 bits or the address starts from an odd number. Note 2: These 2 states are added in the case that the bus width of the destination address area is 8 bits or the address starts from an odd number.
Note 3: This will be a dummy cycle with an instruction queue buffer. Note 4: These 2 states are added in the case that the bus width of the stack address area is 8 bits or the stack pointer starts from an odd number.
TMP93CS32
(2) Register configuration (CPU control register) Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 Channel 1 DMAS1 DMAD1 DMAC1 DMAM1 Channel 2 DMAS2 DMAD2 DMAC2 DMAM2 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3
8 bits
Transfer source address register 0 Transfer destination address register 0 Transfer counter register 0 Transfer mode register 0
(Use only lower 24 bits.) (1 to 65536)
Transfer source address register 1 Transfer destination address register 1 Transfer counter register 1 Transfer mode register 1
Transfer source address register 2 Transfer destination address register 2 Transfer counter register 2 Transfer mode register 2
Transfer source address register 3 Transfer destination address register 3 Transfer counter register 3 Transfer mode register 3
16 bits 32 bits
These control register can not be set only “LDC cr, r” instruction.
Example: LD LDC LD LDC LD LDC LD LDC XWA, 100H DMAS0, XWA XWA, 50H DMAD0, XWA WA, 40H DMAC0, WA A, 05H DMAM0, A
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(3) Transfer mode register details
(DMAM0 to DMAM3) 0 0 0 0 Mode Note: When setting values for this register, clear the upper 4 bits to 0. Execution time (Min) at 20 MHz Z: 0 = Byte transfer, 1 = Word transfer 0 0 0 Z Transfer destination address INC mode for I/O to memory (DMADn+) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INT. Transfer destination address DEC mode for I/O to memory (DMADn−) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INT. Transfer source address INC mode...........for memory to I/O (DMADn) ← (DMASn+) DMACn ← DMACn − 1 if DMACn = 0 then INT. Transfer source address DEC mode .........for memory to I/O (DMADn) ← (DMASn−) DMACn ← DMACn − 1 if DMACn = 0 then INT. Fixed address mode...............................................I/O to I/O (DMADn) ← (DMASn) DMACn ← DMACn − 1 if DMACn = 0 then INT. Counter mode ....................................... for interrupt counter DMASn ← DMASn + 1 DMACn ← DMACn − 1 if DMACn = 0 then INT. 16 states (1.6 µs) 16 states (1.6 µs) 16 states (1.6 µs) 16 states (1.6 µs) 16 states (1.6 µs) 11 states (1.1 µs)
0
0
1
Z
0
1
0
Z
0
1
1
Z
1
0
0
Z
1
0
1
1
(1 states = 100 ns at 20 MHz, high frequency mode) Note 1: n: Corresponds to micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increments register value after transfer.) DMADn−/DMASn−: Post-decrement (Decrement register value after transfer.) Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits. Clock condition: fc = 20 MHz, clock gear: 1(fc) Note 3: Do not use the codes other than the above mentioned codes for transfer mode register.
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TMP93CS32 3.4.3 Interrupt Controller
Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each interrupt channel (Total of 22 channels) in the interrupt controller has an interrupt request flip-flop, interrupt priority setting register, and a register for storing the micro DMA start vector. The interrupt request fip-flop is used to latch interrupt requests from peripheral devices. The flip-flop is cleared to 0 at reset, when the CPU reads the interrupt channel vector after the acceptance of interrupt, or when the CPU executes an instruction that clears the interrupt of that channel (Writes 0 in the clear bit of the interrupt priority setting register). For example, to clear the INT0 interrupt request, set the register after the DI instruction as follows.
LD (INTE0AD), - - - - 0 - - - B
The status of the interrupt request flip-flop is detected by reading the clear bit. Detects whether there is an interrupt request for an interrupt channel. The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTE0AD, INTE45, etc.) provided for each interrupt source. Interrupt levels to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of the non-maskable interrupt ( NMI pin, watchdog timer, etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default priority (The smaller the vector value, the higher the priority). The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value set in the Status Register by the interrupt request signal with the priority value sent; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 in the CPU SR. Interrupt requests where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR. The interrupt controller also has four registers used to store the Micro DMA start vector. These are I/O registers; unlike other micro DMA registers (DMAS, DMAD, DMAM, and DMAC). Writing the start vector of the interrupt source for the micro DMA processing (see Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter registers (e.g., DMAS and DMAD) prior to the micro DMA processing.
93CS32-35
2004-02-10
Interrupt controller Interrupt request flip flop S Q 1 Interrupt request signal to CPU IFF2 to 0 1 7
INTRQ2 to 0
CPU
NMI RESET R interrupt vector V read Interrupt enable flag on CPU side RESET EI 1 to 7 DI Interrupt level detect If INTRQ2 to 0 ≥ IFF2 to 0 then 1.
INTWD 3 3
Priority setting register Dn Dn + 1 D Q Dn + 2 CLR 6 3 Interrupt vector read D0 D1 22 D2 D3 Interrupt vector generation D4 D5 D6 Interrupt request F/F S Q Dn + 3 (Highest priority = 7)
RESET
V = 20H V = 24H Decoder Y1 A Y2 Y3 B Y4 C Y5 Y6 6 Priority encoder 1 2 A 3 Highest B 4 priority C interrupt 5 level select 6 7
Interrupt request signal
INT0 R
During IDLE1 During STOP
Figure 3.4.4 Block Diagram of Interrupt Controller
93CS32-36
5
Micro DMA start vector setting register
Halt release RESET INT0 NMI
INT4 INT5 INT6 INT7 INTT0 INTT1 INTT2 INTT3 INTTR4 INTTR5 INTTR6 INTTR7 INTTO4 INTTO5 INTRX0 INTTX0 INTRX1 INTTX1 INTAD 4 5 5 Match detect 4 input OR
Interrupt request flip flop read Interrupt request clear Dn + 3 Interrupt request V read V = 28H V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH V = 50H V = 54H V = 58H V = 5CH V = 60H V = 64H V = 68H V = 6CH V = 70H V = 74H V = 78H
Micro DMA request
D4 D3 D Q D2 D1 CLR D0 RESET
2 DMA0V DMA1V DMA2V DMA3V
0 A 1 2 B 3 Micro DMA channel priorty encoder
2
Micro DMA channel specification
TMP93CS32
2004-02-10
TMP93CS32
(1) Interrupt priority setting register
Symbol Address 7 IADC R/W 0 I5C R/W 0 I7C R/W 0 IT1C R/W 0 IT3C R/W 0 IT5C R/W 0 IT7C R/W 0 ITO5C R/W 0 ITX0C R/W 0 ITX1C R/W 0 6 5 4 IADM0 0 I5M0 0 I7M0 0 IT1M0 0 IT3M0 0 IT5M0 0 IT7M0 0 ITO5M0 0 ITX0M0 0 ITX1M0 0 3 I0C R/W 0 I4C R/W 0 I6C R/W 0 IT0C R/W 0 IT2C R/W 0 IT4C R/W 0 IT6C R/W 0 ITO4C R/W 0 IRX0C R/W 0 IRX1C R/W 0 2 INT0 I0M2 0 INT4 I4M2 0 INT6 I6M1 W 0 0 INTT0 (Timer0) IT0M2 IT0M1 W 0 0 INTT2 (Timer2) IT2M2 IT2M1 W 0 0 INTTR4 (TREG4) IT4M2 IT4M1 W 0 0 INTTR6 (TREG6) IT6M2 IT6M1 W 0 0 INTTO4 ITO4M2 ITO4M1 W 0 0 INTRX0 IRX0M2 IRX0M1 W 0 0 INTRX1 IRX1M2 IRX1M1 W 0 0 I6M2 I6M0 0 IT0M0 0 IT2M0 0 IT4M0 0 IT6M0 0 ITO4M0 0 IRX0M0 0 IRX1M0 0 I4M1 W 0 I4M0 0 I0M1 W 0 I0M0 0 1 0 ←Interrupt source ←Bit symbol ←Read/Write ←After reset INTAD IADM2 IADM1 W 0 0 INT5 I5M2 I5M1 W 0 0 INT7 I7M2 I7M1 W 0 0 INTT1 (Timer1) IT1M2 IT1M1 W 0 0 INTT3 (Timer3) IT3M2 IT3M1 W 0 0 INTTR5 (TREG5) IT5M2 IT5M1 W 0 0 INTTR7 (TREG7) IT7M2 IT7M1 W 0 0 INTTO5 ITO5M2 ITO5M1 W 0 0 INTTX0 ITX0M2 ITX0M1 W 0 0 INTTX1 ITX1M2 ITX1M1 W 0 0
INTE0AD
0070H
INTE45
0071H
INTE67
0072H
INTET10
0073H
INTET32
0074H
INTET54
0075H
INTET76
0076H
INTEO54
0077H
INTES0 INTES1
0078H
0079H
IxxM2 0 0 0 0 1 1 1 1 IxxC 0 1 Note 1: Note 2:
IxxM1 0 0 1 1 0 0 1 1
IxxM0 0 1 0 1 0 1 0 1
Function (Write) Prohibits interrupt request. Sets interrupt request level to “1”. Sets interrupt request level to “2”. Sets interrupt request level to “3”. Sets interrupt request level to “4”. Sets interrupt request level to “5”. Sets interrupt request level to “6”. Prohibits interrupt request. Function (Write) Clears interrupt request flag. - - - - - Don’t care - - - - -
Function (Read) Indicates no interrupt request. Indicates interrupt request. Read-modify-write is prohibited. Note about clearing interrupt request flag
The interrupt request flag of INTRX0, INTRX1 are not cleared by writing “00” to IXXC because of they are level interrupts. They can be cleared only by resetting or reading SCBUFn.
Figure 3.4.5 Interrupt Priority Setting Register
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2004-02-10
TMP93CS32
(2) External interrupt control Interrupt Input Mode Control Register 7
IIMC (007BH) Bit symbol Read/Write After reset Readmodifywrite instruction prohibited Function
6
5
− W 0 (Note) Always write “0”.
4
3
2
I0IE 0 1: INT0 input enable
1
I0LE W 0 0: INT0 edge mode 1: INT0 level mode
0
NMIREE 0 1: Can be accepted in NMI rising edge.
INT0 input enable (Note 1) 0 1 INT0 disable (P35 function only) Input enable
NMI rising edge enable
0 1
Interrupt request generation at falling edge Interrupt request generation at rising/falling edge Rising edge detect interrupt High level interrupt
INT0 level enable (Note 2) 0 1 Note 1:
The INT0 pin can also be used for standby release as described later. Even if the pin is not used for standby release, setting this register to “0” maintains the port function during standby mode. Case of changing from level to edge for INT0 pin mode ( “1” → “0”) Execution example: LD (INTE0AD), XXXX0000B LD (IIMC), XXXXX10XB LD (INTE0AD), XXXX0nnnB ; ; ; INT0 disable, clean the request flag. Change from level to edge. Set interrupt level “n” for INT0, clear the request flag.
Note 2:
Note 3: Note 4:
IIMC is always read as “1”. See electrical characteristics in section 4 for external 4 for external interrupt input pulse.
Figure 3.4.6 Interrupt Input Mode Control Register Table 3.4.2 Setting of External Interrupt Pin Functions Interrupt
NMI
Shared Pin
NMI
Mode
Falling edge
Setting Method
IIMC = 0 IIMC = 1 IIMC = 0, = 1 IIMC = 1, = 1 T4MOD = 0, 0 or 0, 1 or 1, 1 T4MOD = 1, 0 −−− T5MOD = 0, 0 or 0, 1 or 1, 1 T5MOD = 1, 0 −−−
(Dedicated pin)
Falling and rising edges Rising edge Level
INT0
P35
INT4 INT5 INT6 INT7
P42 P43 P45 P46
Rising edge Falling edge Rising edge Rising edge Falling edge Rising edge
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2004-02-10
TMP93CS32
(3) Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the interrupt vector (Bits 2 to 6 of the interrupt vector) with each channel’s Micro DMA start vector. When the two match, the interrupt from the channel whose value matched is processed in Micro DMA mode. If the interrupt vector matches more than one channel, the channel with the lower channel number has a higher priority. Micro DMA0 Start Vector 7
DMA0V (007CH) (Note) Bit symbol Read/Write After reset Function 0 0
6
5
4
DMA0V4
3
DMA0V3
2
DMA0V2 W 0
1
DMA0V1 0
0
DMA0V0 0
Micro DMA channel 0 processed by matching bits 2 to 6 of the interrupt vector.
Micro DMA1 Start Vector 7
DMA1V (007DH) (Note) Bit symbol Read/Write After reset Function 0 0
6
5
4
DMA1V4
3
DMA1V3
2
DMA1V2 W 0
1
DMA1V1 0
0
DMA1V0 0
Micro DMA channel 1 processed by matching bits 2 to 6 of the interrupt vector.
Micro DMA2 Start Vector 7
DMA2V (007EH) (Note) Bit symbol Read/Write After reset Function 0 0
6
5
4
DMA2V4
3
DMA2V3
2
DMA2V2 W 0
1
DMA2V1 0
0
DMA2V0 0
Micro DMA channel 2 processed by matching bits 2 to 6 of the interrupt vector.
Micro DMA3 Start Vector 7
Bit symbol DMA3V (007FH) (Note) Read/Write After reset Function
6
5
4
DMA3V4 0
3
DMA3V3 0
2
DMA3V2 W 0
1
DMA3V1 0
0
DMA3V0 0
Micro DMA channel 3 processed by matching bits 2 to 6 of the interrupt vector.
Note: Read-modify-write instruction is prohibited.
Figure 3.4.7 Micro DMA Start Vector Register
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TMP93CS32
(4) Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear an interrupt request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might execute the fetched instruction to clear the interrupt request flag while reading the interrupt vector after accepting the interrupt. To avoid the above occurring, clear the interrupt request flag by entering the instruction to clear the flag after the DI instruction. In the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing instruction and following more than one instruction are executed. When EI instruction is placed immediately after clearing instruction, an interrupt becomes enable before interrupt request flags are cleared. In the case of changing the value of the interrupt mask register by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction.
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2004-02-10
TMP93CS32
3.5
Functions of Ports
The TMP93CS32 has 49 bits for I/O ports. These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5.1 lists the function of each port pin. Table 3.5.2 lists I/O registers and specification. Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output are set to input ports. To set port pins for built-in functions, a program is required. Table 3.5.1 Functions of Ports
(PU = with programmable pull-up resistor)
Port Name
Port 0 Port 1 Port 2 Port 3
Pin Name
P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 P35 P41 P42 P43 P44 P45 P46 P47 P50 to P52 P53 P54, P55 P60 P61 P62 P63 P64 P65 P70 P71
Pin No.
8 8 8 1 1 1 1 1 1 1 1 1 1 1 3 1 2 1 1 1 1 1 1 1 1
Direction
I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O
R
− − PU − − PU − − − − − − − − − − − PU PU PU PU PU PU − −
Direction Setting Unit
Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit
Pin Name for Built-in Function
AD0 to AD7 AD8 to AD15/A8 to A15 A0 to A7/A16 to A23
RD WR HWR
INT0 TO3 TI4/INT4 TI5/INT5 TO4 TI6/INT6 TI7/INT7 TO6 AN0 to AN2, AN3/ ADTRG AN4, AN5 TXD0 RXD0 SCLK0/ CTS0 TXD1 RXD1 SCLK1/ CTS1
WAIT /(High current output) (High current output)
Port 4
Port 5
Port 6
Port 7
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Table 3.5.2 I/O Registers and Specification (1/2) Port
Port 0
Name
P00 to P07 Input port Output port AD (0 to 7) bus
Specification Pn
X X X X X X X 0 1 X 1 1 X 1 0 X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X
I/O register PnCR
0 1 X 0 1 0 1 0 0 1 0 1 None 0 0 1 1 0 0 0 1 1 0 1 1 None 0 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 None 0 0 1 None 0 0 1 None 0 1 0 0 0 1 None 0 0 1 None
PnFC
Port 1
P10 to P17
Input port Output port AD (8 to 15) bus A (8 to 15) output
Port 2
P20 to P27
Input port (without pull up) Input port (with pull up) Output port A (0 to 7) Output A (16 to 23) output
Port 3
P30
Output port Outputs RD only when accessing external space Always outputs RD
P31 P32
Output port Outputs WR only when accessing external space Input port (without pull up) Input port (with pull up) Output port
HWR output
P35 Port 4 P41
Input port/INT0 input (Note 1) Output port Input port Output port TO3 output
P42 P43 P44
Input port/TI4/INT4 input Output port Input port/TI5/INT5 input Output port Input port Output port TO4 output
P45 P46 P47
Input port/TI6/INT6 input Output port Input port/TI7/INT7 input Output port Input port Output port TO6 output
Port 5
P50 to P57
Input port AN0 to AN5 input (Note 2)
X: Don’t care Note 1: Using P35 pin as INT0, IIMC register has to be set enable interrupt. Note 2: Using P50 to P55 pins as input channels for the AD converter, the channels are selected by ADMOD1.
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Table 3.5.3 I/O Registers and Specification (2/2) Port
Port 6 P60
Name
Specification Pn
Input port (without pull up) Input port (with pull up) Output port TXD0 output 0 1 X X 0 1 X 0 1 X X 0 1 X X 0 1 X 0 1 X X X X X X
I/O Register PnCR
0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 1 0 1 None 0 0 0 1 None 0 0 0 1 0 0 0 1 None
PnFC
0 0 0 0
P61
Input port/RXD0 input (without pull up) Input port/RXD0 input (with pull up) Output port
P62
Input port/SCLK0/ CTS0 input (without pull up) Input port/SCLK0/ CTS0 input (with pull up) Output port SCLK0 output
P63
Input port (without pull up) Input port (with pull up) Output port TXD1 output
P64
Input port/RXD1 (without pull up) Input port/RXD1 (with pull up) Output port
P65
Input port/SCLK1/ CTS1 input (without pull up) Input port/SCLK1/ CTS1 input (with pull up) Output port SCLK1 output
Port 7
P70 P71
Input port/ WAIT input Output port Input port Output port
X: Don’t care
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2004-02-10
TMP93CS32 3.5.1 Port 0 (P00 to P07)
Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting clears all bits of P0CR to 0 and sets Port 0 to input mode. Figure 3.5.1 shows the registers for Port 0. In addition to functioning as a general-purpose I/O port, Port 0 also functions as an address data bus (AD0 to AD7). To access external memory, Port 0 functions as an address data bus (AD0 to AD7) and all bits of the control register P0CR are cleared to 0.
Reset
Direction control (on bit basis)
P0CR write Internal data bus
Output latch Output buffer P0 write S B Selector A P0 read B A
Port 0 P00 to P07 (AD0 to AD7) S
Y
Selector
Figure 3.5.1 Port 0
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2004-02-10
TMP93CS32 3.5.2 Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Resetting sets all bits of output latch P1, control register P1CR, and function register P1FC to 0 and sets Port 1 to input mode. Figure 3.5.3 shows the registers for Port 1. In addition to functioning as a general-purpose I/O port, Port 1 also shares functions as an address data bus (AD8 to AD15) or an address bus (A8 to A15).
Reset
Direction control (on bit basis)
P1CR write Internal data bus
Function control (on bit basis) P1FC write Port 1 P10 to P17 (AD8 to AD15/A8 to A15)
Output latch Output buffer P1 write S B Selector A P1 read
Figure 3.5.2 Port 1
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TMP93CS32
Port 0 Register 7
P0 (0000H) Bit symbol Read/Write After reset P07
6
P06
5
P05
4
P04 R/W
3
P03
2
P02
1
P01
0
P00
Input mode (Output latch register becomes undefined.)
Port 0 Control Register 7
P0CR (0002H) Bit symbol Read/Write After reset Function 0 0 0 0 P07C
6
P06C
5
P05C
4
P04C W
3
P03C 0
2
P02C 0
1
P01C 0
0
P00C 0
0:Input 1:Output (At external access, Port 0 becomes AD7 to AD0 and P0CR is cleared to 0.)
Port 0 I/O setting 0 1 Note: Read-modify-write instruction is prohibited for P0CR. Input Output
Port 1 Register 7
P1 (0001H) Bit symbol Read/Write After reset P17
6
P16
5
P15
4
P14 R/W
3
P13
2
P12
1
P11
0
P10
Input mode (Output latch register is cleared to “0”.)
Port 1 Control Register 7
P1CR (0004H) Bit symbol Read/Write After reset Function 0 0 0 0 P17C
6
P16C
5
P15C
4
P14C W
3
P13C 0
2
P12C 0
1
P11C 0
0
P10C 0
Note: Read-modify-write instruction is prohibited for P1CR.
Port 1 Function Register 7
P1FC (0005H) Bit symbol Read/Write After reset Function 0 0 0 0 P17F
6
P16F
5
P15F
4
P14F W
3
P13F 0
2
P12F 0
1
P11F 0
0
P10F 0
P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8
Port 1 function setting
P1FC P1CR
0 Input port Output port
1
0 1 Note 1: Note 2: Read-modify-write instruction is prohibited for P1FC. is bit X in register P1FC; , in register P1CR.
Address data bus (AD15 to AD8) Address bus (A15 to A8)
Figure 3.5.3 Registers for Ports 0 and 1
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2004-02-10
TMP93CS32 3.5.3 Port 2 (P20 to P27)
Port 2 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register P2CR and function register P2FC. All bits of the output latch P2 is set to “1” by reset, and all bits of P2CR and P2FC are cleared to “0”. Port 2 becomes the input mode with the pull-up resistor. In addition to functioning as a general-purpose I/O port, Port 2 also shares functions as an address bus (A0 to A7) and an address bus (A16 to A23). To use Port 2 as address bus (A0 to A7 or A16 to A23), write “0” to P2 output latch and turn off the programmable pull-up resistor.
A16 to A23 B Selector A S
A0 to A7 Reset
Direction control (on bit basis)
P2CR write Internal data bus
Function control (on bit basis) S P2FC write B Selector Output latch S B Selector A P2 read A Output buffer
P-ch Programmable pull up Port 2 P20 to P27 (A0 to A7/A16 to A23)
P2 write
Figure 3.5.4 Port 2
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TMP93CS32
Port 2 Register 7
P2 (0006H) Bit symbol Read/Write After reset P27
6
P26
5
P25
4
P24 R/W
3
P23
2
P22
1
P21
0
P20
Input mode (Output latch register is set to “1”.)
Note: When port P2 is used in the input mode, P2 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin.
Port 2 Control Register 7
P2CR (0008H) Bit symbol Read/Write After reset Function 0 0 0 0 P27C
6
P26C
5
P25C
4
P24C W
3
P23C 0
2
P22C 0
1
P21C 0
0
P20C 0
Note: Read-modify-write instruction is prohibited for P2CR.
Port 2 Function Register 7
P2FC (0009H) Bit symbol Read/Write After reset Function 0 0 0 0 P27F
6
P26F
5
P25F
4
P24F W
3
P23F 0
2
P22F 0
1
P21F 0
0
P20F 0
P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16
Port 2 function setting
P2FC P2CR
0 Input port Output port
1
0 1 Note 1: Note 2: Read-modify-write instruction is prohibited for P2FC. is bit X in register P2FC; ; in register P2CR. To set as an address bus A23 to A16, set P2FC after setting P2CR.
Address bus (A7 to A0) Address bus (A23 to A16)
Figure 3.5.5 Registers for Port 2
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2004-02-10
TMP93CS32 3.5.4 Port 3 (P30 to P32, P35)
Port 3 is an 4-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting resets all bits of output latch P3, control register P3CR (bits 0 and 1 are unused), and function register P3FC to 0. Resetting also outputs 1 from P30 and P31. In addition to functioning as a general-purpose I/O port, Port 3 also shares functions as an I/O for the CPU’s control/status signal. With the TMP93CS32, when P30 pin is defined as RD signal output mode ( = 1), clearing the output latch register to 0 outputs the RD strobe (used for the pseudo static RAM) from the P30 pin even when the internal address area is accessed. If the output latch register remains 1, the RD strobe signal is output only when the external address area is accessed. (1) P30 ( RD ) and P31 ( WR )
Reset
Function control (on bit basis) Internal data bus
P3FC write S Output latch P3 write A Selector B
RD , WR
S P30 ( RD ) P31 ( WR ) Output buffer
P3 read
Figure 3.5.6 Port 3 (P30 and P31)
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(2) P32 ( HWR )
Reset
Direction control (on bit basis)
P3CR write
Internal data bus
Function control (on bit basis) P3FC write S Output latch P3 write A Selector
HWR
P-ch Programmable pull up S Output buffer P32 ( HWR )
B
P3 read
Figure 3.5.7 Port 3 (P32) (3) P35 (INT0) Port 35 is a general-purpose I/O port, and also used as an INT0 pin for external interrupt request input.
Reset
Direction control (on bit basis)
P3CR write Internal data bus S Output latch P3 write S B Selector A Level/edge detect IIMC IIMC P35 (INT0)
P3 read INT0 interrupt
Figure 3.5.8 Port 35
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TMP93CS32
Port 3 Register 7
P3 (0007H) Bit symbol Read/Write After reset Function 1 Input mode − −
6
5
P35
4
−
3
− R/W
2
P32 1 Input mode
1
P31 1
0
P30 1
(Note) Always write “1” (This bit is read as “1”).
Output mode
Note: When port 32 is used in the input mode, P3 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin.
Port 3 Control Register 7
P3CR (000AH) Bit symbol Read/Write After reset Function 0 0: Input 1: Output −
6
5
P35C
4
− W
3
− −
2
P32C 0 0: Input 1: Output
1
0
(Note) Always write “1” (This bit is read as “1”).
I/O setting 0 1 Note: Read-modify-write instruction is prohibited for P3CR. Input Output
Port 3 Function Register 7
P3FC (000BH) Bit symbol Read/Write After reset Function
6
− W −
(Note) Always write “0” (This bit is read as “1”).
5
4
− −
3
− −
2
P32F W 0 0: Port 1: HWR
1
P31F 0 0: Port 1: WR
0
P30F 0 0: Port 1: RD
(Note) Always write “0” (This bit is read as “1”).
P32 ( HWR ) function setting 0 0 1 “0” output
1
P30 ( RD ) function setting 0 0 1 “0” output
1
“1” output
“1” output
HWR output only for external access
Always RD output RD output only for (for pseudo SRAM) external access
P31 ( WR ) function setting 0 0 1 “0” output
1
“1” output
WR output only for external access
Note: Read-modify-write instruction is prohibited for P3FC.
Figure 3.5.9 Registers for Port 3
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3.5.5 Port 4 (P41 to P47) Port 4 is a 7-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets Port 4 to the input port. In addition to functioning as a general-purpose I/O port, Port 4 also shares functions as 16-bit timer 4 and 5 clocks, an output for 8-bit timer F/F3, 16-bit timer F/F4 and 5. Writing 1 in the corresponding bit of the Port 4 function register (P4FC) enables output of the timer.
Reset
Direction control (on bit basis)
P4CR write S Output latch P42 (TI4/INT4) P43 (TI5/INT5) P45 (TI6/INT6) P46 (TI7/INT7) S B Selector A
P4 write
P4 read TI4, INT4 TI5, INT5 TI6, INT6 TI7, INT7 Internal data bus
Reset
Direction control (on bit basis)
P4CR write
Function control (on bit basis) P4FC write S Output latch S A Selector B B Selector A S
P4 write Timer F/F OUT TO3: Timer 3 TO4: Timer 4 TO6: Timer 5
P41 (TO3) P44 (TO4) P47 (TO6)
P4 read
Figure 3.5.10 Port 4 (P41 to P47)
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Port 4 Register 7
P4 (000CH) Bit symbol Read/Write After reset Function Input mode 1 1 1 1 P47
6
P46
5
P45
4
P44 R/W
3
P43 1
2
P42 1
1
P41 1
0
− −
(Note) Always write “1” (This bit is read as “1”).
Port 4 Control Register 7
P4CR (000EH) Bit symbol Read/Write After reset Function 0: Input 1: Output 0 0 0 0 P47C
6
P46C
5
P45C
4
P44C W
3
P43C 0
2
P42C 0
1
P41C 0
0
− −
(Note) Always write “1” (This bit is read as “1”).
Port 4 I/O setting 0 1 Input Output
Note: Read-modify-write instruction is prohibited for P4CR.
Port 4 Function Register 7
P4FC (0010H) Bit symbol Read/Write After reset Function P47F W 0 0: Port 1: TO6
6
5
4
P44F W 0 0: Port 1: TO4
3
2
1
P41F W 0 0: Port 1: TO3
0
Setting P47 as TO6 P4FC P4CR 1 1
Setting P44 as TO4 P4FC P4CR 1 1
Setting P41 as TO3 P4FC P4CR 1 1
Note 1: Note 2:
Read-modify-write instruction is prohibited for P4FC. P42/TI4, P43/TI5, P45/TI6, P46/TI7 pin does not have a register changing port/function. For example, when it is used as an input port, the input signal for port is inputted to 8-/16-bit timer as a timer input.
Figure 3.5.11 Register for Port 4
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TMP93CS32
3.5.6 Port 5 (P50 to P55) Port 5 is an 6-bit input port, also used as an analog input pin for the internal AD Converter. Additionally, P53 is also used as an analog conversion external trigger input pin ( ADTRG ).
Internal data bus
Port 5 read
Port 5 P50 to P52 (AN0 to AN2) P53 (AN3/ ADTRG ) P54, P55 (AN4, AN5)
Conversion result register AD read
AD converter
Channel selector
ADTRG
Only for P53 function
Figure 3.5.12 Port 5 Port 5 Register 7
P5 (000DH) Bit symbol Read/Write After reset Function Note:
6
5
P55
4
P54
3
P53 R Undefined Input mode
2
P52
1
P51
0
P50
The input channel selection of AD Converter is set by AD Converter mode register ADMOD1.
Figure 3.5.13 Registers for Port 5
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TMP93CS32 3.5.7 Port 6 (P60 to P65)
Port 60 to 65 is a 6-bit general-purpose I/O port. I/Os can be set on a bit basis. Resetting sets P60 to 65 to an input port and connects a pull-up resistor. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, P60 to P65 can also share function as an I/O for serial channels 0 and 1. Writing “1” in the corresponding bit of the Port 6 function register (P6FC) enables this function. Resetting sets the function register value to “0” and sets all bits to input ports. (1) Ports 60 (TXD0) and 63 (TXD1) Ports 60 and 63 also function as serial channel TXD output pins in addition to I/O ports. They have a programmable open-drain function.
Reset
Direction control (on bit basis)
P6CR write Internal data bus
Function control (on bit basis) P6FC write S Output latch P-ch Programmable pull up S A Selector B S B Selector A P60 (TXD0) P63 (TXD1) Open-drain possible ODE
P6 write TXD0, TXD1
P6 read
Figure 3.5.14 Ports 60 and 63
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(2) Ports 61 (RXD0) and 64 (RXD1) Ports 61 and 64 are I/O ports, and also used as RXD input pins for serial channels.
Reset
Direction control (on bit basis) Internal data bus P-ch Programmable pull up P61 (RXD0) P64 (RXD1) S B Selector A
P6CR write S Output latch
P6 write
P6 read RXD0, RXD1
Figure 3.5.15 Ports 61 and 64 (3) Ports 62 ( CTS0 /SCLK0) and 65 ( CTS1 /SCLK1) Ports 62 and 65 are an I/O port, and also used as a CTS input pin and as a SCLK I/O pin for serial channels.
Reset
Direction control (on bit basis)
P6CR write Internal data bus
Function control (on bit basis) P6FC write S Output latch P-ch Programmable pull up S A Selector B S B Selector A P62 (SCLK0/ CTS0 ) P65 (SCLK1/ CTS1 )
P6 write SCLK0 OUT SCLK1 OUT P6 read
CTS0 , CTS1
SCLK0, SCLK1
Figure 3.5.16 Ports 62 and 65
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Port 6 Register 7
P6 (0012H) Bit symbol Read/Write After reset Function − − 1 1 (Note) Always write “1” (This bit is read as “1”). −
6
−
5
P65
4
P64 R/W
3
P63 1 Input mode
2
P62 1
1
P61 1
0
P60 1
Note: When port P6 is used in the input mode, P6 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin.
Port 6 Control Register 7
P6CR (0014H) Bit symbol Read/Write After reset Function − − 0 0 (Note) Always write “1” (This bit is read as “1”). −
6
−
5
P65C
4
P64C W
3
P63C 0 0: Input
2
P62C 0 1: Output
1
P61C 0
0
P60C 0
Port 6 I/O setting 0 1 Input Output
Note: Read-modify-write instruction is prohibited for P6CR.
Port 6 Function Register 7
P6FC (0016H) Bit symbol Read/Write After reset Function
6
5
P65F W 0 0: Port 1: SCLK1
4
3
P63F W 0 0: Port 1: TXD1
2
P62F 0 0: Port 1: SCLK0
1
0
P60F W 0 0: Port 1: TXD0
P63 TXD1 output setting (Note 2) P6FC P6CR 1 1
P60 TXD0 output setting (Note 2) P6FC P6CR P62 SCLK0 output setting P6FC P6CR 1 1 1 1
P65 SCLK1 output setting P6FC P6CR 1 1
Note 1: Note 2:
Read-modify-write instruction is prohibited for P6FC. To set the TXD pin to open drain, write “1” in bit0 (for TXD0 pin) or bit1 (for TXD1 pin) of the ODE register. P61/RXD0, P64/RXD1 pins do not have a register changing port/function. When using as input ports, the serial receive data is input to SIO.
Figure 3.5.17 Register for Port 6
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TMP93CS32 3.5.8 Port 7 (P70 and P71)
Port 7 is an 2-bit general-purpose I/O port. I/O can be set on a bit basis. Port 7 can output large current and drive LED directly. In addition to I/O port, Port 70 also shares functions as WAIT input pin. Resetting sets the function register P7CR to 0, and all bits to input ports.
Reset
Direction control (on bit basis)
P7CR write S Output latch P70 ( WAIT )
P7 write Internal data bus
S B Selector A
P7 read
WAIT
Reset
Direction control (on bit basis)
P7CR write S Output latch P71
P7 write
S B Selector A
P7 read
Figure 3.5.18 Port 71 to 77
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Port 7 Register 7
P7 (0013H) Bit symbol Read/Write After reset Function − − − − −
6
−
5
−
4
− R/W
3
− −
2
− −
1
P71 1 Input mode
0
P70 1
(Note) Always write “1” (This bit is read as “1”).
Port 7 Control Register 7
P7CR (0015H) Bit symbol Read/Write After reset Function − − − − −
6
−
5
−
4
− W
3
− −
2
− −
1
P71C 0
0
P70C 0
(Note) Always write “1” (This bit is read as “1”).
0: Input 1: Output
Port 7 I/O setting 0 1 Note 1: Note 2: Read-modify-write instruction is prohibited for P7CR. P70/ WAIT pin does not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted as WAIT input. When it is used as WAIT input pin, bit of bus width wait control register must be specified. Input Output
Figure 3.5.19 Registers for Port 7
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3.6
Bus Width/Wait Controller, AM8/ AM16 Pin
TMP93CS32 has a built-in controller used to control wait ( WAIT pin) and data bus size (8 or 16 bits) for any of the three block address areas.
3.6.1
AM8/ AM16 Pin
Set this pin to “H”. After reset, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by the bus width/wait cntrol registers (Described at 3.6.3) and the registers of Port 1. (The value “1” of this pin is ignored and the value set by register is active.)
3.6.2
Address/Data Bus Pins
Port 0/AD0 to AD7, Port 1/AD8 to AD15/A8 to A15 and Port 2/A16 to A23/A0 to A7 function as address/data bus for connecting the external memories. 1 2
Max 24 (to 16 Mbytes) 16 16 VIH VIH AD0 to AD7 A8 to A15 A16 to A23
A23 to 8 AD7 to 0
A23 to 8 A7 to 0 D7 to 0
3
Max 16 (to 64 Kbytes) 8 0
4
Max 8 (to 256 bytes) 16 0
Number of address bus pins Number of data bus pins Number of multiplexed pins Mode pins Port function
EA
Max 24 (to 16 Mbytes) 8 8
AM8/ AM16 Port 0 Port 1 Port 2 AD0 to AD7 AD8 to AD15 A16 to A23
A23 to 16 AD15 to 0 ALE
RD
AD0 to AD7 A8 to A15 A0 to A7
A15 to 0
D15 to 0
AD0 to AD7 AD8 to AD15 A0 to A7
A7 to 0 AD15 to 0 ALE
RD
A23 to 16 A15 to 0
A15 to 0
(note1) A7 D7 to 0 to 0
A7 to 0
A15 to 0 (note1) D15 to 0
AD7 to 0 ALE
RD
Timing chart
ALE
RD
Note 1: In case of 3 and 4, the data bus signals output the addresses since the signals are also used as the address bus. Writing “0” to bit CKOCR, ALE signal can be stopped outputting. Note 2: After reset operation, Port 0, Port 1, and Port 2 function as Input ports, not as address, data bus signals.
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TMP93CS32 3.6.3
.
Bus Width/Wait Control Registers
Figure 3.6.1 shows control registers. One block address areas are controlled by 1-byte bus width/wait control registers (WAITC0, WAITC1, WAITC2). (1) Data bus size select Bit4 (, , ) of the control register is used to specify data bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1 accesses the memory in 8-bit data bus mode. Changing data bus size depending on the access address is called dynamic bus sizing. Table 3.6.1 shows the details of the bus operation. (2) Wait control Control register bits 3 and 2 (, , ) are used to specify the number of waits. These bits execute the following operation by setting. “00” A2-state wait is inserted regardless of the WAIT pin status. “01” A1-state wait is inserted regardless of the WAIT pin status. “10” A1-state wait is inserted and the WAIT pin status is sampled. If the pin is low, inserting the wait maintains the bus cycle until the pin goes high. “11” The bus cycle is completed without a wait (0 waits) regardless of the WAIT pin status. After reset operation, clear to “00” (A2-state wait mode). (3) Address area specification Control register bits 1 and 0 (, , ) are used to specify the target address area. Setting these bits to 00 enables settings (Wait state, Bus size, etc.) as follows: * * * WAITC0 setting enabled when 7F00H to 7FFFH is accessed. WAITC1 setting enabled when 880H to 7FFFH is accessed. WAITC2 setting enabled when 8000H to 3FFFFFH is accessed.
Setting bits to 01 enables setting for each block when 400000H to 7FFFFFH is accessed. Setting bits to 10 enables them when 800000H to BFFFFFH is accessed. Setting bits to 11 enables them when C00000H to FFFFFFH is accessed.
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7
WAITC0 (0068H) Bit symbol Read/Write After reset Function
6
5
4
B0BUS 0 0: 16-bit bus 1: 8-bit bus
3
B0W1 0 00: 2 waits 01: 1 wait 10: (1 + n) waits 11: 0 waits B1W1 0 00: 2 waits 01: 1 wait 10: (1 + n) waits 11: 0 waits B2W1 0 00: 2 waits 01: 1 wait 10: (1 + n) waits 11: 0 waits
2
B0W0 W 0
1
B0C1 0
0
B0C0 0
00: 7F00H to 7FFFH 01: From 400000H 10: From 800000H 11: From C00000H B1W0 W 0 B1C1 0 B1C0 0
WAITC1 (0069H)
Bit symbol Read/Write After reset Function
B1BUS 0 0: 16-bit bus 1: 8-bit bus
00: 880H to 7FFFH 01: From 400000H 10: From 800000H 11: From C00000H B2W0 W 0 B2C1 1 B2C0 1
WAITC2 (006AH)
Bit symbol Read/Write After reset Function
B2BUS 0 0: 16-bit bus 1: 8-bit bus
00: From 8000H 01: From 400000H 10: From 800000H 11: From C00000H
Note: Read-modify-write instruction is prohibited for WAITC0, WAITC1, and WAITC2.
Figure 3.6.1 Bus Width/Wait Control Registers Table 3.6.1 Dynamic Bus Sizing Operand Data Size
8 bits
Operand Start Memory Data CPU Address Address Size
2n + 0 (Even number) 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 2n + 1 (Odd number) 8 bits 16 bits 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 2n + 2 2n + 4
CPU Data D15 to D8
xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx
D7 to D0
b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24
16 bits
2n + 0 (Even number)
32 bits
2n + 0 (Even number)
8 bits
16 bits 2n + 1 (Odd number) 8 bits
16 bits
xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the write strobe signal remains non-active.
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TMP93CS32 3.6.4 Bus Width/Wait Control
An image of the actual Bus-width/Wait control is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for WAITC0; 880H to 7FFFH, for WAITC1; and 8000H to 3FFFFFH, for WAITC2. The reason is that a device other than ROM (e.g., RAM or I/O) might be connected externally. 7F00 to 7FFFH (256 bytes) for WAITC0 are mapped mainly for possible expansions to external I/O. 880H to 7FFFH (Approx. 31 K bytes) for WAITC1 are mapped there mainly for possible extensions to external RAM. 8000H to 3FFFFFH (Approx. 4 M bytes) for WAITC2 are mapped mainly for possible extensions to external ROM. With the TMP93CS32 which has a built-in ROM, addresses from FF0000H to FFFFFFH are used as the internal ROM area; WAITC2 is disabled in this area. After reset, the CPU reads the program from the built-in ROM in 16-bit bus, 0-wait mode.
WAITC0 000000H 7F00H 8000H 400000H 800000H C00000H FFFFFFH (Mainly for I/O) (Mainly for RAM) (Mainly for ROM) 880H = “00” = “01” = “10” = “11” WAITC1 = “00” = “00” = “01” = “10” = “11” = “01” = “10” = “11” WAITC2
Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the bus width/wait controller. Note 2: External areas other than WAITC0 to WAITC2 are accessed in 16-bit data bus (0 waits) mode. When using the bus width/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H to 7FFFH for WAITC0 and 880H to 7FFFH for WAITC1 are specified, in other words, specifications overlap, only the WAITC0 setting is active.)
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(Example of external memory connection) Figure 3.6.2 is an example in which an external memory is connected to the TMP93CS32. In this example, 128-Kbyte ROM is connected using 16 bits bus, and 256-Kbyte RAM using 16-bit bus.
Decorder
ROMCS RAMCS
TMP93CS32
Upper address Latch × 16 AD8 to AD15 D AD0 to AD7 LE Q Address bus
OE CS
ROM (64 Kbits × 16) D8 to D15 D0 to D7
ALE
RAM (128 Kbits × 8) D0 to D7
RD HWR
OE R/ W CS
Upper byte RAM (128 Kbits × 8) D0 to D7
WR
AM8/ AM16
EA
OE R/ W CS
Lower byte
Figure 3.6.2 Example of External Memory Connection (ROM and RAM = 16 Bits) The TMP93CS32 has built-in ROM and RAM. When ROM and RAM have insufficient capacity, it is possible to connect an external memory as the example of the external memory connection. In this example, the memory configuration is as follows. Memory
ROM SRAM Internal External Internal External
Memory Size
64 Kbytes 128 Kbytes 2 Kbytes 256 Kbytes
Address
FF0000H to FFFFFFH 400000H to 41FFFFH 000080H to 00087FH 800000H to 83FFFFH
Data Bus
16 bits 16 bits 16 bits 16 bits
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3.7
8-Bit Timers
The TMP93CS32 contains four 8-bit timers (Timers 0, 1, 2, 3), each of which can be operated independently. The cascade connection allows these timers to be used as 16-bit timer. The following four operating modes are provided for the 8-bit timers. • • • • 8-bit interval timer mode (4 timers) 16-bit interval timer mode (2 timers) Variable combination (8 bits × 2, 16 bits × 1, etc.)
8-bit programmable square wave pulse generation (PPG: Variable duty with variable cycle) output mode (1 timer) 8-bit pulse width modulation (PWM: Variable duty with constant cycle) output mode (1 timer)
Figure 3.7.1 shows the block diagram of 8-bit timer (Timer 0, 1), and Figure 3.7.2 shows the block diagram of 8-bit timer (Timer 2, 3). Each interval timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. Besides, timer flip-flops (TFF1, TFF3), are provided for pair of timer 0/1 and 2/3. Among the input clock sources for the interval timers, the internal clocks of φT1, φT4, φT16, and φT256 are obtained from the 9-bit prescaler shown in Figure 3.7.3. The operation modes and timer flip-flops of the 8-bit timer are controlled by five control registers T10MOD, T32MOD, TFFCR, TRUN, and TRDC.
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TRUN TRUN
Timer F/F control
TFF1
(Timers 4 and 5)
φT1 Selector 2n − 1 Over flow T10MOD φT1 φT16 φT256 Selector 8-bit up counter (UC0) 8-bit up counter (UC1)
RUN
Clear
RUN
Clear TFFCR, T10MOD
φT4
φT16
T10MOD
Figure 3.7.1 Block Diagram of 8-Bit Timers (Timers 0 and 1)
T10MOD
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8-bit comparator (CP0) INTT0 8-bit timer register TREG0 Internal data bus
8-bit comparator (CP1) Selector T10MOD
8-bit timer register TREG1
INTT1
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TRUN TRUN
Timer F/F control
TFF3
TO3 (Also used as P41)
φT1 Selector 2n − 1 Over flow φT1 φT16 φT256 Selector 8-bit up counter (UC2) 8-bit up counter (UC3)
RUN
Clear
RUN
Clear TFFCR, T32MOD
φT4
φT16
T32MOD T32MOD
Figure 3.7.2 Block Diagram of 8-Bit Timers (Timers 2 and 3)
T32MOD
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8-bit comparator (CP2) INTT2 TO2TRG (to serial channel) 8-bit timer register TREG2 Selector Register buffer TRDC Internal data bus
8-bit comparator (CP3) Selector T32MOD
PPGTRG
INTT3 8-bit timer register TREG3
PWMTRG
TREG-WR
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(1) Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timer 0, 1, 2, and 3, 16-bit timers 4 and 5 and serial interfaces 0 and 1. Figure 3.7.3 shows the block diagram. Table 3.7.1 shows prescaler clock resolution into 8and 16-bit timer.
To CPU System clock fSYS 9-bit prescaler fFPH 2 4 8 16 32 64 128 256 512
÷2
Selector
÷4
φT1 φT4 φT16 φT256 φT1 φT4 φT16 φ1 φT0 φT2 φT8 φT32
To 8-bit timers 0, 1, 2, and 3
SYSCR0 Run/stop & clear TRUN Selector
To 16-bit timers 4 and 5
To serial interfaces 0 and 1
÷2
fc
fc/2
fc/4
fc/8 fc/16
X1
÷2 ÷4 ÷8 ÷16
SYSCR1
Figure 3.7.3 The Block Diagram of Prescaler Table 3.7.1 Prescaler Clock Resolution to 8- and 16-Bit Timer
at fc = 20 MHz
Select Prescaler Clock
Gear Value
000 (fc) fc/2
3
Prescaler Clock Resolution φT1
(0.4 µs) fc/2
5
φT4
(1.6 µs) fc/2
7
φT16
(6.4 µs) fc/2 fc/28 (12.8 µs) fc/29 (25.6 µs) fc/2 fc/2
10 11
φT256
11
(102.4 µs)
00 (fFPH)
001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16)
fc/24 (0.8 µs) fc/25 (1.6 µs) fc/2 fc/2
6 7
fc/26 (3.2 µs) fc/27 (6.4 µs) fc/2 fc/2
8 9
fc/212 (204.8 µs) fc/213 (409.6 µs) fc/214 (819.2 µs) fc/215 (1.6384 ms) fc/215 (1.6384 ms)
(3.2 µs) (6.4 µs)
(12.8 µs) (25.6 µs)
(51.2 µs) (102.4 µs)
10 (fc/16 clock) XXX: Don’t care
XXX
fc/27 (6.4 µs)
fc/29 (25.6 µs)
fc/211 (102.4 µs)
16-bit timer 8-bit timer
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The clock selected among fFPH clock and fc/16 clock is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0. Resetting sets to “00”, therefore fFPH/4 clock is input. The 8-bit Timer selects between 4 clock inputs: φT1, φT4, φT16, and φT256 among the prescaler output. This prescaler can be run or stopped by the timer control register TRUN. Counting starts when is set to “1”, while the prescaler is cleared to zero and stops operation when is cleared to “0”. When the IDLE1 mode (Operates only oscillator) is used, clear TRUN to “0” to stop this prescaler before “HALT” instruction is executed. (2) Up counter This is an 8-bit binary counter which counts up by the input clock pulse specified by T10MOD and T32MOD. The input clock of timers 0 and 2 is selected from the three internal clocks φT1, φT4, and φT16, according to the set value of T10MOD/T32MOD registers. The input clock of timer 1 and 3 differs depending on the operation mode. When set to 16-bit timer mode, the overflow outputs of timer 0 and 2 are used as the input clock. When set to any other mode than 16-bit timer mode, the input clock is selected from the internal clocks φT1, φT16, and φT256 as well as the comparator output (match detection signal) of timer 0, 2 according to the set value of T10MOD and T32MOD registers. Example: When T10MOD = “01”, the overflow output of timer 0 becomes the input clock of timer 1 (16-bit timer mode). When T10MOD = “00” and T10MOD = “01”, φT1 becomes the input of timer 1 (8-bit timer mode). Operation mode is also set by T10MOD and T32MOD registers. When reset, it is initialized to T10MOD = “00” and T32MOD = “00” whereby the up counter is placed in the 8-bit timer mode. The counting and stop and clear of up counter can be controlled for each interval timer by the timer operation control register TRUN. When reset, all up-counters will be cleared to stop the timers.
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(3) Timer register This is an 8-bit register for setting an interval time. When the set value of timer registers TREG0, TREG1, TREG2, and TREG3, matches the value of up-counter, the comparator match detect signal becomes active. If the set value is 00H, this signal becomes active when the up-counter overflows. Timer registers TREG2, are double buffer structure, each of which makes a pair with register buffer. The timer flip-flop controll register TRDC bits control whether the double buffer structure in the TREG2 should be enabled or disabled. They are disabled when = 0 and enabled when they are set to 1. In the condition of double buffer enable state, the data is transfered from the register buffer to the timer register when the 2n − 1 overflow occurs in PWM mode, or at the PPG cycle in PPG mode. Therefore, during timer mode, the double buffer can not be used. When reset, it will be initialized to = 0 to disable the double buffer. To use the double buffer, write data in the timer register, set to 1, and write the following data in the register buffer.
Up counter
Comparator (CP2)
Timer registers 2 (TREG2) Matching detection of PPG cycle 2n − 1 overflow of PWM TREG2 WR
Shift trigger Register buffers 2
Selector
Write Internal data bus
TRDC
Figure 3.7.4 Configuration of Timer Register 2 Note: Timer register and the register buffer are allocated to the same memory address. When = 0, the same value is written in the register buffer as well as the timer register, while when = 1 only the register buffer is written.
The memory address of each timer register is as follows. TREG0 : 000022H TREG1 : 000023H TREG2 : 000026H TREG3 : 000027H
All the registers are write-only and cannot be read.
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(4) Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0, INTT1, INTT2, INTT3) is generated. If the timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (Timer F/F: TFF1, TFF3) The timer flip-flop (TFF1, TFF3) is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. Inverting is disabled or enabled by the timer flip-flop control register TFFCR. After reset operation, the value of TFF1 and TFF3 is undefined. Writing “01” or “10” to TFFCR sets “0” or “1” to TFF1, TFF3. Additionally, writing “00” to this bit inverts the value of TFF1, TFF3 (Software inversion). The signal of TFF3 is output through the TO3 pin (Also used as P41). When using as the timer output, the timer flip-flop should be set by port 4 function register P4FC beforehand. The output pin of TFF1 does not exist.
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Timer Operation Control Register 7
TRUN (0020H) Bit symbol Read/Write After reset Function PRRUN R/W 0 0 0 0
6
5
T5RUN
4
T4RUN
3
T3RUN R/W
2
T2RUN 0
1
T1RUN 0
0
T0RUN 0
Prescaler and timer run/stop control 0: Stop and clear 1: Run (count up)
Count operation 0 1 Stop and clear Count
PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (Timer 5) T4RUN: Operation of 16-bit timer (Timer 4) T3RUN: Operation of 8-bit timer (Timer 3) T2RUN: Operation of 8-bit timer (Timer 2) T1RUN: Operation of 8-bit timer (Timer 1) T0RUN: Operation of 8-bit timer (Timer 0) Note: TRUN is always read as “1”.
System Clock Control Register 7
SYSCR0 (006EH) Bit symbol Read/Write After reset Function 1 (Note) Always write “1” (This bit is read as “1”). 0 (Note) Always write “0” (This bit is read as “0”). 1 (Note) Always write “1” (This bit is read as “1”). 0 (Note) Always write “0” (This bit is read as “0”). −
6
−
5
−
4
− R/W
3
− 0 (Note) Always write “0” (This bit is read as “0”).
2
− 0 (Note) Always write “0” (This bit is read as “0”).
1
PRCK1 0
0
PRCK0 0
Select prescaler clock 00: fFPH 01: (Reserved) 10: fc/16 11: (Reserved)
Select prescaler input clock 00 01 10 11 fFPH (Reserved) fc/16 (Reserved)
Figure 3.7.5 8-Bit Timer Related Registers (1/5)
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Timers 0 and 1 Mode Control Register 7
T10MOD (0024H) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: − 11: − T10M1 R/W 0 0 0 Source clock of timer 1 00: TO0TRG 01: φT1 10: φT16 11: φT256
6
T10M0
5
4
3
T1CLK1
2
T1CLK0 R/W
1
T0CLK1 0
0
T0CLK0 0
Source clock of timer 0 00: Don’t set 01: φT1 10: φT4 11: φT16
Input clock of timer 0 00 01 10 11 Don’t set φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler)
T10MOD ≠ 01 T10MOD = 01
Input clock of timer 1 00 01 10 11 00 01 10 11 Comparator output of timer 0 Internal clock φT1 Internal clock φT16 Internal clock φT256 Two 8-bit timers (timer 0 and timer 1) 16-bit timer − − (16-bit timer mode) Overflow output of timer 0
Set the operation mode of timers 0 and 1.
Figure 3.7.6 8-Bit Timer Related Register (2/5)
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Timers 2 and 3 Mode Control Register 7
T32MOD (0028H) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 PWM cycle 00: − 01: 26 − 1 10: 27 − 1 11: 28 − 1 0 T32M1
6
T32M0
5
PWM21
4
PWM20 R/W
3
T3CLK1 0
2
T3CLK0 0
1
T2CLK1 0
0
T2CLK0 0
Source clock of timer 3 00: TO2TRG 01: φT1 10: φT16 11: φT256
Source clock of timer 2 00: Don’t set 01: φT1 10: φT4 11: φT16
Input clock of timer 2 00 01 10 11 Don’t set φT1 (Prescaler) φT4 (Prescaler) φT16 (Prescaler)
T32MOD ≠ 01 T32MOD = 01
Input clock of timer 3 00 01 10 11 00 01 10 11 00 01 10 11 Comparator output of timer 2 Internal clock φT1 Internal clock φT16 Internal clock φT256 * Don’t care (26 − 1) × input clock frequency of timer 2 (27 − 1) × input clock frequency of timer 2 (28 − 1) × input clock frequency of timer 2 Two 8-bit timers (timer 2 and timer 3) 16-bit timer 8-bit PPG output 8-bit PWM output (timer 2) + 8-bit timer (timer 3) (16-bit timer mode) Overflow output of timer 2
Select PWM cycle
Set the operation mode of timers 2 and 3.
Figure 3.7.7 8-Bit Timer Related Register (3/5)
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Timer Flip-Flop Control Register 7
TFFCR (0025H) Bit symbol Read/Write After reset Function 00: 01: 10: 11: 1 Invert TFF3 Set TFF3 Clear TFF3 Don’t care TFF3C1 W 1 0 TFF3 Inversion trigger 0: Disable 1: Enable
6
TFF3C0
5
TFF3IE R/W
4
TFF3IS 0 TFF3 Inversion source 0: Timer 2 1: Timer 3 00: 01: 10: 11:
3
TFF1C1 W 1 Invert TFF1 Set TFF1 Clear TFF1 Don’t care
2
TFF1C0 1
1
TFF1IE R/W 0 TFF1 Inversion trigger 0: Disable 1: Enable
0
TFF1IS 0 TFF1 Inversion source 0: Timer 0 1: Timer 1
Select inverse signal of timer F/F3 (“Don’t care” except in 8-bit timer mode) 0 1 0 1 00 01 10 11 Inversion by timer 2 Inversion by timer 3 Disable invert Enable invert Invert the value of TFF3 (software inversion) Set TFF3 to “1”. Clear TFF3 to “0”. Don’t care
Select inverse signal of timer F/F1 (“Don’t care” except in 8-bit timer mode) 0 1 0 1 00 01 10 11 Inversion by timer 0 Inversion by timer 1 Disable invert Enable invert Invert the value of TFF1 (software inversion) Set TFF1 to “1”. Clear TFF1 to “0”. Don’t care
Inversion of timer F/F3 (TFF3)
Inversion of Timer F/F1 (TFF1)
Control of timer F/F3 (TFF3)
Control of Timer F/F1 (TFF1)
Note:
TFFCR is always read as “1”.
Figure 3.7.8 8-Bit Timer Related Register (4/5)
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Timer Register Double Buffer Control Register 7
TRDC (0029H) Bit symbol Read/Write After reset Function 0 0: Double buffer disable 1: Double buffer enable
6
5
4
3
2
1
TR2DE R/W
0
− 0 (Note) Always write “0”.
Operation of timer register 2 double butter 0 1 Disable Enable
Figure 3.7.9 8-Bit Timer Related Register (5/5)
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(1) 8-bit timer mode Four interval timers 0, 1, 2, and 3, can be used independently as 8-bit interval timer. Generating interrupts in a fixed cycle (in case of timer 3) To generate timer 3 interrupt at constant intervals using timer 3 (INTT3), first stop timer 3 then set the operation mode, input clock, and a cycle to T32MOD and TREG3 register, respectively. Then, enable interrupt INTT3 and start the counting of timer 3.
Example: To generate timer 3 interrupt every 10 µs at fc = 20 MHz, set each register in the following manner. * Clock Condition Clock gear: 1 (fc) Prescaler clock: fFPH LSB 4 3 2 1 0 − − 1 − − Stop timer 3, and clear it to “0”. Set the 8-bit timer mode, and select φT1 (0.4 µs at fc = 20 MHz) as the input clock. Set the timer register 10 µs ÷ φT1 = 25 = 19H Enable INTT3, and set it to “Level 5”. Start timer 3 counting. −− 1− 0 − − 0 − −
1.
MSB 765 TRUN T32MOD TREG3 INTET32 TRUN ←− ←0 ←0 ←1 ←1
X−−0 0XX0 00 10 X− 1 1 − 1 − 1
X: Don’t care, −: No change
Use the Table 3.7.1 for selecting the input clock. Note: The input clock of timer 2 and timer 3 are different from as follows. Timer 2: φT1, φT4, φT16 Timer 3: Match output of timer 2, φT1, φT16, and φT256
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2. Generating a 50% duty square wave pulse The timer flip-flop is included in timers 1 and 3. The timer flip-flop (TFF3) is inverted at constant intervals, and its status is output to timer output pin (TO3). The output pin of TFF1 does not exist.
Example: To output a 2.4 µs square wave pulse from TO3 pin at fc = 20 MHz, set each register in the following procedures. Either timer 2 or timer 3 may be used, but this example uses timer 3. * Clock Condition Clock gear: 1 (fc) Prescaler clock: fFPH 1 0 − − 1 − − X − Stop timer 3, and clear it to “0”. Set the 8-bit timer mode, and select φT1 (0.4 µs at fc = 20 MHz) as the input clock. Set the timer register at 2.4 µ s ÷ φT1 ÷ 2 = 3. Set TFF3 to “0”, and set to invert by the match detect signal from timer 3. Select P41 as TO3 pin. Start timer 3 counting.
7 TRUN T32MOD TREG3 TFFCR P4CR P4FC TRUN ←− ←0 ←0 ←1
6
5
4
3
2
X−−0 0XX0 0 0 0 1 0 1 0 −
−− 1− 0 − − − − 1 − 1 1 −
←X X X X − ←X X X X − ←1 X − − 1
X: Don’t care, −: No change
φT1 TRUN BIT7 to BIT2 Up counter BIT1 BIT0 Comparator timing Comparator output (matching detect) INTT3 UC3 clear TFF3 TO3 1.2 µs at fc = 20 MHz 0 1 2 3 0 1 2 3 0 1 2 3 0
Figure 3.7.10 Square Wave (50% duty) Output Timing Chart
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3. Making timer 1 count up by match signal from timer 0 comparator (Same function is achieved by using timer 3 and timer 2) Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1.
Comparator output (Timer 0 match) Timer 0 up counter (when TREG0 = 5) Timer 1 up counter (when TREG1 = 2) Timer 1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3
Figure 3.7.11 Timer 1 Count up by Timer 0 (2) 16-bit timer mode A 16-bit interval timer is configured by using the pair of timer 0 and timer 1 or timer 2 and timer 3. To make a 16-bit interval timer by cascade connecting timer 0 and timer 1, set timer 1/0 mode register T10MOD to “01”. When set in 16-bit timer mode, the overflow output of timer 0 and 2 will become the input clock of timers 1 and 3, regardless of the set value of T10MODand T32MOD. Table 3.7.1 shows the relation between the cycle of timer (interrupt) and the selection of input clock. The lower 8 bits of the timer (Interrupt) cycle are set by the timer register TREG0 or TREG2, and the upper 8 bits are set by TREG1 or TREG3. Note that TREG0 and TREG2 always must be set first. (Writing data into TREG0 and TREG2 disables the comparator temporarily, and the comparator is restarted by writing data into TREG1 and TREG3.)
Setting example: To generate an interrupt INTT3 every 0.4 seconds at fc = 20 MHz, set the following values for timer registers TREG2 and TREG3. * Clock Condition Clock gear: 1 (fc) Prescaler clock: fFPH
When counting with input clock of φT16 (6.4 µs at 20 MHz) 0.4 s ÷ 6.4 µs = 62500 = F424H Therefore, set TREG3 = F4H and TREG2 = 24H, respectively. The comparator match signal is output from timer 2 each time the up counter UC2 matches TREG2, where the up counter UC2 is not be cleared, and the interrupt INTT2 is not generated. With the timer 3 comparator, the match detect signal is output at each comparator timing when up counter UC3 and TREG3 values match. When the match detect signal is output simultaneously from both comparators of timer 2 and timer 3, the up counters UC2 and UC3 are cleared to “0”, and the interrupt INTT3 is generated. If inversion is enabled, the value of the timer flip-flop TFF3 is inverted.
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Example: When TREG3 = 04H and TREG2 = 80H Value of up counter (UC3, UC2) Timer 2 comparator match detect signal Interrupt INTT3 Timer output TO3 Inversion 0000H 0080H 0180H 0280H 0380H 0480H
Figure 3.7.12 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable Pulse Generation) output mode Square wave pulse can be generated at any frequency and duty by timer 2. The output pulse may be either low active or high active. In this mode, timer 3 cannot be used. Timer 2 outputs pulse to TO3 pin (also used as P41).
tH tL
t TREG2 and UC2 match (Interrupt INTT2) TREG3 and UC2 match (Interrupt INTT3) TO3 TREG2 TREG3
Figure 3.7.13 8-Bit PPG Output Waveforms In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up counter (UC2) matches the timer registers TREG2 and TREG3. However, it is required that the set value of TREG2 is smaller than that of TREG3. Though the up counter (UC3) of timer 3 is not used in this mode, UC3 should be set for counting by setting TRUN to 1. Figure 3.7.14 shows the block diagram for this mode.
TRUN φT1 φT4 φT16 8-bit up counter (UC2) TO3 TFFCR Inversion T32MOD INTT2 Comparator Comparator INTT3
Selector
TFF3
TREG2 Selector TREG2-WR TRDC Register buffer TREG3 Shift trigger
Internal data bus
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
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When the double buffer of TREG2 is enabled in this mode, the value of register buffer will be shifted in TREG2 each time TREG3 matches UC2. Use of the double buffer makes easy the handling of low duty waves (when duty is varied).
Match with TREG2 and up counter (Up counter = Q1) Match with TREG 3 TREG2 (Value to be compared) Register buffer Q1 Q2 Shift from register buffer Q2 Q3 TREG2 (Register buffer) write (Up counter = Q2)
Figure 3.7.15 Operation of Register Buffer
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Example: Generating 1/4 duty 62.5 kHz pulse (at fc = 20 MHz)
16 µs * Clock condition Clock gear: 1 (fc) Prescaler clock: fFPH
Calculate the value to be set for timer register. To obtain the frequency 62.5 kHz, the pulse cycle t should be: t = 1/62.5 kHz = 16 µs. Given φT1 = 0.4 µs (at 20 MHz), 16 µs ÷ 0.4 µs = 40 Consequently, to set the timer register 3 (TREG3) to TREG3 = 40 = 28H and then duty to 1/4, t × 1/4 = 16 µs × 1/4 = 4 µs 4 µs ÷ 0.4 µs = 10 Therefore, set timer register 2 (TREG2) to TREG2 = 10 = 0AH.
7 TRUN T32MOD TREG2 TREG3 TFFCR P4CR P4FC TRUN ← ← ← ← ← − 1 0 0 0 6 X 0 0 0 1 5 − X 0 1 1 4 − X 0 0 X 3 0 X 1 1 − 2 0 X 0 0 − − − 1 1 − 0 1 0 − 1 1 − 0 − 1 0 0 − − X − Stop timer 2, 3 and clear it to “0”. Set the 8-bit PPG mode, and select φT1 as input clock. Write “0AH”. Write “28H”. Sets TFF3 and enable the inversion and double buffer enable. Writing “10” provides negative logic pulse. Set P41 as the TO3 pin. Start timer 2 and timer 3 counting.
←X X X X − ←X X X X − ←1 X − − 1
X: Don’t care −: No change
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(4) 8-bit PWM output mode This mode is valid only for timer 2. In this mode, maximum 8-bit resolution of PWM pulse can be output. PWM pulse is output to TO3 pin (also used as P41) when using timer 2. Timer 3 can also be used as 8-bit timer. Timer output is inverted when up counter (UC2) matches the set value of timer register TREG2 or when 2n − 1 (n = 6, 7, or 8; specified by T32MOD) counter overflow occurs. Up counter UC2 is cleared when 2n − 1 counter overflow occurs. To use this PWM mode, the following conditions must be satisfied. (Set value of timer register) < (Set value of 2n − 1 counter overflow) (Set value of timer register) ≠ 0
TREG2 and UC2 match 2n − 1 overflow (Interrupt INTT2)
TO3 tPWM (PWM cycle)
Figure 3.7.16 8-Bit PWM Waveforms Figure 3.7.17 shows the block diagram of this mode.
TRUN φT1 φT4 φT16 8-bit up counter (UC2) TO3
Selector
Clear
TFF3 Invert
TFFCR
T32MOD
2 −1 overflow control
n
T32MOD = 11 T32MOD Overflow
Comparator
INTT2 TREG2 Selector TREG2-WR TRDC Register buffer Shift trigger
Internal data bus
Figure 3.7.17 Block Diagram of 8-Bit PWM Mode
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In this mode, the value of register buffer will be shifted in TREG2 if 2n − 1 overflow is detected when the double buffer of TREG2 is enabled. Use of the double buffer makes easy the handling of small duty waves.
Match with TREG2 Up counter = Q1 2n − 1 overflow Shift into TREG2 TREG 2 (Value to be compared) Register buffer Q1 Q2 Q2 Q3 TREG2 (Register buffer) write Up counter = Q2
Figure 3.7.18 Operation of Register Buffer
Example: To output the following PWM waves to TO3 pin at fc = 20 MHz.
28.8 µs 50.8 µs * Clock condition Clock gear: 1 (fc) Prescaler clock: fFPH
To realize 50.8 µs of PWM cycle by φT1 = 0.4 µs (at fc = 20 MHz), 50.8 µs ÷ 0.4 µs = 127 = 2n − 1 Consequently, n should be set to 7. As the period of low level is 28.8 µs, for φT1 = 0.4 µs, set the following value for TREG2. 28.8 µs ÷ 0.4 µs = 72 = 48H
MSB 765 TRUN T32MOD TREG2 TFFCR P4CR P4FC TRUN ←− ←1 ←0 ←1 LSB 4 3 − − 2 0 − 0 − − − 1 1 − 0 0 − 1 1 − 0 − 1 0 − − X − Stop timer 2, and clear it to “0”. Set 8-bit PWM mode (cycle: 27 − 1) and select φT1 as the input clock. Writes “48H”. Clears TFF3, enable the inversion and double buffer.
X−− 110 1 0
001 1X−
←X X X X − ←X X X X − ←1 X − − −
Set P41 as the TO3 pin. Start timer 2 counting.
X: Don’t care, −: No change
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Table 3.7.2 PWM Cycle
at fc = 20 MHz Select Gear Value Prescaler Clock 000 (fc) 00 (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16)
10 (fc/16 clock)
PWM Cycle 26 − 1 φT1 25.2 µs 50.4 µs 100.8 µs 201.6 µs 403.2 µs 403.2 µs φT4 100.8 µs 201.6 µs 403.2 µs 806.4 µs 1.61 ms 1.61 ms φT16 403.2 µs 806.4 µs 1.61 ms 3.23 ms 6.45 ms 6.45 ms φT1 50.8 µs 101.6 µs 203.2 µs 406.4 µs 812.8 µs 812.8 µs 27 − 1 φT4 203.2 µs 406.4 µs 812.8 µs 1.63 ms φT16 812.8 µs 1.63 ms 3.26 ms 6.52 ms φT1 102.0 µs 204.0 µs 408.0 µs 816.0 µs 1.63 ms 1.63 ms 28 − 1 φT4 408.0 µs 816.0 µs 1.63 ms φT16 1.63 ms 3.26 ms 6.53 ms
3.26 ms 13.06 ms 6.53 ms 26.11 ms 6.53 ms 26.11 ms
3.25 ms 13.04 ms 3.25 ms 13.04 ms
XXX XXX: Don’t care
(5) Timer mode setting registers Table 3.7.3 shows the list of 8-bit timer modes. Table 3.7.3 Timer Mode Setting Registers
Register Name Name of Function in Register Function 16-bit timer mode T10M/T32M Timer Mode 01 * − * 8-bit timer × 2 channels * 8-bit PPG × 1channel * 8-bit PWM × 1channel 8-bit timer × 1channel −: Don’t care *: Don’t set in T10MOD * 11 11 10 − 00 * − * − * − φT1, φT4, φT16 (01, 10, 11) − T10MOD/T32MOD PWM2 PWM Cycle T1CLK/T3CLK Upper Timer Input Clock − Lower timer match: φT1, 16, 256 (00, 01, 10, 11) * φT1, φT4, φT16 (01, 10, 11) T0CLK/T2CLK Lower Timer Input Clock φT1, φT4, φT16 (01, 10, 11) φT1, φT4, φT16 (01, 10, 11) TFFCR TFF1IS/TFF3IS Timer F/F Invert Signal Select − 0: Lower timer output 1: Upper timer output * − * − Output disabled
* * 26 − 1, 27 − 1, 28 − 1 (01, 10, 11) −
φT1, φT16, φT256 (01, 10, 11)
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3.8
16-Bit Timers/Event Counters
The TMP93CS32 contains two (Timer 4 and timer 5) multifunctional 16-bit timer/event counter with the following operation modes. • • • 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) mode Can be used following operation modes by capture function. • • • Frequency measurement mode Pulse width measurement mode Time differential measurement mode
Timer/event counter consists of 16-bit up counter, two 16-bit timer registers, two 16-bit capture registers (One of them applies double buffer), two comparators, capture input controller, and timer flip-flop and the control circuit. Timer/event counter is controlled by 4 control registers: T4MOD/T5MOD, T4FFCR/T5FFCR, TRUN and T45CR. Figure 3.8.1 and Figure 3.8.2 shows the block diagram of 16-bit timer/event counter (timer 4 and timer 5). Timer 4 and 5 can be used independently. All timer operate in the same manner, and thus only the operation of Timer 4 will be explained below.
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Internal data bus Upper byte 16-bit capture register 1 (CAP1) T4MOD Software capture Trigger Trigger 16-bit capture register 2 (CAP2) T4FFCR Lower byte Upper byte Lower byte
TFF1 TFF4 Timer F/F control TRUN INTTR5 INTTR4 Clear Selector 16-bit up counter UC4 TRUN T4MOD INTTO4 T4MOD TO4
TI4
Capture
control
TI5
T4MOD φT1 φT4 φT16
TI4 external input
INT4 INT5
Figure 3.8.1 Block Diagram of 16-Bit Timer (Timer 4)
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16-bit comparator (CP4) Match detection 16-bit timer register (TREG4) Selector Register buffer4 Upper byte T45CR Lower byte Internal data bus TREG4-WR
16-bit comparator (CP5)
Match detection
16-bit timer register (TREG5)
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Upper byte
Lower byte
Internal dadta bus Upper byte 16-bit capture register 3 (CAP3) T5MOD Software capture Trigger Trigger 16-bit capture register 4 (CAP4) T5FFCR Lower byte Upper byte Lower byte
TFF1 TFF6 Timer F/F control TRUN INTTR7 INTTR6 Clear Selector 16-bit up counter (UC5) TRUN T5MOD INTTO5 T5MOD TO6
Capture
TI6
control
TI7
T5MOD φT1 φT4 φT16
Figure 3.8.2 Block Diagram of 16-Bit Timer (Timer 5)
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16-bit comparator (CP6) Match detection 16-bit timer register (TREG6) Selector Register buffer 6 Upper byte T45CR Lower byte Internal data bus TREG6-WR
TI6 external input
INT6 INT7
16-bit comparator (CP7)
Match detection
16-bit timer register (TREG7)
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Upper byte
Lower byte
TMP93CS32
Timer 4 Mode Control Register 7
T4MOD (0038H) Bit symbol Read/Write After reset Function
6
5
CAP1IN W 1 0: Software capture 1: Don’t care
4
CAP12M1 0 Capture timing 00: Disable
3
CAP12M0 0
2
CLE R/W 0 1: UC4 clear enable
1
T4CLK1 0
0
T4CLK0 0
INT4 occurs at rising edge.
01: TI4↑ 10: TI4↑ 11: TFF1↑
TI5↑ TI4↓ TFF1↓
INT4 occurs at rising edge.
Timer 4 source clock 00: TI4 pin 01: φT1 10: φT4 11: φT16
INT4 occurs at falling edge.
INT4 occurs at rising edge.
Timer 4 input clock 00 External clock (TI4) 01 10 11 φT1 φT4 φT16
Clearing the up counter UC4 0 Clear disable 1 Clear by match with TREG5. INT4 control INT4 occurs on the rising edge of TI4. INT4 occurs on the falling edge of TI4. Capture timing of timer 4 Capture control 00 Capture disable 01 10 11 CAP1 at TI4 rise CAP2 at TI5 rise CAP1 at TI4 rise CAP2 at TI4 fall
CAP1 at TFF1 rise INT4 occurs on the CAP2 at TFF1 fall rising edge of TI4.
Software capture 0 The up counter 4 value is loaded to CAP1. 1 Don’t care
Figure 3.8.3 16-Bit Timer/Event Counter Related Register (1/6)
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Timer 4 Flip-Flop Control Register 7
T4FFCR (0039H) Bit symbol Read/Write After reset Function 0 TFF4 invert trigger 0: Trigger disable 1: Trigger enable
Invert when the UC value is loaded to CAP2. Invert when the UC value is loaded to CAP1. Invert when the UC matches TREG5. Invert when the UC matches TREG4.
6
5
CAP2T4
4
CAP1T4 R/W 0
3
EQ5T4 0
2
EQ4T4 0
1
TFF4C1 W 1 TFF4 control 00: Invert TFF4 01: Set TFF4 10: Clear TFF4 11: Don’t care
0
TFF4C0 1
Timer flip-flop 4 (TFF4) control 00 Inverts the TFF4 value (Software inversion). 01 10 11 Sets TFF4 to “1”. Clear TFF4 to “0”. Don’t care (Always read “11”).
Timer flip-flop 4 (TFF4) invert trigger at the up counter matches TREG4 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) Timer flip-flop 4 (TFF4) invert trigger at the up counter matches TREG5 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) Timer flip-flop 4 (TFF4) invert trigger at the up counter value is loaded to CAP1 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission) Timer flip-flop 4 (TFF4) invert trigger at the up counter value is loaded to CAP2 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission)
Figure 3.8.4 16-Bit Timer/Event Counter Related Register (2/6)
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Timer 5 Mode Control Register 7
T5MOD (0048H) Bit symbol Read/Write After reset Function
6
5
CAP3IN W 1 Software capture control 0: Software capture 1: Don’t care
4
CAP34M1 0 Capture timing 00: Disable
3
CAP34M0 0
2
CLE R/W 0 Timer 5 UC control 0: Clear disable 1: Clear enable
1
T5CLK1 0
0
T5CLK0 0
Timer 5 source clock select 00: 01: 10: 11: TI6 pin φT1 φT4 φT16
INT6 occurs on the rising edge.
01: TI6↑ 10: TI6↑ 11: TFF1↑
TI7↑ TI6↓ TFF1↓
INT6 occurs at rising edge.
INT6 occurs at falling edge.
INT4 occurs at rising edge.
Timer 5 input clock 00 External clock (TI6 pin input) 01 10 11 φT1 φT4 φT16
Clearing the up counter UC5 0 Clear disable 1 Clear by match with TREG7 INT6 control INT6 occurs on the rising edge of TI6. INT6 occurs on the falling edge of TI6. Timer 5 capture timing Capture control 00 Capture disable 01 10 11 CAP3 at TI6 rise CAP4 at TI7 rise CAP3 at TI6 rise CAP4 at TI6 fall
CAP3 at TFF1 rise INT6 occurs on the CAP4 at TFF1 fall rising edge of TI6.
Software capture 0 The up counter 5 value is loaded to CAP3. 1 Don’t care
Figure 3.8.5 16-Bit Timer/Event Counter Related Register (3/6)
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Timer 5 Flip-Flop Control Register 7
T5FFCR (0049H) Bit symbol Read/Write After reset Function 0 TFF6 invert trigger 0: Disable trigger 1: Enable trigger
Invert when the UC value is loaded to CAP4. Invert when the UC value is loaded to CAP3. Invert when the UC matches TREG7. Invert when the UC matches TREG6.
6
5
CAP4T6
4
CAP3T6 R/W 0
3
EQ7T6 0
2
EQ6T6 0
1
TFF6C1 W 1 TFF6 control 00: Invert TFF6 01: Set TFF6 10: Clear TFF6 11: Don’t care
0
TFF6C0 1
Timer flip-flop 6 (TFF6) control 00 Inverts the TFF6 value (Software inversion). 01 10 11 Sets TFF6 to “1”. Clear TFF6 to “0”. Don’t care (Always read “11”)
Timer flip-flop 6 (TFF6) invert trigger at up counter matches TREG6 0 Trigger disable (Invert prohibition) 1 CAP4T6: CAP3T6: EQ7T6: EQ6T6: Trigger enable (Invert permission) Invert when the up counter value is loaded to CAP4 Invert when the up counter value is loaded to CAP3 Invert when up counter matches TREG7 Invert when up counter matches TREG6 Timer flip-flop 6 (TFF6) invert trigger at up counter matches TREG7 0 Trigger disable (Invert prohibition) 1 Trigger enable (Invert permission)
Figure 3.8.6 16-Bit Timer/Event Counter Related Register (4/6)
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Timer 4, 5 Control Register 7
T45CR (003AH) Bit symbol Read/Write After reset Function QCU R/W 0 Watchdog/ Warm-up timer control 0 Double buffer 0: Disable 1: Enable Double buffer of TREG6 Double buffer of TREG4
6
5
4
3
2
1
DB6EN R/W
0
DB4EN 0
Double buffer control 0 Disable 1 Enable DB6EN: Double buffer of TREG6 DB4EN: Double buffer of TREG4 Watchdog timer/warm-up timer input control 0 Use 7 stage binary counter 1 Not use 7 stage binary counter (Note1)
Note 1:
In case of unused 7 state binary counter as a warm-up timer, the stable clock must be input from external circuit.
Note 2:
Bit6 to 2 of T45CR are read as “1”.
Figure 3.8.7 16-Bit Timer/Event Counter Related Register (5/6)
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Timer Operation Control Register 7
TRUN (0020H) Bit symbol Read/Write After reset Function PRRUN R/W 0 0 0 0
6
5
T5RUN
4
T4RUN
3
T3RUN R/W
2
T2RUN 0
1
T1RUN 0
0
T0RUN 0
Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up)
Count operation 0 Stop and clear 1 Count PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (timer 5) T4RUN: Operation of 16-bit timer (timer 4) T3RUN: Operation of 8-bit timer (timer 3) T2RUN: Operation of 8-bit timer (timer 2) T1RUN: Operation of 8-bit timer (timer 1) T0RUN: Operation of 8-bit timer (timer 0) Note: Bit6 of TRUN is read as “1”.
System Clock Control Register 7
SYSCR0 (006EH) Bit symbol Read/Write After reset Function 1 (Note) Always write “1” (This bit is read as “1”). 0 (Note) Always write “0” (This bit is read as “0”). 1 (Note) Always write “1” (This bit is read as “1”). 0 (Note) Always write “0” (This bit is read as “0”). −
6
−
5
−
4
− R/W
3
− 0 (Note) Always write “0” (This bit is read as “0”).
2
− 0 (Note) Always write “0” (This bit is read as “0”).
1
PRCK1 0
0
PRCK0 0
Select prescaler clock 00: fFPH 01: (Reserved) 10: fc/16 11: (Reserved)
Select gear value of high frequency 00 fFPH 01 10 11 (Reserved) fc/16 (Reserved)
Figure 3.8.8 16-Bit Timer/Event Counter Related Registers (6/6)
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(1) Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timer 0, 1, 2, and 3, 16-bit timers 4 and 5 and serial interfaces 0 and 1. Figure 3.8.9 shows the block diagram. Table 3.8.1 shows prescaler clock resolution into 8and 16-bit timers.
To CPU System clock (fSYS) 9-bit prescaler fFPH 2 4 8 16 32 64 128 256 512
÷2
Selector
÷4
φT1 φT4 φT16 φT256 φT1 φT4 φT16 φ1 φT0 φT2 φT8 φT32
To 8-bit timers 0, 1, 2, and 3
SYSCR0 Run/stop and clear TRUN Selector
To 16-bit timers 4 and 5
÷2
To serial interfaces 0 and 1
fc
fc/2
fc/4
fc/8 fc/16
X1
÷2 ÷4 ÷8 ÷16
SYSCR1
Figure 3.8.9 The Block Diagram of Prescaler Table 3.8.1 Prescaler Clock Resalation to 8- and 16-Bit Timer
at fc = 20 MHz
Select Prescaler Clock
Gear Value
000 (fc)
Prescaler Clock Resolution φT1
fc/23 (0.4 µs) fc/24 (0.8 µs) fc/25 (1.6 µs) fc/26 (3.2 µs) fc/27 (6.4 µs) fc/27 (6.4 µs)
φT4
fc/25 (1.6 µs) fc/26 (3.2 µs) fc/27 (6.4 µs) fc/28 (12.8 µs) fc/29 (25.6 µs) fc/29 (25.6 µs)
φT16
fc/27 (6.4 µs) fc/28 (12.8 µs) fc/29 (25.6 µs) fc/210 (51.2 µs) fc/211 (102.4 µs) fc/211 (102.4 µs)
φT256
fc/211 (102.4 µs) fc/212 (204.8 µs) fc/213 (409.6 µs) fc/214 (819.2 µs) fc/215 (1.6384 ms) fc/215 (1.6384 ms)
00 (fFPH)
001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16)
10 (fc/16 clock) XXX: Don’t care
XXX
16-bit timer 8-bit timer
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The clock selected among fFPH clock and fc/16 clock is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0. Resetting sets to “00”, therefore fFPH/4 clock is input. The 16-bit Timers 4 and 5 selects between 3 clock inputs: φT1, φT4, and φT16 among the prescaler outputs. This prescaler can be run or stopped by the timer operation control register TRUN. Counting starts when is set to “1”, while the prescaler is cleared to zero and stops operation when is cleared to “0”. When the IDLE1 mode (operates only oscillator) is used, clear TRUN to “0” to stop this prescaler before “HALT” instruction is executed. (2) Up counter UC4 is a 16-bit binary counter which counts up according to the input clock specified by T4MOD register. As the input clock, one of the internal clocks φT1, φT4, and φT16 from 9-bit prescaler (also used for 8-bit timer), and external clock from TI4 pin (also used as P42/INT4 pin) can be selected. When reset, it will be initialized to = 00 to select TI4 input mode. Counting or stop and clear of the counter is controlled by timer operation control register TRUN. When clearing is enabled, up counter UC4 will be cleared to zero each time it coincides matches the timer register TREG5. The “clear enable/disable” is set by T4MOD. If clearing is disabled, the counter operates as a free-running counter. A timer overflow interrupt (INTTO4) is generated when UC4 overflow occurs. (3) Timer registers These two 16-bit registers are used to set the interval time. When the value of up counter UC4 matches the set value of this timer register, the comparator match detect signal will be active. Setting data for both upper and lower timer registers (TREG4 and TREG5) is always needed. For example, either using 2-byte date transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order.
Timer 4 TREG 4 Upper 8 bits 000031H Timer 5 TREG 6 Upper 8 bits 000041H Lower 8 bits 000040H TREG 7 Upper 8 bits 000043H Lower 8 bits 000042H Lower 8 bits 000030H TREG 5 Upper 8 bits 000033H Lower 8 bits 000032H
TREG4 to TREG7 are write-only registers, so these registers can not be read by software.
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TREG4 timer register is of double buffer structure, which is paired with register buffer. The timer control register T45CR controls whether the double buffer structure should be enabled or disabled: disabled when = 0, while enabled when = 1. When the double buffer is enabled, the timing to transfer data from the register buffer to the timer register is at the match between the up counter (UC4) and timer register TREG5. After reset, TREG4 and TREG5 are undefined. To use the 16-bit timer after reset, data should be written beforehand. When reset, it will be initialized to = 0, whereby the double buffer is disabled. To use the double buffer, write data in the timer register, set = 1, and then write the following data in the register buffer. TREG4 and register buffer are allocated to the same memory addresses 000030H/000031H. When = 0, same value will be written in both the timer register and register buffer. When = 1, the value is written into only the register buffer. To write the initial-value to the timer register, the register buffer should be disabled. (4) Capture register These 16-bit registers are used to latch the values of the up counter. Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1 byte data load instruction, from the lower 8 bits followed by the upper 8 bits.
Timer 4 CAP 1 Upper 8 bits 000035H Timer 5 CAP 3 Upper 8 bits 000045H Lower 8 bits 000044H CAP 4 Upper 8 bits 000047H Lower 8 bits 000046H Lower 8 bits 000034H CAP 2 Upper 8 bits 000037H Lower 8 bits 000036H
CAP 1 to CAP4 are read-only registers, so these registers cannot be written by software.
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2004-02-10
TMP93CS32
(5) Capture input control This circuit controls the timing to latch the value of up counter UC4 into (CAP1 and CAP2). The latch timing of capture register is controlled by register T4MOD. • • When T4MOD = “00” Capture function is disabled. Disable is the default on reset. When T4MOD = “01” Data is loaded to CAP1 at the rise edge of TI4 pin (also used as P42/INT4) input, while data is loaded to CAP2 at the rise edge of TI5 pin (also used as P43/INT5) input. • When T4MOD = “10” Data is loaded to CAP1 at the rise edge of TI4 pin input, while to CAP2 at the fall edge. Only in this setting, interrupt INT4 occurs at fall edge. • When T4MOD = “11” Data is loaded to CAP1 at the rise edge of timer flip-flop TFF1, while to CAP2 at the fall edge. Besides, the value of up counter can be loaded to capture registers by software. Whenever “0” is written in T4MOD the current value of up counter will be loaded to capture register CAP1. It is necessary to keep the prescaler in RUN mode (TRUN to be “1”). (6) Comparator These are 16-bit comparators which compare the up counter UC4 value with the set value of (TREG4, TREG5) to detect the match. When a match is detected, the comparators generate an interrupt (INTTR4, INTTR5) respectively. The up counter UC4 is cleared only when UC4 matches TREG5 (The clearing of up counter UC4 can be disabled by setting T4MOD = 0). (7) Timer flip-flop (TFF4) This flip-flop is inverted by the match detect signal from the comparators and the latch signals to the capture registers. Disable/enable of inversion can be set for each element by T4FFCR. After reset, the value of TFF4 is undefined. TFF4 will be inverted when “00” is written in T4FFCR. Also it is set to “1” when “01” is written, and set to “0” when “10” is written. The value of TFF4 can be output to the timer output pin TO4 (also used as P44). Timer output should be specified by the function register of Port 4. (See Register for Port 4 in Figure 3.5.10.)
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TMP93CS32
(1) 16-bit timer mode Generating interrupts at fixed intervals In this example, the interval time is set in the timer register TREG5 to generate the interrupt INTTR5.
7 TRUN INTET54 T4FFCR T4MOD TREG5 TRUN ←− ←1 6 5 4 0 0 3 − 1 0 0 2 1 0 − 0 1 * * * − Stop timer 4. Enable INTTR5 and sets interrupt level 4. Disable INTTR4. Disable trigger. Select internal clock for input and disable the capture function. Set the interval time (16 bits). Start timer 4.
X− 10
−− 00 0 1 1 * * * −
←X X 0 0 ←0 0 1 0
(* * = 01, 10,11) ←* * * * * * ****** ←1 X − 1 − −
X: Don’t care, −: No change
(2) 16-bit event counter mode In 16-bit timer mode as described in above, the timer can be used as an event counter by selecting the external clock (TI4 pin input) as the input clock. To read the value of the counter, first perform “software capture” once and read the captured value. The counter counts at the rise edge of TI4 pin input. TI4 pin can also be used as P42/INT4. Since both timers operate in exactly the same way, timer 4 is used for the purposes of explanation.
7 TRUN P4CR INTET54 T4FFCR T4MOD TREG5 TRUN ←− ←− ←1 ← ← ← ← X 0 * 1 6 5 4 3 − − 1 0 0 * − 2 1 0 − − 0 1 0 * − Stop timer 4. Set P42 to input mode. Enable INTTR5 and sets interrupt level 4, while disables INTTR4. Disable trigger. Select TI4 as the input clock. Set the number of counts (16 bits). Start timer 4.
X−0 −−− 100 X 0 * X 00 10 ** −1
−− 0− 00 01 10 ** −−
X: Don’t care, −: No change When used as an event counter, set the prescaler in RUN mode. (TRUN = “1”)
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(3) 16-bit programmable pulse generation (PPG) output mode Square wave pulse can be generated at any frequency and duty by timer 4. The output pulse may be either low-active or high-active. The PPG mode is obtained by inversion of the timer flip-flop TFF4 that is to be enabled by the match of the up counter UC4 with the timer register TREG4 or TREG5 and to be output to TO4 (also used as P44). In this mode, the following conditions must be satisfied. (Set value of TREG4) < (Set value of TREG5)
Match with TREG4 (Interrupt INTTR4) Match with TREG5 (Interrupt INTTR5) TO4 pin
Figure 3.8.10 Programmable Pulse Generation (PPG) Output Waveforms When the double buffer of TREG4 is enabled in this mode, the value of register buffer 4 will be shifted in TREG4 at match with TREG5. This feature makes easy the handling of low duty waves.
Match with TREG4 Up counter = Q1 Match with TREG5 Shift into the TREG5 TREG4 (Value to be compared) Register buffer Q1 Q2 Q2 Q3 Write into the TREG4 Up counter = Q2
Figure 3.8.11 Operation of Register Buffer
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Shows the block diagram of this mode.
TRUN TI4 pin φT1 φT4 φT16 16-bit up counter UC4 TO4 (PPG output) F/F (TFF4)
Selector
Clear
16-bit comparator
Match
16-bit comparator
TREG4 Selector TREG4-WR T45CR Register buffer 4 TREG5
Internal data bus
Figure 3.8.12 Block Diagram of 16-Bit PPG Mode Setting 16-bit programmable pulse generation (PPG) output mode.
7 T45CR TRUN TREG4 TREG5 T45CR T4FFCR T4MOD P4CR P4FC TRUN ←0 ←− ←* * ←* * ←0 6 X X * * * * X 5 4 3 2 1 0 0 − * * * * 1 0 * 1 X − Double Buffer of TRG4 disable. Stop timer 4. Set the duty (16 bits). Set the cycle (16 bits). Double Buffer of TREG4 enable. (Change the duty and cycle at the interrupt INTTR5) Set the mode to invert TFF4 at the match with TREG4/TREG5, and also clear the TFF4 to “0”. Select the internal clock for the input, and disable the capture function. Assign P44 as TO4. Start timer 4.
XX −0 ** ** ** ** XX 0 0
XX− −−− *** *** *** *** XX− 1 0 1 1 1 * −
←X X 0 ←0 0 1
(** = 01, 10, 11) ←− − − 1 − − ←− ←1 XX1 X−1
XX− −−−
X: Don’t care, −: No change
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2004-02-10
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(4) Application examples of capture function Used capture function, they can be applied in many ways, for example: 1. 2. 3. 4. 1. One-shot pulse output from external trigger pulse Frequency measurement Pulse width measurement Time difference measurement
One-shot pulse output from external trigger pulse Set to T4MOD = 01. Set the up counter UC4 in free-running mode with the internal input clock, input the external trigger pulse from TI4 pin, and load the value of up counter into capture register CAP1 at the rise edge of the TI4 pin. When the interrupt INT4 is generated at the rise edge of TI4 input, set the CAP1 value (c) plus a delay time (d) to TREG4 (= c + d), and set the above set value (c + d) plus a one-shot pulse width (p) to TREG5 (= c + d + p). When the interrupt INT4 occurs the T4FFCRregister should be set “11” and that the TFF4 inversion is enabled only when the up counter value matches TREG4 or TREG5. When interrupt INTTR5 occurs, this inversion will be disabled after one-shot pulse is output. The (c), (d), and (p) correspond to c, d, and p in Figure 3.8.13.
Set the counter in free-running mode. Count clock (Internal clock) TI4 pin input (External trigger pulse) Match with TREG4 Match with TREG5 Inversion enable Disables inversion caused by loading of the up counter value into CAP1. Delay time (d) Inversion enable INTTR5 occurred c c+d c+d+p
Load the up counter value into capture register 1 (CAP1) INT4 occurred
Timer output pin TO4
Pulse width (p)
Figure 3.8.13 One-shot Pulse Output (with Delay)
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Setting example: To output 2 ms one-shot pulse with 3 ms delay to the external trigger pulse to TI4 pin
Clock gear: 1 (fc) Prescaler clock: fFPH Keep counting (Free running). Count with φT1. ←− − 1 0 0 1 0 0 0 0 1 1 0 Load the up counter value into CAP1 at the rise edge of TI4 pin input. Clear TFF4 to zero. Disable TFF4 inversion. P4CR P4FC INTE45 INTET54 TRUN ←− ←− ←− ←1 ←1 − − 1 − − − 1 X 0 0 − XX1 −−− 00 X− 0 1 XX− 110 1 − 00 −− Select P44 as the TO4 pin. Enable INT4, and disable INTTR4 and INTTR5. Start timer 4.
* Clock Condition
Main setting T4MOD T4FFCR
←X X 0
Setting of INT4 TREG4 TREG5 T4FFCR ← CAP1 + 3 ms/φT1 ← TREG4 + 2 ms/φT1 ←X X − − 1 1 −
− Enable TFF4 inversion when the up counter value matches TREG4 or TREG5.
INTET54
←1
1
0
0
−
−
−
−
Enable INTTR5.
Setting of INTTR5 T4FFCR ←X X − − 0 0 − − Disable TFF4 inversion when the up counter value matches TREG4 or TREG5. Disable INTTR5.
INTET54
←1
0
0
0
−
−
−
−
X: Don’t care, −: No change
When delay time is unnecessary, invert timer flip-flop TFF4 when the up counter value is loaded into capture register 1 (CAP1), and set the CAP1 value (c) plus the one-shot pulse width (p) to TREG5 when the interrupt INT4 occurs. The TFF4 inversion should be enabled when the up counter (UC4) value matches TREG5, and disabled when generating the interrupt INTTR5.
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Count clock (Internal clock) TI4 pin input (External trigger pulse) c c+p Load the up counter value into capture register 1 (CAP1). INT4 occurred INTTR5 occurred. Load the up counter value into capture register 2 (CAP2).
Match with TREG5 Inversion enable Timer output pin TO4 Pulse width (p) Enables inversion caused by loading of the up counter value into CAP1. Disables inversion caused by loading of the up counter value into CAP2.
Figure 3.8.14 One-Shot Pulse Output (without Delay) 2. Frequency measurement The frequency of the external clock can be measured in this mode. The clock is input through the TI4 pin, and its frequency is measured by the 8-bit timers (Timer 0 and Timer 1) and the 16-bit timer/event counter (Timer 4). The TI4 pin input should be selected for the input clock of Timer 4. The value of the up counter is loaded into the capture register CAP1 at the rise edge of the timer flip-flop TFF1 of 8-bit timers (Timer 0 and Timer 1), and into CAP2 at its fall edge. The frequency is calculated by the difference between the loaded values in CAP1 and CAP2 when the interrupt (INTT0 or INTT1) is generated by either 8-bit timer.
Count clock (Internal clock) C1 TFF1 Loading UC4 into CAP1 Loading UC4 into CAP2 INTT0/INTT1 C1 C2 C1 C2 C2
Figure 3.8.15 Frequency Measurement For example, if the value for the level “1” width of TFF1 of the 8-bit timer is set to 0.5 s. and the difference between CAP1 and CAP2 is 100, the frequency will be 100 ÷ 0.5 [s] = 200 [Hz].
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3. Pulse width measurement This mode allows to measure the “H” level width of an external pulse. While keeping the 16-bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the TI4 pin. Then the capture function is used to load the UC4 values into CAP1 and CAP2 at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT4 occurs at the falling edge of TI4. The pulse width is obtained from the difference between the values of CAP1 and CAP2 and the internal clock cycle. For example, if the internal clock is 0.8 microseconds and the difference between CAP1 and CAP2 is 100, the pulse width will be 100 × 0.8 µs = 80 µs. Additionally, the pulse width which is over the UC4 maximum count time specified by the clock source can be measured by changing software.
Count clock (Internal clock) TI4 pin (External pulse) Loading UC4 into CAP1 Loading UC4 into CAP2 INT4 C1 C2
C1 C2
C1 C2
Figure 3.8.16 Pulse Width Measurement Note: Only in this pulse width measuring mode (T4MOD = 10), external interrupt INT4 occurs at the falling edge of TI4 pin input. In other modes, it occurs at the rising edge.
The width of “L” level can be measured by multiplying the difference between the first C2 and the second C1 at the second INT4 interrupt and the internal clock cycle together. See Figure 3.8.17 Time Difference Measurement.
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4. Time difference measurement This mode is used to measure the difference in time between the rising edges of external pulses input through TI4 and TI5. Keep the 16-bit timer/event counter (Timer 4) counting (free-running) with the internal clock, and load the UC4 value into CAP1 at the rising edge of the input pulse to TI4. Then the interrupt INT4 is generated. Similarly, the UC4 value is loaded into CAP2 at the rising edge of the input pulse to TI5, generating the interrupt INT5. The time difference between these pulses can be obtained from the difference between the time counts at which loading the up counter value into CAP1 and CAP2 was performed. (= (CAP2 − CAP1) × the internal clock cycle)
Count clock (Internal clock) C1 TI4 pin input TI5 pin input Loading UC4 into CAP1 Loading UC4 into CAP2 INT4 INT5 Time difference C2
Figure 3.8.17 Time Difference Measurement
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3.9
Serial Channel
TMP93CS32 contains 2 serial I/O channels for full duplex asynchronous transmission (UART) as well as for I/O extension. The serial channel has the following operation modes. • I/O interface mode (channels 0 and 1) UART mode (channels 0 and 1) Mode 0: To transmit and receive I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data Mode 2: 8-bit data Mode 3: 9-bit data
•
In mode 1 and mode 2, a parity bit can be added. Mode 3 has wake-up function for making the master controller start slave controllers in serial link. Figure 3.9.1 shows the data format (for one frame) in each mode. Serial channels 0 and 1 can be used independently. • Mode 0 (I/O interface mode)
Bit0 1 2 3 4 5 6 7
Transfer direction
• Mode 1 (7-bit UART mode)
No parity Parity Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 Stop Parity Stop
• Mode 2 (8-bit UART mode)
No parity Parity Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Stop Parity Stop
• Mode 3 (9-bit UART mode)
Start Start Bit0 Bit0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Bit8 Stop Stop (Wakeup)
When bit8 = 1, address (select code) is denoted. When bit8 = 0, data is denoted.
Figure 3.9.1 Data Formats
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The serial channel has a buffer register for transmitting and receiving operations, in order to temporarily store transmitted or received data, so that transmitting and receiving operations can be done independently (Full duplex). However, in I/O interface mode, SCLK (Serial clock) pin is used for both transmission and receiving, the channel becomes half-duplex. The receiving data register is of a double buffer structure to prevent the occurrence of overrun error and provides one frame of margin before CPU reads the received data. The receiving data register stores the already received data while the buffer register receives the next frame data. By using CTS and RTS (There is no RTS pin, so any 1 port must be controlled by software), it is possible to halt data send until the CPU finishes reading receive data every time a frame is received (Handshake function). In the UART mode, a check function is added not to start the receiving operation by error start bits due to noise. The channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings. When the transmission buffer becomes empty and requests the CPU to send the next transmission data, or when data is stored in the receiving data register and the CPU is requested to read the data, INTTX or INTRX interrupt occurs. Besides, if an overrun error, parity error, or framing error occurs during receiving operation, flag SC0CR/SC1CR will be set. The serial channel 0/1 includes a special baud rate generator, which can set any baud rate by dividing the frequency of 4 clocks (φT0, φT2, φT8, and φT32) from the internal prescaler (shared by 8-bit/16-bit timer) by the value 1 to 16. In addition, serial channel 0/1 can operated by using external input clock (SCLK 0/1). In I/O interface mode, it is possible to input synchronous signals as well as to transmit or receive data by external clock.
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2004-02-10
TMP93CS32 3.9.1 Control registers
The serial channel 0 is controlled by 3 control registers SC0CR, SC0MOD, and BR0CR. Transmitted and received data are stored in register SC0BUF. Serial Channel 0 Mode Control Register 7
SC0MOD (0052H) Bit symbol Read/Write After reset Function Undefined Transfer data bit8 0 Hand shake function 0: CTS0 disable 1: CTS0 enable 0 Receiving function 0: Receive disable 1: Receive enable 0 Wakeup function 0: Disable 1: Enable TB8
6
CTSE0
5
RXE
4
WU R/W
3
SM1 0
2
SM0 0
1
SC1 0
0
SC0 0
Serial transmission mode 00: I/O interface mode 01: 7-bit UART 10: 8-bit UART 11: 9-bit UART
Serial transmission clock (UART) 00: TO2 trigger 01: Baud rate generator 0 10: Internal clock φ1 11: External clock (SCLK0 input)
Serial transmission clock (UART) 00 Timer 2 match detect signal 01 10 11 Baud rate generator 0 Internal clock φ1 (fSYS) External clock (SCLK0 input)
Serial transmission mode 00 I/O interface mode 01 10 11 UART 7-bit length 8-bit length 9-bit length
Wakeup function (Don’t care in the modes other than 9-bit UART) 0 Disable 1 Enable Receiving function 0 Receive Disable 1 0 1 Receive Enable Disable (Always transferable) Enable Stores transmission parity bit Stores transmission data bit8 Hand shake function ( CTS0 pin)
Transmission data bit8 8-bit UART mode (Parity) 9-bit UART mode
Figure 3.9.2 Serial Channel 0 Related Register (1/7)
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Serial Channel 0 Control Register 7
SC0CR (0051H) Bit symbol Read/Write After reset Function RB8 R Undefined Received data bit8 0 Parity 0: Odd 1: Even
6
EVEN R/W
5
PE 0 Parity addition 0: Disable 1: Enable
4
OERR 0 1: Overrun
3
PERR 0 Error Parity
2
FERR 0 Framing
1
SCLKS R/W 0 0: SCLK0 1: SCLK0
0
IOC 0 0: Baud rate
generator 0
R (cleared to Zero when read)
1: SCLK0 pin input
Select I/O interface input clock 0 1 Baud rate generater 0 (Note 1) SCLK0 pin input
Edge selection in SCLK0 pin input mode 0 1 Transmits and receives data at rise edge of SCLK0 Transmits and receives data at fall edge of SCLK0 Cleared to Zero when read. (Note 2)
Framing error flag Parity error flag Overrun error flag Enable parity addition 0 1 0 1 Disable Enable Odd parity Even parity
Addition/check of even parity
Receving data bit8 8-bit UART mode (parity) 9-bit UART mode Stores received parity bit Stores received data bit8
Note 1: Note 2:
To use baud rate generator, set TRUN to “1”, putting the prescaler in RUN mode. As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Figure 3.9.3 Serial Channel 0 Related Register (2/7)
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Baud Rate Generator 0 Control Register 7
BR0CR (0053H) Bit symbol Read/Write After reset Function − R/W 0 (Note) Always write “0”. 0 00: φT0 01: φT2 10: φT8 11: φT32 0 0
6
5
BR0CK1
4
BR0CK0
3
BR0S3 R/W
2
BR0S2 0
1
BR0S1 0
0
BR0S0 0
Setting of the divided frequency
Setting of the divided frequency of baud rate generator 0 0000 16 divisions 0001 to 1111 1 division (Not divided) to 15 divisions (Note 2)
Selecting the input clock of baud rate generator 00 Internal clock φT0 01 10 11 Internal clock φT2 Internal clock φT8 Internal clock φT32
Note 1: Note 2: Note 3: Note 4:
To use baud rate generator, set TRUN to “1”, putting the prescaler in RUN mode. “1 division” of baud rate generator can be used only UART mode. Do not set it in I/O interface mode. Bit6 of BR0CR is read as “1”. Don’t read from or write to BR0CR register during sending or receiving.
Serial Channel 0 Buffer Register 7
SC0BUF (0050H) Bit symbol Read/Write After reset RB7 TB7
6
RB6 TB6
5
RB5 TB5
4
RB4 TB4
3
RB3 TB3
2
RB2 TB2
1
RB1 TB1
0
RB0 TB0
R (Receiving)/W (Transmission) Undefined
Note: Read-modify-write instruction is prohibited for SC0BUF.
Figure 3.9.4 Serial Channel 0 Related Registers (3/7)
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Serial Channel 1 Mode Control Register 7
SC1MOD (0056H) Bit symbol Read/Write After reset Function Undefined Transfer data bit8 0 Hand shake 0: CTS1 disable 1: CTS1 enable 0 Receiving function 0: Receive disable 1: Receive enable 0 Wake up function 0: Disable 1: Enable TB8
6
CTSE1
5
RXE
4
WU R/W
3
SM1 0
2
SM0 0
1
SC1 0
0
SC0 0
Serial transmission mode 00: I/O interface mode 01: 7-bit UART 10: 8-bit UART 11: 9-bit UART
Serial transmission clock (UART) 00: TO2 trigger 01: Baud rate generator 1 10: Internal clock φ1 11: External clock (SCLK1 input)
Serial transmission clock (for UART) 00 Timer 2 match detect signal 01 10 11 Baud rate generator 1 Internal clock φ1 (fSYS) External clock (SCLK1 input)
Serial transmission mode 00 I/O interface mode 01 10 11 UART 7-bit length 8-bit length 9-bit length
Wake up function (Don’t care in the modes other than 9-bit UART) 0 Disable 1 Enable Receiving control 0 Receive disable 1 0 1 Receive enable Disable (always transferable) Enable Stores transmission parity bit Stores transmission data bit8 Hand shake function ( CTS1 pin) enable
Transmission data bit8 8-bit UART mode (parity) 9-bit UART mode
Figure 3.9.5 Serial Channel 1 Related Register (4/7)
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Serial Channel 1 Control Register 7
SC1CR (0055H) Bit symbol Read/Write After reset Function RB8 R Undefined Received data bit8 0 Parity 0: Odd 1: Even
6
EVEN R/W
5
PE 0 Parity addition 0: Disable 1: Enable
4
OERR 0 Overrun
3
PERR 0 1: Error Parity
2
FERR 0 Framing
1
SCLKS R/W 0 0: SCLK1 1: SCLK1
0
IOC 0 0: Baud rate
generator 1
R (Cleared to zero when read.)
1: SCLK1 pin input
Select I/O interface input clock 0 1 Baud rate generator 1 (Note 1) SCLK1 pin input
Edge selection in SCLK1 pin input mode 0 1 Transmits and receives data at rise edge of SCLK1 Transmits and receives data at fall edge of SCLK1 Cleared to Zero when read (Note 2)
Framing error flag Parity error flag Overrun error flag Enable parity addition 0 1 0 1 Disable Enable Odd parity Even parity
Addition/check of even parity
Receiving data bit8 8-bit UART mode (parity) 9-bit UART mode Stores transmission parity bit Stores transmission data bit8
Note 1: Note 2:
To use baud rate generator, set TRUN to “1”, putting the prescaler in RUN mode. As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction.
Figure 3.9.6 Serial Channel 1 Related Register (5/7)
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Baud Rate Generator 1 Control Register 7
BR1CR (0057H) Bit symbol Read/Write After reset Function − R/W 0 (Note) Always write “0”. 0 00: φT0 01: φT2 10: φT8 11: φT32 0 0
6
5
BR1CK1
4
BR1CK0
3
BR1S3 R/W
2
BR1S2 0
1
BR1S1 0
0
BR1S0 0
Setting of the Divided frequency
Setting of the divided frequency of baud rate generator 1 0000 16 divisions 0001 to 1111 1 division (Not divided) to 15 divisions (Note 2)
Selecting the input clock of baud rate generator 00 Internal clock φT0 01 10 11 Internal clock φT2 Internal clock φT8 Internal clock φT32
Note 1: Note 2: Note 3: Note 4:
To use baud rate generator, set TRUNto “1”, putting the prescaler in RUN mode. “1 division” of baud rate generator can be used only UART mode. Do not set it in I/O interface mode. Bit6 of BR1CR is read as “1”. Don’t read from or write to BR1CR register during sending or receiving.
Serial Channel 1 Buffer Register 7
SC1BUF (0054H) Bit symbol Read/Write After reset RB7 TB7
6
RB6 TB6
5
RB5 TB5
4
RB4 TB4
3
RB3 TB3
2
RB2 TB2
1
RB1 TB1
0
RB0 TB0
R (Receiving)/W (Transmission) Undefined
Note: Read-modify-write instruction is prohibited for SC1BUF.
Figure 3.9.7 Serial Channel 1 Related Registers (6/7)
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Port 6 Function Register 7
P6FC (0016H) Bit symbol Read/Write After reset Function
6
5
P65F W 0 0: Port 1: SCLK1
4
3
P63F W 0 0: Port 1: TXD1
2
P62F 0 0: Port 1: SCLK0
1
0
P60F W 0 0: Port 1: TXD0
Setting TXD0 output of P60 0 1 0 1 0 1 0 1 Note: Read-modify-write instruction is prohibited for P6FC. Port TXD0 output (Channel 0) Port SCLK0 output (Channel 0) Port TXD1 output (Channel 1) Port SCLK1 output (Channel 1)
Setting SCLK0 output of P62
Setting TXD1 output of P63
Setting SCLK1 output of P65
Open Drain Enable Register 7
ODE (0058H) Bit symbol Read/Write After reset Function 0 0 P63 0: CMOS 1: Open drain Always write “0”. (This bit is read as “0”.)
6
5
4
3
−
2
− R/W
1
ODE63 0 P60
0
ODE60 0 0: CMOS 1: Open drain
Setting P60 as open-drain output 0 1 0 1 Note: Bit7 to 4 of ODE are read as “1”. CMOS output Open-drain output CMOS output Open-drain output
Setting P63 as open-drain output
Figure 3.9.8 Serial Channel Related Registers (7/7)
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TMP93CS32 3.9.2 Configuration
Figure 3.9.9 shows the block diagram of the serial channel 0.
Serial clock generation circuit BR0CR φT0 φT2 φT8 φT32 Prescaler Selector Selector External clock TO2TRG
(Timer 2 comparator output)
UART mode Selector
SIOCLK
Baud rate generator System clock fSYS (φ1) ÷2 SCLK0 (Shared with P62)
SC0MOD SC0MOD Selector
I/O interface mode
SC0CR SCLK0 (Shared with P62) Receive counter (UART only ÷16) RXDCLK SC0MOD Receive control SC0CR RXD0 (Shared by P61) Receive buffer1(Shift register) Parity control SC0MOD INTRX0 INTTX0 Transmission counter (UART only ÷16) TXDCLK Transmission control
CTS0
Serial channel interrupt control
(Shared with P62) SC0MOD
RB8
Receive buffer2 (SC0BUF)
Error flag
TB8
Transmission buffer (SC0BUF)
SC0CR Internal data bus
TXD0 (Shared with P60)
Figure 3.9.9 Block Diagram of the Serial Channel 0
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Figure 3.9.10 shows the block diagram of the serial channel 1.
Serial clock generation circuit BR1CR External clock TO2TRG Prescaler φT0 Selector φT2 φT8 φT32
(Timer 2 comparator output)
Selector
UART mode Selector
SIOCLK
Baud rate generator System clock fSYS (φ1) ÷2 SCLK1 input (Shared with P65)
SC1MOD SC1MOD Selector
I/O interface mode
SC1CR SCLK1 Output (Shared with P65) INTRX1 Receive counter (UART only ÷16) RXDCLK SC1MOD Receive control SC1CR RXD1 (Shared with P64) Receive buffer1(Shift register) Parity control SC1MOD INTTX1 Transmission counter (UART only ÷16) TXDCLK Transmission control
CTS1
Serial channel interrupt control
(Shared with P65) SC1MOD
RB8
Receive buffer2 (SC1BUF)
Error flag
TB8
Transmission buffer (SC1BUF)
SC1CR Internal data bus
TXD1 (Shared with P63)
Figure 3.9.10 Block Diagram of the Serial Channel 1
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Serial channel 0 and 1 can be used independently. All serial channels operate in the same manner, and thus only operation of serial channel 0 will be explained below. 1. Prescaler There are 9-bit prescaler and prescaler clock selection registers to generate input clock for 8-bit timers 0, 1, 2, 3 and 16-bits timers 4, 5 and Serial interface 0, 1. Figure 3.9.11 shows the block diagram. Table 3.9.1 shows prescaler clock resolution into the baud rate generator.
To CPU System clock (fSYS) 9-bit Prescaler fFPH 2 4 8 16 32 64 128 256 512
÷2
Selector
÷4
φT1 φT4 φT16 φT256 φT1 φT4 φT16 φ1 φT0 φT2 φT8 φT32
To 8-bit timers 0, 1, 2, and 3
SYSCR0 Run/Stop & clear TRUN Selector
To 16-bit timers 4 and 5
To serial interfaces 0 and 1
÷2
fc
fc/2
fc/4
fc/8 fc/16
X1
÷2 ÷4 ÷8 ÷16
SYSCR1
Figure 3.9.11 The Block Diagram of Prescaler Table 3.9.1 Prescaler Clock Resolution to Baud Rate Generator at fc = 20 MHz Select Prescaler Gear value Clock
000 (fc) 00 (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 10 (fc/16 clock) XXX fc/2
2
Prescaler Output Clock Resolution φT0
(0.2 µs) (0.4 µs) (0.8 µs) (1.6 µs) (3.2 µs) − fc/2
4
φT2
(0.8 µs) (1.6 µs) (3.2 µs) (6.4 µs) (12.8 µs) (12.8 µs) fc/2
6
φT8
(3.2 µs) (6.4 µs) (12.8 µs) (25.6 µs) (51.2 µs) (51.2 µs) fc/2
8
φT32
(12.8 µs) (25.6 µs) (51.2 µs) (102.4 µs) (204.8 µs) (204.8 µs) fc/29 fc/210 fc/211 fc/212 fc/2
12
fc/23 fc/24 fc/25 fc/2
6
fc/25 fc/26 fc/27 fc/2 fc/2
8
fc/27 fc/28 fc/29 fc/2 fc/2
10
8
10
XXX: Don’t care −: Can not use
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2004-02-10
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The clock selected among fFPH clock and fc/16 clock is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0 Resetting sets to “00” and selects the fFPH clock input divided by 4. Baud rate generator selects between 4 clock inputs φT0, φT2, φT8, and φT32 among the prescaler outputs. The prescaler can be run or stopped by the timer operation control register TRUN. Counting starts when is set to “1”, while the prescaler is cleared to zero and stops operation when is cleared to “0”. When the IDLE1 mode (operates only oscillator) is used, clear TRUN to “0” to reduce the power consumption of this prescaler before “HALT” instruction is executed. 2. Baud rate generator Baud rate generator comprises a circuit that generates transmission and receiving clocks to determine the transfer rate of the serial channel. The input clock to the baud rate generator, φT0, φT2, φT8, or φT32 is generated by the 9-bit prescaler which is shared by the timers. One of these input clocks is selected by the baud rate generator control register BR0CR. The baud rate generator includes a 4-bit frequency divider, which divides frequency by 1 to 16 values to determine the transfer rate. How to calculate a transfer rate when the baud rate generator is used is explained below. • UART mode Baud rate • = Input clock of baud rate generator Frequency divisor of baud rate generator ÷ 16
I/O interface mode Baud rate =
Input clock of baud rate generator ÷2 Frequency divisor of baud rate generator Accordingly, when source clock fc is 12.288 MHz, input clock is φT2 (fc/16), and frequency divisor is 5, the transfer rate in UART mode becomes as follows:
* Clock condition Clock gear: 1 (fc) Prescaler clock: fFPH
Baud rate
= =
fc/16 ÷ 16 5 6 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps) 12.288 × 10
The maximum baud rate of this baud rate generator is 307.2 kbps. Table 3.9.2 shows an example of the transfer rate in UART mode. Also with 8-bit timer 2, the serial channel can get a transfer rate. Table 3.9.3 shows an example of baud rate using timer 2.
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Table 3.9.2 Selection of UART Transfer Rate (1) (when baud rate generator is used) Unit (kbps) fc [MHz]
9.830400 ↑ ↑ ↑ ↑ 12.288000 ↑ 14.745600 ↑ ↑ ↑ 17.2032 ↑ 19.6608 ↑ ↑ ↑
Input clock
Frequency divisor
φT0 (4/fc)
153.600 76.800 38.400 19.200 9.600 38.400 19.200 230.400 76.800 38.400 19.200 38.400 19.200 153.600 76.800 38.400 19.200
φT2 (16/fc)
38.400 19.200 9.600 4.800 2.400 9.600 4.800 57.600 19.200 9.600 4.800 9.600 4.800 38.400 19.200 9.600 4.800
φT8 (64/fc)
9.600 4.800 2.400 1.200 0.600 2.400 1.200 14.400 4.800 2.400 1.200 2.400 1.200 9.600 4.800 2.400 1.200
φT32 (256/fc)
2.400 1.200 0.600 0.300 0.150 0.600 0.300 3.600 1.200 0.600 0.300 0.600 0.300 2.400 1.200 0.600 0.300
1 2 4 8 16 5 10 1 3 6 12 7 14 2 4 8 16
Note 1: Transfer rate in I/O interface mode is 8 times faster than the values given in the above table. Note 2: This table is calculated when fc/1 is selected as a clock gear, and the system clock as a prescaler clock. Table 3.9.3 Selection of UART Transfer Rate (2) (when timer 2 (input clock φT1) is used) Unit (kbps)
fc TREG2
1H 2H 3H 4H 5H 8H AH 10H 14H
19.6608 MHz
153.6 76.8 51.2 38.4 30.72 19.2 15.36 9.60 7.68
14.7456 MHz
115.2 57.6 38.4 28.8 23.04 14.4 11.52 7.20 5.76
12.288 MHz
96 48 32 24 19.2 12 9.6 6 4.8
12 MHz
9.8304 MHz
76.8 38.4
8 MHz
62.5 31.25
6.144 MHz
48 24 16 12 9.6 6 4.8 3 2.4
31.25 19.2 9.6 4.8
How to calculate the transfer rate (when timer 2 is used): The clock frequency selected by the register SYSCR0 Transfer rate = TREG2 × 8 × 16
(When Timer 2 (input clock φT1) is used.)
Note 1: Timer 2 match detect signal cannot be used as the transfer clock in I/O interface mode. Note 2: This table is calculated when fc/1 is selected as a clock gear, and fFPH as a prescaler clock.
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3. Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • I/O interface mode When in SCLK output mode with the setting of SC0CR = “0”, the basic clock will be generated by dividing by 2 the output of the baud rate generator described before. When in SCLK input mode with the setting of SC0CR = “1”, the rising edge or falling edge will be detected according to the setting of SC0CR register to generate the basic clock. • UART mode According to the setting of SC0MOD, the above baud rate generator clock, internal clock φ1 (Max 625 kbps at fc = 20 MHz), the match detect signal from timer 2, or external clock SCLK0 will be selected to generate the basic clock SIOCLK. 4. Receiving counter The receiving counter is a 4-bit binary counter used in UART mode and counts up by SIOCLK clock. 16 pulses of SIOCLK are used for receiving 1 bit of data, and the data bit is sampled three times at 7th, 8th, and 9th clock. With the three samples, the received data is evaluated by the rule of majority. For example, if the sampled data bit is “1”, “0”, and “1” at 7th, 8th, and 9th clock respectively, the received data is evaluated as “1”. The sampled data “0”, “0”, and “1” is evaluated that the received data is “0”. 5. Receiving control • I/O interface mode When in SCLK0 output mode with the setting of SC0CR = “0”, RXD0 signal will be sampled at the rising edge of shift clock which is output to SCLK0 pin. When in SCLK0 input mode with the setting SC0CR = “1” RXD0 signal will be sampled at the rising edge or falling edge of SCLK0 input according to the setting of SC0CR register. • UART mode The receiving control has a circuit for detecting the start bit by the rule of majority. When two or more “0” are detected during 3 samples, it is recognized as start bit and the receiving operation is started. Data being received are also evaluated by the rule of majority.
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6. Receiving buffer To prevent overrun error, the receiving buffer has a double buffer structure. Received data are stored one bit by one bit in the receiving buffer 1 (shift register type). When 7 bits or 8 bits of data is stored in the receiving buffer 1, the stored data are transferred to the receiving buffer 2 (SC0BUF), generating an interrupt INTRX0. The CPU reads only receiving buffer 2 (SC0BUF). Even before the CPU reads the receiving buffer 2 (SC0BUF), the received data can be stored in the receiving buffer 1. However, unless the receiving buffer 2 (SC0BUF) is read before all bits of the next data are received by the receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of the receiving buffer 1 will be lost, although the contents of the receiving buffer 2 and SC0CR is still preserved. The parity bit added in 8-bit UART mode and the most significant bit (MSB) in 9-bit UART mode are stored in SC0CR. When in 9-bit UART mode, the wake-up function of the slave controllers is enabled by setting SC0MOD to “1”, and interrupt INTRX0 occurs only when SC0CR is set to “1”. 7. Transmission counter Transmission counter is a 4-bit binary counter which is used in UART mode, counts by SIOCLK clock, and generating TXDCLK every 16 clock pulses.
SIOCLK 15 TXDCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
Figure 3.9.12 Generation of Transmission Clock 8. Transmission controller • I/O interface mode In SCLK0 output mode with the setting of SC0CR = “0”, the data in the transmission buffer are output bit by bit to TXD0 pin at the rising edge of shift clock which is output from SCLK0 pin. In SCLK0 input mode with the setting of SC0CR = “1”, the data in the transmission buffer are output bit by bit to TXD0 pin at the rising edge or falling edge of SCLK0 input according to the setting of SC0CR register. • UART mode When transmission data are written in the transmission buffer sent from the CPU, transmission starts at the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT.
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Handshake Function The serial channels use the CTS0 pin to transmit data in units of frames, thus preventing an overrun error. Use SC0MOD to enable or disable the handshake function. When CTS0 goes high, data transmission is halted after the completion of the current transmission and is not restarted until CTS0 returns to low. An INTTX0 interrupt is generated to request the CPU for the next data to transmit. When the CPU write the data to the transmit buffer, processing enters standby mode. An RTS pin is not provided, but a handshake function can easily be configured if the receiver sets any port assigned to the RTS function to high (in the receive interrupt routine) after data receive, and requests the transmitter to temporarily halt transmission.
TMP93CS32 TMP93CS32
TXD
CTS
RXD
RTS (any port)
Sender
Receiver
Figure 3.9.13 Handshake Function
Timing to write transmission buffer
CTS0
Send is suspended (1)from (1) to (2). (2) 13 14
15
16
1
2
3
14
15
16
1
2
3
SIOCLK TXDCLK TXD Start bit Bit0
Note 1:
If the CTS signal rises during transmission, the next data is not sent after the completion of the current transmission.
Note 2:
Transmission starts at the first TXDCLK clock fall after the CTS signal falls.
Figure 3.9.14 Timing of CTS (Clear to send)
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9. Transmission buffer Transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU from the least significant bit (LSB) in order. When all bits are shifted out, the transmission buffer becomes empty and generates INTTX0 interrupt. 10. Parity control circuit When serial channel control register SC0CRis set to “1”, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART or 8-bit UART mode. With SC0CR register, even (odd) parity can be selected. For transmission, parity is automatically generated according to the data written in the transmission buffer SC0BUF, and data are transmitted after being stored in SC0BUF when in 7-bit UART mode while in SC0MOD when in 8-bit UART mode. and must be set before transmission data are written in the transmission buffer. For receiving, data are shifted in the receiving buffer 1, and parity is added after the data are transferred in the receiving buffer 2 (SC0BUF), and then compared with SC0BUF when in 7-bit UART mode and with SC0MOD when in 8-bit UART mode. If they are not equal, a parity error occurs, and SC0CR flag is set. 11. Error flag Three error flags are provided to increase the reliability of receiving data. • Overrun error If all bits of the next data are received in receiving buffer 1 while valid data are stored in receiving buffer 2 (SC0BUF), an overrun error will occur. • Parity error The parity generated for the data shifted in receiving buffer 2 (SC0BUF) is compared with the parity bit received from RXD pin. If they are not equal, a parity error occurs. • Framing error The stop bit of received data is sampled three times around the center. If the majority is “0”, a framing error occurs.
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12. Signal generation timing 1) In I/O Interface mode
SCLK0 output mode SCLK0 input mode SCLK0 output mode SCLK0 input mode Immediately after rise of last SCLK0 signal (See Figure 3.9.17.) Immediately after rise (Rising mode) or fall (Falling mode) of last SCLK0 signal (See Figure 3.9.18.) Immediately after final SCLK0 (When received data are transferred to receive buffer 2 (SC0BUF))(See Figure 3.9.19.) Immediately after final SCLK0 (When received data are transferred to receive buffer 2 (SC0BUF))(See Figure 3.9.20.)
Timing for send interrupt generation Timing for receive interrupt generation
2)
In UART mode
Mode
Receive 9-Bit
Center of last bit (Bit8) Center of stop bit − Center of last bit (Bit8)
8-Bit + Parity
Center of last bit(parity bit) Center of stop bit Center of last bit (parity bit) Center of last bit (parity bit)
8-Bit, 7-Bit + Parity, 7-Bit Center of stop bit Center of stop bit Center of stop bit Center of stop bit
Timing for interrupt generation Timing for framing error generation Timing for parity error generation Timing for overrun error generation
Note:
In 9-Bit and 8-Bit + Parity mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error.
Mode
Send 9-Bit
Immediately before stop bit sent
8-Bit + Parity
←
8-Bit, 7-Bit + Parity, 7-Bit ←
Timing for interrupt generation
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2004-02-10
TMP93CS32 3.9.3 Operational description
(1) Mode 0 (I/O interface mode) This mode is used to increase the number of I/O pins of for transmitting or receiving data to or from the external shifter register. This mode includes SCLK output mode to output synchronous clock SCLK0 and SCLK input mode to input external synchronous clock SCLK0.
Output extension TMP93CS32 Shift register A TXD SCLK Port SI SCK RCK B C D E F G H RXD SCLK Port QH CLOCK S/ L Input extension TMP93CS32 Shift register A B C D E F G H
TC74HC595 or the like
TC74HC165 or the like
Figure 3.9.15 Example of SCLK Output Mode Connection
Output extension TMP93CS32 Shift register A TXD SCLK Port SI SCK RCK B C D E F G H RXD SCLK Port QH CLOCK S/ L Input port extension TMP93CS32 Shift register A B C D E F G H
TC74HC595 or the like External clock
TC74HC165 or the like External clock
Figure 3.9.16 Example of SCLK Input Mode Connection
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1. Transmission In SCLK output mode, 8-bit data and synchronous clock are output from TXD0 pin and SCLK0 pin, respectively, each time the CPU writes data in the transmission buffer. When all data is output, INTES0 will be set to generate INTTX0 interrupt.
Timing to write transmission data SCLK0 output
TXD0
Bit0
Bit1
Bit6
Bit7
TXDSFT ITX0C (INTTX0 interrupt request)
Figure 3.9.17 Transmitting Operation in I/O Interface Mode (SCLK0 output mode) In SCLK output mode, 8-bit data are output from TXD0 pin when SCLK0 input becomes active while data are written in the transmission buffer by CPU. When all data are output, INTES0 will be set to generate INTTX0 interrupt.
SCLK0 input (SCLKS = 0: Rising edge mode) SCLK0 input (SCLKS = 1: Falling edge mode)
TXD0
Bit0
Bit1
Bit5
Bit6
Bit7
TXDSFT ITX0C (INTTX0 interrupt request)
Figure 3.9.18 Transmitting Operation in I/O Interface Mode (SCLK0 input mode)
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2. Receiving In SCLK output mode, synchronous clock is outputted from SCLK0 pin and the data are shifted in the receiving buffer 1 whenever the receive interrupt flag INTES0 is cleared by reading the received data. When 8-bit data are received, the data will be transferred in the receiving buffer 2 (SC0BUF) at the timing shown below, and INTES0 will be set again to generate INTRX0 interrupt.
IRX0C
SCLK0
RXD0 Timing to shift data in the receiving buffer 2
Bit0
Bit1
Bit2
Bit6
Bit7 Generate INTRX0
Figure 3.9.19 Receiving Operation in I/O Interface Mode (SCLK0 Output Mode) In SCLK input mode, the data is shifted in the receiving buffer 1 when SCLK input becomes active while the receive interrupt flag INTES0 is cleared by reading the received data. When 8-bit data is received, the data will be shifted in the receiving buffer 2 (SC0BUF) at the timing shown below, and INTES0 will be set again to generate INTRX0 interrupt.
SCLK0 input (SCLKS = 0: Rising edge mode) SCLK0 input (SCLKS = 1: Falling edge mode)
RXD0 Timing to shift data in the receiving buffer 2
Bit0
Bit1
Bit2
Bit6
Bit7 Generate INTRX0
Figure 3.9.20 Receiving Operation in I/O Interface Mode (SCLK0 Input Mode) Note: For data receiving, the system must be placed in the receive enable state (SC0MOD = “1”).
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(2) Mode 1 (7-bit UART mode) 7-bit mode can be set by setting serial channel mode register SC0MOD to “01”. In this mode, a parity bit can be added, and the addition of a parity bit can be enabled or disabled by serial channel control register SC0CR, and even parity or odd parity is selected by SC0CR when is set to “1” (enable).
Setting example: When transmitting data with the following format, the control registers should be set as described below. Start Bit0 1 2 3 4 5 6
Even parity
Stop
Direction of transmission (transmission rate: 2400 bps at fc = 12.288 MHz) * Clock condition Clock gear: 1 (fc) Prescaler clock: fFPH 2 − − 1 X 1 − − * 1 − X 0 0 0 − − * 0 1 1 1 0 1 − − * Select P60 as the TXD pin. Set 7-bit UART mode. Add an even parity. Set transfer rate at 2400 bps. Start the prescaler for the baud rate generator. Enable INTTX0 interrupt and set interrupt level 4. Set data for transmission.
7 P6CR P6FC SC0MOD SC0CR BR0CR TRUN INTES0 SC0BUF ← ← ← ← ← ← ← X X X 0 1 1 *
6 X 0 1 X X 1 *
5 − − 1 1 − 0 *
4 − X X X 0 − 0 *
3 − − 0 X 0 − − *
←X X −
X: Don’t care, −: No change
(3) Mode 2 (8-bit UART mode) 8-bit UART mode can be specified by setting SC0MOD to “10”. In this mode, parity bit can be added, the addition of a parity bit is enabled or disabled by SC0CR, and even parity or odd parity is selected by SC0CR when is set to “1” (Enable).
Setting example: When receiving data with the following format, the control register should be set as described below. Start Bit0 1 2 3 4 5 6 7
Odd parity
Stop
Direction of transmission (transmission rate: 9600 bps at fc = 12.288 MHz)
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* Clock condition Main setting 7 P6CR SC0MOD SC0CR BR0CR TRUN INTES0 ← ← ← ← ← ← X − X 0 1 − 6 X 0 0 X X − 5 − 1 1 0 − − 4 − X X 1 − − 3 − 1 X 0 − 1 2 − 0 X 1 − 1 1 0 0 0 0 − 0 0 − 1 0 1 − 0
Clock gear: 1 (fc) Prescaler clock: fFPH
Select P61 (RXD) as the input pin. Enable receiving in 8-bit UART mode. Add an odd parity. Set transfer rate at 9600 bps. Start the prescaler for the baud rate generator. Enable INTRX0 interrupt and set interrupt level 4.
Interrupt processing Acc ← SC0CR AND 00011100 if Acc ≠ 0 then ERROR Acc ← SC0BUF X: Don’t care, −: No change Check for error. Read the received data.
(4) Mode 3 (9-bit UART mode) 9-bit UART mode can be specified by setting SC0MOD to “11”. In this mode, parity bit cannot be added. For transmission, the MSB (9th bit) is written in SC0MOD, while in receiving it is stored in SC0CR. For writing and reading the buffer, the MSB is read or written first then SC0BUF. Wake-up function In 9-bit UART mode, the wake-up function of slave controllers is enabled by setting SC0MOD to “1”. The interrupt INTRX0 occurs only when = 1.
TXD
RXD
TXD
RXD
TXD
RXD
TXD
RXD
Master
Slave 1
Slave 2
Slave 3
Note: TXD pin of the slave controllers must be in open-drain output mode.
Figure 3.9.21 Serial Link Using Wake-up Function
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Protocol 1. 2. 3. Select the 9-bit UART mode for the master and slave controllers. Set SC0MOD bit of each slave controller to “1” to enable data receiving. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (bit8) is set to “1”.
Start Bit0 1 2 3 4 5 6 7 8 “1” Stop
Select code of slave controller
4. 5.
Each slave controller receives the above frame, and clears WU bit to “0” if the above select code matches its own select code. The master controller transmits data to the specified slave controller whose SC0MOD bit is cleared to “0”. The MSB (bit8) is cleared to “0”.
Start Bit0 1 2 3 Data 4 5 6 7 Bit8 “0” Stop
6.
The other slave controllers (with the bit remaining at “1”) ignore the receiving data because their MSBs (Bit8 or ) are set to “0” to disable the interrupt INTRX0. The slave controllers ( = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission.
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Setting example: To link two slave controllers serially with the master controller, and use the internal clock φ1 as the transfer clock.
TXD
RXD
TXD
RXD
TXD
RXD
Master
Slave 1
Slave 2
Select code 00000001
Select code 00001010
Since serial channels 0 and 1 operate in exactly the same way, channel 0 is used for the purposes of explanation. •
Main P6CR P6FC INTES0 SC0MOD SC0BUF ←X X − − − − 0 1 ←X X − X − ←1 1 0 0 1 ←1 ←0 010 000 1 0 0X1 101 11 00 0 1 Select P60 as TXD0 pin and P61 as RXD0 pin. Enable INTTX0 and set the interrupt level 4. Enable INTRX0 and set the interrupt level 5. Set φ1 as the transmission clock in 9-bit UART mode. Set the select code for slave controller 1.
Setting the master controller
INTTX0 interrupt SC0MOD SC0BUF ←0 ←* − * − * − * − * − * − * − * Sets TB8 to“0”. Set data for transmission.
•
Main P6CR P6FC ODE INTES0 SC0MOD
Setting the slave controller 1
←X X − ←X X −
−
−
−
0
1 1 0 0
X−
0X1
←X X X X X X − ←1 1 0 1 1 1 1 ←0 0 1 1 1 1 1
Select P61 as RXD0 pin and P60 as TXD0 pin (open-drain output). Enable INTRX0 and INTTX0. Set to “1” in the 9-bit UART transmission mode with transfer clock φ1.
INTRX0 interrupt Acc ← SC0BUF if Acc = Select code Then ←− − − 0 SC0MOD
−
−
−
−
Clear to “0”.
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3.10 Analog/Digital Converter
TMP93CS32 incorporate a high-speed, high-precision 10-bit analog/digital converter (AD converter) with 6-channel analog input. Figure 3.10.1 is a block diagram of the AD converter. The 6-channel analog input pins (AN0 to AN5) are also used as input-only port P5 and can be also used as input ports.
Internal data bus
ADMOD1
ADMOD0
scan Decoder repeat interrupt busy end start Channel select AD converter control circuit INTAD Interrupt ADTRG
Analog Input AN5 (P55) AN4 (P54) AN3/ ADTRG (P53) AN2 (P52) AN1 (P51) AN0 (P50) Mutiplexer Sample hold AD conversion result register ADREG04L to 3L ADREG04H to 3H
VREFH VREFL
DA converter
Figure 3.10.1 Block Diagram of AD Converter Note 1: When the power supply current is reduced in IDLE2, IDLE1, STOP mode, there is possible to set a standby enabling the internal comparator due to a timing. Stop operation of AD converter before execution of “HALT” instruction. Note 2: In regard to the lowest operation frequency. The operation of AD converter is guaranteed with clock of fFPH ≥ 4 MHz.
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TMP93CS32 3.10.1 Analog/Digital Converter Registers
AD converter is controlled by two AD mode control registers (ADMOD0 and ADMOD1). AD conversion result is stored in eight AD conversion result registers (ADREG04H/L, ADREG15H/L, ADREG2H/L, ADREG3H/L). AD Mode Control Register 0 7
ADMOD0 (005EH) Bit symbol Read/Write After reset Function 0 AD conversion end flag 0: Conversion in progress 1: Conversion end EOCF R 0 AD conversion busy flag 0: Conversion is idle. 1: Conversion in progress 0 (Note) Always write “0”. 0 (Note) Always write “0”. 0
6
ADBF
5
−
4
−
3
ITM0 R/W
2
REPET 0
1
SCAN 0
Scan mode specification 0: Fixedchannel mode 1: Channel scan mode
0
ADS 0
AD conversion start 0: Don’t care 1: Start conversion (Note)
Specifies Repeat mode interrupts for specification fixed channel 0: Single /repeatconverconversion sion mode mode. 1: Repeat 0: Every converconversion sion mode 1: Every four conversions
AD conversion start 0 1 Don’t care Start AD conversion
Note: Always read as “0”. AD scan mode specification 0 1 0 1 AD conversion fixed-channel mode AD conversion channel scan mode AD single conversion mode AD repeat conversion mode
AD repeat mode specification
AD conversion interrupt specification for fixedchannel/repeat-conversion mode Fixed channel/repeat conversion mode = “0”, = “1” 0 1 0 1 0 1
Generates interrupt every conversion. Generates interrupt every four conversions.
AD conversion busy flag AD conversion is idle. AD conversion in progress AD conversion in progress AD conversion end
AD conversion end flag
Figure 3.10.2 Register for AD Converter (1/4)
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AD Mode Control Register 1 7
ADMOD1 (005FH) Bit symbol Read/Write After reset Function VREFON R/W 1 String resistance 0: Off 1: On 0
External trigger start control 0: Disable 1: Enable
6
5
4
3
ADTRGE
2
ADCH2 R/W 0
1
ADCH1 0
0
ADCH0 0
Analog input channel selection
Analog input channel selection 000 001 010 011 (Note) 100 101 110 111 0
(Channel fix)
1 (Channel scan) AN0 AN0 → AN1 AN0 → AN1 → AN2 AN0 → AN1 → AN2 → AN3 AN4 AN4 → AN5
AN0 AN1 AN2 AN3 AN4 AN5 Don’t care
Conversion start control by external trigger ( ADTRG pin input) 0 1 0 1 Disable Enable OFF ON
Analog reference voltage control
Note: Set the bit to “1” before starting conversion (write “1” to ADMOD0). Note: As the AN3 and the ADTRG are the same pin, = “011” can’t be set when is set to 1 and ADTRG is used.
Figure 3.10.3 Register for AD Converter (2/4)
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AD Conversion Result Register 0/4 Low 7
ADREG04L (0060H)
6
ADR00 R Undefined
5
4
3
2
1
0
ADR0RF R 0
Conversion result stored flag 1: Exist result
Bit symbol Read/Write After reset Function
ADR01
Stores lower 2 bits of AD conversion result.
AD Conversion Result Register 0/4 High 7
ADREG04H (0061H)
6
ADR08
5
ADR07
4
ADR06 R Undefined
3
ADR05
2
ADR04
1
ADR03
0
ADR02
Bit symbol Read/Write After reset Function
ADR09
Stores upper 8 bits of AD conversion result.
AD Conversion Result Register 1/5 Low 7
ADREG15L (0062H)
6
ADR10 R Undefined
5
4
3
2
1
0
ADR1RF R 0
Conversion result stored flag 1: Exist result
Bit symbol Read/Write After reset Function
ADR11
Stores lower 2 bits of AD conversion result.
AD Conversion Result Register 1/5 High 7
ADREG15H (0063H)
6
ADR18
5
ADR17
4
ADR16 R Undefined
3
ADR15
2
ADR14
1
ADR13
0
ADR12
Bit symbol Read/Write After reset Function
ADR19
Stores upper 8 bits of AD conversion result.
9 Channel x conversion result
8
7
6
5
4
3
2
1
0
ADREGxH 7 6
5
4
3
2
1
0
7
6
5
4
3
2
ADREGxL 1 0
• •
Bits 5 to 1 are always read as “1”. Bit0 is conversion result stored flag bit . is set to “1” when the AD conversion result is stored. Reading either the ADREGxH or the ADREGxL registers clears to “0”.
Figure 3.10.4 Registers for AD Converter (3/4)
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AD Conversion Result Register 2 Low 7
ADREG2L (0064H) Bit symbol Read/Write After reset Function ADR21 R Undefined Stores lower 2 bits of AD conversion result.
6
ADR20
5
4
3
2
1
0
ADR2RF R 0
Conversion result stored flag 1: Exist result
AD Conversion Result Register 2 High 7
ADREG2H Bit symbol (0065H) Read/Write After reset Function ADR29
6
ADR28
5
ADR27
4
ADR26 R Undefined
3
ADR25
2
ADR24
1
ADR23
0
ADR22
Stores upper 8 bits of AD conversion result.
AD Conversion Result Register 3 Low 7
ADREG3L (0066H) Bit symbol Read/Write After reset Function ADR31 R Undefined Stores lower 2 bits of AD conversion result.
6
ADR30
5
4
3
2
1
0
ADR3RF R 0
Conversion result stored flag 1: Exist result
AD Conversion Result Register 3 High 7
ADREG3H Bit symbol (0067H) Read/Write After reset Function ADR39
6
ADR38
5
ADR37
4
ADR36 R Undefined
3
ADR35
2
ADR34
1
ADR33
0
ADR32
Stores upper 8 bits of AD conversion result.
9 Channel x conversion result
8
7
6
5
4
3
2
1
0
ADREGxH 7 6
5
4
3
2
1
0
7
6
5
4
3
2
ADREGxL 1 0
• •
Bits 5 to 1 are always read as “1”. Bit0 is conversion result stored flag bit . is set to “1” when the AD conversion result is stored. Reading either the ADREGxH or the ADREGxL registers clears to “0”.
Figure 3.10.5 Registers for AD Converter (4/4)
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TMP93CS32 3.10.2 Operation
(1) Analog reference voltage High analog reference voltage is applied to the VREFH pin, and low analog reference voltage is applied to the VREFL pin. The voltage between VREFH and VREFL is divided into 1024 increments using a string resistor. AD conversion is based on comparing the analog input voltage with these reference voltage increments. To turn the switch between VREFH and VREFL off, program “0” to the ADMOD1 bit. To start AD conversion when the switch is off, first program “1” to . After that, wait at 3 µs long enough to get the stabilized oscillation, program “1” to ADMOD0. (2) Selecting analog input channels The procedure for selecting analog input channels depends on the operating mode of the AD converter. • When analog input channel is used to fix (ADMOD0 = “0”) To set ADMOD1, selecting one channel from analog input pins AN0 to AN5. • When analog input channel is used to scan (ADMOD0 = “1”) To set ADMOD1, selecting one channel from 6 scan mode. Table 3.10.1 shows the analog input channel selection each operating mode. A reset initializes AD mode control register ADMOD1 to “000”, selecting pin AN0 for the AD converter input. The pins not used as analog input channels can be used as general-purpose input ports (P5). Table 3.10.1 Analog Input Channel Selection
000 001 010 011 100 101 110 111
Fixed Channel = 0
AN0 AN1 AN2 AN3 AN4 AN5 Don’t care AN0
Channel Scan = 1
AN0 → AN1 AN0 → AN1 → AN2 AN0 → AN1 → AN2 → AN3 AN4 AN4 → AN5
(3) Starting AD conversion AD conversion starts when ADMOD0 to “1”, or ADMOD1 is set to “1” and the falling edge is input through ADTRG pin. When AD conversion starts, AD conversion busy flag ADMOD0 is set to “1”, indicating AD conversion is in progress. Writing “1” to while conversion is in progress restarts the conversion. Check the conversion result stored flag ADREGxL to determine whether the AD conversion data are valid at this time. Inputting the falling edge to the ADTRG pin while conversion is in progress is invalid.
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(4) AD conversion modes and completion interrupt Follow the four AD conversion modes are supported. • • • • Fixed channel single conversion mode Channel scan single conversion mode Fixed channel repeat conversion mode Channel scan repeat conversion mode
AD conversion mode can selected by setting AD mode control register ADMOD0. When AD conversion ends, AD conversion completion interrupt INTAD request occurs. And the ADMOD0 flag is set to “1” to indicate that AD conversion has completed. 1. Fixed channel single conversion mode Fixed channel single conversion ADMOD0 to “00”. mode can be specified by setting
In this mode, conversion of the specified single channel is executed once only. After conversion is completed, ADMOD0 is set to “1”, ADMOD0 is cleared to “0” and occurs INTAD interrupt request. 2. Channel scan single conversion mode Channel scan single conversion ADMOD0 to “01”. mode can be specified by setting
In this mode, conversion of the specified channel are executed once only. After conversion is completed, ADMOD0 is set to “1”, ADMOD0 is cleared to “0” and occurs INTAD interrupt request. 3. Fixed channel repeat conversion mode Fixed channel repeat conversion ADMOD0 to “10”. mode can be specified by setting
In this mode, conversion of the specified single channel is executed repeatedly. After conversion is completed, ADMOD0 is set to “1”, ADMOD0 remains “1”, not changed to “0”. The timing of INTAD interrupt request can selected by setting of ADMOD0. When is set to “0”, interrupt request occurs after every conversion. When is set to “1”, interrupt request occurs after every fourth conversion. 4. Channel scan repeat conversion mode Channel scan repeat conversion ADMOD0 to “11”. mode can be specified by setting
In this mode, specified channels are converted repeatedly. After every scan convert completion, ADMOD0 is set to “1” and INTAD interrupt request occurs. ADMOD0 remains “1”, not changed to “0”. To stop the repeat conversion mode (3. and 4. modes), program “0” to ADMOD0. After the current conversion is completed repeat conversion mode is terminated, and ADMOD0 is cleared to “0” . If the device enters the IDLE2, IDLE1 or STOP modes during AD conversion, the conversion halts immediately. After the HALT mode is released, AD conversion restarts from the beginning in repeat conversion mode (3. and 4. modes), it does not restart in single conversion mode (1. and 2. modes).
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Table 3.10.2shows the relations between AD conversion modes and interrupt request. Table 3.10.2 Relation between AD Conversion Modes and Interrupt Request Mode
Fixed channel single conversion mode Channel scan single conversion mode Fixed channel repeat conversion mode (Every conversion) Fixed channel repeat conversion mode (Every fourth conversion) Channel scan repeat conversion mode X: Don’t care
Interrupt Request Timing
After conversion After conversion After every conversion After every fourth conversion After every scan conversion
ADMOD0
X X 0 1 1 X 1 1 0
0 0
0 1
(5) AD conversion time 140 states (14 µs at fc = 20 MHz) are required for AD conversion of one channel. (6) Storing and reading the AD conversion result AD conversion results are stored in AD conversion result registers high/low (ADREG04H/L to ADREG3H/L). These registers are read only. In fixed channel repeat conversion mode, AD conversion results are stored in order from ADREG04H/L to ADREG3H/L. Except in this mode, AD conversion results for channel AN0 and AN4, AN1 and AN5, AN2, AN3 are stored severally ADREG04H/L, ADREG15H/L, ADREG2H/L, ADREG3H/L. Table 3.10.3 shows correspondence between analog input channels and AD conversion result registers. Table 3.10.3 Correspondence Between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Registers Analog Input Channel (port 5)
AN0 AN1 AN2 AN3 AN4 AN5
Conversion Modes Except Right
ADREG04H/L ADREG15H/L ADREG2H/L ADREG3H/L ADREG04H/L ADREG15H/L
Fixed Channel Repeat Conversion Mode (Every fourth conversion)
ADREG04H/L ADREG15H/L ADREG2H/L ADREG3H/L
AD conversion result registers bit0 is AD conversion result stored flag . The flag shows that whether those registers are read or not. When AD conversion results are stored in those registers (ADREGxH or ADREGxL), this flag is set to “1”. When each register is read, this flag is cleared to “0”, and AD conversion end flag ADMOD0 is also cleared to “0”.
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Setting example: 1. This example converts the analog input voltage at the AN3 pin. The INTAD interrupt routine writes the result to memory address 0800H.
Main routine setting: 76 INTE0AD ADMOD1 ADMOD0 ←1 1
5 0
4 0
3 −
2 − 0 0
1 − 1 0
0 − 1 1 Enables INTAD and sets level 4. Sets analog input channel to AN3. Starts AD conversion in fixed channel single conversion mode.
←1 X X X 0 ←X X 0 0 0
Example of interrupt routine processing: WA WA (0800H) ← ADREG3 >>6 ← WA Reads ADREG3L and ADREG3H values and writes them to WA (16 bits). Shifts right WA six times and zero-fills the upper bits. Writes contents of WA to memory address 0800H.
2.
This example repeatedly converts the analog input voltages at pins AN0 to AN2, using channel scan repeat conversion mode.
←1 0 0 0 − − − − 0 1 Disables INTAD. Sets AN0 to AN2 as analog input channels. Starts AD conversion in channel scan repeat conversion mode.
INTE0AD ADMOD1 ADMOD0
←1 X X X 0 ←X X 0 0 0
01 11
X: Don’t care −: No change
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3.11 Watchdog Timer (Runaway Detecting Timer), Warm-up Timer
TMP93CS32 contains a watchdog timer of Runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction. Connecting the watchdog timer output to the reset pin internally forces a reset. This watchdog timer consists of 7-stage and 15-stage binary counters. These binary counters are also used as a warm-up timer for the internal oscillator stabilization. This is used for releasing the STOP.
3.11.1
Configuration
Figure 3.11.1 shows the block diagram of the watchdog timer (WDT).
RESET
Internal reset
WDMOD
WDTI interrupt Enable Interrupt control QS R WDMOD Reset WDMOD Write disable code to WDCR (B1H)
WDMOD T45CR Selector Selector
Selector 27 29
Selector 211 213 215
Selector
7-stage binary counter
15-stage binary counter Reset
Reset Write clear code to WDCR (4EH)
÷2 CPU ÷2 Selector
HALT instruction (STOP, IDLE1 mode)
fc
fc/2
fc/4
fc/8 fc/16
X1
÷2 ÷4 ÷8 ÷16
SYSCR1
Figure 3.11.1 Block Diagram of Watchdog Timer/Warm-up Timer
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The watchdog timer consists of 7-stage and 15-stage binary counters which use System clock (fSYS) as the input clock. The 15-stage binary counter has fSYS/215, fSYS/217, fSYS/219, and fSYS/221 output. Selecting one of the outputs with the WDMOD register generates a watchdog interrupt when an overflow occurs. The binary counter for the watchdog timer should be cleared to “0” with runaway detecting result software (instruction) before an interrupt occurs.
Example: LDW LD SET (WDMOD), B100H (WDCR), 4EH 7, (WDMOD) ; ; ; Disable. Write clear code. Enable again.
The runaway detecting result can also be connected to the reset pin internally. In this case, the watchdog timer resets itself.
WDT counter WDT interrupt WDT clear (Soft ware) Write clear code n Overflow 0
Figure 3.11.2 Normal Mode
Overflow WDT counter WDT interrupt Internal reset 8 to 20 states (12.8 to 32 µs at 20 MHz) n
Figure 3.11.3 Reset Mode For warm-up counter, 27 and 29 output of 15-stage binary counter can be selected using WDMOD register. When a stable-external oscillator is used, shorter warm-up time is available using T45CR register. When = 1, counting value 27 is selected. When the watchdog timer is in operation, this shorter warm-up time function cannot be available. This function can be available by setting = 0.
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TMP93CS32 3.11.2 Control registers
Watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) 1. Setting the detecting time of watchdog timer This 2-bit register is used to set the watchdog timer interrupt time for detecting the runaway. This register is initialized to WDMOD = 00 when reset. The defecting time of WDT is shown Table 3.11.1. 2. Watchdog timer enable/disable control register When reset, WDMOD is initialized to “1” enable the watchdog timer. To disable, it is necessary to set this bit to “0” and write the disable code (B1H) in the watchdog timer control register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return from the disable state to enable state by merely setting to “1”. 3. Watchdog timer out reset connection This register is used to connect the output of the watchdog timer with RESET terminal, internally. Since WDMOD is initialized to 0 at reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear of binary counter the watchdog timer function. • Disable control By writing the disable code (B1H) in this WDCR register after clearing WDMOD to “0”, the watchdog timer can be disabled.
W DMOD W DCR ←0 ←1 −−− 011 − 0 −XX 001 Clear WDMODto “0”. Write the disable code (B1H).
• •
Enable control Set WDMOD to “1”. Watchdog timer clear control The binary counter can be cleared and resume counting by writing clear code (4EH) into the WDCR register.
W DCR
←0 1 0 0 1 1 1 0 X: Don’t care −: No change
Write the clear code (4EH).
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W atchdog Timer Mode Control Register 7
WDMOD (005CH) Bit symbol Read/Write After reset Function 1 WDT control 0: Disable 1: Enable 0 0 0 Select the warm-up time. 00: 01: 10: 11: Select the detecting time of WDT 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS See Table 3.11.1. WDTE
6
WDTP1
5
WDTP0
4
WARM R/W
3
HALTM1 0 Standby mode RUN mode STOP mode IDLE1 mode IDLE2 mode
2
HALTM0 0
1
RESCR 0
0
DRVE 0
1: Internally 1: Drive the connects pin even WDT out in STOP to the mode. reset pin.
Refer to section 3.3 “Standby function.” Watchdog timer out control 0 1 Select the warm-up time Gear value 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) T45CR = 0 = 0 0.8192 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms = 1 3.277 ms 6.554 ms 13.107 ms 26.214 ms 52.429 ms Don’t care Connects WDT out to a reset at fc = 20 MHz T45CR = 1 = X 6.4 µs 12.8 µs 25.6 µs 51.2 µs 102.4 µs
Watchdog timer enable/disable control 0 1 Disable Enable
Note: When the watchdog timer is in operation, T45CR is cleared to “0”.
Figure 3.11.4 Watchdog Timer Related Register (1/2)
93CS32-145
2004-02-10
TMP93CS32
W atchdog Timer Control Register 7
WDCR (005DH) Bit symbol Read/Write After reset Function
6
5
4
− W −
3
2
1
0
B1H: WDT disable code 4EH: WDT clear code
Disable/clear WDT B1H 4EH Others Note: Disable code Clear code Don’t set
When the watchdog timer is in operation, T45CR is cleared to “0”.
Figure 3.11.5 Watchdog Timer Related Register (2/2) Table 3.11.1 Watchdog Timer Detecting Time at fc = 20 MHz W atchdog Timer Detecting Time Gear value 00
000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 3.277 ms 6.554 ms 13.107 ms 26.214 ms 52.429 ms
W DMOD 01
13.107 ms 26.214 ms 52.429 ms 104.858 ms 209.715 ms
10
52.429 ms 104.858 ms 209.715 ms 419.430 ms 838.861 ms
11
209.715 ms 419.430 ms 838.861 ms 1.678 s 3.355 s
93CS32-146
2004-02-10
TMP93CS32 3.11.3 Operation
The watchdog timer generates interrupt INTWD after the detecting time set in the WDMOD. The watchdog timer must be zero-cleared by software before an INTWD interrupt is generated. If the CPU malfunctions (Runaway) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter overflows and an INTWD interrupt is generated. The CPU detects malfunction (Runaway) due to the INTWD Interrupt and it is possible to return to normal operation by an anti-mulfunction program. By connecting the watchdog timer out pin to peripheral devices’ resets, a CPU malfunction can also be acknowledged to other devices. The watchdog timer restarts operation immediately after resetting is released. The watchdog timer stops its operation in the IDLE1 and STOP modes. In the RUN and IDLE2 modes, the watchdog timer is enabled. However, the function can be disabled when entering the RUN, IDLE2 mode.
Example: 1. Clear the binary counter. WDCR ←0 1 0 0 1 1 1 0 Write clear code (4EH). 2. Set the watchdog timer detecting time to 217/fSYS. WDMOD ←1 0 1 − − − X X 3. Disable the watchdog timer. WDMOD ←0 − − − − − X X Clear WDTE to “0”. WDCR ←1 0 1 1 0 0 0 1 Write disable code (B1H). 4. Set IDLE1 mode. WDMOD ←0 − − − 1 0 X X Disables WDT and sets IDLE1 mode. WDCR ←1 0 1 1 0 0 0 1 Executes HALT command. Set the HALT mode. 5. Set the STOP mode (Warm-up time: 216/fSYS). WDMOD ←− − − 1 0 1 X X Set the STOP mode. Executes HALT command. Set the HALT mode. X: Don’t care −: No change
93CS32-147
2004-02-10
TMP93CS32
4.
4.1
Electrical Characteristics
Absolute Maximum Ratings (TMP93CS32F)
Parameter
Power supply voltage Input voltage Output current (per 1 pin) P7 Output current (per 1 pin) except P7 Output current (total) Output current (total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature
“X” used in an expression shows a cycle of clock fFPH. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value as an example is gear = 1/fc (SYSCR1 = “000”).
Symbol
VCC VIN IOL1 IOL2 Σ IOL Σ IOH PD TSOLDER TSTG TOPR
Rating
−0.5 to 6.5 −0.5 to VCC + 0.5 20 2 120 −80 350 260 −65 to 150 −40 to 85
Unit
V
mA
mW °C
Note:
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
4.2
DC Characteristics
Ta = −40 to 85°C Parameter Symbol
VCC
Condition
fc = 4 to 20 MHz fc = 4 to 12.5 MHz VCC ≥ 4.5 V VCC < 4.5 V
Min
4.5 2.7
Typ. (Note)
Max
5.5 0.8 0.6 0.3 VCC 0.25 VCC 0.3 0.2 VCC
Unit
Power supply voltage AVCC = VCC AVSS = VSS = 0 V AD0 to AD15 Input Port 2 to 7 (Except P35) low voltage RESET , NMI , INT0 EA , AM8/ AM16 X1 AD0 to AD15 Input Port 2 to 7 (Except P35) high voltage RESET , NMI , INT0 EA , AM8/ AM16 X1 Output low voltage Output low current (P7)
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL IOL7 VOH1
−0.3 VCC = 2.7 to 5.5 V
V
VCC ≥ 4.5 V VCC < 4.5 V
2.2 2.0 0.7 VCC 0.75 VCC VCC − 0.3 0.8 VCC VCC + 0.3
VCC = 2.7 to 5.5 V
IOL = 1.6 mA (VCC = 2.7 to 5.5 V) VOL = 1.0 V (VCC = 5 V ± 10%) (VCC = 3 V ± 10%) 16 7 2.4
0.45 mA
Output high voltage VOH2
IOH = −400 µA (VCC = 3 V ± 10%) IOH = −400 µA (VCC = 5 V ± 10%)
V 4.2
Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted.
93CS32-148
2004-02-10
TMP93CS32
Parameter
Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at STOP, RAM back up)
Symbol
IDAR (Note2) ILI ILO VSTOP
Condition
VEXT = 1.5 V REXT = 1.1 kΩ (VCC = 5 V ± 10% only) 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 V VIL2 = 0.2 VCC, VIH2 = 0.8 VCC VCC = 5.5 V VCC = 4.5 V VCC = 3.3 V VCC = 2.7 V fc = 1 MHz
Min
−1.0
Typ. (Note1)
Max
−3.5
Unit
mA µA V
0.02 0.05 2.0 45 50 70 90
±5 ±10 6.0 130 160 280 400 10
RESET pull-up resistor
RRST
kΩ
Pin capacitance Schmitt width RESET , NMI , INT0 Programmable pull-up resistor NORMAL (Note3) RUN IDLE2 IDLE1 NORMAL (Note3) RUN IDLE2 IDLE1 STOP
CIO VTH
pF V
0.4 VCC = 5.5 V 45 50 70 90
1.0 130 160 280 400 19 25 25 15 5 10 9 5 1.5 10 0.2 20 50 17 10 3.5 6.5 5.0 3.0 0.8
RKH
VCC = 4.5 V VCC = 3.3 V VCC = 2.7 V VCC = 5 V ± 10% fc = 20 MHz
kΩ
mA
ICC
VCC = 3 V ± 10% fc = 12.5 MHz (Typ.: VCC = 3.0 V) Ta ≤ 50°C Ta ≤ 70°C Ta ≤ 85°C VCC = 2.7 V to 5.5 V
µA
Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: ICC measurement conditions (NORMAL): Only CPU is operational ; output pins are open and input pins are fixed. (Reference) Definition of IDAR
REXT IDAR
VEXT
93CS32-149
2004-02-10
TMP93CS32
4.3
AC Characteristics
(1) VCC = 5 V ± 10% Variable Min
50 2x − 40 0.5x − 20 1.5x − 70 0.5x − 15 0.5x − 20 x − 40 0.5x − 25 0.5x − 20 x − 25 1.5x − 50 0.5x − 25 3.0x − 55 3.5x − 65 2.0x − 60 2.0x − 40 0 x − 15 2.0x − 40 2.0x − 55 0.5x − 15 3.5x − 90 3.0x − 80 2.0x + 0 2.5x − 120 2.5x + 50 200 206 200 125 36 175 200 85 0 48 85 70 16 129 108 100 5
No.
Parameter
Symbol
tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW
(1 + n) WAIT mode (1 + n) WAIT mode (1 + n) WAIT mode
16 MHz Min
62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65
20 MHz Min
50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70
Max
31250
Max
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 Osc. period (= x) 2 CLK pulse width 3 A0 to A23 valid → CLK hold 4 CLK valid → A0 to A23 hold 5 A0 to A15 valid → ALE fall 6 ALE fall → A0 to A15 hold 7 ALE high pulse width 8 ALE fall → RD / WR fall 9 RD / WR rise → ALE rise 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width 17 RD rise → D0 to D15 hold 18 RD rise → A0 to A15 output 19 21
WR low pulse width
20 D0 to D15 valid → WR rise
WR rise → D0 to D15 hold
tWD tAWH tAWL tCW tAPH tAPH2 tCP
22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → Port input 26 A0 to A23 valid → Port hold 27
WR rise → Port valid
AC measuring conditions • • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (Except for AD0 to AD15)
93CS32-150
2004-02-10
TMP93CS32
(2) VCC = 3 V ± 10% No. Parameter Symbol
tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW
(1 + n) WAIT mode (1 + n) WAIT mode (1 + n) WAIT mode
Variable Min
80 2x − 40 0.5x − 30 1.5x − 80 0.5x − 35 0.5x − 35 x − 60 0.5x − 35 0.5x − 40 x − 50 1.5x − 50 0.5x − 40 3.0x − 110 3.5x − 125 2.0x − 115 2.0x − 40 0 x − 25 2.0x − 40 2.0x − 120 0.5x − 40 3.5x − 130 3.0x − 100 2.0x + 0 2.5x − 195 2.5x + 50 200
12.5 MHz Min
80 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 5 250 200
Max
31250
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1 Osc. period (= x) 2 CLK pulse width 3 A0 to A23 valid → CLK hold 4 CLK valid → A0 to A23 hold 5 A0 to A15 valid → ALE fall 6 ALE fall → A0 to A15 hold 7 ALE high pulse width 8 ALE fall → RD / WR fall 9 RD / WR rise → ALE rise 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width 17 RD rise → D0 to D15 hold 18 RD rise → A0 to A15 output 19 21
WR low pulse width
20 D0 to D15 valid → WR rise
WR rise → D0 to D15 Hold
tWD tAWH tAWL tCW tAPH tAPH2 tCP
22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → Port input 26 A0 to A23 valid → Port hold 27
WR rise → Port valid
AC measuring conditions • • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF Input level: High 0.9 × VCC/Low 0.1 × VCC
93CS32-151
2004-02-10
TMP93CS32
(3) Read cycle
tOSC X1
tCLK CLK tAK A0 to A23 tAWH tAWL
WAIT
tKA
tCW
tAPH tAPH2 Port input (Note) tADH
RD
tRR tRD
tCA
tACH tACL tLC
tRAE tHR D0 to D15 tCL
tADL
AD0 to AD15 tAL ALE tLL
A0 to A15 tLA
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93CS32-152
2004-02-10
TMP93CS32
(4) Write cycle
X1
CLK
A0 to A23
WAIT
Port output (Note) tWW
WR , HWR
tCP
tDW AD0 to AD15 A0 to A15 D0 to D15
tWD
ALE
Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93CS32-153
2004-02-10
TMP93CS32
4.4
Serial Channel Timing
(1) I/O interface mode 1. SCLK input mode
Symbol tSCY tOSS tOHS tHSR
Parameter
SCLK cycle Output data → Rising/falling edge of SCLK SCLK rising/falling edge → Output data hold SCLK rising/falling edge → Input data hold
Variable Min
16x tSCY/2 − 5x − 50 5x − 100 0 tSCY − 5x − 100
12.5 MHz Max Min
1.28 µs 190 300 0 780
20 MHz Min
0.8 µs 100 150 0 450
Max
Max
Unit
ns ns ns ns ns
SCLK rising/falling edge → Effective data input tSRD
Note:
SCLK rising/falling timing; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. 2. SCLK output mode
Symbol tSCY tOSS tOHS tHSR tSRD
Parameter
SCLK cycle (programmable) Output data → SCLK rising edge SCLK rising edge → Output data hold SCLK rising edge → Input data hold SCLK rising edge → Effective data input SCLK Output mode/ Input rising edge mode SCLK (Input falling edge mode)
Variable Min
16x tSCY − 2x − 150 2x − 80 0 tSCY − 2x − 150
12.5 MHz Max
8192x
20 MHz Min
0.8 µs
Min
970 80 0
Max
Max
409.6 µs
Unit
ns ns ns ns
1.28 µs 655.36 µs
550 20 0 970 550
ns
tSCY
tOSS Output data TXD 0
tOHS 1 tSRD tHSR 1 Valid 2 Valid 3 Valid 2 3
Input data RXD
0 Valid
(2) UART mode (SCLK0 and SCLK1 are external input) Parameter
SCLK cycle SCLK low level pulse width SCLK high level pulse width Symbol tSCY tSCYL tSCYH
Variable Min
4x + 20 2x + 5 2x + 5
12.5 MHz Max Min
340 165 165
20 MHz Min
220 105 105
Max
Max
Unit
ns ns ns
93CS32-154
2004-02-10
TMP93CS32
4.5
AD Conversion Characteristics
AVCC = VCC, AVSS = VSS Parameter Symbol
VREFH VREFL VAIN IREF (VREFL = 0 V) − VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 2.7 to 5.5 V VCC = 5 V ± 10% VCC = 3 V ± 10%
Power Supply
VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10%
Min
VCC − 0.2 VCC − 0.2 VSS VSS VREFL
Typ.
VCC VCC VSS VSS 0.5 0.3 0.02 ±1.0 ±1.0
Max
VCC VCC VSS + 0.2 VSS + 0.2 VREFH 1.5 0.9 5.0 ±3.0 ±5.0
Unit
Analog reference voltage (+) Analog reference voltage (−) Analog input voltage range Analog current for analog reference voltage = 1 = 0 Error (except quantization errors)
V
mA µA LSB
Note 1: 1LSB = (VREFH − VREFL)/210 [V]. Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin.
4.6
Event Counter Input Clock (External Input Clock: TI4, TI5, TI6, and TI7)
Parameter
Symbol tVCK tVCKL tVCKH
Variable Min
8X + 100 4X + 40 4X + 40
12.5 MHz Max Min
740 360 360
20 MHz Min
500 240 240
Max
Max
Unit
ns ns ns
Clock cycle Low level clock pulse width High level clock pulse width
4.7
Interrupt and Capture Operation
(1) NMI , INT0 interrupts Parameter
Symbol tINTAL tINTAH
Variable Min
4X 4X
12.5 MHz Max Min
320 320
20 MHz Min
200 200
Max
Max
Unit
ns ns
NMI , INT0 low level pulse width
NMI , INT0 high level pulse width
(2) INT4 to INT7 interrupts and capture Parameter
INT4 to INT7 low level pulse width INT4 to INT7 high level pulse width Symbol tINTBL tINTBH
Variable Min
4X + 100 4X + 100
12.5 MHz Max Min
420 420
20 MHz Min
300 300
Max
Max
Unit
ns ns
93CS32-155
2004-02-10
TMP93CS32
5.
Table of Special Function Registers
The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 128-bytes addresses from 000000H to 00007FH. (1) I/O port (2) I/O port control (3) Clock control (4) Interrupt control (5) Bus width/wait control (6) Timer control (7) Serial channel control (8) AD converter control (9) Watchdog timer control
Configuration of the table Symbol Name Address 7 6 1 0 Bit symbol Read/Write Initial value after reset Remarks
Note: “Prohibit RMW” in the table means that you cannot use RMW instructions on these registers. Example: When setting only bit0 of register P0CR, “SET 0, (0002H)” cannot be used. The LD (transfer) instruction must be used to write all eight bits.
93CS32-156
2004-02-10
TMP93CS32
Table 5 I/O Register Address Map
Address
000000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Name
P0 P1 P0CR (Reserved) P1CR P1FC P2 P3 P2CR P2FC P3CR P3FC P4 P5 P4CR (Reserved) P4FC (Reserved) P6 P7 P6CR P7CR P6FC
Address
20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
Name
TRUN (Reserved) TREG0 TREG1 T10MOD TFFCR TREG2 TREG3 T32MOD TRDC
Address
40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH
Name
TREG6L TREG6H TREG7L TREG7H CAP3L CAP3H CAP4L CAP4H T5MOD T5FFCR
Address
60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH
Name
ADREG04L ADREG04H ADREG15L ADREG15H ADREG2L ADREG2H ADREG3L ADREG3H WAITC0 WAITC1 WAITC2 (Reserved) (Reserved) CKOCR SYSCR0 SYSCR1 INTE0AD INTE45 INTE67 INTET10 INTET32 INTET54 INTET76 INTEO54 INTES0 INTES1 (Reserved) IIMC DMA0V DMA1V DMA2V DMA3V
(Reserved)
(Reserved)
TREG4L TREG4H TREG5L TREG5H CAP1L CAP1H CAP2L CAP2H T4MOD T4FFCR T45CR
SC0BUF SC0CR SC0MOD BR0CR SC1BUF SC1CR SC1MOD BR1CR ODE (Reserved) WDMOD WDCR ADMOD0 ADMOD1
(Reserved)
(Reserved)
Note:
Do not access to addresses which do not have register names allocated.
93CS32-157
2004-02-10
TMP93CS32
(1) I/O port
Symbol Name Address
7
P07
6
P06
5
P05
4
P04 R/W Undefined Input mode
3
P03
2
P02
1
P01
0
P00
P0
PORT0
00H
P17 P1 PORT1 01H 0 P27 1
P16 0 P26 1
P15 0 P25 1 P35 1
P14 R/W 0
P13 0
P12 0 P22 1 P32 R/W 1 Input mode P42 1
P11 0 P21 1 P31 1 P41 1
P10 0 P20 1 P30 (Note) 1 − −
(Note) Always write “1”.
Input mode 06H P2 PORT2 (Prohibit RMW *) 07H P3 PORT3 (Prohibit RMW *) P47 P4 PORT4 0CH 1 P46 1 P24 R/W 1 Input mode − − − − 1 P23
Input mode (Note) Always write “1”. P45 P44 P43 R/W 1 1 Input mode P55 P54 P53 R 1
Output mode
P52
P51
P50
P5
PORT5
0DH
Undefined Input mode − − − − P65 1 − − P64 R/W 1 − R/W − − − − − 1 Input mode 1 (Note) Always write “1”. P63 1 Input mode − − P71 P70 P62 1 P61 1 P60 1
12H P6 PORT6 (Prohibit RMW *)
(Note) Always write “1”. − −
P7
PORT7
13H
Note:
When P30 pin is defined as RD signal output mode (P3FC = 1), clearing the output latch register P30 to “0” outputs the RD strobe from P30 pin for PSRAM, even when the internal address is accessed. If the output latch register P30 remains “1”, the RD strobe is output only when the external address is accessed.
Read/Write R/W: Either read or write is possible. R: Only read is possible. W: Only write is possible. Prohibit RMW: Prohibit Read Modify Write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF instruction.) Prohibit RMW *: Read-modify-write is prohibited when controlling the PU resistor.
93CS32-158
2004-02-10
TMP93CS32
(2) I/O port control (1/2)
Symbol Name Address
02H P0CR PORT0 control (Prohibit RMW) 04H P1CR PORT1 control (Prohibit RMW) 05H P1FC PORT1 function (Prohibit RMW) 08H P2CR PORT2 control (Prohibit RMW) 09H P2FC PORT2 function (Prohibit RMW) 0AH P3CR PORT3 control (Prohibit RMW) − 0BH P3FC PORT3 function (Prohibit RMW) P47C 0EH P4CR PORT4 control (Prohibit RMW) 0 0 0 0: IN 1: OUT P47F 10H P4FC PORT4 function (Prohibit RMW) W 0 0: Port 1: TO6 P44F W 0 0: Port 1: TO4 P41F W 0 0: Port 1: TO3 0 W −
(Note) Always write “0”.
7
P07C 0 P17C 0 P17F 0 P27C 0 P27F 0
6
P06C 0 P16C 0 P16F 0 P26C 0 P26F 0
5
P05C 0 P15C 0 P15F 0 P25C 0 P25F 0 P35C 0 0: IN 1: OUT
4
P04C W 0 P14C W 0 P14F W 0 P24C W 0 P24F W 0 − W −
3
P03C 0 P13C 0 P13F 0 P23C 0 P23F 0 − −
2
P02C 0 P12C 0 P12F 0 P22C 0 P22F 0 P32C 0 0: IN 1: OUT P32F W 0 0: Port 1: HWR P42C 0
1
P01C 0 P11C 0 P11F 0 P21C 0 P21F 0
0
P00C 0 P10C 0 P10F 0 P20C 0 P20F 0
0: IN 1: OUT (When external access, set as AD7 to AD0 and cleared to “0”.)
P1FC/P1CR = 00: IN, 01: OUT, 10: AD15 to AD8, 11: A15 to A8
P2FC/P2CR = 00: IN, 01: OUT, 10: A7 to A0, 11: A23 to A16
(Note) Always write “1”. − − − −
P31F 0 0: Port 1: WR P41C 0
P30F 0 0: Port 1: RD − −
(Note) Always write “1”.
(Note) Always write “0”. P45C P44C W 0 P43C
P46C
93CS32-159
2004-02-10
TMP93CS32
I/O port control (2/2)
Symbol Name Address
14H P6CR PORT6 control (Prohibit RMW) 15H P7CR PORT7 control (Prohibit RMW) 16H P6FC PORT6 function (Prohibit RMW)
7
− − − −
6
− − − −
5
P65C 0 − − P65F W 0 0: Port 1: SCLK1
4
P64C W 0 − W −
3
P63C 0 0: IN − − P63F W 0 0: Port 1: TXD1
2
P62C 0 1: OUT − − P62F 0 0: Port 1: SCLK0
1
P61C 0 P71C 0 0: IN
0
P60C 0 P70C 0 1: OUT P60F W 0 0: Port 1: TXD0
(Note) Always write “1”.
(Note) Always write “1”.
93CS32-160
2004-02-10
TMP93CS32
(3) Clock control
Symbol Name Address
7
6
5
4
3
2
1
ALEEN R/W
0
CLKEN 0
CLK pin control
Clock output CKOCR control register
0 006DH
ALE pin control
0: HZ output 1 0: HZ output 1: ALE output 1: CLK output
− 1 006EH
− 0
− 1
− R/W 0
− 0
− 0
PRCK1 0
PRCK0 0
System clock SYSCR0 control register 0
(Note) Always (Note) Always (Note) Always (Note) Always (Note) Always (Note) Always Select prescaler clock write “1”. write “0”. write “1”. write “0”. write “0”. write “0”. 00: fFPH
− 0 System clock control register 1
GEAR2 1
01: (Reserved) 10: fc/16 11: (Reserved) GEAR1 GEAR0 R/W 0 0
(Note) Always Select gear value of high frequency (fc) write “0”. 000: fc/1
SYSCR1
006FH
001: 010: 011: 100: 101: 110: 111:
fc/2 fc/4 fc/8 fc/16 (Reserved) (Reserved) (Reserved)
93CS32-161
2004-02-10
TMP93CS32
(4) Interrupt control (1/2)
Symbol Name Address
70H INTE0AD
INT0/AD enable register
7
IADC
6
INTAD IADM2 0 INT5 I5M2 0 INT7 I7M2 0 IT1M2 0 IT3M2 0 IT5M2 0 IT7M2 0 INTTO5 ITO5M2 0 INTTX0 ITX0M2 0 INTTX1 ITX1M2 0
5
IADM1 W 0 I5M1 W 0 I7M1 W 0 IT1M1 W 0 IT3M1 W 0 IT5M1 W 0 IT7M1 W 0 ITO5M1 W 0 ITX0M1 W 0 ITX1M1 W 0
4
IADM0 0 I5M0 0 I7M0 0 IT1M0 0 IT3M0 0 IT5M0 0 IT7M0 0 ITO5M0 0 ITX0M0 0 ITX1M0 0
3
I0C R/W 0 I4C R/W 0 I6C R/W 0 IT0C R/W 0 IT2C R/W 0 IT4C R/W 0 IT6C R/W 0 ITO4C R/W 0 IRX0C R/W 0 IRX1C R/W 0
2
INT0 I0M2 0 INT4 I4M2 0 INT6 I6M2 0 IT0M2 0 IT2M2 0 IT4M2 0 IT6M2 0 INTTO4 ITO4M2 0 INTRX0 IRX0M2 0 INTTRX1 IRX1M2 0
1
I0M1 W 0 I4M1 W 0 I6M1 W 0 IT0M1 W 0 IT2M1 W 0 IT4M1 W 0 IT6M1 W 0 ITO4M1 W 0 IRX0M1 W 0 IRX1M1 W 0
0
I0M0 0 I4M0 0 I6M0 0 IT0M0 0 IT2M0 0 IT4M0 0 IT6M0 0 ITO4M0 0 IRX0M0 0 IRX1M0 0
(Prohibit PMW) 71H
R/W 0 I5C
INTE45
INT4/5 enable register
(Prohibit PMW) 72H
R/W 0 I7C
INTE67
INT6/7 enable register
(Prohibit PMW) 73H
R/W 0 IT1C
INTT1 (Timer1) R/W 0 IT3C
INTT0 (Timer0)
INTET10
INTT1/0 enable register
(Prohibit PMW) 74H
INTT3 (Timer3) R/W 0 IT5C
INTT2 (Timer2)
INTET32
INTT3/2 enable register
(Prohibit PMW) 75H
INTTR5 (TREG5) R/W 0 IT7C
INTTR4 (TREG4)
INTET54
INTT5/4 enable register
(Prohibit PMW) 76H
INTTR7 (TREG7) R/W 0 ITO5C
INTTR6 (TREG6)
INTET76
INTT7/6 enable register
(Prohibit PMW) 77H
INTEO54
INTTO5/4 enable register
(Prohibit PMW) 78H
R/W 0 ITX0C
INTES0
INTRX0/ TX0 enable register INTRX1/ TX1 enable register
(Prohibit PMW) 79H
R/W 0 ITX1C
INTES1
(Prohibit PMW)
R/W 0
IxxM2 0 0 0 0 1 1 1 1 IxxC 0 1
IxxM1 0 0 1 1 0 0 1 1
IxxM0 0 1 0 1 0 1 0 1
Function (Write) Prohibits interrupt request. Sets interrupt request level to “1”. Sets interrupt request level to “2”. Sets interrupt request level to “3”. Sets interrupt request level to “4”. Sets interrupt request level to “5”. Sets interrupt request level to “6”. Prohibits interrupt request. Function (Write) Clears interrupt request flag. - - - - - Don’t care - - - - -
Function (Read) Indicates no interrupt request. Indicates interrupt request.
93CS32-162
2004-02-10
TMP93CS32
Interrupt control (2/2)
Symbol Name Address
Micro DMA 0 request vector 7CH (Prohibit RMW) 7DH (Prohibit RMW) 7EH (Prohibit RMW) 7FH (Prohibit RMW) − W 7BH Interrupt input mode (Prohibit control RMW) 0
(Note) Always write “0”.
7
6
5
4
DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0
3
DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0
2
DMA0V2 W 0 Micro DMA0 start vector DMA1V2 W 0 Micro DMA1 start vector DMA2V2 W 0 Micro DMA2 start vector DMA3V2 W 0 Micro DMA3 start vector I0IE 0 1: INT0 input enable
1
DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 I0LE W 0 0: INT0 edge mode 1: INT0 level mode
0
DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 NMIREE 0 1: Operation even at
NMI
DMA0V
Micro DMA 1 DMA1V request vector Micro DMA 2 DMA2V request vector Micro DMA 3 DMA3V request vector
IIMC
rising edge
(5) Bus-width/Wait control
Symbol Name Address
7
6
5
4
B0BUS
3
B0W1 0
2
B0W0 W 0
1
B0C1 0
0
B0C0 0
Block 0 wait WAITC0 control register
68H (Prohibit RMW)
0
0: 16-bit bus 00: 2 waits 1: 8-bit bus 01: 1 wait 10: (1 + n) waits B1BUS 11: 0 waits B1W1 0 B1W0 W 0 0
00: 7F00H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B1C1 B1C0 0 0
Block 1 wait WAITC1 control register
69H (Prohibit RMW)
0: 16-bit bus 00: 2 waits 1: 8-bit bus 01: 1 wait 10: (1 + n) waits B2BUS 11: 0 waits B2W1 0 B2W0 W 0 0
00: 880H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B2C1 B2C0 1 00: 8000H to 01: 400000H to 10: 800000H to 11: C00000H to 1
Block 2 wait WAITC2 control register
6AH (Prohibit RMW)
0: 16-bit bus 00: 2 waits 1: 8-bit bus 01: 1 wait 10: (1 + n) waits 11: 0 waits
93CS32-163
2004-02-10
TMP93CS32
(6) Timer control (1/3)
Symbol Name Address
7
PRRUN R/W
6
5
T5RUN 0
4
T4RUN 0
3
T3RUN R/W 0
2
T2RUN 0
1
T1RUN 0
0
T0RUN 0
Timer run
TRUN
control register
20H
0
Prescaler & timer run/stop control 0: Stop & clear 1: Run (count up) 22H (Prohibit RMW) − W Undefined − W Undefined T10M1 R/W 0 24H 0 0 0 00: 8-bit timer 01: 16-bit timer 10: − 11: − TFF3C1 TFF3C0 W 1 25H 00: Invert TFF3 01: Set TFF3 10: Clear TFF3 11: Don’t care 1 00: TO0TRG 01: φT1 10: φT16 11: φT256 TFF1C1 TFF1C0 W 0 TFF3 inversion source 0: Timer 2 1: Timer 3 − W Undefined − W Undefined T32M1 0 28H 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM T32M0 0 PWM21 0 00: − 01: 26 − 1 PWM 10: 27 − 1 cycle 11: 28 − 1 PWM20 R/W 0 0 00: TO2TRG 01: φT1 10: φT16 11: φT256 0 0 00: Don’t set 01: φT1 10: φT4 11: φT16 TR2DE R/W 0 29H 0: Double buffer disable 1: Double buffer enable 0 T3CLK1 T3CLK0 T2CLK1 T2CLK0 1 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don’t care 1 0 1: TFF1 invert enable T10M0 T1CLK1 T1CLK0 R/W 0 00: Don’t set 01: φT1 10: φT4 11: φT16 TFF1IE R/W 0 TFF1 inversion source 0: Timer 0 1: Timer 1 0 T0CLK1 T0CLK0
TREG0
8-bit timer register 0
23H 8-bit timer TREG1 (Prohibit register 1 RMW)
8-bit timers 0 and 1 source CLK & MODE control register
T10 MOD
TFF3IE R/W 0 1: TFF3 invert enable
TFF3IS
TFF1IS
8-bit timer flip-flop TFFCR control register
TREG2
8-bit timer register 2
26H (Prohibit RMW) 27H (Prohibit RMW)
TREG3
8-bit timer register 3 8-bit timers 2 and 3 source CLK & MODE control register
T32 MOD
− 0
(Note) Always write “0”.
TRDC
Timer register double buffer control register
93CS32-164
2004-02-10
TMP93CS32
Timer control (2/3)
Symbol Name Address
30H 16-bit timer TREG4L register 4 (Prohibit low RMW) 31H 16-bit timer TREG4H register 4 (Prohibit high RMW) 32H 16-bit timer TREG5L register 5 (Prohibit low RMW) 33H 16-bit timer TREG5H register 5 (Prohibit high RMW)
Capture register 1 low Capture register 1 high Capture register 2 low Capture register 2 high
7
6
5
4
− W Undefined − W Undefined − W Undefined − W Undefined − R Undefined −
3
2
1
0
CAP1L
34H
CAP1H
35H
R Undefined −
CAP2L
36H
R Undefined −
CAP2H
37H CAP1IN CAP12M1 0
R Undefined CAP12M0 0 CLE R/W 0 1: UC4 clear enable 0 0 Capture timing 00: Disable 01: TI4↑ TI5↑ 10: TI4↑ TI4↓ 11: TFF1↑ TFF1↓ CAP1T4 R/W 0 0 0 0 1 EQ5T4 Source clock 00: TI4 01: φT1 10: φT4 11: φT16 TFF4C1 W 1 TFF4 control 00: Invert TFF4 01: Set TFF4 10: Clear TFF4 11: Don’t care TFF4C0 T4CLK1 T4CLK0 W 1 0: Software capture 1: Don’t care CAP2T4
T4MOD
16-bit timer 4 source CLK & MODE control register
38H
EQ4T4
T4FFCR
16-bit timer 4 flip-flop control register
39H Invert when the UC value is loaded to CAP2.
TFF4 invert trigger 0: Trigger disable 1: Trigger enable Invert when the UC value is loaded to CAP1. Invert when the UC matches TREG5. Invert when the UC matches TREG4.
93CS32-165
2004-02-10
TMP93CS32
Timer control (3/3)
Symbol Name Address
7
QCU R/W 0
6
5
4
3
2
1
DB6EN R/W 0 Double buffer 0: Disable 1: Enable Double buffer of TREG6
0
DB4EN 0
T45CR
T4, T5 control register
3AH
Watchdog/ Warm-up timer control
Double buffer of TREG4
16-bit timer TREG6L register 6 low 16-bit timer TREG6H register 6 high 16-bit timer TREG7L register 7 low 16-bit timer TREG7H register 7 high Capture register 3 low
40H (Prohibit RMW) 41H (Prohibit RMW) 42H (Prohibit RMW) 43H (Prohibit RMW) 44H
− W Undefined − W Undefined − W Undefined − W Undefined − R Undefined −
CAP3L
Capture CAP3H register 3 high Capture register 4 low
45H
R Undefined −
CAP4L
46H
R Undefined −
Capture CAP4H register 4 high
47H CAP3IN CAP34M1 0
R Undefined CAP34M0 0 CLE R/W 0 1: UC5 clear enable 0 0 Capture timing 00: Disable 01: TI6↑ TI7↑ 10: TI6↑ TI6↓ 11: TFF1↑ TFF1↓ CAP3T6 R/W 0 0 0 0 1 TFF6 invert trigger 0: Trigger disable 1: Trigger enable Invert when the UC value is loaded to CAP4. Invert when the UC value is loaded to CAP3. Invert when the UC matches TREG7. Invert when the UC matches TREG6. EQ7T6 Source clock 00: TI6 01: φT1 10: φT4 11: φT16 TFF6C1 W 1 TFF6 control 00: Invert TFF6 01: Set TFF6 10: Clear TFF6 11: Don’t care TFF6C0 T5CLK1 T5CLK0 W 1 0: Software capture 1: Don’t care CAP4T6
16-bit timer 5 source CLK & T5MOD mode control register
48H
EQ6T6
16-bit timer 5 flip-flop T5FFCR control register
49H
93CS32-166
2004-02-10
TMP93CS32
(7) Serial channel control
Symbol Name Address
Serial channel 0 SC0BUF buffer register
7
RB7 TB7
6
RB6 TB6
5
RB5 TB5
4
RB4 TB4
3
RB3 TB3
2
RB2 TB2
1
RB1 RB1
0
RB0 TB0
50H (Prohibit RMW)
R (Receiving)/W (Transmission) Undefined RB8 R EVEN R/W 0 Parity 0: Odd 1: Even CTSE0 0 0 1: Parity enable PE OERR 0 Overrun PERR 0 1: Error Parity Framing 1: SCLK0 RXE 0 1: Receive enable WU R/W Undefined 0 1: Wake up enable 0 0 0 0 SM1 SM0 SC1 FERR 0 SCLKS R/W 0 0: SCLK0 0 1: Input SCLK0 pin SC0 IOC R (Cleared to 0 by reading)
Serial channel 0 SC0CR control register
undefined 51H Receiving data bit8
TB8
Serial channel 0 SC0MOD mode control register
52H
Transmisson 1: CTS0 data bit8 enable
− Baud rate 0 control register R/W 0 53H Fix at ”0”
BR0CK1 0
BR0CK0 0
00: I/O interface 01: UART 7-bit 10: UART 8-bit 11: UART 9-bit BR0S3 BR0S2 R/W 0
00: TO2 trigger 01: Baud rate generator 0 10: Internal clock φ1 11: External clock SCLK0 BR0S1 BR0S0 0
BR0CR
00: φT0 01: φT2 10: φT8 11: φT32 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3
Serial channel 1 SC1BUF buffer register
54H (Prohibit RMW)
RB7 TB7
0 0 Set frequency divisor 0000: 16 divisions 0001 to 1 to 15 divisions 1111 RB2 RB1 TB2 RB1
RB0 TB0
R (Receiving)/W (Transmission) Undefined RB8 R EVEN R/W 0 Parity 0: Odd 1: Even CTSE1 0 0 1: Parity enable PE OERR 0 Overrun PERR 0 1: Error Parity Framing 1: SCLK1 RXE 0 1: Receive enable WU R/W undefined 0 1: Wake up enable 0 0 0 0 SM1 SM0 SC1 FERR 0 SCLKS R/W 0 0: SCLK1 0 1: Input SCLK1 pin SC0 IOC R (Cleared to 0 by reading.)
SC1CR
Serial channel 1 control register
Undefined 55H Receiving data bit8
TB8
Serial channel 1 SC1MOD mode control register
56H
Transmisson 1: CTS1 data bit8 enable
− R/W
BR1CR
BR1CK1 0
BR1CK0 0
00: I/O interface 01: UART 7-bit 10: UART 8-bit 11: UART 9-bit BR1S3 BR1S2 R/W 0
00: TO2 trigger 01: Baud rate generator 1 10: Internal clock φ1 11: External clock SCLK1 BR1S1 BR1S0
Baud rate 1 control register
0 57H Fix at ”0”
00: φT0 01: φT2 10: φT8 11: φT32 −
0 0 0 Set frequency divisor 0000: 16 divisions 0001 to 1 to 15 divisions 1111 ODE63 ODE60 − R/W 0 0 0
ODE
Serial open drain enable
58H
0
(Note) Always write “0”.
1: P63 1: P60 open drain open drain
93CS32-167
2004-02-10
TMP93CS32
(8) AD converter control
Symbol
Name Address
7
EOCF R
6
ADBF 0 1: Busy
5
− 0 (Note) Always write “0”.
4
− 0
3
ITM0 R/W 0
0: Every
2
REPET 0
1
SCAN 0 0: Fixedchannel 1: Scan ADCH1 R/W 0
0
ADS 0 1: Start (Note) Always read “0”. ADCH0 0
ADMOD0
AD mode control register 0
0 5EH 1: End
0: Single conversion 1: Repeat
conversion
1: Every four
VREFON R/W
AD mode control register 1
ADTRGE 0
ADCH2 0
1 5FH 0: OFF 1: ON
ADMOD1
External Analog input channel selection trigger start control 0: Disable 1: Enable
*1)
ADR01 R 60H
ADR00
ADR0RF R 0
Conversion result stored flag
AD ADREG04L conversion result register 0/4 low AD conversion ADREG04H result register 0/4 high
*1)
Undefined Stores lower two bits of AD conversion result ADR09 ADR08 ADR07 ADR06 R Undefined Stores upper eight bits of AD conversion result ADR11 R ADR10 ADR05 ADR04 ADR03
ADR02
61H
ADR1RF R 0
Conversion result stored flag
AD ADREG15L conversion result register 1/5 low AD conversion ADREG15H result register 1/5 high
*1)
62H
Undefined Stores lower two bits of AD conversion result ADR19 ADR18 ADR17 ADR16 R Undefined Stores upper eight bits of AD conversion result ADR21 R ADR20 ADR15 ADR14 ADR13
ADR12
63H
ADR2RF R 0
Conversion result stored flag
AD ADREG2L conversion result register 2 low AD conversion ADREG2H result register 2 high
*1)
64H
Undefined Stores lower two bits of AD conversion result ADR29 ADR28 ADR27 ADR26 R Undefined Stores upper eight bits of AD conversion result ADR31 R ADR30 ADR25 ADR24 ADR23
ADR22
65H
ADR3RF R 0
Conversion result stored flag
AD ADREG3L conversion result register 3 low AD conversion ADREG3H result register 3 high
66H
Undefined Stores lower two bits of AD conversion result ADR39 ADR38 ADR37 ADR36 R Undefined Stores upper eight bits of AD conversion result ADR35 ADR34 ADR33
ADR32
67H
93CS32-168
2004-02-10
TMP93CS32
MSB 9 Converted data of channel x
8
7
6
5
4
3
2
1
LSB 0
ADREGxH 7 6
5
4
3
2
1
0
7
6
5
4
3
2
ADREGxL 1 0
This is 1 when this is read. *1: Data to be stored in AD Conversion Result Reg Low are the lower 2 bits of the conversion result. The contents of the 5 to 1 bits of this register are always read as “1”. Bit0 conversion result stored flag bit is set to “1” when the AD conversion result is stored. Reading either the ADREGxH or the ADREGxL registers clears to “0”.
(9) Watchdog timer
Symbol Name Address
7
WDTE 1
6
WDTP1 0 00: 2 /fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS
15
5
WDTP0 0
4
WARM 0 W arm-up time 0: 214/Inputted
frequency
3
HALTM1 R/W 0 HALT mode 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode −
2
HALTM0 0
1
RESCR 0
0
DRVE 0
Watchdog timer WDMOD mode control register
5CH
1: WDT enable
1: 216/Inputted
frequency
1: Connect 1: Drive internally the pin in STOP WDT out mode to reset pin
Watchdog timer WDCR control register
5DH B1H: WDT disable code
W − 4EH: WDT clear code
93CS32-169
2004-02-10
TMP93CS32
6.
Port Section Equivalent Circuit Diagram
• Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The dedicated signal is described below. STOP: This signal becomes active “1” when the HALT mode setting register is set to the STOP mode (WDMOD = 0, 1) and the CPU executes the HALT instruction. When the drive enable bit WDMOD is set to “1”, however, STOP remains at “0”. • The input protection resistance ranges from several tens of ohms to several hundreds of ohms. ■ P0 (AD0 to AD7), P1 (AD8 to AD15/A8 to A15), P4, and P7
VCC Output data P-ch
Output enable STOP N-ch
Input data
I/O
Input enable
■
P2 (A16 to A23/A0 to A7), P32, P61, P62, P64, and P65
VCC Output data P-ch
Output enable STOP N-ch
VCC P-ch
Programmable pull-up resistor
Input data
I/O
Input enable
93CS32-170
2004-02-10
TMP93CS32
■ P30 ( RD ) and P31 ( WR )
VCC Output data P-ch Output STOP N-ch
■
P35 (INT0)
VCC Output data P-ch
Output enable STOP N-ch
Input data Interrupt request signal Schmitt
I/O
■
P50 to P52 (AN0 to AN2), P54 (AN4), and P55 (AN5)
Analog input channel select P-ch Analog input N-ch input data Input
Input enable
■
P53 (AN3/ ADTRG )
Analog input channel select P-ch Analog input N-ch Input data Input
Input enable AD trigger STOP
93CS32-171
2004-02-10
TMP93CS32
■ P60 (TXD0) and P63 (TXD1)
VCC Output data P-ch
Open-drain output enable STOP
VCC N-ch P-ch
Programmable pull-up resistor
Input data
I/O
Input enable
■
NMI
NMI Schmitt Input
■
CLK
Output enable Internal CLK P-ch P-ch Output N-ch STOP VCC VCC
Internal reset Test circuit
Input enable
■
EA
Input data Input
■
AM8/ AM16
Input data Input
93CS32-172
2004-02-10
TMP93CS32
■ ALE
VCC Internal ALE P-ch Output N-ch
Output enable
■
RESET
VCC
Internal reset WDTOUT Reset enable Schmitt
Input
■
X1 and X2
Clock Oscillator X2 High-frequency oscillation enable P-ch N-ch
X1
■
VREFH and VREFL
VREFON P-ch VREFH
String resistance VREFL
93CS32-173
2004-02-10
TMP93CS32
7.
Points of Note and Restriction
(1) Notation 1. 2. Explanation of a built-in I/O register: register symbol e.g.) TRUN … Bit T0RUN of Register TRUN Read, modify and write instruction An instruction in which the CPU executes following by one instruction. 1. CPU reads data of the memory. 2. CPU modifies the data. 3. CPU writes the data to the same memory. ex1) ex2) • SET 3, (TRUN) … Set bit3 of TRUN INC 1, (100H) … Increment the data of 100H
A sample read, modify and write instructions using the TLCS-900 Exchange EX (mem), R Arithmetic operation ADD (mem), R/# SUB (mem), R/# INC #3, (mem) Logical operation AND (mem), R/# XOR (mem), R/# Bit manipulation STCF #3/A, (mem) RES #3, (mem) CHG #3, (mem) Rotate and shift RLC (mem) RL (mem) SLA (mem) SLL (mem) RLD (mem)
ADC SBC DEC OR
(mem), R/# (mem), R/# #3, (mem) (mem), R/#
SET TSET
#3, (mem) #3, (mem)
RRC RR SRA SRL RRD
(mem) (mem) (mem) (mem) (mem)
3.
fc, fFPH, fSYS, 1 state The clock frequency input from pins X1 and X2 is called fc. The clock frequency selected by SYSCR1 is called system clock fFPH, and the clock frequency given by fFPH divided by 2 is called fSYS. One cycle of fSYS is called 1 state.
93CS32-174
2004-02-10
TMP93CS32
(2) Care points 1. 2.
EA , AM8/ AM16 pin
Fix these pins VCC unless changing voltage. HALT mode (IDLE1) When IDLE1 mode (oscillator operation only) is used, clear TRUN to “0” to stop prescaler before “HALT” instruction is executed. 3. Warm-up counter The warm-up counter operates when STOP mode is released even if the system is using an external oscillator. As a result, it takes warm-up time from inputting the releasing request to outputting the system clock. 4. Programmable pull-up resistor The programmable pull-up resistors can be turned ON/OFF by the program when the ports are used as input ports. When the ports are used as outputs, they can not be selected ON/OFF by the program. The data registers (e.g. P6 register …) are used for the pull-up resistors ON/OFF. Consequently, Read-modify-write instructions are prohibited. 5. Watchdog timer The watchdog timer starts operation immediately after the reset is released. When the watchdog timer is not used, disable it. 6. AD converter The string register between VREFH and VREFL pins can be cut by a program to reduce power consumption. When the Standby mode is used, disable the resistor using the program before the “HALT” instruction is executed. 7. CPU (Micro DMA) Only the “LDC cr, r”, “LDC r, cr” instructions can be used to access the control registers in the CPU like the transfer source address register (DMASn). 8. 9. POP SR instruction Please execute POP SR instruction during DI condition. Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
93CS32-175
2004-02-10
TMP93CS32
8.
TMP93XX32 Different Points
Item
Built-in ROM Built-in RAM CS1 mapping area (WAITC1 = 00) CS2 mapping area (WAITC2 = 11)
TMP93CS32
64-Kbyte Mask ROM (FF0000H to FFFFFFH) 2-Kbyte (80H to 87FH) 880H to 7FFFH
TMP93PW32
128-Kbyte OTP (FE0000H to FFFFFFH) 4-Kbyte (80H to 107FH) 1080H to 7FFFH
C00000H to FEFFFFH
C00000H to FDFFFFH
93CS32-176
2004-02-10
TMP93CS32
9. Package Dimensions
P-QFP64-1414-0.80A Unit: mm
93CS32-177
2004-02-10
TMP93CS32
93CS32-178
2004-02-10
工商网监
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