TMP93CW40

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CW40/41 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2, RUN is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93CW40/TMP93CW41 Low Voltage/Low Power CMOS 16-Bit Microcontrollers TMP93CW40DF/TMP93CW41DF 1. Outline and Device Characteristics TMP93CW40/W41 are high-speed advanced 16-bit microcontrollers developed for controlling medium to large-scale equipment. The TMP93CW40/CW41 enable low-voltage and low consumption power operation. The TMP93CW40/W41 are housed in 100-pin flat package. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) • • • • • TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers and resister bank system 16-bit multiplication/division and bit transfer/arithmetic instructions High-speed micro DMA: 4 channels (1.6 µs/2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 4 Kbytes Internal ROM: TMP93CW40 TMP93CW41 128-Kbyte ROM None (4) External memory expansion • • • Can be expanded up to 16 Mbytes (for both programs and data). AM8/ AM16 pin (select the external data bus width) Can mix 8- and 16-bit external data buses. ... Dynamic data bus sizing (5) 8-bit timer: 2 channels (6) 8-bit PWM timer: 2 channels 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 93CW40-1 2004-02-10 TMP93CW40/TMP93CW41 (7) 16-bit timer: 2 channels (8) 4-bit pattern generator: 2 channels (9) Serial interface: 2 channels (10) 10-bit AD converter: 8 channels (11) Watchdog timer (12) Chip select/wait controller: 3 blocks (13) Interrupt functions: 29 • • • 9 CPU interrupts ... SWI instruction, and Illegal instruction 14 internal interrupts 6 external interrupts 7-level priority can be set. (14) I/O ports 79 pins for TMP93CW40 and 61 pins for TMP93CW41 (15) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (16) Clock gear function • • Dual clock operation Clock gear: High-frequency clock can be changed fc to fc/16. (17) Wide operating voltage • VCC = 2.7 to 5.5 V (18) Package Type No. TMP93CW40DF TMP93CW41DF Package P-LQFP100-1414-0.50F 93CW40-2 2004-02-10 TMP93CW40/TMP93CW41 PA0 to PA6 PA7 (SCOUT) P50 to P57 (AN0 to AN7) AVCC AVSS VREFH VREFL (TXD0) P90 (RXD0) P91 (SCLK0/ CTS0 ) P92 (TXD1) P93 (RXD1) P94 (SCLK1) P95 (PG 00) P60 (PG 01) P61 (PG 02) P62 (PG 03) P63 (PG 10) P64 (PG 11) P65 (PG 12) P66 (PG 13) P67 (TI0) P70 Port A 900L CPU 10-bit 8-channel AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits F SR PC Interrupt controller Watchdog timer 4-Kbyte RAM Port 0 Highfrequency OSC Lowfrequency OSC VCC [3] VSS [3] X1 X2 CLK XT1 XT2 AM8/ AM16 EA RESET Serial I/O (Channel 0) Serial I/O (Channel 1) ALE TEST1 TEST2 P87 (INT0) NMI WDTOUT Pattern generator (Channel 0) Pattern generator (Channel 1) 8-bit timer (Timer 0) 8-bit timer (Timer 1) P00 to P07 (AD0 to AD7) P10 to P17 (AD8 to AD15/A8 to A15) P20 to P27 (A0 to A7/A16 to A23) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P33 ( WAIT ) P34 ( BUSRQ ) P35 ( BUSAK ) P36 ( R / W ) P37 ( RAS ) Port 1 (TO1) P71 Port 2 (TO2) P72 8-bit PWM (Timer 2) 8-bit PWM (Timer 3) 128-Kbyte ROM (TO3) P73 Port 3 (INT4/TI4) P80 (INT5/TI5) P81 (TO4) P82 (TO5) P83 (INT6/TI6) P84 (INT7/TI7) P85 (TO6) P86 16-bit timer (Timer 4) 16-bit timer (Timer 5) Can not be used in the TMP93CW41 CS/WAIT controller (3-block) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 ) Figure 1.1 TMP93CW40/TMP93CW41 Block Diagram 93CW40-3 2004-02-10 TMP93CW40/TMP93CW41 2. Pin Assignment and Functions The assignment of input/output pins for TMP93CW40/41, their name and outline functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of TMP93CW40DF/W41DF. ○ ○ 88 P65/PG11 P66/PG12 P67/PG13 VSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC NMI 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 87 P64/PG10 86 P63/PG03 85 P62/PG02 84 P61/PG01 83 P60/PG00 82 P42/ CS2 / CAS2 81 P41/ CS1 / CAS1 80 P40/ CS0 / CAS0 79 P37/ RAS 78 P36/ R / W 77 P35/ BUSAK 76 P34/ BUSRQ 75 P33/ WAIT 74 P32/ HWR 73 P31/ WR 72 P30/ RD 71 P27/A7/A23 70 P26/A6/A22 69 P25/A5/A21 68 P24/A4/A20 67 66 65 64 63 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 VCC ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ADC SIO ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ P70//TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/TXD0 P91/RXD0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/ AM16 CLK VCC VSS Timer Top view LQFP100 62 VSS 61 WDTOUT 60 P17/AD15/A15 59 P16/AD14/A14 58 P15/AD13/A13 57 P14/AD12/A12 56 P13/AD11/A11 55 P12/AD10/A10 54 P11/AD9/A9 53 P10/AD8/A8 52 P07/AD7 51 P06/AD6 50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3 P92/ CTS0 /SCLK0 19 Clock, Mode X1 X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2 Note: Because the TMP93CW41 does not have an internal ROM, P00 to P17 pins are fixed to AD0 to AD15 (the case of AM8/ AM16 = 0), or to AD0 to AD7, A8 to A15 (the case of AM8/ AM16 = 1); P30 to RD ; and P31 to WR . Figure 2.1.1 Pin Assignment (100-Pin LQFP) 93CW40-4 2004-02-10 Memory interface Stepping motor control Programmable Pull Pull up down TMP93CW40 Pin no. Pin no. TMP93CW40 Programmable Pull Pull down up TMP93CW40/TMP93CW41 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.4 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/4) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O 3-state I/O 3-state Output I/O Output Output Functions Port 0: I/O port that allows I/O to be selected on a bit basis Address/Data (lower) : 0 to 7 for address/data bus Port 1: I/O port that allows I/O to be selected on a bit basis Address data (upper) : 8 to 15 for address/data bus Address: 8 to 15 for address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor) Address: 0 to 7 for address bus Address: 16 to 23 for address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 34: I/O port (with pull-up resistor) Bus request: Signal used to request high impedance for AD0 to AD15, A0 to A23, RD , WR , HWR , R / W , RAS , CS0 , CS1 , and CS2 pins. (For external DMAC) Port 35: I/O port (with pull-up resistor) Bus acknowledge: Signal indicating that AD0 to AD15, A0 to A23, RD , WR , HWR , R / W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after receiving BUSRQ. (For external DMAC) Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents read or dummy cycle; 0, write cycle. Port 37: I/O port (with pull-up resistor) Row address strobe: Outputs RAS strobe for DRAM. Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area. 8 1 1 1 1 1 Output Output Output Output I/O Output I/O Input I/O Input P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK 1 I/O Output P36 R/ W P37 RAS 1 1 1 I/O Output I/O Output I/O Output Output P40 CS0 CAS0 Note: With the external DMA controller, this device’s built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins. 93CW40-5 2004-02-10 TMP93CW40/TMP93CW41 Table 2.2.2 Pin Names and Functions (2/4) Pin Name P41 CS1 CAS1 Number of Pins 1 I/O I/O Output Output I/O Output Output Input Input Input Input I/O Output Functions Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. Port 42: I/O port (with pull-down resistor) Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area. Port 5: Input port Analog input: Input to AD converter Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Ports 60 to 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor) Pattern generator ports: 00 to 03 Ports 64 to 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor) Pattern generator ports: 10 to 13 Port 70: I/O port (with pull-up resistor) Timer input 0: Timer 0 input Port 71: I/O port (with pull-up resistor) Timer output 1: Timer 0 or 1 output Port 72: I/O port (with pull-up resistor) PWM output 2: 8-bit PWM timer 2 output Port 73: I/O port (with pull-up resistor) PWM output 3: 8-bit PWM timer 3 output Port 80: I/O port (with pull-up resistor) Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 81: I/O port (with pull-up resistor) Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 82: I/O port (with pull-up resistor) Timer output 4: Timer 4 output pin Port 83: I/O port (with pull-up resistor) Timer output 5: Timer 4 output pin P42 CS2 CAS2 1 P50 to P57 AN0 to AN7 VREFH VREFL P60 to P63 PG00 to PG03 P64 to P67 PG10 to PG13 P70 TI0 P71 TO1 P72 TO2 P73 TO3 P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 8 1 1 4 4 I/O Output 1 1 1 1 1 I/O Input I/O Output I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output 1 1 1 93CW40-6 2004-02-10 TMP93CW40/TMP93CW41 Table 2.2.3 Pin Names and Functions (3/4) Pin Name P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 TXD0 P91 RXD0 P92 CTS0 Number of Pins 1 I/O I/O Input Input I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O Output Output Input Output Functions Port 84: I/O port (with pull-up resistor) Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 85: I/O port (with pull-up resistor) Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 86: I/O port (with pull-up resistor) Timer output 6: Timer 5 output pin Port 87: I/O port (with pull-up resistor) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 90: I/O port (with pull-up resistor) Serial send data 0 Port 91: I/O port (with pull-up resistor) Serial receive data 0 Port 92: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to Send) Serial Clock I/O 0 Port 93: I/O port (with pull-up resistor) Serial send data 1 Port 94: I/O port (with pull-up resistor) Serial receive data 1 Port 95: I/O port (with pull-up resistor) Serial clock I/O 1 Port A: I/O ports Port A7: I/O port System Clock Output: Outputs system clock or 1/2 oscillation clock for synchronizing to external circuit. Watchdog timer output pin Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Clock output: Outputs [System Clock ÷ 2] Clock. Pulled-up during reset. Can be set to Output Disable for reducing noise. 1 1 1 1 1 1 SCLK0 P93 TXD1 P94 RXD1 P95 SCLK1 PA0 to PA6 PA7 SCOUT WDTOUT NMI 1 1 1 7 1 1 1 1 CLK EA 1 Input External access: “0” should be inputted with TMP93CW41. “1” should be inputted with TMP93CW40. 93CW40-7 2004-02-10 TMP93CW40/TMP93CW41 Table 2.2.4 Pin Names and Functions (4/4) Pin Name AM8/ AM16 Number of Pins 1 I/O Input Functions Address Mode: Selects external data bus width. (The case of TMP93CW40) “1” should be inputted. The data bus width for external access is set by chip select/wait control register, Port 1 control register. (The case of TMP93CW41) “0” should be inputted with fixed 16-bit bus width or 16-bit bus interlarded with 8-bit bus. “1” should be inputted with fixed 8-bit bus width. Address latch enable Can be set to output disable for reducing noise. Reset: initializes LSI. (with pull-up resistor) High-frequency oscillator connecting pin Low-frequency oscillator connecting pin Port 96: I/O port (open-drain output) Low-frequency oscillator connecting pin Port 97: I/O port (open-drain output) TEST1 Should be connected with TEST2 pin. Do not connect to any other pins Power supply pin GND pin (0 V) Power supply pin for AD converter GND pin for AD converter (0 V) ALE RESET 1 1 2 1 1 Output Input Input/Output Input I/O Output I/O Output/Input X1/X2 XT1 P96 XT2 P97 TEST1/TEST2 VCC VSS AVCC AVSS 2 3 3 1 1 Note: Pull-up/pull-down resistor can be released from the pin by software. 93CW40-8 2004-02-10 TMP93CW40/TMP93CW41 3. Operation This section describes in blocks the functions and basic operations of the TMP93CW40/W41 devices. 3.1 CPU The TMP93CW40/W41 devices have a built-in high-performance 16-bit CPU (900/L_CPU). (For CPU operation, see TLCS-900/L CPU in the previous section). 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CW40/W41. 000000H 000080H 000100H 001080H Internal I/O (128 bytes) 256-byte area (n) Internal RAM (4 Kbytes) External memory 64-Kbyte area (nn) 008000H 008100H Interrupt vector table area (64 entries × 4 bytes) External area 128-Kbyte internal ROM (TMP93CW40) External memory (TMP93CW41) 010000H 028000H External memory 16-Mbyte area (R) (−R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Reserved (256 bytes) ( = Internal area) Note: Resetting sets the stack pointer (XSP) to 100H. The 256-byte area from FFFF00H to FFFFFFH can not be used. Figure 3.2.1 Memory Map 93CW40-9 2004-02-10 TMP93CW40/TMP93CW41 4. 4.1 Electrical Characteristics Maximum Ratings (TMP93CW40F, TMP93CW41DF) Parameter Power supply voltage Input voltage Output current (total) Output current (total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature “X” used in an expression shows a frequency of clock fFPH selected by SYSCR1. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value in an example is calculated at fc, gear = 1/fc (SYSCR1 < SYSCK, GEAR2:0 > = “0000”). Symbol VCC VIN ΣIOL ΣIOH PD TSOLDER TSTG TOPR Rating −0.5 to 6.5 −0.5 to VCC + 0.5 120 −80 600 260 −65 to 150 −40 to 85 Unit V V mA mA mW °C °C °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Ta = −40 to 85°C Parameter Power supply voltage AVCC = VCC AVCC = VSS = 0 V AD0 to AD15 Input low voltage Port 2 to port A (except P87) RESET , NMI , INT0 EA , AM8/ AM16 Symbol VCC Condition fc = 4 to 20 MHz fc = 4 to 12.5 MHz VCC ≥ 4.5 V VCC < 4.5 V fs = 30 to 34 kHz Min 4.5 Typ. (Note) Max 5.5 Unit V 2.7 0.8 0.6 −0.3 0.3 VCC 0.25 VCC 0.3 0.2 VCC VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH1 VCC = 2.7 to 5.5 V X1 AD0 to AD15 Input high voltage Port 2 to port A (except P87) RESET , NMI , INT0 EA , AM8/ AM16 VCC ≥ 4.5 V VCC < 4.5 V 2.2 2.0 0.7 VCC VCC + 0.3 V VCC = 2.7 to 5.5 V 0.75 VCC VCC − 0.3 0.8 VCC X1 Output low voltage IOL = 1.6 mA (VCC = 2.7 to 5.5 V) IOH = −400 µA (VCC = 3 V ± 10%) IOH = −400 µA (VCC = 5 V ± 10%) 2.4 4.2 0.45 V Output high voltage VOH2 Note: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. 93CW40-10 2004-02-10 TMP93CW40/TMP93CW41 DC Characteristics (2/2) Parameter Darlington drive current (8 output pins max) Input leakage current Output leakage current Powerdown voltage (at Stop, RAM Back-up) RESET pull-up resistor Symbol IDAR (Note 2) ILI ILO VSTOP RRST CIO VTH RKL RKH Condition VEXT = 1.5 V REXT = 1.1 kΩ (when VCC = 5 V ± 10%) 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 VIL2 = 0.2 VCC, VIH2 = 0.8 VCC VCC = 5 V ± 10% VCC = 3 V ± 10% fc = 1 MHz Min −1.0 Typ. (Note1) Max −3.5 Unit mA 0.02 0.05 2.0 50 80 ±5 ±10 6.0 150 200 10 µA V kΩ pF V Pin capacitance Schmitt width RESET , NMI , INT0 Programmable pull-down resistor Programmable pull-up resistor NORMAL (Note 3) NORMAL2 (Note 4) RUN IDLE2 IDLE1 NORMAL (Note 3) NORMAL2 (Note 4) RUN IDLE2 IDLE1 SLOW (Note 3) RUN IDLE2 IDLE1 0.4 VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% fc = 20 MHz 10 30 50 100 1.0 80 150 150 300 19 24 17 10 3.5 25 30 25 15 5 10 13 9 5 1.5 45 40 30 25 10 0.2 20 50 kΩ mA VCC = 3 V ± 10% fc = 12.5 MHz (Typ: VCC = 3.0 V) ICC VCC = 3 V ± 10% fs = 32.768 kHz (Typ: VCC = 3.0 V) Ta ≤ 50°C 6.5 9.5 5.0 3.0 0.8 20 16 10 5 mA µA STOP Ta ≤ 70°C Ta ≤ 85°C µA Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise Noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: The condition of measurement of ICC (NORMAL/SLOW). Only CPU operates. Output ports are open and Input ports fixed. Note 4: The condition of measurement of ICC (NORMAL2). CPU and all peripherals operate. Output ports are open and input ports fixed. 93CW40-11 2004-02-10 TMP93CW40/TMP93CW41 4.3 AC Characteristics (1) VCC = 5 V ± 10% No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Parameter Osc. period ( = x) CLK pulse width A0 to A23 valid → CLK hold CLK valid → A0 to A23 hold A0 to A15 valid → ALE fall ALE fall → A0 to A15 hold ALE high pulse width ALE fall → RD / WR fall RD / WR rise → ALE rise Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode Variable Min 50 2x − 40 0.5x − 20 1.5x − 70 0.5x − 15 0.5x − 20 x − 40 0.5x − 25 0.5x − 20 x − 25 1.5x − 50 0.5x − 25 3.0x − 55 3.5x − 65 2.0x − 60 2.0x − 40 0 x − 15 2.0x − 40 2.0x − 55 0.5x − 15 3.5x − 90 3.0x − 80 2.0x + 0 2.5x − 120 2.5x + 50 200 1.0x − 40 0.5x − 15 2.5x − 70 0.5x − 15 2.0x − 40 2.0x − 40 1.0x − 40 0.5x − 25 1.0x − 40 1.5x − 65 1.5x − 30 16 MHz Min 62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65 85 0 48 85 70 16 129 108 125 36 206 200 23 16 86 16 85 85 23 6 23 29 64 20 MHz Min 50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70 100 5 175 200 10 10 55 10 60 60 10 0 10 10 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max 31250 Max Max A0 to A15 valid → RD / WR fall A0 to A23 valid → RD / WR fall RD / WR rise → A0 to A23 hold A0 to A15 valid → D0 to D15 input A0 to A23 valid → D0 to D15 input RD fall → D0 to D15 input RD low pulse width RD rise → D0 to D15 hold RD rise → A0 to A15 output WR low pulse width D0 to D15 valid → WR rise WR rise → D0 to D15 hold A0 to A23 valid → WAIT input A0 to A15 valid → WAIT input RD / WR fall → WAIT hold tAWH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS A0 to A23 valid → Port input A0 to A23 valid → Port hold WR rise → Port valid A0 to A23 valid → RAS fall A0 to A15 valid → RAS fall RAS fall → D0 to D15 input RAS fall → A0 to A15 hold RAS low pulse width RAS high pulse width CAS fall → RAS rise RAS rise → CAS rise RAS fall → CAS fall CAS fall → D0 to D15 input CAS low pulse width AC measuring conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R/ W , CLK, RAS , CAS0 to CAS2 ) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (Except for AD0 to AD15) 93CW40-12 2004-02-10 TMP93CW40/TMP93CW41 (2) VCC = 3 V ± 10% No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Parameter Osc. period ( = x) CLK pulse width A0 to A23 valid → CLK hold CLK valid → A0 to A23 hold A0 to A15 valid → ALE fall ALE fall → A0 to A15 hold ALE high pulse width ALE fall → RD / WR fall RD / WR rise → ALE rise Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode Variable Min 80 2x − 40 0.5x − 30 1.5x − 80 0.5x − 35 0.5x − 35 x − 60 0.5x − 35 0.5x − 40 x − 50 1.5x − 50 0.5x − 40 3.0x − 110 3.5x − 125 2.0x − 115 2.0x − 40 0 x − 25 2.0x − 40 2.0x − 120 0.5x − 40 3.5x − 130 3.0x − 100 2.0x + 0 2.5x − 195 2.5x + 50 200 1.0x − 60 0.5x − 40 2.5x − 90 0.5x − 25 2.0x − 40 2.0x − 40 1.0x − 55 0.5x − 25 1.0x − 40 1.5x − 120 1.5x − 40 12.5 MHz Min 80 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 5 250 200 20 0 110 15 120 120 25 15 40 0 80 Max 31250 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns A0 to A15 valid → RD / WR fall A0 to A23 valid → RD / WR fall RD / WR rise → A0 to A23 hold A0 to A15 valid → D0 to D15 input A0 to A23 valid → D0 to D15 input RD fall → D0 to D15 input RD low pulse width RD rise → D0 to D15 hold RD rise → A0 to A15 output WR low pulse width D0 to D15 valid → WR rise WR rise → D0 to D15 hold A0 to A23 valid → WAIT input A0 to A15 valid → WAIT input RD / WR fall → WAIT hold tAWH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS A0 to A23 valid → Port input A0 to A23 valid → Port hold WR rise → Port valid A0 to A23 valid → RAS fall A0 to A15 valid → RAS fall RAS fall → D0 to D15 input RAS fall → A0 to A15 hold RAS low pulse width RAS high pulse width CAS fall → RAS rise RAS rise → CAS rise RAS fall → CAS fall CAS fall → D0 to D15 input CAS low pulse width AC measuring conditions • • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF Input level: High 0.9 × VCC/Low 0.1 × VCC 93CW40-13 2004-02-10 TMP93CW40/TMP93CW41 (1) Read cycle tOSC X1 tCLK CLK tAK A0 to A23 tKA CS0 to CS2 R/W tAWH tAWL tCW WAIT tAPH tAPH2 Port input (Note) tASRH tRSH RAS tRP tRAS tASRL tRAH tRCD tADH tRAC tCAS tCAC tRSC CAS0 to CAS2 tCA tRR tRAE tHR D0 to D15 tCL RD tACH tACL tLC tRD tADL AD0 to AD15 tAL ALE tLL A0 to A15 tLA Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93CW40-14 2004-02-10 TMP93CW40/TMP93CW41 (2) Write cycle X1 CLK A0 to A23 CS0 to CS2 R/W WAIT Port output (Note) tCP RAS CAS0 to CAS2 WR , HWR tWW tDW AD0 to AD15 A0 to A15 D0 to D15 tWD ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93CW40-15 2004-02-10 TMP93CW40/TMP93CW41 4.4 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Analog reference voltage (+) Analog reference voltage (−) Analog input voltage range Analog current for analog reference voltage Symbol VREFH VREFL VAIN IREF (VREFL = 0 V) – 10 Power Supply VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 2.7 to 5.5 V VCC = 5 V ± 10% VCC = 3 V ± 10% Min VCC − 1.5 V VCC − 0.2 V VSS VSS VREFL Typ. VCC VCC VSS VSS 0.5 0.3 0.02 ±1.0 ±1.0 Max VCC VCC VSS + 0.2 V VSS + 0.2 V VREFH 1.5 0.9 5.0 ±3.0 ±3.0 Unit V = 1 = 0 Error (excluding quantizing error) mA µA LSB Note 1: 1LSB = (VREFH − VREFL) /2 [V] Note 2: Minimum operation frequency The operation of the AD converter is guaranteed only when fc (high-frequency oscillator) is used. (It is not guaranteed when fs is used.) Additionally, it is guaranteed when the clock frequency which is selected by the clock gear is 4 MHz or more. Note 3: The value ICC includes the current which flows through the AVCC pin. 93CW40-16 2004-02-10 TMP93CW40/TMP93CW41 4.5 Serial Channel Timing (1) I/O interface mode a. SCLK input mode Variable Symbol Parameter 32.768 kHz (Note) Max Min 488 µs 91.5 12.5 MHz Min 1280 20 MHz Min 800 Unit Min SCLK cycle Output data tSCY tOSS 16X tSCY/2 − 5X − 50 5x − 100 Max Max Max ns → R ising edge or falling edge (Note 2) of SCLK SCLK rising edge or falling edge (Note 2) µs 152 µs 190 100 ns → O utput data hold SCLK rising edge or falling edge (Note 2) tOHS tHSR tSRD 300 150 ns → Input data hold SCLK rising edge or falling edge (Note 2) 0 tSCY − 5X − 100 0 336 µs 0 0 ns → Effective data input 780 450 ns Note 1: When fs is used as system clock (fSYS) or fs is used as input clock to prescaler. Note 2: SCLK rising/falling timing ... SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. b. SCLK output mode Variable Symbol Parameter 32.768 kHz (Note) Max 8192x 12.5 MHz Min 1.28 970 80 0 20 MHz Min 0.8 550 20 0 Unit Min SCLK cycle (programmable) Output data → SCLK rising edge SCLK rising edge → Output data hold SCLK rising edge → Input data hold SCLK rising edge → Effective data input tSCY tOSS tOHS tHSR tSRD 16x tSCY − 2x − 150 2x − 80 0 Min 488 427 µs 60 µs 0 Max 250 ms Max 655.36 Max 409.6 µs ns ns ns tSCY − 2x − 150 428 µs 970 550 ns Note: When fs is used as system clock (fSYS) or fs is used as input clock to prescaler. tSCY SCLK Output mode/ Input rising mode SCLK (Input falling mode) tOSS 0 tOHS 1 tSRD tHSR 1 Valid 2 Valid 3 Valid 2 3 Output data TxD Input data RxD 0 Valid 93CW40-17 2004-02-10 TMP93CW40/TMP93CW41 4.6 Timer/Counter Input Clock (TI0, TI4, TI5, TI6 and TI7) Parameter Variable Symbol 12.5 MHz Max Min 740 360 360 20 MHz Min 500 240 240 Unit ns ns ns Min Clock cycle Low level clock pulse width High level clock pulse width tVCK tVCKL tVCKH 8X + 100 4X + 40 4X + 40 Max Max 4.7 Interrupt and Capture (1) NMI , INT0 interrupts Parameter Variable Symbol 12.5 MHz Max Min 320 320 20 MHz Min 200 200 Unit ns ns Min NMI , INT0 low level pulse width NMI , INT0 high level pulse width Max Max tINTAL tINTAH 4X 4X (2) INT4 to 7 interrupts, capture Input pulse width of INT4 to 7 depends on the operation clock of CPU and Timer (9-bit prescaler). The following shows the pulse width in each clock. System Clock Prescaler Clock tINTBL (INT4 to 7 low level pulse width) tINTBH (INT4 to 7 high level pulse width) Selected Selected Variable 20 MHz Variable 20 MHz Min Min Min Min 00 (fFPH) 0 (fc) 1 (fs) (Note 2) 01 (fs) 10 (fc/16) 00 (fFPH) 01 (fs) 8X + 100 8XT + 0.1 128X + 0.1 8XT + 0.1 500 244.3 6.5 244.3 8X + 100 8XT + 0.1 128X + 0.1 8XT + 0.1 500 244.3 6.5 244.3 µs Unit ns Note 1: XT represents the cycle of the low frequency clock fs. Calculated at fs = 32.768 kHz. Note 2: When fs is used as the system clock, fc/16 can not be selected for the prescaler clock. 4.8 SCOUT pin AC characteristics Parameter Variable Symbol 12.5 MHz Max Min 30 20 30 20 20 MHz Min 15 − 15 − − − Unit ns ns Min High-level pulse width Low-level pulse width VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10% tSCH tSCL 0.5X − 10 0.5X − 20 0.5X − 10 0.5X − 20 Max Max Measurement condition • Output level: High 2.2 V/Low 0.8 V, CL = 10 pF tSCH tSCL SCOUT 93CW40-18 2004-02-10 TMP93CW40/TMP93CW41 4.9 Timing Chart for Bus Request ( BUSRQ )/Bus Acknowledge ( BUSAK ) (Note 1) CLK tBRC BUSRQ tBRC tCBAL tCBAH BUSAK tBAA AD0 to AD15, A0 to A23, CS0 to CS2 , R/ W , RAS , CAS0 to CAS2 tABA (Note 2) (Note 2) RD , WR , HWR ALE Parameter BUSRQ set-up time to CLK Variable Symbol 12.5 MHz Min 120 20 MHz Min 120 Min 120 Max 1.5x + 120 0.5x + 40 Max 240 80 Max 195 65 Unit ns ns ns ns ns tBRC tCBAL tCBAH tABA tBAA CLK → BUSAK falling edge CLK → BUSAK rising edge Output buffer off to BUSAK BUSAK 0 0 80 80 0 0 80 80 0 0 80 80 to output buffer on Note 1: The Bus will be released after the WAIT request is inactive, when the BUSRQ is set to “0” during “Wait” cycle. Note 2: This line only shows the output buffer is off-state. It doesn’t indicate the signal level is fixed. Just after the bus is released, the signal level which is set before the bus is released is kept dynamically by the external capacitance. Therefore, to fix the signal level by an external resistor during bus releasing, designing is executed carefully because the level-fix will be delayed. The internal programmable pull-up/pull-down resistor is switched active/non-active by an internal signal. 93CW40-19 2004-02-10 TMP93CW40/TMP93CW41 5. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 93CW40-20 2004-02-10