TMP93CW44

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CW44 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93CW44 Low Voltage/Low Power CMOS 16-Bit Microcontroller TMP93CW44DF 1. Outline and Device Characteristics The TMP93CW44 are high speed, advanced 16-bit microcontroller developed for controlling medium to large-scale equipment. The TMP93CW44DF are housed in 80-pin flat package (P-QFP80-1420-0.80B). The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) • • • • • TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions Micro DMA:4 channels (1.6 µs per 2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 4 Kbytes Internal ROM: 128 Kbytes (4) External memory expansion • • • Can be expanded up to 16 Mbytes (for both programs and data) AM8/ AM16 pin (Select the external data bus width) Can mix 8- and 16- bit external data buses (Dynamic bus sizing) (5) 8-bit timer: 4 channels (6) 16-bit timer: 2 channels (7) Serial interface: 2 channels 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93CW44-1 2004-02-10 TMP93CW44 (8) Serial bus interface: 1 channel • I2C bus mode/clocked-synchronous 8-bit serial interface mode (9) 10-bit AD converter: 8 channels (10) High current output: 8 ports (11) Watchdog timer (12) Bus width/wait controller: 3 blocks (13) Interrupt functions: 33 • • • 9 CPU interrupts 17 internal interrupts 7 external interrupts 7-level priority can be set (except NMI and INTWD). (14) I/O ports: 62 pins (15) Standby function • • • • 4 HALT modes (RUN, IDLE2, IDLE1, STOP) Dual clock operation High-frequency clock can be changed from fc to fc/16. VCC = 2.7 to 5.5 V (The operation voltage of TMP93PW44A which is OTP product is VCC = 4.5 to 5.5 V.) P-QFP80-1420-0.80B (16) Clock gear function (17) Wide range of operating voltage (18) Package • 93CW44-2 2004-02-10 TMP93CW44 AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4 to AN7 (P54 to P57) AVCC AVSS VREFH VREFL 900/L CPU 10-bit 8-ch AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Interrupt controller F Highfrequency OSC VCC [2] VSS [2] X1 X2 CLK Lowfrequency OSC XT1 (P66) XT2 (P67) AM8/ AM16 EA RESET TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65) Serial I/O (Channel 0) Serial I/O (Channel 1) ALE TEST1/TEST2 INT0 (P35) NMI WAIT (P70) P71 P72 P73 P74 P75 P76 P77 TI0/INT1 (P40) Port 7 Watchdog timer 4-Kbyte RAM Port 0 AD0 to AD7 (P00 to P07) 8-bit timer (Timer 0) 8-bit timer (Timer 1) 8-bit timer (Timer 2) Port 1 AD8 to AD15/A8 to A15 (P10 to P17) Port 2 A0 to A7/A16 to A23 (P20 to P27) RD (P30) WR (P31) HWR /SCK (P32) TO3 (P41) 8-bit timer (Timer 3) 128-Kbyte ROM Port 3 INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (Timer 4) 16-bit timer (Timer 5) Wait controller (3 blocks) Serial bus interface controller SO/SDA (P33) SI/SCL (P34) Note: The items in parentheses ( ) are the initial setting after reset. Figure 1.1 TMP93CW44 Block Diagram 93CW44-3 2004-02-10 TMP93CW44 2. Pin Assignment and Functions The assignment of input and output pins for the TMP93CW44, their names and functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93CW44DF. P40 (TI0/INT1) P35 (INT0) P34 (SI/SCL) P33 (SO/SDA) P32 (HWR/SCK) P31(WR) P30 (RD) VCC P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12) P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) 64 60 55 50 45 (TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54 65 41 40 70 TMP93CW44DF QFP80 Top view 35 75 30 P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC TEST2 TEST1 P67 (XT2) P66 (XT1) RESET 80 10 15 20 24 EA 25 1 5 NMI Figure 2.1.1 Pin Assignment (P-QFP80-1420-0.80B) (TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS P72 P73 P74 P75 P76 P77 CLK AM8/AM16 X1 X2 (AN5) P55 (AN6) P56 (AN7) P57 93CW44-4 2004-02-10 TMP93CW44 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/3) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to D15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O Functions I/O Port 0: I/O port that allows selection of I/O on a bit basis 3-state Address/data (Lower): Bits 0 to 7 for address/data bus I/O Port 1: I/O port that allows selection of I/O on a bit basis 3-state Address/data (Upper): Bits 8 to 15 for address/data bus Output Address: Bits 8 to 15 for address bus 8 I/O Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Output Address: Bits 0 to 7 for address bus Output Address: Bits 16 to 23 for address bus 1 1 1 Output Port 30: Output port Output Read: Strobe signal for reading external memory Output Port 31: Output port Output Write: Strobe signal for writing data on pins AD0 to AD7 I/O Port 32: I/O port (with pull-up resistor) Output High write: Strobe signal for writing data on pins AD8 to AD15 I/O Mode clock SBI SIO mode clock P31 WR P32 HWR SCK P33 SO SDA P34 SI SCL P35 INT0 P40 TI0 INT1 P41 TO3 P42 TI4 INT4 1 I/O Port 33: I/O port Output Serial send data I/O SBI I2C bus mode channel data 1 I/O Port 34: I/O port Input Serial receive data I/O SBI I2C bus mode clock 1 I/O Port 35: I/O port Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge 1 I/O Port 40: I/O port Input Timer input 0: Timer 0 input Input Interrupt request pin 1: Interrupt request pin with rising edge 1 1 I/O Port 41: I/O port Output Timer output 3: 8-bit timer 3 output I/O Port 42: I/O port Input Timer input 4: Timer 4 input Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge 93CW44-5 2004-02-10 TMP93CW44 Table 2.2.2 Pin Names and Functions (2/3) Pin Name P43 TI5 INT5 P44 TO4 P45 TI6 INT6 P46 TI7 INT7 P47 TO6 P50 to P52, P54 to P57 AN0 to AN2, AN4 to AN7 P53 AN3 ADTRG Number of Pins 1 I/O I/O Port 43: I/O port Input Timer input 5: Timer 4 input Functions Input Interrupt request pin 5: Interrupt request pin with rising edge 1 1 I/O Port 44: I/O port Output Timer output 4: Timer 4 output I/O Port 45: I/O port Input Timer input 6: Timer 5 input Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge 1 I/O Port 46: I/O port Input Timer input 7: Timer 5 input Input Interrupt request pin 7: Interrupt request pin with rising edge 1 7 I/O Port 47: I/O port Output Timer output 6: Timer 5 output pin Input Port 50 to port 52, port 54 to port 57: Input port Input Analog input: Analog signal input for AD converter 1 Input Port 53: Input port Input Analog input: Analog signal input for AD converter Input AD converter external start trigger input 1 1 1 I/O Port 60: I/O port (with pull-up resistor) Output Serial send data 0 I/O Port 61: I/O port (with pull-up resistor) Input Serial receive data 0 I/O Port 62: I/O port (with pull-up resistor) I/O Serial Clock I/O 0 Input Serial data send enable 0 (Clear to send) 1 1 1 I/O Port 63: I/O port (with pull-up resistor) Output Serial send data 1 I/O Port 64: I/O port (with pull-up resistor) Input Serial receive data 1 I/O Port 65: I/O port (with pull-up resistor) I/O Serial clock I/O 1 Input Serial data send enable 1 (Clear to send) 1 1 I/O Port 66: I/O port (Open-drain output) Input Low-frequency oscillator connecting pin I/O Port 67: I/O port (Open-drain output) Output Low-frequency oscillator connecting pin P60 TXD0 P61 RXD0 P62 SCLK0 CTS0 P63 TXD1 P64 RXD1 P65 SCLK1 CTS1 P66 XT1 P67 XT2 93CW44-6 2004-02-10 TMP93CW44 Table 2.2.3 Pin Names and Functions (3/3) Pin Name P70 WAIT Number of Pins 1 I/O I/O Functions Port 70: I/O port (High current output available) Input WAIT: Pin used to request CPU bus wait (It is active in (1 + N) WAIT mode. Set by the bus-width/wait control register.) 7 1 1 1 1 1 1 1 1 1 1 I/O Port 71 to port 77: I/O port (High current output available) Input Power supply pin for AD converter Input GND pin for AD converter (0 V) Input Pin for high level reference voltage input to AD converter Input Pin for low level reference voltage input to AD converter Input Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. Input High-frequency oscillator connecting pin Output High-frequency oscillator connecting pin Input Reset: Initializes TMP93CW44 (with pull-up resistor). Output Address latch enable Can be disabled for reducing noise. Output Clock output: Outputs “fSYS ÷ 2” clock. Pulled-up during reset. Can be disabled for reducing noise. Input External access: “1” should be inputted with TMP93CW44. Input Address mode: Selects external data bus width. “1” should be inputted. The data bus width for external access is set by chip select/WAIT control register, port 1 control register. Input Power supply pin (All VCC pins should be connected with GND (0 V)). Input GND pin (0 V) (All VSS pins should be connected with GND (0 V)). Output/Input TEST1 Should be connected with TEST2 pin. Do not connect to any other pins. P71 to P77 AVCC AVSS VREFH VREFL NMI X1 X2 RESET ALE CLK EA 1 1 AM8/ AM16 VCC VSS TEST1 TEST2 2 2 2 Note: Built-in pull-up resistors can be released from the pins other than the RESET pin by software. 93CW44-7 2004-02-10 TMP93CW44 3. 3.1 Operation This section describes the functions and basic operational blocks of TMP93CW44 devices. CPU TMP93CW44 devices have a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous section.) 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CW44. 000000H 000080H 000100H Internal RAM (4 Kbytes) 001080H Internal I/O (128 bytes) 256-byte direct area (n) 64-Kbyte area (nn) External memory 010000H FE0000H 16-Mbyte area (r32) (−r32) (r32+) (r32 + d8/16) (r32 + r8/16) (nnn) Internal ROM (128 Kbytes) FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map 93CW44-8 2004-02-10 TMP93CW44 4. 4.1 Electrical Characteristics Maximum Ratings (TMP93CW44D) Parameter Power supply voltage Input voltage Output current (Per 1 pin) P7 Output current (Per 1 pin) except P7 Output current (P7 total) Output current (Total) Output current (Total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature “X” used in an expression shows a cycle of clock fFPH selected by SYSCR1. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value as an example is calculated at fc, gear = 1/fc (SYSCR1 = “0000”). Symbol VCC VIN IOL1 IOL2 ΣIOL1 ΣIOL ΣIOH PD TSOLDER TSTG TOPR Rating −0.5 to 6.5 −0.5 to VCC + 0.5 20 2 80 120 −80 350 260 −65 to 150 −40 to 85 Unit V mA mW °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) Ta = −40 to 85°C Parameter Symbol VCC Condition fc = 4 to 20 MHz fc = 4 to 12.5 MHz VCC ≥ 4.5 V VCC < 4.5 V fs = 30 to 34 kHz Min 4.5 Typ. (Note 1) Max 5.5 Unit Power supply voltage AVCC = VCC AVSS = VSS = 0 V Input low voltage AD0 to AD15 2.7 (Note 2) 0.8 0.6 −0.3 0.3 VCC 0.25 VCC 0.3 0.2 VCC V 2.2 2.0 0.7 VCC 0.75 VCC VCC − 0.3 0.8 VCC VCC + 0.3 VIL Port 2 to 7 (except P35) VIL1 RESET , NMI , INT0 EA , AM8/ AM16 VIL2 VIL3 VIL4 VIH VCC = 2.7 to 5.5 V X1 Input high voltage AD0 to AD15 VCC ≥ 4.5 V VCC < 4.5 V Port 2 to 7 (except P35) VIH1 RESET , NMI , INT0 EA , AM8/ AM16 VIH2 VIH3 VIH4 VOL IOL7 VOH1 VCC = 2.7 to 5.5 V X1 Output low voltage Output low current (P7) IOL = 1.6 mA (VCC = 2.7 to 5.5 V) VOL = 1.0 V (VCC = 5 V ± 10%) (VCC = 3 V ± 10%) 16 7 2.4 0.45 mA Output high voltage VOH2 IOH = −400 µA (VCC = 3 V ± 10%) IOH = −400 µA (VCC = 5 V ± 10%) V 4.2 Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: The minimum operation voltage of TMP93PW44A is VCC = 4.5 V. 93CW44-9 2004-02-10 TMP93CW44 DC Characteristics (2/2) Typ. (Note 1) Parameter Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at STOP, RAM backup) Symbol Condition Min −1.0 Max −3.5 Unit mA µA V VEXT = 1.5 V IDAR REXT = 1.1 kΩ (Note 2) (VCC = 5 V ± 10% only) ILI ILO VSTOP 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 VIL2 = 0.2VCC, VIH2 = 0.8VCC VCC = 5.5 V VCC = 4.5 V VCC = 3.3 V VCC = 2.7 V fc = 1 MHz 0.02 0.05 2.0 45 50 70 90 ±5 ±10 6.0 130 160 280 400 10 RESET pull-up resistance RRST kΩ Pin capacitance Schmitt width RESET , NMI , INT0 CIO VTH pF V 0.4 VCC = 5.5 V 45 50 70 90 1.0 130 160 280 400 21 28 25 17 4 10 9 6 1 35 30 25 15 10 0.2 20 50 17 12.5 2.5 7 5.5 4.5 0.7 20 16 11 4 Programmable pull-up resistance RKH VCC = 4.5 V VCC = 3.3 V VCC = 2.7 V kΩ NORMAL (Note 3) RUN IDLE2 IDLE1 NORMAL (Note 3) RUN IDLE2 IDLE1 SLOW (Note 3) RUN IDLE2 IDLE1 Ta ≤ 50°C STOP Ta ≤ 70°C Ta ≤ 85°C VCC = 2.7 V to 5.5 V ICC VCC = 3 V ± 10% fs = 32.768 kHz (Typ: VCC = 3.0 V) VCC = 3 V ± 10% fc = 12.5 MHz (Typ: VCC = 3.0 V) VCC = 5 V ± 10% fc = 20 MHz mA µA Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: ICC measurement conditions (NORMAL, SLOW). Only CPU is operational; output pins are open and input pins are fixed. (Reference) Definition of IDAR REXT IDAR VEXT 93CW44-10 2004-02-10 TMP93CW44 4.3 AC Characteristics (1) VCC = 5 V ± 10% Variable Min Max 50 2X − 40 0.5X − 20 1.5X − 70 0.5X − 15 0.5X − 20 X − 40 0.5X − 25 0.5X − 20 X − 25 1.5X − 50 0.5X − 25 3.0X − 55 3.5X − 65 2.0X − 60 2.0X − 40 0 X − 15 2.0X − 40 2.0X − 55 0.5X − 15 3.5X − 90 3.0X − 80 2.0X + 0 2.5X − 120 2.5X + 50 200 206 200 125 36 175 200 85 0 48 85 70 16 129 108 100 5 31250 No. 1 Osc. period ( = X) 2 CLK pulse width Parameter Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode 16 MHz Min Max 62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65 20 MHz Unit Min Max 50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 A0 to A23 valid → CLK hold 4 CLK valid → A0 to A23 hold 5 A0 to A15 valid → ALE fall 6 ALE fall → A0 to A15 hold 7 ALE high pulse width 8 ALE fall → RD / WR fall 9 RD / WR rise → ALE rise 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width 17 RD rise → D0 to D15 hold 18 RD rise → A0 to A15 output 19 21 WR low pulse width WR rise → D0 to D15 hold 20 D0 to D15 valid → WR rise 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → Port input 26 A0 to A23 valid → Port hold 27 WR rise → Port valid tAWH tAWL tCW tAPH tAPH2 tCP AC measuring conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (except for AD0 to AD15) 93CW44-11 2004-02-10 TMP93CW44 (2) VCC = 3 V ± 10% No. 1 Osc. period (= X) 2 CLK pulse width 3 A0 to A23 valid → CLK hold 4 CLK valid → A0 to A23 hold 5 A0 to A15 valid → ALE fall 6 ALE fall → A0 to A15 hold 7 ALE high pulse width 8 ALE fall → RD / WR fall 9 RD / WR rise → ALE rise 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width 17 RD rise → D0 to D15 hold 18 RD fall → A0 to A15 output 19 21 WR low pulse width WR rise → D0 to D15 hold (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode Parameter Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tAWH tAWL tCW tAPH tAPH2 tCP Variable Min Max 80 2X − 40 0.5X − 30 1.5X − 80 0.5X − 35 0.5X − 35 X − 60 0.5X − 35 0.5X − 40 X − 50 1.5X − 50 0.5X − 40 3.0X − 110 3.5X − 125 2.0X − 115 2.0X − 40 0 X − 25 2.0X − 40 2.0X − 120 0.5X − 40 3.5X − 130 3.0X − 100 2.0X + 0 2.5X − 195 2.5X + 50 200 31250 12.5 MHz Unit Min Max 80 120 10 40 5 5 20 5 0 30 70 0 130 155 45 120 0 55 120 40 0 150 140 160 5 250 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 D0 to D15 valid → WR rise 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → Port input 26 A0 to A23 valid → Port hold 27 WR rise → Port valid AC measuring conditions • Output level: High 0.7 × VCC/Low 0.3 × VCC, CL = 50 pF • Input level: High 0.9 × VCC/Low 0.1 × VCC 93CW44-12 2004-02-10 TMP93CW44 (3) Read cycle tOSC X1/XT1 tCLK CLK tAK A0 to A23 tAWH tAWL WAIT tKA tCW tAPH tAPH2 Port input (Note) tADH tRR RD tCA tACH tACL AD0 to AD15 tAL ALE tLL tLC tRD tADL tHR D0 to D15 tCL tRAE A0 to A15 tLA Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93CW44-13 2004-02-10 TMP93CW44 (4) Write cycle X1/XT1 CLK A0 to A23 WAIT Port output (Note) WR , HWR tWW tDW tCP tWD AD0 to AD15 A0 to A15 D0 to D15 ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93CW44-14 2004-02-10 TMP93CW44 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Symbol Min tSCY tOSS tOHS tHSR tSRD 16X tSCY/2 − 5X − 50 5X − 100 0 tSCY − 5X − 100 Parameter SCLK cycle Output Data → Falling edge of SCLK SCLK rising/falling edge → Output data hold SCLK rising/falling edge → Input data hold SCLK rising/falling edge → Effective data input Variable Max 32.768 MHz (Note) Min 488 µs 91.5 µs 152 µs 0 336 µs 12.5 MHz Min 1.28 µs 190 300 0 780 20 MHz Min Max 0.8 µs 100 150 0 450 Unit ns ns ns ns ns Max Max Note 1: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. Note 2: SCLK rising/falling timing; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. 2. Parameter SCLK cycle (Programmable) Output data → SCLK rising edge SCLK rising edge → Output data hold SCLK rising edge → Input data hold SCLK rising edge → Effective data input SCLK output mode Symbol Min tSCY tOSS tOHS tHSR tSRD 16X tSCY − 2X − 150 2X − 80 0 tSCY − 2X − 150 Variable Max 8192X 32.768 MHz (Note) Min 427 µs 60 µs 0 428 µs 12.5 MHz Min Max 20 MHz Min Max Unit Max 488 µs 250 ms 1.28 µs 655.36 µs 0.8 µs 409.6 µs ns 970 80 0 970 550 20 0 550 ns ns ns ns Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. SCLK Output mode/ Input rising edge mode SCLK (Input falling edge mode) Input data TXD Input data RXD tSCY tOSS 0 tOHS 1 tSRD 0 Valid 1 Valid tHSR 2 Valid 3 Valid 2 3 (2) UART mode (SCLK0 and SCLK1 are external input) Parameter SCLK cycle SCLK low level pulse width SCLK high level pulse width Symbol Min tSCY tSCYL tSCYH Variable Max 32.768 MHz (Note) Min 122 µs 6 µs 6 µs 12.5 MHz 20 MHz Unit ns ns ns Max Min Max Min Max 340 165 165 220 105 105 4X + 20 2X + 5 2X + 5 Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. 93CW44-15 2004-02-10 TMP93CW44 4.5 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Symbol Power Supply VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% VCC = 3 V ± 10% VCC = 5 V ± 10% IREF VCC = 3 V ± 10% (VREFL = 0 V) VCC = 2.7 to 5.5 V − 10 Min VCC − 0.2 V VCC − 0.2 V VSS VSS VREFL Typ. VCC VCC VSS VSS 0.5 0.3 0.02 ±1.0 ±1.0 Max VCC VCC VSS + 0.2 V VSS + 0.2 V VREFH 1.5 0.9 5.0 ±3.0 ±5.0 Unit Analog reference voltage ( + ) VREFH Analog reference voltage ( − ) VREFL Analog input voltage range Analog current for analog reference voltage = 1 = 0 Error (except quantization errors) VAIN V mA µA LSB VCC = 5 V ± 10% VCC = 3 V ± 10% Note 1: 1LSB = (VREFH − VREFL)/2 [V] Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.6 Event Counter Input Clock (External input clock: TI0, TI4, TI5, TI6, TI7) Parameter Symbol tVCK tVCKL tVCKH Variable Min Max 8X + 100 4X + 40 4X + 40 12.5 MHz Min Max 740 360 360 20 MHz Min Max 500 240 240 Unit ns ns ns Clock cycle Low level clock pulse width High level clock pulse width 4.7 Interrupt and Capture Operation (1) NMI , INT0 interrupts Parameter Symbol tINTAL tINTAH Variable Min Max 4X 4X 12.5 MHz Min Max 320 320 20 MHz Min Max 200 200 Unit ns ns NMI , INT0 low level pulse width NMI , INT0 high level pulse width (2) INT1, INT4 to INT7 interrupts and capture Parameter INT1, INT4 to INT7 low level pulse width INT1, INT4 to INT7 high level pulse width Symbol tINTBL tINTBH Variable Min Max 4X + 100 4X + 100 12.5 MHz Min Max 420 420 20 MHz Min Max 300 300 Unit ns ns 93CW44-16 2004-02-10 TMP93CW44 4.8 Serial Bus Interface Timing (1) I2C bus mode Parameter Symbol tGSTA tHD:STA tLOW tHIGH tHD:IDAT tSU:IDAT tHD:ODAT tODAT tFSDA tFDRC tSU:STO 3X 2nX 2nX + 16X Min 3X 2nX 2nX 2nX + 12X 0 250 7X Variable Typ. Max Unit ns ns ns ns ns ns START command → SDA fall Hold time START condition SCL low level pulse width SCL high level pulse width Data hold time (Input) Data setup time (Input) Data hold time (Output) Data output → SCL rising edge STOP command → SDA fall SDA falling edge → SCL rising edge Setup time STOP condition 11X 2nX − tHD:ODAT ns ns ns ns ns Note: “n” value is set by SBICR1 START command SDA tGSTA tLOW SCL tHD:STA tHD:IDAT tHIGH tSU:IDAT tSU:STO tHD:ODAT tODAT tFSDA tFDRC STOP command 93CW44-17 2004-02-10 TMP93CW44 (2) Clocked-synchronous 8-bit SIO mode 1. SCK input mode Parameter SCK cycle SCK falling edge → Output data hold Output data → SCK rising edge SCK rising edge → Input data hold Input data → SCK rising edge Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 6X tSCY2 − 6X 6X 0 Max Unit ns ns ns ns ns 2. SCK output mode Parameter Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 2X tSCY2 − 2X 2X 0 tOSS2 tISS2 Max 211X Unit ns ns ns ns ns SCK cycle SCK falling edge → Output data hold Output data → SCK rising edge SCK rising edge → Input data hold Input data → SCK rising edge tSCY2 SCK (Input/output mode) SO (Output data) SI (Input date) tHSR2 tOHS2 93CW44-18 2004-02-10 TMP93CW44 5. Package Dimensions P-QFP80-1420-0.80B Unit: mm 93CW44-19 2004-02-10 TMP93CW44 93CW44-20 2004-02-10