TMP93PW44A

TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93PW44A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93PW44A Low-power CMOS 16-Bit Microcontroller TMP93PW44ADF 1. Outline and Device Characteristics The TMP93PW44A is OTP type MCU which includes 128-Kbyte one-time PROM. Using the adapter socket, you can write and verify the data for the TMP93PW44A. The TMP93PW44ADF has the same pin assignment as TMP93CW44 (Mask ROM type). Writing the program to built-in PROM, the TMP93PW44A operates as the same way as the TMP93CW44. Note: The operation voltage of TMP93PW44A is VCC = 4.5 to 5.5 V though the operation voltage of TMP93CS44/45, TMP93PS44, TMP93CU44 and TMP93CW44 is VCC = 2.7 to 5.5 V. Especially, be careful when TMP93CU44, TMP93CW44 and TMP93PW44A are used. Please refer to the fourth chapter electric characteristic of each product for details. MCU TMP93PW44ADF ROM OTP 128 Kbytes RAM 4 Kbytes Package P-QFP80-1420-0.80B Adapter Socket BM11152 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93PW44A-1 2004-02-10 TMP93PW44A AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4 to AN7 (P54 to P57) AVCC AVSS VREFH VREFL 900/L CPU 10-bit 8-ch AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Interrupt controller F Highfrequency OSC VCC [2] VSS [2] X1 X2 CLK Lowfrequency OSC XT1 (P66) XT2 (P67) AM8/ AM16 EA RESET TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65) Serial I/O (Channel 0) Serial I/O (Channel 1) ALE TEST1/TEST2 INT0 (P35) NMI WAIT (P70) P71 P72 P73 P74 P75 P76 P77 TI0/INT1 (P40) Port 7 Watchdog timer 4-Kbyte RAM Port 0 AD0 to AD7 (P00 to P07) 8-bit timer (TIMER 0) 8-bit timer (TIMER 1) 8-bit timer (TIMER 2) Port 1 AD8 to AD15/A8 to A15 (P10 to P17) Port 2 A0 to A7/A16 to A23 (P20 to P27) RD (P30) WR (P31) HWR /SCK (P32) TO3 (P41) 8-bit timer (TIMER 3) 128-Kbyte PROM Port 3 INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (TIMER 4) 16-bit timer (TIMER 5) Wait controller (3 blocks) Serial bus interface controller SO/SDA (P33) SI/SCL (P34) Note: The items in parentheses ( ) are the initial setting after reset. Figure 1.1 TMP93PW44A Block Diagram 93PW44A-2 2004-02-10 TMP93PW44A 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93PW44A, their names and outline functions are described below. 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93PW44ADF. P40 (TI0/INT1) P35 (INT0) P34 (SI/SCL) P33 (SO/SDA) P32 (HWR/SCK) P31(WR) P30 (RD) VCC P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12) P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) 64 60 55 50 45 (TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54 65 41 40 70 TMP93PW44ADF QFP80 Top view 35 75 30 P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC TEST2 TEST1 P67 (XT2) P66 (XT1) RESET 80 10 15 20 24 EA 25 1 5 NMI Figure 2.1.1 Pin Assignment (P-QFP80-1420-0.80B) (TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS P72 P73 P74 P75 P76 P77 CLK AM8/AM16 X1 X2 (AN5) P55 (AN6) P56 (AN7) P57 93PW44A-3 2004-02-10 TMP93PW44A 2.2 Pin Names and Functions The TMP93PW44A has MCU mode and PROM mode. (1) Table 2.2.1 shows pin function of TMP93PW44A in MCU mode. Table 2.2.1 Pin Names and Functions (1/3) Pin Name P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O Functions I/O Port 0: I/O port that allows selection of I/O on a bit basis 3-state Address/data (Lower): Bits 0 to 7 for address/data bus I/O Port 1: I/O port that allows selection of I/O on a bit basis 3-state Address/data (Upper): Bits 8 to 15 for address/data bus Output Address: Bits 8 to 15 for address bus 8 I/O Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Output Address: Bits 0 to 7 for address bus Output Address: Bits 16 to 23 for address bus 1 1 1 Output Port 30: Output port Output Read: Strobe signal for reading external memory Output Port 31: Output port Output Write: Strobe signal for writing data on pins AD0 to AD7 I/O Port 32: I/O port (with pull-up resistor) Output High write: Strobe signal for writing data on pins AD8 to AD15 I/O Mode clock SBI SIO mode clock P31 WR P32 HWR SCK P33 SO SDA P34 SI SCL P35 INT0 P40 TI0 INT1 P41 TO3 P42 TI4 INT4 1 I/O Port 33: I/O port Output Serial send data I/O SBI I2C bus mode channel data 1 I/O Port 34: I/O port Input Serial receive data I/O SBI I2C bus mode clock 1 I/O Port 35: I/O port Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge 1 I/O Port 40: I/O port Input Timer input 0: Timer 0 input Input Interrupt request pin 1: Interrupt request pin with rising edge 1 1 I/O Port 41: I/O port Output PWM output 3: 8-bit PWM timer 3 output I/O Port 42: I/O port Input Timer input 4: Timer 4 count/capture trigger signal input Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge 93PW44A-4 2004-02-10 TMP93PW44A Table 2.2.2 Pin Names and Functions (2/3) Pin Name P43 TI5 INT5 P44 TO4 P45 TI6 INT6 P46 TI7 INT7 P47 TO6 P50 to P52, P54 to P57 AN0 to AN2, AN4 to AN7 P53 AN3 ADTRG Number of Pins 1 I/O I/O Port 43: I/O port Functions Input Timer input 5: Timer 4 count/capture trigger signal input Input Interrupt request pin 5: Interrupt request pin with rising edge 1 1 I/O Port 44: I/O port Output Timer output 4: Timer 4 output pin I/O Port 45: I/O port Input Timer input 6: Timer 5 count/capture trigger signal input Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge 1 I/O Port 46: I/O port Input Timer input 7: Timer 5 count/capture trigger signal input Input Interrupt request pin 7: Interrupt request pin with rising edge 1 7 I/O Port 47: I/O port Output Timer output 6: Timer 5 output pin Input Port 50 to 52, port 54 to 57: Input port Input Analog input: Analog signal input for AD converter 1 Input Port 53: Input port Input Analog input: Analog signal input for AD converter Input AD converter external start trigger input 1 1 1 I/O Port 60: I/O port (with pull-up resistor) Output Serial send data 0 I/O Port 61: I/O port (with pull-up resistor) Input Serial receive data 0 I/O Port 62: I/O port (with pull-up resistor) Input Serial data send enable 0 (Clear to send) I/O Serial clock I/O 0 1 1 1 I/O Port 63: I/O port (with pull-up resistor) Output Serial send data 1 I/O Port 64: I/O port (with pull-up resistor) Input Serial receive data 1 I/O Port 65: I/O port (with pull-up resistor) I/O Serial clock I/O 1 Input Serial data send enable 1 (Clear to send) 1 1 I/O Port 66: I/O port (Open-drain output) Input Low-frequency oscillator connecting pin I/O Port 67: I/O port (Open-drain output) Output Low-frequency oscillator connecting pin P60 TXD0 P61 RXD0 P62 CTS0 SCLK0 P63 TXD1 P64 RXD1 P65 SCLK1 CTS1 P66 XT1 P67 XT2 93PW44A-5 2004-02-10 TMP93PW44A Table 2.2.3 Pin Names and Functions (3/3) Pin Name P70 WAIT Number of Pins 1 I/O I/O Functions Port 70: I/O port (High current output available) Input WAIT: Pin used to request CPU bus wait. (It is active in (1 + N) WAIT mode. Set by the bus-width/wait control register.) 7 1 1 1 1 1 1 1 1 1 1 I/O Port 71 to 77: I/O port (High current output available) Input Power supply pin for AD converter Input GND pin for AD converter (0 V) Input Pin for high level reference voltage input to AD converter Input Pin for low level reference voltage input to AD converter Input Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. Input High-frequency oscillator connecting pin Output High-frequency oscillator connecting pin Input Reset: Initializes TMP93PW44A (with pull-up resistor). Output Address latch enable Can be disabled for reducing noise. Output Clock output: Outputs “fSYS ÷ 2” clock. Pulled-up during reset. Can be disabled for reducing noise. Input External access: “1” should be inputted Input Address mode: Selects external data bus width. “1” should be inputted. The data bus width for external access is set by chip select/WAIT control register, port 1 control register. Input Power supply pin Input GND pin (All VSS pins are connected to the GND (0 V)). Output/Input TEST1 should be connected with TEST2 pin. Do not connect to any other pins. P71 to P77 AVCC AVSS VREFH VREFL NMI X1 X2 RESET ALE CLK EA 1 1 AM8/ AM16 VCC VSS TEST1/TEST2 2 2 2 Note: Built-in pull-up resistors can be released from the pins other than the RESET pin by software. 93PW44A-6 2004-02-10 TMP93PW44A (2) PROM mode Table 2.2.4 shows pin functions of the TMP93PW44A in PROM mode. Table 2.2.4 Pin Names and Functions of PROM Mode Pin Function A7 to A0 A15 to A8 A16 D7 to D0 CE OE PGM Number of Input/Output Pins 8 8 1 8 1 1 1 1 3 3 Input Input Input I/O Input Input Input Function Pin Name (MCU Mode) P27 to P20 Memory address of program Memory data of pfogram Chip enable Output control Program control P17 to P10 P33 P07 to P00 P32 P30 P31 EA VPP VCC VSS Power supply 12.75 V/5 V (Power supply of program) Power supply 6.25 V/5 V Power supply 0 V VCC, AVCC VSS, AVSS Pin Function P60 RESET Number of Input/Output Pins 1 1 1 1 1 1 7 2 Input Input Input Output Input Output Input Input/Output Disposal of Pin Fix to low level (Security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level TEST1 should be connected with TEST2 pin. Do not connect to any other pins. CLK ALE X1 X2 P66 to P61 AM8/ AM16 TEST1/TEST2 P35, P34 P47 to P40 P57 to P50 P67 P77 to P70 VREFH VREFL NMI 30 I/O Open 93PW44A-7 2004-02-10 TMP93PW44A 3. Operation This section describes the functions and basic operational blocks of the TMP93PW44A. The TMP93PW44A has PROM in place of the mask ROM which is included in the TMP93CW44. The other configuration and functions are the same as the TMP93CW44. Regarding the function of the TMP93PW44A (Not described), see the part of TMP93CW44. The TMP93PW44A has two operational modes: MCU mode and PROM mode. 3.1 MCU mode (1) Mode setting and function The MCU mode is set by opening the CLK pin (Pin open). In the MCU mode, the operation is same as TMP93CW44. (2) Memory map The memory map of TMP93PW44A is same as that of TMP93CW44. Figure 3.1.1 shows the memory map in MCU mode. Figure 3.1.2 show that in PROM mode. 000000H 000080H Internal RAM (4 Kbytes) 001080H 00000H Internal I/O (128 bytes) Internal PROM (128 Kbytes) External memory FE0000H 1FFFFH Internal PROM (128 Kbytes) FFFF00H FFFFFFH ( Interrupt vector table area (256 bytes) = Internal area) Figure 3.1.1 Memory Map in MCU Mode Figure 3.1.2 Memory Map in PROM Mode 93PW44A-8 2004-02-10 TMP93PW44A 3.2 PROM Mode (1) Mode setting and function PROM mode is set by setting the RESET and CLK pins to the “L” level. The programming and verification for the internal PROM is achieved by using a general EPROM programmer with the adaptor socket. 1. Preparation of OTP adaptor BM11152: for TMP93PW44ADF 2. Setting of OTP adaptor The switch (SW1) is set to N side. 3. Setting of PROM writer i) Set PROM type to TC 571000D. Size: 1 Mbits (128 K × 8 bits) VPP: 12.75 V tPW: 100 µs Electric signature mode: None ii) Data transmittion In TMP93PW44A, PROM is placed on addresses 00000H to 1FFFFH in PROM mode, and addresses FE0000H to FFFFFFH in MCU mode. Therefore data should be transferred to addresses 00000H to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode (See instruction manual of PROM programmer.) iii) Setting of the program address Start address: 00000H End address: 1FFFFH 4. Programming Program and verify according to operating process of PROM programmer. 93PW44A-9 2004-02-10 TMP93PW44A Figure 3.2.1 shows the setting of the pins in PROM mode. VPP (12.75 V/5 V) EA VCC AVCC, VCC P30 P32 P31 P07 to P00 RESET TEST1 TEST2 P33 P17 to P10 P27 to P20 OE CE PGM A16 to A0 D7 to D0 * For other pins, refer to the section on pin functions (Table 2.2.2). * Use the 10 MHz resonator in case of programming and CLK VCC verification by a general PROM programmer. X1 P65 to P61 AM8/ AM16 X2 VSS AVSS P60 SECURITY Figure 3.2.1 PROM Mode Pin Setting (2) Caution for electric signature The TMP93PW44A dose not support the electric signature mode (Hereinafter referred to as “signature”). If PROM programmer used the signature, the device would be damaged because of applying voltage of 12 ± 0.5 V to pin 9 (A9) of the address. Please use without setting the signature. (3) Program mode All bits of the TMP93PW44A are “1” when delivered (The erase state). Data “0” is written in the necessary bit location during program operating. Writing function can be operated at VPP = 12.5 V, OE = VIH, CE = VIL. Built-in one time PROM can be written in any sequence. It is possible to write only special address. (4) Adopter socket (BM11152: for TMP93PW44ADF) BM11152 is the adapter sockets to write data into the TMP93PW44A. The TMP93PW44A has built-in one time PROM using a general EPROM programmer. 93PW44A-10 2004-02-10 TMP93PW44A (5) Program storing area of PROM mode The TMP93PW44A has the program space (FE0000H to FFFFFFH) of 128 Kbytes. The address 0000H to 1FFFFH of PROM mode equals to the address FE0000H to FFFFFFH of MCU mode. (6) Program write setting method using a general PROM programmer PROM to be prepared should equal to TC571000D functions. 1. 2. 3. 4. 5. 6. Set the switch (SW1) of BM11152 (Hereinafter referred to as “adapter”) to the program side (NOR) (Note 1). Connect MCU to the adapter (Note 2). Connect the adapter to PROM programmer (Note 2). Set the PROM type of PROM programmer to TC571000D. Set the start address for writing PROM to 0000H, and the end address to 1FFFFH (Note 3). Writing to built-in one time PROM and verifying should be operated according to the operation procedures of PROM programmer. Note 1: If data is written to built-in one time PROM without setting the switch (SW1) to the program side, the device would be damaged. Note 2: Please set with the first pin of the adapter and that of PROM programmer socket matched. If the first pin is conversely set, MCU or programmer would be damaged. Note 3: If data “0” is written to the address which is over 1FFFFH, the contents of the original program would be damaged because of writing “0” to the addresses 0000H to 1FFFFH. 93PW44A-11 2004-02-10 TMP93PW44A (7) Programming flow chart The programming mode is set by applying 12.75 V (Programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : “L” level, CLK: “L” level). While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “L” level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address (25 times maximum). Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.2.2 shows the programming flowchart. Start VCC = 6.25 V ± 0.25 V VPP = 12.75 V ± 0.25 V Address = Start address X=0 Program 0.1 ms pulse X=X+1 X > 25? No Error Address = Address + 1 No Verify OK Last address? Yes VCC = 5 V VPP = 5 V Yes Read all data OK Pass Error Failure Figure 3.2.2 Flowchart (High-speed program writing) 93PW44A-12 2004-02-10 TMP93PW44A (8) Security bit The TMP93PW44A has a security bit in PROM cell. If the security bit is programmed to “0”, the content of the PROM is disable to be read (FFH data) in PROM mode. (How to program the security bit) The difference from the programming procedures described in section 3.2 (1) are as follows. 1. 2. Setting OTP adaptor Set the switch (SW1) to S side. Setting PROM programmer i) Transferring the data ii) Setting of programming address The security bit is in bit0 of address 00000H. Set the start address 00000H and the end address 00000H. Set the data FEH at the address 00000H. 93PW44A-13 2004-02-10 TMP93PW44A 4. 4.1 Electrical Characteristics Maximum Ratings (TMP93PW44AD) Parameter Power supply voltage Input voltage Output current (Per 1 pin) P7 Output current (Per 1 pin) except P7 Output current (P7 total) Output current (Total) Output current (Total) Power dissipation (Ta = 85°C) Soldering temperature (10 s) Storage temperature Operating temperature “X” used in an expression shows a cycle of clock fFPH selected by SYSCR1. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value as an example is calculated at fc, gear=1/fc (SYSCR1 = “0000”). Symbol VCC VIN IOL1 IOL2 ΣIOL1 ΣIOL ΣIOH PD TSOLDER TSTG TOPR EA pin Rating −0.5 to 6.5 except EA pin −0.5 to VCC + 0.5 −0.5 to 14.0 20 2 80 120 −80 350 260 −65 to 150 −40 to 85 Unit V mA mW °C Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. 4.2 DC Characteristics (1/2) VCC = 5 V ± 10%, Ta = −40 to 85°C Parameter Symbol VCC VIL VCC = 5 V ± 10% −0.3 Condition fc = 4 to 20 MHz fs = 30 to 34 kHz Min 4.5 (Note 2) Typ. (Note 1) Max 5.5 0.8 0.3 VCC 0.25 VCC 0.3 0.2 VCC Unit V Power supply voltage AVCC = VCC AVSS = VSS = 0 V AD0 to AD15 Input low voltage Port 2 to 7 (except P35) VIL1 VIL2 RESET , NMI , INT0 EA , AM8/ AM16 VIL3 VIL4 VIH VCC = 5 V ± 10% 2.2 0.7VCC 0.75VCC VCC − 0.3 0.8 VCC IOL = 1.6 mA VOL = 1.0 V IOH = −400 µA 16 4.2 X1 AD0 to AD15 V Port 2 to 7 (except P35) VIH1 Input high VIH2 RESET , NMI , INT0 voltage EA , AM8/ AM16 VIH3 X1 Output low voltage Output low current (P7) Output high voltage VIH4 VOL IOL7 VOH VCC + 0.3 0.45 V mA V Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2:The minimum operation voltage of TMP93CU44/TMP93CW44 is VCC = 2.7 V (at fc = 4 to 12.5 MHz, fs = 30 to 34 kHz). 93PW44A-14 2004-02-10 TMP93PW44A DC Characteristics (2/2) Typ. (Note 1) Parameter Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at STOP, RAM backup) RESET pull-up resistance Symbol IDAR (Note 2) ILI ILO VSTOP RRST CIO VTH RKH Condition VEXT = 1.5 V REXT = 1.1 kΩ 0.0 ≤ VIN ≤ VCC 0.2 ≤ VIN ≤ VCC − 0.2 VIL2 = 0.2VCC, VIH2 = 0.8VCC VCC = 5.5 V VCC = 4.5 V fc = 1 MHz Min −1.0 Max −3.5 Unit mA µA V kΩ pF V 0.02 0.05 2.0 45 50 ±5 ±10 6.0 130 160 10 Pin capacitance Schmitt width RESET , NMI , INT0 Programmable pull-up resistance NORMAL (Note 3) RUN IDLE2 IDLE1 SLOW (Note 3) RUN IDLE2 IDLE1 0.4 VCC = 5.5 V VCC = 4.5 V 45 50 1.0 130 160 27 33 27 19 7 140 100 75 65 10 0.2 20 50 22 16 4.2 85 kΩ fc = 20 MHz mA ICC fs = 32.768 kHz 50 35 20 µA Ta ≤ 50°C STOP Ta ≤ 70°C Ta ≤ 85°C µA Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: ICC measurement conditions (NORMAL, SLOW): Only CPU is operational; output pins are open and input pins are fixed. (Reference) Definition of IDAR REXT IDAR VEXT 93PW44A-15 2004-02-10 TMP93PW44A 4.3 AC Electrical Characteristics (1) VCC = 5 V ± 10% Variable Min Max 50 2X − 40 0.5X − 20 1.5X − 70 0.5X − 15 0.5X − 20 X − 40 0.5X − 25 0.5X − 20 X − 25 1.5X − 50 0.5X − 25 3.0X − 55 3.5X − 65 2.0X − 60 2.0X − 40 0 X − 15 2.0X − 40 2.0X − 55 0.5X − 15 3.5X − 90 3.0X − 80 2.0X + 0 2.5X − 120 2.5X + 50 200 206 200 125 36 175 200 85 0 48 85 70 16 129 108 100 5 31250 No. 1 Osc. period (= X) 2 CLK pulse width Parameter Symbol tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD (1 + N) WAIT mode (1 + N) WAIT mode (1 + N) WAIT mode 16 MHz Min Max 62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65 20 MHz Unit Min Max 50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 A0 to A23 valid → CLK hold 4 CLK valid → A0 to A23 hold 5 A0 to A15 valid → ALE fall 6 ALE fall → A0 to A15 hold 7 ALE high pulse width 8 ALE fall → RD / WR fall 9 RD / WR rise → ALE rise 10 A0 to A15 valid → RD / WR fall 11 A0 to A23 valid → RD / WR fall 12 RD / WR rise → A0 to A23 hold 13 A0 to A15 valid → D0 to D15 input 14 A0 to A23 valid → D0 to D15 input 15 RD fall → D0 to D15 input 16 RD low pulse width 17 RD rise → D0 to D15 hold 18 RD rise → A0 to A15 output 19 21 WR low pulse width WR rise → D0 to D15 hold 20 D0 to D15 valid → WR rise 22 A0 to A23 valid → WAIT input 23 A0 to A15 valid → WAIT input 24 RD / WR fall → WAIT hold 25 A0 to A23 valid → PORT input 26 A0 to A23 valid → PORT hold 27 WR rise → PORT valid tAWH tAWL tCW tAPH tAPH2 tCP AC Measuring Conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (except for AD0 to AD15) 93PW44A-16 2004-02-10 TMP93PW44A (2) Read cycle tOSC X1/XT1 tCLK CLK t AK A0 to A23 tAWH tAWL WAIT tKA tCW tAPH tAPH2 Port input (Note) tADH tRR RD tCA tACH tACL AD0 to AD15 tAL ALE tLL tLC tRD tADL tHR D0 to D15 tCL tRAE A0 to A15 tLA Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW44A-17 2004-02-10 TMP93PW44A (3) Write cycle X1/XT1 CLK A0 to A23 WAIT Port output (Note) WR , HWR tWW tDW tCP tWD AD0 to AD15 A0 to A15 D0 to D15 ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW44A-18 2004-02-10 TMP93PW44A 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Parameter SCLK cycle Output data → Falling edge of SCLK Symbol tSCY tOSS tOHS tHSR tSRD Variable Min 16X tSCY/2 − 5X − 50 5X − 100 0 tSCY − 5X − 100 32.768 MHz Max Min 488 µs 91.5 µs 152 µs 0 (Note) 20 MHz Min Max 0.8 µs 100 150 0 Max Unit ns ns ns ns SCLK rising/falling edge → Output data hold SCLK rising/falling edge → Input data hold SCLK rising/falling edge → Effective data input 336 µs 450 ns Note 1: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. Note 2: SCLK rising/falling timing; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. 2. SCLK output mode Parameter SCLK cycle (Programmable) Output data → SCLK rising edge SCLK rising edge → Output data hold SCLK rising edge → Input data hold SCLK rising edge → Effective data input Symbol tSCY Variable Min 16X 32.768 MHz Max 8192X (Note) 20 MHz Min Max Min 488 µs 427 µs 60 µs 0 Max Unit 250 ms 0.8 µs 550 20 0 428 µs 409.6 ns µs ns ns ns 550 ns tOHS tHSR tSRD tOSS tSCY − 2X − 150 2X − 80 0 tSCY − 2X − 150 Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. tSCY SCLK Output mode/ Input rising edge mode SCLK (Input falling edge mode) Output data TXD Input data RXD tOSS 0 tOHS 1 tSRD 0 Valid 1 Valid tHSR 2 Valid 3 Valid 2 3 (2) UART mode (SCLK0 and SCLK 1 are external input) Parameter SCLK cycle SCLK low level pulse width SCLK high level pulse width Symbol tSCY tSCYL tSCYH Variable Min 4X + 20 2X + 5 2X + 5 32.768 MHz Max Min 122 µs 6 µs 6 µs (Note) 20 MHz Min 220 105 105 Max Max Unit ns ns ns Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. 93PW44A-19 2004-02-10 TMP93PW44A 4.5 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Analog reference voltage ( + ) Analog reference voltage ( − ) Analog input voltage range Analog current for analog reference voltage = 1 = 0 Error (except quantization errors) − 10 Symbol VREFH VREFL VAIN IREF (VREFL = 0 V) Power Supply Min VCC − 0.2 V VSS VREFL Typ. VCC VSS Max VCC VSS + 0.2 V VREFH Unit V VCC = 5 V ± 10% 0.5 0.02 ±1.0 1.5 5.0 ±3.0 mA µA LSB Note 1: 1LSB = (VREFH − VREFL)/2 [V] Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.6 Event Counter Input Clock (External Input Clock: TI0, TI4, TI5, TI6, TI7) Parameter Symbol tVCK tVCKL tVCKH Variable Min Max 8X + 100 4X + 40 4X + 40 20 MHz Min Max 500 240 240 Unit ns ns ns Clock cycle Low level clock pulse width High level clock pulse width 4.7 Interrupt and Capture Operation (1) NMI , INT0 interrupts Parameter Symbol tINTAL tINTAH Variable Min Max 4X 4X 20 MHz Min Max 200 200 Unit ns ns NMI , INT0 low level pulse width NMI , INT0 high level pulse width (2) INT1, INT4 to INT7 interrupts and capture Parameter INT1, INT4 to INT7 low level pulse width INT1, INT4 to INT7 high level pulse width Symbol tINTBL tINTBH Variable Min Max 4X + 100 4X + 100 20 MHz Min Max 300 300 Unit ns ns 93PW44A-20 2004-02-10 TMP93PW44A 4.8 Serial Bus Interface Timing (1) I2C bus mode Parameter Symbol tGSTA tHD:STA tLOW tHIGH tHD:IDAT tSU:IDAT tHD:ODAT tODAT tFSDA tFDRC tSU:STO 3X 2nX 2nX + 16X Min 3X 2nX 2nX 2nX + 12X 0 250 7X Variable Typ. Max Unit ns ns ns ns ns ns START command → SDA fall Hold time START condition SCL low level pulse width SCL high level pulse width Data hold time (input) Data setup time (input) Data hold time (output) Data output → SCL rising edge STOP command → SDA fall SDA falling edge → SCL rising edge Setup time STOP condition 11X 2nX − tHD:ODAT ns ns ns ns ns Note: “n” value is set by SBICR1 START command SDA tGSTA tLOW SCL tHD:STA tHD:IDAT tHIGH tSU:IDAT tSU:STO tHD:ODAT tODAT tFSDA tFDRC STOP Command 93PW44A-21 2004-02-10 TMP93PW44A (2) Clocked-synchronous 8-bit SIO mode 1. SCK input mode Parameter SCK cycle SCK falling edge → Output data hold Output data → SCK rising edge SCK rising edge → Input data hold Input data → SCK rising edge Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 6X tSCY2 − 6X 6X 0 Max Unit ns ns ns ns ns 2. SCK output mode Parameter Symbol tSCY2 tOHS2 tOSS2 tHSR2 tISS2 Variable Min 25X 2X tSCY2 − 2X 2X 0 tOSS2 tISS2 Max 211X Unit ns ns ns ns ns SCK cycle SCK falling edge → Output data hold Output data → SCK rising edge SCK rising edge → Input data hold Input data → SCK rising edge tSCY2 SCK (Input/output mode) tOHS2 SO (Output data) SI (Input data) tHSR2 93PW44A-22 2004-02-10 TMP93PW44A 4.9 Read Operation in PROM Mode DC/AC characteristics Ta = 25 ± 5°C Vcc = 5 V ± 10% Parameter VPP read voltage Input high voltage (A0 to A16, CE , OE , PGM ) Input low voltage (A0 to A16, CE , OE , PGM ) Address to output delay Symbol Condition VPP VIH1 VIL1 tACC − − − CL = 50 pF Min 4.5 2.2 −0.3 − Max 5.5 VCC + 0.3 0.8 2.25TCYC + α Unit V ns TCYC = 400 ns (10 MHz clock) α = 200 ns A0 to A16 CE OE PGM tACC D0 to D7 Data output 93PW44A-23 2004-02-10 TMP93PW44A 4.10 Program Operation in PROM Mode DC/AC characteristics Ta = 25 ± 5°C VCC = 6.25 V ± 0.25 V Parameter Programming supply voltage Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VCC supply current VPP supply current PGM program pulse width Symbol VPP VIH VIL ICC IPP tPW Condition − − − fc = 10 MHz VPP = 13.00 V CL = 50 pF Min 12.50 2.6 −0.3 − − 0.095 Typ. 12.75 Max 13.00 VCC + 0.3 0.8 50 50 Unit V mA ms 0.1 0.105 A0 to A16 CE OE D0 to D7 Unknown Data-in stable tPW Data-out valid PGM VPP Note 1: The power supply of VPP (12.75 V) must be set power-on at the same time or the later time for a power supply of VCC and must be clear power-on at the same time or early time for a power supply of VCC. Note 2: The pulling up/down device on condition of VPP = 12.75 V suffers a damage for the device. Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the programming. 93PW44A-24 2004-02-10 TMP93PW44A 5. Package Dimensions P-QFP80-1420-0.80B Unit: mm 93PW44A-25 2004-02-10 TMP93PW44A 93PW44A-26 2004-02-10