TMPM333FYFG(C)

32 Bit RISC Microcontroller TX03 Series TMPM333FDFG/FYFG/FWFG © 2010 TOSHIBA CORPORATION All Rights Reserved TMPM333FDFG/FYFG/FWFG ************************************************************************************************************************* ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* R TMPM333FDFG/FYFG/FWFG Introduction: Notes on the description of SFR (Special Function Register) under this specification An SFR (Special Function Register) is a control register for periperal circuits (IP). The SFR addressses of IPs are described in the chapter on memory map, and the details of SFR are given in the chapter of each IP. Definition of SFR used in this specification is in accordance with the following rules. a. SFR table of each IP as an example ・ SFR tables in each chapter of IP provides register names, addresses and brief descriptions. ・ All registers have a 32-bit unique address and the addresses of the registers are defined as follows, with some exceptions: "Base address + (Unique) address" Base Address = 0x0000_0000 Register name Control register Address(Base+) SAMCR 0x0004 0x000C Note: SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) + unique address (0x0004)). Note: The register shown above is an example for explanation purpose and not for demonstration purpose. This register does not exist in this microcontroller. b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and functions. TMPM333FDFG/FYFG/FWFG 1.2.2 SAMCR(Control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 9 15 14 13 12 11 10 bit symbol - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol MODE After reset 0 0 0 0 Bit Bit Symbol TDATA 0 0 1 Type 0 Function 31-10 − R "0" can be read. 9-7 MODE[2:0] R/W Operation mode settings 000 : Sample mode 0 001 : Sample mode 1 010 : Sample mode 2 011 : Sample mode 3 The settings other than those above: Reserved 6-0 Note: TDATA[6:0] W Transmitted data The Type is divided into three as shown below. R/W c. 8 MODE READ WRITE R READ W WRITE Data descriptopn Meanings of symbols used in the SFR description are as shown below. ・ x:channel numbers/ports ・ n,m:bit numbers d. Register descriptoption Registers are described as shown below. ・ Register name Exmaple: SAMCR="000" or SAMCR="000" indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width). TMPM333FDFG/FYFG/FWFG Revision History Date Revision Comment 2010/6/1 1 First Release 2010/10/6 2 Contents Revised Table of Contents Introduction: Notes on the description of SFR (Special Function Register) under this specification TMPM333FDFG/FYFG/FWFG 1.1 1.2 1.3 1.4 Features......................................................................................................................................1 Block Diagram...........................................................................................................................3 Pin Layout (Top view)...............................................................................................................4 Pin names and Functions...........................................................................................................5 1.4.1 1.4.2 1.5 Sorted by Pin........................................................................................................................................................................5 Sorted by Port....................................................................................................................................................................11 Pin Numbers and Power Supply Pins......................................................................................16 2. Processor Core 2.1 2.2 2.3 Information on the processor core...........................................................................................17 Configurable Options...............................................................................................................17 Exceptions/ Interruptions.........................................................................................................17 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.5 2.6 Number of Interrupt Inputs................................................................................................................................................17 Number of Priority Level Interrupt Bits............................................................................................................................18 SysTick..............................................................................................................................................................................18 SYSRESETREQ................................................................................................................................................................18 LOCKUP...........................................................................................................................................................................18 Auxiliary Fault Status register...........................................................................................................................................18 Events......................................................................................................................................19 Power Management.................................................................................................................19 Exclusive access......................................................................................................................19 3. Debug Interface 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Specification Overview...........................................................................................................21 SWJ-DP...................................................................................................................................21 ETM.........................................................................................................................................21 Pin Functions...........................................................................................................................22 Peripheral Functions in Halt Mode..........................................................................................23 Reset Vector Break..................................................................................................................23 Connection with a Debug Tool................................................................................................24 3.7.1 3.7.2 About connection with debug tool.....................................................................................................................................24 Important points of using debug interface pins used as general-purpose ports.................................................................24 4. Memory Map i 4.1 Memory map............................................................................................................................25 4.1.1 4.1.2 4.1.3 4.2 Memory map of the TMPM333FDFG...............................................................................................................................26 Memory Map of TMPM333FYFG....................................................................................................................................27 Memory Map of TMPM333FWFG...................................................................................................................................28 SFR area detail.........................................................................................................................29 5. Reset 5.1 5.2 Cold reset.................................................................................................................................31 Warm reset...............................................................................................................................32 5.2.1 5.2.2 Reset period.......................................................................................................................................................................32 After reset..........................................................................................................................................................................32 6. Clock/Mode control 6.1 6.2 Features....................................................................................................................................33 Registers..................................................................................................................................34 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 Register List.......................................................................................................................................................................34 CGSYSCR (System control register)................................................................................................................................35 CGOSCCR (Oscillation control register)..........................................................................................................................36 CGSTBYCR (Standby control register)............................................................................................................................37 CGPLLSEL (PLL Selection Register)...............................................................................................................................38 CGCKSEL (System clock selection register)....................................................................................................................39 Clock control...........................................................................................................................40 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 Clock System Block Diagram............................................................................................................................................40 Initial Values after Reset....................................................................................................................................................40 Clock system Diagram.......................................................................................................................................................41 Clock Multiplication Circuit (PLL)...................................................................................................................................42 Warm-up function..............................................................................................................................................................42 System Clock.....................................................................................................................................................................44 6.3.6.1 6.3.6.2 6.3.7 6.3.8 6.4 Mode Transitions...............................................................................................................................................................46 Operation mode.......................................................................................................................47 6.5.1 6.5.2 6.6 Prescaler Clock Control.....................................................................................................................................................44 System Clock Pin Output Function...................................................................................................................................45 Modes and Mode Transitions.................................................................................................46 6.4.1 6.5 High speed clock Low speed clock NORMAL mode................................................................................................................................................................47 SLOW mode......................................................................................................................................................................47 Low Power Consumption Modes............................................................................................48 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 IDLE mode........................................................................................................................................................................48 SLEEP mode......................................................................................................................................................................48 STOP mode........................................................................................................................................................................49 Low power Consumption Mode Setting............................................................................................................................49 Operational Status in Each Mode......................................................................................................................................50 Releasing the Low Power Consumption Mode.................................................................................................................51 Warm-up............................................................................................................................................................................52 Clock Operations in Mode Transition...............................................................................................................................53 6.6.8.1 6.6.8.2 6.6.8.3 6.6.8.4 Transition of operation modes: NORMAL → STOP → NORMAL Transition of operation modes: NORMAL → SLEEP → NORMAL Transition of operation modes: SLOW → STOP → SLOW Transition of operation modes: SLOW → SLEEP → SLOW 7. Exceptions 7.1 Overview..................................................................................................................................55 7.1.1 7.1.2 ii Exception Types................................................................................................................................................................55 Handling Flowchart...........................................................................................................................................................56 7.1.2.1 7.1.2.2 7.1.2.3 7.1.2.4 7.2 7.3 7.4 7.5 Reset Exceptions......................................................................................................................61 Non-Maskable Interrupts (NMI)..............................................................................................62 SysTick....................................................................................................................................62 Interrupts..................................................................................................................................63 7.5.1 Interrupt Sources................................................................................................................................................................63 7.5.1.1 7.5.1.2 7.5.1.3 7.5.1.4 7.5.1.5 7.5.1.6 7.5.2 Interrupt Route Generation Transmission Precautions when using external interrupt pins List of Interrupt Sources Active level Interrupt Handling..............................................................................................................................................................67 7.5.2.1 7.5.2.2 7.5.2.3 7.5.2.4 7.5.2.5 7.5.2.6 7.6 Exception Request and Detection Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) Executing an ISR Exception exit Flowchart Preparation Detection by Clock Generator Detection by CPU CPU processing Interrupt Service Routine (ISR) Exception/Interrupt-Related Registers.....................................................................................72 7.6.1 7.6.2 Register List.......................................................................................................................................................................72 NVIC Registers..................................................................................................................................................................73 7.6.2.1 7.6.2.2 7.6.2.3 7.6.2.4 7.6.2.5 7.6.2.6 7.6.2.7 7.6.2.8 7.6.2.9 7.6.2.10 7.6.2.11 7.6.2.12 7.6.2.13 7.6.2.14 7.6.2.15 7.6.2.16 7.6.2.17 7.6.3 SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register SysTick Calibration Value Register Interrupt Set-Enable Register 1 Interrupt Set-Enable Register 2 Interrupt Clear-Enable Register 1 Interrupt Clear-Enable Register 2 Interrupt Set-Pending Register 1 Interrupt Set-Pending Register 2 Interrupt Clear-Pending Register 1 Interrupt Clear-Pending Register 2 Interrupt Priority Register Vector Table Offset Register Application Interrupt and Reset Control Register System Handler Priority Register System Handler Control and State Register Clock generator registers...................................................................................................................................................91 7.6.3.1 7.6.3.2 7.6.3.3 7.6.3.4 7.6.3.5 7.6.3.6 CGIMCGA(CG Interrupt Mode Control Register A) CGIMCGB(CG Interrupt Mode Control Register B) CGIMCGC(CG Interrupt Mode Control Register C) CGICRCG(CG Interrupt Request Clear Register) CGNMIFLG(NMI Flag Register) CGRSTFLG (Reset Flag Register) 8. Input/Output Ports 8.1 Port Functions........................................................................................................................101 8.1.1 8.1.2 8.1.3 8.1.4 8.2 Function Lists..................................................................................................................................................................101 Port Registers Outline......................................................................................................................................................104 Port States in STOP Mode...............................................................................................................................................105 Precautions for Mode Transition between STOP and SLEEP.........................................................................................105 Port functions.........................................................................................................................106 8.2.1 Port A (PA0 to PA7)........................................................................................................................................................106 8.2.1.1 8.2.1.2 8.2.1.3 8.2.1.4 8.2.1.5 8.2.1.6 8.2.1.7 8.2.1.8 8.2.2 Port A Circuit Type Port A register PADATA (Port A data register) PACR (Port A output control register) PAFR1 (Port A function register 1) PAPUP (Port A pull-up control register) PAPDN (Port A pull-down control register) PAIE (Port A input control register) Port B (PB0 to PB7).........................................................................................................................................................111 8.2.2.1 Port B Circuit Type iii 8.2.2.2 8.2.2.3 8.2.2.4 8.2.2.5 8.2.2.6 8.2.2.7 8.2.3 Port B Register PBDATA (Port B data register) PBCR (Port B output control register) PBFR1 (Port B function register 1) PBPUP (Port B pull-up control register) PBIE (Port B input control register) Port C (PC0 to PC3).........................................................................................................................................................115 8.2.3.1 8.2.3.2 8.2.3.3 8.2.3.4 8.2.3.5 8.2.4 Port C Circuit Type Port C Register PCDATA (Port C data register) PCPUP (Port C pull-up control register) PCIE (Port C input control register) Port D (PD0 to PD7)........................................................................................................................................................118 8.2.4.1 8.2.4.2 8.2.4.3 8.2.4.4 8.2.4.5 8.2.4.6 8.2.5 Port D Circuit Type Port D Register PDDATA (Port D data register) PDFR1 (Port D function register 1) PDPUP (Port D pull-up control register) PDIE (Port D input control register) Port E (PE0 to PE6).........................................................................................................................................................121 8.2.5.1 8.2.5.2 8.2.5.3 8.2.5.4 8.2.5.5 8.2.5.6 8.2.5.7 8.2.5.8 8.2.5.9 8.2.6 Port E Circuit Type Port E Register PEDATA (Port E data register) PECR (Port E output control register) PEFR1(Port E function register 1) PEFR2(Port E function register 2) PEOD (Port E open drain control register) PEPUP (Port E pull-up control register) PEIE (Port E input control register) Port F (PF0 to PF7)..........................................................................................................................................................126 8.2.6.1 8.2.6.2 8.2.6.3 8.2.6.4 8.2.6.5 8.2.6.6 8.2.6.7 8.2.6.8 8.2.6.9 8.2.7 Port F Circuit Type Port F Register PFDATA (Port F data register) PFCR (Port F output control register) PFFR1(Port F function register 1) PFFR2(Port F function register 2) PFOD (Port F open drain control register) PFPUP (Port F pull-up control register) PFIE (Port F input control register) Port G (PG0 to PG7)........................................................................................................................................................131 8.2.7.1 8.2.7.2 8.2.7.3 8.2.7.4 8.2.7.5 8.2.7.6 8.2.7.7 8.2.7.8 8.2.8 Port G Circuit Type Port G Register PGDATA (Port G data register) PGCR (Port G output control register) PGFR1(Port G function register 1) PGOD (Port G open drain control register) PGPUP (Port G pull-up control register) PGIE (Port G input control register) Port H (PH0 to PH7)........................................................................................................................................................136 8.2.8.1 8.2.8.2 8.2.8.3 8.2.8.4 8.2.8.5 8.2.8.6 8.2.8.7 8.2.9 Port H Circuit Type Port H Register PHDATA (Port H data register) PHCR (Port H output control register) PHFR1(Port H function register 1) PHPUP (Port H pull-up control register) PHIE (Port H input control register) Port I (PI0 to PI7).............................................................................................................................................................140 8.2.9.1 8.2.9.2 8.2.9.3 8.2.9.4 8.2.9.5 8.2.9.6 8.2.9.7 8.2.10 Port I Circuit Type Port I Register PIDATA(Port I data register) PICR (Port I output control register) PIFR1(Port I function register 1) PIPUP (Port I pull-up control register) PIIE (Port I input control register) Port J (PJ0 to PJ7)..........................................................................................................................................................144 8.2.10.1 8.2.10.2 8.2.10.3 8.2.10.4 8.2.10.5 8.2.10.6 8.2.10.7 8.2.11 Port K (PK0 to PK2)......................................................................................................................................................148 8.2.11.1 8.2.11.2 8.2.11.3 iv Port J Circuit Type Port J Register PJDATA (Port J data register) PJCR (Port J output control register) PJFR1(Port J function register 1) PJPUP (Port J pull-up control register) PJIE (Port J input control register) Port K Circuit Type Port K Register PKDATA(Port K data register) 8.2.11.4 8.2.11.5 8.2.11.6 8.2.11.7 8.2.11.8 8.3 Block Diagrams of Ports........................................................................................................153 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.3.17 8.3.18 8.3.19 8.4 PKCR (Port K output control register) PKFR1(Port K function register 1) PKFR2(Port K function register 2) PKPUP (Port K pull-up control register) PKIE (Port K input control register) Port Types........................................................................................................................................................................153 Type T1............................................................................................................................................................................154 Type T2............................................................................................................................................................................155 Type T3............................................................................................................................................................................156 Type T4............................................................................................................................................................................157 Type5 T5..........................................................................................................................................................................158 Type T6............................................................................................................................................................................159 Type T7............................................................................................................................................................................160 Type T8............................................................................................................................................................................161 Type T9..........................................................................................................................................................................162 Type T10........................................................................................................................................................................163 Type T11........................................................................................................................................................................164 Type T12........................................................................................................................................................................165 Type T13........................................................................................................................................................................166 Type T14........................................................................................................................................................................167 Type T15........................................................................................................................................................................168 Type T16........................................................................................................................................................................169 Type T17........................................................................................................................................................................170 Type T18........................................................................................................................................................................171 Appendix (Port setting List)..................................................................................................172 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 Port A Setting...................................................................................................................................................................172 Port B Setting...................................................................................................................................................................173 Port C Setting...................................................................................................................................................................174 Port D Setting...................................................................................................................................................................174 Port E Setting...................................................................................................................................................................175 Port F Setting...................................................................................................................................................................176 Port G Setting...................................................................................................................................................................177 Port H Setting...................................................................................................................................................................178 Port I Setting....................................................................................................................................................................179 Port J Setting..................................................................................................................................................................180 Port K Setting.................................................................................................................................................................181 9. 16-bit Timer/Event Counters(TMRB) 9.1 9.2 9.3 9.4 Outline...................................................................................................................................183 Differences in the Specifications...........................................................................................184 Configuration.........................................................................................................................185 Registers................................................................................................................................186 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.4.9 9.4.10 9.4.11 9.4.12 9.4.13 9.5 Register list according to channel....................................................................................................................................186 TBxEN (Enable register).................................................................................................................................................187 TBxRUN(RUN register)..................................................................................................................................................188 TBxCR(Control register).................................................................................................................................................189 TBxMOD(Mode register)................................................................................................................................................190 TBxFFCR(Flip-flop control register)..............................................................................................................................191 TBxST(Status register)....................................................................................................................................................192 TBxIM(Interrupt mask register)......................................................................................................................................193 TBxUC(Up counter capture register)..............................................................................................................................193 TBxRG0(Timer register 0)............................................................................................................................................194 TBxRG1(Timer register 1)............................................................................................................................................194 TBxCP0(Capture register 0)..........................................................................................................................................195 TBxCP1(Capture register 1)..........................................................................................................................................195 Description of Operations for Each Circuit...........................................................................196 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 Prescaler...........................................................................................................................................................................196 Up-counter (UC)..............................................................................................................................................................200 Timer registers (TBxRG0, TBxRG1)..............................................................................................................................200 Capture.............................................................................................................................................................................201 Capture registers (TBxCP0, TBxCP1).............................................................................................................................201 v 9.5.6 9.5.7 9.5.8 9.5.9 9.6 Up-counter capture register (TBxUC).............................................................................................................................201 Comparators (CP0, CP1).................................................................................................................................................201 Timer Flip-flop (TBxFF0)...............................................................................................................................................201 Capture interrupt (INTCAPx0, INTCAPx1)...................................................................................................................201 Description of Operations for Each Mode.............................................................................202 9.6.1 9.6.2 9.6.3 9.6.4 9.7 16-bit Interval Timer Mode.............................................................................................................................................202 16-bit Event Counter Mode.............................................................................................................................................202 16-bit PPG (Programmable Pulse Generation) Output Mode.........................................................................................203 Timer synchronous mode.................................................................................................................................................205 Applications using the Capture Function..............................................................................206 9.7.1 9.7.2 9.7.3 9.7.4 One-shot pulse output triggered by an external pulse......................................................................................................206 Frequency measurement..................................................................................................................................................208 Pulse width measurement................................................................................................................................................209 Time Difference Measurement........................................................................................................................................210 10. Serial Channel (SIO/UART) 10.1 10.2 10.3 10.4 Overview.............................................................................................................................211 Difference in the Specifications of SIO Modules................................................................211 Configuration.......................................................................................................................212 Registers Description...........................................................................................................213 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 10.4.12 10.4.13 10.5 10.6 Registers List in Each Channel......................................................................................................................................213 SCxEN (Enable Register)..............................................................................................................................................214 SCxBUF (Buffer Register)............................................................................................................................................215 SCxCR (Control Register).............................................................................................................................................216 SCxMOD0 (Mode Control Register 0)..........................................................................................................................217 SCxMOD1 (Mode Control Register 1)..........................................................................................................................218 SCxMOD2 (Mode Control Register 2)..........................................................................................................................219 SCxBRCR (Baud Rate Generator Control Register), SCxBRADD (Baud Rate Generator Control Register 2)..........221 SCxFCNF ( FIFO Configuration Register)...................................................................................................................223 SCxRFC (RX FIFO Configuration Register)..............................................................................................................224 SCxTFC (TX FIFO Configuration Register) (Note2).................................................................................................225 SCxRST (RX FIFO Status Register)...........................................................................................................................226 SCxTST (TX FIFO Status Register)............................................................................................................................227 Operation in Each Mode......................................................................................................228 Data Format.........................................................................................................................229 10.6.1 10.6.2 Data Format List............................................................................................................................................................229 Parity Control.................................................................................................................................................................230 10.6.2.1 10.6.2.2 10.6.3 10.7 Transmission Receiving Data STOP Bit Length...........................................................................................................................................................230 Clock Control.......................................................................................................................231 10.7.1 10.7.2 Prescaler.........................................................................................................................................................................231 Serial Clock Generation Circuit.....................................................................................................................................235 10.7.2.1 10.7.2.2 10.8 Baud Rate Generator Clock Selection Circuit Transmit/Receive Buffer and FIFO.....................................................................................239 10.8.1 10.8.2 10.8.3 Configuration.................................................................................................................................................................239 Transmit/Receive Buffer................................................................................................................................................239 FIFO...............................................................................................................................................................................239 10.9 Status Flag...........................................................................................................................240 10.10 Error Flag...........................................................................................................................240 10.10.1 10.10.2 10.10.3 10.11 10.11.1 10.11.2 OERR Flag...................................................................................................................................................................240 PERR Flag...................................................................................................................................................................241 FERR Flag...................................................................................................................................................................241 Receive..............................................................................................................................242 Receive Counter...........................................................................................................................................................242 Receive Control Unit...................................................................................................................................................242 10.11.2.1 10.11.2.2 10.11.3 vi I/O interface mode UART Mode Receive Operation........................................................................................................................................................242 10.11.3.1 10.11.3.2 10.11.3.3 10.11.3.4 10.11.3.5 10.11.3.6 10.12 Receive Buffer Receive FIFO Operation I/O interface mode with SCLK output Read Received Data Wake-up Function Overrun Error Transmission......................................................................................................................246 10.12.1 10.12.2 Transmission Counter..................................................................................................................................................246 Transmission Control...................................................................................................................................................246 10.12.2.1 10.12.2.2 10.12.3 Transmit Operation......................................................................................................................................................246 10.12.3.1 10.12.3.2 10.12.3.3 10.12.3.4 10.13 10.14 I/O Interface Mode UART Mode Operation of Transmission Buffer Transmit FIFO Operation I/O interface Mode/Transmission by SCLK Output Under-run error Handshake function...........................................................................................................250 Interrupt/Error Generation Timing....................................................................................251 10.14.1 RX Interrupts...............................................................................................................................................................251 10.14.1.1 10.14.1.2 10.14.2 TX interrupts................................................................................................................................................................252 10.14.2.1 10.14.2.2 10.14.3 Single Buffer / Double Buffer FIFO Error Generation..........................................................................................................................................................253 10.14.3.1 10.14.3.2 10.15 10.16 Single Buffer / Double Buffer FIFO UART Mode IO Interface Mode Software Reset...................................................................................................................253 Operation in Each Mode....................................................................................................254 10.16.1 Mode 0 (I/O interface mode).......................................................................................................................................254 10.16.1.1 10.16.1.2 10.16.1.3 10.16.2 10.16.3 10.16.4 Transmitting Data Receive Transmit and Receive (Full-duplex) Mode 1 (7-bit UART mode)........................................................................................................................................265 Mode 2 (8-bit UART mode)........................................................................................................................................265 Mode 3 (9-bit UART mode)........................................................................................................................................266 10.16.4.1 10.16.4.2 Wakeup function Protocol 11. Serial Bus Interface (I2C/SIO) 11.1 11.2 Configuration.......................................................................................................................270 Register................................................................................................................................271 11.2.1 11.3 11.4 Registers for each channel.............................................................................................................................................271 I2C Bus Mode Data Format.................................................................................................272 Control Registers in the I2C Bus Mode...............................................................................273 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.5 SBIxCR0(Control register 0).........................................................................................................................................273 SBIxCR1(Control register 1).........................................................................................................................................274 SBIxCR2(Control register 2).........................................................................................................................................276 SBIxSR (Status Register)...............................................................................................................................................277 SBIxBR0(Serial bus interface baud rate register 0).......................................................................................................278 SBIxDBR (Serial bus interface data buffer register).....................................................................................................278 SBIxI2CAR (I2Cbus address register)..........................................................................................................................279 Control in the I2C Bus Mode...............................................................................................280 11.5.1 Serial Clock....................................................................................................................................................................280 11.5.1.1 11.5.1.2 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 11.5.9 Clock source Clock Synchronization Setting the Acknowledgement Mode.............................................................................................................................281 Setting the Number of Bits per Transfer........................................................................................................................281 Slave Addressing and Address Recognition Mode........................................................................................................281 Operating mode..............................................................................................................................................................281 Configuring the SBI as a Transmitter or a Receiver......................................................................................................282 Configuring the SBI as a Master or a Slave...................................................................................................................282 Generating Start and Stop Conditions...........................................................................................................................282 Interrupt Service Request and Release..........................................................................................................................283 vii 11.5.10 11.5.11 11.5.12 11.5.13 11.5.14 11.5.15 11.5.16 11.6 Arbitration Lost Detection Monitor.............................................................................................................................283 Slave Address Match Detection Monitor.....................................................................................................................285 General-call Detection Monitor...................................................................................................................................285 Last Received Bit Monitor...........................................................................................................................................285 Data Buffer Register (SBIxDBR)................................................................................................................................285 Baud Rate Register (SBIxBR0)...................................................................................................................................285 Software Reset.............................................................................................................................................................285 Data Transfer Procedure in the I2C Bus ModeI2C.............................................................286 11.6.1 11.6.2 Device Initialization.......................................................................................................................................................286 Generating the Start Condition and a Slave Address.....................................................................................................286 11.6.2.1 11.6.2.2 11.6.3 Transferring a Data Word..............................................................................................................................................288 11.6.3.1 11.6.3.2 11.6.4 11.6.5 11.7 Master mode Slave mode Master mode ( = "1") Slave mode ( = "0") Generating the Stop Condition......................................................................................................................................293 Restart Procedure...........................................................................................................................................................293 Control register of SIO mode..............................................................................................295 11.7.1 11.7.2 11.7.3 11.7.4 11.7.5 11.7.6 11.8 SBIxCR0(control register 0)..........................................................................................................................................295 SBIxCR1(Control register 1).........................................................................................................................................296 SBIxDBR (Data buffer register)....................................................................................................................................297 SBIxCR2(Control register 2).........................................................................................................................................298 SBIxSR (Status Register)...............................................................................................................................................299 SBIxBR0 (Baud rate register 0).....................................................................................................................................300 Control in SIO mode............................................................................................................301 11.8.1 Serial Clock....................................................................................................................................................................301 11.8.1.1 11.8.1.2 11.8.2 Clock source Shift Edge Transfer Modes..............................................................................................................................................................303 11.8.2.1 11.8.2.2 11.8.2.3 11.8.2.4 8-bit transmit mode 8-bit receive mode 8-bit transmit/receive mode Data retention time of the last bit at the end of transmission 12. Analog/Digital Converter (ADC) 12.1 12.2 12.3 Outline.................................................................................................................................309 Configuration.......................................................................................................................310 Registers..............................................................................................................................311 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.3.9 12.3.10 12.3.11 12.3.12 12.3.13 12.3.14 12.3.15 12.3.16 12.3.17 12.3.18 12.3.19 12.3.20 12.4 Register list....................................................................................................................................................................311 ADCBAS (Conversion Accuracy Setting Register)......................................................................................................312 ADCLK (Conversion Clock Setting Register)..............................................................................................................313 ADMOD0 (Mode Control Register 0) ..........................................................................................................................314 ADMOD1 (Mode Control Register 1)...........................................................................................................................315 ADMOD2 (Mode Control Register 2) ..........................................................................................................................317 ADMOD4 (Mode Control Register 4) ..........................................................................................................................319 ADMOD3 (Mode Control Register 3)...........................................................................................................................320 ADMOD5 (Mode Control Register 5)...........................................................................................................................321 ADREG08 (Conversion Result Register 08)...............................................................................................................322 ADREG19 (AD Conversion Result Register 19)........................................................................................................323 ADREG2A (AD Conversion Result Register 2A)......................................................................................................324 ADREG3B (AD Conversion Result Register 3B).......................................................................................................325 ADREG4C (AD Conversion Result Register 4C).......................................................................................................326 ADREG5D (AD Conversion Result Register 5D)......................................................................................................327 ADREG6E (AD Conversion Result Register 6E).......................................................................................................328 ADREG7F (AD Conversion Result Register 7F)........................................................................................................329 ADREGSP (AD Conversion Result Register SP).......................................................................................................330 ADCMP0 (AD Conversion Result Comparison Register 0).......................................................................................331 ADCMP1 (AD Conversion Result Comparison Register 1).......................................................................................331 Description of Operations....................................................................................................332 12.4.1 12.4.2 Analog Reference Voltage.............................................................................................................................................332 AD Conversion Mode....................................................................................................................................................332 12.4.2.1 12.4.2.2 viii Normal AD conversion Top-priority AD conversion 12.4.3 12.4.4 12.4.5 AD Monitor Function....................................................................................................................................................333 Selecting the Input Channel...........................................................................................................................................334 AD Conversion Details..................................................................................................................................................334 12.4.5.1 12.4.5.2 12.4.5.3 12.4.5.4 12.4.5.5 12.4.5.6 12.4.5.7 Starting AD Conversion AD Conversion Top-priority AD conversion during normal AD conversion Stopping Repeat Conversion Mode Reactivating normal AD conversion Conversion completion Interrupt generation timings and AD conversion result storage register 13. Watchdog Timer(WDT) 13.1 13.2 Configuration.......................................................................................................................341 Register................................................................................................................................342 13.2.1 13.2.2 13.3 WDMOD(Watchdog Timer Mode Register) ................................................................................................................342 WDCR (Watchdog Timer Control Register).................................................................................................................343 Operations............................................................................................................................344 13.3.1 13.3.2 13.4 Basic Operation..............................................................................................................................................................344 Operation Mode and Status............................................................................................................................................344 Operation when malfunction (runaway) is detected............................................................345 13.4.1 13.4.2 13.5 INTWDT interrupt generation.......................................................................................................................................345 Internal reset generation.................................................................................................................................................346 Control register....................................................................................................................347 13.5.1 13.5.2 13.5.3 Watchdog Timer Mode Register (WDMOD)................................................................................................................347 Watchdog Timer Control Register(WDCR)..................................................................................................................347 Setting example..............................................................................................................................................................348 13.5.3.1 13.5.3.2 13.5.3.3 13.5.3.4 Disabling control Enabling control Watchdog timer clearing control Detection time of watchdog timer 14. Real Time Clock (RTC) 14.1 14.2 14.3 Function...............................................................................................................................349 Block Diagram.....................................................................................................................349 Detailed Description Register..............................................................................................350 14.3.1 14.3.2 14.3.3 Register List...................................................................................................................................................................350 Control Register.............................................................................................................................................................350 Detailed Description of Control Register......................................................................................................................352 14.3.3.1 14.3.3.2 14.3.3.3 14.3.3.4 14.3.3.5 14.3.3.6 14.3.3.7 14.3.3.8 14.3.3.9 14.3.3.10 14.3.3.11 14.4 14.4.1 14.4.2 14.4.3 14.5 14.5.1 14.5.2 14.5.3 RTCSECR (Second column register (for PAGE0 only)) RTCMINR (Minute column register (PAGE0/1)) RTCHOURR (Hour column register(PAGE0/1)) RTCDAYR (Day of the week column register(PAGE0/1)) RTCDATER (Day column register (for PAGE0/1 only)) RTCMONTHR (Month column register (for PAGE0 only)) RTCMONTHR (Selection of 24-hour clock or 12-hour clock24(for PAGE1 only)) RTCYEARR (Year column register (for PAGE0 only)) RTCYEARR (Leap year register (for PAGE1 only)) RTCPAGER(PAGE register(PAGE0/1)) RTCRESTR (Reset register (for PAGE0/1)) Operational Description.......................................................................................................359 Reading clock data.........................................................................................................................................................359 Writing clock data..........................................................................................................................................................359 Entering the Low Power Consumption Mode...............................................................................................................361 Alarm function.....................................................................................................................362 "Low" pulse (when the alarm register corresponds with the clock).............................................................................362 1Hz cycle "Low" pulse1 Hz...........................................................................................................................................363 16Hz cycle "Low" pulse16 Hz.......................................................................................................................................363 ix 15. Flash Memory Operation 15.1 Flash Memory......................................................................................................................365 15.1.1 15.1.2 15.2 Features..........................................................................................................................................................................365 Block Diagram of the Flash Memory Section...............................................................................................................367 Operation Mode...................................................................................................................368 15.2.1 15.2.2 Reset Operation..............................................................................................................................................................369 User Boot Mode (Single chip mode).............................................................................................................................370 15.2.2.1 15.2.2.2 15.2.3 (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1-B) Method 2: Transferring a Programming Routine from an External Host Single Boot Mode..........................................................................................................................................................378 15.2.3.1 15.2.4 15.2.5 15.2.6 15.2.7 15.2.8 15.2.9 (2-A) Using the Program in the On-Chip Boot ROM Configuration for Single Boot Mode.............................................................................................................................381 Memory Map.................................................................................................................................................................382 Interface specification....................................................................................................................................................383 Data Transfer Format.....................................................................................................................................................384 Restrictions on internal memories.................................................................................................................................384 Transfer Format for Single Boot Mode commands.......................................................................................................384 15.2.9.1 15.2.9.2 15.2.9.3 15.2.9.4 15.2.10 RAM Transfer Show Flash Memory SUM Transfer Format for the Show Product Information Chip Erase and Protect Bit Erase Operation of Boot Program..........................................................................................................................................391 15.2.10.1 15.2.10.2 15.2.10.3 15.2.10.4 15.2.10.5 15.2.10.6 15.2.10.7 15.2.10.8 15.2.10.9 15.2.11 15.3 RAM Transfer Command Show Flash Memory SUM Command Show Product Information Command Chip and Protection Bit Erase Command Acknowledge Responses Determination of a Serial Operation Mode Password Calculation of the Show Flash Memory Sum Command Checksum Calculation General Boot Program Flowchart................................................................................................................................405 On-board Programming of Flash Memory (Rewrite/Erase)................................................406 15.3.1 Flash Memory................................................................................................................................................................406 15.3.1.1 15.3.1.2 15.3.1.3 15.3.1.4 15.3.1.5 15.3.1.6 15.3.1.7 15.3.1.8 Block Configuration Basic operation Reset(Hardware reset) Commands Flash control/ status register List of Command Sequences Address bit configuration for bus write cycles Flowchart 16. ROM protection 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.4 16.4.1 16.4.2 Outline.................................................................................................................................421 Future...................................................................................................................................421 Write/ erase-protection function....................................................................................................................................421 Security function............................................................................................................................................................421 Register................................................................................................................................422 FCFLCS (Flash control register)...................................................................................................................................423 FCSECBIT(Security bit register)...................................................................................................................................424 Writing and erasing..............................................................................................................425 Protection bits................................................................................................................................................................425 Security bit.....................................................................................................................................................................425 17. Electrical Characteristics 17.1 x Absolute Maximum Ratings................................................................................................427 17.2 17.3 17.4 DC Electrical Characteristics (1/3)......................................................................................428 DC Electrical Characteristics (2/3)......................................................................................429 DC Electrical Characteristics (3/3)......................................................................................430 17.4.1 17.4.2 17.5 17.6 TMPM333FDFG/TMPM333FYFG..............................................................................................................................430 TMPM333FWFG...........................................................................................................................................................430 10-bit ADC Electrical Characteristics.................................................................................431 AC Electrical Characteristics...............................................................................................432 17.6.1 17.6.2 AC measurement condition...........................................................................................................................................432 Serial Channel (SIO/UART)..........................................................................................................................................432 17.6.2.1 17.6.3 17.6.3.1 17.6.3.2 17.6.4 17.6.5 17.6.6 17.6.7 17.6.8 17.6.9 17.6.10 17.7.1 17.8 17.8.1 17.8.2 17.9 17.9.1 17.9.2 I2C Mode Clock-Synchronous 8-Bit SIO mode Event Counter................................................................................................................................................................436 Capture...........................................................................................................................................................................436 External Interrupt...........................................................................................................................................................436 NMI................................................................................................................................................................................437 SCOUT Pin AC Characteristic......................................................................................................................................437 Debug Communication..................................................................................................................................................438 17.6.9.1 17.6.9.2 17.7 I/O Interface mode Serial Bus Interface(I2C/SIO).......................................................................................................................................434 SWD Interface JTAG Interface ETM Trace...................................................................................................................................................................439 Flash Characteristics............................................................................................................439 Rewriting.......................................................................................................................................................................439 Recommended Oscillation Circuit.......................................................................................440 Ceramic oscillator..........................................................................................................................................................440 Crystal oscillator............................................................................................................................................................440 Handling Precaution............................................................................................................441 Solderability...................................................................................................................................................................441 Power-on sequence........................................................................................................................................................441 18. Port Section Equivalent Circuit Schematic 18.1 PA0, PB1 to 2, PE1 to 3, PE5 to 6, PF1 to 7, PG0 to 6, PH0 to 7, PI6 to 7, PJ0 to 3, PJ6 to 7 ................................................................................................................................................443 18.2 PA1......................................................................................................................................443 18.3 PA2 to 7, PB0, PB3 to 7, PE0, PE4, PF0, PG7, PI0 to 5, PJ4 to 5, PK1 to 2.....................444 18.4 PC0 to 3, PD4 to 7...............................................................................................................444 18.5 PD0 to 3...............................................................................................................................444 18.6 PK0......................................................................................................................................445 18.7 NMI, MODE........................................................................................................................445 18.8 RESET.................................................................................................................................445 18.9 X1, X2..................................................................................................................................446 18.10 XT1, XT2...........................................................................................................................446 18.11 VREFH, AVSS..................................................................................................................446 19. Package Dimensions xi xii TMPM333FDFG/FYFG/FWFG TMPM333FDFG/FYFG/FWFG The TMPM333FDFG/FYFG/FWFG is a 32-bit RISC microprocessor series with an ARM Cortex™-M3 microprocessor core. ROM Product Name RAM (FLASH) TMPM333FDFG 512 Kbyte 32 Kbyte TMPM333FYFG 256 Kbyte 16 Kbyte TMPM333FWFG 128 Kbyte 8 Kbyte Package LQFP100-P-1414-0.50H Features of the TMPM333FDFG/FYFG/FWFG are as follows: 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb® -2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ New 32-bit Thumb instructions for improved performance ・ New Thumb mixed 16-/32-bit instruction set can produce faster, more efficient code. b. Both high performance and low power consumption have been achieved. [High performance] ・ A 32-bit multiplication (32×32=32 bit) can be executed with one clock. ・ Division takes between 2 and 12 cycles depending on dividend and devisor [Low power consumption] ・ Optimized design using a low power consumption library ・ Standby function that stops the operation of the micro controller core c. High-speed interrupt response suitable for real-time control ・ An interruptible long instruction. ・ Stack push automatically handled by hardware. 2. On Chip program memory and data memory Product name On chip Flash ROM On chip RAM TMPM333FDFG 512 Kbyte 32 Kbyte TMPM333FYFG 256 Kbyte 16 Kbyte TMPM333FWFG 128 Kbyte 8 Kbyte 3. 16-bit timer (TMRB): 10 channels ・ 16-bit interval timer mode ・ 16-bit event counter mode ・ 16-bit PPG output ・ Input capture function 4. Real time clock (RTC): 1 channel ・ Clock (hour, minute and second) ・ Calendar (month, week, date and leap year) Page 1 1.1 Features TMPM333FDFG/FYFG/FWFG ・ Time correction + or − 30seconds (by software) ・ Alarm (Alarm output) ・ Alarm interrupt 5. Watchdog timer (WDT): 1 channel Watchdog timer (WDT) generates a reset or a non-maskable interrupt (NMI). 6. General-purpose serial interface (SIO/UART): 3 channels Either UART mode or synchronous mode can be selected (4byte FIFO equipped) 7. Serial bus interface (I2C/SIO): 3channels Either I2C bus mode or synchronous mode can be selected. 8. 10-bit AD converter (ADC): 12 channels ・ Start by an internal timer trigger ・ Fixed channel/scan mode ・ Single/repeat mode ・ AD monitoring 2ch ・ Conversion speed 1.15μsec. (@fsys = 40MHz) 9. Interrupt source ・ Internal: 38 factors...The order of precedence can be set over 7 levels (except the watchdog timer interrupt). ・ External: 8 factors...The order of precedence can be set over 7 levels. 10. Non-maskable interrupt (NMI) Non-maskable interrupt (NMI) is generated by a watchdog timer or a NMI pin. 11. Input/ output ports (PORT): 78 pins 12. Standby mode ・ Standby modes: IDLE, SLOW, SLEEP, STOP ・ Sub clock operation(32.768kHz):SLOW, SLEEP 13. Clock generator (CG) ・ On-chip PLL (quadrupled) ・ Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 14. Endian Little endian 15. Maximum operating frequency: 40 MHz 16. Operating voltage range 2.7 V to 3.6 V (with on-chip regulator) 17. Temperature range ・ -20 to 85 degrees (except during Flash writing/ erasing) ・ 0 to 70 degrees (during Flash writing/ erasing) 18. Package LQFP100-P-1414-0.50H (14mm × 14mm, 0.5mm pitch) Page 2 TMPM333FDFG/FYFG/FWFG 1.2 Block Diagram D-Code Debug FLASH I/F RAM I/F BOOTROM I-Code System AHB-Bus-Matrix Cortex-M3 CPU I/F NVIC Bus Bridge CG PORT A~K SIO/UART (3ch) TMRB (10ch) I/O-Bus I2C/SIO (3ch) WDT RTC ADC (12ch) Figure 1-1 TMPM333FDFG/FYFG/FWFGBlock Diagram Page 3 Pin Layout (Top view) Pin Layout (Top view) 55 60 65 70 50 80 45 85 TMPM333FDFG TMPM333FYFG TMPM333FWFG 40 Top View 35 90 95 25 20 15 100 10 30 5 RVDD3 XT1 XT2 TB4IN0/PI6 NMI MODE RESET TB4IN1/PI7 TB3IN0/PH6 TB3IN1/PH7 INT2/PJ2 INT3/PJ3 TB6OUT/PJ4 PE3 TEST4 AIN0/PC0 AIN1/PC1 AIN2/PC2 AIN3/PC3 TB5IN0/AIN4/PD0 TB5IN1/AIN5/PD1 TB6IN0/AIN6/PD2 TB6IN1/AIN7/PD3 AIN8/PD4 AIN9/PD5 75 RVSS X1 DVSS X2 DVDD3 PJ0/INT0 PA7 PA6/TRACEDATA3 PA5/TRACEDATA2 PA4/TRACEDATA1 PA3/TRACEDATA0 PA2/TRACECLK DVSS DVDD3 PF3 PB2/TRST PB1/TDI PJ7/INT7 TEST3 PA1/TCK/SWCLK PA0/TMS/SWDIO PB0/TDO/SWV PI5/TB5OUT PI4/TB4OUT PK1/SCOUT/ALARM Figure 1-2 shows the pin layout of TMPM333FDFG/FYFG/FWFG. 1 1.3 TMPM333FDFG/FYFG/FWFG AIN10/PD6 AIN11/PD7 AVSS VREFH AVDD3 INT4/PG3 TB9OUT/PK2 TB7OUT/PJ5 TB2IN0/PH4 TB2IN1/PH5 TB8OUT/PG7 TEST2 DVSS DVDD3 SDA2/SO2/PG4 SCL2/SI2/PG5 SCK2/PG6 TEST1 INT5/PF7 TXD0/PE0 RXD0/PE1 CTS0/SCLK0/PE2 TXD1/PE4 RXD1/PE5 CTS1/SCLK1/PE6 1.3 Figure 1-2 Pin Layout (LQFP100) Page 4 PK0 PJ1/INT1 PI3/TB3OUT PB7 PF6/SCK1 PF5/SI1/SCL1 PF4/SO1/SDA1 PB6 PI2/TB2OUT PB5 PI1/TB1OUT PJ6/INT6 PI0/TB0OUT PB4 PH3/TB1IN1 PF2/SCLK2/CTS2 PF1/RXD2 PF0/TXD2 PH2/TB1IN0 PH1/TB0IN1 PH0/TB0IN0/BOOT PB3 PG2/SCK0 PG1/SI0/SCL0 PG0/SO0/SDA0 TMPM333FDFG/FYFG/FWFG 1.4 Pin names and Functions Table 1-1 and Table 1-2 sort the input and output pins of the TMPM333FDFG/FYFG/FWFG by pin or port. Each table includes alternate pin names and functions for multi-function pins. 1.4.1 Sorted by Pin Table 1-1 Pin Names and Functions Sorted by Pin (1/6) Type Pin No. Function 1 Function 2 PS Pin Name Input/ Output Function PD6 I Input port AIN10 I Analog input PD7 I Input port AIN11 I Analog input 3 AVSS I PS 4 VREFH I PS 5 AVDD3 I Function 6 PG3 I/O I/O port INT4 I External interrupt pin Function 7 PK2 I/O I/O port TB9OUT O Timer B output Function 8 PJ5 I/O I/O port TB7OUT O Timer B output Function 9 PH4 I/O I/O port TB2IN0 I Inputting the timer B capture trigger Function 10 PH5 I/O I/O port TB2IN1 I Inputting the timer B capture trigger Function 11 PG7 I/O I/O port TB8OUT O Timer B output Test 12 TEST2 − PS 13 DVSS − GND pin PS 14 DVDD3 − Power supply pin PG4 I/O If the serial bus interface operates SDA2/SO2 I/O -in the I2C mode: data pin AD converter: GND pin (0V) (note) AVSS must be connected to GND even if the A/D converter is not used. Supplying the AD converter with a reference power supply. (note) VREFH must be connected to power supply even if A/D converter is not used. Supplying the AD converter with a power supply. (note) AVDD must be connected to power supply even if A/D converter is not used. TEST pin: (note) TEST pin must be left OPEN. I/O port Function 15 -in the SIO mode: data pin I/O port Function 16 PG5 I/O If the serial bus interface operates SCL2/SI2 I/O -in the I2C mode: clock pin -in the SIO mode: data pin Function 17 Test 18 PG6 I/O I/O port SCK2 I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. TEST1 − TEST pin: (note) TEST pin must be left OPEN. Page 5 1.4 Pin names and Functions TMPM333FDFG/FYFG/FWFG Table 1-1 Pin Names and Functions Sorted by Pin (2/6) Type Pin No. Function 19 Function 20 Function 21 Function 22 Function 23 Function 24 Function 25 Function Function 26 27 Function 28 Function 29 Function/ Control 30 Pin Name Input/ Output Function PF7 I/O I/O port INT5 I External interrupt pin PE0 I/O I/O port TXD0 O Sending serial data PE1 I/O I/O port RXD0 I Receiving serial data PE2 I/O I/O port SCLK0 I/O Serial clock input/ output CTS0 I Handshake input pin PE4 I/O I/O port TXD1 O Sending serial data PE5 I/O I/O port RXD1 I Receiving serial data PE6 I/O I/O port SCLK1 I/O Serial clock input/ output CTS1 I Handshake input pin PG0 I/O SDA0/SO0 I/O PG1 I/O SCL0/SI0 I/O PG2 I/O I/O port SCK0 I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. PB3 I/O I/O port PH0 I/O I/O port TB0IN0 I Inputting the timer B capture trigger BOOT I Setting a single boot mode: I/O port -in the I2C mode: data pin -in the SIO mode: data pin I/O port -in the I2C mode: clock pin -in the SIO mode: data pin (note) This pin goes into single boot mode by sampling "Low" at the rise of a RESET signal. Function 31 Function 32 Function 33 Function 34 Function 35 PH1 I/O I/O port TB0IN1 I Inputting the timer B capture trigger PH2 I/O I/O port TB1IN0 I Inputting the timer B capture trigger PF0 I/O I/O port TXD2 O Sending serial data PF1 I/O I/O port RXD2 I Receiving serial data PF2 I/O I/O port SCLK2 I/O Serial clock input/ output CTS2 I Handshake input pin Page 6 TMPM333FDFG/FYFG/FWFG Table 1-1 Pin Names and Functions Sorted by Pin (3/6) Type Pin No. Function 36 Function 37 Function 38 Function 39 Function 40 Function 41 Function 42 Function 43 Function 44 Function 45 Function 46 Function 47 Function 48 Function 49 Function 50 Function 51 Function 52 Function 53 Function/ Debug Function/ Debug 54 55 Pin Name Input/ Output Function PH3 I/O I/O port TB1IN1 I Inputting the timer B capture trigger PB4 I/O I/O port PI0 I/O I/O port TB0OUT O Timer B output PJ6 I/O I/O port INT6 I External interrupt pin PI1 I/O I/O port TB1OUT O Timer B output PB5 I/O I/O port PI2 I/O I/O port TB2OUT O Timer B output PB6 I/O I/O port PF4 I/O SDA1/SO1 I/O PF5 I/O SCL1/SI1 I/O PF6 I/O I/O port SCK1 I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. PB7 I/O I/O port PI3 I/O I/O port TB3OUT O Timer B output PJ1 I/O I/O port INT1 I External interrupt pin PK0 I/O PK1 I/O I/O port SCOUT O System clock output ALARM O Alarm output PI4 I/O I/O port TB4OUT O Timer B output PI5 I/O I/O port TB5OUT O Timer B output PB0 I/O I/O port TDO/SWV O Debug pin PA0 I/O I/O port TMS/SWDIO I/O Debug pin I/O port -in the I2C mode: data pin -in the SIO mode: data pin I/O port -in the I2C mode: clock pin -in the SIO mode: data pin I/O port (note) Nch open drain port. Page 7 1.4 Pin names and Functions TMPM333FDFG/FYFG/FWFG Table 1-1 Pin Names and Functions Sorted by Pin (4/6) Type Function/ Debug Pin No. 56 Test 57 Function 58 Function/ Debug Function/ Debug 59 60 Pin Name Input/ Output Function PA1 I/O I/O port TCK/SWCLK I Debug pin TEST3 − PJ7 I/O I/O port INT7 I External interrupt pin PB1 I/O I/O port TDI I Debug pin PB2 I/O I/O port TRST I Debug pin TEST pin: (note) TEST pin must be left OPEN. Function 61 PF3 I/O I/O port PS 62 DVDD3 − Power supply pin PS 63 DVSS − GND pin PA2 I/O I/O port TRACECLK O Debug pin PA3 I/O I/O port TRACEDATA0 O Debug pin PA4 I/O I/O port TRACEDATA1 O Debug pin PA5 I/O I/O port TRACEDATA2 O Debug pin PA6 I/O I/O port TRACEDATA3 O Debug pin PA7 I/O I/O port PJ0 I/O I/O port INT0 I External interrupt pin Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug 64 65 66 67 68 Function 69 Function 70 PS 71 DVDD3 − Power supply pin Clock 72 X2 O Connected to a high-speed oscillator. PS 73 DVSS − GND pin Clock 74 X1 I Connected to a high-speed oscillator. PS 75 RVSS − GND pin PS 76 RVDD3 − Power supply pin Clock 77 XT1 I Connected to a low-speed oscillator. Clock 78 XT2 O Connected to a low-speed oscillator. Function 79 PI6 I/O I/O port TB4IN0 I Inputting the timer B capture trigger Page 8 TMPM333FDFG/FYFG/FWFG Table 1-1 Pin Names and Functions Sorted by Pin (5/6) Type Pin No. Function 80 NMI I Control 81 MODE I Function 82 RESET I Function 83 PI7 I/O I/O port TB4IN1 I Inputting the timer B capture trigger Function 84 PH6 I/O I/O port TB3IN0 I Inputting the timer B capture trigger Function 85 PH7 I/O I/O port TB3IN1 I Inputting the timer B capture trigger Function 86 PJ2 I/O I/O port INT2 I External interrupt pin Function 87 PJ3 I/O I/O port INT3 I External interrupt pin Function 88 PJ4 I/O I/O port TB6OUT O Timer B output Function 89 PE3 I/O I/O port Test 90 TEST4 − Function 91 PC0 I Input port AIN0 I Analog input Function 92 PC1 I Input port AIN1 I Analog input Function 93 PC2 I Input port AIN2 I Analog input Function 94 PC3 I Input port AIN3 I Analog input PD0 I Input port Function 95 AIN4 I Analog input TB5IN0 I Inputting the timer B capture trigger PD1 I Input port AIN5 I Analog input TB5IN1 I Inputting the timer B capture trigger Function 96 Pin Name Input/ Output Function Non-maskable interrupt (note) With a noise filter (about 30ns (typical value)) Mode pin: (note) MODE pin must be connected to GND. Reset input pin (note) With a pull-up and a noise filter (about 30ns (typical value)) TEST pin: (note) TEST pin must be left OPEN. Page 9 1.4 Pin names and Functions TMPM333FDFG/FYFG/FWFG Table 1-1 Pin Names and Functions Sorted by Pin (6/6) Type Pin No. Function 97 Function 98 Function 99 Function 100 Pin Name Input/ Output Function PD2 I Input port AIN6 I Analog input TB6IN0 I Inputting the timer B capture trigger PD3 I Input port AIN7 I Analog input TB6IN1 I Inputting the timer B capture trigger PD4 I Input port AIN8 I Analog input PD5 I Input port AIN9 I Analog input Page 10 TMPM333FDFG/FYFG/FWFG 1.4.2 Sorted by Port Table 1-2 Pin Names and Functions Sorted by Port (1/5) PORT PORT A PORT A PORT A PORT A PORT A PORT A PORT A PORT A PORT B PORT B PORT B Type Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function Function/ Debug Function/ Debug Function/ Debug Pin No. 55 56 64 65 66 67 68 69 54 59 60 Pin Name Input/ Output Function PA0 I/O I/O port TMS/SWDIO I/O Debug pin PA1 I/O I/O port TCK/SWCLK I Debug pin PA2 I/O I/O port TRACECLK O Debug pin PA3 I/O I/O port TRACEDATA0 O Debug pin PA4 I/O I/O port TRACEDATA1 O Debug pin PA5 I/O I/O port TRACEDATA2 O Debug pin PA6 I/O I/O port TRACEDATA3 O Debug pin PA7 I/O I/O port PB0 I/O I/O port TDO/SWV O Debug pin PB1 I/O I/O port TDI I Debug pin PB2 I/O I/O port TRST I Debug pin PORT B Function 29 PB3 I/O I/O port PORT B Function 37 PB4 I/O I/O port PORT B Function 41 PB5 I/O I/O port PORT B Function 43 PB6 I/O I/O port PORT B Function 47 PB7 I/O I/O port PORT C Function 91 PC0 I Input port AIN0 I Analog input PORT C Function 92 PC1 I Input port AIN1 I Analog input PORT C Function 93 PC2 I Input port AIN2 I Analog input PORT C Function 94 PC3 I Input port AIN3 I Analog input PD0 I Input port PORT D Function 95 AIN4 I Analog input TB5IN0 I Inputting the timer B capture trigger Page 11 1.4 Pin names and Functions TMPM333FDFG/FYFG/FWFG Table 1-2 Pin Names and Functions Sorted by Port (2/5) PORT Type Pin No. PORT D Function 96 PORT D PORT D Function Function 97 98 PORT D Function 99 PORT D Function 100 PORT D Function 1 PORT D Function 2 PORT E Function 20 PORT E Function 21 PORT E Function 22 PORT E Function 89 PORT E Function 23 PORT E Function 24 PORT E Function 25 PORT F Function 33 PORT F Function 34 PORT F Function 35 PORT F Function 61 Pin Name Input/ Output Function PD1 I Input port AIN5 I Analog input TB5IN1 I Inputting the timer B capture trigger PD2 I Input port AIN6 I Analog input TB6IN0 I Inputting the timer B capture trigger PD3 I Input port AIN7 I Analog input TB6IN1 I Inputting the timer B capture trigger PD4 I Input port AIN8 I Analog input PD5 I Input port AIN9 I Analog input PD6 I Input port AIN10 I Analog input PD7 I Input port AIN11 I Analog input PE0 I/O I/O port TXD0 O Sending serial data PE1 I/O I/O port RXD0 I Receiving serial data PE2 I/O I/O port SCLK0 I/O Serial clock input/ output CTS0 I Handshake input pin PE3 I/O I/O port PE4 I/O I/O port TXD1 O Sending serial data PE5 I/O I/O port RXD1 I Receiving serial data PE6 I/O I/O port SCLK1 I/O Serial clock input/ output CTS1 I Handshake input pin PF0 I/O I/O port TXD2 O Sending serial data PF1 I/O I/O port RXD2 I Receiving serial data PF2 I/O I/O port SCLK2 I/O Serial clock input/ output CTS2 I Handshake input pin PF3 I/O I/O port Page 12 TMPM333FDFG/FYFG/FWFG Table 1-2 Pin Names and Functions Sorted by Port (3/5) PORT Type Pin No. PORT F Function 44 PORT F Function 45 PORT F Function 46 PORT F Function 19 PORT G Function 26 PORT G Function 27 PORT G Function 28 PORT G Function 6 Pin Name Input/ Output Function I/O port PF4 I/O SDA1/SO1 I/O PF5 I/O SCL1/SI1 I/O PF6 I/O I/O port SCK1 I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. PF7 I/O I/O port INT5 I External interrupt pin PG0 I/O SDA0/SO0 I/O PG1 I/O SCL0/SI0 I/O PG2 I/O I/O port SCK0 I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. PG3 I/O I/O port INT4 I External interrupt pin PG4 I/O If the serial bus interface operates SDA2/SO2 I/O -in the I2C mode: data pin -in the I2C mode: data pin -in the SIO mode: data pin I/O port -in the I2C mode: clock pin -in the SIO mode: data pin I/O port -in the I2C mode: data pin -in the SIO mode: data pin I/O port -in the I2C mode: clock pin -in the SIO mode: data pin I/O port PORT G Function 15 -in the SIO mode: data pin I/O port PORT G Function 16 PG5 I/O If the serial bus interface operates SCL2/SI2 I/O -in the I2C mode: clock pin -in the SIO mode: data pin PORT G Function 17 PORT G Function 11 PORT H Function/ Control 30 PG6 I/O I/O port SCK2 I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. PG7 I/O I/O port TB8OUT O Timer B output PH0 I/O I/O port TB0IN0 I Inputting the timer B capture trigger BOOT I Setting a single boot mode: This pin goes into single boot mode by sampling "Low" at the rise of a RESET signal. PORT H Function 31 PORT H Function 32 PORT H Function 36 PH1 I/O I/O port TB0IN1 I Inputting the timer B capture trigger PH2 I/O I/O port TB1IN0 I Inputting the timer B capture trigger PH3 I/O I/O port TB1IN1 I Inputting the timer B capture trigger Page 13 1.4 Pin names and Functions TMPM333FDFG/FYFG/FWFG Table 1-2 Pin Names and Functions Sorted by Port (4/5) PORT Type Pin No. PORT H Function 9 PORT H Function 10 PORT H Function 84 PORT H Function 85 PORT I Function 38 PORT I Function 40 PORT I Function 42 PORT I Function 48 PORT I Function 52 PORT I Function 53 PORT I Function 79 PORT I Function 83 PORT J Function 70 PORT J Function 49 PORT J Function 86 PORT J Function 87 PORT J Function 88 PORT J Function 8 PORT J Function 39 PORT J Function 58 PORT K Function 50 Pin Name Input/ Output Function PH4 I/O I/O port TB2IN0 I Inputting the timer B capture trigger PH5 I/O I/O port TB2IN1 I Inputting the timer B capture trigger PH6 I/O I/O port TB3IN0 I Inputting the timer B capture trigger PH7 I/O I/O port TB3IN1 I Inputting the timer B capture trigger PI0 I/O I/O port TB0OUT O Timer B output PI1 I/O I/O port TB1OUT O Timer B output PI2 I/O I/O port TB2OUT O Timer B output PI3 I/O I/O port TB3OUT O Timer B output PI4 I/O I/O port TB4OUT O Timer B output PI5 I/O I/O port TB5OUT O Timer B output PI6 I/O I/O port TB4IN0 I Inputting the timer B capture trigger PI7 I/O I/O port TB4IN1 I Inputting the timer B capture trigger PJ0 I/O I/O port INT0 I External interrupt pin PJ1 I/O I/O port INT1 I External interrupt pin PJ2 I/O I/O port INT2 I External interrupt pin PJ3 I/O I/O port INT3 I External interrupt pin PJ4 I/O I/O port TB6OUT O Timer B output PJ5 I/O I/O port TB7OUT O Timer B output PJ6 I/O I/O port INT6 I External interrupt pin PJ7 I/O I/O port INT7 I External interrupt pin PK0 I/O I/O port (note) Nch open drain port. Page 14 TMPM333FDFG/FYFG/FWFG Table 1-2 Pin Names and Functions Sorted by Port (5/5) PORT Type Pin No. PORT K Function 51 Pin Name Input/ Output Function PK1 I/O I/O port SCOUT O System clock output ALARM O Alarm output PK2 I/O I/O port TB9OUT O Timer B output PORT K Function 7 - Function 82 RESET I - Function 80 NMI I - Control 81 MODE I - Clock 72 X2 O Connected to a high-speed oscillator. - Clock 74 X1 I Connected to a high-speed oscillator. - Clock 77 XT1 I Connected to a low-speed oscillator. - Clock 78 XT2 O Connected to a low-speed oscillator. - Test 12 TEST2 − - Test 18 TEST1 − - Test 57 TEST3 − - Test 90 TEST4 − - PS 3 AVSS I - PS 4 VREFH I - PS 5 AVDD3 I - PS 13 DVSS − GND pin - PS 14 DVDD3 − Power supply pin - PS 62 DVDD3 − Power supply pin - PS 63 DVSS − GND pin - PS 71 DVDD3 − Power supply pin - PS 73 DVSS − GND pin - PS 75 RVSS − GND pin - PS 76 RVDD3 − Power supply pin Reset input pin (note) With a pull-up and a noise filter (about 30ns (typical value)) Non-maskable interrupt (note) With a noise filter (about 30ns (typical value)) Mode pin: (note) MODE pin must be connected to GND. TEST pin: (note) TEST pin must be left OPEN. TEST pin: (note) TEST pin must be left OPEN. TEST pin: (note) TEST pin must be left OPEN. TEST pin: (note) TEST pin must be left OPEN. AD converter: GND pin (0V) (note) AVSS must be connected to GND even if the A/D converter is not used. Supplying the AD converter with a reference power supply. (note) VREFH must be connected to power supply even if A/D converter is not used. Supplying the AD converter with a power supply. (note) AVDD must be connected to power supply even if A/D converter is not used. Page 15 1.5 Pin Numbers and Power Supply Pins 1.5 TMPM333FDFG/FYFG/FWFG Pin Numbers and Power Supply Pins Table 1-3 Pin Numbers and Power Supplies Power supply Voltage range DVDD3 AVDD3 RVDD3 2.7 to 3.6V Pin No. Pin name 14, 62,71 PA,PB,PE,PF,PG,PH,PI,PJ,PK,X1,X2,XT1, XT2,RESET,NMI,MODE 5 PC,PD 76 − Page 16 TMPM333FDFG/FYFG/FWFG 2. Processor Core The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor core). For information on the operations of this processor core, please refer to the "Cortex-M3 Technical Reference Manual" issued by ARM Limited.This chapter describes the functions unique to the TX03 series that are not explained in that document. 2.1 Information on the processor core The following table shows the revision of the processor core in the TMPM333FDFG/FYFG/FWFG. Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M series processors" in the following URL: http://infocenter.arm.com/help/index.jsp Core Revision Product Name TMPM333FDFG r1p1-00rel0 TMPM333FYFG TMPM333FWFG 2.2 r1p1-01rel0 Configurable Options The Cortex-M3 core has optional blocks. The optional blocks of the revision r1p1 are ETM™ and MPU. The following tables shows the configurable options in the TMPM333FDFG/FYFG/FWFG. 2.3 Configurable Options Implementation MPU Not implementable ETM Implementable Exceptions/ Interruptions Exceptions and interruptions are described in the following section. 2.3.1 Number of Interrupt Inputs The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM333FDFG/FYFG/FWFG has 46 interrupt inputs. The number of interrupt inputs is reflected in bit of NVIC register. In this product, if read bit, "0y00001" is read out. Page 17 2. 2.3 Processor Core Exceptions/ Interruptions 2.3.2 TMPM333FDFG/FYFG/FWFG Number of Priority Level Interrupt Bits The Cortex-M3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits. TMPM333FDFG/FYFG/FWFG has three priority level interrupt bits. The number of priority level interrupt bits is used for assigning a priority level in the interrupt priority registers and system handler priority registers. 2.3.3 SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. In the TMPM333FDFG/FYFG/FWFG, the clock that is input from X1 pin dividing by 32 is used as a count clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product, when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this value is read as "0" both of bit and bit, it indicates that external reference clock are available and the calibration value is accurate as 10ms. 2.3.4 SYSRESETREQ The Cortex-M3 core outputs SYSRESETREQ signal when bit of Application Interrupt and Reset Control Register are set. TMPM333FDFG/FYFG/FWFG provides the same operation when SYSRESETREQ signal are output. Note:Do not reset with in SLOW mode. 2.3.5 LOCKUP When irreparable exception generates, the Cortex-M3 core outputs LOCKUP signal to show a serious error included in software. TMPM333FDFG/FYFG/FWFG does not use this signal. To return from LOCKUP status, it is necessary to use non-maskable interruput (NMI) or reset. 2.3.6 Auxiliary Fault Status register The Cortex-M3 core provides auxiliary fault status registers to supply additional system fault information to software. However, TMPM333FDFG/FYFG/FWFG is not defined this function. If auxiliary fault status register is read, always "0x0000_0000" is read out. Page 18 TMPM333FDFG/FYFG/FWFG 2.4 Events The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV instruction execution. If an event is input, the core returns from low-power consumption mode caused by WFE instruction. TMPM333FDFG/FYFG/FWFG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 Power Management The Cortex-M3 core provides power management system which uses SLEEPING signals and SLEEPDEEP signals. SLEEPDEEP signals are output when bit of System Control Register is set. These signals are output in the following circumstances: -Wait-For-Interrupt (WFI) instruction execution -Wait-For-Event (WFE) instruction execution -the timing when interrupt-service-routine (ISR) exit in case that bit of System Control Register is set. TMPM333FDFG/FYFG/FWFG does not use SLEEPDEEP signals so that bit must not be set. And also event signals are not used so that please do not use WFE instruction. For detail of power management, refer to the Chapter "Clock/Mode control." 2.6 Exclusive access In Cortex-M3 core, the DCode bus system supports exclusive access. However TMPM333FDFG/FYFG/FWFG does not use this function. Page 19 2. 2.6 Processor Core Exclusive access TMPM333FDFG/FYFG/FWFG Page 20 TMPM333FDFG/FYFG/FWFG 3. Debug Interface 3.1 Specification Overview TMPM333FDFG/FYFG/FWFG contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell™(ETM) unit for instruction trace output.Trace data is output to the dedicated pins(TRACEDATA[3:0], SWV) for the debugging via the on-chip Trace Port Interface Unit (TPIU). For details about SWJ-DP, ETM and TPIU, refer to "Cortex-M3 Technical Reference Manual" . 3.2 SWJ-DP SWJ-DP supports the Serial Wire Debug Port (SWDCK, SWDIO) and the JTAG Debug Port (TDI, TDO, TMS, TCK, TRST). 3.3 ETM ETM supports four data signal pins (TRACEDATA[3:0]), one clock signal pin (TRACECLK) and trace output from SWV. Page 21 3. Debug Interface 3.4 Pin Functions 3.4 TMPM333FDFG/FYFG/FWFG Pin Functions The debug interface pins can also be used as general-purpose ports. The PA0 and PA1 pins are shared between the JTAG debug port function and the Serial Wire Debug Port function. The PB0 pin is shared between the JTAG debug port function and the SWV trace output function. Table 3-1 SWJ-DP,ETM Debug Functions SWJ-DP Pin Name Generalpurpose JTAG Debug Function SW Debug Function Port Name I/O Explanation I/O Explanation TMS / SWDIO PA0 Input JTAG Test Mode Selection I/O Serial Wire Data Input/Output TCK / SWCLK PA1 Input JTAG Test Check Input Serial Wire Clock TDO / SWV PB0 Output JTAG Test Data Output (Output)(Note) (Serial Wire Viewer Output) TDI PB1 Input JTAG Test Data Input - - TRST PB2 Input JTAG Test RESET - - TRACECLK PA2 Output TRACE Clock Output TRACEDATA0 PA3 Output TRACE DATA Output0 TRACEDATA1 PA4 Output TRACE DATA Output1 TRACEDATA2 PA5 Output TRACE DATA Output2 TRACEDATA3 PA6 Output TRACE DATA Output3 Note:When SWV function is enabled. After reset, PA0, PA1, PB0, PB1 and PB2 pins are configured as debug port function pins. The functions of other debug interface pins need to be programmed as required. When using a low power consumption mode, take note of the following points. Note 1: If PA0 and PB0 are configured as TMS/SWDIO and TDO/SWV, output continues to be enabled even in STOP mode regardless of the setting of the CGSTBYCR bit. Note 2: If PA1 is configured as a debug function pin, it prevents a low power consumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used. Table 3-2 summarizes the debug interface pin and related port settings after reset. Page 22 TMPM333FDFG/FYFG/FWFG Table 3-2 Debug Interface Pins and Related Port Settings after Reset Port Name (Bit Name) Value of Related port settings after reset Debug Function Function Input Output Pull-up Pull-down (PxFR) (PxIE) (PxCR) (PxPUP) (PxPDN) − PA0 TMS/SWDIO 1 1 1 1 PA1 TCK/SWCLK 1 1 0 − 1 PB0 TDO/SWV 1 0 1 0 − PB1 TDI 1 1 0 1 − PB2 TRST 1 1 0 1 − PA2 TRACECLK 0 0 0 0 − PA3 TRACEDATA0 0 0 0 0 − PA4 TRACEDATA1 0 0 0 0 − PA5 TRACEDATA2 0 0 0 0 − PA6 TRACEDATA3 0 0 0 0 − − : Don’t care 3.5 Peripheral Functions in Halt Mode When the Cortex-M3 core enters in the halt mode, the watchdog-timer (WDT) automatically stops. Other peripheral functions continue to operate. 3.6 Reset Vector Break TMPM333FDFG/FYFG/FWFG is prohibited from transmission with debug tools while reset caused by RESET pin is effective.When setting a stop by using reset vector, set the following procedure after reset; set break points from the debug tools, then set the application interrupt and the bit of the reset control register to reset again. Note:Do not reset with in SLOW mode. Page 23 3. 3.7 Debug Interface Connection with a Debug Tool 3.7 TMPM333FDFG/FYFG/FWFG Connection with a Debug Tool 3.7.1 About connection with debug tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are connected with external pull-up or pull-down, please pay attention to input level. 3.7.2 Important points of using debug interface pins used as general-purpose ports TMPM333FDFG/FYFG/FWFG is prohibited from transmission with debug tools while reset caused by RESET pin is effective. Therefor it cannot change to the debug mode. The PA0, PA1, PB0, PB1 and PB2 ports are the debug interface pins after reset however if these pins are changed to the general-purpose port immediately after reset, the control from the debug tools are not accepted under some circumstances.When changing the settings, please pay attention to the status of debug interface pins. Table 3-3 Table of using debug interface pins Debug interface pins TDO / TCK / TMS / TRACE TRACE SWV SWCLK SWDIO DATA[3:0] CLK ο ο ο ο × × × ο ο ο ο × × ο ο ο ο ο ο ο SW × × × ο ο × × SW+SWV × × ο ο ο × × Debugging function disabled × × × × × × × TRST TDI JTAG+SW (After reset) ο JTAG+SW (without TRST) JTAG+TRACE ο : Enabled × : Disabled (Usable as general-purpose port) Page 24 TMPM333FDFG/FYFG/FWFG 4. Memory Map 4.1 Memory map The memory maps for theTMPM333FDFG/FYFG/FWFG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. The special function register (SFR) indicates I/O ports and control registers for the peripheral function. The SRAM and SFR regions are all included in the bit-band region. The CPU register region is the processor core's internal register region. For more information on each region, see the "Cortex-M3 Technical Reference Manual". Note that access to regions indicated as "Fault" causes a memory fault if memory faults are enabled or a hard fault if memory faults are disabled. Do not access the vendor-specific region. Page 25 4. 4.1 Memory Map Memory map 4.1.1 TMPM333FDFG/FYFG/FWFG Memory map of the TMPM333FDFG Figure 4-1shows the memory map of the TMPM333FDFG. [))))B)))) Vendor-Specific [(B [()B)))) CPU Register Region [(B [')))B)))) Fault [B)))) SFR [B Fault [B))) [B Internal RAM (32K) Fault [B)))) [B Internal ROM (512K) Figure 4-1 Memory Map (TMPM333FDFG) Page 26 TMPM333FDFG/FYFG/FWFG 4.1.2 Memory Map of TMPM333FYFG Figure 4-2 shows the memory map of the TMPM333FYFG. [))))B)))) Vendor-Specific [(B [()B)))) CPU Register Region [(B [')))B)))) Fault [B)))) SFR [B Fault [B))) [B Internal RAM (16K) Fault [B)))) [B Internal ROM (256K) Figure 4-2 Memory Map (TMPM333FYFG) Note:In addition to 256KB flash area, the TMPM333FYFG provides 128-word data/ password area (1 page) for Show Product Information command in the address range 0x0007_FE00 - 0x0007_FFFF. See the Chapter "Flash Memory Operation" for details on the single boot mode. Do not Access to the range from 0x0004_0000 through the password area. Page 27 4. 4.1 Memory Map Memory map 4.1.3 TMPM333FDFG/FYFG/FWFG Memory Map of TMPM333FWFG Figure 4-3 shows the memory map of the TMPM333FWFG. [))))B)))) Vencor-Specific [(B [()B)))) CPU Register Region [(B [')))B)))) Fault [B)))) SFR [B Fault [B))) [B Internal RAM (8K) Fault [B)))) [B Internal ROM (128K) Figure 4-3 Memory Map (TMPM333FWFG) Page 28 TMPM333FDFG/FYFG/FWFG 4.2 SFR area detail This section contains the list of addresses in the SFR area (0x4000_0000 through 0x4007_FFFF) assigned to peripheral function. Access to the Reserved areas in the Table 4-1 is prohibited. As for the SFR area, reading the areas not described in the Table 4-1 yields undefined value. Writing these area is ignored. Table 4-1 SFR area detail Start Address 0x4000_0000 End Address 0x4000_02BF Peripheral PORT(A to K) Reserved 0x4000_0190 to 0x4000_0193 0x4000_01D0 to 0x4000_01D3 0x4000_0210 to 0x4000_0213 0x4000_0250 to 0x4000_0253 0x4003_0024 to 0x4003_002F 0x4001_0000 0x4001_027F TMRB(10ch) 0x4002_0000 0x4002_007F I2C/SIO(3ch) 0x4002_0080 0x4002_013F SIO/UART(3ch) 0x4003_0000 0x4003_007F ADC(12ch) 0x4004_0000 0x4004_003F WDT 0x4004_0100 0x4004_013F RTC 0x4004_010D 0x4004_0200 0x4004_023F CG 0x4004_022C to 0x4004_023F 0x4004_0300 0x4004_033F Reserved 0x4004_0400 0x4004_047F Reserved 0x4004_0428 to 0x4004_0433 0x4004_0468 to 0x4004_0473 0x4004_0504 to 0x4004_0507 0x4004_0524 to 0x4004_052B 0x4004_0540 to 0x4004_0547 0x4004_0550 to 0x4004_0553 0x4004_0560 to 0x4004_0593 0x4004_0700 to 0x4004_0707 0x4004_0500 0x4004_053F FLASH 0x4004_0540 0x4004_05BF Reserved 0x4004_0700 0x4004_073F Reserved Page 29 4. 4.2 Memory Map SFR area detail TMPM333FDFG/FYFG/FWFG Page 30 TMPM333FDFG/FYFG/FWFG 5. Reset The TMPM333FDFG/FYFG/FWFG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from , refer to "Cortex-M3 Technical Reference Manual". Note:Do not reset with in SLOW mode. 5.1 Cold reset The power-on sequence must consider the time for the internal regulator and oscillator to be stable.In the TMPM333FDFG/FYFG/FWFG, the internal regulator requires at least 700 μs to be stable. The time required to achieve stable oscillation varies with system. At cold reset, the external reset pin must be kept "Low" for a duration of time sufficiently long enough for the internal regulator and oscillator to be stable. Figure 5-1 shows the power-on sequence. RVDD3, DVDD3, AVDD3 2.7 V 0V 0.37ms/V (min.) 700 ȣs (min.) RESET High-speed oscillation 12 cycle(min.) The case where it takes 700 ȣs or more for stable oscillation RESET High-speed oscillation 12 cycle(min.) Figure 5-1 Cold Reset Sequence Note 1: The power supply must be raised (from 0V to 2.7V) at a speed of 0.37ms/V or slower. Note 2: Turn on the power while the RESET pin is fixed to "Low". Release the reset while all the power supplies are stabilized within operating voltage. Page 31 5. 5.2 Reset Warm reset 5.2 TMPM333FDFG/FYFG/FWFG Warm reset 5.2.1 Reset period As a precondition, ensure that the power supply voltage is within the operating range and the internal highfrequency oscillator is providing stable oscillation. To reset the TMPM333FDFG/FYFG/FWFG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. 5.2.2 After reset A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal function registers. The processor core's system debug components (FPB, DWT, ITM) register, the clock generator's CGRSTFLG register and the FCSECBIT register are initialized by a only cold reset. After reset, the PLL multiplication circuit is inactive and must be enabled in the CGPLLSEL register if needed. When the reset exception handling is completed, the program branches to the reset interrupt service routine. Note:The reset operation may alter the internal RAM state. Page 32 TMPM333FDFG/FYFG/FWFG 6. Clock/Mode control 6.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL clock multiplication circuit and oscillator. There is also the low power consumption mode which can reduce power consumption by mode transitions. This chapter describes how to control clock operating modes and mode transitions. The clock/mode control block has the following functions: ・ ・ ・ ・ Controls the system clock Controls the prescaler clock Controls the PLL multiplication circuit Controls the warm-up timer In addition to NORMAL mode, the TMPM333FDFG/FYFG/FWFG can operate in three types of low power mode to reduce power consumption according to its usage conditions. Page 33 6. 6.2 Clock/Mode control Registers 6.2 TMPM333FDFG/FYFG/FWFG Registers 6.2.1 Register List The following table shows the CG-related registers and addresses. Base Address = 0x4004_0200 Register name Address (Base+) System control register CGSYSCR 0x0000 Oscillation control register CGOSCCR 0x0004 Standby control register CGSTBYCR 0x0008 PLL selection register CGPLLSEL 0x000C System clock selection register CGCKSEL 0x0010 Page 34 TMPM333FDFG/FYFG/FWFG 6.2.2 CGSYSCR (System control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 - - - - - - bit symbol After reset 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 bit symbol - - - FPSEL - After reset 0 0 0 0 0 0 2 7 6 5 4 3 bit symbol - - - - - After reset 0 0 0 0 0 Bit 16 SCOSEL Bit Symbol Type Function 31-18 − R Read as 0. 17-16 SCOSEL[1:0] R/W SCOUT out 00: fs 01: fsys/2 10: fsys 11: φT0 Enables to output the specified clock from SCOUT pin. 15-13 − R Read as 0. 12 FPSEL R/W fperiph 0: fgear 1: fc Specifies the source clock to fperiph. 11 − R Read as 0. 10-8 PRCK[2:0] R/W Prescaler clock 000: fperiph 001: fperiph/2 010: fperiph/4 011: fperiph/8 100: fperiph/16 101: fperiph/32 110: Reserved 111: Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as 0. 2-0 GEAR[2:0] R/W High-speed clock gear (fc) gear 000: fc 001: Reserved 010: Reserved 011: Reserved 100: fc/2 101: fc/4 110: fc/8 111: Reserved Page 35 PRCK 0 0 1 0 GEAR 0 0 0 6. 6.2 Clock/Mode control Registers TMPM333FDFG/FYFG/FWFG 6.2.3 CGOSCCR (Oscillation control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - XTEN XEN After reset 0 0 0 0 0 0 1 1 7 6 5 4 bit symbol - After reset 0 Bit Bit Symbol WUPT 0 0 1 Type 3 2 1 0 WUPSEL PLLON WUEF WUEON 0 0 0 0 Function 31-14 − R Read as 0. 13-12 − R/W Write "0". 11-10 − R Read as 0 9 XTEN R/W Low-speed oscillator 0: Stop 1:Oscillation 8 XEN R/W High-speed oscillator 0: stop 1:Oscillation 7 − R Read as 0 6-4 WUPT[2:0] R/W Warm-up time X1 XT1 000: No warm-up 000:No warm-up 001: 210/ input freq. 001: 26/ input freq. 010: 2 / input freq. 010: 27/ input freq. 011: 212/ input freq. 011: 28/ input freq. 100: 213/input freq. 100: 215/ input freq. 101: 214/ input freq. 101: 216/ input freq. 110: 2 / input freq. 110: 217/ input freq. 111: 2 / input freq. 111: 218/ input freq. 11 15 16 3 WUPSEL R/W Warm-up counter 0: X1 1: XT1 Specifies the oscillator to warm-up. A clock generated by the specified oscillator is used for the warm-up timer count. 2 PLLON R/W PLL operation 0: Stop 1: Oscillation Specifies operation of the PLL. It stops after reset.Setting the bit is required. 1 WUEF R Status of Warm-up timer (WUP) 0:Warm-up completed 1: Warm-up operation Enables to monitor the status of the warm-up timer. 0 WUEON W Operation of warm-up timer 0: don't care 1: starting warm-up Enables to start the warm-up timer. Page 36 TMPM333FDFG/FYFG/FWFG 6.2.4 CGSTBYCR (Standby control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - DRVE bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - RXTEN RXEN After reset 0 0 0 0 0 0 0 1 2 1 0 7 6 5 4 3 bit symbol - - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type Function 31-18 − R Read as 0. 17 − R/W Write "0". 16 DRVE R/W Pin status in STOP mode. 0: Inactive 1:Active 15-10 − R Read as 0 9 RXTEN R/W Low-speed oscillator operation after releasing the STOP mode. 0: Stop 1:Oscillation 8 RXEN R/W High-speed oscillator operation after releasing the STOP mode. 0: Stop 1:Oscillation 7-3 − R Read as 0. 2-0 STBY[2:0] R/W Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE 100: Reserved 101: Reserved 110: Reserved 111: Reserved Page 37 STBY 0 1 1 6. 6.2 Clock/Mode control Registers TMPM333FDFG/FYFG/FWFG 6.2.5 CGPLLSEL (PLL Selection Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - PLLSEL After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 PLLSEL R/W Use of PLL 0: Disuse. X1 selected 1: Use Specifies use or disuse of the clock multiplied by the PLL. "X1" is automatically set after reset. Resetting is required when using the PLL. Page 38 TMPM333FDFG/FYFG/FWFG 6.2.6 CGCKSEL (System clock selection register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - SYSCK SYSCKFLG After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 SYSCK R/W System clock 0: High-speed (fc) 1: Low-speed (fs) Enables to specify the system clock. Setting CGOSCCR and to "1" in advance is required. 0 SYSCKFLG R System clock status 0: High-speed (fc) 1: Low-speed (fs) Shows the status of the system clock. Switching the oscillator with generates time lag to complete. If the output of the oscillator specified in is read out by , the switching has been completed. Page 39 6. 6.3 Clock/Mode control Clock control 6.3 TMPM333FDFG/FYFG/FWFG Clock control 6.3.1 Clock System Block Diagram Each clock is defined as follows: fosc : Clock input from the X1 and X2 pins fs : Clock input from the XT1 and XT2 (low-speed clock) fpll : Clock quadrupled by PLL fc : Clock specified by CGPLLSEL (high-speed clock) fgear : Clock specified by CGSYSCR fsys : Clock specified by CGCKSEL (system clock) fperiph : Clock specified by CGSYSCR φT0 : Clock specified by CGSYSCR (prescaler clock) The high-speed clock fc and the prescaler clock ΦT0 are dividable as follows. High-speed clock : fc, fc/2, fc/4, fc/8 Prescaler clock : fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 CPU uses the following clocks. HCLK and FCLK stop in the low power consumption mode (IDLE,SLEEP,STOP.) 6.3.2 HCLK,FCLK : fsys STCLK (Systick timer) : fosc/32 Initial Values after Reset Reset operation initializes the clock configuration as follows. High-speed oscillator : oscillating Low-speed oscillator : oscillating PLL (phase locked loop circuit) : stop High-speed clock gear : fc (no frequency dividing) Reset operation causes all the clock configurations excluding the low-speed clock (fs) to be the same as fosc. fc = fosc fsys = fosc φT0 = fosc For example, reset operation configures fsys as 10MHz when a 10MHz oscillator is connected to the X1 or X2 pin. Page 40 TMPM333FDFG/FYFG/FWFG 6.3.3 Clock system Diagram Figure 6-1 shows the clock system diagram. CGOSCCR CGOSCCR ADC conversion clock Warming-up timer CGSYSCR CGOSCCR fperiph (TO peripheal I/O) fgear CGPLLSEL CGOSCCR Starts oscillation after reset X1 X2 XT1 XT2 High-spped oscillation PLL fsys 1/2 fc fosc 1/4 1/8 CGSYSCR CGCKSEL fpll = fosc™4 CGOSCCR Stops after releasing reset Low-spped oscillation fs fs ࠙Systick Timer inputࠚ CPU(STCLK) 1/32 CGOSCCR Starts oscillation after reset ȭT0 fperiph 1/2 1/4 ࠙PeripheralI/O prescaler inputࠚ TMRB, SIO 1/8 1/16 1/32 CGSYSCR 【AHB-Bus I/O】 CPU(HCLK/FCLK), ROM, RAM, BOOT ROM 【IO-Bus I/O】 TMRB, WDT, RTC, SIO, SBI, ADC, PORT fsys 1/2 【RTC】 Sec. counter fs CGSYSCR SCOUT Figure 6-1 Clock Block Diagram The input clocks to selector shown with an arrow are set as default after reset. Page 41 6. 6.3 Clock/Mode control Clock control 6.3.4 TMPM333FDFG/FYFG/FWFG Clock Multiplication Circuit (PLL) This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock (fosc.) As a result, the input frequency to oscillator can be low, and the internal clock be made high-speed. The PLL is disabled after reset. To enable the PLL, set "1" to the CGOSCCR bit. The PLL requires a certain amount of time to be stabilized, which should be secured using the warm-up function. Note:It takes approximately 200μs for the PLL to be stabilized. 6.3.5 Warm-up function The warm-up function secures the stability time for the oscillator and the PLL with the warm-up timer. The warm-up function is used when returning from STOP/SLEEP mode. In this case, an interrupt for returning from the low power consumption mode triggers the automatic timer count. After the specified time is reached, the system clock is output and the CPU starts operation. In STOP/ SLEEP modes, the PLL is disabled. When returning from these modes, configure the warm-up time in consideration of the stability time of the PLL and the internal oscillator. How to configure the warm-up function. Specify the count up clock for the warm-up counter in the CGOSCCR bit. The warm-up time can be selected by setting the CGOSCCR. The CGOSCCR is used to confirm the start and completion of warm-up through software (instruction). After the completion of warm-up is confirmed, switch the system clock by setting the CGCKSEL. When clock switching occurs, the current system clock can be checked by monitoring the CGCKSEL Table 6-1 shows the warm-up time. Table 6-1 Warm-up Time (fosc = 10MHz, fs = 32.768kHz) Warm-up time options High-speed clock (fosc) Low-speed clock (fs) CGOSCCR CGOSCCR = "0" CGOSCCR = "1" 000 − Without WUP − With WUP 001 210/input frequency 102.4 (μs) 26/input frequency 1.953 (ms) 010 211/input frequency 204.8 (μs) 27/input frequency 3.906 (ms) 011 2 /input frequency 409.6 (μs) 2 /input frequency 7.813 (ms) 100 213/input frequency 819.2 (μs) 215/input frequency 1.0 (s) 101 2 /input frequency 1.638 (ms) 2 /input frequency 2.0 (s) 110 215/input frequency 3.277 (ms) 217/input frequency 4.0 (s) 111 216/input frequency 6.554 (ms) 218/input frequency 8.0 (s) 12 14 8 16 Note:The warm-up timer operates according to the oscillation clock, and it may contain errors if there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be taken as approximate time. Page 42 TMPM333FDFG/FYFG/FWFG The following are the examples of the warm-up function configuration. Securing the stability time for the PLL CGOSCCR = "0" : Specify the warm-up counter CGOSCCR = "010" : Specify the warm-up time (204.8μs) CGOSCCR = "1" : Start the warm-up timer (WUP) CGOSCCR Read : Wait until the state becomes "0" (warm-up is finished) Transition from the NORMAL mode to the SLOW mode CGOSCCR = "1" : Specify the warm-up counter CGOSCCR = "xxx" : Specify the warm-up time CGOSCCR = "1" : Enable the low-speed oscillation (fs) CGOSCCR = "1" : Start the warm-up timer CGOSCCR Read : Wait until the state becomes "0" (warm-up is finished) CGCKSEL = "1" : Switch the system clock to low speed (fs) CGCKSEL Read : Confirm that the current state is "1" (the current system clock is fs) CGOSCCR = "0" : Disable the high-speed oscillation (fosc) Transition from the SLOW mode to the NORMAL mode CGOSCCR = "0" : Specify the warm-up counter CGOSCCR = "xxx" : Specify the warm-up time CGOSCCR = "1" : Enable the high-speed oscillation (fosc) CGOSCCR = "1" :Start the warm-up timer CGOSCCR Read : Wait until the state becomes "0" (warm-up is finished) CGCKSEL = "0" : Switch the system clock to high speed (fgear) CGCKSEL Read : Confirm that the current state is "0" (the current system clock is fgear) CGOSCCR = "0" : Disable the low-speed oscillation (fs) Note:When switching the system clock, ensure that the switching has been completed by reading the CGSYSCR. Page 43 6. 6.3 Clock/Mode control Clock control TMPM333FDFG/FYFG/FWFG 6.3.6 System Clock The TMPM333FDFG/FYFG/FWFG offers two selectable system clocks: low-speed or high-speed. The highspeed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR register. The actual switching takes place after a slight delay. 6.3.6.1 High speed clock ・ Input frequency from X1 and X2: 8MHz to 10MHz ・ Allows for oscillator connection or external clock input ・ Clock gear:1/1, 1/2, 1/4, 1/8 (after reset: 1/1) Table 6-2 Range of High Speed frequency Input freq. X1, X2 8MHz 10MHz Min. operating freq. Max operating freq. 1 MHz 40 MHz After reset Clock gear (CG) PLL = @ON (PLL = OFF, CG = 1/1) 1/1 1/2 8 32 10 40 1/4 1/8 16 8 20 10 Clock gear (CG) PLL = @OFF 1/1 1/2 1/4 1/8 4 8 4 2 1 5 10 5 2.5 1.25 Note:PLL=ON/OFF setting: available in CGOSCCR Clock gear setting: available in CGSYSCR. 6.3.6.2 Low speed clock Input frequency from XT1 and XT2 Table 6-3 Range of Low Speed Frequency 6.3.7 Input Frequency Range Maximum Operating Frequency Minimum Operating Frequency 30 to 34 (kHz) 34 kHz 30 kHz Prescaler Clock Control Each peripheral function has a prescaler for dividing a clock. As the clock φT0 to be input to each prescaler, the "fperiph" clock specified in the CGSYSCR can be divided according to the setting in the CGSYSCR. After the controller is reset, fperiph/1 is selected as φT0. Note:To use the clock gear, ensure that you make the time setting such that prescaler output φTn from each peripheral function is slower than fsys (φTn < fsys). Do not switch the clock gear while the timer counter or other peripheral function is operating. Page 44 TMPM333FDFG/FYFG/FWFG 6.3.8 System Clock Pin Output Function The TX03 enables to output the system clock from a pin. The PK1/SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral I/O φT0. By setting the port K registers, the PKCR and PKFR1 to "1", the PK1/SCOUT pin (pin number 51) becomes the SCOUT output pin. The output clock is selected by setting the CGSYSCR. Table 6-4 shows the pin status in each mode when the SCOUT pin is set to the SCOUT output. Table 6-4 SCOUT Output Status in Each Mode Low power consumption mode Mode SCOUT selection NORMAL SLOW CGSYSCR = "00" = "01" SLEEP STOP Output the fs clock Output the fsys/2 clock = "10" = "11" IDLE Output the fsys clock Output the φT0 clock Fixed to "0" or "1". Note:The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed. Page 45 6. 6.4 Clock/Mode control Modes and Mode Transitions 6.4 6.4.1 TMPM333FDFG/FYFG/FWFG Modes and Mode Transitions Mode Transitions The NORMAL mode and the SLOW mode use the high-speed and low-speed clocks for the system clock respectively. The IDLE, SLEEP and STOP modes can be used as the low power consumption mode that enables to reduce power consumption by halting processor core operation. When the low-speed clock is not used, the SLOW and SLEEP modes cannot be used. Figure 6-2 shows a mode transition diagram. For a detail of sleep-on-exit, refer to "Cortex-M3 Technical Reference Manual." 5HVHW 5HVHWKDVEHHQSHUIRPHG ,QWHUUXSW IDLE PRGH ,QVWUXFWLRQ/ sleep on exit SLEEP mode NORMAL mode ,QVWUXFWLRQ/ sleep on exit ,QVWUXFWLRQ ,QWHUUXSW ,QWHUUXSW ,QWHUUXSW SLOW mode ,QVWUXFWLRQ/ sleep on exit ,QVWUXFWLRQ/ sleep on exit ,QWHUUXSW ,QVWUXFWLRQ/ sleep on exit Figure 6-2 Mode Transition Diagram Page 46 STOP PRGH TMPM333FDFG/FYFG/FWFG 6.5 Operation mode Two operation modes, NORMAL and SLOW, are available. The features of each mode are described in the following section. 6.5.1 NORMAL mode This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock. It is shifted to the NORMAL mode after reset. The low-speed clock can also be used. 6.5.2 SLOW mode This mode is to operate the CPU core and the peripheral hardware by using the low-speed clock with highspeed clock stopped. The SLOW mode reduces power consumption compared to the NORMAL mode. This mode allows only the following peripheral functions to operate: I/O ports, real-time clock (RTC). Note 1: Be sure to stop peripheral functions except for the CPU, RTC and I/O ports before switching to the SLOW mode. Note 2: In the slow mode, be sure not to perform reset using the Application Interrupt and Reset Control Register of the Cortex-M3 NVIC register. Page 47 6. 6.6 Clock/Mode control Low Power Consumption Modes 6.6 TMPM333FDFG/FYFG/FWFG Low Power Consumption Modes The TX03 has three low power consumption modes: IDLE, SLEEP and STOP. To shift to the low power consumption mode, specify the mode in the system control register CGSTBYCR and execute the WFI (Wait For Interrupt) instruction. In this case, execute reset or generate the interrupt to release the mode. Releasing by the interrupt requires settings in advance. See the chapter "Exceptions" for details. Note 1: The TX03 does not offer any event for releasing the low power consumption mode. Transition to the low power consumption mode by executing the WFE (Wait For Event) instruction is prohibited. Note 2: The TX03 does not support the low power consumption mode configured with the SLEEPDEEP bit in the Cortex-M3 core. Setting the bit of the system control register is prohibited. The features of each mode are described as follows. 6.6.1 IDLE mode Only the CPU is stopped in this mode. Each peripheral function has one bit in its control register for enabling or disabling operation in the IDLE mode. When the IDLE mode is entered, peripheral functions for which operation in the IDLE mode is disabled stop operation and hold the state at that time. The following peripheral functions can be enabled or disabled in the IDLE mode. For setting details, see the chapter on each peripheral function. ・ ・ ・ ・ ・ 6.6.2 16-bit timer/event counter (TMRB) Serial channel (SIO/UART) Serial bus interface (I2C/SIO) Analog Digital converter (ADC) Watch dog timer (WDT) SLEEP mode In the SLEEP mode, the internal low-speed oscillator and real time clock can be operated. By releasing the SLEEP mode, the device returns to the preceding mode of the SLEEP mode and starts operation. Note:When PA1 (pin number 56) is configured as a debug function pin, it prevents the low power consumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used. Page 48 TMPM333FDFG/FYFG/FWFG 6.6.3 STOP mode All the internal circuits including the internal oscillator are brought to a stop in the STOP mode. By releasing the STOP mode, the device returns to the preceding mode of the STOP mode and starts operation. The STOP mode enables to select the pin status by setting the CGSTBYCR.Table 6-5 shows the pin status in the STOP mode. Note:When PA1 (pin number 56) is configured as a debug function pin, it prevents the low power consumption mode from being fully effective. Configure PA1 to function as a general-purpose port when the debug function is not used. Table 6-5 Pin States in the STOP Mode Pin Name Not Ports I/O = 1 X1, XT1 Input only × × X2, XT2 Output only "High" level output. "High" level output. Input only ο ο Input × RESET, NMI, MODE PA0, PB0 [When used as a debug pin (PxFRn=1) and output is enabled (PxCR=1)] (Note) Ports = 0 PF7, PG3, PJ0, PJ1, PJ2, PJ3, PJ6, PJ7 [When used as an interrupt pin (PxFRn=1) and input is enabled (PxIE=1)] (Note) other port pins Depends on (PxIE[m]) Enabled when data is valid. Output Disabled when data is invalid. Input ο ο Output × Depends on (PxCR[m]) Input × Depends on (PxIE[m]) Output × Depends on (PxCR[m]) ο : Input or output enabled. × : Input or output disabled. Note:x: port number / m: corresponding bit / n: function register number 6.6.4 Low power Consumption Mode Setting The low power consumption mode is specified by the setting of the standby control register CGSTBYCR. Table 6-6 shows the mode setting in the . Table 6-6 Low power consumption mode setting CGSTBYCR Mode STOP 001 SLEEP 010 IDLE 011 Note:Do not set any value other than those shown above in . Page 49 6. 6.6 Clock/Mode control Low Power Consumption Modes 6.6.5 TMPM333FDFG/FYFG/FWFG Operational Status in Each Mode Table 6-7 show the operational status in each mode. For I/O port, "ο" and "×" indicate that input/output is enabled and disabled respectively. For other functions, "ο" and "×" indicate that clock is supplied and is not supplied respectively. Table 6-7 Operational Status in Each Mode NORMAL SLOW IDLE SLEEP STOP Processor core ο ο × × × I/O port ο ο ο ο * (Note 3) ADC ο × (Note 1) × × SIO ο × (Note 1) × × SBI ο × (Note 1) × × TMRB ο × (Note 1) × × WDT ο × (Note 1) × × RTC ο ο ο ο × CG ο ο ο ο × PLL ο × ο × × High-speed oscillator (fc) ο * (Note 2) ο × × Low-speed oscillator (fs) ο ο ο ο × Block ON/OFF selectable for each module Note 1: In the SLOW mode, the ADC, SIO, SBI, TMRB and WDT cannot be used and must be stopped. Note 2: The high-speed oscillator does not stop automatically and must be stopped by setting the CGOSCCR bit. Note 3: The status depends on the CGSTBYCR bit. Page 50 TMPM333FDFG/FYFG/FWFG 6.6.6 Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, Non-Maskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown in Table 6-8. Table 6-8 Release Source in Each Mode IDLE SLEEP STOP INT0 to 7 (Note1) ο ο ο INTRTC ο ο × INTTB0 to 9 ο × × INTCAP00 to 60, 01 to 61 ο × × INTRX0 to 2, INTTX0 to 2 ο × × INTSBI0 to 2 ο × × INTAD/INTADHP/INTADM0, 1 Low power consumption mode Interrupt Release source ο × × NMI (INTWDT) ο × × NMI (NMI pin) ο ο ο RESET (RESET pin) ο ο ο ο : Starts the interrupt handling after the mode is released. (The reset initializes the LSI) × : Unavailable Note 1: To release the low power consumption mode by using the level mode interrupt, keep the level until the interrupt handling is started. Changing the level before then will prevent the interrupt handling from starting properly. Note 2: For shifting to the low power consumption mode, set the CPU to prohibit all the interrupts other than the release source. If not, releasing may be executed by an unspecified interrupt. ・ Release by interrupt request To release the low power consumption mode by an interrupt, the CPU must be set in advance to detect the interrupt. In addition to the setting in the CPU, the clock generator must be set to detect the interrupt to be used to release the SLEEP and STOP modes. ・ Release by Non-Maskable Interrupt (NMI) There are two kinds of NMI sources: WDT interrupt (INTWDT) and NMI pin. INTWDT can only be used in the IDLE mode. The NMI pin can be used to release all the lower power consumption modes. ・ Release by reset Any low power consumption mode can be released by reset from the RESET pin. After that, the mode switches to the NORMAL mode and all the registers are initialized as is the case with normal reset. Note that returning to the STOP mode by reset does not induce the automatic warm-up. Keep the reset signal valid until the oscillator operation becomes stable. Refer to "Interrupts" for details. Page 51 6. 6.6 Clock/Mode control Low Power Consumption Modes 6.6.7 TMPM333FDFG/FYFG/FWFG Warm-up Mode transition may require the warm-up so that the internal oscillator provides stable oscillation. In the mode transition from STOP to the NORMAL/ SLOW or from SLEEP to NORMAL, the warm-up counter is activated automatically. And then the system clock output is started after the elapse of configured warm-up time. It is necessary to select a oscillator to be used for warm-up in the CGOSCCR and to set a warmup time in the CGOSCCR before executing the instruction to enter the STOP/ SLEEP mode. Note:In STOP/ SLEEP modes, the PLL is disabled. When returning from these modes, configure the warm-up time in consideration of the stability time of the PLL and the internal oscillator. It takes approximately 200μs for the PLL to be stabilized. In the transition from NORMAL to SLOW/ SLEEP, the warm-up is required so that the internal oscillator to stabilize if the low-speed clock is disabled. Enable the low-speed clock and then activate the warm-up by software. In the transition from SLOW to NORMAL when the high-speed clock is disabled, enable the high-speed clock and then activate the warm-up. Table 6-9 shows whether the warm-up setting of each mode transition is required or not. Table 6-9 Warm-up setting in mode transition Warm-up setting Mode transition NORMAL → IDLE Not required NORMAL → SLEEP (Note1) NORMAL → SLOW (Note 1) NORMAL → STOP Not required IDLE → NORMAL Not required SLEEP → NORMAL Auto-warm-up SLEEP → SLOW Not required SLOW → NORMAL (Note 2) SLOW → SLEEP Not required SLOW → STOP STOP → NORMAL Not required Auto-warm-up (Note 3) STOP → SLOW Auto-warm-up Note 1: If the low-speed clock is disabled, enable the low-speed clock and then activate the warm-up by software. Note 2: If the high-speed clock is disabled, enable the high-speed clock and then activate the warm-up by software. Note 3: Returning to NORMAL mode by reset does not induce the automatic warm-up. Keep the reset signal valid until the oscillator operation becomes stable. Page 52 TMPM333FDFG/FYFG/FWFG 6.6.8 Clock Operations in Mode Transition The clock operations in mode transition are described in Chapter 6.6.8.1 to 6.6.8.4. 6.6.8.1 Transition of operation modes: NORMAL → STOP → NORMAL When returning to the NORMAL mode from the STOP mode, the warm-up is activated automatically. It is necessary to set the warm-up time before entering the STOP mode. Returning to the NORMAL mode by reset does not induce the automatic warm-up. Keep the reset signal asserted until the oscillator operation becomes stable. WFI instruction/ sleep on exit Release event occurs. NORMAL Mode STOP NORMAL fosc Warm-up fsys (System clock) System clock stops 6.6.8.2 Warm-up completes. System clock starts High-speed clock starts oscillating. Warm-up starts. Transition of operation modes: NORMAL → SLEEP → NORMAL When returning to the NORMAL mode from the SLEEP mode, the warm-up is activated automatically. It is necessary to set the warm-up time before entering the SLEEP mode. Returning to the NORMAL mode by reset does not induce the automatic warm-up. Keep the reset signal asserted until the oscillator operation becomes stable. WFI instruction/ sleep on exit Mode Release event occurs. NORMAL SLEEP NORMAL fosc Warm-up fsys (System clock) fs (Low speed clock) Oscillation continues. System clock stops High-speed clock starts oscillating. Warm-up starts. Page 53 Warm-up completes. System clock starts. 6. 6.6 Clock/Mode control Low Power Consumption Modes 6.6.8.3 TMPM333FDFG/FYFG/FWFG Transition of operation modes: SLOW → STOP → SLOW The warm-up is activated automatically. It is necessary to set the warm-up time before entering the STOP mode. WFI insutruction/ sleep on exit Mode Release eventoccurs. SLOW STOP SLOW fs Warm-up fsys (System clock=fs) System clock stops 6.6.8.4 Low-speed clock starts oscillating. Warm-up starts. Warm-up completes. System clock starts. Transition of operation modes: SLOW → SLEEP → SLOW The low-speed clock continues oscillation in the SLEEP mode. There is no need to make a warm-up setting. WFI instruction / sleep on exit Mode Release event occurs. SLOW SLEEP SLOW fs fsys (System clock= fs) System clock stops. System clock starts. Page 54 TMPM333FDFG/FYFG/FWFG 7. Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to "Cortex-M3 Technical Reference Manual" if needed. 7.1 Overview An exception causes the CPU to stop the currently executing process and handle another process. There are two types of exceptions: those that are generated when some error condition occurs or when an instruction to generate an exception is executed; and those that are generated by hardware, such as an interrupt request signal from an external pin or peripheral function. All exceptions are handled by the Nested Vectored Interrupt Controller (NVIC) in the CPU according to the respective priority levels. When an exception occurs, the CPU stores the current state to the stack and branches to the corresponding interrupt service routine (ISR). Upon completion of the ISR, the information stored to the stack is automatically restored. 7.1.1 Exception Types The following types of exceptions exist in the Cortex-M3. For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Reset Non-Maskable Interrupt (NMI) Hard Fault Memory Management Bus Fault Usage Fault SVCall (Supervisor Call) Debug Monitor PendSV SysTick External Interrupt Page 55 7. Exceptions 7.1 Overview TMPM333FDFG/FYFG/FWFG 7.1.2 Handling Flowchart The following shows how an exception/interrupt is handled. In the following descriptions, indicates hardware handling. Indicates software handling. Each step is described later in this chapter. Processing Description Detection by The CG/CPU detects the exception request. CG/CPU Handling by CPU See Section 7.1.2.1 The CPU handles the exception request. Section 7.1.2.2 Branch to ISR The CPU branches to the corresponding interrupt service routine (ISR). Execution of ISR Return from exception 7.1.2.1 Necessary processing is executed. Section 7.1.2.3 The CPU branches to another ISR or returns to the previous program. Section 7.1.2.4 Exception Request and Detection (1) Exception occurrence Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. An exception occurs when the CPU executes an instruction that causes an exception or when an error condition occurs during instruction execution. An exception also occurs by an instruction fetch from the Execute Never (XN) region or an access violation to the Fault region. An interrupt request is generated from an external interrupt pin or peripheral function.For interrupts that are used for releasing a standby mode, relevant settings must be made in the clock generator.For details, refer to "7.5 Interrupts". Page 56 TMPM333FDFG/FYFG/FWFG (2) Exception detection If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority. Table 7-1 shows the priority of exceptions. "Configurable" means that you can assign a priority level to that exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or disabled. If a disabled exception occurs, it is handled as Hard Fault. Table 7-1 Exception Types and Priority No. Exception type Priority Description 1 Reset −3 (highest) Reset pin, WDT or SYSRETREQ 2 Non-Maskable Interrupt −2 NMI pin or WDT 3 Hard Fault −1 Fault that cannot activate because a higher-priority fault is being handled or it is disabled 4 Memory Management Configurable 5 Bus Fault Configurable Access violation to the Hard Fault region of the memory map 6 Usage Fault Configurable Undefined instruction execution or other faults related to instruction execution 7~10 Exception from the Memory Protection Unit (MPU) (Note 1) Instruction fetch from the Execute Never (XN) region Reserved − 11 SVCall Configurable System service call with SVC instruction 12 Debug Monitor Configurable Debug monitor when the CPU is not faulting 13 Reserved − 14 PendSV Configurable Pendable system service request 15 SysTick Configurable Notification from system timer 16~ External Interrupt Configurable External interrupt pin or peripheral function (Note 2) Note 1: This product does not contain the MPU. Note 2: External interrupts have different sources and numbers in each product. For details, see "7.5.1.5 List of Interrupt Sources". (3) Priority setting ・ Priority levels The external interrupt priority is set to the interrupt priority register and other exceptions are set to bit in the system handler priority register. The configuration can be changed, and the number of bits required for setting the priority varies from 3 bits to 8 bits depending on products. Thus, the range of priority values you can specify is different depending on products. In the case of 8-bit configuration, the priority can be configured in the range from 0 to 255. The highest priority is "0". If multiple elements with the same priority exist, the smaller the number, the higher the priority becomes. Note: bit is defined as a 3-bit configuration with this product. ・ Priority grouping The priority group can be split into groups. By setting the of the application interrupt and reset control register, can be divided into the pre-emption priority and the sub priority. A priority is compared with the pre-emption priority. If the priority is the same as the preemption priority, then it is compared with the sub priority. If the sub priority is the same as the priority, the smaller the exception number, the higher the priority. Page 57 7. Exceptions 7.1 Overview TMPM333FDFG/FYFG/FWFG The Table 7-2 shows the priority group setting. The pre-emption priority and the sub priority in the table are the number in the case that is defined as an 8-bit configuration. Table 7-2 Priority grouping setting Number of Number of Pre-emption Subpriority pre-emption field field priorities 000 [7:1] [0] 128 2 001 [7:2] [1:0] 64 4 010 [7:3] [2:0] 32 8 011 [7:4] [3:0] 16 16 100 [7:5] [4:0] 8 32 101 [7:6] [5:0] 4 64 110 [7] [6:0] 2 128 111 None [7:0] 1 256 setting subpriorities Note:If the configuration of is less than 8 bits, the lower bit is "0". For the example, in the case of 3-bit configuration, the priority is set as and is "00000". 7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) When an exception occurs, the CPU suspends the currently executing process and branches to the interrupt service routine. This is called "pre-emption". (1) Stacking When the CPU detects an exception, it pushes the contents of the following eight registers to the stack in the following order: ・ ・ ・ ・ ・ Program Counter (PC) Program Status Register (xPSR) r0 - r3 r12 Link Register (LR) The SP is decremented by eight words by the completion of the stack push.The following shows the state of the stack after the register contents have been pushed. Page 58 TMPM333FDFG/FYFG/FWFG Old SP → xPSR PC LR r12 r3 r2 r1 SP → (2) r0 Fetching an ISR The CPU enables instruction to fetch the interrupt processing with data store to the register. Prepare a vector table containing the top addresses of ISRs for each exception.After reset, the vector table is located at address 0x0000_0000 in the Code area.By setting the Vector Table Offset Register, you can place the vector table at any address in the Code or SRAM space. The vector table should also contain the initial value of the main stack. (3) Late-arriving If the CPU detects a higher priority exception before executing the ISR for a previous exception, the CPU handles the higher priority exception first. This is called "late-arriving". A late-arriving exception causes the CPU to fetch a new vector address for branching to the corresponding ISR, but the CPU does not newly push the register contents to the stack. (4) Vector table The vector table is configured as shown below. You must always set the first four words (stack top address, reset ISR address, NMI ISR address, and Hard Fault ISR address).Set ISR addresses for other exceptions if necessary. Exception Offset Contents Setting 0x00 Reset Initial value of the main stack Required 0x04 Reset ISR address Required 0x08 Non-Maskable Interrupt ISR address Required 0x0C Hard Fault ISR address Required 0x10 Memory Management ISR address Optional 0x14 Bus Fault ISR address Optional 0x18 Usage Fault ISR address Optional 0x1C ~ 0x28 Reserved 0x2C SVCall ISR address Optional 0x30 Debug Monitor ISR address Optional 0x34 Reserved 0x38 PendSV ISR address Optional 0x3C SysTick ISR address Optional 0x40 External Interrupt ISR address Optional Page 59 7. Exceptions 7.1 Overview TMPM333FDFG/FYFG/FWFG 7.1.2.3 Executing an ISR An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the user. An ISR may need to include code for clearing the interrupt request so that the same interrupt will not occur again upon return to normal program execution. For details about interrupt handling, see "7.5 Interrupts". If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons the currently executing ISR and services the newly detected exception. 7.1.2.4 Exception exit (1) Execution after returning from an ISR When returning from an ISR, the CPU takes one of the following actions: ・ Tail-chaining If a pending exception exists and there are no stacked exceptions or the pending exception has higher priority than all stacked exceptions, the CPU returns to the ISR of the pending exception. In this case, the CPU skips the pop of eight registers and push of eight registers when exiting one ISR and entering another. This is called "tail-chaining". ・ Returning to the last stacked ISR If there are no pending exceptions or if the highest priority stacked exception is of higher priority than the highest priority pending exception, the CPU returns to the last stacked ISR. ・ Returning to the previous program If there are no pending or stacked exceptions, the CPU returns to the previous program. (2) Exception exit sequence When returning from an ISR, the CPU performs the following operations: ・ Pop eight registers Pops the eight registers (PC, xPSR, r0 to r3, r12 and LR) from the stack and adjust the SP. ・ Load current active interrupt number Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. ・ Select SP If returning to an exception (Handler Mode), SP is SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 60 TMPM333FDFG/FYFG/FWFG 7.2 Reset Exceptions Reset exceptions are generated from the following three sources. Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset. ・ External reset pin A reset exception occurs when an external reset pin changes from "Low" to "High". ・ Reset exception by WDT The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT. ・ Reset exception by SYSRESETREQ A reset can be generated by setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register. Note:Do not reset with in SLOW mode. Page 61 7. 7.3 Exceptions Non-Maskable Interrupts (NMI) 7.3 TMPM333FDFG/FYFG/FWFG Non-Maskable Interrupts (NMI) Non-maskable interrupts are generated from the following two sources. Use the NMI Flag (CGNMIFLG) Register of the clock generator to identify the source of a non-maskable interrupt. ・ External NMI pin A non-maskable interrupt is generated when an external NMI pin changes from "High" to "Low". ・ Non-maskable interrupt by WDT The watchdog timer (WDT) has a non-maskable interrupt generating feature. For details, see the chapter on the WDT. 7.4 SysTick SysTick provides interrupt features using the CPU's system timer. When you set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Control and Status Register, the counter loads with the value set in the Reload Value Register and begins counting down.When the counter reaches "0", a SysTick exception occurs.You may be pending exceptions and use a flag to know when the timer reaches "0". The SysTick Calibration Value Register holds a reload value for counting 10 ms with the system timer. The count clock frequency varies with each product, and so the value set in the SysTick Calibration Value Register also varies with each product. Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms timing when the clock input from X1 is 8 MHz. Page 62 TMPM333FDFG/FYFG/FWFG 7.5 Interrupts This chapter describes routes, sources and required settings of interrupts. The CPU is notified of interrupt requests by the interrupt signal from each interrupt source. It sets priority on interrupts and handles an interrupt request with the highest priority. Interrupt requests for clearing a standby mode are notified to the CPU via the clock generator. Therefore, appropriate settings must be made in the clock generator. 7.5.1 Interrupt Sources 7.5.1.1 Interrupt Route Figure 7-1 shows an interrupt request route. The interrupts issued by the peripheral function that is not used to release standby are directly input to the CPU (route1). The peripheral function interrupts used to release standby (route 2) and interrupts from the external interrupt pin (route 3) are input to the clock generator and are input to the CPU through the logic for releasing standby (route 4 and 5). If interrupts from the external interrupt pins are not used to release standby, they are directly input to the CPU, not through the logic for standby release (route 6). Peripheral function InterruptrequestԘ Ԝ ԝ External interrupt pin 0 Ԛ Port Exiting standby mode 1 ԙ Clock generator Peripheral function Figure 7-1 Interrupt Route Page 63 ԛ CPU 7. Exceptions 7.5 Interrupts TMPM333FDFG/FYFG/FWFG 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. ・ From external pin Set the port control register so that the external pin can perform as an interrupt function pin. ・ From peripheral function Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. ・ By setting Interrupt Set-Pending Register (forced pending) An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pending Register. 7.5.1.3 Transmission An interrupt signal from an external pin or peripheral function is directly sent to the CPU unless it is used to exit a standby mode. Interrupt requests from interrupt sources that can be used for clearing a standby mode are transmitted to the CPU via the clock generator. For these interrupt sources, appropriate settings must be made in the clock generator in advance. External interrupt sources not used for exiting a standby mode can be used without setting the clock generator. 7.5.1.4 Precautions when using external interrupt pins If you use external interrupts, be aware the followings not to generate unexpected interrupts. If input disabled (PxIE="0"), inputs from external interrupt pins are "High". Also, if external interrupts are not used as a trigger to release standby (route 6 of "Figure 7-1 Interrupt Route"), input signals from the external interrupt pins are directly sent to the CPU. Since the CPU recognizes "High" input as an interrupt, interrupts occur if corresponding interrupts are enabled by the CPU as inputs are being disabled. To use the external interrupt without setting it as a standby trigger, set the interrupt pin input as "Low" and enable it. Then, enable interrupts on the CPU. Page 64 TMPM333FDFG/FYFG/FWFG 7.5.1.5 List of Interrupt Sources Table 7-3 shows the list of interrupt sources. Table 7-3 List of Interrupt Sources No. Interrupt Source 0 INT0 Interrupt pin (PJ0/70pin) 1 INT1 Interrupt pin (PJ1/49pin) 2 INT2 Interrupt pin (PJ2/86pin) 3 INT3 Interrupt pin (PJ3/87pin) 4 INT4 Interrupt pin (PG3/6pin) 5 INT5 Interrupt pin (PF7/19pin) 6 INTRX0 Serial reception (channel.0) 7 INTTX0 Serial transmission (channel.0) 8 INTRX1 Serial reception (channel.1) 9 INTTX1 Serial transmission (channel.1) 10 INTSBI0 Serial bus interface 0 11 INTSBI1 Serial bus interface 1 12 Reserved - 13 Reserved - 14 Reserved - 15 INTADHP Highest priority AD conversion complete interrupt 16 INTADM0 AD conversion monitoring function interrupt 0 17 INTADM1 AD conversion monitoring function interrupt 1 18 INTTB0 16-bit TMRB match detection 0 19 INTTB1 16-bit TMRB match detection 1 20 INTTB2 16-bit TMRB match detection 2 21 INTTB3 16-bit TMRB match detection 3 22 INTTB4 16-bit TMRB match detection 4 23 INTTB5 16-bit TMRB match detection 5 24 INTTB6 16-bit TMRB match detection 6 25 INTRTC Real time clock 26 INTCAP00 16-bit TMRB input capture 00 27 INTCAP01 16-bit TMRB input capture 01 28 INTCAP10 16-bit TMRB input capture 10 29 INTCAP11 16-bit TMRB input capture 11 30 INTCAP50 16-bit TMRB input capture 50 31 INTCAP51 16-bit TMRB input capture 51 32 INTCAP60 16-bit TMRB input capture 60 33 INTCAP61 16-bit TMRB input capture 61 34 INT6 Interrupt pin (PJ6/39pin) 35 INT7 Interrupt pin (PJ7/58pin) 36 INTRX2 Serial reception (channel.2) 37 INTTX2 Serial transmission (channel.2) 38 INTSBI2 Serial bus interface 2 39 Reserved - active level CG interrupt mode (Clearing standby) control register CGIMCGA Selectable CGIMCGB Page 65 Falling edge CGIMCGC Selectable CGIMCGC 7. Exceptions 7.5 Interrupts TMPM333FDFG/FYFG/FWFG Table 7-3 List of Interrupt Sources No. Interrupt Source 40 INTTB7 16-bit TMRB match detection 7 41 INTTB8 16-bit TMRB match detection 8 42 INTTB9 16-bit TMRB match detection 9 43 INTCAP20 16-bit TMRB input capture 20 44 INTCAP21 16-bit TMRB input capture 21 45 INTCAP30 16-bit TMRB input capture 30 46 INTCAP31 16-bit TMRB input capture 31 47 INTCAP40 16-bit TMRB input capture 40 48 INTCAP41 16-bit TMRB input capture 41 49 INTAD A/D conversion completion 7.5.1.6 active level CG interrupt mode (Clearing standby) control register Active level The active level indicates which change in signal of an interrupt source triggers an interrupt. The CPU recognizes interrupt signals in "High" level as interrupt. Interrupt signals directly sent from peripheral functions to the CPU are configured to output "High" to indicate an interrupt request. Active level is set to the clock generator for interrupts which can be a trigger to release standby. Interrupt requests from peripheral functions are set as rising-edge or falling-edge triggered. Interrupt requests from interrupt pins can be set as level-sensitive ("High" or "Low") or edge-triggered (rising or falling). If an interrupt source is used for clearing a standby mode, setting the relevant clock generator register is also required. Enable the CGIMCGx bit and specify the active level in the CGIMCGx bits. You must set the active level for interrupt requests from each peripheral function as shown in Table 7-3. An interrupt request detected by the clock generator is notified to the CPU with a signal in "High" level. Note:For the real time clock interrupts, set the bit to "1" and specify the active level, even when they are not used for clearing a standby mode. Page 66 TMPM333FDFG/FYFG/FWFG 7.5.2 Interrupt Handling 7.5.2.1 Flowchart The following shows how an interrupt is handled. In the following descriptions, handling. indicates hardware handling. Processing Details indicates software See Set the relevant NVIC registers for detecting interrupts. Set the clock generator as well if each interrupt source is used to clear a standby mode. Settings for detection οCommon setting NVIC registers οSetting to clear standby mode Clock generator "7.5.2.2 Preparation" Execute an appropriate setting to send the interrupt signal depending on the interrupt type. Settings for sending interrupt signal οSetting for interrupt from external pin Port οSetting for interrupt from peripheral function Peripheral function (See the chapter of each peripheral function for details.) Interrupt generation Not clearing standby mode An interrupt request is generated. Clearing standby mode CG detects interrupt (clearing standby mode) Interrupt lines used for clearing a standby mode are connected to the CPU via the clock generator. "7.5.2.3 Detection by Clock Generator" The CPU detects the interrupt. CPU detects interrupt If multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. "7.5.2.4 Detection by CPU" The CPU handles the interrupt. "7.5.2.5 CPU processing" CPU handles interrupt The CPU pushes register contents to the stack before entering the ISR. Page 67 7. Exceptions 7.5 Interrupts TMPM333FDFG/FYFG/FWFG Processing Details See Program for the ISR. ISR execution Clear the interrupt source if needed. "7.5.2.6 Interrupt Service Routine (ISR)" Return to preceding program 7.5.2.2 Configure to return to the preceding program of the ISR. Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following order basically. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the interrupt by the CPU. To configure the clock generator, you must follow the order indicated here not to cause any unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt in the clock generator and then enable the interrupt. The following sections are listed in the order of interrupt handling and describe how to configure them. 1. 2. 3. 4. 5. 6. 7. (1) Disabling interrupt by CPU CPU registers setting Preconfiguration (1) (Interrupt from external pin) Preconfiguration (2) (Interrupt from peripheral function) Preconfiguration (3) (Interrupt Set-Pending Register) Configuring the clock generator Enabling interrupt by CPU Disabling interrupt by CPU To make the CPU for not accepting any interrupt, write "1" to the corresponding bit of the PRIMASK Register. All interrupts and exceptions other than non-maskable interrupts and hard faults can be masked. Use "MSR" instruction to set this register. Interrupt mask register PRIMASK ← "1" (interrupt disabled) Note 1: PRIMASK register cannot be modified by the user access level. Note 2: If a fault causes when "1" is set to the PRIMASK register, it is treated as a hard fault. (2) CPU registers setting You can assign a priority level by writing to field in an Interrupt Priority Register of the NVIC register. Page 68 TMPM333FDFG/FYFG/FWFG Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.Priority level 0 is the highest priority level.If multiple sources have the same priority, the smallest-numbered interrupt source has the highest priority. You can assign grouping priority by using the PRIGROUP field in the Application Interrupt and Reset Control Register. NVIC register ← "priority" ← "group priority"(This is configurable if required.) Note:"n" indicates the corresponding exceptions/interrupts. This product uses three bits for assigning a priority level. (3) Preconfiguration (1) (Interrupt from external pin) Set "1" to the port function register of the corresponding pin. Setting PxFRn[m] allows the pin to be used as the function pin. Setting PxIE[m] allows the pin to be used as the input port. Port register PxFRn ← "1" PxIE ← "1" Note:x: port number / m: corresponding bit / n: function register number In modes other than STOP mode, setting PxIE to enable input enables the corresponding interrupt input regardless of the PxFR setting. Be careful not to enable interrupts that are not used. Also, be aware of the description of "7.5.1.4 Precautions when using external interrupt pins". (4) Preconfiguration (2) (Interrupt from peripheral function) The setting varies depending on the peripheral function to be used. See the chapter of each peripheral function for details. (5) Preconfiguration (3) (Interrupt Set-Pending Register) To generate an interrupt by using the Interrupt Set-Pending Register, set "1" to the corresponding bit of this register. NVIC register Interrupt Set-Pending [m] ← "1" Note:m: corresponding bit (6) Configuring the clock generator For an interrupt source to be used for exiting a standby mode, you need to set the active level and enable interrupts in the CGIMCG register of the clock generator. The CGIMCG register is capable of configuring each source. Page 69 7. Exceptions 7.5 Interrupts TMPM333FDFG/FYFG/FWFG Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the interrupt to be used to the CGICRCG register.See "7.6.3.4 CGICRCG(CG Interrupt Request Clear Register)" for each value. Interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting a standby mode. However, an "High" pulse or "High"-level signal must be input so that the CPU can detect it as an interrupt request. Also, be aware of the description of"7.5.1.4 Precautions when using external interrupt pins". Clock generator register CGIMCGn ← active level CGICRCG ← Value corresponding to the interrupt to be used CGIMCGn ← "1" (interrupt enabled) Note:n: register number / m: number assigned to interrupt source (7) Enabling interrupt by CPU Enable the interrupt by the CPU as shown below. Clear the suspended interrupt in the Interrupt Clear-Pending Register. Enable the intended interrupt with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single interrupt source. Writing "1" to the corresponding bit of the Interrupt Clear-Pending Register clears the suspended interrupt. Writing "1" to the corresponding bit of the Interrupt Set-Enable Register enables the intended interrupt. To generate interrupts in the Interrupt Set-Pending Register setting, factors to trigger interrupts are lost if pending interrupts are cleared. Thus, this operation is not necessary. At the end, PRIMASK register is zero cleared. NVIC register Interrupt Clear-Pending [m] ← "1" Interrupt Set-Enable [m] ← "1" ← "0" Interrupt mask register PRIMASK Note 1: m : corresponding bit Note 2: PRIMASK register cannot be modified by the user access level. 7.5.2.3 Detection by Clock Generator If an interrupt source is used for exiting a standby mode, an interrupt request is detected according to the active level specified in the clock generator, and is notified to the CPU. An edge-triggered interrupt request, once detected, is held in the clock generator. A level-sensitive interrupt request must be held at the active level until it is detected, otherwise the interrupt request will cease to exist when the signal level changes from active to inactive. When the clock generator detects an interrupt request, it keeps sending the interrupt signal in "High" level to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear (CGICRCG) Register. If a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt request in the ISR. Page 70 TMPM333FDFG/FYFG/FWFG 7.5.2.4 Detection by CPU The CPU detects an interrupt request with the highest priority. 7.5.2.5 CPU processing On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack then enter the ISR. 7.5.2.6 Interrupt Service Routine (ISR) An ISR requires specific programming according to the application to be used. This section describes what is recommended at the service routine programming and how the source is cleared. (1) Pushing during ISR An ISR normally pushes register contents to the stack and handles an interrupt as required. The CortexM3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No extra programming is required for them. Push the contents of other registers if needed. Interrupt requests with higher priority and exceptions such as NMI are accepted even when an ISR is being executed. We recommend you to push the contents of general-purpose registers that might be rewritten. (2) Clearing an interrupt source If an interrupt source is used for clearing a standby mode, each interrupt request must be cleared with the CG Interrupt Request Clear (CGICRCG) Register. If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source automatically clears the interrupt request signal from the clock generator. If an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the CGICRCG register. When an active edge occurs again, a new interrupt request will be detected. Page 71 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6 TMPM333FDFG/FYFG/FWFG Exception/Interrupt-Related Registers The CPU's NVIC registers and clock generator registers described in this chapter are shown below with their respective addresses. 7.6.1 Register List NVIC registers Base Address = 0xE000_E000 Register name Address SysTick Control and Status Register 0x0010 SysTick Reload Value Register 0x0014 SysTick Current Value Register 0x0018 SysTick Calibration Value Register 0x001C Interrupt Set-Enable Register 1 0x0100 Interrupt Set-Enable Register 2 0x0104 Interrupt Clear-Enable Register 1 0x0180 Interrupt Clear-Enable Register 2 0x0184 Interrupt Set-Pending Register 1 0x0200 Interrupt Set-Pending Register 2 0x0204 Interrupt Clear-Pending Register 1 0x0280 Interrupt Clear-Pending Register 2 0x0284 Interrupt Priority Register 0x0400 ~ 0x0430 Vector Table Offset Register 0x0D08 Application Interrupt and Reset Control Register 0x0D0C System Handler Priority Register 0x0D18, 0x0D1C, 0x0D20 System Handler Control and State Register 0x0D24 Clock generator registers Base Address = 0x4004_0200 Register name Address CG Interrupt Request Clear Register CGICRCG NMI Flag Register CGNMIFLG 0x0014 0x0018 Reset Flag Register CGRSTFLG 0x001C CG Interrupt Mode Control Register A CGIMCGA 0x0020 CG Interrupt Mode Control Register B CGIMCGB 0x0024 CG Interrupt Mode Control Register C CGIMCGC 0x0028 Reserved - 0x002C Reserved - 0x0030 Reserved - 0x0034 Reserved - 0x0038 Reserved - 0x003C Note:Access to the "Reserved" areas is prohibited. Page 72 TMPM333FDFG/FYFG/FWFG 7.6.2 NVIC Registers 7.6.2.1 SysTick Control and Status Register bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - COUNTFLAG After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - CLKSOURCE TICKINT ENABLE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-17 − R Read as 0. 16 COUNTFLAG R/W 0: Timer not counted to 0 1: Timer counted to 0 Returns "1" if timer counted to "0" since last time this was read. Clears on read of any part of the SysTick Control and Status Register. 15-3 − R Read as 0. 2 CLKSOURCE R/W 0: External reference clock 1 TICKINT R/W 0 ENABLE R/W 1: CPU clock 0: Do not pend SysTick 1: Pend SysTick 0: Disable 1: Enable If "1" is set, it reloads with the value of the Reload Value Register and starts operation. Page 73 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.2 TMPM333FDFG/FYFG/FWFG SysTick Reload Value Register bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 bit symbol RELOAD After reset Undefined 15 14 13 12 bit symbol RELOAD After reset Undefined 7 6 5 4 bit symbol RELOAD After reset Undefined Bit Bit Symbol Type Function 31-24 − R Read as 0. 23-0 RELOAD R/W Reload value Set the value to load into the SysTick Current Value Register when the timer reaches "0". Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32. Page 74 TMPM333FDFG/FYFG/FWFG 7.6.2.3 bit symbol After reset SysTick Current Value Register 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 bit symbol CURRENT After reset Undefined 15 14 13 12 bit symbol CURRENT After reset Undefined 7 6 5 4 bit symbol CURRENT After reset Undefined Bit Bit Symbol Type Function 31-24 − R Read as 0. 23-0 CURRENT R/W [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears it to 0. Clearing this register also clears the bit of the SysTick Control and Status Register. Page 75 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.4 TMPM333FDFG/FYFG/FWFG SysTick Calibration Value Register bit symbol 31 30 29 28 27 26 25 24 NOREF SKEW - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol TENMS After reset bit symbol TENMS After reset 0 0 0 0 1 0 0 1 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 0 bit symbol TENMS After reset Bit Bit Symbol Type Function 31 NOREF R 0: Reference clock provided 30 SKEW R 29-24 − R Read as 0. 23-0 TENMS R Calibration value 1: No reference clock 0: Calibration value is 10 ms. 1: Calibration value is not 10 ms. Reload value to use for 10 ms timing (0x9C4). (Note) Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to a value that provides 10 ms timing when the cock input from X1 is 8 MHz. Page 76 TMPM333FDFG/FYFG/FWFG 7.6.2.5 bit symbol Interrupt Set-Enable Register 1 31 30 29 28 27 26 25 24 SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 31) (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 After reset bit symbol SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 23 (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) After reset bit symbol 31-15 0 0 0 0 0 0 13 12 11 10 9 8 - - - 0 0 0 7 6 5 SETENA SETENA SETENA SETENA SETENA (Interrupt 11) (Interrupt 10) (Interrupt 9) (Interrupt 8) 0 0 0 0 0 4 3 2 1 0 SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2) (Interrupt 1) (Interrupt 0) 0 0 0 0 0 0 0 0 After reset Bit 0 14 (Interrupt 15) After reset bit symbol 0 15 Bit Symbol SETENA Type R/W Function Interrupt number [31:15] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 14-12 - R/W Write "0". 11-0 SETENA R/W Interrupt number [11:0] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 77 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.6 Interrupt Set-Enable Register 2 bit symbol After reset bit symbol After reset bit symbol TMPM333FDFG/FYFG/FWFG 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - SETENA (Interrupt 48) 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) 0 0 0 0 0 0 0 0 After reset 7 bit symbol - After reset 0 Bit SETENA (Interrupt 49) Bit Symbol 6 5 4 3 2 1 0 SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 38) (Interrupt 37) (Interrupt 36) (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) 0 0 0 0 0 0 0 Type Function 31-18 − R Read as 0. 17-8 SETENA R/W Interrupt number [49:40] [Write] 1: Enable [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 7 − R/W Write "0". 6-0 SETENA R/W Interrupt number [38:32] [Write] 1: Enable [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 78 TMPM333FDFG/FYFG/FWFG 7.6.2.7 bit symbol Interrupt Clear-Enable Register 1 31 30 29 28 27 26 25 24 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 31) (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 After reset bit symbol CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 23) (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) After reset bit symbol 31-15 0 0 0 0 0 0 13 12 11 10 9 8 - - - 0 0 0 7 6 5 CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 11) (Interrupt 10) (Interrupt 9) (Interrupt 8) 0 0 0 0 0 4 3 2 1 0 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2) (Interrupt 1) (Interrupt 0) 0 0 0 0 0 0 0 0 After reset Bit 0 14 (Interrupt 15) After reset bit symbol 0 15 Bit Symbol CLRENA Type R/W Function Interrupt number [31:15] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 14-12 - R/W Write "0". 11-0 CLRENA R/W Interrupt number [11:0] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 79 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.8 Interrupt Clear-Enable Register 2 bit symbol After reset bit symbol After reset bit symbol TMPM333FDFG/FYFG/FWFG 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - CLRENA (Interrupt 48) 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) 0 0 0 0 0 0 0 0 After reset 7 bit symbol - After reset 0 Bit CLRENA (Interrupt 49) Bit Symbol 6 5 4 3 2 1 0 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 38) (Interrupt 37) (Interrupt 36) (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) 0 0 0 0 0 0 0 Type Function 31-18 − R Read as 0. 17-8 CLRENA R/W Interrupt number [49:40] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 7 - R/W Write "0". 6-0 CLRENA R/W Interrupt number [38:32] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 80 TMPM333FDFG/FYFG/FWFG 7.6.2.9 bit symbol After reset bit symbol After reset bit symbol After reset bit symbol After reset Bit 31-15 Interrupt Set-Pending Register 1 31 30 29 28 27 26 25 24 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 31) (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 23) (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 - - - Undefined Undefined Undefined 7 6 5 SETPEND (Interrupt 15) SETPEND SETPEND SETPEND SETPEND (Interrupt 11) (Interrupt 10) (Interrupt 9) (Interrupt 8) Undefined Undefined Undefined Undefined Undefined 4 3 2 1 0 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2) (Interrupt 1) (Interrupt 0) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol SETPEND Type R/W Function Interrupt number [31:15] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 14-12 - R/W Write "0". 11-0 SETPEND R/W Interrupt number [11:0] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 81 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.10 bit symbol After reset bit symbol After reset bit symbol After reset TMPM333FDFG/FYFG/FWFG Interrupt Set-Pending Register 2 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - SETPEND (Interrupt 48) 0 0 0 0 0 0 Undefined Undefined 15 14 13 12 11 10 9 8 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 bit symbol - After reset Undefined Bit SETPEND (Interrupt 49) Bit Symbol 6 5 4 3 2 1 0 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 38) (Interrupt 37) (Interrupt 36) (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Type Function 31-18 − R Read as 0. 17-8 SETPEND R/W Interrupt number [49:40] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Clear and Interrupt Set-Pending Register bit by writing "1" to the corresponding bit in the Interrupt Clear-Pending Register. 7 - R/W Write "0". 6-0 SETPEND R/W Interrupt number [38:32] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Clear and Interrupt Set-Pending Register bit by writing "1" to the corresponding bit in the Interrupt Clear-Pending Register. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 82 TMPM333FDFG/FYFG/FWFG 7.6.2.11 bit symbol After reset bit symbol After reset bit symbol After reset bit symbol After reset Bit 31-15 Interrupt Clear-Pending Register 1 31 30 29 28 27 26 25 24 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 31) (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 23) (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 - - - Undefined Undefined Undefined 7 6 5 CLRPEND (Interrupt 15) CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 11) (Interrupt 10) (Interrupt 9) (Interrupt 8) Undefined Undefined Undefined Undefined Undefined 4 3 2 1 0 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2) (Interrupt 1) (Interrupt 0) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol CLRPEND Type R/W Function Interrupt number [31:15] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 14-12 - R/W Write "0". 11-0 CLRPEND R/W Interrupt number [11:0] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 83 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.12 bit symbol After reset bit symbol After reset bit symbol After reset TMPM333FDFG/FYFG/FWFG Interrupt Clear-Pending Register 2 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - CLRPEND (Interrupt 48) 0 0 0 0 0 0 Undefined Undefined 15 14 13 12 11 10 9 8 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 bit symbol - After reset Undefined Bit CLRPEND (Interrupt 49) Bit Symbol 6 5 4 3 2 1 0 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 38) (Interrupt 37) (Interrupt 36) (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Type Function 31-18 − R Read as 0. 17-8 CLRPEND R/W Interrupt number [49:40] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 7 - R/W Write "0". 6-0 CLRPEND R/W Interrupt number [38:32] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 84 TMPM333FDFG/FYFG/FWFG 7.6.2.13 Interrupt Priority Register Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 24 23 31 16 15 8 7 0 0xE000_E400 PRI_3 PRI_2 PRI_1 PRI_0 0xE000_E404 PRI_7 PRI_6 PRI_5 PRI_4 0xE000_E408 PRI_11 PRI_10 PRI_9 PRI_8 0xE000_E40C PRI_15 − − − 0xE000_E410 PRI_19 PRI_18 PRI_17 PRI_16 0xE000_E414 PRI_23 PRI_22 PRI_21 PRI_20 0xE000_E418 PRI_27 PRI_26 PRI_25 PRI_24 0xE000_E41C PRI_31 PRI_30 PRI_29 PRI_28 0xE000_E420 PRI_35 PRI_34 PRI_33 PRI_32 0xE000_E424 − PRI_38 PRI_37 PRI_36 0xE000_E428 PRI_43 PRI_42 PRI_41 PRI_40 0xE000_E42C PRI_47 PRI_46 PRI_45 PRI_44 0xE000_E430 − − PRI_49 PRI_48 The number of bits to be used for assigning a priority varies with each product. This product uses three bits for assigning a priority. The following shows the fields of the Interrupt Priority Registers for interrupt numbers 0 to 3. The Interrupt Priority Registers for all other interrupt numbers have the identical fields. Unused bits return "0" when read, and writing to unused bits has no effect. 31 30 bit symbol 28 - - - - - 0 0 0 0 0 0 0 22 21 20 19 18 17 16 - - - - - PRI_3 After reset 0 23 bit symbol PRI_2 After reset 26 25 24 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 PRI_1 - - - - - 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - - 0 0 0 0 0 0 bit symbol PRI_0 After reset 27 0 bit symbol After reset Bit 29 0 Bit Symbol 0 Type Function 31-29 PRI_3 R/W Priority of interrupt number 3 28-24 − R Read as 0. 23-21 PRI_2 R/W Priority of interrupt number 2 20-16 − R Read as 0. 15-13 PRI_1 R/W Priority of interrupt number 1 12-8 − R Read as 0. 7-5 PRI_0 R/W Priority of interrupt number 0 4-0 − R Read as 0. Page 85 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.14 TMPM333FDFG/FYFG/FWFG Vector Table Offset Register 31 30 29 - - TBLBASE bit symbol After reset 28 27 26 25 24 TBLOFF 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol TBLOFF After reset bit symbol TBLOFF After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBLOFF - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-30 − R Read as 0. 29 TBLBASE R/W Table base The vector table is in: 0: Code space 1: SRAM space 28-7 TBLOFF R/W Offset value Set the offset value from the top of the space specified in TBLBASE. The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for up to 16 interrupts.For more interrupts, you must adjust the alignment by rounding up to the next power of two. 6-0 − R Read as 0. Page 86 TMPM333FDFG/FYFG/FWFG 7.6.2.15 Application Interrupt and Reset Control Register 31 30 29 bit symbol 28 27 26 25 24 VECTKEY/VECTKEYSTAT After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol ENDIANESS - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - SYSRESET VECTCLR REQ ACTIVE After reset 0 0 0 0 0 0 0 bit symbol Bit 31-16 15 VECTKEY/VECTKEYSTAT Bit Symbol VECTKEY Type R/W PRIGROUP Register key [Write] Writing to this register requires 0x5FA in the field. VECTKEYSTAT(Read) [Read] Read as 0xFA05. R/W 0 Function (Write)/ ENDIANESS VECTRESET Endianness bit:(Note1) 1: big endian 0: little endian 14-11 − R Read as 0. 10-8 PRIGROUP R/W Interrupt priority grouping 000: seven bits of pre-emption priority, one bit of subpriority 001: six bits of pre-emption priority, two bits of subpriority 010: five bits of pre-emption priority, three bits of subpriority 011: four bits of pre-emption priority, four bits of subpriority 100: three bits of pre-emption priority, five bits of subpriority 101: two bits of pre-emption priority, six bits of subpriority 110: one bit of pre-emption priority, seven bits of subpriority 111: no pre-emption priority, eight bits of subpriority The bit configuration to split the interrupt priority register into pre-emption priority and sub priority. 7-3 − R Read as 0. 2 SYSRESET R/W System Reset Request. REQ 1 1=CPU outputs a SYSRESETREQ signal. (note2) VECTCLR R/W ACTIVE Clear active vector bit 1: clear all state information for active NMI, fault, and interrupts 0: do not clear. This bit self-clears. It is the responsibility of the application to reinitialize the stack. 0 VECTRESET R/W System Reset bit 1: reset system 0: do not reset system Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this bit is also zero cleared. Note 1: Little-endian is the default memory format for this product. Note 2: When SYSRESETREQ is output, warm reset is performed on this product. is cleared by warm reset. Page 87 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.2.16 TMPM333FDFG/FYFG/FWFG System Handler Priority Register Each exception is provided with eight bits of a System Handler Priority Register. The following shows the addresses of the System Handler Priority Registers corresponding to each exception. 31 24 23 PRI_7 16 15 8 7 0 PRI_6 PRI_5 PRI_4 (Usage Fault) (Bus Fault) (Memory Management) PRI_10 PRI_9 PRI_8 PRI_15 PRI_14 PRI_13 (SysTick) (PendSV) 0xE000_ED18 PRI_11 0xE000_ED1C (SVCall) 0xE000_ED20 PRI_12 (Debug Monitor) The number of bits to be used for assigning a priority varies with each product. This product uses three bits for assigning a priority. The following shows the fields of the System Handler Priority Registers for Memory Management, Bus Fault and Usage Fault. Unused bits return "0" when read, and writing to unused bits has no effect. 31 30 bit symbol After reset 26 25 24 - - - - 0 0 0 0 0 0 0 22 21 20 19 18 17 16 - - - - - 0 0 0 0 0 0 0 14 13 12 11 10 9 8 - - - - - PRI_6 15 bit symbol PRI_5 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - - 0 0 0 0 0 0 bit symbol PRI_4 After reset 27 - 0 0 After reset 28 23 bit symbol After reset Bit 29 PRI_7 0 Bit Symbol 0 Type Function 31-29 PRI_7 R/W Reserved 28-24 − R Read as 0. 23-21 PRI_6 R/W Priority of Usage Fault 20-16 − R Read as 0. 15-13 PRI_5 R/W Priority of Bus Fault 12-8 − R Read as 0. 7-5 PRI_4 R/W Priority of Memory Management 4-0 − R Read as 0. Page 88 TMPM333FDFG/FYFG/FWFG 7.6.2.17 System Handler Control and State Register 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - USGFAULT BUSFAULT MEMFAULT ENA ENA ENA After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SYSTICKACT PENDSVACT - 0 0 0 3 2 bit symbol SVCALL BUSFAULT MEMFAULT USGFAULT PENDED PENDED PENDED PENDED 0 0 0 0 7 6 5 4 After reset bit symbol SVCALLACT - - - After reset 0 0 0 0 Bit Bit Symbol Type − R Read as 0. 18 USGFAULT R/W Usage Fault 0: Disabled 1: Enable 17 BUSFAUL R/W TENA Bus Fault 0: Disabled 1: Enable 16 MEMFAULT R/W ENA Memory Management 0: Disabled 1: Enable 15 SVCALL R/W PENDED SVCall 0: Not pended 1: Pended 14 BUSFAULT R/W PENDED Bus Fault 0: Not pended 1: Pended 13 MEMFAULT R/W PENDED Memory Management 0: Not pended 1: Pended 12 USGFAULT R/W PENDED Usage Fault 0: Not pended 1: Pended 11 SYSTICKACT R/W SysTick 0: Inactive 1: Active 10 PENDSVACT R/W PendSV 0: Inactive 1: Active 9 − R Read as 0. 8 MONITORACT R/W Debug Monitor 0: Inactive 1: Active 7 SVCALLACT R/W SVCall 0: Inactive 1: Active 6-4 − R ACT 0 Function 31-19 ENA USGFAULT Read as 0. Page 89 0 MONITOR ACT 0 1 0 BUSFAULT MEMFAULT ACT ACT 0 0 7. 7.6 Exceptions Exception/Interrupt-Related Registers Bit 3 Bit Symbol USGFAULT TMPM333FDFG/FYFG/FWFG Type R/W ACT Function Usage Fault 0: Inactive 1: Active 2 − R Read as 0. 1 BUSFAULT R/W Bus Fault ACT 0: Inactive 1: Active 0 MEMFAULT ACT R/W Memory Management 0: Inactive 1: Active Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents. Page 90 TMPM333FDFG/FYFG/FWFG 7.6.3 Clock generator registers 7.6.3.1 CGIMCGA(CG Interrupt Mode Control Register A) 31 bit symbol 30 - After reset 29 28 27 EMCG3 26 EMST3 25 24 - INT3EN 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 - INT2EN 1 0 0 0 Undefined 0 13 12 11 10 9 8 - INT1EN bit symbol - After reset 0 0 EMCG2 15 14 EMST2 bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INT0EN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCG1 EMST1 EMCG0 0 1 EMST0 Type Function 31 − R Read as 0. 30-28 EMCG3[2:0] R/W active level setting of INT3 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 27-26 EMST3[1:0] R active level of INT3 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 25 − R Reads as undefined. 24 INT3EN R/W INT3 clear input 0:Disable 1: Enable 23 − R Read as 0. 22-20 EMCG2[2:0] R/W active level setting of INT2 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 19-18 EMST2[1:0] R active level of INT2 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 17 − R Reads as undefined. 16 INT2EN R/W INT2 clear input 0:Disable 1: Enable 15 − R Read as 0. Page 91 7. 7.6 Exceptions Exception/Interrupt-Related Registers Bit 14-12 Bit Symbol EMCG1[2:0] TMPM333FDFG/FYFG/FWFG Type R/W Function active level setting of INT1 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 11-10 EMST1[1:0] R active level of INT1 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 9 − R Reads as undefined. 8 INT1EN R/W INT1 clear input 0:Disable 1: Enable 7 − R Read as 0. 6-4 EMCG0[2:0] R/W active level setting of INT0 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 3-2 EMST0[1:0] R active level of INT0 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 1 − R Reads as undefined. 0 INT0EN R/W INT0 clear input 0:Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. Page 92 TMPM333FDFG/FYFG/FWFG 7.6.3.2 CGIMCGB(CG Interrupt Mode Control Register B) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 1 0 0 0 Undefined 0 15 14 13 12 11 10 9 8 - INT5EN bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INT4EN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCG5 EMST5 EMCG4 0 1 EMST4 Type Function 31 − R Read as 0. 30-28 − R/W Write any value. 27-26 − R Read as 0. 25 − R Reads as undefined. 24 − R/W Write "0". 23 − R Read as 0. 22-20 − R/W Write any value. 19-18 − R Read as 0. 17 − R Reads as undefined. 16 − R/W Write "0". 15 − R Read as 0. 14-12 EMCG5[2:0] R/W active level setting of INT5 standby clear request (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 11-10 EMST5[1:0] R active level of INT5 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 9 − R Reads as undefined. 8 INT5EN R/W INT5 clear input 0:Disable 1: Enable 7 − R Read as 0. 6-4 EMCG4[2:0] R/W active level setting of INT4 standby clear request (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 3-2 EMST4[1:0] R active level of INT4 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edges 1 − R Reads as undefined. Page 93 7. 7.6 Exceptions Exception/Interrupt-Related Registers Bit 0 Bit Symbol INT4EN TMPM333FDFG/FYFG/FWFG Type R/W Function INT4 clear input 0:Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. Page 94 TMPM333FDFG/FYFG/FWFG 7.6.3.3 CGIMCGC(CG Interrupt Mode Control Register C) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 - INTAEN 1 0 0 0 Undefined 0 13 12 11 10 9 8 - INT9EN bit symbol - After reset 0 0 EMCGA 15 14 EMSTA bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INT8EN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCG9 EMST9 EMCG8 0 1 EMST8 Type Function 31 − R Read as 0. 30-28 − R/W Write any value. 27-26 − R Read as 0. 25 − R Reads as undefined. 24 − R/W Write "0". 23 − R Read as 0. 22-20 EMCGA[2:0] R/W active level setting of INT7 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 19-18 EMSTA[1:0] R active level of INT7 standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edges 17 − R Reads as undefined. 16 INTAEN R/W INT7clear input 0:Disable 1: Enable 15 − R Read as 0. 14-12 EMCG9[2:0] R/W active level setting of INT6 standby clear request. (101~111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edges 11-10 EMST9[1:0] R active level of INT6 standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edges 9 − R Reads as undefined. 8 INT9EN R/W INT6 clear input 0:Disable 1: Enable 7 − R Read as 0. Page 95 7. 7.6 Exceptions Exception/Interrupt-Related Registers Bit 6-4 Bit Symbol EMCG8[2:0] TMPM333FDFG/FYFG/FWFG Type R/W Function active level setting of INTRTC standby clear request. Set it as shown below. 010: Falling edge 3-2 EMST8[1:0] R active level of INTRTC standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edges 1 − R Reads as undefined. 0 INT8EN R/W INTRTC clear input 0:Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. Page 96 TMPM333FDFG/FYFG/FWFG 7.6.3.4 bit symbol After reset CGICRCG(CG Interrupt Request Clear Register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol - - - After reset 0 0 0 Bit Bit Symbol ICRCG Type Function 31-5 − R Read as 0. 4-0 ICRCG[4:0] W Clear interrupt requests. 0_0000: INT0 0_0001: INT1 0_0010: INT2 0_0011: INT3 0_0100: INT4 0_0101: INT5 0_0110: Reserved 0_0111: Reserved 0_1000: INTRTC 0_1001: INT6 0_1010: INT7 0_1011 to 1_1111: setting prohibited. Read as 0. Page 97 0 7. 7.6 Exceptions Exception/Interrupt-Related Registers 7.6.3.5 TMPM333FDFG/FYFG/FWFG CGNMIFLG(NMI Flag Register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - NMIFLG1 NMIFLG0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 NMIFLG1 R NMI source generation flag 0: not applicable 1: generated from NMI pin 0 NMIFLG0 R NMI source generation flag 0: not applicable 1: generated from WDT Note: are cleared to "0" when they are read. Page 98 TMPM333FDFG/FYFG/FWFG 7.6.3.6 CGRSTFLG (Reset Flag Register) bit symbol After pin reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After pin reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After pin reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - SYSRSTF - WDTRSTF PINRSTF PONRSTF After pin reset 0 0 0 0 0 0 1 1/0 Bit Bit Symbol Type Function 31-5 − R Read as 0. 4 SYSRSTF R/W Debug reset flag(Note1) 0: "0" is written 1: Reset from SYSRESETREQ 3 − R/W Write as 0. 2 WDTRSTF R/W WDT reset flag 0: "0" is written 1: Reset from WDT 1 PINRSTF R/W RESET pin flag 0: "0" is written 1: Reset from RESET pin 0 PONRSTF R/W Power-on flag 0: "0" is written 1: "1" is set to this bit in initial reset state right after power-on. Note 1: This flag indicates a reset generated by the SYSRESETREQ bit of the Application Interrupt and Reset Control Register of the CPU's NVIC. Note 2: This register is not cleared automatically. Write "0" to clear the register. Page 99 7. 7.6 Exceptions Exception/Interrupt-Related Registers TMPM333FDFG/FYFG/FWFG Page 100 TMPM333FDFG/FYFG/FWFG 8. Input/Output Ports 8.1 Port Functions 8.1.1 Function Lists TMPM333FDFG/FYFG/FWFG has 78 ports. Besides the ports function, these ports can be used as I/O pins for peripheral functions. Table 8-1, Table 8-2 and Table 8-3 show the port function table. Table 8-1 Port Function List (Port A-Port C) Pin Port Port A Port B Port C Input/ Pull-up Schmitt Noise Output Pull-down input Filter Programmable Function pin Open-drain PA0 I/O Pull-up ο − − TMS/ SWDIO PA1 I/O Pull-down − − − TCK/ SWCLK PA2 I/O Pull-up − − − TRACECLK PA3 I/O Pull-up − − − TRACEDATA0 PA4 I/O Pull-up − − − TRACEDATA1 PA5 I/O Pull-up − − − TRACEDATA2 PA6 I/O Pull-up − − − TRACEDATA3 PA7 I/O Pull-up − − − − PB0 I/O Pull-up − − − TDO/ SWV PB1 I/O Pull-up − − − TDI PB2 I/O Pull-up ο − − TRST PB3 I/O Pull-up − − − − PB4 I/O Pull-up − − − − PB5 I/O Pull-up − − − − PB6 I/O Pull-up − − − − PB7 I/O Pull-up − − − − PC0 Input Pull-up − − − AIN0 PC1 Input Pull-up − − − AIN1 PC2 Input Pull-up − − − AIN2 PC3 Input Pull-up − − − AIN3 ο : Exist - : Not exist Note:The noise elimination width of the noise filter is approximately 30 ns under typical conditions. Page 101 8. Input/Output Ports 8.1 Port Functions TMPM333FDFG/FYFG/FWFG Table 8-2 Port Function List (Port D-Port G) Port Port D Port E Port F Port G Programmable Input/Output Pull-up Schmitt Noise Pull-down Input Filter PD0 Input Pull-up − − − AIN4, TB5IN0 PD1 Input Pull-up − − − AIN5, TB5IN1 PD2 Input Pull-up − − − AIN6, TB6IN0 PD3 Input Pull-up − − − AIN7, TB6IN1 PD4 Input Pull-up − − − AIN8 PD5 Input Pull-up − − − AIN9 PD6 Input Pull-up − − − AIN10 PD7 Input Pull-up − − − AIN11 PE0 I/O Pull-up − − ο TXD0 PE1 I/O Pull-up ο − ο RXD0 PE2 I/O Pull-up ο − ο SCLK0, CTS0 PE3 I/O Pull-up ο − ο − PE4 I/O Pull-up − − ο TXD1 PE5 I/O Pull-up ο − ο RXD1 PE6 I/O Pull-up ο − ο SCLK1, CTS1 PF0 I/O Pull-up − − ο TXD2 PF1 I/O Pull-up ο − ο RXD2 PF2 I/O Pull-up ο − ο SCLK2, CTS2 PF3 I/O Pull-up ο − ο − PF4 I/O Pull-up ο − ο SDA1/ SO1 PF5 I/O Pull-up ο − ο SCL1/ SI1 PF6 I/O Pull-up ο − ο SCK1 PF7 I/O Pull-up ο ο ο INT5 PG0 I/O Pull-up ο − ο SDA0/ SO0 PG1 I/O Pull-up ο − ο SCL0/ SI0 PG2 I/O Pull-up ο − ο SCK0 PG3 I/O Pull-up ο ο ο INT4 PG4 I/O Pull-up ο − ο SDA2/ SO2 PG5 I/O Pull-up ο − ο SCL2/ SI2 PG6 I/O Pull-up ο − ο SCK2 PG7 I/O Pull-up − − ο TB8OUT Pin Function pin Open-drain ο : Exist - : Not exist Note:The noise elimination width of the noise filter is approximately 30 ns under typical conditions. Page 102 TMPM333FDFG/FYFG/FWFG Table 8-3 Port Function List (Port H-Port K) Port Port H Port I Port J Port K Programmable Input/Output Pull-up Schmitt Noise Pull-down input Filter PH0 I/O Pull-up ο − − TB0IN0, BOOT PH1 I/O Pull-up ο − − TB0IN1 PH2 I/O Pull-up ο − − TB1IN0 PH3 I/O Pull-up ο − − TB1IN1 PH4 I/O Pull-up ο − − TB2IN0 PH5 I/O Pull-up ο − − TB2IN1 PH6 I/O Pull-up ο − − TB3IN0 PH7 I/O Pull-up ο − − TB3IN1 PI0 I/O Pull-up − − − TB0OUT PI1 I/O Pull-up − − − TB1OUT PI2 I/O Pull-up − − − TB2OUT PI3 I/O Pull-up − − − TB3OUT PI4 I/O Pull-up − − − TB4OUT PI5 I/O Pull-up − − − TB5OUT PI6 I/O Pull-up ο − − TB4IN0 PI7 I/O Pull-up ο − − TB4IN1 PJ0 I/O Pull-up ο ο − INT0 PJ1 I/O Pull-up ο ο − INT1 PJ2 I/O Pull-up ο ο − INT2 PJ3 I/O Pull-up ο ο − INT3 PJ4 I/O Pull-up − − − TB6OUT PJ5 I/O Pull-up − − − TB7OUT PJ6 I/O Pull-up ο ο − INT6 PJ7 I/O Pull-up ο ο − INT7 PK0 I/O − ο − ο (Note1) PK1 I/O Pull-up − − − SCOUT, ALARM PK2 I/O Pull-up − − − TB9OUT Pin Function pin Open-drain − ο : Exist - : Not exist Note 1: N-ch open drain port. Note 2: The noise elimination width of the noise filter is approximately 30 ns under typical conditions. Page 103 8. Input/Output Ports 8.1 Port Functions 8.1.2 TMPM333FDFG/FYFG/FWFG Port Registers Outline The following registers need to be configured to use ports. ・ PxDATA: Port x data register To read/ write port data. ・ PxCR: Port x output control register To control output. PxIE needs to be configured to control input. ・ PxFRn: Port x function register n To set functions. An assigned function can be activated by setting "1". ・ PxOD: Port x open drain control register To control the programmable open drain. Programmable open drain is function to be materialized pseudo-open-drain by setting the PxOD. When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control program pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE: Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. Page 104 TMPM333FDFG/FYFG/FWFG 8.1.3 Port States in STOP Mode Input and output in STOP mode are enabled/disabled by the CGSTBYCR bit. If PxIE or PxCR is enabled with =1, input or output is enabled respectively in STOP mode.If =0, both input and output are disabled in STOP mode except for some ports even if PxIE or PxCR are enabled. Table 8-4 shows the pin conditions in STOP mode. Table 8-4 Port conditions in STOP mode Pin Name Excluding port I/O = 0 = 1 X1, XT1 Input only × × X2, XT2 Output only "High" Level Output "High" Level Output Input only ο ο Input × Depends on PxIE[m] RESET, NMI, MODE PA0, PB0 [When used for debug (PxFRn=1) and output is enabled (PxCR=1)] Enabled when data is valid. Output Disabled when data is invalid. (note) Port PF7, PG3, PJ0 to PJ3, PJ6, PJ7 Input ο ο Output × Depends on PxCR[m]. Input × Depends on PxIE[m]. Output × Depends on PxCR[m]. [When used for interrupt (PxFRn=1) and input is enabled (PxIE=1)] (note) Other ports ο :Input or output enabled × :Input or output disabled Note:"x" indicates a port number, "m" a corresponding bit and "n" a function register number. 8.1.4 Precautions for Mode Transition between STOP and SLEEP If PA1 is configured as a debug function pin of TCK/SWCLK, it prevents the low power consumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the debug function is not used. Page 105 8. 8.2 Input/Output Ports Port functions 8.2 TMPM333FDFG/FYFG/FWFG Port functions This chapter describes the port registers detail. This chapter describes only "circuit type" reading circuit configuration.For detailed circuit diagram, refer to "8.3 Block Diagrams of Ports". 8.2.1 Port A (PA0 to PA7) The port A is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port A performs the debug interface and the debug trace output. PA0 and PA1 are assigned as the debug interface after reset. PA0 is initialized as the TMS/SWDIO pin with input, output and pull-up enabled. PA1 is initialized as the TCK/SWCLK pin with input and pull-down enabled. Pins from PA2 to PA7 operate as general-purpose-ports, and input, output and pull-up are disabled. Note 1: If PA0 is configured as the TMS/SWDIO pin, output is enabled even in STOP mode regardless of the CGSTBYCR bit setting Note 2: If PA1 is configured as the TCK/SWCLK pin, it prevents the low power consumption mode from being fully effective. Configure PA1 to function as a general-purpose port if the TCK/SWCLK is not used. 8.2.1.1 Type 8.2.1.2 Port A Circuit Type 7 6 5 4 3 2 1 0 T1 T9 T9 T9 T9 T9 T6 T12 Port A register Base Address = 0x4000_0000 Register name Address (Base+) Port A data register Port A output control register PADATA 0x0000 PACR 0x0004 Port A function register 1 PAFR1 0x0008 Port A pull-up control register PAPUP 0x002C Port A pull-down control register PAPDN 0x0030 PAIE 0x0038 Port A input control register Page 106 TMPM333FDFG/FYFG/FWFG 8.2.1.3 PADATA (Port A data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PA7-PA0 R/W Port A data register. 8.2.1.4 bit symbol After reset PACR (Port A output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7C PA6C PA5C PA4C PA3C PA2C PA1C PA0C After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PA7C-PA0C R/W Output 0: disable 1: enable Page 107 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.1.5 PAFR1 (Port A function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PA6F1 PA5F1 PA4F1 PA3F1 PA2F1 PA1F1 PA0F1 After reset 0 0 0 0 0 0 1 1 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6 PA6F1 R/W 0: PORT 1: TRACEDATA3 5 PA5F1 R/W 0: PORT 1: TRACEDATA2 4 PA4F1 R/W 0: PORT 1: TRACEDATA1 3 PA3F1 R/W 2 PA2F1 R/W 1 PA1F1 R/W 0 PA0F1 R/W 0: PORT 1: TRACEDATA0 0: PORT 1: TRACECLK 0: PORT 1: TCK/SWCLK 0: PORT 1: TMS/SWDIO Page 108 TMPM333FDFG/FYFG/FWFG 8.2.1.6 PAPUP (Port A pull-up control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7UP PA6UP PA5UP PA4UP PA3UP PA2UP - PA0UP After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-2 PA7UP-PA2UP R/W Pull-up 0: Disable 1: Enable 1 − R Read as 0. 0 PA0UP R/W Pull-up 0:Disable 1:Enable 8.2.1.7 PAPDN (Port A pull-down control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - PA1DN - After reset 0 0 0 0 0 0 1 0 Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 PA1DN R/W Pull-down 0: Disable 1: Enable 0 − R Read as 0. Page 109 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.1.8 bit symbol After reset PAIE (Port A input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7IE PA6IE PA5IE PA4IE PA3IE PA2IE PA1IE PA0IE After reset 0 0 0 0 0 0 1 1 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PA7IE-PA0IE R/W Input 0: DIsable 1: Enable Page 110 TMPM333FDFG/FYFG/FWFG 8.2.2 Port B (PB0 to PB7) The port B is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port B performs the debug interface. Reset configures PB0, PB1 and PB2 as debug interface.PB0 is initialized as the TDO/SWV pin with output enabled. PB1 is initialized as the TDI pin with input and pull-up enabled. PB2 is initialized as the TRST pin with input and pull-up enabled.PB3 to PB7 are initialized as general-purpose ports with input, output and pull-up disabled. Note:If PB0 is configured as the TDO/SWV pin, output is enabled even in STOP mode regardless of the CGSTBYCR bit setting. 8.2.2.1 Type 8.2.2.2 Port B Circuit Type 7 6 5 4 3 2 1 0 T1 T1 T1 T1 T1 T2 T2 T11 Port B Register Base Address = 0x4000_0040 Register name Address (Base+) Port B data register Port B output control register PBDATA 0x0000 PBCR 0x0004 Port B function register 1 PBFR1 0x0008 Port B pull-up control register PBPUP 0x002C PBIE 0x0038 Port B input control register Page 111 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.2.3 PBDATA (Port B data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PB7-PB0 R/W Port B data register. 8.2.2.4 PBCR (Port B output control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7C PB6C PB5C PB4C PB3C PB2C PB1C PB0C After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PB7C-PB0C R/W Output 0: Disable 1: Enable Page 112 TMPM333FDFG/FYFG/FWFG 8.2.2.5 PBFR1 (Port B function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PB2F1 PB1F1 PB0F1 After reset 0 0 0 0 0 1 1 1 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 PB2F1 R/W 0: PORT 1 PB1F1 R/W 0 PB0F1 R/W 1: TRST 0: PORT 1: TDI 0: PORT 1: TDO/SWV Page 113 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.2.6 bit symbol After reset PBPUP (Port B pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7UP PB6UP PB5UP PB4UP PB3UP PB2UP PB1UP PB0UP After reset 0 0 0 0 0 1 1 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PB7UP-PB0UP R/W Pull-up 0: Disable 1: Enable 8.2.2.7 PBIE (Port B input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7IE PB6IE PB5IE PB4IE PB3IE PB2IE PB1IE PB0IE After reset 0 0 0 0 0 1 1 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PB7IE-PB0IE R/W Input 0: Disable 1: Enable Page 114 TMPM333FDFG/FYFG/FWFG 8.2.3 Port C (PC0 to PC3) The port C is a 4-bit input port. Besides the general-purpose input function, the port C functions as analog input pins of the AD converter. Reset initializes all bits of the port C as general-purpose input ports with input and pull-up disabled. To use the Port C as an analog input of the AD converter, disable input on PCIE and disable pull-up on PCPUP. Note:Unless you use all the bits of port C and port D as analog input pins, conversion accuracy may be reduced. Be sure to verify that this causes no problem on your system. 8.2.3.1 Type 8.2.3.2 Port C Circuit Type 7 6 5 4 3 2 1 0 − − − − T17 T17 T17 T17 Port C Register Base Address = 0x4000_0080 Register name Address (Base+) Port C data register Port C pull-up control register Port C input control register Page 115 PCDATA 0x0000 PCPUP 0x002C PCIE 0x0038 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.3.3 PCDATA (Port C data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PC3 PC2 PC1 PC0 After reset 0 0 0 0 1 1 1 1 Bit Bit Symbol Type Function 31-4 − R Read as 0. 3-0 PC3-PC0 R Port C data register. 8.2.3.4 bit symbol After reset PCPUP (Port C pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PC3UP PC2UP PC1UP PC0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as 0. 3-0 PC3UP-PC0UP R/W Pull-up 0: Disable 1: Enable Page 116 TMPM333FDFG/FYFG/FWFG 8.2.3.5 bit symbol After reset PCIE (Port C input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PC3IE PC2IE PC1IE PC0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as 0. 3-0 PC3IE-PC0IE R/W input 0: Disable 1: Enable Page 117 8. 8.2 Input/Output Ports Port functions 8.2.4 TMPM333FDFG/FYFG/FWFG Port D (PD0 to PD7) The port D is an 8-bit input port. Besides the general-purpose input function, the port D receives an analog input of the AD converter and a 16-bit timer input. Reset initializes all bits of the port D as general-purpose input ports with input and pull-up disabled. Set the PDFR1 and PDIE when you use the port D as input pins of the 16-bit timer. To use the Port D as an analog input of the AD converter, disable input on PDIE and disable pull-up on PDPUP. Note:Unless you use all the bits of port C and port D as analog input pins, conversion accuracy may be reduced. Be sure to verify that this causes no problem on your system. 8.2.4.1 Type 8.2.4.2 Port D Circuit Type 7 6 5 4 3 2 1 0 T17 T17 T17 T17 T18 T18 T18 T18 Port D Register Base Address = 0x4000_00C0 Register name Address (Base+) Port D data register PDDATA 0x0000 Port D function register 1 PDFR1 0x0008 Port D pull-up control register PDPUP 0x002C PDIE 0x0038 Port D input control register Page 118 TMPM333FDFG/FYFG/FWFG 8.2.4.3 PDDATA (Port D data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 After reset 1 1 1 1 1 1 1 1 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PD7-PD0 R Port D data register. 8.2.4.4 PDFR1 (Port D function register 1) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PD3F1 PD2F1 PD1F1 PD0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as 0. 3 PD3F1 R/W 0: PORT 1: TB6IN1 2 PD2F1 R/W 0: PORT 1: TB6IN0 1 PD1F1 R/W 0 PD0F1 R/W 0: PORT 1: TB5IN1 0: PORT 1: TB5IN0 Page 119 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.4.5 bit symbol After reset PDPUP (Port D pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PD7UP PD6UP PD5UP PD4UP PD3UP PD2UP PD1UP PD0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PD7UP-PD0UP R/W Pull-up 0: Disable 1: Enable 8.2.4.6 PDIE (Port D input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PD7IE PD6IE PD5IE PD4IE PD3IE PD2IE PD1IE PD0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PD7IE-PD0IE R/W Input 0: Disable 1: Enable Page 120 TMPM333FDFG/FYFG/FWFG 8.2.5 Port E (PE0 to PE6) The port E is a general-purpose, 7-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port E performs the serial interface function. Reset initializes all bits of the port E as general-purpose ports with input, output and pull-up disabled. The port E has two types of function register. If you use the port E as a general-purpose port, set "0" to the corresponding bit of the two registers. If you use the port E as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the both function registers at the same time. 8.2.5.1 Type 8.2.5.2 Port E Circuit Type 7 6 5 4 3 2 1 0 − T16 T4 T10 T4 T16 T4 T10 Port E Register Base Address = 0x4000_0100 Register name Address (Base+) Port E data register PEDATA 0x0000 Port E output control register PECR 0x0004 Port E function register 1 PEFR1 0x0008 Port E function register 2 PEFR2 0x000C Port E open drain control register PEOD 0x0028 Port E pull-up control register PEPUP 0x002C PEIE 0x0038 Port E input control register Page 121 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.5.3 PEDATA (Port E data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6 PE5 PE4 PE3 PE2 PE1 PE0 After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6-0 PE6-PE0 R/W Port E data register 8.2.5.4 PECR (Port E output control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6C PE5C PE4C PE3C PE2C PE1C PE0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6-0 PE6C-PE0C R/W Output 0: Disable 1: Enable Page 122 TMPM333FDFG/FYFG/FWFG 8.2.5.5 PEFR1(Port E function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6F1 PE5F1 PE4F1 PE3F1 PE2F1 PE1F1 PE0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6 PE6F1 R/W 0: PORT 1: SCLK1 5 PE5F1 R/W 0: PORT 1: RXD1 4 PE4F1 R/W 0: PORT 1: TXD1 3 PE3F1 R/W 2 PE2F1 R/W 1 PE1F1 R/W 0 PE0F1 R/W 0: PORT 1: Reserved 0: PORT 1: SCLK0 0: PORT 1: RXD0 0: PORT 1: TXD0 Page 123 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.5.6 PEFR2(Port E function register 2) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6F2 - - - PE2F2 - - After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6 PE6F2 R/W 0: PORT 5-3 − R Read as 0. 2 PE2F2 R/W 0: PORT 1: CTS1 1: CTS0 1-0 − 8.2.5.7 R Read as 0. PEOD (Port E open drain control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6OD PE5OD PE4OD PE3OD PE2OD PE1OD PE0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6-0 PE6ODPE0OD R/W 0: CMOS 1: Open-drain Page 124 TMPM333FDFG/FYFG/FWFG 8.2.5.8 bit symbol After reset PEPUP (Port E pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6UP PE5UP PE4UP PE3UP PE2UP PE1UP PE0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6-0 PE6UP-PE0UP R/W Pull-up 0: Disable 1: Enable 8.2.5.9 PEIE (Port E input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6IE PE5IE PE4IE PE3IE PE2IE PE1IE PE0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6-0 PE6IE-PE0IE R/W Input 0: Disable 1: Enable Page 125 8. 8.2 Input/Output Ports Port functions 8.2.6 TMPM333FDFG/FYFG/FWFG Port F (PF0 to PF7) The port F is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port F performs the functions of the serial interface, the serial bus interface and the external interrupt input. Reset initializes all bits of the port F as general-purpose ports with input, output and pull-up disabled. The port F has two types of function register. If you use the port F as a general-purpose port, set "0" to the corresponding bit of the two registers. If you use the port F as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the both function registers at the same time. To use the external interrupt input for releasing STOP mode, select this function in the PFFR1 and enable input in the PFIE register. These settings enable the interrupt input even if the CGSTBYCR bit in the clock/mode control block is set to stop driving of pins during STOP mode. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PFFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.6.1 Type 8.2.6.2 Port F Circuit Type 7 6 5 4 3 2 1 0 T8 T13 T13 T13 T4 T16 T4 T10 Port F Register Base Address = 0x4000_0140 Register name Address (Base+) Port F data register PFDATA 0x0000 Port F output control register PFCR 0x0004 Port F function register 1 PFFR1 0x0008 Port F function register 2 PFFR2 0x000C Port F open drain control register PFOD 0x0028 Port F pull-up control register PFPUP 0x002C PFIE 0x0038 Port F input control register Page 126 TMPM333FDFG/FYFG/FWFG 8.2.6.3 PFDATA (Port F data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PF7-PF0 R/W Port F data register 8.2.6.4 bit symbol After reset PFCR (Port F output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PF7C PF6C PF5C PF4C PF3C PF2C PF1C PF0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PF7C-PF0C R/W Output 0: Disable 1: Enable Page 127 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.6.5 PFFR1(Port F function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PF7F1 PF6F1 PF5F1 PF4F1 PF3F1 PF2F1 PF1F1 PF0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 PF7F1 R/W 0: PORT 1: INT5 6 PF6F1 R/W 0: PORT 1: SCK1 5 PF5F1 R/W 0: PORT 1: SI1/SCL1 4 PF4F1 R/W 3 PF3F1 R/W 2 PF2F1 R/W 1 PF1F1 R/W 0 PF0F1 R/W 0: PORT 1: SO1/SDA1 0: PORT 1: Reserved 0: PORT 1: SCLK2 0: PORT 1: RXD2 0: PORT 1: TXD2 Page 128 TMPM333FDFG/FYFG/FWFG 8.2.6.6 PFFR2(Port F function register 2) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PF2F2 - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 PF2F2 R/W 0: PORT 1-0 − R 1: CTS2 8.2.6.7 bit symbol After reset Read as 0. PFOD (Port F open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PF7OD PF6OD PF5OD PF4OD PF3OD PF2OD PF1OD PF0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PF7OD-PF0OD R/W 0: CMOS 1: Open-drain Page 129 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.6.8 bit symbol After reset PFPUP (Port F pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PF7UP PF6UP PF5UP PF4UP PF3UP PF2UP PF1UP PF0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PF7UP-PF0UP R/W Pull-up 0: Disable 1: Enable 8.2.6.9 PFIE (Port F input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PF7IE PF6IE PF5IE PF4IE PF3IE PF2IE PF1IE PF0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PF7IE-PF0IE R/W Input 0: Disable 1: Enable Page 130 TMPM333FDFG/FYFG/FWFG 8.2.7 Port G (PG0 to PG7) The port G is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port G performs the functions of the serial bus interface, the external interrupt input, and the 16-bit timer output. Reset initializes all bits of the port G as general-purpose ports with input, output and pull-up disabled. To use the external interrupt input for releasing STOP mode, select function in the PGFR register and enable input in the PGIE register. These settings enable the interrupt input even if the CGSTBYCR bit in the clock/mode control block is set to stop driving of pins during STOP mode. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PGFR register setting if input is enabled in PGIE. Make sure to disable unused interrupts when programming the device. 8.2.7.1 Port G Circuit Type Type 8.2.7.2 7 6 5 4 3 2 1 0 T10 T13 T13 T13 T8 T13 T13 T13 Port G Register Base Address = 0x4000_0180 Register name Address (Base+) Port G data register PGDATA 0x0000 Port G output control register PGCR 0x0004 Port G function register 1 PGFR1 0x0008 - 0x0010 Reserved Port G open drain control register PGOD 0x0028 Port G pull-up control register PGPUP 0x002C PGIE 0x0038 Port G input control register Note:Access to the "reserved" areas is prohibited. Page 131 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.7.3 PGDATA (Port G data register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PG7-PG0 R/W Port G data register. 8.2.7.4 bit symbol After reset PGCR (Port G output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7C PG6C PG5C PG4C PG3C PG2C PG1C PG0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PG7C-PG0C R/W Output 0: Disable 1: Enable Page 132 TMPM333FDFG/FYFG/FWFG 8.2.7.5 PGFR1(Port G function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7F1 PG6F1 PG5F1 PG4F1 PG3F1 PG2F1 PG1F1 PG0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 PG7F1 R/W 0: PORT 1: TB8OUT 6 PG6F1 R/W 0: PORT 1: SCK2 5 PG5F1 R/W 0: PORT 1: SI2/SCL2 4 PG4F1 R/W 3 PG3F1 R/W 2 PG2F1 R/W 1 PG1F1 R/W 0 PG0F1 R/W 0: PORT 1: SO2/SDA2 0: PORT 1: INT4 0: PORT 1: SCK0 0: PORT 1: SI0/SCL0 0: PORT 1: SO0/SDA0 Page 133 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.7.6 PGOD (Port G open drain control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7OD PG6OD PG5OD PG4OD PG3OD PG2OD PG1OD PG0OD After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PG7ODPG0OD R/W 0: CMOS 8.2.7.7 1: Open-drain PGPUP (Port G pull-up control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7UP PG6UP PG5UP PG4UP PG3UP PG2UP PG1UP PG0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PG7UPPG0UP R/W Pull-up 0: Disable 1: Enable Page 134 TMPM333FDFG/FYFG/FWFG 8.2.7.8 bit symbol After reset PGIE (Port G input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7IE PG6IE PG5IE PG4IE PG3IE PG2IE PG1IE PG0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PG7IE-PG0IE R/W Input 0: Disable 1: Enable Page 135 8. 8.2 Input/Output Ports Port functions 8.2.8 TMPM333FDFG/FYFG/FWFG Port H (PH0 to PH7) The port H is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port H performs the functions of the 16-bit timer input and the operation mode setting. While a reset signal is in "Low" state, the 「PH0/BOOT」 input and pull-up are enabled. At the rising edge of the reset signal, if 「PH0」 is "High", the device enters single mode and boots from the on-chip flash memory. If 「PH0」 is "Low", the device enters single BOOT mode and boots from the internal BOOT program.For details of single boot mode, refer to "Flash Memory Operation". Reset initializes PH0 to PH7 bits of the port H as general-purpose ports with input and output disabled.Pullup is enabled for PH0 and disabled for PH1 to PH7. 8.2.8.1 Port H Circuit Type Type 8.2.8.2 7 6 5 4 3 2 1 0 T3 T3 T3 T3 T3 T3 T3 T5 Port H Register Base Address = 0x4000_01C0 Register name Address (Base+) Port H data register PHDATA 0x0000 Port H output control register PHCR 0x0004 Port H function register 1 PHFR1 0x0008 - 0x0010 PHPUP 0x002C PHIE 0x0038 Reserved Port H pull-up control register Port H input control register Note:Access to the "reserved" areas is prohibited. Page 136 TMPM333FDFG/FYFG/FWFG 8.2.8.3 PHDATA (Port H data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PH7-PH0 R/W Port H data register. 8.2.8.4 bit symbol After reset PHCR (Port H output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PH7C PH6C PH5C PH4C PH3C PH2C PH1C PH0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PH7C-PH0C R/W Output 0: Disable 1: Enable Page 137 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.8.5 PHFR1(Port H function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PH7F1 PH6F1 PH5F1 PH4F1 PH3F1 PH2F1 PH1F1 PH0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 PH7F1 R/W 0: PORT 1: TB3IN1 6 PH6F1 R/W 0: PORT 1: TB3IN0 5 PH5F1 R/W 0: PORT 1: TB2IN1 4 PH4F1 R/W 3 PH3F1 R/W 2 PH2F1 R/W 1 PH1F1 R/W 0 PH0F1 R/W 0: PORT 1: TB2IN0 0: PORT 1: TB1IN1 0: PORT 1: TB1IN0 0: PORT 1: TB0IN1 0: PORT 1: TB0IN0 Page 138 TMPM333FDFG/FYFG/FWFG 8.2.8.6 bit symbol After reset PHPUP (Port H pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PH7UP PH6UP PH5UP PH4UP PH3UP PH2UP PH1UP PH0UP After reset 0 0 0 0 0 0 0 1 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PH7UP-PH0UP R/W Pull-up 0: Disable 1: Enable 8.2.8.7 PHIE (Port H input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PH7IE PH6IE PH5IE PH4IE PH3IE PH2IE PH1IE PH0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PH7IE-PH0IE R/W Input 0: Disable 1: Enable Page 139 8. 8.2 Input/Output Ports Port functions 8.2.9 TMPM333FDFG/FYFG/FWFG Port I (PI0 to PI7) The port I is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port I performs the 16-bit timer input/output function. Reset initializes all bits of the port I as general-purpose ports with input, output and pull-up disabled. 8.2.9.1 Port I Circuit Type Type 8.2.9.2 7 6 5 4 3 2 1 0 T3 T3 T9 T9 T9 T9 T9 T9 Port I Register Base Address = 0x4000_0200 Register name Address (Base+) Port I data register PIDATA 0x0000 Port I output control register PICR 0x0004 Port I function register 1 PIFR1 0x0008 Reserve Port I pull-up control register Port I input control register Note:Access to the "reserved" areas is prohibited. Page 140 - 0x0010 PIPUP 0x002C PIIE 0x0038 TMPM333FDFG/FYFG/FWFG 8.2.9.3 PIDATA(Port I data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PI7-PI0 R/W Port I data register. 8.2.9.4 bit symbol After reset PICR (Port I output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PI7C PI6C PI5C PI4C PI3C PI2C PI1C PI0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PI7C-PI0C R/W Output 0: Disable 1: Enable Page 141 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.9.5 PIFR1(Port I function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PI7F1 PI6F1 PI5F1 PI4F1 PI3F1 PI2F1 PI1F1 PI0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 PI7F1 R/W 0: PORT 1: TB4IN1 6 PI6F1 R/W 0: PORT 1: TB4IN0 5 PI5F1 R/W 0: PORT 1: TB5OUT 4 PI4F1 R/W 3 PI3F1 R/W 2 PI2F1 R/W 1 PI1F1 R/W 0 PI0F1 R/W 0: PORT 1: TB4OUT 0: PORT 1: TB3OUT 0: PORT 1: TB2OUT 0: PORT 1: TB1OUT 0: PORT 1: TB0OUT Page 142 TMPM333FDFG/FYFG/FWFG 8.2.9.6 bit symbol After reset PIPUP (Port I pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PI7UP PI6UP PI5UP PI4UP PI3UP PI2UP PI1UP PI0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PI7UP-PI0UP R/W Pull-up 0: Disable 1: Enable 8.2.9.7 PIIE (Port I input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PI7IE PI6IE PI5IE PI4IE PI3IE PI2IE PI1IE PI0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PI7IE-PI0IE R/W Input 0: Disable 1: Enable Page 143 8. 8.2 Input/Output Ports Port functions 8.2.10 TMPM333FDFG/FYFG/FWFG Port J (PJ0 to PJ7) The port J is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port J performs the functions of the 16-bit timer output and the external interrupt input. Reset initializes all bits of the port J as to perform as the general-purpose ports with input, output and pull-up disabled. To use the external interrupt input for releasing STOP mode, select this function in the PJFR1 register and enable input in the PJIE register. These settings enable the interrupt input even if the CGSTBYCR bit in the clock/mode control block is set to stop driving of pins during STOP mode. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PJFR register setting if input is enabled in PJIE. Make sure to disable unused interrupts when programming the device. 8.2.10.1 Port J Circuit Type Type 8.2.10.2 7 6 5 4 3 2 1 0 T7 T7 T9 T9 T7 T7 T7 T7 Port J Register Base Address = 0x4000_0240 Register name Address (Base+) Port J data register PJDATA 0x0000 Port J output control register PJCR 0x0004 Port J function register 1 PJFR1 0x0008 Reserved Port J pull-up control register Port J input control register Note:Access to the "reserved" areas is prohibited. Page 144 - 0x0010 PJPUP 0x002C PJIE 0x0038 TMPM333FDFG/FYFG/FWFG 8.2.10.3 PJDATA (Port J data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PJ7-PJ0 R/W Port J data register. 8.2.10.4 bit symbol After reset PJCR (Port J output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7C PJ6C PJ5C PJ4C PJ3C PJ2C PJ1C PJ0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PJ7C-PJ0C R/W Output 0: Disable 1: Enable Page 145 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.10.5 bit symbol After reset PJFR1(Port J function register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7F1 PJ6F1 PJ5F1 PJ4F1 PJ3F1 PJ2F1 PJ1F1 PJ0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 PJ7F1 R/W 0: PORT 1: INT7 6 PJ6F1 R/W 0: PORT 1: INT6 5 PJ5F1 R/W 0: PORT 1: TB7OUT 4 PJ4F1 R/W 3 PJ3F1 R/W 2 PJ2F1 R/W 1 PJ1F1 R/W 0 PJ0F1 R/W 0: PORT 1: TB6OUT 0: PORT 1: INT3 0: PORT 1: INT2 0: PORT 1: INT1 0: PORT 1: INT0 Page 146 TMPM333FDFG/FYFG/FWFG 8.2.10.6 bit symbol After reset PJPUP (Port J pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7UP PJ6UP PJ5UP PJ4UP PJ3UP PJ2UP PJ1UP PJ0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PJ7UP-PJ0UP R/W Pull-up 0: Disable 1: Enable 8.2.10.7 PJIE (Port J input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7IE PJ6IE PJ5IE PJ4IE PJ3IE PJ2IE PJ1IE PJ0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 PJ7IE-PJ0IE R/W Input 0: Disable 1: Enable Page 147 8. 8.2 Input/Output Ports Port functions 8.2.11 TMPM333FDFG/FYFG/FWFG Port K (PK0 to PK2) The port K is a general-purpose, 3-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port K performs the functions of the 16-bit timer output, the clock output and the alarm output. Reset initializes all bits of the port K as general-purpose ports with input, output and pull-up disabled. Note:PK0 is an N-ch open drain port. 8.2.11.1 Type 8.2.11.2 Port K Circuit Type 7 6 5 4 3 2 1 0 − − − − − T9 T15 T14 Port K Register Base Address = 0x4000_0280 Register name Address (Base+) Port K data register PKDATA 0x0000 Port K output control register PKCR 0x0004 Port K function register 1 PKFR1 0x0008 Port K function register 2 PKFR2 0x000C Port K pull-up control register PKPUP 0x002C PKIE 0x0038 Port K input control register Page 148 TMPM333FDFG/FYFG/FWFG 8.2.11.3 PKDATA(Port K data register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PK2 PK1 PK0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2-0 PK2-PK0 R/W Port K data register. 8.2.11.4 bit symbol After reset PKCR (Port K output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PK2C PK1C PK0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2-0 PK2C-PK0C R/W Output 0: Disable 1: Enable Page 149 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.11.5 bit symbol After reset PKFR1(Port K function register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PK2F1 PK1F1 PK0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 PK2F1 R/W 0: PORT 1 PK1F1 R/W 0 PK0F1 R/W 1: TB9OUT 0: PORT 1: SCOUT 0: PORT 1: Reserved Page 150 TMPM333FDFG/FYFG/FWFG 8.2.11.6 bit symbol After reset PKFR2(Port K function register 2) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - PK1F2 - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 PK1F2 R/W 0: PORT 0 − R 1: ALARM 8.2.11.7 bit symbol After reset Read as 0. PKPUP (Port K pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PK2UP PK1UP - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2-1 PK2UP-PK1UP R/W Pull-up 0: Disable 1: Enable 0 − R Read as 0. Page 151 8. 8.2 Input/Output Ports Port functions TMPM333FDFG/FYFG/FWFG 8.2.11.8 bit symbol After reset PKIE (Port K input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PK2IE PK1IE PK0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2-0 PK2IE-PK0IE R/W Input 0: Disable 1: Enable Page 152 TMPM333FDFG/FYFG/FWFG 8.3 Block Diagrams of Ports 8.3.1 Port Types The ports are classified as shown below. Please refer to the following pages for the block diagrams of each port type. Dot lines in the figure indicate the part of the equivalent circuit described in the "Block diagrams of ports". Table 8-5 Function Lists Type GP Port Function 1 Function 2 Analog Pull-up Pull-down Programmable Note open-drain T1 I/O − − − R − − T2 I/O Input − − NoR − − T3 I/O Input − − R − − T4 I/O Input − − R − ο T5 I/O Input − − NoR − − T6 I/O Input − − − NoR − T7 I/O Input (int) − − R − − T8 I/O Input (int) − − R − ο BOOT input enabled during reset T9 I/O Output − − R − − T10 I/O Output − − R − ο T11 I/O Output − − R − − Function output triggered by enable signal T12 I/O I/O − − NoR − − Function output triggered by enable signal T13 I/O I/O − − R − ο T14 I/O I/O − − − − − T15 I/O Output Output − R − − T16 I/O I/O Input − R − ο T17 Input − − ο R − − Input Input − ο R − − T18 int: Interrupt input −: Not exist ο: Exist R: Forced disable during reset. NoR: Unaffected by reset. Page 153 Nch open drain port 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.2 TMPM333FDFG/FYFG/FWFG Type T1 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) Internal Data Bus PxCR (Output Controll) RESET PxDATA (Output Latch) I/O Port PxIE (Input Control) 0 1 Port Read Figure 8-1 Port Type T1 Page 154 TMPM333FDFG/FYFG/FWFG 8.3.3 Type T2 Drive Disable In STOP Mode Set by PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal Data Bus PxFR1 (Function Control) I/O Port PxDATA (Output Latch) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-2 Port type T2 Page 155 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.4 TMPM333FDFG/FYFG/FWFG Type T3 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal Data Bus PxFR1 (Function Control) I/O Port PxDATA (Output Latch) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-3 Port Type T3 Page 156 TMPM333FDFG/FYFG/FWFG 8.3.5 Type T4 Drive Disable In STOP Mode Set by  PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal Data Bus PxFR1 (Function Control) I/O Port PxDATA (Output Latch) PxOD (Open Drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-4 Port Type T4 Page 157 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.6 TMPM333FDFG/FYFG/FWFG Type5 T5 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal Data Base PxFR1 (Function Control) I/O Port PxDATA (Output Latch) PxIE (Input Control) 0 1 3RUW5HDG Function Input BOOT Figure 8-5 Port Type T5 Page 158 TMPM333FDFG/FYFG/FWFG 8.3.7 Type T6 Drive Disable In STOP Mode (Set by ) PxPDN (Pull-down Control) PxCR (Output Control) RESET ,QWHUQDO'DWD%XV PxFR1 (Function Control) I/O Port PxDATA (Output Latch) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-6 Port Type T6 Page 159 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.8 TMPM333FDFG/FYFG/FWFG Type T7 Drive Disable In STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal Data Bas PxFR1 (Function Control) PxDATA (Output Latch) I/O Port PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-7 Port Type T7 Page 160 TMPM333FDFG/FYFG/FWFG 8.3.9 Type T8 Drive Disable In STOP Mode Set by  PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal Data Bas I/O Port PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-8 Port Type T8 Page 161 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.10 TMPM333FDFG/FYFG/FWFG Type T9 Drive Disable In STOP Mode (Set by  PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal Data Bus PxFR1 (Function Control) PxDATA (Output Latch) Function Output 1 I/O Port 0 PxIE (Input Control) 0 1 Port Read Figure 8-9 Port Type T9 Page 162 TMPM333FDFG/FYFG/FWFG 8.3.11 Type T10 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal Data Bus PxDATA (Output Latch) Function Output 1 I/O Port 0 PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-10 Port Type T10 Page 163 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.12 TMPM333FDFG/FYFG/FWFG Type T11 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) Function Output Enable 1 0 RESET Internal Data Bus PxFR1 (Function Control) PxDATA (Output Latch) Function Output 1 I/O Port 0 PxIE (Input Control) 0 1 Port Read Figure 8-11 Port Type T11 Page 164 TMPM333FDFG/FYFG/FWFG 8.3.13 Type T12 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) Function Output Enable 1 0 RESET Internal Data Bus PxFR1 (Function Control) Function Output PxDATA (Output Latch) 1 I/O Port 0 PxIE (Input Control) 0 1 Port Read Function Input Figure 8-12 Port Type T12 Page 165 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.14 TMPM333FDFG/FYFG/FWFG Type T13 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal Data Bus Function 1 Output PxDATA (Output Latch) I/O Port 0 PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-13 Port Type T13 Page 166 TMPM333FDFG/FYFG/FWFG 8.3.15 Type T14 Drive Disable in STOP Mode (Set by ) PxCR (Output Control) RESET PxFR1 (Function Control) Internal Data Bus Function 1 Output PxDATA (Output Latch) N-chanel Open-drain 0 PxIE (Input Control) 0 1 Port Read Function Input Figure 8-14 Port Type T14 Page 167 I/O Port 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.16 TMPM333FDFG/FYFG/FWFG Type T15 Drive Disable in STOP Mode Set by  PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR2 (Function Control) Internal Data Bus PxFR1 (Function Control) Function 1 Output1 PxDATA (Output Latch) Function 1 Output2 0 0 PxIE (Input Control) Port Read Figure 8-15 Port Type T15 Page 168 I/O Port TMPM333FDFG/FYFG/FWFG 8.3.17 Type T16 Drive Disable in STOP Mode Set by  PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR2 (Function Control) Internal Data Bus PxFR1 (Function Control) Function 1 Output1 PxDATA (Output Latch) I/O Port 0 PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input1 Function Input2 Figure 8-16 Port Type T16 Page 169 8. 8.3 Input/Output Ports Block Diagrams of Ports 8.3.18 TMPM333FDFG/FYFG/FWFG Type T17 Drive Disable in STOP Mode 6HWE\ PxPUP (Pull-up Control) RESET Internal Data Bus Input Port PxIE (Input Control) Port Read Analog Input Figure 8-17 Port Type T17 Page 170 TMPM333FDFG/FYFG/FWFG 8.3.19 Type T18 Drive Disable in STOP Mode Set by ) PxPUP (Pull-up Control) RESET I/O Port Internal Data Bus PxFR1 (Function Control) PxIE (Input Control) Port Read Function Input Analog Input Figure 8-18 Port TypeT18 Page 171 8. 8.4 Input/Output Ports Appendix (Port setting List) 8.4 TMPM333FDFG/FYFG/FWFG Appendix (Port setting List) The following table shows the register setting for each function. Initialization of the ports where the [・] does not exist in the "After reset" field is set to "0" for all register settings. Setting for the bit "x" can be arbitrarily-specified. 8.4.1 Port A Setting Table 8-6 Port Setting List (Port A) Pin PA0 Port Type T12 Function PACR PAFR1 PAPUP PAPDN PAIE Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 1 1 1 0 1 Input Port 0 0 0 x 1 Output Port 1 0 0 x 0 0 1 0 1 1 Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 TRACECLK(Output) 1 1 x 0 0 Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 TRACEDATA0(Output) 1 1 x 0 0 Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 TRACEDATA1(Output) 1 1 x 0 0 Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 TRACEDATA2(Output) 1 1 x 0 0 Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 TRACEDATA3(Output) 1 1 x 0 0 Input Port 0 0 x 0 1 Output Port 1 0 x 0 0 TMS(Input)/ SWDIO(I/O) PA1 T6 TCK(Input)/ SWCLK(Input) PA2 PA3 PA4 PA5 PA6 PA7 T9 T9 T9 T9 T9 T1 After reset ・ ・ Page 172 TMPM333FDFG/FYFG/FWFG 8.4.2 Port B Setting Table 8-7 Port Setting List (Port B) Pin PB0 Port Type T11 Function PBCR PBFR1 PBPUP PBIE Input Port 0 0 x 1 Output Port 1 0 x 0 1 1 0 0 Input Port 0 0 x 1 Output Port 1 0 x 0 0 1 1 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TDO(Output)/ SWV(Output) PB1 T2 TDI(Input) PB2 T2 TRST(Input) PB3 T1 PB4 T1 PB5 T1 PB6 PB7 T1 T1 After reset ・ ・ 0 1 1 1 Input Port 0 0 x 1 Output Port 1 0 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 ・ Page 173 8. 8.4 Input/Output Ports Appendix (Port setting List) 8.4.3 TMPM333FDFG/FYFG/FWFG Port C Setting Table 8-8 Port Setting List (Port C) Port Pin PC0 T17 PC1 8.4.4 T17 PC2 T17 PC3 T17 After reset Function Type PCPUP PCIE x 1 0 0 x 1 0 0 x 1 ・ 0 0 x 1 ・ 0 0 Input Port Analog Input ・ Input Port Analog Input ・ Input Port Analog Input Input Port Analog Input Port D Setting Table 8-9 Port Setting List (Port D) Pin PD0 Port Type T18 Function After reset PDFR1 PDPUP PDIE Input Port 0 x 1 TB5IN0(Input) 1 x 1 x 0 0 0 x 1 1 x 1 x 0 0 0 x 1 1 x 1 x 0 0 0 x 1 1 x 1 x 0 0 0 x 1 Analog Input ・ Input Port PD1 T18 TB5IN1(Input) Analog Input ・ Input Port PD2 T18 TB6IN0(Input) Analog Input ・ Input Port PD3 T18 TB6IN1(Input) Analog Input PD4 PD5 T17 T17 PD6 T17 PD7 T17 ・ Input Port Analog Input ・ Input Port Analog Input ・ Input Port Analog Input ・ Input Port Analog Input ・ Page 174 x 0 0 0 x 1 x 0 0 0 x 1 x 0 0 0 x 1 x 0 0 TMPM333FDFG/FYFG/FWFG 8.4.5 Port E Setting Table 8-10 Port Setting List (Port E) Pin PE0 PE1 PE2 PE3 PE4 PE5 PE6 Port Type T10 T4 T16 T4 T10 T4 T16 Function After reset PECR PEFR1 PEFR2 PEOD PEPUP PEIE Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 TXD0(Output) 1 1 0 x x 0 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 RXD0(Input) 0 1 0 x x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 SCLK0(Input) 0 1 0 x x 1 SCLK0(Output) 1 1 0 x x 0 CTS0(Input) 0 0 1 x x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 TXD1(Output) 1 1 0 x x 0 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 RXD1(Input) 0 1 0 x x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 SCLK1(Input) 0 1 0 x x 1 SCLK1(Output) 1 1 0 x x 0 CTS1(Input) 0 0 1 x x 1 Page 175 8. 8.4 Input/Output Ports Appendix (Port setting List) 8.4.6 TMPM333FDFG/FYFG/FWFG Port F Setting Table 8-11 Port Setting List (Port F) Pin PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 Port Type T10 T4 T16 T4 T13 T13 T13 T8 Function After reset PFCR PFFR1 PFFR2 PFOD PFPUP PFIE Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 TXD2(Output) 1 1 0 x x 0 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 RXD2(Input) 0 1 0 x x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 SCLK2(Input) 0 1 1 x x 1 SCLK2(Output) 1 1 0 x x 0 CTS2(Input) 0 0 0 x x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 SO1(Output) 1 1 0 x x 0 SDA1(Input/Output) 1 1 0 1 x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 SI1(Input) 0 1 0 x x 1 SCL1(Input/Output) 1 1 0 1 x 1 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 SCK1(Input) 0 1 0 x x 1 SCK1(Output) 1 1 0 x x 0 Input Port 0 0 0 x x 1 Output Port 1 0 0 x x 0 INT5(Input) 0 1 0 x x 1 Page 176 TMPM333FDFG/FYFG/FWFG 8.4.7 Port G Setting Table 8-12 Port Setting List (Port G) Pin PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 Port Type T13 T13 T13 T8 T13 T13 T13 T10 Function After reset PGCR PGFR1 PGOD PGPUP PGIE Input Port 0 0 x x 1 Output Port 1 0 x x 0 SO0(Output) 1 1 x x 0 SDA0(Input/Output) 1 1 1 x 1 Input Port 0 0 x x 1 Output Port 1 0 x x 0 SI0(Input) 0 1 x x 1 SCL0(Input/Output) 1 1 1 x 1 Input Port 0 0 x x 1 Output Port 1 0 x x 0 SCK0(Input) 0 1 x x 1 SCK0(Output) 1 1 x x 0 Input Port 0 0 x x 1 Output Port 1 0 x x 0 INT4(Input) 0 1 x x 1 Input Port 0 0 x x 1 Output Port 1 0 x x 0 SO2(Output) 1 1 x x 0 SDA2(Input/Output) 1 1 1 x 1 Input Port 0 0 x x 1 Output Port 1 0 x x 0 SI2(Input) 0 1 x x 1 SCL2(Input/Output) 1 1 1 x 1 Input Port 0 0 x x 1 Output Port 1 0 x x 0 SCK2(Input) 0 1 x x 1 SCK2(Output) 1 1 x x 0 Input Port 0 0 x x 1 Output Port 1 0 x x 0 TB8OUT(Output) 1 1 x x 0 Page 177 8. 8.4 Input/Output Ports Appendix (Port setting List) 8.4.8 TMPM333FDFG/FYFG/FWFG Port H Setting Table 8-13 Port Setting List (Port H) Pin PH0 PH1 PH2 PH3 Port Type T5 T3 T3 T3 PH4 T3 PH5 T3 PH6 PH7 T3 T3 Function After reset PHCR PHFR1 PHPUP PHIE Input Port 0 0 x 1 Output Port 1 0 x 0 TB0IN0(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB0IN1(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB1IN0(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB1IN1(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB2IN0(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB2IN1(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB3IN0(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB3IN1(Input) 0 1 x 1 Note:The PH0 input and pull-up are enabled and act as BOOT input pin while a RESET is in "Low" state. Page 178 TMPM333FDFG/FYFG/FWFG 8.4.9 Port I Setting Table 8-14 Port Setting List (Port I) Pin Port Function PI0 PI1 PI2 PI3 PI4 PI5 PI6 T9 T9 T9 T9 T9 T9 T3 PI7 T3 After reset PICR PIFR1 PIPUP PIIE Input Port 0 0 x 1 Output Port 1 0 x 0 TB0OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB1OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB2OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB3OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB4OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB5OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB4IN0(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB4IN1(Input) 0 1 x 1 Type Page 179 8. 8.4 Input/Output Ports Appendix (Port setting List) 8.4.10 TMPM333FDFG/FYFG/FWFG Port J Setting Table 8-15 Port Setting List (Port J) pin PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 Port Type T7 T7 T7 T7 T9 T9 T7 T7 Function After reset PJCR PJFR1 PJPUP PJIE Input Port 0 0 x 1 Output Port 1 0 x 0 INT0(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 INT1(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 INT2(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 INT3(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 TB6OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 TB7OUT(Output) 1 1 x 0 Input Port 0 0 x 1 Output Port 1 0 x 0 INT6(Input) 0 1 x 1 Input Port 0 0 x 1 Output Port 1 0 x 0 INT7(Input) 0 1 x 1 Page 180 TMPM333FDFG/FYFG/FWFG 8.4.11 Port K Setting Table 8-16 Port Setting List (Port K) Pin PK0 Port Type T14 T15 PK1 PK2 T9 Function After reset PKCR PKFR1 PKFR2 PKPUP PKIE Input Port 0 0 0 0 1 Output Port 1 0 0 0 0 Input Port 0 0 0 x 1 Output Port 1 0 0 x 0 SCOUT(Output) 1 1 0 x 0 ALARM(Output) 1 0 1 x 0 Input Port 0 0 0 x 1 Output Port 1 0 0 x 0 TB9OUT(Output) 1 1 0 x 0 Note:PK0 is an N-ch open drain port. Page 181 8. 8.4 Input/Output Ports Appendix (Port setting List) TMPM333FDFG/FYFG/FWFG Page 182 TMPM333FDFG/FYFG/FWFG 9. 16-bit Timer/Event Counters(TMRB) 9.1 Outline TMRB operate in the following four operation modes: ・ ・ ・ ・ 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation mode (PPG) Timer synchronous mode The use of the capture function allows TMRB to perform the following three measurements. ・ Frequency measurement ・ Pulse width measurement ・ Time difference measurement In the following explanation of this section, "x" indicates a channel number. Page 183 9. 9.2 16-bit Timer/Event Counters(TMRB) Differences in the Specifications 9.2 TMPM333FDFG/FYFG/FWFG Differences in the Specifications TMPM333FDFG/FYFG/FWFG contains 10-channel of TMRB. Each channel functions independently and the channels operate in the same way except for the differences in their specification as shown in Table 9-1. Some of the channels can put the capture trigger and the synchronous start trigger on other channels. 1. The flip-flop output of TMRB 7 through TMRB 9 can be used as the capture trigger of other channels. ・ TB7OUT → available for TMRB0 through TMRB1 ・ TB8OUT → available for TMRB2 through TMRB4 ・ TB9OUT → available for TMRB5 through TMRB6 2. The start trigger of the timer synchronous mode (with TBxRUN) ・ TMRB0 → can start TMRB0 through TMRB3 synchronously ・ TMRB4 → can start TMRB4 through TMRB7 synchronously Table 9-1 Differences in the Specifications of TMRB Modules External pins Specification External clock/ Channel capture trigger input pins Signal TMRB0 TMRB1 Port (Pin number) TB0IN0 PH0 (30) TB0IN1 PH1 (31) TB1IN0 PH2 (32) TB1IN1 PH3 (36) Trigger function between timers Timer flip-flop output pin Signal Port trigger Synchronous start trigger channel Capture Interrupt Capture TMRB interrupt interrupt (Pin number) TB0OUT PI0 (38) TB7OUT − TB1OUT PI1 (40) TB7OUT TMRB0 TB2OUT PI2 (42) TB8OUT TMRB0 TB3OUT PI3 (48) TB8OUT TMRB0 TB4OUT PI4 (52) TB8OUT − TB5OUT PI5 (53) TB9OUT TMRB4 TB6OUT PJ4 (88) TB9OUT TMRB4 INTCAP00 INTCAP01 INTCAP10 INTCAP11 INTTB1 TB2IN0 PH4 (9) TB2IN1 PH5 (10) TB3IN0 PH6 (84) TB3IN1 PH7 (85) TB4IN0 PI6 (79) TB4IN1 PI7 (83) TB5IN0 PD0 (95) TB5IN1 PD1 (96) TB6IN0 PD2 (97) TB6IN1 PD3 (98) TMRB7 − − TB7OUT PJ5 (8) − TMRB4 − INTTB7 TMRB8 − − TB8OUT PG7 (11) − − − INTTB8 TMRB9 − − TB9OUT PK2 (7) − − − INTTB9 TMRB2 TMRB3 TMRB4 TMRB5 TMRB6 Page 184 INTCAP20 INTTB0 INTCAP21 INTCAP30 INTCAP31 INTCAP40 INTCAP41 INTCAP50 INTCAP51 INTCAP60 INTCAP61 INTTB2 INTTB3 INTTB4 INTTB5 INTTB6 TBxOUT TBxIN0 TBxIN1 Prescaler clock : φT0 Run/ clear 4 Page 185 TBxCR Match detection Interrupt mask register TBxIM Register 0 interrupt mask Figure 9-1 TMRBx Block Diagram(x= 0 to 9) Internal data bus Match detection Overflow interrupt mask Register buffer1 Timer register1 TBxRG1 Comparator (CP1) Timer flip-flop control Register 1 interrupt mask Register buffer0 Timer register0 TBxRG0 Comparator (CP0) Run/clear 16-bit up-counter (UC) TBxMOD Capture register1 TBxCP1 TBxFF0 Timer flip-flop status register TBxST Register 0 interrupt output Synchronous Start Trigger output TBxCR TBxCR φT1 φT4 φT16 Count clock TBxMOD TBxMOD Capture register0 TBxCP0 Up counter capture register TBxUC Register 1 interrupt output Synchronous Start Trigger input TBxMOD φT16 Capture control φT4 8 16 32 Prescaler/ Up-counter Control TBxRUN φT1 2 TMRBx interrupt INTTBx Timer flip-flop output TBxOUT Capture interrupt INTCAPx1 Capture interrupt INTCAPx0 9.3 Internal data bus TMPM333FDFG/FYFG/FWFG Configuration Each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer flip-flop and its associated control circuit.Timer operation modes and the timer flip-flop are controlled by a register. Overflow interrupt output 9. 9.4 16-bit Timer/Event Counters(TMRB) Registers 9.4 TMPM333FDFG/FYFG/FWFG Registers 9.4.1 Register list according to channel The following table shows the register names and addresses of each channel. Channel x Base Address Channel0 0x4001_0000 Channel1 0x4001_0040 Channel2 0x4001_0080 Channel3 0x4001_00C0 Channel4 0x4001_0100 Channel5 0x4001_0140 Channel6 0x4001_0180 Channel7 0x4001_01C0 Channel8 0x4001_0200 Channel9 0x4001_0240 Register name(x=0 to 9) Enable register Address(Base+) TBxEN 0x0000 TBxRUN 0x0004 TBxCR 0x0008 Mode register TBxMOD 0x000C Flip-flop control register TBxFFCR 0x0010 Status register TBxST 0x0014 Interrupt mask register TBxIM 0x0018 Up counter capture register TBxUC 0x001C Timer register 0 TBxRG0 0x0020 Timer register 1 TBxRG1 0x0024 Capture register 0 TBxCP0 0x0028 Capture register 1 TBxCP1 0x002C RUN register Control register Page 186 TMPM333FDFG/FYFG/FWFG 9.4.2 TBxEN (Enable register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBEN - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 TBEN R/W TMRBx operation 0: Disabled 1: Enabled Specifies the TMRB operation. When the operation is disabled, no clock is supplied to the other registers in the TMRB module. This can reduce power consumption. (This disables reading from and writing to the other registers except TBxEN register.) To use the TMRB, enable the TMRB operation (set to "1") before programming each register in the TMRB module. If the TMRB operation is executed and then disabled, the settings will be maintained in each register. 6-0 − R Read as 0. Page 187 9. 9.4 16-bit Timer/Event Counters(TMRB) Registers TMPM333FDFG/FYFG/FWFG 9.4.3 TBxRUN(RUN register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - TBPRUN - TBRUN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 TBPRUN R/W Prescaler operation 0: Stop & clear 1: Count 1 − R Read as 0. 0 TBRUN R/W Count operation 0: Stop & clear 1: Count Page 188 TMPM333FDFG/FYFG/FWFG 9.4.4 TBxCR(Control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBWBF - TBSYNC - I2TB - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 TBWBF R/W Double Buffer 0: Disabled 1: Enabled 6 − R/W Write 0. 5 TBSYNC R/W Synchronous mode switching 0: individual (unit of channel) 1: synchronous 4 − R Read as 0. 3 I2TB R/W Operation at IDLE mode 0: Stop 1:Operation 2-0 − R Read as 0. Page 189 9. 9.4 16-bit Timer/Event Counters(TMRB) Registers TMPM333FDFG/FYFG/FWFG 9.4.5 TBxMOD(Mode register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 4 2 1 7 6 5 bit symbol - - TBCP After reset 0 0 1 Bit Bit Symbol 3 TBCPM 0 Type TBCLE 0 0 0 TBCLK 0 0 Function 31-7 − R Read as 0. 6 − R/W Write 0. 5 TBCP W Capture control by software 0: Capture by software 1: Don’t care When "0" is written, the capture register 0 (TBxCP0) takes count value. Read as 1. 4-3 TBCPM[1:0] R/W Capture timing 00: Disable Capture timing 01: TBxIN0↑ TBxIN1↑ Takes count values into capture register 0 (TBxCP0) upon rising of TBxIN0 pin input. Takes count values into capture register 1 (TBxCP1) upon rising of TBxIN1 pin input. 10: TBxIN0↑ TBxIN0↓ Takes count values into capture register 0 (TBxCP0) upon rising of TBxIN0 pin input. Takes count values into capture register 1 (TBxCP1) upon falling of TBxIN0 pin input. 11: TBxOUT↑ TBxOUT↓ Takes count values into capture register 0 (TBxCP0) upon rising of 16-bit timer match output (TBxOUT) and into capture register 1 (TBxCP1) upon falling of TBxOUT. (TMRB0 and TMRB1:TB7OUT, TMRB2 through TMRB4:TB8OUT, TMRB5 and TMRB6:TB9OUT). 2 TBCLE R/W Up-counter control 0: Disables clearing of the up-counter. 1: Enables clearing of the up-counter. Clears and controls the up-counter. When "0" is written, it disables clearing of the up-counter. When "1" is written, it clears up counter when there is a match with Timer Regsiter1 (TBxRG1). 1-0 TBCLK[1:0] R/W Selects the TMRBx source clock. 00: TBxIN0 pin input 01: φT1 10: φT4 11: φT16 Page 190 TMPM333FDFG/FYFG/FWFG 9.4.6 TBxFFCR(Flip-flop control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 1 7 6 5 4 3 2 bit symbol - - TBC1T1 TBC0T1 TBE1T1 TBE0T1 After reset 1 1 0 0 0 0 Bit Bit Symbol Type 0 TBFF0C 1 1 Function 31-8 − R Read as 0. 7-6 − R Read as 1. 5 TBC1T1 R/W TBxFF0 reverse trigger when the up-counter value is taken into the TBxCP1. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when the up-counter value is taken into the Capture register 1 (TBxCP1). 4 TBC0T1 R/W TBxFF0 reverse trigger when the up-counter value is taken into the TBxCP0. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when the up-counter value is taken into the Capture register 0 (TBxCP0). 3 TBE1T1 R/W TBxFF0 reverse trigger when the up-counter value is matched with TBxRG1. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when the up-counter value is matched with the Timer register 1 (TBxRG1). 2 TBE0T1 R/W TBxFF0 reverse trigger when the up-counter value is matched with TBxRG0. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when an up-counter value is matched with the Timer register 0 (TBxRG0). 1-0 TBFF0C[1:0] R/W TBxFF0 control 00: Invert Reverses the value of TBxFF0 (reverse by using software). 01: Set Sets TBxFF0 to "1". 10: Clear Clears TBxFF0 to "0". 11: Don't care * This is always read as "11". Page 191 9. 9.4 16-bit Timer/Event Counters(TMRB) Registers TMPM333FDFG/FYFG/FWFG 9.4.7 TBxST(Status register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - INTTBOF INTTB1 INTTB0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 INTTBOF R Overflow flag 0:No overflow occurs 1:Overflow occurs When an up-counter is overflow, "1" is set. 1 INTTB1 R Match flag (TBxRG1) 0:No detection of a mach 1:Detects a match with TBxRG1 When a match with the timer register 1 (TBxRG1) is detected,"1" is set. 0 INTTB0 R Match flag (TBxRG0) 0:No match is detected 1:Detects a match with TBxRG0 When a match with the timer register 0 (TBxRG0) is detected, "1" is set. Note 1: The factors only which is not masked by TBxIM output interrupt request to the CPU.Even if the mask setting is done, the flag is set. Note 2: The flag is cleared by reading the TBxST register.To clear the flag, TBxST register should be read. Page 192 TMPM333FDFG/FYFG/FWFG 9.4.8 TBxIM(Interrupt mask register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - TBIMOF TBIM1 TBIM0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 TBIMOF R/W Overflow interrupt mask 0:Disable 1:Enable Sets the up-counter overflow interrupt to disable or enable. 1 TBIM1 R/W Match interrupt mask (TBxRG1) 0:Disable 1:Enable Sets the match interrupt mask with the Timer register 1 (TBxRG1) to enable or disable. 0 TBIM0 R/W Match interrupt mask (TBxRG0) 0:Disable 1:Enable Sets the match interrupt mask with the Timer register 0 (TBxRG0) to enable or disable. 9.4.9 TBxUC(Up counter capture register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset TBUC 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 bit symbol After reset Bit TBUC Bit Symbol Type Function 31-16 − R Read as 0. 15-0 TBUC[15:0] R Captures a value by reading up-counter out. If TBxUC is read, current up-counter value can be captured. Page 193 9. 9.4 16-bit Timer/Event Counters(TMRB) Registers TMPM333FDFG/FYFG/FWFG 9.4.10 TBxRG0(Timer register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 26 25 24 bit symbol After reset TBRG0 bit symbol After reset Bit TBRG0 0 Bit Symbol 0 0 0 Type Function 31-16 − R Read as 0. 15-0 TBRG0[15:0] R/W Sets a value comparing to the up-counter. 9.4.11 TBxRG1(Timer register 1) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset TBRG1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 bit symbol After reset Bit TBRG1 Bit Symbol Type Function 31-16 − R Read as 0. 15-0 TBRG1[15:0] R/W Sets a value comparing to the up-counter. Page 194 TMPM333FDFG/FYFG/FWFG 9.4.12 TBxCP0(Capture register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined 26 25 24 bit symbol After reset TBCP0 bit symbol After reset Bit TBCP0 Undefined Bit Symbol Undefined Undefined Undefined Type Function 31-16 − R Read as 0. 15-0 TBCP0[15:0] R A value captured from the up-counter is read. 9.4.13 TBxCP1(Capture register 1) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset TBCP1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After reset Bit TBCP1 Bit Symbol Type Function 31-16 − R Read as 0. 15-0 TBCP1[15:0] R A value captured from the up-counter is read. Page 195 9. 9.5 16-bit Timer/Event Counters(TMRB) Description of Operations for Each Circuit 9.5 TMPM333FDFG/FYFG/FWFG Description of Operations for Each Circuit The channels operate in the same way, except for the differences in their specifications as shown in Table 9-1 . 9.5.1 Prescaler There is a 4-bit prescaler to generate the source clock for up-counter UC. The prescaler input clock φT0 is fperiph/1, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selected by CGSYSCR in the CG.The peripheral clock, fperiph, is either fgear, a clock selected by CGSYSCR in the CG, or fc, which is a clock before it is divided by the clock gear. The operation or the stoppage of a prescaler is set with TBxRUN where writing "1" starts counting and writing "0" clears and stops counting. Table 9-2 and Table 9-3 show prescaler output clock resolutions. Table 9-2 Prescaler Output Clock Resolutions(fc = 40MHz) Select peripheral clock CGSYSCR Clock gear value CGSYSCR 000 (fc) 100 (fc/2) 0 (fgear) 101 (fc/4) 110 (fc/8) Select Prescaler output clock function prescaler clock CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.05 μs) fc/23 (0.2 μs) fc/25 (0.8 μs) 001 (fperiph/2) fc/22 (0.1 μs) fc/24 (0.4 μs) fc/26 (1.6 μs) 010 (fperiph/4) fc/2 (0.2 μs) fc/2 (0.8 μs) fc/27 (3.2 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 100 (fperiph/16) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 000 (fperiph/1) fc/22 (0.1 μs) fc/24 (0.4 μs) fc/26 (1.6 μs) 001 (fperiph/2) fc/2 (0.2 μs) fc/2 (0.8 μs) fc/27 (3.2 μs) 010 (fperiph/4) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 011 (fperiph/8) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 100 (fperiph/16) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/210 (25.6 μs) 101 (fperiph/32) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 000 (fperiph/1) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/28 (6.4 μs) 010 (fperiph/4) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 011 (fperiph/8) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/210 (25.6 μs) 100 (fperiph/16) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 101 (fperiph/32) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 000 (fperiph/1) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/28 (6.4 μs) 001 (fperiph/2) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 010 (fperiph/4) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 011 (fperiph/8) fc/2 (3.2 μs) fc/2 (12.8 μs) fc/211 (51.2 μs) 100 (fperiph/16) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 101 (fperiph/32) fc/29 (12.8 μs) fc/211 (51.2 μs) fc/213 (204.8 μs) 3 5 3 6 4 6 4 7 Page 196 5 7 5 8 6 8 6 9 TMPM333FDFG/FYFG/FWFG Table 9-2 Prescaler Output Clock Resolutions(fc = 40MHz) Select peripheral clock CGSYSCR Clock gear value CGSYSCR 000 (fc) 100 (fc/2) 1 (fc) 101 (fc/4) 110 (fc/8) Select Prescaler output clock function prescaler clock CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.05 μs) fc/23 (0.2 μs) fc/25 (0.8 μs) 001 (fperiph/2) fc/22 (0.1 μs) fc/24 (0.4 μs) fc/26 (1.6 μs) 010 (fperiph/4) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) 011 (fperiph/8) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/28 (6.4 μs) 100 (fperiph/16) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 101 (fperiph/32) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/210 (25.6 μs) 000 (fperiph/1) − fc/23 (0.2 μs) fc/25 (0.8 μs) 001 (fperiph/2) fc/22 (0.1 μs) fc/24 (0.4 μs) fc/26 (1.6 μs) 010 (fperiph/4) fc/2 (0.2 μs) fc/2 (0.8 μs) fc/27 (3.2 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 100 (fperiph/16) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 101 (fperiph/32) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/210 (25.6 μs) 000 (fperiph/1) − fc/23 (0.2 μs) fc/25 (0.8 μs) 001 (fperiph/2) − fc/2 (0.4 μs) fc/26 (1.6 μs) 010 (fperiph/4) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 100 (fperiph/16) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 000 (fperiph/1) − − fc/25 (0.8 μs) 001 (fperiph/2) − fc/2 (0.4 μs) fc/26 (1.6 μs) 010 (fperiph/4) − fc/25 (0.8 μs) fc/27 (3.2 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 100 (fperiph/16) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 4 6 3 6 5 5 6 8 5 8 4 7 4 7 Note 1: The prescaler output clock φTn must be selected so that φTn < fsys is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while the timer is operating. Note 3: "−" denotes a setting prohibited. Page 197 9. 9.5 16-bit Timer/Event Counters(TMRB) Description of Operations for Each Circuit TMPM333FDFG/FYFG/FWFG Table 9-3 Prescaler Output Clock Resolutions(fc = 32MHz) Select peripheral clock CGSYSCR Clock gear value CGSYSCR 000 (fc) 100 (fc/2) 0 (fgear) 101 (fc/4) 110 (fc/8) Select Prescaler output clock function prescaler clock CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) 001 (fperiph/2) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 010 (fperiph/4) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 011 (fperiph/8) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 100 (fperiph/16) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 101 (fperiph/32) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 000 (fperiph/1) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 001 (fperiph/2) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 010 (fperiph/4) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 011 (fperiph/8) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 100 (fperiph/16) fc/2 (8.0 μs) fc/2 (32.0 μs) fc/212 (128.0 μs) 101 (fperiph/32) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 4 6 4 7 4 7 5 8 Page 198 6 8 6 9 6 9 7 10 TMPM333FDFG/FYFG/FWFG Table 9-3 Prescaler Output Clock Resolutions(fc = 32MHz) Select peripheral clock CGSYSCR Clock gear value CGSYSCR 000 (fc) 100 (fc/2) 1 (fc) 101 (fc/4) 110 (fc/8) Select Prescaler output clock function prescaler clock CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) − fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) − fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) − fc/2 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) − − fc/25 (1.0 μs) 001 (fperiph/2) − fc/2 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) − fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 4 6 3 6 5 5 6 8 5 8 4 7 4 7 Note 1: The prescaler output clock φTn must be selected so that φTn < fsys is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while the timer is operating. Note 3: "−" denotes a setting prohibited. Page 199 9. 9.5 16-bit Timer/Event Counters(TMRB) Description of Operations for Each Circuit 9.5.2 TMPM333FDFG/FYFG/FWFG Up-counter (UC) UC is a 16-bit binary counter. ・ Source clock UC source clock, specified by TBxMOD, can be selected from either three types φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TBxIN0 pin. ・ Count start/ stop Counter operation is specified by TBxRUN. UC starts counting if = "1", and stops counting and clears counter value if = "0". ・ Timing to clear UC 1. When a match is detected By setting TBxMOD = "1", UC is cleared if when the comparator detects a match between counter value and the value set in TBxRG1. UC operates as a free-running counter if TBxMOD = "0". 2. When UC stops UC stops counting and clears counter value if TBxRUN = "0". ・ UC overflow If UC overflow occurs, the INTTBx overflow interrupt is generated. 9.5.3 Timer registers (TBxRG0, TBxRG1) TBxRG0 and TBxRG1 are registers for setting values to compare with up-counter values and two registers are built into each channel. If the comparator detects a match between a value set in this timer register and that in a UC up-counter, it outputs the match detection signal. TBxRG0 and TBxRG1 are consisted of the double-buffered configuration which are paired with register buffers. The double buffering is disabled in the initial state. Controlling double buffering disable or enable is specified by TBxCR bit. If = "0", the double buffering becomes disable. If = "1", it becomes enable. When the double buffering is enabled, a data transfer from the register buffer to the timer register (TBxRG0/1) is done in the case that UC is matched with TBxRG1.When the counter is stopped even if double buffering is enabled, the double buffering operates as a single buffer, and an immediate data can be written to the TBxRG0 and TBxRG1. Page 200 TMPM333FDFG/FYFG/FWFG 9.5.4 Capture This is a circuit that controls the timing of latching values from the UC up-counter into the TBxCP0 and TBxCP1 capture registers. The timing with which to latch data is specified by TBxMOD. Software can also be used to import values from the UC up-counter into the capture register; specifically, UC values are taken into the TBxCP0 capture register each time "0" is written to TBxMOD. 9.5.5 Capture registers (TBxCP0, TBxCP1) This register captures an up-counter (UC) value. 9.5.6 Up-counter capture register (TBxUC) Other than the capturing functions shown above, the current count value of the UC can be captured by reading the TBxUC registers. 9.5.7 Comparators (CP0, CP1) This register compares with the up-counter (UC) and the value setting of the Timer Register (TBxRG0 and TBxRG1) to detect whether there is a match or not. If a match is detected, INTTBx is generated. 9.5.8 Timer Flip-flop (TBxFF0) The timer flip-flop (TBxFF0) is reversed by a match signal from the comparator and a latch signal to the capture registers. It can be enabled or disabled to reverse by setting the TBxFFCR. The value of TBxFF0 becomes undefined after a reset. The flip-flop can be reversed by writing "00" to TBxFFCR. It can be set to "1" by writing "01," and can be cleared to "0" by writing "10." The value of TBxFF0 can be output to the Timer output pin (TBxOUT). If the timer output is performed, the corresponding port settings must be programmed beforehand. 9.5.9 Capture interrupt (INTCAPx0, INTCAPx1) Interrupts INTCAPx0 and INTCAPx1 can be generated at the timing of latching values from the UC up-counter into the TBxCP0 and TBxCP1 capture registers. The interrupt timing is specified by the CPU. Page 201 9. 9.6 16-bit Timer/Event Counters(TMRB) Description of Operations for Each Mode 9.6 TMPM333FDFG/FYFG/FWFG Description of Operations for Each Mode 9.6.1 16-bit Interval Timer Mode In the case of generating constant period interrupt, set the interval time to the Timer register (TBxRG1) to generate the INTTBx interrupt. 7 6 5 4 3 2 1 0 TBxEN ← 1 X X X X X X X Enables TMRBx operation. TBxRUN ← X X X X X 0 X 0 Stops count operation. Interrupt Set-Enable Register ← * * * * * * * * Permits INTTBx interrupt by setting corresponding bit to "1". TBxFFCR ← X X 0 0 0 0 1 1 Disable to TBxFF0 reverse trigger TBxMOD ← X 0 1 0 0 1 * * Changes to prescaler output clock as input clock. Specifies Capture function to disable. (** = 01, 10, 11) TBxRG1 TBxRUN ← * * * * * * * * ← * * * * * * * * ← * * * * * 1 X 1 Specifies a time interval. (16 bits) Starts TMRBx. Note:X; Don’t care −; No change 16-bit Event Counter Mode 9.6.2 It is possible to make it the event counter by using an input clock as an external clock (TBxIN0 pin input). The up-counter counts up on the rising edge of TBxIN0 pin input. It is possible to read the count value by capturing value using software and reading the captured value. 7 6 5 4 3 2 1 0 TBxEN ← 1 X X X X X X X Enables TMRBx operation. TBxRUN ← X X X X X 0 X 0 Stops count operation. PxIE[m] ← 1 PxFR1[m] ← 1 TBxFFCR ← X X 0 0 0 0 1 1 Disables to TBxFF0 reverse trigger TBxMOD ← X 0 1 0 0 0 0 0 Changes toTBxIN0 as an input clock TBxRUN ← * * * * * 1 X 1 Starts TMRBx. TBxMOD ← X 0 0 0 0 0 0 0 Software capture is done. Note 1: m: corresponding bit of port Note 2: X; Don’t care −; No change Page 202 Allocates corresponding port toTBxIN0. TMPM333FDFG/FYFG/FWFG 9.6.3 16-bit PPG (Programmable Pulse Generation) Output Mode Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active. Programmable square waves can be output from the TBxOUT pin by triggering the timer flip-flop (TBxFF) to reverse when the set value of the up-counter (UC) matches the set values of the timer registers (TBxRG0 and TBxRG1). Note that the set values of TBxRG0 and TBxRG1 must satisfy the following requirement: (Set value of TBxRG0) < (Set value of TBxRG1) Match with TBxRG0 (INTTBx interrupt) Match with TBxRG1 (INTTBx interrupt) TBxOUT pin Figure 9-2 Example of Output of Programmable Pulse Generation (PPG) In this mode, by enabling the double buffering of TBxRG0, the value of register buffer 0 is shifted into TBxRG0 when the set value of the up-counter matches the set value of TBxRG1. This facilitates handling of small duties. Match with TBxRG0 Up-counter= Q1 Up-counter= Q2 Match with TBxRG1 Trigger to shift to TBxRG1 TBxRG0 (compare value) Register buffer Q1 Q2 Q2 Q3 Write TBxRG0 Figure 9-3 Register Buffer Operation Page 203 9. 9.6 16-bit Timer/Event Counters(TMRB) Description of Operations for Each Mode TMPM333FDFG/FYFG/FWFG The block diagram of this mode is shown below. TBxOUT (PPG output) TBxRUN Selector TBxIN0 φT1 φT4 φT16 16-bit up-counter UC F/F (TBxFF0) Clear Match 16-bit comparator Selector 16-bit comparator Selector TBxRG0 Write TBxRG0 TBxRG1 Write TBxRG1 Register buffer 1 Register buffer 0 TBxCR TBxCR Internal data bus Figure 9-4 Block Diagram of 16-bit PPG Mode Each register in the 16-bit PPG output mode must be programmed as listed below. 7 6 5 4 3 2 1 0 TBxEN ← 1 X X X X X X X TBxRUN ← X X X X X 0 X 0 Stops count operation. TBxCR ← 0 0 − X − X X X Disables double buffering. TBxRG0 ← * * * * * * * * Specifies a duty. (16 bits) ← * * * * * * * * ← * * * * * * * * ← * * * * * * * * ← 1 0 X 0 0 0 0 0 TBxRG1 TBxCR Enables TMRBx operation. Specifies a cycle. (16 bits) Enables the TBxRG0 double buffering. (Changes the duty/cycle when the INTTBx interrupt is generated) TBxFFCR ← X X 0 0 1 TBxMOD ← X 0 1 0 0 1 1 0 Specifies to trigger TBxFF0 to reverse when a match with TBxRG0 or TBxRG1 is detected,and sets the initial value of TBxFF0 to "0." 1 * * Designates the prescaler output clock as the input clock,and disables the capture function. (** = 01, 10, 11) PxCR[m] ← 1 PxFR1[m] ← 1 TBxRUN ← * * * * * 1 X 1 Allocates corresponding port to TBxOUT. Starts TMRBx. Note 1: m: corresponding bit of port Note 2: X; Don’t care −; No change Page 204 TMPM333FDFG/FYFG/FWFG 9.6.4 Timer synchronous mode This mode enables the timers to start synchronously. If the mode is used with PPG output, the output can be applied to drive a motor. TMRB is consisted of two pairs of 4-channel TMRB. If one channel starts, remaining 3 channels can be start synchronously. In the TMPM333FDFG/FYFG/FWFG, the following combinations allow to use. Start trigger channel Synchronous operation channel (Master channel) (Slave channel) TMRB0 TMRB1, TMRB2, TMRB3 TMRB4 TMRB5, TMRB6, TMRB7 Use of the timer synchronous mode is specified in TBxCR bit. ・ = "0" : Timer operates individually. ・ = "1" : Timers operates synchronously. Set "0" to the bit in the master channel. If = "1" is set in the slave channel, the start timing is synchronized with master channel start timing. Setting of start timing for TBxRUN bit in the slave channel is not required. Page 205 9. 9.7 16-bit Timer/Event Counters(TMRB) Applications using the Capture Function 9.7 TMPM333FDFG/FYFG/FWFG Applications using the Capture Function The capture function can be used to develop many applications, including those described below: 1. 2. 3. 4. 9.7.1 One-shot pulse output triggered by an external pulse Frequency measurement Pulse width measurement Time difference measurement One-shot pulse output triggered by an external pulse One-shot pulse output triggered by an external pulse is carried out as follows: The 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler output clock. An external pulse is input through the TBxIN0 pin. A trigger is generated at the rising of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (TBxCP0). The CPU must be programmed so that an interrupt INTCAPx0 is generated at the rising of an external trigger pulse. This interrupt is used to set the timer registers (TBxRG0) to the sum of the TBxCP0 value (c) and the delay time (d), (c + d), and set the timer registers (TBxRG1) to the sum of the TBxRG0 values and the pulse width (p) of one-shot pulse, (c + d + p).[TBxRG1 change must be completed before the next match.] In addition, the timer flip-flop control registers(TBxFFCR) must be set to "11". This enables triggering the timer flip-flop (TBxFF0) to reverse when TBxUC matches TBxRG0 and TBxRG1. This trigger is disabled by the INTTBx interrupt after a one-shot pulse is output. Symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in "Figure 9-5 One-shot Pulse Output (With Delay)". Put the counter in a free-running state. Count clock (Internal clock) c+d c TBxIN0 pin input (External trigger pulse) Match with TBxRG0 c+d+p Taking data into the capture register (TBxCP0). INTTBx generation INTCAPx0 generation INTTBx generation Match with TBxRG1 Enable reverse Enable reverse Timer output TBxOUT pin Disable reverse when data is taken into TBxCP0. Delay time (d) Pulse width (p) Figure 9-5 One-shot Pulse Output (With Delay) Page 206 TMPM333FDFG/FYFG/FWFG The followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by triggering TBxIN0 input at the rising edge. (ΦT1 is selected for counting.) Changes source clock to ΦT1. Fetches a count value into the TBxCP0 at the rising edge of TBxIN0. 7 6 5 4 3 2 1 0 [Main processing] Capture setting by TBxIN0 PxIE[m] ← 1 PxFR1[m] ← 1 TBxEN ← 1 X X X X X X X TBxRUN ← X X X X X 0 X 0 Stops count operation. Allocates corresponding port to TBxIN0. Enables TMRBx operation. TBxMOD ← X 0 1 0 1 0 0 1 Changes source clock to ΦT1. Fetches a count value into the TBxCP0 at the rising edge of TBxIN0. TBxFFCR ← X X 0 0 0 0 1 0 Clears TBxFF0 reverse trigger and disables. PxCR[m] ← 1 PxFR1[m] ← 1 Interrupt Set-Enable Register ← * * * * * * * * Permits to generate interrupts specified by INTCAPx0 interrupt corresponding bit by setting to "1". TBxRUN ← * * * * * 1 X 1 Starts the TMRBx module. Allocates corresponding port toTBxOUT. [Processing of INTCAPx0 interrupt service routine] Pulse output setting TBxRG0 ← * * * * * * * * Sets count value. (TBxCAP0 + 3ms/ΦT1) TBxRG1 ← * * * * * * * * Sets count value.(TBxCAP0 + (3+2)ms/ΦT1) TBxFFCR ← X X − − 1 1 − − Reverses TBxFF0 if TBxRG0 consistent with TBxRG1. TBxIM ← X X X X X 1 0 1 Masks except TBxRG1 correspondence interrupt. * * Permits to generate interrupt specified by INTTBx interrupt corresponding bit setting to "1". − − Clears TBxFF0 reverse trigger setting. * Prohibits interrupts specified by INTTBx interrupt corresponding bit by setting to "1". Interrupt Set-Enable Register ← * * * * * * [Processing of INTTBx interrupt service routine] Output disable TBxFFCR Interrupt enable clear register ← ← X * X * − − * 0 * * 0 * * Note 1: m: corresponding bit of port Note 2: X; Don’t care −; No change If a delay is not required, TBxFF0 is reversed when data is taken into TBxCP0, and TBxRG1 is set to the sum of the TBxCP0 value (c) and the one-shot pulse width (p), (c + p), by generating the INTCAPx0 interrupt. (TBxRG1 change must be completed before the next match.) TBxFF0 is enabled to reverse when UC matches with TBxRG1, and is disabled by generating the INTTBx interrupt. Count clock (Prescaler output clock) TBxIN0 input (External trigger pulse) c+p c Taking data into the capture register TBxCP0. INTCAPx0 INTTBx generation generation Taking data into the capture register TBxCP1. Match with TBxRG1 Enable reverse Timer output TBxOUT pin Enable reverse when data is taken into TBxCP0. Pulse width (p) Disable reverse when data is taken into TBxCP1. Figure 9-6 One-shot Pulse Output Triggered by an External Pulse (Without Delay) Page 207 9. 9.7 16-bit Timer/Event Counters(TMRB) Applications using the Capture Function 9.7.2 TMPM333FDFG/FYFG/FWFG Frequency measurement The frequency of an external clock can be measured by using the capture function. To measure frequency, another 16-bit timer is used in combination with the 16-bit event counter mode. As an example, we explain with TMRB3 and TMRB8. TB8OUT of the 16-bit timer TMRB8 is used to specify the measurement time. TMRB3 count clock selects TB3IN0 input and performs count operation by using external clock input. If TB3MOD is set "11", TMRB3 count clock takes the counter value into the TB3CP0 at the rising edge of TB8OUT and takes the counter value into TB3CP1 at the falling edge of TB8OUT. This setting allows a count value of the 16-bit up-counter UC to be taken into the capture register (TB3CP0) upon rising of a timer flip-flop output (TB8OUT) of the 16-bit timer (TMRB8), and an UC counter value to be taken into the capture register (TB3CP1) upon falling of TB8OUT of the 16-bit timer (TMRB8). A frequency is then obtained from the difference between TB3CP0 and TB3CP1 based on the measurement, by generating the INTTB8 16-bit timer interrupt. For example, if the difference between TB3CP0 and TB3CP1 is 100 and the level width setting value of TB8OUT is 0.5 s, the frequency is 200 Hz (100 ÷ 0.5 s = 200 Hz). Count clock (TB3IN0 pin input) C1 C2 TB8OUT Taking data into TB3CP0 Taking data into TB3CP1 C1 C1 C2 INTTB8 Figure 9-7 Frequency Measurement Page 208 C2 TMPM333FDFG/FYFG/FWFG 9.7.3 Pulse width measurement By using the capture function, the "High" level width of an external pulse can be measured. Specifically, by putting it in a free-running state using the prescaler output clock, an external pulse is input through the TBxIN0 pin and the up-counter (UC) is made to count up. A trigger is generated at each rising and falling edge of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (TBxCP0, TBxCP1). The CPU must be programmed so that INTCAPx1 is generated at the falling edge of an external pulse input through the TBxIN0 pin. The "High" level pulse width can be calculated by multiplying the difference between TBxCP0 and TBxCP1 by the clock cycle of an internal clock. For example, if the difference between TBxCP0 and TBxCP1 is 100 and the cycle of the prescaler output clock is 0.5 μs , the pulse width is 100 × 0.5 μs = 50 μs. Caution must be exercised when measuring pulse widths exceeding the UC maximum count time which is dependant upon the source clock used. The measurement of such pulse widths must be made using software. The "Low" level width of an external pulse can also be measured. In such cases, the difference between C2 generated the first time and C1 generated the second time is initially obtained by performing the second stage of INTCAPx0 interrupt processing as shown in "Figure 9-8 Pulse Width Measurement" and this difference is multiplied by the cycle of the prescaler output clock to obtain the "Low" level width. Prescaler output clock C1 C2 TBxIN0 pin input (external pulse) Taking data into TBxCP0 Taking data into TBxCP1 C1 C1 C2 INTCAPx0 INTCAPx1 Figure 9-8 Pulse Width Measurement Page 209 C2 9. 9.7 16-bit Timer/Event Counters(TMRB) Applications using the Capture Function 9.7.4 TMPM333FDFG/FYFG/FWFG Time Difference Measurement The time difference of two events can be measured by the capture function. The up-counter (UC) is made to count up by putting it in a free-running state using the prescaler output clock. The value of UC is taken into the capture register (TBxCP0) at the rising edge of the TBxIN0 pin input pulse. The CPU must be programmed to generate INTCAPx0 interrupt at this time. The value of UC is taken into the capture register (TBxCP1) at the rising edge of the TBxIN1 pin input pulse. The CPU must be programmed to generate INTCAPx1 interrupt at this time. The time difference can be calculated by multiplying the difference between TBxCP1 and TBxCP0 by the clock cycle of an internal clock. Prescaler output clock C1 C2 TBxIN0 pin input TBxIN1 pin input Taking data into TBxCP0 Taking data into TBxCP1 INTCAPx0 INTCAPx1 Time difference Figure 9-9 Time Difference Measurement Page 210 TMPM333FDFG/FYFG/FWFG 10. Serial Channel (SIO/UART) 10.1 Overview This device has two mode for the serial channel, one is the synchronous communication mode (I/O interface mode), and the other is the asynchronous communication mode (UART mode). Their features are given in the following. ・ Transfer Clock - Dividing by the prescaler, from the peripheral clock (ΦT0) frequency into 1/2, 1/8, 1/32, 1/128. - Make it possible to divide from the prescaler output clock frequency into 1-16. - Make it possible to divide from the prescaler output clock frequency into 1, N+m/16 (N=2-15, m=1-15), 16. (only UART mode) - The usable system clock (only UART mode). ・ Double Buffer /FIFO The usable double buffer function, and the usable FIFO buffers of transmit and receive in all for maximum 4-byte. ・ I/O Interface Mode - Transfer Mode: the half duplex (transmit/receive), the full duplex - Clock: Output (fixed rising edge) /Input (selectable rising/falling edge) - Make it possible to specify the interval time of continuous transmission. ・ UART Mode - Data length: 7 bits, 8bits, 9bits - Add parity bit (to be against 9bits data length) - Serial links to use wake-up function - Handshaking function with CTS pin In the following explanation, "x" represents channel number. 10.2 Difference in the Specifications of SIO Modules TMPM333FDFG/FYFG/FWFG has three SIO channels. Each channel functions independently. The used pins and interrupt in each channel are collected in the following. Table 10-1 Difference in the Specifications of SIO Modules Pin name Interrupt Channel 0 Channel 1 Channel 2 TXD PE0(20pin) PE4(23pin) PF0(33pin) RXD PE1(21pin) PE5(24pin) PF1(34pin) CTS/SLCK PE2(22pin) PE6(25pin) PF2(35pin) Receive Interrupt INTRX0 INTRX1 INTRX2 Transmit Interrupt INTTX0 INTTX1 INTTX2 Page 211 10. 10.3 Serial Channel (SIO/UART) Configuration 10.3 TMPM333FDFG/FYFG/FWFG Configuration Figure 10-1 shows SIO block diagram. Prescaler 4 2 φT0 ǾT1 8 16 32 64 128 ǾT16 ǾT64 ǾT4 Serial clock generation circuit SCxBRCR TBxOUT (from TMRBx) SCxBRCR SCxBRADD Selector SCxMOD0 Selector Divider UART mode SCxBRCR Selector ǾT1 ǾT4 ǾT16 ǾT64 SIOCLK SCxMOD0 Baud rate generator fsys Selector ¸2 SCLKx input I/O interface mode SCxCR I/O interface mode SCLKx output Interrupt request INTRXx Interrupt request INTTXx Recive counter SCxMOD0 (Only at UART : ÷16) Serial channel Interrupt control (Only at UART : ÷16) TXDCLK RXDCLK SCxMOD0 Transmission counter Transmission control Recive control CTSx SCxCR SCxMOD0 Parity control RXDx Recive shift register RB8 Recive buffer (SCxBUF) error flag TB8 Transmit buffer (SCxBUF) SCxCR FIFO control Internal data bus TXDx Transmit shift register Internal data bus FIFO control Internal data bus Figure 10-1 SIO Block Diagram Page 212 TMPM333FDFG/FYFG/FWFG 10.4 Registers Description 10.4.1 Registers List in Each Channel The each channel registers and addresses are shown here. Channel x Base Address Channel0 0x4002_0080 Channel1 0x4002_00C0 Channel2 0x4002_0100 Register name (x=0 to 2) Address (Base+) Enable register SCxEN 0x0000 Buffer register SCxBUF 0x0004 Control register SCxCR 0x0008 Mode control register 0 SCxMOD0 0x000C Baud rate generator control register SCxBRCR 0x0010 SCxBRADD 0x0014 Baud rate generator control register 2 Mode control register 1 SCxMOD1 0x0018 Mode control register 2 SCxMOD2 0x001C RX FIFO configuration register SCxRFC 0x0020 TX FIFO configuration register SCxTFC 0x0024 RX FIFO status register SCxRST 0x0028 SCxTST 0x002C SCxFCNF 0x0030 TX FIFO status register FIFO configuration register Note:Do not modify any control register when data is being transmitted or received. Page 213 10. 10.4 Serial Channel (SIO/UART) Registers Description 10.4.2 TMPM333FDFG/FYFG/FWFG SCxEN (Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - SIOE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 SIOE R/W SIO operation 0: Disabled 1: Enabled Specified the SIO operation. To use the SIO, set = "1". When the operation is disabled, no clock is supplied to the other registers in the SIO module. This can reduce the power consumption. If the SIO operation is executed and then disabled, the settings will be maintained in each register except for SCxTFC. Page 214 TMPM333FDFG/FYFG/FWFG 10.4.3 SCxBUF (Buffer Register) SCxBUF works as a transmit buffer or FIFO for write operation and as a receive buffer or FIFO for read operation. bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After reset Bit TB / RB 0 Bit Symbol 0 0 0 Type Function 31-8 − R Read as 0. 7-0 TB[7:0] / RB [7:0] R/W [write] TB : Transmit buffer / FIFO [read] RB : Receive buffer / FIFO Page 215 10. 10.4 Serial Channel (SIO/UART) Registers Description 10.4.4 TMPM333FDFG/FYFG/FWFG SCxCR (Control Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 RB8 R Receive data bit 8 (For UART) 6 EVEN R/W 9th bit of the received data in the 9 bits UART mode. Parity (For UART) 0: Odd 1: Even Selects even or odd parity. "0" : odd parity, "1" : even parity. The parity bit may be used only in the 7- or 8-bit UART mode. 5 PE R/W Add parity (For UART) 0: Disabled 1: Enabled Controls enabling/ disabling parity. The parity bit may be used only in the 7- or 8-bit UART mode. 4 OERR R Overrun error flag (Note) 0: Normal operation 1: Error 3 PERR R Parity / Underrun error flag (Note) 0: Normal operation 1: Error 2 FERR R Framing error flag (Note) 0: Normal operation 1: Error 1 SCLKS R/W Selecting input clock edge (For I/O Interface) 0: Rising edges 1: Falling edges Selects input clock edge for data transmission and reception. Set to "0" in the clock output mode. 0 IOC R/W Selecting clock (For I/O Interface) 0: Baud rate generator 1: SCLK pin input Note:Any error flag (OERR, PERR, FERR) is cleared to "0" when read. Page 216 TMPM333FDFG/FYFG/FWFG 10.4.5 SCxMOD0 (Mode Control Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol TB8 CTSE RXE WU After reset 0 0 0 0 Bit Bit Symbol Type SM 0 0 SC 0 0 0 Function 31-8 − R Read as 0. 7 TB8 R/W Transmit data bit 8 (For UART) Writes the 9th bit of transmit data in the 9 bits UART mode. 6 CTSE R/W Handshake function control (For UART) 0: CTS disabled 1: CTS enabled Controls handshake function. Setting "1" enables handshake function using CTS pin. 5 RXE R/W Receive control (Note) 0: Disabled 1: Enabled 4 WU R/W Wake-up function (For UART) 0: Disabled 1: Enabled This function is available only at 9-bit UART mode. In other mode, this function has no meaning. In it is Enabled, Interrupt only when RB9 = "1" at 9-bit UART mode. 3-2 SM[1:0] R/W Specifies transfer mode. 00: I/O interface mode 01: 7-bit length UART mode 10: 8-bit length UART mode 11: 9-bit length UART mode 1-0 SC[1:0] R/W Serial transfer clock (For UART) 00: Timer TB9OUT 01: Baud rate generator 10: Internal clock fsys 11: External clock (SCLK input) (As for the I/O interface mode, the serial transfer clock can be set in the control register (SCxCR). Note 1: With set to "0", set each mode register (SCxMOD0, SCxMOD1 and SCxMOD2). Then set to "1". Note 2: Do not stop the receive operation (by setting SCxMOD0 = "0") when data is being received. Page 217 10. 10.4 Serial Channel (SIO/UART) Registers Description 10.4.6 TMPM333FDFG/FYFG/FWFG SCxMOD1 (Mode Control Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 4 3 2 1 0 bit symbol I2SC After reset 0 Bit Bit Symbol 5 FDPX 0 TXE 0 0 Type SINT 0 0 0 0 Function 31-8 − R Read as 0. 7 I2SC R/W IDLE 0: Stop 1: Operate Specifies the IDLE mode operation. 6-5 FDPX[1:0] R/W Transfer mode setting 00: Transfer prohibited 01: Half duplex (Recieve) 10: Half duplex (Trasmitt) 11: Full duplex Configures the transfer mode in the I/O interface mode. Also configures the FIFO if it is enabled. In the UART mode, it is used only to specify the FIFO configuration. 4 TXE R/W Transmit control (Note) 0 :Disabled 1: Enabled This bit enables transmission and is valid for all the transfer modes. 3-1 SINT[2:0] R/W Interval time of continuous transmission (For I/O interface) 000: None 001: 1SCLK 010: 2SCLK 011: 4SCLK 100: 8SCLK 101: 16SCLK 110: 32SCLK 111: 64SCLK This parameter is valid only for the I/O interface mode when SCLK pin output is selected. In other modes, this function has no meaning. Specifies the interval time of continuous transmission when double buffering or FIFO is enabled in the I/O interface mode. 0 − R/W Write a "0". Note 1: Specify the all mode first and then enable the bit. Note 2: Do not stop the transmit operation (by setting = "0")when data is being transmitted. Page 218 TMPM333FDFG/FYFG/FWFG 10.4.7 SCxMOD2 (Mode Control Register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol TBEMP RBFLL TXRUN SBLEN DRCHG WBUF After reset 1 0 0 0 0 0 Bit Bit Symbol Type 0 SWRST 0 0 Function 31-8 − R Read as 0. 7 TBEMP R Transmit buffer empty flag. 0: Full 1: Empty If double buffering is disabled, this flag is insignificant. This flag shows that the transmit double buffers are empty. When data in the transmit double buffers is moved to the transmit shift register and the double buffers are empty, this bit is set to "1". Writing data again to the double buffers sets this bit to "0". 6 RBFLL R Receive buffer full flag. 0: Empty 1: Full This is a flag to show that the receive double buffers are full. When a receive operation is completed and received data is moved from the receive shift register to the receive double buffers, this bit changes to "1" while reading this bit changes it to "0". If double buffering is disabled, this flag is insignificant. 5 TXRUN R In transmission flag 0: Stop 1: Operate This is a status flag to show that data transmission is in progress. and bits indicate the following status. 1 − Transmission in progress 1 Transmission completed 0 Wait state with data in Transmitt buffer 0 4 SBLEN R/W Status STOP bit (for UART) 0 : 1-bit 1 : 2-bit This specifies the length of transmission stop bit in the UART mode. On the receive side, the decision is made using only a single bit regardless of the setting. 3 DRCHG R/W Setting transfer direction 0: LSB first 1: MSB first Specifies the direction of data transfer in the I/O interface mode. In the UART mode, set this bit to LSB first. Page 219 10. 10.4 Serial Channel (SIO/UART) Registers Description Bit 2 Bit Symbol WBUF TMPM333FDFG/FYFG/FWFG Type R/W Function Double-buffer 0: Disabled 1 : Enabled This parameter enables or disables the transmit/receive double buffers to transmit (in both SCLK output/input modes) and receive (in SCLK output mode) data in the I/O interface mode and to transmit data in the UART mode. When receiving data in the I/O interface mode (SCLK input) and UART mode, double buffering is enabled in both cases that 0 or 1 is set to bit. 1-0 SWRST[1:0] R/W Software reset Overwriting "01" in place of "10" generates a software reset. When this software reset is executed, the following bits are initialized and the transmit/receive circuit, the transmit circuit and the FIFO become initial state (see Note1 and Note2). Register Bit SCxMOD0 RXE SCxMOD1 TXE SCxMOD2 TBEMP, RBFLL, TXRUN SCxCR OERR, PERR, FERR Note 1: While data transmission is in progress, any software reset operation must be executed twice in succession. Note 2: A software reset requires 2 clocks-duration at the time between the end of recognition and the start of execution of software reset instruction. Page 220 TMPM333FDFG/FYFG/FWFG 10.4.8 SCxBRCR (Baud Rate Generator Control Register), SCxBRADD (Baud Rate Generator Control Register 2) The division ratio of the baud rate generator can be specified in the registers shown below. SCxBRCR 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 7 6 bit symbol - BRADDE After reset 0 0 Bit Bit Symbol BRCK 0 BRS 0 Type 0 Function 31-8 − R Read as 0. 7 − R/W Write "0". 6 BRADDE R/W N + (16 − K)/16 divider function (For UART) 0: disabled 1: enabled This division function can only be used in the UART mode. 5-4 BRCK[1:0] R/W Select input clock to the baud rate generator. 00: φT1 01: φT4 10: φT16 11: φT64 3-0 BRS[3:0] R/W Division ratio "N" 0000: 16 0001: 1 0010: 2 ... 1111: 15 Page 221 0 10. 10.4 Serial Channel (SIO/UART) Registers Description TMPM333FDFG/FYFG/FWFG SCxBRADD bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol - - - - After reset 0 0 0 0 Bit Bit Symbol BRK Type Function 31-4 − R Read as 0. 3-0 BRK[3:0] R/W Specify K for the "N + (16 − K)/16" division (For UART) 0000: Prohibited 0001: K = 1 0010: K = 2 ... 1111: K = 15 Table 10-2 lists the settings of baud rate generator division ratio. Table 10-2 Setting division ratio = "0" = "1" (Note1) (Only UART mode) Specify "N" (Note2) (Note3) No setting required Division ratio Divide by N Specify "K" (Note4) N+ (16 − K) GLYLVLRQ 16 Note 1: To use the "N + (16 - K)/16" division function, be sure to set to "1" after setting the K value to . The "N + (16 - K)/16" division function can only be used in the UART mode. Note 2: As a division ratio, 1 ("0001") or 16 ("0000") can not be applied to N when using the "N + (16 - K)/16" division function in the UART mode. Note 3: The division ratio "1" of the baud rate generator can be specified only when the double buffering is used in the I/O interface mode. Note 4: Specifying "K = 0" is prohibited. Page 222 TMPM333FDFG/FYFG/FWFG 10.4.9 SCxFCNF ( FIFO Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - RFST TFIE RFIE RXTXCNT CNFG After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0 7-5 - R/W Be sure to write "000" 4 RFST R/W Bytes used in RX FIFO 0:Maximum 1:Same as FILL level of RX FIFO When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected (Note1) 0: The maximun number of bytes of the FIFO configured (see also ). 1: Same as the fill level for receive interrupt generation specified by SCxRFC 3 TFIE R/W TX interrupt for TX FIFO 0: Disabled 1:Enabled When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter. 2 RFIE R/W RX interrupt for RX FIFO 0: Disabled 1:Enabled When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter. 1 RXTXCNT R/W Automatic disable of RXE/TXE 0: None 1: Auto diabled Controls automatic disabling of transmission and reception. Setting "1" enables to operate as follows Half duplex RX When receive shift register, the receive buffer and the RX FIFO are filled, SCxMOD0 is automatically set to "0" to inhibit further reception. Half duplex TX When the TX FIFO, the transmit buffer and the transmit shift register is empty, SCxMOD1 is automatically set to "0" to inhibit further transmission. Full duplex 0 CNFG R/W When either of the above two conditions is satisfied, TXE/RXE are automatically set to "0" to inhibit further transmission and reception. Enables FIFO. 0: Disabled 1: Enabled If enabled, the SCxMOD1 setting automatically configures FIFO as follows: (The type of TX/RX can be specified in the mode control register 1 SCxMOD1). Half duplex RX RX FIFO 4byte Half duplex TX TX FIFO 4byte Full duplex RX FIFO 2byte + TX FIFO 2byte Note 1: Regarding TX FIFO, the maximum number of bytes being configured is always available. The available number of bytes is the bytes already written to the TX FIFO. Note 2: The FIFO can not use in 9bit UART mode. Page 223 10. 10.4 Serial Channel (SIO/UART) Registers Description TMPM333FDFG/FYFG/FWFG 10.4.10 SCxRFC (RX FIFO Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol RFCS RFIS - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 RIL 0 0 Function 31-8 − R Read as 0. 7 RFCS W RX FIFO clear 1: Clear Setting "1" clears RX FIFO and "0" is always read. 6 RFIS R/W Select interrupt generation condition 0: when the data reaches to the specified fill level. 1: when the data reaches to the specified fill level or the data exceeds the specified fill level at the time data is read. 5-2 − R Read as 0. 1-0 RIL[1:0] R/W FIFO fill level to generate RX interrupts Half duplex Full duplex 00 4byte 2byte 01 1byte 1byte 10 2byte 2byte 11 3byte 1byte Note:To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode (half duplex/ full duplex) and enabling FIFO (SCxFCNF = "1"). Page 224 TMPM333FDFG/FYFG/FWFG 10.4.11 SCxTFC (TX FIFO Configuration Register) (Note2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol TFCS TFIS - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 TIL 0 0 Function 31-8 − R Read as 0. 7 TFCS W TX FIFO clear (Note 1) 1: Clears TX FIFO. Setting "1" clears TX FIFO and "0" is always read. 6 TFIS R/W Selects interrupt generation condition. 0: An interrupt is generated when the data reaches to the specified fill level. 1: An interrupt is generated when the data reaches to the specified fill level or the data can not reach the specified fill level at the time new data is read. 5-2 − R Read as 0. 1-0 TIL[1:0] R/W Selects FIFO fill level. Other than full duplex Full duplex 00 Empty Empty 01 1 byte 1 byte 10 2 byte Empty 11 3 byte 1 byte Note 1: To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode (half duplex/full duplex) and enabling FIFO (SCxFCNF = "1"). Note 2: After you perform the following operations, configure the SCxTFC register again. SCxEN = "0" (SIO operation stop) Conditions are as follows:SCxMOD1 = "0" (operation is prohibited in IDLE mode) and releasing the low power consumption mode which started by the WFI (Wait For Interrupt) instruction. Page 225 10. 10.4 Serial Channel (SIO/UART) Registers Description TMPM333FDFG/FYFG/FWFG 10.4.12 SCxRST (RX FIFO Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ROR - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type RLVL 0 0 Function 31-8 − R Read as 0. 7 ROR R RX FIFO Overrun (Note) 0: Not generated 1: Generated 6-3 − R Read as 0. 2-0 RLVL[2:0] R Status of RX FIFO fill level. 000: Empty 001: 1 byte 010: 2 byte 011: 3 byte 100: 4 byte Note:The bit is cleared to "0" when receive data is read from the SCxBUF register. Page 226 0 TMPM333FDFG/FYFG/FWFG 10.4.13 SCxTST (TX FIFO Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TUR - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type TLVL 0 0 Function 31-8 − R Read as 0. 7 TUR R TX FIFO under run (Note) 0: Not generated 1: Generated. 6-3 − R Read as 0. 2-0 TLVL[2:0] R Status of TX FIFO fill level. 000: Empty 001: 1 byte 010: 2 byte 011: 3 byte 100: 4 byte Note:The bit is cleared to "0" when transmit data is written to the SCxBUF register. Page 227 0 10. Serial Channel (SIO/UART) 10.5 Operation in Each Mode 10.5 TMPM333FDFG/FYFG/FWFG Operation in Each Mode Table 10-3 shows the modes and data formats. Table 10-3 Mode and Data format Mode Mode type Data length Transfer direction Specifies whether to use parity bits. STOP bit length (transmit) Mode 0 Synchronous communication mode 8 bit LSB first/MSB first - - (IO interface mode) Mode 1 Mode 2 Mode 3 Asynchronous communication mode (UART mode) 7 bit 8 bit ο LSB first 9 bit ο 1 bit or 2 bit × Mode 0 is a synchronous communication and can be used to extend I/O. This mode transmits and receives data in synchronization with SCLK. SCLK can be used for both input and output. The direction of data transfer can be selected from LSB first and MSB first. This mode is not allowed either to use parity bits or STOP bits. The mode 1, mode 2 and mode 3 are asynchronous modes and the transfer direction is fixed to the LSB first. Parity bits can be added in the mode 1 and mode 2. The mode 3 has a wakeup function in which the master controller can start up slave controllers via the serial link (multi-controller system). STOP bit in transmission can be selected from 1 bit and 2 bits. The STOP bit length in reception is fixed to a one bit. Page 228 TMPM333FDFG/FYFG/FWFG 10.6 Data Format 10.6.1 Data Format List Figure 10-2 shows data format. ● Mode0 (I/O interface mode) / LSB first bit 0 1 2 3 4 5 6 7 3 2 1 0 Transmission direction ● Mode0 (I/O interface mode ) / MSB first bit 7 6 5 4 Transmission direction ● ● ● Mode1 (7bits UART mode) Without parity start bit 0 1 2 3 4 5 6 stop With parity start bit 0 1 2 3 4 5 6 parity stop Mode2 (8bits UART mode) Without parity start bit 0 1 2 3 4 5 6 7 stop With parity start bit 0 1 2 3 4 5 6 7 parity stop start bit 0 1 2 3 4 5 6 7 8 stop start bit 0 1 2 3 4 5 6 7 bit 8 Mode3 (9bits UART mode) bit 8 = 1 represents address. (select code) bit 8 = 0 represents data. Figure 10-2 Data Format Page 229 stop (Wake-up) 10. 10.6 Serial Channel (SIO/UART) Data Format 10.6.2 TMPM333FDFG/FYFG/FWFG Parity Control The parity bit can be added only in the 7- or 8-bit UART mode. Setting "1" to SCxCR enables the parity. The bit of SCxCR selects either even or odd parity. 10.6.2.1 Transmission Upon data transmission, the parity control circuit automatically generates the parity with the data in the transmit buffer. After data transmission is complete, the parity bit will be stored in SCxBUF in the 7-bit UART mode and SCxMOD in the 8-bit UART mode. The and settings must be completed before data is written to the transmit buffer. 10.6.2.2 Receiving Data If the received data is moved from the receive shift register to the receive buffer, a parity is generated. In the 7-bit UART mode, the generated parity is compared with the parity stored in SCxBUF, while in the 8-bit UART mode, it is compared with the one in SCxCR. If there is any difference, a parity error occurs and the of the SCxCR register is set to "1". In use of the FIFO, indicates that a parity error was generated in one of the recieved data. 10.6.3 STOP Bit Length The length of the STOP bit in the UART transmission mode can be selected from one bit or two bits by setting the SCxMOD2. The length of the STOP bit data is determined as one-bit when it is received regardless of the setting of this bit. Page 230 TMPM333FDFG/FYFG/FWFG 10.7 Clock Control 10.7.1 Prescaler There is a 7-bit prescaler to divide a prescaler input clock ΦT0 by 2, 8, 32 and 128. Use the CGSYSCR register in the clock/mode control block to select the input clock ΦT0 of the prescaler. The prescaler becomes active only when the baud rate generator is selected as a transfer clock by SCxMOD0 = "11". Table 10-4 (operation frequency 40MHz), Table 10-5 (operation frequency 32MHz) show the resolution of the input clock to the baud rate generator. Table 10-4 Clock Resolution to the Baud Rate Generator fc = 40 MHz peripheral clock selection Clock gear value Prescaler clock selection CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 (fgear) 101 (fc/4) 110 (fc/8) Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.05 μs) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) fc/2 (0.1 μs) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/28 (6.4 μs) 010 (fperiph/4) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 100 (fperiph/16) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/2 (12.8 μs) fc/211 (51.2 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 000 (fperiph/1) fc/22 (0.1 μs) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 001 (fperiph/2) fc/2 (0.2 μs) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 010 (fperiph/4) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 011 (fperiph/8) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/2 (12.8 μs) fc/211 (51.2 μs) 100 (fperiph/16) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 101 (fperiph/32) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) fc/213 (204.8 μs) 000 (fperiph/1) fc/2 (0.2 μs) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 001 (fperiph/2) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 010 (fperiph/4) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 011 (fperiph/8) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/2 (25.6 μs) fc/212 (102.4 μs) 100 (fperiph/16) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) fc/213 (204.8 μs) 101 (fperiph/32) fc/2 (6.4 μs) fc/2 (25.6 μs) fc/2 (102.4 μs) fc/214 (409.6 μs) 000 (fperiph/1) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 001 (fperiph/2) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 010 (fperiph/4) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/2 (25.6 μs) fc/212 (102.4 μs) 011 (fperiph/8) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) fc/213 (204.8 μs) 100 (fperiph/16) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) fc/214 (409.6 μs) 101 (fperiph/32) fc/2 (12.8 μs) fc/2 (51.2 μs) fc/2 (204.8 μs) fc/215 (819.2 μs) 2 5 3 5 3 6 8 6 9 Page 231 4 7 5 7 5 8 10 8 11 6 9 7 9 7 10 12 10 13 10. 10.7 Serial Channel (SIO/UART) Clock Control TMPM333FDFG/FYFG/FWFG Table 10-4 Clock Resolution to the Baud Rate Generator fc = 40 MHz peripheral clock selection Clock gear value Prescaler clock selection CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 1 (fc) 101 (fc/4) 110 (fc/8) Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.05 μs) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) fc/2 (0.1 μs) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/28 (6.4 μs) 010 (fperiph/4) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 011 (fperiph/8) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/210 (25.6 μs) 100 (fperiph/16) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 000 (fperiph/1) − fc/2 (0.2 μs) fc/2 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) fc/22 (0.1 μs) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 010 (fperiph/4) fc/23 (0.2 μs) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) 011 (fperiph/8) fc/2 (0.4 μs) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/210 (25.6 μs) 100 (fperiph/16) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 000 (fperiph/1) − fc/2 (0.2 μs) fc/2 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) − fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 010 (fperiph/4) fc/2 (0.2 μs) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 100 (fperiph/16) fc/25 (0.8 μs) fc/27 (3.2 μs) fc/29 (12.8 μs) fc/211 (51.2 μs) 101 (fperiph/32) fc/2 (1.6 μs) fc/2 (6.4 μs) fc/2 (25.6 μs) fc/212 (102.4 μs) 000 (fperiph/1) − − fc/25 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) − fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) 010 (fperiph/4) − fc/2 (0.8 μs) fc/2 (3.2 μs) fc/29 (12.8 μs) 011 (fperiph/8) fc/24 (0.4 μs) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) 100 (fperiph/16) fc/2 (0.8 μs) fc/2 (3.2 μs) fc/2 (12.8 μs) fc/211 (51.2 μs) 101 (fperiph/32) fc/26 (1.6 μs) fc/28 (6.4 μs) fc/210 (25.6 μs) fc/212 (102.4 μs) 2 4 4 3 6 5 4 6 3 6 3 5 8 5 7 6 8 5 8 5 7 10 7 9 Note 1: The prescaler output clock φTn must be selected so that the relationship "φTn ≤ fsys / 2" is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while SIO is operating. Note 3: The dashes in the above table indicate that the setting is prohibited. Page 232 TMPM333FDFG/FYFG/FWFG Table 10-5 Clock Resolution to the Baud Rate Generator fc = 32 MHz peripheral clock selection Clock gear value Prescaler clock selection CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 (fgear) 101 (fc/4) 110 (fc/8) Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) fc/2 (0.0625 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 001 (fperiph/2) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 010 (fperiph/4) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 011 (fperiph/8) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 100 (fperiph/16) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 101 (fperiph/32) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 000 (fperiph/1) fc/2 (0.0625 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 001 (fperiph/2) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 010 (fperiph/4) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 011 (fperiph/8) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 100 (fperiph/16) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 101 (fperiph/32) fc/2 (8.0 μs) fc/2 (32.0 μs) fc/2 (128.0 μs) fc/214 (512.0 μs) 000 (fperiph/1) fc/21 (0.0625 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 001 (fperiph/2) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 010 (fperiph/4) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/2 (32.0 μs) fc/212 (128.0 μs) 011 (fperiph/8) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 100 (fperiph/16) fc/2 (8.0 μs) fc/2 (32.0 μs) fc/2 (128.0 μs) fc/214 (512.0 μs) 101 (fperiph/32) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) fc/215 (1024 μs) 2 4 1 5 1 5 8 6 8 Page 233 4 6 4 7 5 7 10 8 10 6 8 6 9 7 9 12 10 12 10. 10.7 Serial Channel (SIO/UART) Clock Control TMPM333FDFG/FYFG/FWFG Table 10-5 Clock Resolution to the Baud Rate Generator fc = 32 MHz peripheral clock selection Clock gear value Prescaler clock selection CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 1 (fc) 101 (fc/4) 110 (fc/8) Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) − fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) − fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) − fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/2 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) − − fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) − fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) − fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 2 4 4 3 6 5 4 6 3 6 3 5 8 5 7 6 8 5 8 5 7 10 7 9 Note 1: The prescaler output clock φTn must be selected so that the relationship "φTn ≤ fsys / 2" is satisfied (so that φTn is slower than fsys / 2). Note 2: Do not change the clock gear while SIO is operating. Note 3: The dashes in the above table indicate that the setting is prohibited. Page 234 TMPM333FDFG/FYFG/FWFG 10.7.2 Serial Clock Generation Circuit The serial clock circuit is a block to generate transmit and receive clocks (SIOCLK) and consists of the circuits in which clocks can be selected by the settings of the baud rates generator and modes. 10.7.2.1 Baud Rate Generator The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate. (1) Baud Rate Generator input clock The input clock of the baud rate generator is selected from the prescaler outputs divided by 2, 8, 32 and 128. This input clock is selected by setting the SCxBRCR. (2) Baud Rate Generator output clock The frequency division ratio of the output clock in the baud rate generator is set by SCxBRCR and SCxBRADD. The following frequency divide ratios can be used; 1/N frequency division in the I/O interface mode ,either 1/N or N + (16-K)/16 in the UART mode. The table below shows the frequency division ratio which can be selected. Mode I/O interface UART Divide Function Setting Divide by N Divide by K SCxBRCR SCxBRCR SCxBRADD Divide by N 1 to 16 (Note) - Divide by N 1 to 16 - N + (16-K)/16 division 2 to 15 1 to 15 Note:1/N (N=1)frequency division ratio can be used only when a double buffer is enabled. Page 235 10. 10.7 Serial Channel (SIO/UART) Clock Control TMPM333FDFG/FYFG/FWFG 10.7.2.2 Clock Selection Circuit A clock can be selected by setting the modes and the register. Modes can be specified by setting the SCxMOD0. The input clock in I/O interface mode is selected by setting SCxCR. The clock in UART mode is selected by setting SCxMOD0. (1) Transfer Clock in I/O interface mode Table 10-6 shows clock selection in I/O interface mode. Table 10-6 Clock Selection in I/O Interface Mode Input/Output Mode Clock edge selection selection SCxMOD0 SCLK output Clock of use SCxCR SCxCR Set to "0". (Fixed to the rising edge) Divided by 2 of the baud rate generator output. Rising edge SCLK input rising edge Falling edge SCLK input falling edge I/O interface mode SCLK input To get the highest baud rate, the baud rate generator must be set as below. Note:When deciding clock settings, make sure that AC electrical character is satisfied. ・ Clock/mode control block settings - fc = 40MHz - fgear = 40MHz (CGSYSCR = "000" : fc selected) - ΦT0 = 40MHz (CGSYSCR = "000" : 1 division ratio) ・ SIO settings (if double buffer is used) - Clock (SCxBRCR = "00" : ΦT1 selected) = 20MHz - Divided clock frequency (SCxBRCR = "0001" : 1 division ratio) = 20MHz 1 division ratio can be selected if double buffer is used. In this case, baud rate is 10Mbps because 20MHz is divided by 2. ・ SIO settings (if double buffer is not used) - Clock (SCxBRCR = "00" : ΦT1 selected) = 20MHz - Divided clock frequency (SCxBRCR = "0010" : 2 division ratio) = 10MHz 2 division ratio is the highest if double buffer is not used. In this case, baud rate is 5Mbps because 10MHz is divided by 2. To use SCLK input, the following conditions must be satisfied. ・ If double buffer is used - SCLK cycle > 6/fsys The highest baud rate is less than 40 ÷ 6 = 6.66 Mbps. ・ If double buffer is not used - SCLK cycle > 8/fsys Page 236 TMPM333FDFG/FYFG/FWFG The highest baud rate is less than 40 ÷ 8 = 5.0 Mbps. (2) Transfer clock in the UART mode Table 10-7 shows the clock selection in the UART mode. In the UART mode, selected clock is divided by 16 in the receive counter or the transmit counter before use. Table 10-7 Clock Selection in UART Mode Mode Clock selection SCxMOD0 SCxMOD0 Timer output Baud rate generator UART Mode fsys SCLK input The examples of baud rate in each clock settings. ・ If the baud rate generator is used - fc = 40MHz - fgear = 40MHz (CGSYSCR = "000" : fc selected) - ΦT0 = 40MHz (CGSYSCR = "000" : 1 division ratio) - Clock = ΦT1 = 20MHz (SCxBRCR = "00" : ΦT1 selected) The highest baud rate is 1.25Mbps because 20MHz is divided by 16. Table 10-8 shows examples of baud rate when the baud rate generator is used with the following clock settings. ・ fc = 9.8304MHz ・ fgear = 9.8304MHz (CGSYSCR = "000" : fc selected) ・ ΦT0 = 4.9152MHz (CGSYSCR = "001" : 2 division ratio) Table 10-8 Example of UART Mode Baud Rate (Using the Baud Rate Generator) fc [MHz] 9.830400 Division ratio N φT1 φT4 φT16 φT64 (SCxBRCR) (fc/4) (fc/16) (fc/64) (fc/256) 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 16 9.600 2.400 0.600 0.150 Unit：kbps ・ If the SCLK input is used To use SCLK input, the following conditions must be satisfied. - SCLK cycle > 2/fsys The highest baud rate must be less than 40 ÷ 2 ÷ 16 = 1.25 Mbps. ・ If fsys is used Since the highest value of fsys is 40MHz, the highest baud rate is 40 ÷ 16 = 2.5Mbps. Page 237 10. 10.7 Serial Channel (SIO/UART) Clock Control TMPM333FDFG/FYFG/FWFG ・ If timer output is used To enable the timer output, the following condition must be set: a timer flip-flop output inverts when the value of the counter and that of TBxRG0 match. The SIOCLK clock frequency is "Setting value of TBxRG0 × 2". Baud rates can be obtained by using the following formula. Baud rate calculation Transfer rate = Clock frequency selected by CGSYSCR (TBxRG0 × 2) × 2 × 16 In the case the tim er prescaler clock Φ T 1 (2div ition ratio) is selected. O ne clock cycle is a period that the tim er flip-flop is inv erted twice. Table 10-9 shows the examples of baud rates when the timer output is used with the following clock settings. ・ fc = 32MHz / 9.8304MHz / 8MHz ・ fgear = 32MHz / 9.8304MHz / 8MHz (CGSYSCR = "000" : fc selected) ・ ΦT0 = 16MHz / 4.9152MHz / 4MHz (CGSYSCR = "001" : 2 division ratio) ・ Timer count clock = 4MHz / 1.2287MHz / 1MHz (TBxMOD = "01" : ΦT1 selected) Table 10-9 Example of UART Mode Baud Rate (Using the Timer Output) TBxRG0 setting fc 32MHz 9.8304MHz 8MHz 0x0001 250 76.8 62.5 0x0002 125 38.4 31.25 0x0003 - 25.6 - 0x0004 62.5 19.2 15.625 0x0005 50 15.36 12.5 0x0006 - 12.8 - 0x0008 31.25 9.6 - 0x000A 25 7.68 6.25 0x0010 15.625 4.8 - 0x0014 12.5 3.84 3.125 Unit：kbps Page 238 TMPM333FDFG/FYFG/FWFG 10.8 Transmit/Receive Buffer and FIFO 10.8.1 Configuration Figure 10-3 shows the configuration of transmit buffer, receive buffer and FIFO. Appropriate settings are required for using buffer and FIFO. The configuration may be predefined depending on the mode. 4GEGKXGUJKHVTGIKUVGT 4:& 6TCPUOKVUJKHVTGIKUVGT 6TCPUOKVDWHHGT 4GEGKXGDWHHGT 4GEGKXG(+(1 6:& (KTUVUVCIG 6TCPUOKV(+(1 (KTUVUVCIG 5GEQPFUVCIG 5GEQPFUVCIG 6JKTFUVCIG 6JKTFUVCIG (QWTVJUVCIG (QWTVJUVCIG Figure 10-3 The Configuration of Buffer and FIFO 10.8.2 Transmit/Receive Buffer Transmit buffer and receive buffer are double-buffered. The buffer configuration is specified by SCxMOD2. In the case of using a receive buffer, if SCLK input is set to generate clock output in the I/O interface mode or the UART mode is selected, it’s double buffered despite the settings. In other modes, it’s according to the settings. Table 10-10 shows correlation between modes and buffers. Table 10-10 Mode and buffer Composition SCxMOD2 Mode UART 10.8.3 "0" "1" Transmit Single Double Receive Double Double I/O interface Transmit Single Double (SCLK input) Receive Double Double I/O interface Transmit Single Double (SCLK output) Receive Single Double FIFO In addition to the double buffer function above described, 4-byte FIFO can be used. Page 239 10. 10.9 Serial Channel (SIO/UART) Status Flag TMPM333FDFG/FYFG/FWFG To enable FIFO, enable the double buffer by setting SCxMOD2 to "1" and SCxFCNF to "1". The FIFO buffer configuration is specified by SCxMOD1. Note:To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode (half duplex/ full duplex) and enabling FIFO (SCxFCNF = "1"). Table 10-11 shows correlation between modes and FIFO. Table 10-11 Mode and FIFO Composition 10.9 SCxMOD1 RX FIFO TX FIFO Half duplex RX "01" 4byte - Half duplex TX "10" - 4byte Full duplex "11" 2byte 2byte Status Flag The SCxMOD2 register has two types of flag. This bit is significant only when the double buffer is enabled. is a flag to show that the receive buffer is full. When one frame of data is received and the data is moved from the receive shift register to the receive buffers, this bit changes to "1" while reading this bit changes it to "0". shows that the transmit buffers are empty. When data in the transmit buffers is moved to the transmit shift register, this bit is set to "1" When data is set to the transmit buffers, the bit is cleared to "0". 10.10 Error Flag Three error flags are provided in the SCxCR register. The meaning of the flags is changed depending on the modes. The table below shows the meanings in each mode. These flags are cleared to "0" after reading the SCxCR register. Mode UART Flag Overrun error Parity error Framing error Underrun error I/O Interface (SCLK input) Overrun error (When using double buffer or FIFO) Fixed to 0 Fixed to 0 (When a double buffer and FIFO unused) I/O Interface (SCLK output) 10.10.1 Undefined Undefined Fixed to 0 OERR Flag In both UART and I/O interface modes, this bit is set to "1" when an error is generated by completing the reception of the next frame of receive data before the receive buffer has been read. If the receive FIFO is enabled, the received data is automatically moved to the receive FIFO and no overrun error will be generated until the receive FIFO is full (or until the usable bytes are fully occupied). Page 240 TMPM333FDFG/FYFG/FWFG In the I/O interface with SCLK output mode, the SCLK output stops upon setting the flag. Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the overrun flag. 10.10.2 PERR Flag This flag indicates a parity error in the UART mode and an under-run error in the I/O interface mode. In the UART mode, is set to "1" when the parity generated from the received data is different from the parity received. In the I/O interface mode, is set to "1" under the following conditions when a double buffer is enabled. In the SCLK input mode, is set to "1" when the SCLK is input after completing data output of the transmit shift register with no data in the tarnsmit buffer. In the SCLK output mode, is set to "1" after completing output of all data and the SCLK output stops. Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the under-run flag. 10.10.3 FERR Flag A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at around the center. Regardless of the stop bit length settings in the SCxMOD2register, the stop bit status is determined by only 1. This bit is fixed to "0" in the I/O interface mode. Page 241 10. Serial Channel (SIO/UART) 10.11 Receive TMPM333FDFG/FYFG/FWFG 10.11 Receive 10.11.1 Receive Counter The receive counter is a 4-bit binary counter and is up-counted by SIOCLK. In the UART mode, sixteen SIOCLK clock pulses are used in receiving a single data bit and the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three samples, majority logic is applied to decide the received data. 10.11.2 Receive Control Unit 10.11.2.1 I/O interface mode In the SCLK output mode with SCxCR set to "0", the RXD pin is sampled on the rising edge of the shift clock outputted to the SCLK pin. In the SCLK input mode with SCxCR set to "1", the serial receive data RXD pin is sampled on the rising or falling edge of SCLK input signal depending on the SCxCR setting. 10.11.2.2 UART Mode The receive control unit has a start bit detection circuit, which is used to initiate receive operation when a normal start bit is detected. 10.11.3 Receive Operation 10.11.3.1 Receive Buffer The received data is stored by 1 bit in the receive shift register. When a complete set of bits has been stored, the interrupt INTRXx is generated. When the double buffer is enabled, the data is moved to the receive buffer (SCxBUF) and the receive buffer full flag (SCxMOD2) is set to "1". The receive buffer full flag is "0" cleared by reading the receive buffer. Receive shift register Receive buffer DATA 1 DATA 1 Receive interrupt(INTRXx) SCxMOD2 Receive buffer read Figure 10-4 Receive Buffer Operation Page 242 TMPM333FDFG/FYFG/FWFG 10.11.3.2 Receive FIFO Operation When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and the receive buffer full flag is cleared immediately. An interrupt will be generated according to the SCxRFC setting. Note:When the data with parity bit are received in UART mode by using the FIFO, the parity error flag is shown the occurring the parity error in the received data. The following describes configurations and operations in the half duplex RX mode. SCxMOD1[6:5] =01 : Transfer mode is set to half duplex mode SCxFCNF[4:0] = 10111 : Automatically inhibits continuous reception after reaching the fill level. SCxRFC[1:0] = 00 : The fill level of FIFO in which generated receive interrupt is set to 4-byte. SCxRFC[7:6] = 11 : Clears receive FIFO and sets the condition of interrupt generation. : The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill level. After setting of the above FIFO configuration, the data reception is started by writing "1" to the SCxMOD0 . When the data is stored all in the receive shift register, receive buffer and receive FIFO, SCxMOD0 is automatically cleared and the receive operation is finished. In this above condition, if the cotinuous reception after reaching the fill level is enabed, and it is possible to receive a data continuouslywith and reading the data in the FIFO. Receive shift register Receive buffer RX FIFO The first stage The second stage DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA1 DATA2 DATA3 DATA4 DATA5 DATA1 DATA5 DATA2 DATA3 DATA4 DATA4 DATA4 DATA1 DATA2 DATA3 DATA3 DATA3 DATA1 DATA2 DATA2 DATA2 DATA1 DATA1 DATA1 The third stage The fourth stage RX Interrupt (INTRXx) SCxMOD2 SCxMOD0 Figure 10-5 Receive FIFO Operation Page 243 10. Serial Channel (SIO/UART) 10.11 Receive TMPM333FDFG/FYFG/FWFG 10.11.3.3 I/O interface mode with SCLK output In the I/O interface mode and SCLK output setting, SCLK output stops when all received data is stored in the receive buffer and FIFO. So, in this mode, the overrun error flag has no meaning. The timing of SCLK output stop and re-output depends on receive buffer and FIFO. (1) Case of single buffer Stop SCLK output after receiving a data. In this mode, I/O interface can transfer each data with the transfer device by hand-shake. When the data in a buffer is read, SCLK output is restarted. (2) Case of double buffer Stop SCLK output after receiving the data into a receive shift register and a receive buffer. When the data is read, SCLK output is restarted. (3) Case of FIFO Stop SCLK output after receiving the data into a shift register, received buffer and FIFO. When one byte data is read, the data in the received buffer is transferred into FIFO and the data in the receive shift register is transferred into received buffer and SCLK output is restarted. And if SCxFCNFis set to "1", SCLK stops and receive operation stops with clearing SCxMOD0 bit too. 10.11.3.4 Read Received Data In spite of enabling or disabling FIFO, read the received data from the receive buffer (SCxBUF). When receive FIFO is disabled, the buffer full flag SCxMOD2 is cleared to "0" by this reading. In the case of the next data can be received in the receive shift register before reading a data from the receive buffer. The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit UART mode will be stored in SCxCR. When the receive FIFO is available, the 9-bit UART mode is prohibited because up to 8-bit data can be stored in FIFO. In the 8-bit UART mode, the parity bit is lost but parity error is determined and the result is stored in SCxCR. 10.11.3.5 Wake-up Function In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wake-up function SCxMOD0 to "1." In this case, the interrupt INTRXx will be generated only when SCxCR is set to "1." Page 244 TMPM333FDFG/FYFG/FWFG 10.11.3.6 Overrun Error When FIFO is disabled, the overrun errorr is occurred and set overrun flag without completing data read before receiveing the next data. When overrun error is ocurred, a content of receive buffer and SCxCR is not lost, but a content of receive shift register is lost. When FIFO is enabled, overrun error is ocurred and set overrun flag by no reading the data before moving the next data into received buffer when FIFO is full . In this case, the contens of FIFO are not lost. In the I/O interface mode with SCLK output setting, the clock output automatically stops, so this flag has no meaning. Note:When the mode is changed from I/O interface SCLK outout mode to the other mode, read SCxCR and clear overrun flag. Page 245 10. Serial Channel (SIO/UART) 10.12 Transmission 10.12 TMPM333FDFG/FYFG/FWFG Transmission 10.12.1 Transmission Counter The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of the receive counter. In UART mode, it generates a transmit clock (TXDCLK) on every 16th clock pulse. SIOCLK 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK Figure 10-6 Generation of Transmission Clock 10.12.2 Transmission Control 10.12.2.1 I/O Interface Mode In the SCLK output mode with SCxCR set to "0", each bit of data in the transmit buffer is outputted to the TXD pin on the falling edge of the shift clock outputted from the SCLK pin. In the SCLK input mode with SCxCR set to "1", each bit of data in the transmit buffer is outputted to the TXD pin on the rising or falling edge of the SCLK input signal according to the SCxCR setting. 10.12.2.2 UART Mode When the transmit data is written in the transmit buffer, data transmission is initiated on the rising edge of the next TXDCLK and the transmit shift clock signal is also generated. 10.12.3 Transmit Operation 10.12.3.1 Operation of Transmission Buffer If double buffering is disabled, the CPU writes data only to Transmit shift Buffer and the transmit interrupt INTTXx is generated upon completion of data transmission. If double buffering is enabled (including the case the transmit FIFO is enabled), data written to the transmit buffer is moved to the transmit shift register. The INTTXx interrupt is generated at the same time and the transmit buffer empty flag (SCxMOD2) is set to "1". This flag indicates that the next transmit data can be written. When the next data is written to the transmit buffer, the flag is cleared to "0". Page 246 TMPM333FDFG/FYFG/FWFG Write data Transmit buffer DATA 1 DATA 2 DATA 1 Transmit shift register Transmit shift register(INTTXx) SCxMOD2 Figure 10-7 Operation of Transmission Buffer (Double-buffer is enabled) 10.12.3.2 Transmit FIFO Operation When FIFO is enabled, the maximum 5-byte data can be stored using the transmit buffer and FIFO. Once transmission is enabled, data is transferred to the transmit shift register from the transmit buffer and start transmission. If data exists in the FIFO, the data is moved to the transmit buffer immediately, and the flag is cleared to "0". Note:To use TX FIFO buffer, TX FIFO must be cleared after setting the SIO transfer mode (half duplex/ full duplex) and enabling FIFO (SCxFCNF = "1"). Settings and operations to transmit 4-byte data stream by setting the transfer mode to half duplex are shown as below. SCxMOD1[6:5] =10 : Transfer mode is set to half duplex. SCxFCNF[4:0] = 11011 : Transmission is automatically disabled if FIFO becomes empty. The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill level. SCxTFC[1:0] = 00 : Sets the interrupt generation fill level to "0". SCxTFC[7:6] = 11 : Clears receive FIFO and sets the condition of interrupt generation. After above settings are configured, data transmission can be initiated by writing 5 bytes of data to the transmit buffer or FIFO, and setting the SCxMOD1 bit to "1". When the last transmit data is moved to the transmit buffer, the transmit FIFO interrupt is generated. When transmission of the last data is completed, the clock is stopped and the transmission sequence is terminated. Once above settings are configured, if the transmission is not set as auto disabled, the transmission should lasts by writing transmit data. Page 247 10. Serial Channel (SIO/UART) 10.12 Transmission TMPM333FDFG/FYFG/FWFG Transmit FIFO fourth stage DATA 5 Third stage DATA 4 DATA 5 Second stage DATA 3 DATA 4 DATA 5 First stage DATA 2 DATA 3 DATA 4 DATA 5 Transmit buffer DATA 1 DATA 2 DATA 3 DATA 4 Transmit shift register DATA 1 DATA 2 DATA 3 DATA 5 DATA 4 DATA 5 SCxMOD1 SCxMOD2 Transmit interrupt(INTTXx) 10.12.3.3 I/O interface Mode/Transmission by SCLK Output If SCLK is set to generate clock the I/O interface mode, the SCLK output automatically stops when all data transmission is completed and underrun error will not occur. The timing of suspension and resume of SCLK output is different depending on the buffer and FIFO usage. (1) Single Buffer The SCLK output stops each time one frame of data is transferred. Handshaking for each data with the other side of communication can be enabled. The SCLK output resumes when the next data is written in the buffer. (2) Double Buffer The SCLK output stops upon completion of data transmission of the transmit shift register and the transmit buffer. The SCLK output resumes when the next data is written in the buffer. (3) FIFO The transmission of all data stored in the transmit shift register, transmit buffer and FIFO is completed, the SCLK output stops. The next data is written, SCLK output resumes. If SCxFCNF is configured, SCxMOD0 bit is cleared at the same time as SCLK stop and the transmission stops. 10.12.3.4 Under-run error If the transmit FIFO is disabled in the I/O interface SCLK input mode and if no data is set in transmit buffer before the next frame clock input, which occurs upon completion of data transmission from transmit shift register, an under-run error occurs and SCxCR is set to "1". Page 248 TMPM333FDFG/FYFG/FWFG In the I/O interface mode with SCLK output setting, the clock output automatically stops, so this flag has no meaning. Note:Before switching the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the underrun flag. Page 249 10. Serial Channel (SIO/UART) 10.13 Handshake function 10.13 TMPM333FDFG/FYFG/FWFG Handshake function The function of the handshake is to enable frame-by-frame data transmission by using the CTS (Clear to send) pin and to prevent overrun errors. This function can be enabled or disabled by SCxMOD0. When the CTS pin is set to "High" level, the current data transmission can be completed but the next data transmission is suspended until the CTS pin returns to the "Low" level. However in this case, the INTTXx interrupt is generated in the normal timing, the next transmit data is written in the transmit buffer, and it waits until it is ready to transmit data. Note:(1) If the CTS signal is set to "H" during transmission, the next data transmission is suspended after the current transmission is completed. (2) Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to "L". Although no RTS pin is provided, a handshake control function can easily implemented by assigning one bit of the port for the RTS function. By setting the port to "High" level upon completion of data reception (in the receive interrupt routine), the transmit side can be requested to suspend data transmission. TXD RXD CTS RTS (Any port) Receive side Transmit side Figure 10-8 Handshake Function Data write to transmit buffer or shift register CTS Transmission is suspended during b a this period. 13 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TXDCLK Start bit TXD Figure 10-9 CTS Signal timing Page 250 Bit 0 TMPM333FDFG/FYFG/FWFG 10.14 Interrupt/Error Generation Timing 10.14.1 RX Interrupts Figure 10-10 shows the data flow of receive operation and the route of read. 4:& 4GEGKXGUJKHVTGIKUVGT 4GCFKPIKPVJGUKPINGDWHHGTEQPHKIWTCVKQP ‫ޓޓ‬#PKPVGTTWRVKUIGPGTCVGFCHVGTTGEGKXKPICNNDKVU +HVJGTGEGKXGDWHHGTKUGORV[ VJGFCVCKUOQXGF 4GEGKXGDWHHGT 4GCFKPIKPVJGFQWDNGDWHHGTEQPHKIWTCVKQP ‫ޓޓ‬#PKPVGTTWRVKUIGPGTCVGFYJGPVJGFCVCKUOQXGFVQ VJGTGEGKXGDWHHGT +HVJG4:(+(1KUPQVHWNN VJGFCVCKUOQXGF 4:(+(1 6JGHKTUVUVCIG 4GCFKPIKPWUGVJG(+(1 ‫ޓޓ‬#PKPVGTTWRVKUIGPGTCVGF ‫ޓޓޓ‬YJGPVJGFCVCKUOQXGFVQVJG(+(1 ‫ޓޓޓ‬QTYJGPTGCFKPIVJG(+(1 6JGUGEQPFUVCIG 6JGVJKTFUVCIG 6JGHQWTVJUVCIG Figure 10-10 Receive Buffer/FIFO Configuration Diagram 10.14.1.1 Single Buffer / Double Buffer RX interrupts are generated at the time depends on the transfer mode and the buffer configurations, which are given as follows. Buffer UART modes Configurations IO interface modes ・Immediately after the raising / falling edge of the last SCLK Single Buffer − Double Buffer ・Around the center of the first stop bit 　(Rising or falling is determined according to SCxCR setting.) ・Immediately after the raising / falling edge of the last SCLK 　(Rising or falling is determined according to SCxCR setting.) ・On data transfer from the shift register to the buffer by reading buffer. Note:Interrupts are not generated when an overrun error is occurred. 10.14.1.2 FIFO In use of FIFO, receive interrupt is generated on the condition that the following either operation and SCxRFC setting are established. ・ Reception completion of all bits of one frame. ・ Reading FIFO Interrupt conditions are decided by the SCxRFC settings as described in Table 10-12. Table 10-12 Receive Interrupt conditions in use of FIFO SCxRFC Interrupt conditions "0" "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation." "1" "The fill level of FIFO" is greater than or equal to "the fill level of FIFO intrruption generation." Page 251 10. Serial Channel (SIO/UART) 10.14 Interrupt/Error Generation Timing 10.14.2 TMPM333FDFG/FYFG/FWFG TX interrupts Figure 10-11 shows the data flow of transmit operation and the route of read. 6:& 6TCPUOKVUJKHVTGIKUVGT 9TKVKPIKPVJGUKPINGDWHHGTEQPHKIWTCVKQP ‫ޓޓ‬#PKPVGTTWRVKUIGPGTCVGFCHVGTVTCPUOKVVKPICNNDKVU +HVJGUJKHVTGIKUVGTKUGORV[ VJGFCVCKUOQXGF 6TCPUOKVDWHHGT 9TKVKPIKPVJGFQWDNGDWHHGTEQPHKIWTCVKQP ‫ޓޓ‬#PKPVGTTWRVKUIGPGTCVGFYJGPVJGFCVCKUOQXGFVQ VJGVTCPUOKVUJKHVTGIKUVGT +HVJGVTCPUOKVDWHHGTKUGORV[ VJGFCVCKUOQXGF 6:(+(1 6JGHKTUVUVCIG 6JGUGEQPFUVCIG 6JGVJKTFUVCIG 6JGHQWTVJUVCIG 9TKVKPIKPWUGVJG(+(1 ‫ޓޓ‬#PKPVGTTWRVKUIGPGTCVGF ‫ޓޓޓ‬YJGPVJGFCVCKUOQXGFVQVJGVTCPUOKVDWHHGT ‫ޓޓޓ‬QTYJGPYTKVKPIVQVJG(+(1 Figure 10-11 Transmit Buffer/FIFO Configuration Diagram 10.14.2.1 Single Buffer / Double Buffer TX interrupts are generated at the time depends on the transfer mode and the buffer configurations, which are given as follows. Buffer Configurations UART modes IO interface modes Immediately after the raising / falling edge of the last SCLK Single Buffer Just before the stop bit is sent Double Buffer When a data is moved from the transmit buffet to the transmit shift register. (Rising or falling is determined according to SCxCR setting.) Note:If double buffer is enabled, a interrupt is also generated when the data is moved from the buffer to the shift register by writing to the buffer. 10.14.2.2 FIFO In use of FIFO, transmit interrupt is generated on the condition that the fllowing either operation and SCxTFC setting are established. ・ Transmittion completion of all bits of one frame. ・ Writing FIFO Interrupt conditions are decided by the SCxTFC settings as described in Table 10-13. Table 10-13 Transmit Interrupt conditions in use of FIFO SCxTFC Interrupt conditions "0" "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation." "1" "The fill level of FIFO" is smaller than or equal to "the fill level of FIFO intrruption generation." Page 252 TMPM333FDFG/FYFG/FWFG 10.14.3 Error Generation 10.14.3.1 UART Mode 7 bits modes 8 bits 9 bits 7 bits+ Parity 8 bits + Parity Framing Error Around the center of stop bit Overrun Error Parity Error 10.14.3.2 − Around the center of parity bit IO Interface Mode Overrun Error Underrun Error Immediately after the raising / falling edge of the last SCLK (Rising or falling is determined according to SCxCR setting.) Immediately after the rising or falling edge of the next SCLK. (Rising or falling is determined according to SCxCR setting.) Note:Over-run error and Under-run error have no meaning in SCLK output mode. 10.15 Software Reset Software reset is generated by writing SCxMOD2 as "10" followed by "01". As a result, SCxMOD0, SCxMOD1, SCxMOD2, SCxCR are initialized. And the receive circuit, the transmit circuit and the FIFO become initial stete. Other states are maintained. Page 253 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode 10.16 TMPM333FDFG/FYFG/FWFG Operation in Each Mode 10.16.1 Mode 0 (I/O interface mode) Mode 0 consists of two modes, the SCLK output mode to output synchronous clock and the SCLK input mode to accept synchronous clock from an external source. The following operational descriptions are for the case use of FIFO is disabled. For details of FIFO operation, refer to the previous sections describing receive/transmit FIFO functions. 10.16.1.1 Transmitting Data (1) SCLK Output Mode ・ If the transmit double buffer is disabled (SCxMOD2 = "0") Data is output from the TXD pin and the clock is output from the SCLK pin each time the CPU writes data to the transmit buffer. When all data is output, an interrupt (INTTXx) is generated. ・ If the transmit double buffer is enabled (SCxMOD2 = "1") Data is moved from the transmit buffer to the transmit shift register when the CPU writes data to the transmit buffer while data transmission is halted or when data transmission from the transmit buffer (shift register) is completed. Simultaneously, the transmit buffer empty flag SCxMOD2 is set to "1", and the INTTXx interrupt is generated. When data is moved from the transmit buffer to the transmit shift register, if the transmit buffer has no data to be moved to the transmit shift register, INTTXx interrupt is not generated and the SCLK output stops. Page 254 TMPM333FDFG/FYFG/FWFG Transmit data write timing SCLK output bit 0 TXD bit 1 bit 6 bit 7 bit 0 (INTTXx interrupt request) = "0" (if double buffering is disabled) Transmit data write timing SCLK output bit 0 TXD bit 1 bit 6 bit 7 bit 0 (INTTXx interrupt request) TBEMP = "1" (if double buffering is enabled and there is data in buffer) Transmit data write timing SCLK output bit 0 TXD bit 1 bit 6 bit 7 (INTTXx interrupt request) TBEMP = "1" (if double buffering is enabled and threre is no data in buffer) Figure 10-12 Transmit Operation in the I/O Interface Mode (SCLK Output Mode) Page 255 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode (2) TMPM333FDFG/FYFG/FWFG SCLK Input Mode ・ If double buffering is disabled (SCxMOD2 = "0") If the SCLK is input in the condition where data is written in the transmit buffer, 8-bit data is outputted from the TXD pin. When all data is output, an interrupt INTTXx is generated. The next transmit data must be written before the timing point "A" as shown in Figure 10-13. ・ If double buffer is enabled (SCxMOD2 = "1") Data is moved from the transmit buffer to the transmit shift register when the CPU writes data to the transmit buffer before the SCLK input becomes active or when data transmission from the transmit shift register is completed. Simultaneously, the transmit buffer empty flag SCxMOD2 is set to "1", and the INTTXx interrupt is generated. If the SCLK input becomes active while no data is in the transmit buffer, although the internal bit counter is started, an under-run error occurs and 8-bit dummy data (0xFF) is sent. Page 256 TMPM333FDFG/FYFG/FWFG A Transmit data write timing SCLK0 input (=0 Rising edge mode) SCLK0 input (=1 Falling edge mode) TXD0 bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 bit 0 bit 1 (INTTX0 interrupt request) = "0" (if double buffering is disabled) A Transmit data write timing SCLK0 input (=0 Rising edge mode) SCLK0 input (=1 Falling edge mode) TXD0 bit 0 bit 1 bit 5 bit 6 bit 7 (INTTX0 interrupt request) TBEMP = "1" (if double buffering is enabled and there is data in buffer2) A Transmit data write timing SCLK0 input (=0 Rising edge mode) SCLK0 input (=1 Falling edge mode) TXD0 bit 0 bit 1 bit 5 bit 6 bit 7 1 1 (INTTX0 interrupt request) TBEMP PERR (Functions to detect under-run errors) = "1" (if double buffering is enabled and there is no data in buffer2) Figure 10-13 Transmit Operation in the I/O Interface Mode (SCLK Input Mode) Page 257 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode 10.16.1.2 TMPM333FDFG/FYFG/FWFG Receive (1) SCLK Output Mode The SCLK output can be started by setting the receive enable bit SCxMOD0 to "1". ・ If double buffer is disabled (SCxMOD2 = "0") A clock pulse is outputted from the SCLK pin and the next data is stored into the shift register each time the CPU reads received data. When all the 8 bits are received, the INTRXx interrupt is generated. ・ If double buffer is enabled (SCxMOD2 = "1") Data stored in the shift register is moved to the receive buffer and the receive buffer can receive the next frame. A data is moved from the shift register to the receive buffer, the receive buffer full flag SCxMOD2 is set to "1" and the INTRXx is generated. While data is in the receive buffer, if the data cannot be read from the receive buffer before completing reception of the next 8 bits, the INTRXx interrupt is not generated and the SCLK output stops. In this state, reading data from the receive buffer allows data in the shift register to move to the receive buffer and thus the INTRXx interrupt is generated and data reception resumes. Page 258 TMPM333FDFG/FYFG/FWFG 5HFHLYHGDWD UHDGWLPLQJ SCLK output RXD bit 0 bit 1 bit 7 bit 6 bit 0 (INTRX interrupt request) = "0" (if double buffering is disableG 5HFHLYHGDWD UHDGWLPLQJ SCLK output RXD bit 7 bit 0 bit 1 bit 6 bit 7 bit 0 (INTRX interrupt request) RBFLL = "1" (if double buffering is enabled and data is read from buffer) 5HFHLYHGDWD UHDGWLPLQJ SCLK output RXD bit 7 bit 0 bit 1 bit 6 bit 7 (INTRX interrupt request) RBFLL = "1" (if double buffering is enabled and data cannot be read from buffer) Figure 10-14 Receive Operation in the I/O Interface Mode (SCLK Output Mode) Page 259 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode TMPM333FDFG/FYFG/FWFG (2) SCLK Input Mode In the SCLK input mode, receiving double buffering is always enabled, the received frame can be moved to the receive buffer from the shift register, and the receive buffer can receive the next frame successively. The INTRx receive interrupt is generated each time received data is moved to the receive buffer. Receive data read timing SCLK input (=”0” Rising mode) SCLK input (=”1” Falling mode) RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 (INTRXx interrupt request) RBFLL If data is read from buffer Receive data read timing SCLK input (=”0” Rising mode) SCLK input (=”1” Falling mode) RXD bit 0 bit 1 bit 5 (INTRXx interrupt request) RBFLL OERR If data cannot be read from buffer Figure 10-15 Receive Operation in the I/O Interface Mode (SCLK Input Mode) Page 260 TMPM333FDFG/FYFG/FWFG 10.16.1.3 Transmit and Receive (Full-duplex) (1) SCLK Output Mode ・ If SCxMOD2 is set to "0" and the double buffers are disabled SCLK is outputted when the CPU writes data to the transmit buffer. Subsequently, 8 bits of data are shifted into receive buffer and the INTRXx receive interrupt is generated. Concurrently, 8 bits of data written to the transmit buffer are outputted from the TXD pin, the INTTXx transmit interrupt is generated when transmission of all data bits has been completed. Then, the SCLK output stops. The next round of data transmission and reception starts when the data is read from the receive buffer and the next transmit data is written to the transmit buffer by the CPU. The order of reading the receive buffer and writing to the transmit buffer can be freely determined. Data transmission is resumed only when both conditions are satisfied. ・ If SCxMOD2 is set to "1" and the double buffers are enabled SCLK is outputted when the CPU writes data to the transmit buffer. 8 bits of data are shifted into the receive shift register, moved to the receive buffer, and the INTRXx interrupt is generated. While 8 bits of data is received, 8 bits of transmit data is outputted from the TXD pin. When all data bits are sent out, the INTTXx interrupt is generated and the next data is moved from the transmit buffer to the transmit shift register. If the transmit buffer has no data to be moved to the transmit buffer (SCxMOD2 = 1) or when the receive buffer is full (SCxMOD2 = 1), the SCLK output is stopped. When both conditions, receive data is read and transmit data is written, are satisfied, the SCLK output is resumed and the next round of data transmission and reception is started. Page 261 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode TMPM333FDFG/FYFG/FWFG Receive data read timing Transmit data write timing SCLK output TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "0" (if double buffering is disabled) Receive data read timing Transmit data write timing SCLK output TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "1" (if double buffering is enabled) Receive data read timing Transmit data write timing SCLK output TXD bit 0 bit 1 bit 5 bit 6 bit 7 RXD bit 0 bit 1 bit 5 bit 6 bit 7 (INTTXx interrupt request) (INTRXx interrupt request) = "1" (if double buffering is enabled) Figure 10-16 Transmit/Receive Operation in the I/O Interface Mode (SCLK Output Mode) Page 262 TMPM333FDFG/FYFG/FWFG (2) SCLK Input Mode ・ If SCxMOD2 is set to "0" and the transmit double buffer is disabled When receiving data, double buffer is always enabled regardless of the SCxMOD2 settings. 8-bit data written in the transmit buffer is outputted from the TXD pin and 8 bit of data is shifted into the receive buffer when the SCLK input becomes active.The INTTXx interrupt is generated upon completion of data transmission. The INTTRXx interrupt is generated when the data is moved from shift register to receive buffer after completion of data reception. Note that transmit data must be written into the transmit buffer before the SCLK input for the next frame (data must be written before the point A in Figure 10-17). Data must be read before completing reception of the next frame data. ・ If SCxMOD2 is set to "1" and the double buffer is enabled. The interrupt INTRXx is generated at the timing the transmit buffer data is moved to the transmit shift register after completing data transmission from the transmit shift register. At the same time, data received is shifted to the shift register, it is moved to the receive buffer, and the INTRXx interrupt is generated. Note that transmit data must be written into the transmit buffer before the SCLK input for the next frame (data must be written before the point A in Figure 10-17). Data must be read before completing reception of the next frame data. Upon the SCLK input for the next frame, transmission from transmit shift register (in which data has been moved from transmit buffer) is started while receive data is shifted into receive shift register simultaneously. If data in receive buffer has not been read when the last bit of the frame is received, an overrun error occurs. Similarly, if there is no data written to transmit buffer when SCLK for the next frame is input, an under-run error occurs. Page 263 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode TMPM333FDFG/FYFG/FWFG Receive data read timing A Transmit data write timing SCLK input TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "0" (if double buffering is disabled) Receive data read timing A Transmit data write timing SCLK input TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "1" (if double buffering is enabled with no errors) Receive data read timing A Transmit data write timing SCLK input TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) PERR(Under-run errors) = "1" (if double buffering is enabled with error generation) Figure 10-17 Transmit/Receive Operation in the I/O Interface Mode (SCLK Input Mode) Page 264 TMPM333FDFG/FYFG/FWFG 10.16.2 Mode 1 (7-bit UART mode) The 7-bit UART mode can be selected by setting the serial mode control register (SCxMOD) to "01". In this mode, parity bits can be added to the transmit data stream; the serial mode control register (SCxCR) controls the parity enable/disable setting. When is set to "1" (enable), either even or odd parity may be selected using the SCxCR bit. The length of the stop bit can be specified using SCxMOD2. The following table shows the control register settings for transmitting in the following data format. start bit 0 1 2 3 4 5 even parity 6 stop 7UDQVPLVVLRQGLUHFWLRQ(7UDQVPLVVLRQUDWHRIbps @fc = 9.8304 MHz) Clocking conditions SCxMOD0 system clock : High-speed (fc) High-speed clock gear: X1 (fc) Prescaler clock: fperiph/2 (fperiph = fsys) ← 7 6 5 4 3 2 1 0 x 0 - 0 0 1 0 1 Set 7-bit UART mode SCxCR ← x 1 1 x x x 0 0 Even parity enabled SCxBRCR ← 0 0 1 0 0 1 0 0 Set 2400bps SCxBUF ← * * * * * * * * Set transmit data x : don’t care - : no change 10.16.3 Mode 2 (8-bit UART mode) The 8-bit UART mode can be selected by setting SCxMOD0 to "10." In this mode, parity bits can be added and parity enable/disable is controlled using SCxCR. If = "1" (enabled), either even or odd parity can be selected using SCxCR. The control register settings for receiving data in the following format are as follows: start bit 0 1 2 3 4 5 6 7 odd parity Recetion direction (Reception rate of9600 bps @fc = 9.8304 MHz) Clocking conditions System clock: High-speed (fc) High-speed clock gear: X1 Prescaler clock: fperiph/2 (fperiph = fsys) Page 265 stop 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode TMPM333FDFG/FYFG/FWFG SCxMOD0 ← 7 6 5 4 3 2 1 0 x 0 0 0 1 0 0 1 SEt 8-bit UART mode SCxCR ← x 0 1 x x x 0 0 Odd parity enabled SCxBRCR ← 0 0 0 1 0 1 0 0 Set 9600bps SCxMOD0 ← - - 1 - - - - - Reception enabled x : don’t care - : no change 10.16.4 Mode 3 (9-bit UART mode) The 9-bit UART mode can be selected by setting SCxMOD0 to "11." In this mode, parity bits must be disabled (SCxCR = "0"). The most significant bit (9th bit) is written to bit 7 of the serial mode control register 0 (SCxMOD0) for transmitting data. The data is stored in bit 7 of the serial control register SCxCR. When writing or reading data to/from the buffers, the most significant bit must be written or read first before writing or reading to/from SCxBUF. The stop bit length can be specified using SCxMOD2. 10.16.4.1 Wakeup function In the 9-bit UART mode, slave controllers can be operated in the wake-up mode by setting the wake-up function control bit SCxMOD0 to "1." In this case, the interrupt INTRXx will be generated only when SCxCR is set to "1". Note:The TXD pin of the slave controller must be set to the open drain output mode using the ODE register. TXD RXD Master TXD RXD TXD Slave1 RXD Slave2 TXD RXD Slave3 Figure 10-18 Serial Links to Use Wake-up Function Page 266 TMPM333FDFG/FYFG/FWFG 10.16.4.2 Protocol 1. Select the 9-bit UART mode for the master and slave controllers. 2. Set SCxMOD to "1" for the slave controllers to make them ready to receive data. 3. The master controller is to transmit a single frame of data that includes the slave controller select code (8 bits). In this, the most significant bit (bit 8) must be set to "1". start bit 0 1 2 3 4 5 6 7 8 stop "1" Select code of the slave controller 4. Each slave controller receives the above data frame; if the code received matches with the controller's own select code, it clears the WU bit to "0". 5. The master controller transmits data to the designated slave controller (the controller of which SCxMOD bit is cleared to "0"). In this, the most significant bit (bit 8) must be set to "0". start bit 0 1 2 3 4 5 6 7 bit 8 stop "0" Data 6. The slave controllers with the bit set to "1" ignore the receive data because the most significant bit (bit 8) is set to "0" and thus no interrupt (INTRXx) is generated.Also, the slave controller with the bit set to "0" can transmit data to the master controller to inform that the data has been successfully received. Page 267 10. Serial Channel (SIO/UART) 10.16 Operation in Each Mode TMPM333FDFG/FYFG/FWFG Page 268 TMPM333FDFG/FYFG/FWFG 11. Serial Bus Interface (I2C/SIO) The TMPM333FDFG/FYFG/FWFG contains three Serial Bus Interface (I2C/SIO) channels, in which the following two operating modes are included: ・ I2C bus mode (with multi-master capability) ・ Clock-synchronous 8-bit SIO mode In the I2C bus mode, the I2C/SIO is connected to external devices via SCL and SDA. In the clock-synchronous 8-bit SIO mode, the I2C/SIO is connected to external devices via SCK, SI and SO. The following table shows the programming required to put the I2C/SIO in each operating mode. Table 11-1 Port settings for using serial bus interface channel Operating mode pin I2C SCL0 :PG1 bus mode SDA0 :PG0 SBI0 Port Function Register Port Output Control Register Port Input Control Register Port Open Drain Output Control Register PGFR1[1:0] = "11" PGCR[1:0] = "11" PGIE[1:0] = "11" PGOD[1:0] = "11" PGCR[2:0] = "101" (SCK0 output) PGIE[2:0] = "010" (SCK0 output) PGCR[2:0] = "001"(SCK0 input) PGIE[2:0] = "110" (SCK0 input) PFCR[5:4] = "11" PFIE[5:4] = "11" PFCR[6:4] = "101" (SCK1output) PFIE[6:4] = "010" (SCK1 output) PFCR[6:4] = "001" (SCK1 input) PFIE[6:4] = "110" (SCK1 input) PGCR[5:4] = "11" PGIE[5:4] = "11" PGCR[6:4] = "101" (SCK2 output) PGIE[6:4] = "010" (SCK2 output) PGCR[6:4] = "001" (SCK2 input) PGIE[6:4] = "110" (SCK2 input) SCK0 :PG2 SIO mode SI0 :PG1 PGFR1[2:0] = "111" SO0 :PG0 I2C SCL1 :PF5 bus mode SDA1 :PF4 SBI1 PFFR1[5:4] = "11" SCK1 :PF6 SIO mode SI1 :PF5 PFFR1[6:4] = "111" SO1 :PF4 I2C SCL2 :PG5 bus mode SDA2 :PG4 SBI2 PGFR1[5:4] = "11" SCK2 :PG6 SIO mode SI2 :PG5 SO2 :PG4 PGFR1[6:4] = "111" Note:x: Don't care Page 269 PGOD[2:0] = "xxx" PFOD[5:4] = "11" PFOD[6:4] = "xxx" PGOD[5:4] = "11" PGOD[6:4] = "xxx" 11. 11.1 Serial Bus Interface (I2C/SIO) Configuration 11.1 TMPM333FDFG/FYFG/FWFG Configuration The configuration is shown in Figure 11-1. INTSBIx interrupt request SCL SCK SIO clock control fsys Frequency Divider Noise canceller I2C bus clock synchronization + control SBIxCR2/ SBIxSR Control register2/ Status register SCKx Input/ Output control SIO data control Transfer control circuit Shift register SBIxI2CAR I2C bus address register SBIxDBR Data buffer register I2C bus data control SO SI Noise canceller SBIxCR0, 1 SBIxBR0 Control register0, 1 Baud rate register0 Figure 11-1 (I2C/SIO) Block Interface Page 270 SDA SDAx SOx SCLx SIx TMPM333FDFG/FYFG/FWFG 11.2 Register The following registers control the serial bus interface and provide its status information for monitoring. The register below performs different functions depending on the mode. For details, refer to "11.4 Control Registers in the I2C Bus Mode" and "11.7 Control register of SIO mode". 11.2.1 Registers for each channel The tables below show the registers and register addresses for each channel. Channel x Base Address Channel0 0x4002_0000 Channel1 0x4002_0020 Channel2 0x4002_0040 Register name (x=0 to 2) Address(Base+) Control register 0 SBIxCR0 0x0000 Control register 1 SBIxCR1 0x0004 Data buffer register I2C bus address register SBIxDBR 0x0008 SBIxI2CAR 0x000C Control register 2 SBIxCR2 (writing) Status register SBIxSR (reading) Baud rate register 0 SBIxBR0 Page 271 0x0010 0x0014 11. Serial Bus Interface (I2C/SIO) 11.3 I2C Bus Mode Data Format 11.3 TMPM333FDFG/FYFG/FWFG I2C Bus Mode Data Format Figure 11-2 shows the data formats used in the I2C bus mode. (a) Addressing format 8 bit S Slave address 1 RA / C WK 1 to 8 bits 1 1 to 8 bits Data A C K Data Once 1 A CP K Repeated (b) Addressing format (with repeated start condition) 8 bit S Slave address 1 RA / C WK Once 1 to 8 bits 1 A CS K Data Repeated 8 bit Slave address 1 RA / C WK Once S 1 1 to 8 bits 1 1 to 8 bits Data A C K Data A C K Data Once 1 A CP K Repeated Note) S : Start condition R/W : Direction bit ACK : Acknowledge bit P : Stop condition Figure 11-2 I2C Bus Mode Data Formats Page 272 Data Repeated (c) Free data format (master-transmitter to slave-receiver) 8 bit 1 to 8 bits 1 A CP K TMPM333FDFG/FYFG/FWFG 11.4 Control Registers in the I2C Bus Mode The following registers control the serial bus interface in the I2C bus mode and provide its status information for monitoring. 11.4.1 SBIxCR0(Control register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SBIEN - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 SBIEN R/W Serial bus interface operation 0:Disable 1:Enable To use the serial bus interface, enable this bit first. Since all clocks except SBIxCR0 stop if this bit is disabled, power consumption can be reduced by disabling this bit. If this bit is disabled after it’s been enabled once, the settings of each register are retained. 6-0 - R Read as 0. Page 273 11. 11.4 Serial Bus Interface (I2C/SIO) Control Registers in the I2C Bus Mode 11.4.2 TMPM333FDFG/FYFG/FWFG SBIxCR1(Control register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol BC After reset Bit 0 Bit Symbol 0 ACK - SCK2 SCK1 0 1 0 0 0 Type Function 31-8 - R Read as 0. 7-5 BC[2:0] R/W Select the number of bits per transfer (Note 1) When = 0 4 ACK R/W Data When = 1 Data Number of clock cycles length Number of clock cycles length 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 Master mode 0: Acknowledgement clock pulse is not generated. 1: Acknowledgement clock pulse is generated. Slave mode 0: Acknowledgement clock pulse is not counted. 1: Acknowledgement clock pulse is counted. 3 - R Read as 1. 2-1 SCK[2:1] R/W Select internal SCL output clock frequency (Note 2). 0 SCK[0] W 000 n=5 385 kHz 001 n=6 294 kHz 010 n=7 200 kHz 011 n=8 122 kHz 100 n=9 68 kHz 101 n = 10 36 kHz 110 n = 11 19 kHz 111 SWRMON R reserved On reading : Software reset status monitor 0:Software reset operation is in progress. 1:Software reset operation is not in progress. Page 274 System Clock: fsys ( = 40 MHz) Clock gear : fc/1 Frequency = fsys [Hz] 2n + 72 0 SCK0 / SWRMON 1(Note3) TMPM333FDFG/FYFG/FWFG Note 1: Clear to "000" before switching the operation mode to the SIO mode. Note 2: For details on the SCL line clock frequency, refer to "11.5.1 Serial Clock". Note 3: After a reset, the bit is read as "1". However, if the SIO mode is selected at the SBIxCR2 register, the initial value of the bit is "0". Note 4: The initial value for selecting a frequency is =000 and is independent of the read initial value. Page 275 11. 11.4 Serial Bus Interface (I2C/SIO) Control Registers in the I2C Bus Mode 11.4.3 TMPM333FDFG/FYFG/FWFG SBIxCR2(Control register 2) This register serves as SBIxSR register by reading it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol MST TRX BB PIN After reset 0 0 0 1 Bit Bit Symbol Type SBIM 0 0 SWRST 0 0 Function 31-8 - R Read as 0. 7 MST W Select master/slave 0: Slave mode 1: Master mode 6 TRX W Select transmit/ receive 0: Receive 1: Transmit 5 BB W Start/stop condition generation 0: Stop condition generated 1: Start condition generated 4 PIN W Clear INTSBIx interrupt request 0: − 1: Clear interrupt request 3-2 SBIM[1:0] W Select serial bus interface operating mode (Note) 00: Port mode (Disables a serial bus interface output) 01: SIO mode 10: I2C bus mode 11: Reserved 1-0 SWRST[1:0] W Software reset generation Write "10" followed by "01" to generate a reset. Note:Make sure that modes are not changed during a communication session.Ensure that the bus is free before switching the operating mode to the port mode. Ensure that the port is at the "High" level before switching the operating mode from the port mode to the I2C bus or clock-synchronous 8-bit SIO mode. Page 276 0 TMPM333FDFG/FYFG/FWFG 11.4.4 SBIxSR (Status Register) This register serves as SBIxCR2 by writing to it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol MST TRX BB PIN AL AAS ADO LRB After reset 0 0 0 1 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 MST R Master/slave selection monitor 0: Slave mode 1: Master mode 6 TRX R Transmit/receive selection monitor 0: Receive 1: Transmit 5 BB R I2C bus state monitor 0: Free 1: Busy 4 PIN R INTSBIx interrupt request monitor 0:Interrupt request generated 1: Interrupt request cleared 3 AL R Arbitration lost detection 0: − 1:Detected 2 AAS R Slave address match detection 0: − 1: Detected (This bit is set when the general call is detected as well.) 1 ADO R General call detection 0: − 1:Detected 0 LRB R Last received bit monitor 0:Last received bit "0" 1:Last received bit "1" Page 277 11. 11.4 Serial Bus Interface (I2C/SIO) Control Registers in the I2C Bus Mode 11.4.5 TMPM333FDFG/FYFG/FWFG SBIxBR0(Serial bus interface baud rate register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - I2SBI - - - - - - After reset 1 0 1 1 1 1 1 0 24 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 - R Read as 1. 6 I2SBI R/W Operation at the IDLE mode 0: Stop 1: Operate 5-1 - R Read as 1. 0 - R/W Be sure to write "0". 11.4.6 SBIxDBR (Serial bus interface data buffer register) 31 30 29 28 27 26 25 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol DB After reset Bit 0 0 Bit Symbol 0 0 Type Function 31-8 - R Read as 0. 7-0 DB[7:0] R (Receive)/ W (Transmit) Receive data / Transmit data Note 1: The transmission data must be written in to the register from the MSB (bit 7). The received data is stored in the LSB. Note 2: Since SBIxI2CAR has independent buffers for writing and reading, a written data cannot be read. Thus, readmodify-write instructions, such as bit manipulation, cannot be used. Page 278 TMPM333FDFG/FYFG/FWFG 11.4.7 SBIxI2CAR (I2Cbus address register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol SA After reset Bit 0 Bit Symbol 0 0 0 Type 0 ALS 0 0 0 0 Function 31-8 - R Read as 0. 7-1 SA[6:0] R/W Set the slave address when the SBI acts as a slave device. 0 ALS R/W Specify address recognition mode. 0: Recognize its slave address. 1: Do not recognize its slave address (free-data format). Note 1: Please set the bit 0 of I2C bus address register SBIxI2CAR to "0", except when you use a free data format. It operates as a free data format when setting it to "1". Selecting the master fixes to transmission. Selecting the slave fixes to reception. Note 2: Do not set SBIxI2CAR to "0x00" in slave mode. (If SBIxI2CAR is set to "0x00", it’s recognized that the slave address matches the START byte ("0x01") of the I2C standard received in slave mode.) Page 279 11. Serial Bus Interface (I2C/SIO) 11.5 Control in the I2C Bus Mode 11.5 TMPM333FDFG/FYFG/FWFG Control in the I2C Bus Mode 11.5.1 Serial Clock 11.5.1.1 Clock source SBIxCR1 specifies the maximum frequency of the serial clock to be output from the SCL pin in the master mode. tHIGH tLOW 1/fscl tLOW = 2n-1/fsys + 58/fsys tHIGH = 2n-1/fsys + 14/fsys fscl = 1/(tLOW + tHIGH) fsys = n 2 + 72 SBIxCR1 000 001 010 011 100 101 110 n 5 6 7 8 9 10 11 Figure 11-3 Clock source Note:The maximum speeds in the standard and high-speed modes are specified to 100kHz and 400kHz respectively following the communications standards. Notice that the internal SCL clock frequency is determined by the fsys used and the calculation formula shown above. 11.5.1.2 Clock Synchronization The I2C bus is driven by using the wired-AND connection due to its pin structure. The first master that pulls its clock line to the "Low" level overrides other masters producing the "High" level on their clock lines. This must be detected and responded by the masters producing the "High" level. Clock synchronization assures correct data transfer on a bus that has two or more master. For example, the clock synchronization procedure for a bus with two masters is shown below. Wait for “High”level period counting Start “High” level period counting Internal SCL output (Master A) Reset “High”level period counting Internal SCL output (Master B) SCL line a b c Figure 11-4 Example of Clock Synchronization At the point a, Master A pulls its internal SCL output to the "Low" level, bringing the SCL bus line to the "Low" level. Master B detects this transition, resets its "High" level period counter, and pulls its internal SCL output level to the "Low" level. Page 280 TMPM333FDFG/FYFG/FWFG Master A completes counting of its "Low" level period at the point b, and brings its internal SCL output to the "High" level. However, Master B still keeps the SCL bus line at the "Low" level, and Master A stops counting of its "High" level period counting.After Master A detects that Master B brings its internal SCL output to the "High" level and brings the SCL bus line to the "High" level at the point c, it starts counting of its "High" level period. After that Master finishes counting the "High" level period, the Master pulls the SCL pin to "Low" and the SCL bus line becomes "Low". This way, the clock on the bus is determined by the master with the shortest "High" level period and the master with the longest "Low" level period among those connected to the bus. 11.5.2 Setting the Acknowledgement Mode Setting SBIxCR1 to "1" selects the acknowledge mode.When operating as a master, the SBI adds one clock for acknowledgment signal. In slave mode, the clock for acknowledgement signals is counted. In transmitter mode, the SBI releases the SDAx pin during clock cycle to receive acknowledgement signals from the receiver. In receiver mode, the SBI pulls the SDAx pin to the "Low" level during the clock cycle and generates acknowledgement signals. Also in slave mode, if a general-call address is received, the SBI pulls the SDAx pin to the "Low" level during the clock cycle and generates acknowledgement signals. By setting to "0", the non-acknowledgment mode is activated. When operating as a master, the SBI does not generate clock for acknowledgement signals. In slave mode, the clock for acknowledgement signals is counted. 11.5.3 Setting the Number of Bits per Transfer SBIxCR1 specifies the number of bits of the next data to be transmitted or received. Under the start condition, is set to "000", causing a slave address and the direction bit to be transferred in a packet of eight bits. At other times, keeps a previously programmed value. 11.5.4 Slave Addressing and Address Recognition Mode Setting "0" to SBIxI2CAR and a slave address in SBIxI2CAR sets addressing format, and then the SBI recognizes a slave address transmitted by the master device and receives data in the addressing format. If is set to "1", the SBI does not recognize a slave address and receives data in the free data format. In the case of free data format, a slave address and a direction bit are not recognized; they are recognized as data immediately after generation of the start condition. 11.5.5 Operating mode The setting of SBIxCR2 controls the operating mode. To operate in I2C mode, ensure that the serial bus interface pins are at "High" level before setting to "10". Also, ensure that the bus is free before switching the operating mode to the port mode. Page 281 11. Serial Bus Interface (I2C/SIO) 11.5 Control in the I2C Bus Mode 11.5.6 TMPM333FDFG/FYFG/FWFG Configuring the SBI as a Transmitter or a Receiver Setting SBIxCR2 to "1" configures the SBI as a transmitter. Setting to "0" configures the SBI as a receiver. At the slave mode: ・ when data is transmitted in the addressing format. ・ when the received slave address matches the value specified at SBIxI2CAR. ・ when a general-call address is received; i.e., the eight bits following the start condition are all zeros. If the value of the direction bit (R/W) is "1", is set to "1" by the hardware. If the bit is "0", is set to "0". As a master device, the SBI receives acknowledgement from a slave device. If the direction bit of "1" is transmitted, is set to "0" by the hardware. If the direction bit is "0", changes to "1". If the SBI does not receive acknowledgement, retains the previous value. is cleared to "0" by the hardware when it detects the stop condition on the bus or the arbitration lost. If SBI is used in free data format, is not changed by the hardware. 11.5.7 Configuring the SBI as a Master or a Slave Setting SBIxCR2 to "1" configures the SBI to operate as a master device. Setting to "0" configures the SBI as a slave device. is cleared to "0" by the hardware when it detects the stop condition on the bus or the arbitration lost. 11.5.8 Generating Start and Stop Conditions When SBIxSR is "0", writing "1" to SBIxCR2 causes the SBI to start a sequence for generating the start condition and to output the slave address and the direction bit prospectively written in the data buffer register. must be set to "1" in advance. SCLx pin 1 2 3 4 5 6 7 8 SDAx pin A6 A5 A4 A3 A2 A1 A0 R/W Start condition Slave address and direction bit 9 Acknowledgement signal Figure 11-5 Generating the Start Condition and a Slave Address When is "1", writing "1" to and "0" to causes the SBI to start a sequence for generating the stop condition on the bus. The contents of should not be altered until the stop condition appears on the bus. If SCL bus line is pulled "Low" by other devices when the stop condition is generated, the stop condition is generated after the SCL line is released. Page 282 TMPM333FDFG/FYFG/FWFG SCL line SDA line Stop condition Figure 11-6 Generating the Stop Condition SBIxSR can be read to check the bus state. is set to "1" when the start condition is detected on the bus (the bus is busy), and cleared to "0" when the stop condition is detected (the bus is free). 11.5.9 Interrupt Service Request and Release In master mode, a serial bus interface request (INTSBIx) is generated when the transfer of the number of clock cycles set by and is completed. In slave mode, INTSBIx is generated under the following conditions. ・ After output of the acknowledge signal which is generated when the received slave address matches the slave address set to SBIxI2CAR. ・ After the acknowledge signal is generated when a general-call address is received. ・ When the slave address matches or a data transfer is completed after receiving a general-call address. In the address recognition mode ( = "0"), INTSBIx is generated when the received slave address matches the values specified at SBIxI2CAR or when a general-call (eight bits data following the start condition is all "0") is received. When an interrupt request (INTSBIx) is generated, SBIxCR2 is cleared to "0". While is cleared to "0", the SBI pulls the SCL line to the "Low" level. is set to "1" when data is written to or read from SBIxDBR. It takes a period of tLOW for the SCL line to be released after is set to "1". When the program writes "1" to , it is set to "1". However, writing "0" does not clear this bit to "0". Note:When arbitration is lost in master mode, is not cleared to "0" if the slave address does not match (INTSBIx is generated). 11.5.10 Arbitration Lost Detection Monitor The I2C bus has the multi-master capability (there are two or more masters on a bus), and requires the bus arbitration procedure to ensure correct data transfer. A master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no start condition occurring on the SDA and SCL lines.The I2C-bus arbitration takes place on the SDA line. The arbitration procedure for two masters on a bus is shown below. Up until the point a, Master A and Master B output the same data. At the point a, Master A outputs the "Low" level and Master B outputs the "High" level. Page 283 11. Serial Bus Interface (I2C/SIO) 11.5 Control in the I2C Bus Mode TMPM333FDFG/FYFG/FWFG Then Master A pulls the SDA bus line to the "Low" level because the line has the wired-AND connection. When the SCL line goes high at the point b, the slave device reads the SDA line data, i.e., data transmitted by Master A. At this time, data transmitted by Master B becomes invalid. This condition of Master B is called "Arbitration Lost". Master B releases its SDA pin, so that it does not affect the data transfer initiated by another master. If two or more masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. SCL (Line) Internal SDA output (masterA) Loses arbitration and sets the internal SDA output to “1”. Internal SDA output(master B) SDA Line a b Figure 11-7 Lost Arbitration A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line. If there is a difference between these two values, Arbitration Lost occurs and SBIxSR is set to "1". When is set to "1", SBIxSR are cleared to "0", causing the SBI to operate as a slave receiver.Therefore, the serial bus interface circuit stops the clock output during data transfer after is set to "1". is cleared to "0" when data is written to or read from SBIxDBR or data is written to SBIxCR2. Internal SCL output 1 2 3 D7A D6A D5A 4 5 6 7 8 9 1 2 3 4 MasterA Internal SDA output D4A D3A D2A D1A D0A D7A' D6A' D5A' D4A' Clock output dstops here Internal SCL output 1 2 3 4 MasterB InternalSDA output D7B D6B Internal SDA output is fixed to "High"level . due to Arbitration Lost of Master B. Access to SBIxDBR or SBIxCR2 Figure 11-8 Example of Master B Lost Arbitration (D7A = D7B, D6A = D6B) Page 284 TMPM333FDFG/FYFG/FWFG 11.5.11 Slave Address Match Detection Monitor When the SBI operates as a slave device in the address recognition mode (SBIxI2CAR="0"), SBIxSR is set to "1" on receiving the general-call address or the slave address that matches the value specified at SBIxI2CAR. When is "1", is set to "1" when the first data word has been received. is cleared to "0" when data is written to or read from SBIxDBR. 11.5.12 General-call Detection Monitor When the SBI operates as a slave device, SBIxSR is set to "1" when it receives the general-call address; i.e., the eight bits following the start condition are all zeros. is cleared to "0" when the start or stop condition is detected on the bus. 11.5.13 Last Received Bit Monitor SBIxSR is set to the SDA line value that was read at the rising of the SCL line. In the acknowledgment mode, reading SBIxSR immediately after generation of the INTSBIx interrupt request causes ACK signal to be read. 11.5.14 Data Buffer Register (SBIxDBR) Reading or writing SBIxDBR initiates reading received data or writing transmitted data. When the SBI is acting as a master, setting a slave address and a direction bit to this register generates the start condition. 11.5.15 Baud Rate Register (SBIxBR0) The SBIxBR0 register determines if the SBI operates or not when it enters the IDLE mode. This register must be programmed before executing an instruction to switch to the standby mode. 11.5.16 Software Reset If the serial bus interface circuit locks up due to external noise, it can be initialized by using a software reset. Writing "10" followed by "01" to SBIxCR2 generates a reset signal that initializes the serial bus interface circuit. After a reset, all control registers and status flags are initialized to their reset values. When the serial bus interface is initialized, is automatically cleared to "0". Note:A software reset causes the SBI operating mode to switch from the I2C mode to the port mode. Page 285 11. 11.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C 11.6 TMPM333FDFG/FYFG/FWFG Data Transfer Procedure in the I2C Bus ModeI2C 11.6.1 Device Initialization First, program SBIxCR1. Writing "000" to SBIxCR1 at the time. Next, program SBIxI2CAR by specifying a slave address at and an address recognition mode at . ( must be cleared to "0" when using the addressing format). To configure the Serial Bus Interface as a slave receiver, ensure that the serial bus interface pin is at "High" first. Then write "0" to SBIxCR2, "1" to , "10" to and "0" to the bit 1 and 0. Note:Initialization of the serial bus interface circuit must be completed within a period that any device does not generate start condition after all devices connected to the bus were initialized. If this rule is not followed, data may not be received correctly because other devices may start transfer before the initialization of the serial bus interface circuit is completed. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 0 0 X 0 X X X SBIxI2CAR ← X X X X X X X X Specifies a slave address and an address recognition mode. SBIxCR2 ← 0 0 0 1 1 0 0 0 Configures the SBI as a slave receiver. Specifies ACK and SCL clock. Note:X; Don’t care 11.6.2 Generating the Start Condition and a Slave Address 11.6.2.1 Master mode In the master mode, the following steps are required to generate the start condition and a slave address. First, ensure that the bus is free ( = "0"). Then, write "1" to SBIxCR1 to select the acknowledgment mode. Write to SBIxDBR a slave address and a direction bit to be transmitted. When = "0", writing "1111" to SBIxCR2 generates the start condition on the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The SBI outputs the slave address and the direction bit specified at SBIxDBR with the first eight clocks, and releases the SDA line in the ninth clock to receive an acknowledgment signal from the slave device. The INTSBIx interrupt request is generated on the falling of the ninth clock, and is cleared to "0". In the master mode, the SBI holds the SCL line at the "Low" level while is = "0". changes its value according to the transmitted direction bit at generation of the INTSBIx interrupt request, provided that an acknowledgment signal has been returned from the slave device. Note:To output salve address, check with software that the bus is free before writing to SBIxDBR. If this rule is not followed, data being output on the bus may get ruined. Page 286 TMPM333FDFG/FYFG/FWFG Settings in main routine 7 6 5 Reg. ← Reg. ← Reg. e 0x20 if Reg. ≠ 0x00 4 3 2 1 0 SBIxSR Ensures that the bus is free. Then SBIxCR1 ← X X X 1 0 X X X Selects the acknowledgement mode. SBIxDR1 ← X X X X X X X X Specifies the desired slave address and direction. SBIxCR2 ← 1 1 1 1 1 0 0 0 Generates the start condition. Example of INTSBI0 interrupt routine Clears the interrupt request. Processing End of interrupt 11.6.2.2 Slave mode In the slave mode, the SBI receives the start condition and a slave address. After receiving the start condition from the master device, the SBI receives a slave address and a direction bit from the master device during the first eight clocks on the SCL line. If the received address matches its slave address specified at SBIxI2CAR or is equal to the general-call address, the SBI pulls the SDA line to the "Low" level during the ninth clock and outputs an acknowledgment signal. The INTSBIx interrupt request is generated on the falling of the ninth clock, and is cleared to "0". In the slave mode, the SBI holds the SCL line at the "Low" level while is "0". SCLx pin 1 2 3 4 5 6 7 8 9 SDAx pin A6 A5 A4 A3 A2 A1 A0 R/W ACK Start condition Slave address + Direction bit Acknowledgement from slave device INTSBIx Interrupt request Master output Slave output Figure 11-9 Generation of the Start Condition and a Slave Address Page 287 11. 11.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C 11.6.3 TMPM333FDFG/FYFG/FWFG Transferring a Data Word At the end of a data word transfer, the INTSBIx interrupt is generated to test to determine whether the SBI is in the master or slave mode. 11.6.3.1 Master mode ( = "1") Test to determine whether the SBI is configured as a transmitter or a receiver. (1) Transmitter mode ( = "1") Test . If is "1", that means the receiver requires no further data. The master then generates the stop condition as described later to stop transmission. If is "0", that means the receiver requires further data.If the next data to be transmitted has eight bits, the data is written into SBIxDBR. If the data has different length, and are programmed and the transmit data is written into SBIxDBR.Writing the data makes to "1", causing the SCL pin to generate a serial clock for transferring a next data word, and the SDA pin to transfer the data word. After the transfer is completed, the INTSBIx interrupt request is generated, is cleared to "0", and the SCL pin is pulled to the "Low" level. To transmit more data words, test again and repeat the above procedure. INTSBIx interrupt if MST = 0 Then go to the slave-mode processing. if TRX = 0 Then go to the receiver-mode processing. if LRB = 0 Then go to processing for generating the stop condition. SBIxCR1 ← X X X X 0 X X X Specifies the number of bits to be transmitted and specify whether ACK is required. SBIxDBR ← X X X X X X X X Writes the transmit data. End of interrupt processing. Note:X; Don’t care Page 288 TMPM333FDFG/FYFG/FWFG SCLx pin 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Write to SBIxDBR SDAx pin Acknowledgement from receiver INTSBIx interrupt request Master output Slave output Figure 11-10 = "000",= "1" (Transmitter Mode) (2) Receiver mode ( = "0") If the next data to be transmitted has eight bits, the transmit data is written into SBIxDBR. If the data has different length, and are programmed and the received data is read from SBIxDBR to release the SCL line. (The data read immediately after transmission of a slave address is undefined.)On reading the data, is set to "1", and the serial clock is output to the SCL pin to transfer the next data word.In the last bit, when the acknowledgment signal becomes the "Low" level, "0" is output to the SDA pin. After that, the INTSBIx interrupt request is generated, and is cleared to "0", pulling the SCL pin to the "Low" level.Each time the received data is read from SBIxDBR, one-word transfer clock and an acknowledgement signal are output. Read the received data SCLx pin 1 2 3 4 5 6 7 8 9 SDAx pin D7 D6 D5 D4 D3 D2 D1 D0 ACK Next D7 Acknowledgment signal to transmitter INTSBIx interrupt request Master output Slave output Figure 11-11 = "000",= "1" (Receiver Mode) To terminate the data transmission from the transmitter, must be cleared to "0" immediately before reading the data word second to last. This disables generation of an acknowledgment clock for the last data word. When the transfer is completed, an interrupt request is generated. After the interrupt processing, must be set to "001" and the data must be read so that a clock is generated for 1-bit transfer. At this time, the master receiver holds the SDA bus line at the "High" level, which signals the end of transfer to the transmitter as an acknowledgment signal. Page 289 11. 11.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C TMPM333FDFG/FYFG/FWFG In the interrupt processing for terminating the reception of 1-bit data, the stop condition is generated to terminate the data transfer. SCLx pin 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 9 SDAx pin 1 Acknowlegment signal to transmitter “High” INTSBIx interrupt request Read receive data aftwer clear to “0” Read receive data after set to “001”. Master output Slave output Figure 11-12 Terminating Data Transmission in the Master Receiver Mode Example: When receiving N data word INTSBIx interrupt (after data transmission) 7 6 5 4 3 2 1 0 X X X 0 X X X SBIxCR1 ← X Reg. ← SBIxDBR Sets the number of bits of data to be received and specify whether ACK is required. Reads dummy data. End of interrupt INTSBIx interrupt (first to (N-2)th data reception) 7 Reg. ← 6 5 4 3 2 1 0 SBIxDBR Reads the first to (N-2)th data words. End of interrupt INTSBIx interrupt ((N-1)th data reception) 7 6 5 4 3 2 1 0 X X 0 0 X X X SBIxCR1 ← X Reg. ← SBIxDBR Disables generation of acknowledgement clock. Reads the (N-1)th data word. End of interrupt INTSBIx interrupt (Nth data reception) 7 6 5 4 3 2 1 0 0 1 0 0 X X X SBIxCR1 ← 0 Reg. ← SBIxDBR Disables generation of acknowledgement clock. Reads the Nth data word. End of interrupt INTSBIx interrupt (after completing data reception) Processing to generate the stop condition. Terminates the data transmission. End of interrupt Note:X; Don’t care Page 290 TMPM333FDFG/FYFG/FWFG 11.6.3.2 Slave mode ( = "0") In the slave mode, the SBI generates the INTSBIx interrupt request on four occasions: 1) when the SBI has received any slave address from the master. 2) when the SBI has received a general-call address. 3) when the received slave address matches its address. 4) when a data transfer has been completed in response to a general-call. Also, if the SBI detects Arbitration Lost in the master mode, it switches to the slave mode. Upon the completion of data word transfer in which Arbitration Lost is detected, the INTSBIx interrupt request is generated, is cleared to "0", and the SCL pin is pulled to the "Low" level. When data is written to or read from SBIxDBR or when is set to "1", the SCLx pin is released after a period of tLOW. In the slave mode, the normal slave mode processing or the processing as a result of Arbitration Lost is carried out. SBIxSR, , and are tested to determine the processing required. "Table 11-2 Processing in Slave Mode"shows the slave mode states and required processing. Example: When the received slave address matches the SBI's own address and the direction bit is "1" in the slave receiver mode. INTSBIx interrupt if TRX = 0 Then go to other processing. if AL = 0 Then go to other processing. if AAS = 0 Then go to other processing. SBIxCR1 ← X X X 1 0 X X X Sets the number of bits to be transmitted. SBIxDBR ← X X X X 0 X X X Sets the transmit data. Note:X; Don’t care Page 291 11. 11.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C TMPM333FDFG/FYFG/FWFG Table 11-2 Processing in Slave Mode 1 1 1 0 Set the number of bits in a data word to and write the transmit data into SBIxDBR. In the slave receiver mode, the SBI received a slave address with the direction bit "1" transmitted by the master. 0 Test LRB. If it has been set to "1", that means the receiver does not require further data. Set to 1 and reset to 0 to release the bus. If has In the slave transmitter mode, the SBI has completed been reset to "0", that means the receiver requires a transmission of one data word. further data. Set the number of bits in the data word to and write the transmit data to the SBIxDBR. 0 Arbitration Lost is detected while a slave address is being transmitted, and the SBI receives either a slave address with the direction bit "0" or a general-call address transmitted by another master. 1 1/0 0 0 1 1/0 In the slave receiver mode, the SBI received either a slave address with the direction bit "0" or a generalcall address transmitted by the master. 0 1/0 In the slave receiver mode, the SBI has completed a reception of a data word. 1 0 Processing 0 1 0 State Arbitration Lost is detected while the slave address was being transmitted and the SBI received a slave address with the direction bit "1" transmitted by another master. 0 Arbitration Lost is detected while a slave address or a Read the SBIxDBR (a dummy read) to set to data word is being transmitted, and the transfer is ter- 1, or write "1" to . minated. Page 292 Set the number of bits in the data word to and read the received data from SBIxDBR. TMPM333FDFG/FYFG/FWFG 11.6.4 Generating the Stop Condition When SBIxSR is "1", writing "1" to SBIxCR2 and "0" to causes the SBI to start a sequence for generating the stop condition on the bus. Do not alter the contents of until the stop condition appears on the bus. If another device is holding down the SCL bus line, the SBI waits until the SCL line is released. After that, the SDA pin goes "High", causing the stop condition to be generated. SBIxCR2 ← 7 6 5 4 3 2 1 0 1 1 0 1 1 0 0 0 Generates the stop condition. "1"→ "1"→ "0"→ "1"→ Stop condition SCLx pin SDAx pin (Read) Figure 11-13 Generating the Stop Condition 11.6.5 Restart Procedure Restart is used when a master device changes the data transfer direction without terminating the transfer to a slave device.The procedure of generating a restart in the master mode is described below. First, write SBIxCR2 to "0" and write "1" to to release the bus. At this time, the SDAx pin is held at the "High" level and the SCLx pin is released. Because no stop condition is generated on the bus, other devices recognize that the bus is busy. Then, test SBIxSR and wait until it becomes "0" to ensure that the SCLx pin is released. Next, test and wait until it becomes "1" to ensure that no other device is pulling the SCLx bus line to the "Low" level. Once the bus is determined to be free by following the above procedures, follow the procedures described in "11.6.2 Generating the Start Condition and a Slave Address"to generate the start condition. To satisfy the setup time of restart, at least 4.7μs wait period (in the standard mode) must be created by the software after the bus is determined to be free. Note 1: Do not write to "0" when it is "0". (Restart cannot be initiated.) Note 2: When the master device is acting as a receiver, data transmission from the slave device which serves as a transmitter must be completed before generating a restart. To complete data transfer, slave device must receive a "High" level acknowledge signal. For this reason, before generating a Page 293 11. 11.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C TMPM333FDFG/FYFG/FWFG restart becomes "1", the rising edge of the SCL line is not detected even = "1" is confirmed by following the restart procedure. To check the status of the SCL line, read the port. SBIxCR2 ← 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 Releases the bus. if SBIxSR ≠ 0 Checks that the SCL pin is released. Then if SBIxSR ≠ 1 Checks that no other device is pulling the SCL pin to the "Low". Then 4.7 μs Wait SBIxCR1 ← X X X 1 0 X X X Selects the acknowledgment mode. SBIxDBR ← X X X X X X X X Sets the desired slave address and direction. SBIxCR2 ← 1 1 1 1 1 0 0 0 Generates the start condition. Note:X; Don’t care "0"→ "0"→ "0"→ "1"→ "1"→ "1"→ "1"→ "1"→ 4.7 ms (min.) Start condition SCL(Bus) SCL pin 9 SDA pin Figure 11-14 Timing Chart of Generating a Restart Page 294 TMPM333FDFG/FYFG/FWFG 11.7 Control register of SIO mode The following registers control the serial bus interface in the clock-synchronous 8-bit SIO mode and provide its status information for monitoring. 11.7.1 SBIxCR0(control register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 16 23 22 21 20 19 18 17 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SBIEN - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 SBIEN R/W Serial bus interface operation. 0:Disable 1: Enable Enable this bit before using the serial bus interface. If this bit is disabled, power consumption can be reduced because all clocks except SBIxCR0 stop. If the serial bus interface operation is enabled and then disabled, the settings will be maintained in each register. 6-0 - R Read as 0. Page 295 11. 11.7 Serial Bus Interface (I2C/SIO) Control register of SIO mode 11.7.2 TMPM333FDFG/FYFG/FWFG SBIxCR1(Control register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SIOS SIOINH After reset 0 0 Bit Bit Symbol SIOM - 0 0 SCK 1 Type 0 0 0(Note 1) Function 31-8 - R Read as 0. 7 SIOS R/W Transfer Start/Stop 0: Stop 1: Start 6 SIOINH R/W Transfer 0: Continue 1: Forced termination 5-4 SIOM[1:0] R/W Select transfer mode 00: Transmit mode 01: Reserved 10:Transmit/receive mode 11:Receive mode 3 - R Read as 1. 2-0 SCK[2:0] R/W On writing : Select serial clock frequency. (Note 1) 000 n=3 2.5 MHz 001 n=4 1.25 MHz 010 n=5 625 kHz 011 n=6 313 kHz System clock: fsys ( = 40 MHz) 100 n=7 156 kHz Clock gear: fc/1 101 n=8 78 kHz Frequency = 110 n=9 39 kHz 111 − fsys/2 2n [Hz] External clock Note 1: After a reset, the bit is read as "1". However, if the SIO mode is selected at the SBIxCR2 register, the initial value is read as "0". In this document, the value written in the column "after reset" is the value after setting the SIO mode in the initial state. The descriptions of the SBIxCR2 register and the SBIxSR register are the same. Note 2: Set to "0" and to "1" before programming the transfer mode and the serial clock. Page 296 TMPM333FDFG/FYFG/FWFG 11.7.3 SBIxDBR (Data buffer register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol DB After reset Bit 0 0 Bit Symbol 0 0 Type Function 31-8 - R Read as 0. 7-0 DB[7:0] R Receive data W Transmit data Note 1: The transmission data must be written in to the register from the MSB (bit 7). The received data is stored in the LSB. Note 2: Since SBIxI2CAR has independent buffers for writing and reading, a written data cannot be read. Thus, readmodify-write instructions, such as bit manipulation, cannot be used. Page 297 11. 11.7 Serial Bus Interface (I2C/SIO) Control register of SIO mode 11.7.4 TMPM333FDFG/FYFG/FWFG SBIxCR2(Control register 2) This register serves as SBIxSR register by writing to it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 3 2 1 0 7 6 5 4 bit symbol - - - - After reset 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) Bit Bit Symbol Type SBIM 0 0 - - 1(Note 1) 1(Note 1) Function 31-8 - R Read as "0". 7-4 - R Read as 1. (Note 1) 3-2 SBIM[1:0] W Select serial bus interface operating mode (Note 2) 00: Port mode 01: SIO mode 10: I2Cbus mode 11: Reserved 1-0 - R Read as 1. (Note 1) Note 1: In this document, the value written in the column "after reset" is the value after setting the SIO mode in the initial state. Note 2: Make sure that modes are not changed during a communication session. Page 298 TMPM333FDFG/FYFG/FWFG 11.7.5 SBIxSR (Status Register) This register serves as SBIxCR2 by writing to it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - SIOF SEF - - After reset 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) 0 0 1(Note 1) 1(Note 1) Bit Bit Symbol Type Function 31-8 - R Read as 0. 7-4 - R Read as 1.(Note 1) 3 SIOF R Serial transfer status monitor. 0: Completed 1: In progress 2 SEF R Shift operation status monitor 0: Completed. 1: In progress 1-0 - R Read as 1. (Note 1) Note:In this document, the value written in the column "after reset" is the value after setting the SIO mode in the initial state. Page 299 11. 11.7 Serial Bus Interface (I2C/SIO) Control register of SIO mode 11.7.6 TMPM333FDFG/FYFG/FWFG SBIxBR0 (Baud rate register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - I2SBI - - - - - - After reset 1 0 1 1 1 1 1 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 - R Read as 1. 6 I2SBI R/W Operation in IDLE mode. 0: Stop 1: Operate 5-1 - R Read as 1. 0 - R/W Make sure to write "0". Page 300 TMPM333FDFG/FYFG/FWFG 11.8 Control in SIO mode 11.8.1 Serial Clock 11.8.1.1 Clock source Internal or external clocks can be selected by programming SBIxCR1. (1) Internal clocks In the internal clock mode, one of the seven frequencies can be selected as a serial clock, which is output to the outside through the SCKx pin. At the beginning of a transfer, the SCKx pin output becomes the "High" level. If the program cannot keep up with this serial clock rate in writing the transmit data or reading the received data, the SBI automatically enters a wait period. During this period, the serial clock is stopped automatically and the next shift operation is suspended until the processing is completed. $XWRPDWLFZDLW SCKx pin output 1 SOx pin output a0 :ULWHWKH WUDQVPLWGDWD 2 3 7 8 a 1 a2 a 5 a6 a7 a 1 2 6 7 b 0 b 1 b 4 b 5 b6 b 8 1 b7 c0 2 3 c1 c2 c Figure 11-15 Automatic Wait (2) External clock ( = "111") The SBI uses an external clock supplied from the outside to the SCKx pin as a serial clock. For proper shift operations, the serial clock at the "High" and "Low" levels must have the pulse widths as shown below. SCKx┵ሶ fSCKL fSCKH fSCKL, fSCKH > 4/fsys Figure 11-16 Maximum Transfer Frequency of External Clock Input Page 301 11. 11.8 Serial Bus Interface (I2C/SIO) Control in SIO mode 11.8.1.2 TMPM333FDFG/FYFG/FWFG Shift Edge Leading-edge shift is used in transmission. Trailing-edge shift is used in reception. - Leading-edge shift Data is shifted at the leading edge of the serial clock (or the falling edge of the SCKx pin input/ output). - Trailing-edge shift Data is shifted at the trailing edge of the serial clock (or the rising edge of the SCKx pin input/ output). SCKx pin bit 0 SOx pin Shift register bit 1 bit 2 bit 3 bit 4 76543210 *7654321 **765432 ***76543 ****7654 bit 5 bit 6 bit 7 *****765 ******76 *******7 bit 5 bit 6 bit 7 (a) Leading-edge SCKx pin bit 0 SIx pin Shift register ******** bit 1 0******* bit 2 10****** bit 3 210***** bit 4 3210**** 43210*** 543210** 6543210* 76543210 (b) Trailing-edge Figure 11-17 Shift Edge Page 302 TMPM333FDFG/FYFG/FWFG 11.8.2 Transfer Modes The transmit mode, the receive mode or the transmit/receive mode can be selected by programming SBIxCR1. 11.8.2.1 8-bit transmit mode Set the control register to the transmit mode and write the transmit data to SBIxDBR. After writing the transmit data, writing "1" to SBIxCR1 starts the transmission. The transmit data is moved from SBIxDBR to a shift register and output to the SO pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the transmit data is transferred to the shift register, SBIxDBR becomes empty, and the INTSBIx (buffer-empty) interrupt is generated, requesting the next transmit data. In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if next data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared when SBIxDBR is loaded with the next transmit data. In the external clock mode, SBIxDBR must be loaded with data before the next data shift operation is started. Therefore, the data transfer rate varies depending on the maximum latency between when the interrupt request is generated and when SBIxDBR is loaded with data in the interrupt service program. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting SBIxSR to "1" to the falling edge of SCK. Transmission can be terminated by clearing to "0" or setting to "1" in the INTSBIx interrupt service program. If is cleared, remaining data is output before transmission ends. The program checks SBIxSR to determine whether transmission has come to an end. is cleared to "0" at the end of transmission. If is set to "1", the transmission is aborted immediately and is cleared to "0". When in the external clock mode, must be cleared to "0" before next data shifting. If does not be cleared to "0" before next data shifting, SBI output dummy data and stopped. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 0 0 0 X X X Selects the transmit mode. SBIxDBR ← X X X X X X X X Writes the transmit data. SBIxCR1 ← 1 0 0 0 0 X X X Starts transmission. X X X X X X X Writes the transmit data. INTSBIx interrupt SBIxDBR ← X Page 303 11. 11.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM333FDFG/FYFG/FWFG is cleared SCKx pin(RXWSXW) a0 * SOx pin a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 b6 b7 INTSBIx LQWHUUXSWUHTXHVW a SBIxDBR b (a) Internal clock :ULWHWKHWUDQVPLWGDWD is cleared. SCKx pin(input) SOx pin a0 * a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 INTSBIx LQWHUQDOUHTXHVW a SBIxDBR b (b)External clock :ULWHWKHWUDQVPLWGDWD Figure 11-18 Transmit Mode Example: Example of programming (external clock) to terminate transmission by 7 6 5 4 3 2 1 0 if SBIxSR ≠ 0 Recognizes the completion of the transmission. Then if SCK ≠ 1 Recognizes "1" is set to the SCK pin by monitoring the port. Then SBIxCR1 ← 0 0 0 0 0 1 1 1 Page 304 Completes the transmission by setting = 0. TMPM333FDFG/FYFG/FWFG 11.8.2.2 8-bit receive mode Set the control register to the receive mode. Then writing "1" to SBIxCR1 enables reception.Data is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the shift register is loaded with the 8-bit data, it transfers the received data to SBIxDBR and the INTSBIx (buffer-full) interrupt request is generated to request reading the received data. The interrupt service program then reads the received data from SBIxDBR. In the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the received data is read from SBIxDBR. In the external clock mode, shift operations are executed in synchronization with the external clock. The maximum data transfer rate varies, depending on the maximum latency between generating the interrupt request and reading the received data Reception can be terminated by clearing to "0" or setting to "1" in the INTSBIx interrupt service program. If is cleared, reception continues until all the bits of received data are written to SBIxDBR. The program checks SBIxSR to determine whether reception has come to an end. is cleared to "0" at the end of reception. After confirming the completion of the reception, last received data is read. If is set to "1", the reception is aborted immediately and is cleared to "0". (The received data becomes invalid, and there is no need to read it out.) Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 1 1 0 X X X Selects the receive mode. SBIxCR1 ← 1 0 1 1 0 X X X Starts reception. INTSBIx interrupt Reg. ← SBIxDBR Reads the received data. Clear SCKx pin(Output) SIx pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSBIx interrupt request a b Read receive data Read receive data SBIxDBR Figure 11-19 Receive Mode (Example: Internal Clock) Page 305 11. 11.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM333FDFG/FYFG/FWFG 11.8.2.3 8-bit transmit/receive mode Set the control register to the transfer/receive mode. Then writing the transmit data to SBIxDBR and setting SBIxCR1 to "1" enables transmission and reception.The transmit data is output through the SOx pin at the falling of the serial clock, and the received data is taken in through the SI pin at the rising of the serial clock, with the least-significant bit (LSB) first. Once the shift register is loaded with the 8-bit data, it transfers the received data to SBIxDBR and the INTSBIx interrupt request is generated.The interrupt service program reads the received data from the data buffer register and writes the next transmit data. Because SBIxDBR is shared between transmit and receive operations, the received data must be read before the next transmit data is written. In the internal clock operation, the serial clock will be automatically in the wait state until the received data is read and the next transmit data is written. In the external clock mode, shift operations are executed in synchronization with the external serial clock. Therefore, the received data must be read and the next transmit data must be written before the next shift operation is started.The maximum data transfer rate for the external clock operation varies depending on the maximum latency between when the interrupt request is generated and when the transmit data is written. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting to "1" to the falling edge of SCK. Transmission and reception can be terminated by clearing to "0" or setting SBIxCR1 to "1" in the INTSBIx interrupt service program. If is cleared, transmission and reception continue until the received data is fully transferred to SBIxDBR. The program checks SBIxSR to determine whether transmission and reception have come to an end. is cleared to "0" at the end of transmission and reception.If is set to "1", the transmission and reception is aborted immediately and is cleared to "0". Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing transmission and reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. is cleard. SCKx pin (output) SOx pin * SIx pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 INTSBIx interrupt request SBIxDBR c a Write the transmitted data(a) Read the received data(c) b Write the transmitted data(b) Figure 11-20 Transmit/Receive Mode (Example: Internal Clock) Page 306 d Read the received data(d) TMPM333FDFG/FYFG/FWFG 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 1 0 0 X X X Selects the transmit mode. SBIxDBR ← X X X X X X X X Writes the transmit data. SBIxCR1 ← 1 0 1 0 0 X X X Starts reception/transmission. X X X X X X INTSBIx interrupt Reg. ← SBIxDBR SBIxDBR ← X 11.8.2.4 X Reads the received data. Writes the transmit data. Data retention time of the last bit at the end of transmission Under the condition SBIxCR1= "0", the last bit of the transmitted data retains the data of SCK rising edge as shown below. Transmit mode and transmit/receive mode are the same. SCKx pin SOx pin bit 6 Bit 7 of end of transmitted word tSODH = Min. 4/fsys [s] Figure 11-21 Data retention time of the last bit at the end of transmission Page 307 11. 11.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM333FDFG/FYFG/FWFG Page 308 TMPM333FDFG/FYFG/FWFG 12. Analog/Digital Converter (ADC) 12.1 Outline A 10-bit, sequential-conversion analog/digital converter (AD converter) is built into the TMPM333FDFG/FYFG/ FWFG. This AD converter is equipped with 12 analog input channels. These 12 analog input channels (pins AIN0 through AIN11) are also used as input/output ports. Note 1: To assure conversion accuracy, the specified value must be set to the ADCBAS register. Note 2: If it is necessary to reduce a power current by operating the TMPM333FDFG/FYFG/FWFG in IDLE or STOP mode and if either case shown below is applicable, you must first stop the AD converter and then execute the instruction to put the TMPM333FDFG/FYFG/FWFG into standby mode. 1. The TMPM333FDFG/FYFG/FWFG must be put into IDLE mode when ADMOD1 is "0". 2.The TMPM333FDFG/FYFG/FWFG must be put into STOP mode. Page 309 Page 310 VREFL (AVSS) fc Channel select control circuit End ADMOD0 Busy ADCLK DA Converter Comparator   Normal AD conversion control circuit ADSCN ADS Sample hold ADMOD1 1/1 1/2 1/4 1/8 1/16 VREF Multiplexer VREFH AIN11 AIN0 ADTRG ADCLK ADMOD2 Internal data bus Scan Repeat INTAD INTADHP INTADM0, 1 TBxRG0 Configuration Figure 12-1 AD Converter Block Diagram Internal data bud AD conversion result register ADCMP0,1 AD conversion result register ADREGSP AD conversion result register ADREG08-7F AD monitor function interrupt AD monitor function control ADMOD3, 5 Start High priority AD conversion end interrupt AD conversion end interrupt High priority AD conversion control Interrupt Interval AD start control HPADCE ADMOD4 12.2 End 12.2 Busy 12. Analog/Digital Converter (ADC) TMPM333FDFG/FYFG/FWFG Configuration Figure 12-1 shows the block diagram of this AD converter. High priority AD conversion completion interrupt TMPM333FDFG/FYFG/FWFG 12.3 Registers 12.3.1 Register list The control registers and addresses of the AD converter are as follows. The AD converter is controlled by the AD mode control registers (ADMOD0 through ADMOD5). The result of AD conversion is stored in the eight AD conversion result registers, ADREG08 through ADREG7F. The highest-priority conversion result is stored in the register ADREGSP. To assure conversion accuracy, the specified value must be set to the ADCBAS register. Base Address = 0x4003_0000 Register name Address (Base+) Conversion Clock Setting Register ADCLK 0x0000 Mode Control Register 0 ADMOD0 0x0004 Mode Control Register 1 ADMOD1 0x0008 Mode Control Register 2 ADMOD2 0x000C Mode Control Register 3 ADMOD3 0x0010 Mode Control Register 4 ADMOD4 0x0014 Mode Control Register 5 ADMOD5 0x0018 Conversion Accuracy Setting Register ADCBAS 0x0020 Reserved - 0x0024 Reserved - 0x0028 Conversion Result Register 08 ADREG08 0x0030 Conversion Result Register 19 ADREG19 0x0034 Conversion Result Register 2A ADREG2A 0x0038 Conversion Result Register 3B ADREG3B 0x003C Conversion Result Register 4C ADREG4C 0x0040 Conversion Result Register 5D ADREG5D 0x0044 Conversion Result Register 6E ADREG6E 0x0048 Conversion Result Register 7F ADREG7F 0x004C Conversion Result Register SP ADREGSP 0x0050 Conversion Result Comparison Register 0 ADCMP0 0x0054 Conversion Result Comparison Register 1 ADCMP1 0x0058 Note:Access to the "Reserved" address is prohibited. Page 311 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.2 ADCBAS (Conversion Accuracy Setting Register) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 1 0 0 0 Bit symbol After reset Bit ADCBAS 0 Bit Symbol 0 1 1 Type Function 31-8 − R Read as 0. 7-0 ADCBAS[7:0] R/W Write "0x58". Note:To assure conversion accuracy, the specified value (0x0000_0058) must be set to the ADCBAS register. Page 312 TMPM333FDFG/FYFG/FWFG 12.3.3 ADCLK (Conversion Clock Setting Register) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Bit symbol TSH After reset Bit 1 Bit Symbol 0 0 0 ADCLK 0 Type 0 0 0 Function 31-8 − R Read as 0. 7-4 TSH[3:0] R/W Select the AD sample hold time. 1000: 8 conversion clock 1001: 16 conversion clock 1010: 24 conversion clock 1011: 32 conversion clock 0011: 64 conversion clock 1100: 128 conversion clock 1101: 512 conversion clock The setup other than those above: Reserved 3 − R Read as 0. 2-0 ADCLK[2:0] R/W Select the AD conversion clock. 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 111: Reserved A clock count required for conversion is 46 clocks at the minimum. Examples of sample hold time and conversion time as shown as below. (Example: If fc = 40MHz) Conversion time( setting) Sample hold time 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 1000 (8 conversion clock) 0.2 μs 1.15 μs 2.3 μs 4.6 μs 9.2μs 18.4μs 1001 (16 conversion clock) 0.4 μs 1.35 μs 2.7μs 5.4μs 10.8μs 21.6μs 1010 (24 conversion clock) 0.6 μs 1.55 μs 3.1μs 6.2μs 12.4μs 24.8μs 1011 (32 conversion clock) 0.8 μs 1.75 μs 3.5μs 7.0μs 14.0μs 28.0μs 0011 (64 conversion clock) 1.6 μs 2.55 μs 5.1μs 10.2μs 20.4μs 40.8μs 1100 (128 conversion clock) 3.2 μs 4.15 μs 8.3μs 16.6μs 33.2μs 66.4μs 1101 (512 conversion clock) 12.8 μs 13.75 μs 27.5μs 55.0μs 110.0μs 220.0μs Note:Do not change the setting of the AD conversion clock during AD conversion. Page 313 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.4 ADMOD0 (Mode Control Register 0) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 Bit symbol EOCFN ADBFN - After reset 0 0 0 Bit Bit Symbol 3 ITM 0 0 Type 2 1 0 REPEAT SCAN ADS 0 0 0 Function 31-8 − R Read as 0. 7 EOCFN R Normal AD conversion completion flag (note1) 0: Before or during conversion 1: Completion 6 ADBFN R Normal AD conversion BUSY flag 0: Conversion stop 1: During conversion 5 − R Read as 0. 4-3 ITM[1:0] R/W Specify interrupt in fixed channel repeat conversion mode (refer to the table below and note 2) 2 REPEAT R/W Specify repeat mode 0: Single conversion mode 1: Repeat conversion mode 1 SCAN R/W Specify scan mode 0: Fixed channel mode 1: Channel scan mode 0 ADS R/W Start AD conversion start (note 3) 0: Don't care 1: Start conversion "0" is always read. Specify AD conversion interrupt in fixed channel repeat conversion mode Fixed channel repeat conversion mode = "0", = "1" 00 Generate in interrupt once every single conversion. 01 Generate interrupt once every 4 conversions. 10 Generate interrupt once every 8 conversions. 11 Setting prohibited. Note 1: This flag is "0" cleared by reading the ADMOD0 register. Note 2: It is valid only when it’s specified in the fixed channel repeat mode ( ="1", = "0") Note 3: Conversion must be started after setting the mode. Page 314 TMPM333FDFG/FYFG/FWFG 12.3.5 ADMOD1 (Mode Control Register 1) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Bit symbol VREFON I2AD ADSCN - After reset 0 0 0 0 0 0 Bit Bit Symbol Type ADCH 0 0 Function 31-8 − R Read as 0. 7 VREFON R/W VREF application control(Note1 and Note2) 0: OFF 1: ON 6 I2AD R/W Specify operation mode in IDLE mode 0: Stop 1: Operation 5 ADSCN R/W Specify operation mode in channel scan mode 0: 4-channel scan 1: 8-channel scan 4 − R/W Write "0". 3-0 ADCH[3:0] R/W Select analog input channel (Refer to the below table.) Select Analog Input Channel ADMOD0 0 1 1 Fixed channel Channel scan Channel scan ( = 0) ( = 1) ADMOD1 0000 AIN0 AIN0 AIN0 0001 AIN1 AIN0 to AIN1 AIN0 to AIN1 0010 AIN2 AIN0 to AIN2 AIN0 to AIN2 0011 AIN3 AIN0 to AIN3 AIN0 to AIN3 0100 AIN4 AIN4 AIN0 to AIN4 0101 AIN5 AIN4 to AIN5 AIN0 to AIN5 0110 AIN6 AIN4 to AIN6 AIN0 to AIN6 0111 AIN7 AIN4 to AIN7 AIN0 to AIN7 1000 AIN8 AIN8 AIN8 1001 AIN9 AIN8 to AIN9 AIN8 to AIN9 1010 AIN10 AIN8 to AIN10 AIN8 to AIN10 1011 AIN11 AIN8 to AIN11 AIN8 to AIN11 1100 1101 1110 1111 Page 315 Setting prohibited 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG Note 1: Before starting AD conversion, write "1" to the bit, wait for 3μs during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0. Note 2: Set to "0" to go into standby mode upon completion of AD conversion. Page 316 TMPM333FDFG/FYFG/FWFG 12.3.6 ADMOD2 (Mode Control Register 2) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Bit symbol EOCFHP ADBFHP HPADCE - After reset 0 0 0 0 0 0 Bit Bit Symbol Type HPADCH 0 0 Function 31-8 − R Read as 0. 7 EOCFHP R Top-priority AD conversion completion flag (Note1) 0: Before or during conversion 1: Completion 6 ADBFHP R Top-priority AD conversion BUSY flag 0: During conversion halts 1: During conversion 5 HPADCE R/W Activate top-priority conversion 0: Don't care 1: Start conversion "0" is always read. 4 − R/W Write "0". 3-0 HPADCH[3:0] R/W Select analog input channel when activating top-priority conversion. (See the table below) Analog input channel whene xecuting top-priority conversion 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 AIN8 1001 AIN9 1010 AIN10 1011 AIN11 1100 1101 1110 1111 Page 317 Setting prohibited 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG Note 1: This flag is "0" cleared by reading the ADMOD2 register. Page 318 TMPM333FDFG/FYFG/FWFG 12.3.7 ADMOD4 (Mode Control Register 4) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 Bit symbol HADHS HADHTG ADHS ADHTG - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 ADRST 0 0 Function 31-8 − R Read as 0. 7 HADHS R/W H/W source for activating top-priority AD conversion 0: External trigger 1: Match with timer register 0 (TB5RG0) 6 HADHTG R/W H/W for activating top-priority AD conversion 0: Disable 1: Enable 5 ADHS R/W H/W source for activating normal AD conversion (note1) 0: External trigger 1: Match with timer register 0 (TB6RG0) 4 ADHTG R/W HW for activating normal AD conversion 0: Disable 1: Enable 3-2 − R Read as 0. 1-0 ADRST[1:0] W Overwriting 10 with 01 allows ADC to be software reset.(note 2) Note 1: The external trigger cannot be used for H/W activation of AD conversion when it is used for H/W activation of top priority AD conversion. Note 2: A software reset initializes all the registers except for ADCLK. Note:The TX03 disables the external trigger used for H/W activation. Therefore "0" cannot be set to and . Page 319 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.8 ADMOD3 (Mode Control Register 3) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 4 3 2 1 7 6 5 Bit symbol - - ADOBIC0 After reset 0 0 0 Bit Bit Symbol ADREGS0 0 Type 0 0 ADOBSV0 0 0 0 Function 31-8 − R Read as 0. 7 − R/W Write "0". 6 − R Read as 0. 5 ADOBIC0 R/W Set the AD monitor function interrupt 0 0: If the value of the conversion result is smaller than the comparison register 0, an interrupt is generated. 1: If the value of the conversion result is bigger than the comparison register 0, an interrupt is generated. 4-1 ADREGS0[3:0] R/W Select a target conversion result register when using the AD monitor function 0 (See the below table). 0 ADOBSV0 R/W AD monitor function 0 0: Disable 1: Enable Conversion result register to be compared Conversion result register to be compared 0000 ADREG08 0100 ADREG4C 0001 ADREG19 0101 ADREG5D 0010 ADREG2A 0110 ADREG6E 0011 ADREG3B 0111 ADREG7F - - 1xxx ADREGSP Page 320 TMPM333FDFG/FYFG/FWFG 12.3.9 ADMOD5 (Mode Control Register 5) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 4 3 2 1 7 6 5 Bit symbol - - ADOBIC1 After reset 0 0 0 Bit Bit Symbol ADREGS1 0 Type 0 0 ADOBSV1 0 0 0 Function 31-6 − R Read as 0. 5 ADOBIC1 R/W Set the AD monitor function interrupt 1. 0: If the value of the conversion result is smaller than the comparison register 1, an interrupt is generated. 1: If the value of the conversion result is bigger than the comparison register 1, an interrupt is generated. 4-1 ADREGS1[3:0] R/W Select a target conversion result register when using the AD monitor function 1 (See the below table). 0 ADOBSV1 R/W AD monitor function 1 0: Disable 1: Enable Conversion result register to be compared Conversion result register to be compared 0000 ADREG08 0100 ADREG4C 0001 ADREG19 0101 ADREG5D 0010 ADREG2A 0110 ADREG6E 0011 ADREG3B 0111 ADREG7F − − 1xxx ADREGSP Page 321 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.10 ADREG08 (Conversion Result Register 08) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR0 ADR0RF 0 0 0 0 0 0 Bit symbol ADR0 After reset 7 Bit symbol ADR0 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR0[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR0 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR0RF R AD conversion result storage flag 0: Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 322 TMPM333FDFG/FYFG/FWFG 12.3.11 ADREG19 (AD Conversion Result Register 19) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR1 ADR1RF 0 0 0 0 0 0 Bit symbol ADR1 After reset 7 Bit symbol ADR1 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR1[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR1 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before , "1" is set. This bit is "0" cleared when it is read. 0 ADR1RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 323 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.12 ADREG2A (AD Conversion Result Register 2A) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR2 ADR2RF 0 0 0 0 0 0 Bit symbol ADR2 After reset 7 Bit symbol ADR2 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR2[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR2 R Overrun flag 0: Not generated. 1: Generated. If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR2RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 324 TMPM333FDFG/FYFG/FWFG 12.3.13 ADREG3B (AD Conversion Result Register 3B) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR3 ADR3RF 0 0 0 0 0 0 Bit symbol ADR3 After reset 7 Bit symbol ADR3 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR3[9:0] R AD conversion result. Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR3 R Overrun flag 0: Not generated. 1: Generated. If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR3RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 325 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.14 ADREG4C (AD Conversion Result Register 4C) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR4 ADR4RF 0 0 0 0 0 0 Bit symbol ADR4 After reset 7 Bit symbol ADR4 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR4[9:0] R AD conversion result. Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR4 R Overrun flag 0: Not generated. 1: Generated If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR4RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a halfword or a word access. Page 326 TMPM333FDFG/FYFG/FWFG 12.3.15 ADREG5D (AD Conversion Result Register 5D) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR5 ADR5RF 0 0 0 0 0 0 Bit symbol ADR5 After reset 7 Bit symbol ADR5 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR5[9:0] R AD conversion result. Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR5 R Overrun flag 0: Not generated. 1: Generated If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR5RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 327 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.16 ADREG6E (AD Conversion Result Register 6E) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR6 ADR6RF 0 0 0 0 0 0 Bit symbol ADR6 After reset 7 Bit symbol ADR6 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR6[9:0] R AD conversion result. Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter12.4.5.7. 5-2 − R Read as 0. 1 OVR6 R Overrun flag 0: Not generated. 1: Generated. If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR6RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 328 TMPM333FDFG/FYFG/FWFG 12.3.17 ADREG7F (AD Conversion Result Register 7F) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR7 ADR7RF 0 0 0 0 0 0 Bit symbol ADR7 After reset 7 Bit symbol ADR7 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADR7[9:0] R AD conversion result. Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 12-2, chapter 12.4.5.7. 5-2 − R Read as 0. 1 OVR7 R Overrun flag 0: Not generated 1: Generated If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR7RF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 329 12. 12.3 Analog/Digital Converter (ADC) Registers TMPM333FDFG/FYFG/FWFG 12.3.18 ADREGSP (AD Conversion Result Register SP) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVRSP ADRSPRF 0 0 0 0 0 0 Bit symbol ADRSP After reset 7 Bit symbol ADRSP After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADRSP[9:0] R AD conversion result. Top-priority AD conversion result is stored 5-2 − R Read as 0 1 OVRSP R Overrun flag 0: Not generated 1: Generated If a conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADRSPRF R AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 330 TMPM333FDFG/FYFG/FWFG 12.3.19 ADCMP0 (AD Conversion Result Comparison Register 0) 31 30 29 28 27 26 25 24 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - Bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - - - 0 0 0 0 0 0 Bit symbol After reset ADCOM0 7 Bit symbol After reset Bit ADCOM0 0 Bit Symbol 0 Type Function 31-16 − R Read as 0. 15-6 ADCOM0[9:0] R/W When AD monitor function 0 is enabled, it sets a value to be compared with the value of the conversion result register specified by ADMOD3. 5-0 − R Read as 0. Note:To write values into this register, the AD monitor function 0 must be disabled (ADMOD3 ="0"). 12.3.20 Bit symbol After reset ADCMP1 (AD Conversion Result Comparison Register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 Bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Bit symbol After reset ADCOM1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - - - 0 0 0 0 0 0 0 Bit symbol After reset Bit ADCOM1 0 Bit Symbol Type Function 31-16 − R Read as 0. 15-6 ADCOM1[9:0] R/W When AD monitor function 1 is enabled, it sets a value to be compared with the value of the conversion result register specified by ADMODt. 5-0 − R Read as 0. Note:To write values into this register, the AD monitor function 1 must be disabled (ADMOD5="0"). Page 331 12. 12.4 Analog/Digital Converter (ADC) Description of Operations 12.4 TMPM333FDFG/FYFG/FWFG Description of Operations 12.4.1 Analog Reference Voltage The "High" level of the analog reference voltage shall be applied to the VRFEH pin, and the "Low" shall be applied to the VREFL pin. To start AD conversion, make sure that you first write "1" to the bit, wait for 3 μs during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0 bit. By writing "0" to the ADMOD1 bit, a switched-on state of VREFH − VREFL can be turned into a switched -off state. To switch to the power-consumption mode, set "0" to the bit after conversion. Note:VREFL and AVSS are shared by TMPM333FDFG/FYFG/FWFG. 12.4.2 AD Conversion Mode Two types of AD conversion are supported: normal AD conversion and top-priority AD conversion. For normal AD conversion, the following four operation modes are supported. 12.4.2.1 Normal AD conversion For normal AD conversion, the following four operation modes are supported and the operation mode is selected with the ADMOD0. ・ ・ ・ ・ (1) Fixed channel single conversion mode Channel scan single conversion mode Fixed channel repeat conversion mode Channel scan repeat conversion mode Fixed channel single conversion mode If ADMOD0 is set to "00", "AD conversion is performed in the fixed channel single conversion mode. In this mode, AD conversion is performed once for one channel selected. After AD conversion is completed, ADMOD0 is set to "1", ADMOD0 is cleared to "0", and the AD conversion completion interrupt request (INTAD) is generated. is cleared to "0" upon read. (2) Channel scan single conversion mode If ADMOD0 is set to "01," AD conversion is performed in the channel scan single conversion mode. In this mode, AD conversion is performed once for each scan channel selected. After AD scan conversion is completed, ADMOD0 is set to "1", ADMOD0 is cleared to "0", and the conversion completion interrupt request (INTAD) is generated. is cleared to "0". Page 332 TMPM333FDFG/FYFG/FWFG (3) Fixed channel repeat conversion mode If ADMOD0 is set to "10", AD conversion is performed in fixed channel repeat conversation mode. In this mode, AD conversion is performed repeatedly for one channel selected. After AD conversion is completed, ADMOD0 is set to "1". ADMOD0 is not cleared to "0". It remains at "1". The timing with which the conversion completion interrupt request (INTAD) is generated can be selected by setting ADMOD0 to an appropriate setting. is set with the same timing as this interrupt INTAD is generated. By reading , it is cleared to "0". (4) Channel scan repeat conversion mode If ADMOD0 is set to "11", AD conversion is performed in the channel scan repeat conversion mode. In this mode, AD conversion is performed repeatedly for a scan channel selected. Each time one AD scan conversion is completed, ADMOD0 is set to "1", and the conversion completion interrupt request (INTAD) is generated. ADMOD0 is not cleared to "0". It remains at "1". is cleared to "0" upon read. 12.4.2.2 Top-priority AD conversion By interrupting ongoing normal AD conversion, top-priority AD conversion can be performed. The fixed-channel single conversion is automatically selected, irrespective of the ADMOD0 setting. When conditions to start operation are met, a conversion is performed just once for a channel designated by ADMOD2. When conversion is completed, the top-priority AD conversion completion interrupt (INTADHP) is generated, and ADMOD2 showing the completion of AD conversion is set to "1". returns to "0". EOCFHP flag is cleared to "0" upon read. Top-priority AD conversion activated while top-priority AD conversion is under way is ignored. 12.4.3 AD Monitor Function There are two channels of AD monitor function. If ADMOD3 and ADMOD5 are set to "1", the AD monitor function is enabled. If the value of the conversion result register specified by ADMOD3 and ADMOD5 becomes larger or smaller ("Larger" or "Smaller" to be designated by ADMOD3 and ADMOD5) than the value of a comparison register, the AD monitor function interrupt (INTADM0,INTADM1) is generated. This comparison operation is performed each time a result is stored in a corresponding conversion result register. If the conversion result register assigned to perform the AD monitor function is continuously used without reading the conversion result, the conversion result is overwritten. The conversion result storage flag and the overrun flag remain being set. Page 333 12. 12.4 Analog/Digital Converter (ADC) Description of Operations 12.4.4 TMPM333FDFG/FYFG/FWFG Selecting the Input Channel After reset, ADMOD0 is initialized to "00" and ADMOD1 is initialized to "0000". The channels to be converted are selected according to the operation mode of the AD converter as shown below. 1. Normal AD conversion mode ・ If the analog input channel is used in a fixed state (ADMOD0 = "0") One channel is selected from analog input pins AIN0 through AIN11 by setting ADMOD1 to an appropriate setting. ・ If the analog input channel is used in a scan state (ADMOD0 = "1") One scan mode is selected from the scan modes by setting ADMOD1 and ADSCN to an appropriate setting. 2. Top-priority AD conversion mode One channel is selected from analog input pins from AIN0 through AIN11 by setting ADMOD2 to an appropriate setting. 12.4.5 AD Conversion Details 12.4.5.1 Starting AD Conversion Normal AD conversion is activated by setting ADMOD0 to "1". Top-priority AD conversion is activated by setting ADMOD2 to "1". Four operation modes are made available to normal AD conversion. In performing normal AD conversion, one of these operation modes must be selected by setting ADMOD0 to an appropriate setting. For top-priority AD conversion, only one operation mode can be used: fixed channel single conversion mode. Normal AD conversion can be activated using the H/W activation source selected by ADMOD4, and top-priority AD conversion can be activated using the HW activation source selected by ADMOD4. If bits of and are "0", normal and top-priority AD conversions are activated in response to the input of a falling edge through the ADTRG pin. If these bits are "1", normal AD conversion is activated in response to TB6RG0 generated by the 16-bit timer 6, and top-priority AD conversion is activated in response to TB5RG0 generated by the 16-bit timer 5. To permit H/W activation, set ADMOD4 to "1" for normal AD conversion and set ADMOD4 to "1" for top-priority AD conversion. Software activation is still valid even after H/W activation has been permitted. Note:When an external trigger is used for the HW activation source of a top-priority AD conversion, an external trigger cannot be set for activating normal AD conversion H/W. Note:The TMPM333FDFG/FYFG/FWFG disables the external trigger used for H/W activation. Therefore "0" cannot be set to and . Page 334 TMPM333FDFG/FYFG/FWFG 12.4.5.2 AD Conversion When normal AD conversion starts, the AD conversion Busy flag (ADMOD0) showing that AD conversion is under way is set to "1". When top-priority AD conversion starts, the top-priority AD conversion Busy flag (ADMOD2) showing that AD conversion is underway is set to "1". At that time, the value of the Busy flag ADMOD0 for normal AD conversion before the start of top-priority AD conversions are retained. The value of the conversion completion flag ADMOD0 for normal AD conversion before the start of top-priority AD conversion is retained. Note:Normal AD conversion must not be activated when top-priority AD conversion is under way. 12.4.5.3 Top-priority AD conversion during normal AD conversion If top-priority AD conversion has been activated during normal AD conversion, ongoing normal AD conversion is suspended, and restarts normal AD conversion after top-priority AD conversion is completed. If ADMOD2 is set to "1" during normal AD conversion, ongoing normal AD conversion is suspended, and the top-priority AD conversion starts; specifically, AD conversion (fixed-channel single conversion) is executed for a channel designated by ADMOD2. After the result of this top-priority AD conversion is stored in the storage register ADREGSP, normal AD conversion is resumed. If H/W activation of top-priority AD conversion is authorized during normal AD conversion, ongoing AD conversion is discontinued when requirements for activation using a H/W activation resource are met, and top-priority AD conversion (fixed-channel single conversion) starts for a channel designated by ADMOD2. After the result of this top-priority AD conversion is stored in the storage register ADREGSP, normal AD conversion is resumed. For example, if channel repeat conversion is activated for channels AIN0 through AIN3 and if is set to "1" during AIN2 conversion, AIN2 conversion is suspended, and conversion is performed for a channel designated by (AIN11 in the case shown below). After the result of conversion is stored in ADREGSP, channel repeat conversion is resumed, starting from AIN2. Top-priority AD has been activated Conversion Ch 12.4.5.4 Ch0 Ch1 Ch2 Ch11 Ch2 Ch3 Ch0 Stopping Repeat Conversion Mode To stop the AD conversion operation in the repeat conversion mode (fixed-channel repeat conversion mode or channel scan conversion mode), write "0" to ADMOD0. When ongoing AD conversion is completed, the repeat conversion mode terminates, and ADMOD0 is set to "0". Page 335 12. 12.4 Analog/Digital Converter (ADC) Description of Operations 12.4.5.5 TMPM333FDFG/FYFG/FWFG Reactivating normal AD conversion To reactivate normal AD conversion while the conversion is underway, a software reset (ADMOD3) must be performed before starting AD conversion. The H/W activation method must not be used to reactivate normal AD conversion. 12.4.5.6 Conversion completion (1) Normal AD conversion completion When normal AD conversion is completed, the AD conversion completion interrupt (INTAD) is generated. The result of AD conversion is stored in the storage register, and two registers change: the register ADMOD0 which indicates the completion of AD conversion and the register ADMOD0. Interrupt request, conversion register storage register and change with a different timing according to a mode selected. In mode other than fixed-channel repeat conversion mode, conversion results are stored in AD conversion result registers (ADREG08 through ADRG7F) corresponding to a channel. In fixed-channel repeat conversion mode, the conversion results are sequentially stored in storage registers ADREG08 through ADREG7F. However, if interrupt setting on is set to be generated each time one AD conversion is completed, the conversion result is stored only in ADREG08. If interrupt setting on is set to be generated each time four AD conversions are completed, the conversion results are sequentially stored in ADREG08H through ADREG3B. Interrupt requests, flag changes and conversion result registers in each mode are as shown below. ・ Fixed-channel single conversion mode After AD conversion completed, ADMOD0 is set to "1", ADMOD0 is cleared to "0", and the interrupt request is generated. Conversion results are stored a conversion result register correspond to a channel. ・ Channel scan single conversion mode After the channel scan conversion is completed, ADMOD0 is set to "1", ADMOD0 is set to "0", and the interrupt request INTAD is generated. Conversion results are stored a conversion result register correspond to a channel. ・ Fixed-channel repeat conversion mode ADMOD0 is not cleared to "0". It remains at "1". The timing with which the interrupt request INTAD is generated can be selected by setting ADMOD0 to an appropriate setting. ADMOD0 is set with the same timing as this interrupt INTAD is generated. a. One conversion With set to "00", an interrupt request is generated each time one AD conversion is completed. In this case, the conversion results are always stored in the storage register ADREG08. After the conversion result is stored, changes to "1". b. Four conversions With set to "01", an interrupt request is generated each time four AD conversions are completed. In this case, the conversion results are sequentially stored in the storage register ADREG08 through ADREG3B. After the conversion result is stored in ADREG3B, is set to "1", and the storage of subsequent conversion results starts from ADREG08. Page 336 TMPM333FDFG/FYFG/FWFG c. 8 conversions With set to "10", an interrupt request is generated each time eight AD conversions are completed. In this case, the conversion results are sequentially stored in the storage register ADREG08 through ADREG7F. After the conversion result is stored in ADREG7F, is set to "1", and the storage of subsequent conversion results starts from ADREG08. ・ Channel scan repeat conversion mode Each time one AD conversion is completed, ADMOD0 is set to "1" and interrupt request INTAD is generated. ADMOD0 is not cleared to "0". It remains at "1". AD conversion results are stored in a AD conversion result register corresponding to a channel. (2) Top-priority AD conversion completion After the AD conversion is completed, the top-priority AD conversion completion interrupt (INTADHP) is generated, and ADMOD2 which indicates the completion of top-priority AD conversion is set to "1". AD conversion results are stored in the AD conversion result register SP. (3) Data polling To confirm the completion of AD conversion without using interrupts, data polling can be used. When AD conversion is completed, ADMOD0 is set to "1". To confirm the completion of AD conversion and to obtain the results, poll this bit. AD conversion result storage register must be read by half word or word access. If = “0” and = “1”, a correct conversion result has been obtained. Page 337 12. 12.4 Analog/Digital Converter (ADC) Description of Operations 12.4.5.7 TMPM333FDFG/FYFG/FWFG Interrupt generation timings and AD conversion result storage register Table 12-1 shows a relation in the following three items: AD conversion modes, interrupt generation timings and flag operations. Table 12-2 shows a relation between analog channel inputs and AD conversion result registers. Table 12-1 Relations in conversion modes, interrupt generation timings and flag operations Scan/repeat mode setting (ADMOD0) / Conversion mode Interrupt generation timing set timing ADMOD0 ADMOD2 (After the 0 0 − After generation is completed. After conversion is completed. 0 − 00 Each time one conversion is completed. After one conversion is completed. 1 − 01 Each time four conversion is completed. After four conversions are completed. 1 − 10 Each time eight conversion is completed. After eight conversions are completed. 1 − After scan conversion is completed. 0 − Fixed-channel single conversion Fixed-channel repeat conversion 1 0 Normal conversion Channel scan single conversion Channel scan repeat conversion Top-priority conversion 0 1 − (See note) After scan conversion is completed. interrupt is generated) 1 1 − After one scan conversion is completed. After one scan conversion is completed. 1 − − − − After completion is completed. Conversion completion − 0 Note:ADMOD0 and ADMOD2 are cleared upon read. Table 12-2 Relation between analog channels input and AD conversion result registers Normal AD conversion Analog input Other conversion mode than those Fixed channel repeat conversion mode shown on the right side (every one conversion) AIN0 ADREG08 ADREG08 fixed AIN1 ADREG19 AIN2 ADREG2A AIN3 ADREG3B AIN4 ADREG4C AIN5 ADREG5D AIN6 ADREG6E AIN7 ADREG7F AIN8 ADREG08 AIN9 ADREG19 AIN10 ADREG2A AIN11 ADREG3B channels Fixed channel repeat conversion mode Fixed channel repeat conversion mode (every four conversions) (every eight conversions) Top-priority AD conversion ADREGSP ADREG08 ↓ ↓ ADREG3B ADREG08 ↓ ↓ ↓ ADREG7F Note:To access the conversion result register, use a half-word or a word access. Page 338 TMPM333FDFG/FYFG/FWFG Cautions The result value of AD conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. When using analog input pins and ports alternately, do not read and write ports during conversion because the conversion accuracy may be reduced. Also the conversion accuracy may be reduced if the output ports current fluctuate during AD conversion. Please take counteractive measures with the program such as averaging the AD conversion results. Page 339 12. 12.4 Analog/Digital Converter (ADC) Description of Operations TMPM333FDFG/FYFG/FWFG Page 340 TMPM333FDFG/FYFG/FWFG 13. Watchdog Timer(WDT) The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or other disturbances and remedying them to return the CPU to normal operation. If the watchdog timer detects a runaway, it generates a INTWDT interrupt or reset. Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI). Also, the watchdog timer notifies of the detecting malfunction to the external peripheral devices from the watchdog timer pin (WDTOUT) by outputting "Low". Note:This product does not have the watchdog timer out pin (WDTOUT). 13.1 Configuration Figure 13-1shows the block diagram of the watchdog timer. WDMOD RESET pin To internal reset Watchdog timer out control WDTOUT Watchdog timer interrupt INTWDT 225/fsys 223/fsys 221/fsys 217/fsys 215/fsys fsys 219/fsys Selector WDMOD Q Binary counter R S Reset Internal reset Write “0x4E” Write “0xB1” WDMOD Watch dog timer Control Register WDCR Internal data bus Figure 13-1 Block Diagram of the Watchdog Timer Page 341 13. 13.2 Watchdog Timer(WDT) Register TMPM333FDFG/FYFG/FWFG 13.2 Register The followings are the watchdog timer control registers and addresses. Base Address = 0x4004_0000 Register name Address(Base+) Watchdog Timer Mode Register Watchdog Timer Control Register 13.2.1 WDMOD 0x0000 WDCR 0x0004 WDMOD(Watchdog Timer Mode Register) 31 30 29 28 27 26 25 bit symbol - - - - - - - 24 - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol WDTE - I2WDT RESCR - After reset 1 0 0 1 0 Bit Bit Symbol WDTP 0 0 0 Type Function 31-8 − R Read as 0. 7 WDTE R/W Enable/Disable control 0:Disable 1:Enable 6-4 WDTP[2:0] R/W Selects WDT detection time(Refer toTable 13-1) 000: 215/fsys 100: 223/fsys 001: 217/fsys 101: 225/fsys 010: 219/fsys 110:Setting prohibited. 011: 221/fsys 111:Setting prohibited. 3 − R Read as 0. 2 I2WDT R/W Operation when IDLE mode 0: Stop 1:In operation 1 RESCR R/W Operation after detecting malfunction 0: INTWDT interrupt request generates. (Note) 1: Reset 0 − R/W Write 0. Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI). Page 342 TMPM333FDFG/FYFG/FWFG Table 13-1 Detection time of watchdog timer (fc = 40 MHz) WDMOD Clock gear value 13.2.2 CGSYSCR 000 001 010 011 100 101 000 (fc) 0.82 ms 3.28 ms 13.11 ms 52.43 ms 209.72 ms 838.86 ms 100 (fc/2) 1.63 ms 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s 101 (fc/4) 3.28 ms 13.11 ms 52.43 ms 209.72 ms 838.86 ms 3.36 s 110 (fc/8) 6.55 ms 26.21 ms 104.86 ms 419.43 ms 1.68 s 6.71 s WDCR (Watchdog Timer Control Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 16 23 22 21 20 19 18 17 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - - - - - bit symbol WDCR After reset Bit Bit Symbol Type Function 31-8 − R Read as 0. 7-0 WDCR W Disable/Clear code 0xB1:Disable code 0x4E: Clear code Others:Reserved Page 343 13. 13.3 Watchdog Timer(WDT) Operations 13.3 TMPM333FDFG/FYFG/FWFG Operations 13.3.1 Basic Operation The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input. Detecting time can be selected between 215, 217, 219 , 221, 223 and 225 by the WDMOD. The detecting time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer out pin (WDTOUT) output "Low". To detect malfunctions (runaways) of the CPU caused by noise or other disturbances, the binary counter of the watchdog timer should be cleared by software instruction before INTWDT interrupt generates. If the binary counter is not cleared, the non-maskable interrupt generates by INTWDT. Thus CPU detects malfunction (runway), malfunction countermeasure program is performed to return to the normal operation. Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices. Note:This product does not include a watchdog timer out pin (WDTOUT). 13.3.2 Operation Mode and Status The watchdog timer begins operation immediately after a reset is cleared. If not using the watchdog timer, it should be disabled. The watchdog timer cannot be used in the STOP mode, SLEEP mode and SLOW mode where high-speed frequency clock is stopped. Before transition to these modes, the watchdog timer should be disabled. In IDLE mode, its operation depends on the WDMOD setting. Also, the binary counter is automatically stopped during debug mode. Page 344 TMPM333FDFG/FYFG/FWFG 13.4 Operation when malfunction (runaway) is detected 13.4.1 INTWDT interrupt generation In the Figure 13-2 shows the case that INTWDT interrupt generates (WDMOD="0"). When an overflow of the binary counter occurs, INTWDT interrupt generates. It is a factor of non-maskable interrupt (NMI). Thus CPU detects non-maskable interrupt and performs the countermeasure program. The factor of non-maskable interrupt is the plural. CGNMIFLG identifies the factor of non-maskable interrupts. In the case of INTWDT interrupt, CGNMIFLG is set. When INTWDT interrupt generates, simultaneously the watchdog timer out (WDTOUT) output "Low". WDTOUT becomes "High" by the watchdog timer clearing that is writing clear code 0x4E to the WDCR register. Note:This product does not have the watchdog timer output pin(WDTOUT). WDT counter n Overflow 0 INTWDT Write of a clear code WDT clear WDTOUT Figure 13-2 INTWDT interrupt generation Page 345 13. 13.4 Watchdog Timer(WDT) Operation when malfunction (runaway) is detected 13.4.2 TMPM333FDFG/FYFG/FWFG Internal reset generation Figure 13-3 shows the internal reset generation (WDMOD="1"). MCU is reset by the overflow of the binary counter. In this case, reset status continues for 32 states. A clock is initialized so that input clock (fsys) is the same as a high-speed frequency clock (fosc). This means fsys = fosc. Overflow WDT counter n INTWDT Internal reset WDTOUT 32-state (3.2 Ǵs @fosc = fsys = 10 MHz) Figure 13-3 Internal reset generation Page 346 TMPM333FDFG/FYFG/FWFG 13.5 Control register The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. 13.5.1 Watchdog Timer Mode Register (WDMOD) 1. Specifying the detection time of the watchdog timer . Set the watchdog timer detecting time to WDMOD. After reset, it is initialized to WDMOD = "000". 2. Enabling/disabling the watchdog timer . When resetting, WDMOD is initialized to "1" and the watchdog timer is enabled. To disable the watchdog timer to protect from the error writing by the malfunction, first bit is set to "0", and then the disable code (0xB1) must be written to WDCR register. To change the status of the watchdog timer from "disable" to "enable," set the bit to "1". 3. Watchdog timer out reset connection This register specifies whether WDTOUT is used for internal reset or interrupt. After reset, WDMOD is initialized to "1", the internal reset is generated by the overflow of binary counter. 13.5.2 Watchdog Timer Control Register(WDCR) This is a register for disabling the watchdog timer function and controlling the clearing function of the binary counter. Page 347 13. 13.5 Watchdog Timer(WDT) Control register 13.5.3 TMPM333FDFG/FYFG/FWFG Setting example 13.5.3.1 Disabling control By writing the disable code (0xB1) to this WDCR register after setting WDMOD to "0," the watchdog timer can be disabled and the binary counter can be cleared. 13.5.3.2 7 6 5 4 3 2 1 0 WDMOD ← 0 − − − − − − − Set to "0". WDCR ← 1 0 1 1 0 0 0 1 Writes the disable code (0xB1). 7 6 5 4 3 2 1 0 1 − − − − − − − Enabling control Set WDMOD to "1". WDMOD 13.5.3.3 ← Set to "1". Watchdog timer clearing control Writing the clear code (0x4E) to the WDCR register clears the binary counter and it restarts counting. WDCR 13.5.3.4 ← 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 Writes the clear code (0x4E). Detection time of watchdog timer In the case that 221/fsys is used, set "011" to WDMOD. WDMOD ← 7 6 5 4 3 2 1 0 1 0 1 1 − − − − Page 348 TMPM333FDFG/FYFG/FWFG 14. Real Time Clock (RTC) 14.1 Function 1. 2. 3. 4. 5. 6. 14.2 Clock (hour, minute and second) Calendar (month, week, date and leap year) Selectable 12 (am/ pm) and 24 hour display Time adjustment + or − 30 seconds (by software) Alarm (alarm output) Alarm interrupt Block Diagram Clock (fs) 16 Hz clock Sec.counter 1 Hz clock Alarm register Alarm selector Comparator ALARM INTRTC Clock Internal address bus R/W control Adjust RD Internal data bus WR Data Address Figure 14-1 Block Diagram Note 1: Western calendar year column:This product uses only the final two digits of the year. The year following 99 is 00 years. Please take into account the first two digits when handling years in the western calendar. Note 2: Leap year:A leap year is divisible by 4 excluding a year divisible by 100; the year divisible by 100 is not considered to be a leap year. Any year divisible by 400 is a leap year. This product is considered the year divisible by 4 to be a leap year and does not take into account the above exceptions. It needs adjustments for the exceptions. Page 349 14. 14.3 Real Time Clock (RTC) Detailed Description Register 14.3 TMPM333FDFG/FYFG/FWFG Detailed Description Register 14.3.1 Register List The registers and the addresses related to RTC are shown as below. RTC has two functions, PAGE0 (clock) and PAGE1 (alarm), which share some parts of registers. The PAGE can be selected by setting RTCPAGER. Base Address = 0x4004_0100 Register name Address(Base+) Second column register (only PAGE0) Minute column register Hour column register - (note 1) Day of the week column register Day column register Month column register (PAGE0) Selection register of 24-hour,12-hour (PAGE1) Year column register (PAGE0) Leap year register (PAGE1) PAGE register RTCSECR 0x0000 RTCMINR 0x0001 RTCHOURR 0x0002 - 0x0003 RTCDAYR 0x0004 RTCDATER 0x0005 RTCMONTHR 0x0006 RTCYEARR 0x0007 RTCPAGER 0x0008 - (note 1) - 0x0009 - (note 1) - 0x000A - (note 1) - 0x000B RTCRESTR 0x000C Reserved - 0x000D - (note 1) - 0x000E - (note 1) - 0x000F Reset register Note 1: "0" is read by reading the address. Writing is disregarded. Note 2: Access to the "Reserved" areas is prohibited. 14.3.2 Control Register Reset operation initializes the following registers. ・ RTCPAGER, , ・ RTCRESTR, , , Other clock-related registers are not initialized by reset operation. Before starting the RTC, set the time, month, day, day of the week, year and leap year in the relevant registers. Caution is required in setting clock data, adjusting seconds or resetting the clock. Refer to "14.4.3 Entering the Low Power Consumption Mode" for more information. Page 350 TMPM333FDFG/FYFG/FWFG Table 14-1 PAGE0 (clock function) register Symbol Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function RTCSECR − 40sec. 20sec. 10sec. 8sec. 4sec. 2sec. 1sec. Second column RTCMINR − 40min. 20min. 10min. 8min. 4min. 2min. 1min. Minute column 10hour 8hour 4hour 2hour 1hours Hour column RTCHOURR − − 20hours PM/AM RTCDAYR − − − − − RTCDATER − − Day20 Day10 Day8 Day4 Day2 Day1 Day column RTCMONTHR − − − Oct. Aug. Apr. Feb. Jan. Month column RTCYEARR year 80 year 40 year20 year 10 year 8 year 4 year 2 year 1 − − Adjustment Clock enable Alarm enable − 1 Hz 16 Hz Clock Alarm enable enable reset reset RTCPAGER RTCRESTR Interrupt enable function − Day of the week Day of the week column Year column (lower two columns) PAGE PAGE setting register (FD/FY) − Reset (FW) Always write "1" register Note:Reading RTCSECR, RTCMINR, RTCHOURR, RTCDAYR, RTCMONTHR, RTCYEARR of PAGE0 captures the current state. Table 14-2 PAGE1 (alarm function) registers Symbol Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function RTCSECR − − − − − − − − − RTCMINR − 40min. 20min. 10min. 8min. 4min. 2min. 1min. Minute column 10hour 8hour 4hour 2hour 1hour Hour column RTCHOURR − − 20hours PM/AM RTCDAYR − − − − − RTCDATER − − Day20 Day10 Day8 Day4 Day2 Day1 Day column RTCMONTHR − − − − − − − 24/12 24-hour clock mode − − − − − − RTCYEARR RTCPAGER RTCRESTR Interrupt Adjustment − − 1 Hz 16 Hz Clock Alarm Enable Enable reset reset enable function Clock enable − Day of the week Alarm enable Day of the week column Leap-year setting − (FD/FY) − (FW) Always write "1" Leap-year mode PAGE PAGE setting register Reset register Note 1: Reading RTCMINR, RTCHOURR, RTCDAYR, RTCMONTHR, RTCYEARR of PAGE1 captures the current state. Note 2: RTCSECR, RTCMINR, RTCHOURR, RTCDAYR, RTCDATER, RTCMONTHR, RTCYEARR of PAGE0 and RTCYEARR of PAGE1 (for leap year) must be read twice and compare the data captured. Note:Regarding the Table 14-1 and the Table 14-2,"FD" indicates TMPM333FDFG, "FY" indicates TMPM333FYFG and "FW" indicates TMPM333FWFG. Page 351 14. 14.3 Real Time Clock (RTC) Detailed Description Register 14.3.3 TMPM333FDFG/FYFG/FWFG Detailed Description of Control Register 14.3.3.1 RTCSECR (Second column register (for PAGE0 only)) 7 bit symbol - After reset 0 Bit Bit Symbol 6 5 4 3 2 1 0 Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined SE Undefined Undefined Undefined Undefined Type Functon 7 − R Read as 0. 6-0 SE R/W Setting digit register of second 000_0000 : 00sec. 001_0000 : 10sec. 000_0001 : 01sec. 001_0001 : 11sec. 010_0000 : 20sec. ・ 000_0010 : 02sec. 001_0010 : 12sec. 011_0000 : 30sec. 000_0011 : 03sec. 001_0011 : 13sec. ・ 000_0100 : 04sec. 001_0100 : 14sec. 100_0000 : 40sec. 000_0101 : 05sec. 001_0101 : 15sec. ・ 000_0110 : 06sec. 001_0110 : 16sec. 101_0000 : 50sec. 000_0111 : 07sec. 001_0111 : 17sec. ・ 000_1000 : 08sec. 001_1000 : 18sec. ・ 000_1001 : 09sec. 001_1001 : 19sec. 101_1001 : 59sec. Note:The setting other than listed above is prohibited. 14.3.3.2 RTCMINR (Minute column register (PAGE0/1)) 7 Bit symbol - After reset 0 Bit Bit Symbol 6 5 4 3 MI Undefined Undefined Undefined Undefined Type Functon 7 − R Read as 0. 6-0 MI R/W Setting digit register of Minutes. 000_0000 : 00min. 001_0000 : 10min. 000_0001 : 01min. 001_0001 : 11min. ・ 000_0010 : 02min. 001_0010 : 12min. 011_0000 : 30min. 000_0011 : 03min. 001_0011 : 13min. ・ 000_0100 : 04min. 001_0100 : 14min. 100_0000 : 40min. 000_0101 : 05min. 001_0101 : 15min. ・ 000_0110 : 06min. 001_0110 : 16min. 101_0000 : 50min. 000_0111 : 07min. 001_0111 : 17min. ・ 000_1000 : 08min. 001_1000 : 18min. ・ 000_1001 : 09min. 001_1001 : 19min. 101_1001 : 59min. Note:The setting other than listed above is prohibited. Page 352 010_0000 : 20min. TMPM333FDFG/FYFG/FWFG 14.3.3.3 RTCHOURR (Hour column register(PAGE0/1)) (1) 24-hour clock mode (RTCMONTHR= "1") 7 6 Bit symbol - - After reset 0 0 Bit Bit Symbol 5 4 3 Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined HO Type Functon 7-6 − R Read as 0. 5-0 HO R/W Setting digit register of Hour. 00_0000 : 0 o’clock 01_0000 : 10 o’clock 10_0000 : 20 o’clock 00_0001 : 1 o’clock 01_0001 : 11 o’clock 10_0001 : 21 o’clock 00_0010 : 2 o’clock 01_0010 : 12 o’clock 10_0010 : 22 o’clock 00_0011 : 3 o’clock 01_0011 : 13 o’clock 10_0011 : 23 o’clock 00_0100 : 4 o’clock 01_0100 : 14 o’clock 00_0101 : 5 o’clock 01_0101 : 15 o’clock 00_0110 : 6 o’clock 01_0110 : 16 o’clock 00_0111 : 7 o’clock 01_0111 : 17 o’clock 00_1000 : 8 o’clock 01_1000 : 18 o’clock 00_1001 : 9 o’clock 01_1001 : 19 o’clock Note:The setting other than listed above is prohibited. (2) 12-hour clock mode (RTCMONTHR = "0") 7 6 Bit symbol - - After reset 0 0 Bit Bit Symbol 5 4 3 Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined HO Type Functon 7-6 − R Read as 0. 5-0 HO R/W Setting digit register of Hour. (AM) (PM) 00_0000 : 0 o’clock 10_0000 : 0 o’clock 00_0001 : 1 o’clock 10_0001 : 1 o’clock 00_0010 : 2 o’clock 10_0010 : 2 o’clock 00_0011 : 3 o’clock 10_0011 : 3 o’clock 00_0100 : 4 o’clock 10_0100 : 4 o’clock 00_0101 : 5 o’clock 10_0101 : 5 o’clock 00_0110 : 6 o’clock 10_0110 : 6 o’clock 00_0111 : 7 o’clock 10_0111 : 7 o’clock 00_1000 : 8 o’clock 10_1000 : 8 o’clock 00_1001 : 9 o’clock 10_1001 : 9 o’clock 01_0000 : 10 o’clock 11_0000 : 10 o’clock 01_0001 : 11 o’clock 11_0001 : 11 o’clock Note:The setting other than listed above is prohibited. Page 353 14. 14.3 Real Time Clock (RTC) Detailed Description Register 14.3.3.4 TMPM333FDFG/FYFG/FWFG RTCDAYR (Day of the week column register(PAGE0/1)) 7 6 5 4 3 Bit symbol - - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type 2 1 0 WE Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined Function 7-3 − R Read as 0. 2-0 WE R/W Setting digit register of day of the week. 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday Note:The setting other than listed above is prohibited. 14.3.3.5 RTCDATER (Day column register (for PAGE0/1 only)) 7 6 Bit symbol - - After reset 0 0 Bit Bit Symbol 5 4 3 Undefined Undefined Undefined DA Type Functon 7-6 − R Read as 0. 5-0 DA R/W Setting digit register of day. 01_0000 : 10th day 10_0000 : 20th day 11_0000 : 30th day 00_0001 : 1st day 01_0001 : 11th day 10_0001 : 21th day 11_0001 : 31th day 00_0010 : 2nd day 01_0010 : 12th day 10_0010 : 22th day 00_0011 : 3rd day 01_0011 : 13th day 10_0011 : 23th day 00_0100 : 4th day 01_0100 : 14th day 10_0100 : 24th day 00_0101 : 5th day 01_0101 : 15th day 10_0101 : 25th day 00_0110 : 6th day 01_0110 : 16th day 10_0110 : 26th day 00_0111 : 7th day 01_0111 : 17th day 10_0111 : 27th day 00_1000 : 8th day 01_1000 : 18th day 10_1000 : 28th day 00_1001 : 9th day 01_1001 : 19th day 10_1001 : 29th day Note 1: The setting other than listed above is prohibited. Note 2: Do not set for non-existent days (e.g.: 30th Feb.). Page 354 TMPM333FDFG/FYFG/FWFG 14.3.3.6 RTCMONTHR (Month column register (for PAGE0 only)) 7 6 5 Bit symbol - - - After reset 0 0 0 Bit Bit Symbol 4 3 2 1 0 Undefined Undefined MO Undefined Undefined Type Undefined Functon 7-5 − R Read as 0. 4-0 MO R/W Setting digit register of Month. 0_0001 : January 0_0111 : July 0_0010 : February 0_1000 : August 0_0011 : March 0_1001 : September 0_0100 : April 1_0000 : October 0_0101 : May 1_0001 : November 0_0110 : June 1_0010 : December Note:The setting other than listed above is prohibited. 14.3.3.7 RTCMONTHR (Selection of 24-hour clock or 12-hour clock24(for PAGE1 only)) 7 6 5 4 3 2 1 0 bit symbol - - - - - - - MO0 After reset 0 0 0 0 0 0 0 Undefined Bit Bit Symbol Type Function 7-1 − R Read as 0. 0 MO0 R/W 0: 12-hour 1: 24-hour Note:Do not change the RTCMONTHR while the RTC is in operation. Page 355 14. 14.3 Real Time Clock (RTC) Detailed Description Register 14.3.3.8 TMPM333FDFG/FYFG/FWFG RTCYEARR (Year column register (for PAGE0 only)) 7 6 5 4 bit symbol After reset Bit 7-0 3 2 1 0 Undefined Undefined Undefined Undefined YE Undefined Bit Symbol YE Undefined Undefined Undefined Type R/W Function Setting digit register of Year. 0000_0000 : 00 years 0001_0000 : 10 years 0000_0001 : 01 years ・ 0110_0000 : 60 years ・ 0000_0010 : 02 years 0010_0000 : 20 years 0111_0000 : 70 years 0000_0011 : 03 years ・ ・ 0000_0100 : 04 years 0011_0000 : 30 years 1000_0000 : 80 years 0000_0101 : 05 years ・ ・ 0000_0110 : 06 years 0100_0000 : 40 years 1001_0000 : 90 years 0000_0111 : 07 years ・ ・ 0000_1000 : 08 years 01001_0000 : 50 years ・ 0000_1001 : 09 years ・ 1001_1001 : 99 years Note:The setting other than listed above is prohibited. 14.3.3.9 RTCYEARR (Leap year register (for PAGE1 only)) 7 6 5 4 3 2 bit symbol - - - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type Functon 7-2 − R Read as 0. 1-0 LEAP R/W 00 : leap year 01 : one year after leap year 10 : two years after leap year 11 : three years after leap year Page 356 1 0 LEAP Undefined Undefined TMPM333FDFG/FYFG/FWFG 14.3.3.10 RTCPAGER(PAGE register(PAGE0/1)) 7 6 5 4 3 2 1 0 Bit symbol INTENA - - ADJUST ENATMR ENAALM - PAGE After reset 0 0 0 0 Undefined Undefined 0 0 Bit 7 Bit Symbol INTENA Type R/W Function INTRTC 0:Disable 1:Enable 6-5 − R Read as 0. 4 ADJUST R/W [Write] 0: Don't care 1: Sets ADJUST request Adjusts seconds. The request is sampled when the sec. counter counts up. If the time elapsed is between 0 and 29 seconds, the sec. counter is cleared to "0". If the time elapsed is between 30 and 59 seconds, the min. counter is carried and sec. counter is cleared to "0". [Read] 0: ADJUST no request 1: ADJUST requested If "1" is read, it indicates that ADJUST is being executed. If "0" is read, it indicates that the execution is finished. 3 ENATMR R/W Clock 0: Disable 1: Enable 2 ENAALM R/W ALARM 0: Disable 1: Enable 1 − R Read as 0. 0 PAGE R/W PAGE selection 0:Selects Page0 1:Selects Page1 Note 1: A read-modify-write operation cannot be porfomed. Note 2: To set interrupt enable bits to , and , you must follow the order specified here. Make sure not to set them at the same time (make sure that there is time lag between interrupt enable and clock/ alarm enable).To change the setting of and , must be disabled first. Example: Clock setting/Alarm setting 7 6 5 4 3 2 1 0 RTCPAGER ← 0 0 0 0 1 1 0 0 Enables Clock and alarm RTCPAGER ← 1 0 0 0 1 1 0 0 Enables interrupt Page 357 14. 14.3 Real Time Clock (RTC) Detailed Description Register 14.3.3.11 TMPM333FDFG/FYFG/FWFG RTCRESTR (Reset register (for PAGE0/1)) 7 6 5 4 3 2 1 0 Bit symbol DIS1HZ DIS16HZ RSTTMR RSTALM - - - - After reset 1 1 0 0 0 0(FD/FY) 0(FD/FY) 0(FD/FY) 1(FW) 1(FW) 1(FW) Bit 7 Bit Symbol DIS1HZ Type R/W Function 1 Hz 0:Enable 1: Disable 6 DIS16HZ R/W 16 Hz 0: Enable 1: Disable 5 RSTTMR R/W [Write] 0: Don't care 1: Sec.counter reset Resets the sec counter. The equest is sampled using low-speed clock. [Read] 0: No reset request 1: RESET requested If "1" is read, it indicates that RESET is being executed. If "0" is read, it indicates that the execution is finished. 4 RSTALM R/W 0:Don't care 1: Alarm reset Initializes alarm registers (Minute column, hour column, day column and day of the week column) as follows. MInute:00, Hour:00, Day:01, Day of the week:Sunday 3 − R Read as 0. 2-0 − R FD/FY(Note2) : Read as 0. R/W FW(Note2) : Write "1". Note 1: A read-modify-write operation cannot be performed. Note 2: "FD" indicates TMPM333FDFG, "FY" indicates TMPM333FYFG and "FW" indicates TMPM333FWFG. The setting of and ,RTCPAGER used for alarm, 1Hz interrupt and 16Hz interrupt is shown as below. RTCPAGER Interrupt source signal 1 1 Alarm 1 0 1 Hz 0 0 1 0 1 Others Page 358 16 Hz Interrupt not generated. TMPM333FDFG/FYFG/FWFG 14.4 Operational Description The RTC incorporates a second counter that generates a 1Hz signal from a 32.768 kHz signal. The second counter operation must be taken into account when using the RTC. 14.4.1 Reading clock data 1. Using 1Hz interrupt The 1Hz interrupt is generated being synchronized with counting up of the second counter. Data can be read correctly if reading data after 1Hz interrupt occurred. 2. Using pair reading There is a possibility that the clock data may be read incorrectly if the internal counter operates carry during reading. To ensure correct data reading, read the clock data twice as shown below. A pair of data read successively needs to match. Start RTCPAGER = "0", then select PAGE0 Clock data reading (1st) Clock data reading (2nd) 1st data = 2nd data NO YES End Figure 14-2 Flowchart of the clock data reading 14.4.2 Writing clock data A carry during writing ruins correct data writing. The following procedure ensures the correct data writing. 1. Using 1 Hz interrupt The 1Hz interrupt is generated by being synchronized with counting up of the second counter. If data is written in the time between 1Hz interrupt and subsequent one second count, it completes correctly. 2. Resetting counter Write data after resetting the second counter. The 1Hz-interrupt is generated one second after enabling the interrupt subsequent to counter reset. The time must be set within one second after the interrupt. Page 359 14. 14.4 Real Time Clock (RTC) Operational Description TMPM333FDFG/FYFG/FWFG Strat RTCPAGER = "0" then select PAGE0 RTCRESTR = "1" then reset counter RTCRESTR = "0" then enable 1Hz interrupt First interrupt (After 1s) NO YES Timer setting End Figure 14-3 Flowchart of the clock data writing 3. Disabling the clock Writing "0" to RTCPAGER disables clock operation including a carry. Stop the clock after the 1Hz-interrupt. The second counter keeps counting. Set the clock again and enable the clock within one second before next 1Hz-interrupt Start Disabling clock Writing the clock data Enabling the clock End Figure 14-4 Flowchart of the disabling clock Page 360 TMPM333FDFG/FYFG/FWFG 14.4.3 Entering the Low Power Consumption Mode To enter SLEEP mode, in which the system clock stops, after changing clock data, adjusting seconds or resetting the clock, be sure to observe one of the following procedures 1. After changing the clock setting registers, setting the RTCPAGER bit or setting the RTCRESTR bit, wait for one second for an interrupt to be generated. 2. After changing the clock setting registers, setting the RTCPAGER bit or setting the RTCRESTR bit, read the corresponding clock register values, or to make sure that the setting you have made is reflected. Page 361 14. 14.5 Real Time Clock (RTC) Alarm function 14.5 TMPM333FDFG/FYFG/FWFG Alarm function By writing "1" to RTCPAGER, the alarm function of the PAGE1 registers is enabled. One of the following three signals is output to the ALARM pin. 1. "Low" pulse (when the alarm register corresponds with the clock) 2. 1Hz cycle "Low" pulse 3. 16Hz cycle "Low" pulse In any cases shown above, the INTRTC outputs one cycle pulse of low-speed clock. It outputs the INTRTC interrupt request simultaneously. The INTRTC interrupt signal is falling edge triggered.Specify the falling edge as the active state in the CG Interrupt Mode Control Register 14.5.1 "Low" pulse (when the alarm register corresponds with the clock) "Low" pulse is output to the ALARM pin when the values of the PAGE0 clock register and the PAGE1 alarm register correspond. The INTRTC interrupt is generated and the alarm is triggered. The alarm settings Initialize the alarm with alarm prohibited. Write "1" to RTCRESTR. It makes the alarm setting to be 00 minute, 00 hour, 01 day and Sunday. Setting alarm for min., hour, date and day is done by writing data to the relevant PAGE1 register. Enable the alarm with the RTCPAGER bit. Enable the interrupt with the RTCPAGER bit. The following is an example program for outputting an alarm from the ALARM pin at noon (12:00) on Monday 5th. 7 6 5 4 3 2 1 0 RTCPAGER ← 0 0 0 0 1 0 0 1 Disables alarm,sets PAGE1 RTCRESTR ← 1 1 0 1 0 0 0 0 Initializes alarm RTCDAYR ← 0 0 0 0 0 0 0 1 Monday RTCDATER ← 0 0 0 0 0 1 0 1 5th day RTCHOURR ← 0 0 0 1 0 0 1 0 Sets 12 o’clock RTCMINR ← 0 0 0 0 0 0 0 0 Sets 00 min RTCPAGER ← 0 0 0 0 1 1 0 0 Enables alarm RTCPAGER ← 1 0 0 0 1 1 0 0 Enables interrupts The above alarm works in synchronization with the low-speed clock. When the CPU is operating at high frequency oscillation, a maximum of one clock delay at fs (about 30μs) may occur for the time register setting to become valid. Note:To make the alarm work repeatedly (e.g. every Wednesday at 12:00), next alarm must be set during the INTRTC interrupt routine that is generated when the time set for the alarm matches the RTC count. Page 362 TMPM333FDFG/FYFG/FWFG 14.5.2 1Hz cycle "Low" pulse1 Hz The RTC outputs a "Low" pulse cycle of low-speed 1Hz clock to the ALARM pin by setting RTCPAGER="1" after setting RTCPAGER= "0", RTCRESTR= "0" and = "1". It generates an INTRTC interrupt simultaneously. 14.5.3 16Hz cycle "Low" pulse16 Hz The RTC outputs a "Low" pulse cycle of low-speed 16Hz clock to the ALARM pin by setting RTCPAGER="1" after setting RTCPAGER= "0", RTCRESTR= "1" and = "0". It generates an INTRTC interrupt simultaneously. Page 363 14. 14.5 Real Time Clock (RTC) Alarm function TMPM333FDFG/FYFG/FWFG Page 364 TMPM333FDFG/FYFG/FWFG 15. Flash Memory Operation This section describes the hardware configuration and operation of the flash memory. 15.1 Flash Memory 15.1.1 Features 1. Memory capacity The TMPM333FDFG/FYFG/FWFG devices contain flash memory. The memory sizes and configurations of each device are shown in the table below. Independent write access to each block is available. When the CPU is to access the internal flash memory, 32-bit data bus width is used. 2. Write/erase time Writing is executed per page. The TMPM333FDFG/TMPM333FYFG contain 128 words and the TMPM333FWFG contains 64 words in a page. Page writing requires 1.25ms (typical) regardless of number of words. A block erase requires 0.1 sec. (typical). The following table shows write and erase time per chip. Note: Product Name Memory Size TMPM333FDFG 512 KB TMPM333FYFG TMPM333FWFG Block Configuration # of Words Write Time Erase Time − 128 1.28 sec 0.4 sec 2 − 128 0.64 sec 0.4 sec 1 2 64 0.64 sec 0.2 sec 128 KB 64 KB 32 KB 16 KB 3 1 2 256 KB 1 1 128 KB − 1 The above values are theoretical values not including data transfer time. The write time per chip depends on the write method to be used by the user. 3. Programming method There are two types of the onboard programming mode for the user to program (rewrite) the device while it is mounted on the user's board: ・ The onboard programming mode a. User boot mode The user's original rewriting method can be supported. b. Single boot mode The rewriting method to use serial data transfer (Toshiba's unique method) can be supported. 4. Rewriting method The flash memory included in this device is generally compliant with the applicable JEDEC standards except for some specific functions. Therefore, if the user is currently using an external flash memory Page 365 15. 15.1 Flash Memory Operation Flash Memory TMPM333FDFG/FYFG/FWFG device, it is easy to implement the functions into this device. Furthermore, the user is not required to build his/her own programs to realize complicated write and erase functions because such functions are automatically performed using the circuits already built-in the flash memory chip. JEDEC compliant functions Modified, added, or deleted functions ・ Automatic programming ・ Automatic chip erase Block protect (only software protection is supported) ・ Automatic block erase Erase resume - suspend function ・ Data polling/toggle bit 5. Protect/ Security Function This device is also implemented with a read-protect function to inhibit reading flash memory data from any external writer device. On the other hand, rewrite protection is available only through command-based software programming; any hardware setting method to apply +12VDC is not supported. See the chapter "ROM protection" for details of ROM protection and security function. Note: If a password is set to 0xFF (erased data), it is difficult to protect data securely due to an easy-to-guess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. Page 366 TMPM333FDFG/FYFG/FWFG 15.1.2 Block Diagram of the Flash Memory Section Internal address bus Internal data bus Internal control bus ROM controller Control Address Data Flash memory Control circuit (includes automatic sequence control) Data latch Column decoder/sense amplifier Row decoder Command register Address latch Flash memory cell Erase block decoder Figure 15-1 Block Diagram of the Flash Memory Section Page 367 15. 15.2 Flash Memory Operation Operation Mode 15.2 TMPM333FDFG/FYFG/FWFG Operation Mode This device has three operation modes including the mode not to use the internal flash memory. Table 15-1 Operation Modes Operation mode Operation details Single chip mode After reset is cleared, it starts up from the internal flash memory. Normal mode In this operation mode, two different modes, i.e., the mode to execute user application programs and the mode to rewrite the flash memory onboard the user’s card, are defined. The former is referred to as "normal mode" and the latter "user boot mode. User boot mode The user can uniquely configure the system to switch between these two modes. For example, the user can freely design the system such that the normal mode is selected when the port "A0" is set to "1" and the user boot mode is selected when it is set to "0." The user should prepare a routine as part of the application program to make the decision on the selection of the modes. Single boot mode After reset is cleared, it starts up from the internal Boot ROM (Mask ROM). In the Boot ROM, an algorithm to enable flash memory rewriting on the user’s set through the serial port of this device is programmed. By connecting to an external host computer through the serial port, the internal flash memory can be programmed by transferring data in accordance with predefined protocols. Among the flash memory operation modes listed in the above table, the User Boot mode and the Single Boot mode are the programmable modes. These two modes, the User Boot mode and the Single Boot mode, are referred to as "Onboard Programming" modes where onboard rewriting of internal flash memory can be made on the user's card. Either the Single Chip or Single Boot operation mode can be selected by externally setting the level of the BOOT (PH0) pin while the device is in reset status. Table 15-2 Operation Mode Setting Operation mode Pin RESET BOOT (PH0) Single chip mode 0→1 1 Single boot mode 0→1 0 Reset state Single chip mode Single boot mode Normal mode User boot mode Onboard programming mode User to set the switch method Figure 15-2 Mode Transition Diagram Page 368 TMPM333FDFG/FYFG/FWFG 15.2.1 Reset Operation To reset the device, ensure that the power supply voltage is within the operating voltage range, that the internal oscillator has been stabilized, and that the RESET input is held at "0" for a minimum duration of 12 system clocks (0.3 μs with 40MHz operation; the "1/1" clock gear mode is applied after reset). Note 1: Regarding power-on reset of devices with internal flash memory; for devices with internal flash memory, it is necessary to apply "0" to the RESET inputs upon power on for a minimum duration of 700 microseconds regardless of the operating frequency. Note 2: While flash auto programming or deletion is in progress, at least 0.5 microseconds of reset period is required regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. Page 369 15. 15.2 Flash Memory Operation Operation Mode 15.2.2 TMPM333FDFG/FYFG/FWFG User Boot Mode (Single chip mode) User Boot mode is to use flash memory programming routine defined by users. It is used when the data transfer buses for flash memory program code on the old application and for serial I/O are different. It operates at the single chip mode; therefore, a switch from normal mode in which user application is activated at the single chip mode to User Boot Mode for programming flash is required. Specifically, add a mode judgment routine to a reset program in the old application. The condition to switch the modes needs to be set by using the I/O of TMPM333FDFG/FYFG/FWFG in conformity with the user’s system setup condition. Also, flash memory programming routine that the user uniquely makes up needs to be set in the new application. This routine is used for programming after being switched to User Boot Mode. The execution of the programming routine must take place while it is stored in the area other than the flash memory since the data in the internal flash memory cannot be read out during delete/ writing mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. Be sure not to cause any exceptions including a non-maskable while User Boot Mode. (1-A) and (1-B) are the examples of programming with routines in the internal flash memory and in the external memory. For a detailed description of the erase and program sequence, refer to "15.3 On-board Programming of Flash Memory (Rewrite/Erase)". 15.2.2.1 (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1) Step-1 Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMPM333FDFG/FYFG/FWFG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Programming routine: Code to download new program code from a host controller and re-program the flash memory (c) Copy routine: Code to copy the data described in (b) from the TMPM333FDFG/FYFG/FWFG flash memory to either the TMPM333FDFG/FYFG/FWFG on-chip RAM or external memory device. (Host) New Application Program Code TMPM333FDFG/FYFG/FWFG (I/O) Flash memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy routine Page 370 TMPM333FDFG/FYFG/FWFG (2) Step-2 After RESET is released, the reset procedure determines whether to put the TMPM333FDFG/FYFG/ FWFG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be disabled while in User Boot mode.) (Host) TMPM333FDFG/FYFG/FWFG New Application Program Code (I/O) 0 → 1 RESET Flash memory Old Application Program Code Conditions for entering User Boot mode (defined by the user) [Reset Procedure] (a) Mode Judgment Routine (b) Programming routine RAM (c) Copy routine (3) Step-3 Once transition to User Boot mode is occurred, execute the copy routine (c) to copy the flash programming routine (b) to the TMPM333FDFG/FYFG/FWFG on-chip RAM. (Host) TMPM333FDFG/FYFG/FWFG (I/O) Flash memory Old Application Program Code [Reset procedure] (b) Programming routine (a) Mode judgment routine (b) Programming routine (c) Copy routine RAM Page 371 New Application Program Code 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG (4) Step-4 Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. (Host) TMPM333FDFG/FYFG/FWFG New Application Program Code (I/O) Flash memory (Erased) [Reset procedure] (b) Programming routine (a) Mode judgment routine (b) Programming routine (c) Copy routine (5) RAM Step-5 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user’s program area must be set. (Host) TMPM333FDFG/FYFG/FWFG (I/O) Flash memory New Application Program Code [Reset procedure] (b) Programming࣮ routine (a) Mode judgment routine (b) Programming routine (c) Copy routine RAM Page 372 New Application Program Code TMPM333FDFG/FYFG/FWFG (6) Step-6 Set RESET to "0" to reset the TMPM333FDFG/FYFG/FWFG. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. (Host) TMPM333FDFG/FYFG/FWFG (I/O) 0 → 1 RESET Flash memory New application program code Set to normal mode [Reset procedure] (a) Mode judgment routine (b) Programming routine (c) Copy routine RAM Page 373 15. 15.2 Flash Memory Operation Operation Mode 15.2.2.2 TMPM333FDFG/FYFG/FWFG (1-B) Method 2: Transferring a Programming Routine from an External Host (1) Step-1 Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMPM333FDFG/FYFG/FWFG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Transfer routine: Code to download new program code from a host controller Also, prepare a programming routine shown below on the host controller: (c) Programming routine: Code to download new program code from an external host controller and re-program the flash memory (Host) New application program code (c) Programming routine TMPM333FDFG/FYFG/FWFG (I/O) Flash memory Old application program code [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine Page 374 TMPM333FDFG/FYFG/FWFG (2) Step-2 After RESET is released, the reset procedure determines whether to put the TMPM333FDFG/FYFG/ FWFG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be disabled while in User Boot mode). New application program code (Host) (c) Programming routine TMPM333FDFG/FYFG/FWFG (I/O) 0 → 1 RESET Flash memory Old application program code Conditions for entering User Boot mode (defined by the user) [Reset procedure] (a) Mode judgment routine (b) Transfer routine (3) RAM Step-3 Once User Boot mode is entered, execute the transfer routine (b) to download the flash programming routine (c) from the host controller to the TMPM333FDFG/FYFG/FWFG on-chip RAM. New application Program code (Host) (c) Programming routine TMPM333FDFG/FYFG/FWFG (I/O) Flash memory Old application program code (c) Programming routine [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine Page 375 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG (4) Step-4 Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. (Host) New application program code (c) Programming routine TMPM333FDFG/FYFG/FWFG (I/O) Flash memory (Erased) (c) Programming routine [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine (5) Step-5 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user program area must be set. (Host) New application program code (c) Programming routine TMPM333FDFG/FYFG/FWFG (I/O) Flash memory New application Program code (c) Programming routine [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine Page 376 TMPM333FDFG/FYFG/FWFG (6) Step-6 Set RESET to "0" low to reset the TMPM333FDFG/FYFG/FWFG. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. (Host) TMPM333FDFG/FYFG/FWFG (I/O) 0 → 1 RESET Flash memory New application program code Set to normal mode [Reset procedure] (a) Mode judgment routine (b) Transfer routine RAM Page 377 15. 15.2 Flash Memory Operation Operation Mode 15.2.3 TMPM333FDFG/FYFG/FWFG Single Boot Mode In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMPM333FDFG/FYFG/FWFG on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it. Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the TMPM333FDFG/FYFG/FWFG is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMPM333FDFG/FYFG/FWFG on-chip RAM. Then, the flash memory is re-programmed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO0 and the host must follow the protocol described later. To secure the contents of the flash memory, the validity of the application’s password is verified before a programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the non-maskable interrupt (NMI) must be disabled in Single Boot mode while the flash memory is being erased or programmed. In Single Boot mode, the boot-ROM programs are executed in Normal mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. 15.2.3.1 (2-A) Using the Program in the On-Chip Boot ROM (1) Step-1 The flash block containing the older version of the program code need not be erased before executing the programming routine. Since a programming routine and programming data are transferred via the SIO (SIO0), the SIO0 must be connected to a host controller. Prepare a programming routine (a) on the host controller. (Host) New application program code (a) Programming routine TMPM333FDFG/FYFG/FWFG Boot ROM (I/O) SIO0 Flash memory Old application program code (or erased state) RAM Page 378 TMPM333FDFG/FYFG/FWFG (2) Step-2 Set the RESET pin to "1" to cancel the reset of the TMPM333FDFG/FYFG/FWFG when the BOOT pin has already been set to "0". After reset, CPU reboots from the on-chip boot ROM. The 12byte password transferred from the host controller via SIO0 is first compared to the contents of the special flash memory locations. (If the flash block has already been erased, the password is 0xFF). (Host) New application program code (a) Programming routine TMPM333FDFG/FYFG/FWFG Boot ROM (I/O) 0 → 1 RESET SIO0 Flash memory 0 BOOT Old application program code (or erased state) (3) RAM Step-3 If the password was correct, the boot program downloads, via the SIO0, the programming routine (a) from the host controller into the on-chip RAM of the TMPM333FDFG/FYFG/FWFG. The programming routine must be stored in the range from 0x2000_0400 to the end address of RAM. (Host) New application program code (a) Programming routine TMPM333FDFG/FYFG/FWFG Boot ROM (I/O) SIO0 Flash memory Old application Program code (or erased state) (a) Programming routine RAM Page 379 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG (4) Step-4 The CPU jumps to the programming routine (a) in the on-chip RAM to erase the flash block containing the old application program code. The Block Erase or Chip Erase command may be used. (Host) New application Program code (a) Programming routine TMPM333FDFG/FYFG/FWFG Boot ROM (I/O) SIO0 Flash memory (a) Programming routine Erased RAM (5) Step-5 Next, the programming routine (a) downloads new application program code from the host controller and programs it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user’s program area must be set. In the example below, new program code comes from the same host controller via the same SIO0 channel as for the programming routine. However, once the programming routine has begun to execute, it is free to change the transfer path and the source of the transfer. Create board hardware and a programming routine to suit your particular needs. (Host) New application Program code (a) Programming routine TMPM333FDFG/FYFG/FWFG Boot ROM (I/O) SIO0 Flash memory New application program code (a) Programming routine RAM Page 380 TMPM333FDFG/FYFG/FWFG (6) Step-6 When programming of the flash memory is complete, power off the board and disconnect the cable leading from the host to the target board. Turn on the power again so that the TMPM333FDFG/FYFG/ FWFG re-boots in Single-Chip (Normal) mode to execute the new program. (Host) TMPM333FDFG/FYFG/FWFG (I/O) Boot ROM 0 → 1 RESET SIO0 Flash memory Set to Single-Chip Normal) mode (BOOT=1) New application program code RAM 15.2.4 Configuration for Single Boot Mode To execute the on-board programming, boot the TMPM333FDFG/FYFG/FWFG with Single Boot mode following the configuration shown below. BOOT(PH0) = 0 RESET = 0 → 1 Set the RESET input to "0", and set the each BOOT (PH0) pins to values shown above, and then release RESET (high). Page 381 15. 15.2 Flash Memory Operation Operation Mode 15.2.5 TMPM333FDFG/FYFG/FWFG Memory Map Figure 15-3 shows a comparison of the memory maps in Normal and Single Boot modes. In Single Boot mode, the internal flash memory is mapped to 0x3F80_0000 and later addresses, and the Internal boot ROM (Mask ROM) is mapped to 0x0000_0000 through 0x0000_1FFF. The internal flash memory and RAM addresses of each device are shown below. Product Name Flash Size RAM Size TMPM333FDFG 512 KB 32 KB Flash Address RAM Address (Single Chip/ Single Boot Mode) 0x0000_0000 to 0x0007_FFFF 0x2000_0000 to 0x2000_7FFF 0x3F80_0000 to 0x3F87_FFFF 0x0000_0000 to 0x0003_FFFF TMPM333FYFG 256 KB 16 KB (0x0007_FE00 to 0x0007_FFFF) (Note) 0x2000_0000 to 0x2000_3FFF 0x3F80_0000 to 0x3F83_FFFF (0x3F87_FE00 to 0x3F87_FFFF) (Note) TMPM333FWFG 128 KB 8 KB 0x0000_0000 to 0x0001_FFFF 0x2000_0000 to 0x2000_1FFF 0x3F80_0000 to 0x3F81_FFFF Note:In addition to 256KB flash area, the TMPM333FYFG provides 128-word data/password area (1 page) for Show Product Information command. Single Boot Mode Single Chip Mode 0xFFFF_FFFF 0xFFFF_FFFF 0x4000_7FFF Internal I/O Internal I/O 0x4000_0000 0x4000_7FFF 0x4000_0000 Internal Flash ROM (512 KB) Reserved 0x3F87_FFFF 0x3F80_0000 0x3F7F_FFFF 0x3F7F_F000 Internal RAM (32 KB) 0x2000_7FFF Internal Flash ROM 0x0007_FFFF (512 KB) Internal RAM (32 KB) 0x2000_0000 0x2000_7FFF 0x2000_0000 Internal BOOT ROM 0x0000_0FFF (4 KB) 0x0000_0000 Figure 15-3 Memory Maps for TMPM333FDFG Page 382 0x0000_0000 TMPM333FDFG/FYFG/FWFG 15.2.6 Interface specification In Single Boot mode, an SIO channel is used for communications with a programming controller. The same configuration is applied to a communication format on a programming controller to execute the on-board programming. Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. The communication formats are shown below. ・ UART communication Communication channel : SIO channel 0 Serial transfer mode : UART (asynchronous), half -duplex, LSB fast Data length : 8 bit Parity bits : None STOP bits : 1 bit Baud rate : Arbitrary baud rate ・ I/O interface mode Communication channel : SIO channel 0 Serial transfer mode : I/O interface mode, full -duplex, LSB fast Synchronization clock (SCLK0) : Input mode Handshaking signal : PE4 configured as an output mode Baud rate : Arbitrary baud rate Table 15-3 Required Pin Connections Interface Pins Power supply pins UART I/O Interface Mode RVDD3 ο ο AVDD ο ο DVDD3 ο ο RVSS ο ο AVSS ο ο DVSS3 ο ο Mode-setting pin BOOT (PH0) ο ο Reset pin RESET ο ο TXD0 (PE0) ο ο Communication pins RXD0 (PE1) ο ο SCLK0 (PE2) × ο (Input mode) PE4 × ο(Output mode) Page 383 15. 15.2 Flash Memory Operation Operation Mode 15.2.7 TMPM333FDFG/FYFG/FWFG Data Transfer Format Table 15-4 and Table 15-6 to Table 15-9 illustrate the operation commands and data transfer formats at each operation mode. In conjunction with this section, refer to "15.2.10 Operation of Boot Program". Table 15-4 Single Boot Mode Commands 15.2.8 Code Command 0x10 RAM transfer 0x20 Show Flash Memory SUM 0x30 Show Product Information 0x40 Chip and protection bit erase Restrictions on internal memories Single Boot Mode places restrictions on the internal RAM and ROM as shown in Table 15-5. Table 15-5 Restrictions in Single Boot Mode Details Memory Internal RAM A program contained in the BOOT ROM uses the area, through 0x2000_0000 to 0x2000_03FF as a work area. Store the RAM transfer program from 0x2000_0400 through the end address of RAM. The following addresses are assigned for storing software ID information and passwords. Storing program in these addresses is not recommendable. Internal ROM TMPM333FDFG: 0x3F87_FF00 to 0x3F87_FF0F TMPM333FYFG: 0x3F87_FF00 to 0x3F87_FF0F TMPM333FWFG: 0x3F81_FF00 to 0x3F81_FF0F 15.2.9 Transfer Format for Single Boot Mode commands The following tables shows the transfer format for each Single Boot Mode command. Use this section in conjunction with Chapter "15.2.10 Operation of Boot Program". Page 384 TMPM333FDFG/FYFG/FWFG 15.2.9.1 RAM Transfer Table 15-6 Transfer Format for the RAM Transfer Command Data Transferred from the Controller Byte Boot ROM 1 byte to the TMPM333FDFG/FYFG/FWFG Serial operation mode and baud rate For UART mode : 0x86 Data Transferred from the TMPM333FDFG/ FYFG/FWFG to the Controller Baud rate Desired baud rate (Note 1) − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode -Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode -Normal acknowledge :0x30 3 byte Command code (0x10) − 4 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 5 byte Password sequence (12 bytes) to 0x3F87_FF04 to 0x3F87_FF0F (FD/FY) − 16 byte 0x3F81_FF04 to 0x3F81_FF0F (FW) 17 byte Check SUM value for bytes 5 - 16 − 18 byte − ACK for the checksum byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 19 byte RAM storage start address 31 to 24 − 20 byte RAM storage start address 23 to 16 − 21 byte RAM storage start address 15 to 8 − 22 byte RAM storage start address 7 to 0 − 23 byte RAM storage byte count 15 to 8 − 24 byte RAM storage byte count 7 to 0 − 25 byte Check SUM value for bytes 19 to 24 − 26 byte − ACK for the checksum byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 27 byte RAM storage data − m + 1 byte Checksum value for bytes 27 ~ m − m + 2 byte − ACK for the checksum byte (Note 2) to m byte -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 RAM m + 3 byte − Jump to RAM storage start address Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Note 3: The 19th to 25th bytes must be within the RAM address range from 0x2000_0400 through the end address of RAM. Note 4: FD/ FY/ FW in the above table denotes the TMPM333FDFG, TMPM333FYFG and TMPM333FWFG respectively. Page 385 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG 15.2.9.2 Show Flash Memory SUM Table 15-7 Transfer Format for the Show Flash Memory SUM Command Data Transferred from the Controller Byte Boot ROM 1 byte to the TMPM333FDFG/FYFG/FWFG Data Transferred from the TMPM333FDFG/ FYFG/FWFG to the Controller Baud rate Serial operation mode and baud rate Desired baud For UART mode : 0x86 rate (Note 1) − For I/O Interface mode: 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode -Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode -Normal acknowledge : 0x30 3 byte Command code (0x20) − 4 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x20 -Negative acknowledge : 0xX1 -Communication error : 0xX8 5 byte − SUM (upper byte) 6 byte − SUM (lower byte) 7 byte − Checksum value for bytes 5 and 6 8 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Page 386 TMPM333FDFG/FYFG/FWFG 15.2.9.3 Transfer Format for the Show Product Information Table 15-8 Transfer Format for the Show Product Information Command Data Transferred from the Controller Byte Boot ROM 1 byte to the TMPM333FDFG/FYFG/FWFG Baud rate Serial operation mode and baud rate Desired baud For UART mode : 0x86 rate (Note 1) Data Transferred from the TMPM333FDFG/FYFG/ FWFG to the Controller − For I/O Interface mode: 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode -Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode -Normal acknowledge : 0x30 3 byte Command code (0x30) − 4 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x30 -Negative acknowledge : 0xX1 -Communication error : 0xX8 5 byte − Flash memory data at address 0x3F87_FF00 (FD/ FY) 0x3F81_FF00 (FW) 6 byte − Flash memory data at address 0x3F87_FF01 (FD/ FY) 0x3F81_FF01 (FW) 7 byte − Flash memory data at address 0x3F87_FF02 (FD/ FY) 0x3F81_FF02 (FW) 8 byte − Flash memory data at address 0x3F87_FF03 (FD/ FY) 0x3F81_FF03 (FW) 9 byte − Product name (12-byte ASCII code) to From the 9th byte: 20 byte TMPM330FD_ _’ (FD/ FY) TMPM330FW_ _’ (FW) 21 byte − Password comparison start address (4 bytes) to From the 21st byte: 24 byte 0x04 , 0xFF, 0x87, 0x3F (FD/FY) 0x04 , 0xFF, 0x81, 0x3F (FW) 25 byte − RAM start address (4 bytes) to From the 25th byte: 28 byte 29 byte 0x00, 0x00, 0x00, 0x20 (FD/FY/FW) − Dummy data (4 bytes) to From the 29th byte: 32 byte 0x00, 0x00, 0x00, 0x00 (FD/FY/FW) 33 byte − RAM end address (4 bytes) to From the 33rd byte: 36 byte 0xFF, 0x7F, 0x00, 0x20 (FD/FY) (Note 4) 0xFF, 0x1F, 0x00, 0x20 (FW) 37 byte − Dummy data (4 bytes) to From the 37th byte: 40 byte 0x00, 0x00, 0x00, 0x00 (FD/FY/FW) 41 byte − Dummy data (4 bytes) to From the 41st byte: 44 byte 0x00, 0x00, 0x00, 0x00 (FD/FY/FW) Page 387 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG Table 15-8 Transfer Format for the Show Product Information Command Data Transferred from the Controller Byte 45 byte to the TMPM333FDFG/FYFG/FWFG − From the 45th byte: 46 byte 0x00, 0x00 (FD/FY/FW) − Flash memory start address (4 bytes) to From the 47th byte: 50 byte 51 byte Data Transferred from the TMPM333FDFG/FYFG/ FWFG to the Controller Dummy data or Fuse information (2 bytes) to 47 byte Baud rate 0x00, 0x00, 0x80, 0x3F (FD/FY/FW) − Flash memory end address (4 bytes) to From the 51st byte: 54 byte 0xFF, 0xFF, 0x87, 0x3F (FD/FY) (Note 5) 0xFF, 0xFF, 0x81, 0x3F (FW) 55 byte − Flash memory block count (2 bytes) to From the 55th byte: 56 byte 0x06, 0x00 (FD/FY) 0x04, 0x00 (FW) 57 byte to − Start address of a group of the same-size (16K) flash blocks (4 bytes) 60 byte From 57th byte: 0x00, 0x00, 0x00, 0x00 (FD/FY) 0x00, 0x00, 0x80, 0x3F (FW) 61 byte to − Size (in halfwords) of the same-size (16K) flash blocks (4 bytes) 64 byte From 61st byte: 0x00, 0x20, 0x00, 0x00 (FD/FY/FW) 65 byte − Number of flash blocks of the same size (16K) (1 byte) 0x00 (FD/FY) 0x02 (FW) 66 byte to − Start address of a group of the same-size (32K) flash blocks (4 bytes) 69 byte From 66th byte: 0x00, 0x00, 0x80, 0x3F (FD/FY) 0x00, 0x80, 0x80, 0x3F (FW) 70 byte − to Size (in halfwords) of the same-size (32K) flash blocks (4 bytes) 73 byte From 70th byte: 0x00, 0x40, 0x00, 0x00 (FD/FY/FW) 74 byte − Number of flash blocks of the same size (32K) (1 byte) 0x02 (FD/FY) 0x01 (FW) 75 byte to − Start address of a group of the same-size (64K) flash blocks (4 bytes) 78 byte From 75th byte: 0x00, 0x00, 0x81, 0x3F (FD/FY/FW) 79 byte to − Size (in halfwords) of the same-size (64K) flash blocks (4 bytes) 82 byte From 79th byte: 0x00, 0x80, 0x00, 0x00 (FD/FY/FW) Page 388 TMPM333FDFG/FYFG/FWFG Table 15-8 Transfer Format for the Show Product Information Command Data Transferred from the Controller Byte 83 byte to the TMPM333FDFG/FYFG/FWFG Baud rate − Data Transferred from the TMPM333FDFG/FYFG/ FWFG to the Controller Number of flash blocks of the same size (64K) (1 byte) 0x01 (FD/FY/FW) 84 byte − to Start address of a group of the same-size (128K) flash blocks (4 bytes) 87 byte From 84th byte: 0x00, 0x00, 0x82, 0x3F (FD/FY) 0x00, 0x00, 0x00, 0x00 (FW) 88 byte − to Size (in halfwords) of the same-size (128K) flash blocks (4 bytes) 91 byte From 88th byte: 0x00, 0x00, 0x01, 0x00 (FD/FY/FW) 92 byte − Number of flash blocks of the same size (128K) (1 byte) 0x03 (FD/FY) (Note 6) 0x00 (FW) 93 byte − Checksum value for bytes 5 ~ 92 94 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Note 3: FD/ FY/ FW in the above table denotes the TMPM333FDFG, TMPM333FYFG and TMPM333FWFG respectively. Note 4: The RAM actual end address of the TMPM333FYFG is 0x2000_3FFF. Note 5: The flash memory actual end address of the TMPM333FYFG is 0x3F83_FFFF. In addition to 256KB flash area, the TMPM333FYFG provides 128-word data/ password area (0x3F87_FF00 to 0x3F87_FF80, 1 page) for Show Product Information command. Note 6: The actual number of the TMPM333FYFG flash blocks is one. Page 389 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG 15.2.9.4 Chip Erase and Protect Bit Erase Table 15-9 Transfer Format for the Chip and Protection Bit Erase Command Data Transferred from the Controller Byte Boot ROM 1 byte to the TMPM333FDFG/FYFG/FWFG Data Transferred from the TMPM333FDFG/ FYFG/FWFG to the Controller Baud rate Serial operation mode and baud rate Desired baud For UART mode : 0x86 rate (Note 1) − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode -Normal acknowledge : 0x86 ・For I/O Interface mode -Normal acknowledge : 0x30 (The boot program aborts if the baud rate can not be set correctly.) 3 byte Command code (0x40) − 4 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x40 -Negative acknowledge : 0xX1 -Communication error : 0xX8 5 byte Chip erase command code (0x54) − 6 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x54 -Negative acknowledge : 0xX1 -Communication error : 0xX8 7 byte − ACK for the chip erase command code byte -Normal acknowledge : 0x4F -Negative acknowledge : 0x4C 8 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Page 390 TMPM333FDFG/FYFG/FWFG 15.2.10 Operation of Boot Program When Single Boot mode is selected, the boot program is automatically executed on startup. The boot program offers these four commands, of which the details are provided on the following subsections. 1. RAM Transfer command The RAM Transfer command stores program code transferred from a host controller to the on-chip RAM and executes the program once the transfer is successfully completed. The user program RAM space can be assigned to the range from 0x2000_0400 to the end address of RAM, whereas the boot program area (0x2000_0000 ~ 0x2000_03FF) is unavailable. The user program starts at the assigned RAM address. The RAM Transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. The programming routine must utilize the flash memory command sequences described in Section 15.3. Before initiating a transfer, the RAM Transfer command verifies a password sequence coming from the controller against that stored in the flash memory. Note: If a password is set to 0xFF (erased data), it is difficult to protect data securely due to an easy-to-guess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. 2. Show Flash Memory SUM command The Show Flash Memory SUM command adds the entire contents of the flash memory together. The boot program does not provide a command to read out the contents of the flash memory. Instead, the Flash Memory SUM command can be used for software revision management. 3. Show Product Information command The Show Product Information command provides the product name, on-chip memory configuration and the like. This command also reads out the contents of the flash memory locations at addresses shown below. In addition to the Show Flash Memory Sum command, these locations can be used for software revision management. Area Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG 0x3F87_FF00 to 0x3F87_FF03 0x3F81_FF00 to 0x3F81_FF03 4. Chip and Protection Bit Erase command This command erases the entire area of the flash memory automatically without verifying a password. All the blocks in the memory cell and their protection conditions are erased even when any of the blocks are prohibited from writing and erasing. When the command is completed, the FCSECBIT bit is set to "1". This command serves to recover boot programming operation when a user forgets the password. Therefore password verification is not executed. Page 391 15. 15.2 Flash Memory Operation Operation Mode 15.2.10.1 TMPM333FDFG/FYFG/FWFG RAM Transfer Command See Table 15-6 for the transfer format of this command. 1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed description of how the serial operation mode is determined, see "15.2.10.6 Determination of a Serial Operation Mode" described later. If it is determined as UART mode, the boot program then checks if the SIO0 is programmable to the baud rate at which the 1st byte was transferred. During the first-byte interval, the RXE bit in the SC0MOD register is cleared. ・ To communicate in UART mode Send, from the controller to the target board, 0x86 in UART data format at the desired baud rate. If the serial operation mode is determined as UART, then the boot program checks if the SIO0 can be programmed to the baud rate at which the first byte was transferred. If that baud rate is not possible, the boot program aborts, disabling any subsequent communications. ・ To communicate in I/O Interface mode Send, from the controller to the target board, 0x30 in I/O Interface data format at 1/16 of the desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent bytes at a rate equal to the desired baud rate. In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port in monitoring its logic transitions. If the baud rate of the incoming data is high or the chip’s operating frequency is high, the CPU may not be able to keep up with the speed of logic transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the boot program does not check the receive error flag; thus there is no such thing as error acknowledge (bit 3, 0x08). 2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. The boot program echoes back the first byte: 0x86 for UART mode and 0x30 for I/ O Interface mode. ・ UART mode If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the boot program programs the SC0BRCR and sends back 0x86 to the controller as an acknowledge. If the SIO0 is not programmable at that baud rate, the boot program simply aborts with no error indication. Following the 1st byte, the controller should allow for a time-out period of five seconds. If it does not receive 0x86 within the allowed time-out period, the controller should give up the communication. The boot program sets the RXE bit in the SC0MOD0 register to enable reception ("1") before loading the SIO transmit buffer with 0x86. ・ I/O Interface mode The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O Interface mode (clocked by the rising edge of SCLK0), writes 0x30 to the SC0BUF. Then, the SIO0 waits for the SCLK0 signal to come from the controller. Following the transmission of the 1st byte, the controller should send the SCLK clock to the target board after a certain idle time (several microseconds). This must be done at 1/16 the desire baud rate. If the 2nd byte, which is from the target board to the controller, is 0x30, then the controller should take it as a go-ahead. The controller must then deliver the 3rd byte to the target board at a rate equal to the desired baud rate. The boot program sets the RXE bit in the SC0MOD register to enable reception before loading the SIO transmit buffer with 0x30. 3. The 3rd byte transmitted from the controller to the target board is a command. The code for the RAM Transfer command is 0x10. 4. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the state Page 392 TMPM333FDFG/FYFG/FWFG in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 15-4, the boot program echoes it back to the controller. When the RAM Transfer command was received, the boot program echoes back a value of 0x10 and then branches to the RAM Transfer routine. Once this branch is taken, password verification is done. Password verification is detailed in a later section "Password". If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte password. Each byte is compared to the contents of following addresses in the flash memory. The verification is started with the 5th byte and the smallest address in the designated area. If the password verification fails, the RAM Transfer routine sets the password error flag. Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG Area 0x3F87_FF04 to 0x3F87_FF0F 0x3F81_FF04 to 0x3F81_FF0F 6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in a later section "Checksum Calculation". 7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th bytes. If there was a receive error, the boot program sends back 0x18 (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 5th to 16th bytes must result in 0x00 (with the carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. Finally, the RAM Transfer routine examines the result of the password verification. The following two cases are treated as a password error. In these cases, the RAM Transfer routine sends back 0x11 (bit 0) to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ・ Irrespective of the result of the password comparison, all the 12 bytes of a password in the flash memory are the same value other than 0xFF. ・ Not the entire password bytes transmitted from the controller matched those contained in the flash memory. When all the above verification has been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the start address of the RAM region where subsequent data (e.g., a flash programming routine) should be stored. The 19th byte corresponds to bits 31.24 of the address and the 22nd byte corresponds to bits 7.0 of the address. Page 393 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG 9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate the number of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte corresponds to bits 15.8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7.0 of the number of bytes. 10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add all these bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in a later section "Checksum Calculation". 11. The 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer routine sends back 0x18 and returns to the command wait state (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 19th to 25th bytes must result in 0x00 (with the carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ・ The RAM storage start address must be within the range of 0x2000_0400 to the end address of RAM. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMPM333FDFG/ FYFG/FWFG. Storage begins at the address specified by the 19th.22nd bytes and continues for the number of bytes specified by the 23rd.24th bytes. 13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in a later section "Checksum Calculation". 14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes. First, the RAM Transfer routine checks for a receive error in the 27th to (m+1) th bytes. If there was a receive error, the RAM Transfer routine sends back 0x18 (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 0x11 (bit 0) to the controller and returns to the command wait state (i.e., the 3rd byte) again. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes. 15.2.10.2 Show Flash Memory SUM Command See Table 15-7 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. Page 394 TMPM333FDFG/FYFG/FWFG 2. The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Flash Memory Sum command is 0x20. 3. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 15-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 0x20 and then branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the command wait state (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. The Show Flash Memory Sum routine adds all the bytes of the flash memory together. The 5th and 6th bytes, transmitted from the target board to the controller, indicate the upper and lower bytes of this total sum, respectively. For details on sum calculation, see a later section "15.2.10.8 Calculation of the Show Flash Memory Sum Command". 5. The 7th byte is a checksum value for the 5th and 6th bytes. To calculate the checksum value, add the 5th and 6th bytes together, drop the carry and take the two’s complement of the sum. Transmit this checksum value from the controller to the target board. 6. The 8th byte is the next command code. 15.2.10.3 Show Product Information Command See Table 15-8 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. 2. The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 0x30. 3. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 15-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 0x30 and then branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. The 5th to 8th bytes, transmitted from the target board to the controller, are the data read from addresses shown below in the flash memory. Software version management is possible by storing a software ID in these locations. Area Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG 0x3F87_FF00 to 0x3F87_FF03 0x3F81_FF00 to 0x3F81_FF03 Page 395 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG 5. The 9th to 20th bytes, transmitted from the target board to the controller, indicate the product name as shown below (where [ ] is a space) in ASCII code. Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG Code T, M, P, M, 3, 3, 0, F, D, _, [ ], _ T, M, P, M, 3, 3, 0, F, W, _, [ ], _ 6. The 21st to 24th bytes, transmitted from the target board to the controller, indicate the start address of the flash memory area containing the password. Each product has own start address shown below. Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG Address 0x04, 0xFF,0x 87, 0x3F 0x04, 0xFF,0x 81, 0x3F 7. The 25th to 28th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip RAM, i.e., 0x00, 0x00, 0x00, 0x20. 8. The 29th to 32nd bytes, transmitted from the target board to the controller, are dummy data (0x00, 0x00, 0x00 and 0x00). 9. The 33rd to 36th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip RAM. Each product has own end address shown below. Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG Note: Address 0xFF, 0x7F, 0x00, 0x20 0xFF, 0x1F, 0x00, 0x20 The RAM actual end address of the TMPM333FYFG is 0x2000_3FFF. 10. The 37th to 40th bytes, transmitted from the target board to the controller, are 0x00, 0x00, 0x00 and 0x00. The 41st to 44th bytes, transmitted from the target board to the controller, are 0x00, 0x00, 0x00 and 0x00. 11. The 45th and 46th bytes transmitted are 0x00, 0x00. 12. The 47th to 50th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip flash memory, are 0x00, 0x00, 0x80, and 0x3F. 13. The 51st to 54th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip flash memory. Each product has own end address shown below. Address Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG Note: 0xFF, 0xFF, 0x87, 0x3F 0xFF, 0xFF, 0x81, 0x3F The flash memory actual end address of the TMPM333FYFG is 0x3F83_FFFF. In addition to 256KB flash area, the TMPM333FYFG provides 128-word data area (0x3F87_FF00 . 0x3F87_FF80, 1 page) for Show Product Information command and the password area. 14. The 55th to 56th bytes, transmitted from the target board to the controller, indicate the Page 396 TMPM333FDFG/FYFG/FWFG number of flash blocks available. Each product transmits own number shown below. Product name Number of flash blocks TMPM333FDFG 0x06, 0x00 TMPM333FYFG 0x06, 0x00 TMPM333FWFG 0x04, 0x00 15. The 57th to 83rd bytes, transmitted from the target board to the controller, contain information about the flash blocks. Flash blocks of the same size are treated as a group. Information about the flash blocks indicate the start address of a group, the size of the blocks in that group (in halfwords) and the number of the blocks in that group. The 57th to 65th bytes are the information about the 16-kbyte blocks. The 66th to 74th bytes are the information about the 32-kbyte blocks. The 75th to 83rd bytes are the information about the 64-kbyte blocks. The 84th to 92nd bytes are the information about the 128-kbyte blocks. See Table 15-8 for the values of bytes transmitted. 16. The 66th byte, transmitted from the target board to the controller, is a checksum value for the 5th to 92nd bytes. The checksum value is calculated by adding all these bytes together, dropping the carry and taking the two’s complement of the total sum. 17. The 94th byte is the next command code. Page 397 15. 15.2 Flash Memory Operation Operation Mode 15.2.10.4 TMPM333FDFG/FYFG/FWFG Chip and Protection Bit Erase Command See Table 15-9 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. 2. From the Controller to the TMPM333FDFG/FYFG/FWFG The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 0x40. 3. From the TMPM333FDFG/FYFG/FWFG to the Controller The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. If the 3rd byte is equal to any of the command codes listed in Table 15-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 0x40. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. From the Controller to the TMPM333FDFG/FYFG/FWFG The 5th byte, transmitted from the target board to the controller, is the Chip Erase Enable command code (0x54). 5. From the TMPM333FDFG/FYFG/FWFG to the Controller The 6th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. If the 5th byte is equal to any of the command codes to enable erasing, the boot program echoes it back to the controller. When the Chip and Protection Erase command was received, the boot program echoes back a value of 0x54 and then branches to the Chip Erase routine. If the 5th byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 6. From the TMPM333FDFG/FYFG/FWFG to the Controller The 7th byte indicates whether the Chip Erase command is normally completed or not. At normal completion, completion code (0x4F) is sent. When an error was detected, error code (0x4C) is sent. 7. The 9th byte is the next command code. Page 398 TMPM333FDFG/FYFG/FWFG 15.2.10.5 Acknowledge Responses The boot program represents processing states with specific codes. Table 15-10 to Table 15-13 show the values of possible acknowledge responses to the received data. The upper four bits of the acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1 and bit 2 are always "0". Receive error checking is not done in I/O Interface mode. Table 15-10 ACK Response to the Serial Operation Mode Byte Return Value Meaning 0x86 The SIO can be configured to operate in UART mode. (See Note) 0x30 The SIO can be configured to operate in I/O Interface mode. Note:If the serial operation mode is determined as UART, the boot program checks if the SIO can be programmed to the baud rate at which the operation mode byte was transferred. If that baud rate is not possible, the boot program aborts, without sending back any response. Table 15-11 ACK Response to the Command Byte Return Value 0x?8 (See Note) 0x?1 (See Note) Meaning A receive error occurred while getting a command code. An undefined command code was received. (Reception was completed normally.) 0x10 The RAM Transfer command was received. 0x20 The Show Flash Memory Sum command was received. 0x30 The Show Product Information command was received. 0x40 The Chip Erase command was received. Note:The upper four bits of the ACK response are the same as those of the previous command code. Table 15-12 ACK Response to the Checksum Byte Return Value 0xN8 (See Note) 0xN1 (See Note) 0xN0 (See Note) Meaning A receive error occurred. A checksum or password error occurred. The checksum was correct. Note:The upper four bits of the ACK response are the same as those of the operation command code. It is 1 (N ; RAM transfer command data [7:4] ) when password error occurs. Table 15-13 ACK Response to Chip and Protection Bit Erase Byte Return Value Meaning 0x54 The Chip Erase enabling command was received. 0x4F The Chip Erase command was completed. 0x4C The Chip Erase command was abnormally completed. Page 399 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG 15.2.10.6 Determination of a Serial Operation Mode The first byte from the controller determines the serial operation mode. To use UART mode for communications between the controller and the target board, the controller must first send a value of 0x86 at a desired baud rate to the target board. To use I/O Interface mode, the controller must send a value of 0x30 at 1/16 the desired baud rate. Figure 15-4 shows the waveforms for the first byte. Start Point A bit 0 bit 1 Point B bit 2 bit 3 Point C bit 4 bit 5 bit 6 bit 7 Point D Stop UART (0x86) tAB bit 0 Point A bit 1 tCD bit 2 bit 3 bit 4 Point B bit 5 bit 6 Point C bit 7 Point D I/O Interface (0x30) tCD tAB Figure 15-4 Serial Operation Mode Byte After RESET is released, the boot program monitors the first serial byte from the controller, with the SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Figure 15-5 shows a flowchart describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot program captures timer counts each time a logic transition occurs in the first serial byte. Consequently,the calculated tAB, tAC and tAD intervals are bound to have slight errors. If the transfer goes at a high baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive pin. In particular, I/O Interface mode is more prone to this problem since its baud rate is generally much higher than that for UART mode. To avoid such a situation, the controller should send the first serial byte at 1/16 the desired baud rate. The flowchart in Figure 15-5 shows how the boot program distinguishes between UART and I/O Interface modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is determined as UART mode. If the length of tAB is greater than the length of tCD, the serial operation mode is determined as I/O Interface mode. Bear in mind that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. This becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. To prevent this problem, reset UART mode within the programming routine. For example, the serial operation mode may be determined to be I/O Interface mode when the intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should allow for a time-out period within which it expects to receive an echo-back (0x86) from the target board. The controller should give up the communication if it fails to get that echo-back within the allowed time. When I/O Interface mode is utilized, once the first serial byte has been transmitted, the controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowledge response is not 0x30, the controller should give up further communications. When the intended mode is I/O interface mode, the first byte does not have to be 0x30 as long as tAB is greater than tCD as shown above. 0x91, 0xA1 or 0xB1 can be sent as the first byte code to determine the falling edges of Point A and Point C and the rising edges of Point B and Point D. If tAB is greater than tCD and SIO is selected by the resolution of the operation mode determination, the second byte code is 0x30 even though the transmitted code on the first byte is not 0x30 (The first byte code to determine I/O interface mode is described as 0x30). Page 400 TMPM333FDFG/FYFG/FWFG Start Initialize TMRB0 Prescaler is on.(source clock:φT0) Point A High-to-low transition on serial receive pin? YES TMRB0 starts counting up Point B Low-to-high transition on serial receive pin? YES Software-capture and save timer value (tAB) Point C High-to-low transition on serial receive pin? YES Software-capture and save timer value (tAC) Point D Low-to-high transition on serial receive pin? YES Software-capture and save timer value (tAD) 16-bit Timer 0 stops counting YES WAC Ӎ tAD? Make backup copy of tAD value Done Stop operation (infinite loop waiting for RESET) Figure 15-5 Serial Operation Mode Byte Reception Flowchart Page 401 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG Start tCD ← tAD  tAC YES WAB > tCD? UART mode I/O interface mode Figure 15-6 Serial Operation Mode Determination Flowchart 15.2.10.7 Password The RAM Transfer command (0x10) causes the boot program to perform password verification. Following an echo-back of the command code, the boot program verifies the contents of the 12-byte password area within the flash memory. The following table shows the password area of each product. Product name TMPM333FDFG TMPM333FYFG TMPM333FWFG Area 0x3F87_FF04 to 0x3F87_FF0F 0x3F81_FF04 to 0x3F81_FF0F Note:If a password is set to 0xFF (erased data area), it is difficult to protect data securely due to an easy-to-guess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. If all these address locations contain the same bytes of data other than 0xFF, a password area error occurs as shown in Figure 15-7. In this case, the boot program returns an error acknowledge (0x11) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all 0xFFs. The password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. All of the 12 bytes must match to pass the password verification. Otherwise, a password error occurs, which causes the boot program to reply an error acknowledge in response to the checksum byte (the 17th byte). The password verification is performed even if the security function is enabled. Page 402 TMPM333FDFG/FYFG/FWFG Start Are all bytes the same? YES Are all bytes equal to FFH? YES Password area error Password area is normal. Figure 15-7 Password Area Verification Flowchart Page 403 15. 15.2 Flash Memory Operation Operation Mode TMPM333FDFG/FYFG/FWFG 15.2.10.8 Calculation of the Show Flash Memory Sum Command The result of the sum calculation "byte + byte + byte + ・・・" is responded by a word quantity. The Show Flash Memory Sum command adds all 512 Kbytes of the flash memory together and provides the total sum as a halfword quantity. The sum is sent to the controller, with the upper eight bits first, followed by the lower eight bits. Note:In the TMP333FYFG, the range from 256KB through the password area and from the password area through 0x007_FFFF area are calculated as "0xFF". Example) 0xA1 0xB2 0xC3 0xD4 15.2.10.9 For the interest of simplicity, assume the depth of the flash memory is four locations. Then the sum of the four bytes is calculated as: 0xA1 + 0xB2 + 0xC3 + 0xD4 = 0x02EA Hence, 0x02 is first sent to the controller, followed by 0xEA. Checksum Calculation The checksum byte for a series of bytes of data is calculated by adding the bytes together, dropping the carries, and taking the two’s complement of the total sum. The Show Flash Memory Sum command and the Show Product Information command perform the checksum calculation. The controller must perform the same checksum operation in transmitting checksum bytes. Example) Assume the Show Flash Memory Sum command provides the upper and lower bytes of the sum as 0xE5 and 0xF6. To calculate the checksum for a series of 0xE5 and 0xF6: Add the bytes together 0xE5 + 0xF6 = 0x1DB Take the two’s complement of the sum, and that is the checksum byte. 0 − 0xDB = 0x25 Page 404 TMPM333FDFG/FYFG/FWFG 15.2.11 General Boot Program Flowchart Figure 15-8 shows an overall flowchart of the boot program. Single Boot program starts Initialize Get SIO operation mode  UART SIO operation mode?  Baud rate setting ? I/O interface Cannot be set Can be set Set I/O interface mode Program UART mode and baud rate ACK data← received data (0x30) ACK data← received data (0x86@UART) (Send 0x30) Normal response (Send 0x86) Normal response Stop operation Prepare to get a command ACK data← ACK data & 0xF0 Receive routine Get a command  Yes Receive error ? ACK data ← ACK data 0x08 Transmission routine (Send 0xX8:receive error No normally   RAM transfer? SUM? YES (0x10)   Show product information? YES (0x20) Chip erase? YES (0x30) YES (0x40) ACK data ← Received data (0x10) ACK data ← Received data (0x20) ACK data ← Received data (0x30) ACK data ← Received data (0x40) Transmission routine (Send 0x10: normal response) Transmission routine (Send 0x20: normal response) Transmission routine (Send 0x30: normal response) Transmission routine (Send 0x40: normal response) RAM transfer processing Show Flash Memory Sum processing Show Product Information processing Chip erase processing Command error ACK data ← Received data (0x01) Transmission routine (Send 0xX1: Command error)  Processed normally? Yes normally Jump to RAM Figure 15-8 Overall Boot Program Flowchart Page 405 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) 15.3 TMPM333FDFG/FYFG/FWFG On-board Programming of Flash Memory (Rewrite/Erase) In on-board programming, the CPU is to execute software commands for rewriting or erasing the flash memory. The rewrite/erase control program should be prepared by the user beforehand. Because the flash memory content cannot be read while it is being written or erased, it is necessary to run the rewrite/erase program from the internal RAM after shifting to the user boot mode. 15.3.1 Flash Memory Except for some functions, writing and erasing flash memory data are in accordance with the standard JEDEC commands. In writing or erasing, use 32-bit data transfer command of the CPU to enter commands to the flash memory. Once the command is entered, the actual write or erase operation is automatically performed internally. Table 15-14 Flash Memory Functions Major functions 15.3.1.1 Description Automatic page program Writes data automatically per page. Automatic chip erase Erases the entire area of the flash memory automatically. Automatic block erase Erases a selected block automatically. Protect function The write or erase operation can be individually inhibited for each block. Block Configuration (1) TMPM333FDFG User Boot Mode 0x0007_FFFF 0x0006_0000 0x0004_0000 0x0002_0000 Single Boot Mode Page Configuration 0x3F87_FFFF 128K bytes (BLOCK0) 128 ZRUGV™256 128K bytes (BLOCK1) 128 ZRUGV™256 128K bytes (BLOCK2) 128 ZRUGV™256 64K bytes (BLOCK3) 128 ZRUGV™128 32K bytes (BLOCK5) 128 ZRUGV™64 32K bytes (BLOCK4) 128 ZRUGV™64 0x3F86_0000 0x3F84_0000 0x3F82_0000 0x0001_0000 0x3F81_0000 0x0000_8000 0x3F80_8000 0x0000_0000 0x3F80_0000 Figure 15-9 Block Configuration of Flash Memory (TMPM333FDFG) Page 406 TMPM333FDFG/FYFG/FWFG (2) TMPM333FYFG User Boot Mode 0x0007_FFFF 0x0007_FE00 Single Boot Mode Page Configuration 0x3F87_FFFF 0x3F87_FE00 128 ZRUGV™1 128K bytes (BLOCK0) 0x0006_0000 0x3F86_0000 128K bytes (BLOCK1) 0x0004_0000 0x0003_FFFF 0x0002_0000 0x3F84_0000 0x3F83_FFFF 128K bytes (BLOCK2) 128 ZRUGV™256 64K bytes (BLOCK3) 128 ZRUGV™128 32K bytes (BLOCK5) 128 ZRUGV™64 32K bytes (BLOCK4) 128 ZRUGV™64 0x3F82_0000 0x0001_0000 0x3F81_0000 0x0000_8000 0x3F80_8000 0x0000_0000 0x3F80_0000 Figure 15-10 Block Configuration of Flash Memory (TMPM333FYFG) Note:In addition to 256KB flash area, the TMPM333FYFG provides 128-word data/password area (0x3F87_FE00 . 0x3F87_FFFF, 1 page) for Show Product Information command. To erase the content, execute the automatic chip erase command or assign block 0 with the automatic block erase command. (3) TMPM333FWFG User Boot Mode 0x0001_FFFF 0x0001_0000 Page Configuration Single Boot Mode 0x3F81_FFFF 64K bytes (BLOCK0) 64 ZRUGV™256 32K bytes (BLOCK1) 64 ZRUGV™128 16K bytes (BLOCK3) 64 ZRUGV™64 16K bytes (BLOCK2) 64 ZRUGV™64 0x3F81_0000 0x0000_8000 0x3F80_8000 0x0000_4000 0x3F80_4000 0x0000_0000 0x3F80_0000 Figure 15-11 Block Configuration of Flash Memory (TMPM333FWFG) Page 407 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) 15.3.1.2 TMPM333FDFG/FYFG/FWFG Basic operation This flash memory device has the following two operation modes: ・ The mode to read memory data (Read mode) ・ The mode to automatically erase or rewrite memory data (Automatic operation) Transition to the automatic mode is made by executing a command sequence while it is in the memory read mode. In the automatic operation mode, flash memory data cannot be read and any commands stored in the flash memory cannot be executed. In the automatic operation mode, any interrupt or exception generation cannot set the device to the read mode except when a hardware reset is generated. During automatic operation, be sure not to cause any exceptions other than reset and debug exceptions while a debug port is connected. Any exception generation cannot set the device to the read mode except when a hardware reset is generated. (1) Read When data is to be read, the flash memory must be set to the read mode. The flash memory will be set to the read mode immediately after power is applied, when CPU reset is removed, or when an automatic operation is normally terminated. In order to return to the read mode from other modes or after an automatic operation has been abnormally terminated, either the Read/reset command (a software command to be described later) or a hardware reset is used. The device must also be in the read mode when any command written on the flash memory is to be executed. ・ Read/reset command and Read command (software reset) When ID-Read command is used, the reading operation is terminated instead of automatically returning to the read mode. In this case, the Read/reset command can be used to return the flash memory to the read mode. Also, when a command that has not been completely written has to be canceled, the Read/reset command must be used. The Read command is used to return to the read mode after executing 32-bit data transfer command to write the data "0x0000_00F0" to an arbitrary address of the flash memory. ・ With the Read/reset command, the device is returned to the read mode after completing the third bus write cycle. (2) Command write This flash memory uses the command control method. Commands are executed by executing a command sequence to the flash memory. The flash memory executes automatic operation commands according to the address and data combinations applied (refer to Command Sequence). If it is desired to cancel a command write operation already in progress or when any incorrect command sequence has been entered, the Read/reset command is to be executed. Then, the flash memory will terminate the command execution and return to the read. While commands are generally comprised of several bus cycles, the operation to apply 32-bit data transmit command to the flash memory is called "bus write cycle." The bus write cycles are to be in a specific sequential order and the flash memory will perform an automatic operation when the sequence of the bus write cycle data and address of a command write operation is in accordance with a predefined specific sequence. If any bus write cycle does not follow a predefined command write sequence, the flash memory will terminate the command execution and return to the read mode. Note 1: Command sequences are executed from outside the flash memory area. Note 2: Each bus write cycle must be sequentially executed by 32-bit data transmit command. While a command sequence is being executed, access to the flash memory is prohibited. Also, don't generate any interrupt (except debug exceptions when a debug port is connected).If such an operation is made, it can result in an unexpected read access to the flash memory and the command sequencer may not be able to correctly recognize the command. While it could cause an abnormal termination of the command sequence, it is also possible that the written command is incorrectly recognized. Page 408 TMPM333FDFG/FYFG/FWFG Note 3: For the command sequencer to recognize a command, the device must be in the read mode prior to executing the command. Be sure to check before the first bus write cycle that FCFLCS is set to "1." It is recommended to subsequently execute a Read command. Note 4: Upon issuing a command, if any address or data is incorrectly written, be sure to perform a software reset to return to the read mode again. 15.3.1.3 Reset(Hardware reset) A hardware reset is used to cancel the operational mode set by the command write operation when forcibly termination during auto programming/ erasing or abnormal termination during automatic operation. The flash memory has a reset input as the memory block and it is connected to the CPU reset signal. Therefore, when the RESET input pin of this device is set to VIL or when the CPU is reset due to any overflow of the watch dog timer, the flash memory will return to the read mode terminating any automatic operation that may be in progress. It should also be noted that applying a hardware reset during an automatic operation can result in incorrect rewriting of data. In such a case, be sure to perform the rewriting again. Refer to Section "15.2.1 Reset Operation" for CPU reset operations. After a given reset input, the CPU will read the reset vector data from the flash memory and starts operation after the reset is removed. 15.3.1.4 Commands (1) Automatic Page Programming Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is necessary to perform an erase operation. The automatic page programming function of this device writes data of each page. The TMPM333FDFG/ TMPM333FYFG contain 128 words and the TMPM333FWFG contains 64 words in a page. A 128 word block is defined by a same [31:9] address and it starts from the address [8:0] = 0x00 and ends at the address [8:0] = 0x1FF. A 64 word block is defined by a same [31:8] address and it starts from the address [7:0] = 0x00 and ends at the address [7:0] = 0xFF. This programming unit is hereafter referred to as a "page". Writing to data cells is automatically performed by an internal sequencer and no external control by the CPU is required. The state of automatic page programming (whether it is in writing operation or not) can be checked by FCFLCS [0] . Also, any new command sequence is not accepted while it is in the automatic page programming mode. If it is desired to interrupt the automatic page programming, use the hardware reset function. If the operation is stopped by a hardware reset operation, it is necessary to once erase the page and then perform the automatic page programming again because writing to the page has not been normally terminated. The automatic page programming operation is allowed only once for a page already erased. No programming can be performed twice or more times irrespective of the data cell value whether it is "1" or "0." Note that rewriting to a page that has been once written requires execution of the automatic block erase or automatic chip erase command before executing the automatic page programming command again. Note that an attempt to rewrite a page two or more times without erasing the content can cause damages to the device. No automatic verify operation is performed internally to the device. So, be sure to read the data programmed to confirm that it has been correctly written. The automatic page programming operation starts when the third bus write cycle of the command cycle is completed. On and after the fifth bus write cycle, data will be written sequentially starting from Page 409 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM333FDFG/FYFG/FWFG the next address of the address specified in the fourth bus write cycle (in the fourth bus write cycle, the page top address will be command written) (32 bits of data is input at a time). Be sure to use the 32-bit data transfer command in writing commands on and after the fourth bus cycle. In this, any 32-bit data transfer commands shall not be placed across word boundary. On and after the fifth bus write cycle, data is command written to the same page area. Even if it is desired to write the page only partially, it is required to perform the automatic page programming for the entire page. In this case, the address input for the fourth bus write cycle shall be set to the top address of the page. Be sure to perform command write operation with the input data set to "1" for the data cells not to be set to "0." For example, if the top address of a page is not to be written, set the input data of the fourth bus write cycle to 0xFFFFFFFF to command write the data. Once the third bus cycle is executed, the automatic page programming is in operation. This condition can be checked by monitoring FCFLCS. Any new command sequence is not accepted while it is in automatic page programming mode. If it is desired to stop operation, use the hardware reset function. Be careful in doing so because data cannot be written normally if the operation is interrupted. When a single page has been command written normally terminating the automatic page writing process, FCFLCS is set to "1" and it returns to the read mode. When multiple pages are to be written, it is necessary to execute the page programming command for each page because the number of pages to be written by a single execution of the automatic page program command is limited to only one page. It is not allowed for automatic page programming to process input data across pages. Data cannot be written to a protected block. When automatic programming is finished, it automatically returns to the read mode. This condition can be checked by monitoring FCFLCS . If automatic programming has failed, the flash memory is locked in the mode and will not return to the read mode. For returning to the read mode, it is necessary to execute hardware reset to reset the flash memory or the device. In this case, while writing to the address has failed, it is recommended not to use the device or not to use the block that includes the failed address. Note:Software reset becomes ineffective in bus write cycles on and after the fourth bus write cycle of the automatic page programming command. (2) Automatic chip erase The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is completed. This condition can be checked by monitoring FCFLCS . While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. Any new command sequence is not accepted while it is in an automatic chip erase operation. If it is desired to stop operation, use the hardware reset function. If the operation is forced to stop, it is necessary to perform the automatic chip erase operation again because the data erasing operation has not been normally terminated. Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic chip erase operation will not be performed and it returns to the read mode after completing the sixth bus read cycle of the command sequence. When an automatic chip erase operation is normally terminated, it automatically returns to the read mode. If an automatic chip erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. For returning to the read mode, it is necessary to execute hardware reset to reset the device. In this case, the failed block cannot be detected. It is recommended not to use the device anymore or to identify the failed block by using the block erase function for not to use the identified block anymore. Page 410 TMPM333FDFG/FYFG/FWFG (3) Automatic block erase (for each block) The automatic block erase operation starts when the sixth bus write cycle of the command cycle is completed. This status of the automatic block erase operation can be checked by monitoring FCFLCS . While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. Any new command sequence is not accepted while it is in an automatic block erase operation. If it is desired to stop operation, use the hardware reset function. In this case, it is necessary to perform the automatic block erase operation again because the data erasing operation has not been normally terminated. Also, any protected blocks cannot be erased. If an automatic block erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. In this case, execute hardware reset to reset the device. (4) Automatic programming of protection bits (for each block) This device is implemented with protection bits. This protection can be set for each block. See Table 15-18 for table of protection bit addresses. This device assigns 1 bit to 1 block as a protection bit. The applicable protection bit is specified by PBA in the seventh bus write cycle. By automatically programming the protection bits, write and/or erase functions can be inhibited (for protection) individually for each block. The protection status of each block can be checked by FCFLCS to be described later. This status of the automatic programming operation to set protection bits can be checked by monitoring FCFLCS . Any new command sequence is not accepted while automatic programming is in progress to program the protection bits. If it is desired to stop the programming operation, use the hardware reset function. In this case, it is necessary to perform the programming operation again because the protection bits may not have been correctly programmed. If all the protection bits have been programmed, all FCFLCS are set to "1" indicating that it is in the protected state. This disables subsequent writing and erasing of all blocks. Note:Software reset is ineffective in the seventh bus write cycle of the automatic protection bit programming command. FCFLCS turns to "0" after entering the seventh bus write cycle. (5) Automatic erasing of protection bits Different results will be obtained when the automatic protection bit erase command is executed depending on the status of the protection bits and the security bits. It depends on the status of FCFLCS whether all are set to "1" or not if FCSECBIT is 0x1. Be sure to check the value of FCFLCS before executing the automatic protection bit erase command. See the chapter "ROM protection" for details. Note:The TMPM333FYFG is configured with block 2 through 5. Block 0 and 1 require a programming of protection bits when using security function. ・ When all the FCFLCS are set to "1" (all the protection bits are programmed): When the automatic protection bit erase command is command written, the flash memory is automatically initialized within the device. When the seventh bus write cycle is completed,the entire area of the flash memory data cells is erased and then the protection bits are erased. This operation can be checked by monitoring FCFLCS . If the automatic operation to erase protection bits is normally terminated, FCFLCS will be set to "0x00000001".While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that it has been correctly erased. For returning to the read mode while the automatic operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to reset the device. If this is done, it is necessary to check the status of Page 411 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM333FDFG/FYFG/FWFG protection bits by FCFLCS after retuning to the read mode and perform either the automatic protection bit erase, automatic chip erase, or automatic block erase operation, as appropriate. ・ When FCFLCS include "0" (not all the protection bits are programmed): If the automatic protection bit is cleared to "0", the protection condition is canceled. With this device, protection bits can be programmed to an individual block and performed bit-erase operation in the four bits unit as shown in Table 15-19. The target bits are specified in the seventh bus write cycle.The protection status of each block can be checked by FCFLCS to be described later. This status of the programming operation for automatic protection bits can be checked by monitoring FCFLCS . When the automatic operation to erase protection bits is normally terminated, the protection bits of FCFLCS selected for erasure are set to "0". In any case, any new command sequence is not accepted while it is in an automatic operation to erase protection bits. If it is desired to stop the operation, use the hardware reset function. When the automatic operation to erase protection bits is normally terminated, it returns to the read mode. Note:The FCFLCS bit is "0" while in automatic operation and it turns to "1" when the automatic operation is terminated. (6) ID-Read Using the ID-Read command, you can obtain the type and other information on the flash memory contained in the device. The data to be loaded will be different depending on the address [15:14] of the fourth and subsequent bus write cycles (recommended input data is 0x00). On and after the fourth bus write cycle, when an arbitrary flash memory area is read, the ID value will be loaded. Once the fourth bus write cycle of an ID-Read command has passed, the device will not automatically return to the read mode. In this condition, the set of the fourth bus write cycle and ID-Read commands can be repetitively executed. For returning to the read mode, use the Read/reset command or hardware reset command. Page 412 TMPM333FDFG/FYFG/FWFG 15.3.1.5 Flash control/ status register Base Address = 0x4004_0500 Register name Address(Base+) Security bit register FCSECBIT 0x0000 - 0x0004 FCFLCS 0x0020 Reserved - 0x0024 Reserved - 0x0028 Reserved Flash control register Note:Access to the "Reserved" areas is prohibited. (1) FCFLCS (Flash control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - BLPRO5 BLPRO4 BLPRO3 BLPRO2 BLPRO1 BLPRO0 After reset 0 0 (Note2) (Note2) (Note2) (Note2) (Note2) (Note2) 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RDY/BSY After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-22 − R Read as 0. 21-16 BLPRO5 to BLPRO0 R Protection for Block5 to 0 (Note 3) 0: disabled 1: enabled Protection status bits Each of the protection bits represents the protection status of the corresponding block. When a bit is set to "1," it indicates that the block corresponding to the bit is protected. When the block is protected, data cannot be written to it. 15-1 − R Read as 0. 0 RDY/BSY R Ready/Busy (Note 1) 0: Auto operating 1:Auto operation terminated Ready/Busy flag bit The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a function bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and outputs "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0" output. By applying a hardware reset, it returns to "1." Note 1: This command must be issued in the ready state. Issuing the command in the busy state may disable both correct command transmission and further command input. To exit from the condition, execute system reset. System reset requires at least 0.5 μs regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. Note 2: The value varies depending on protection applied. Note 3: The FCFLCS[21:20] of TMPM333FWFG have no function. They are read as "0". Page 413 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) (2) bit symbol After reset TMPM333FDFG/FYFG/FWFG FCSECBIT (Security bit register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - SECBIT After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 SECBIT R/W Security bits 0:disabled 1:enabled Note:This register is initialized by cold reset. Page 414 TMPM333FDFG/FYFG/FWFG 15.3.1.6 List of Command Sequences Table 15-15 shows the addresses and the data of each command of flash memory. Bus cycles are "bus write cycles" except for the second bus cycle of the Read command, the fourth bus cycle of the Read/reset command, and the fifth bus cycle of the ID-Read command. Bus write cycles are executed by 32-bit (word) data transfer commands. (In the following table, only lower 8 bits data are shown.) See Table 15-16 for the detail of the address bit configuration. Use a value of "Addr." in the Table 15-15 for the address [15:8] of the normal command in the Table 15-16. Note:Always set "0" to the address bits [1:0] in the entire bus cycle. Table 15-15 Flash Memory Access from the Internal CPU Command sequence Read Read/Reset ID-Read Automatic page programming Automatic chip erase Auto Block erase Protection bit programming Protection bit erase First bus cycle Second bus cycle Third bus cycle Fourth bus cycle Fifth bus cycle Sixth bus cycle Seventh bus cycle Addr. Addr. Addr. Addr. Addr. Addr. Addr. Data Data Data Data Data Data Data 0xXX − − − − − − 0xF0 − − − − − − 0x54XX 0xAAXX 0x54XX RA − − − 0xAA 0x55 0xF0 RD − − − 0x54XX 0xAAXX 0x54XX IA 0xXX − − 0xAA 0x55 0x90 0x00 ID − − 0x54XX 0xAAXX 0x54XX PA PA PA PA 0xAA 0x55 0xA0 PD0 PD1 PD2 PD3 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX − 0xAA 0x55 0x80 0xAA 0x55 0x10 − 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX BA − 0xAA 0x55 0x80 0xAA 0x55 0x30 − 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA 0xAA 0x55 0x9A 0xAA 0x55 0x9A 0x9A 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA 0xAA 0x55 0x6A 0xAA 0x55 0x6A 0x6A Supplementary explanation RA: Read address RD: Read data IA: ID address ID: ID data PA: Program page address PD: Program data (32 bit data) After the fourth bus cycle, enter data in the order of the address for a page. ・ BA: Block address ・ PBA: Protection bit address ・ ・ ・ ・ ・ Page 415 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) 15.3.1.7 TMPM333FDFG/FYFG/FWFG Address bit configuration for bus write cycles Table 15-16 is used in conjunction with Table 15-15 "Flash Memory Access from the Internal CPU." Address setting can be performed according to the normal bus write cycle address configuration from the first bus cycle. "0" is recommended" in the Table 15-16 Address Bit Configuration for Bus Write Cycles can be changed as necessary. Table 15-16 Address Bit Configuration for Bus Write Cycles Address Addr Addr [18] [31:19] Addr [17] Addr [16] Addr [15] Addr [14] Addr [13:11] Addr [10] Addr [9] Addr Addr [8] [7:0] [TMPM333FDFG/FYFG/FWFG] Normal bus write cycle address configuration Normal commands Addr[1:0]="0" (fixed) Flash area "0" is recommended. Others:0 Command (recommended) ID-READ IA: ID address (Set the fourth bus write cycle address for ID-Read operation) Flash area "0" is recommended. ID address Addr[1:0]="0" (fixed) , Others:0 (recommended) [TMPM333FDFG/FYFG] BA: Block address (Set the sixth bus write cycle address for block erase operation) Block erase Block selection (Table 15-17) Addr[1:0]="0" (fixed) , Others:0 (recommended) PA: Program page address (Set the fourth bus write cycle address for page programming operation) Auto page programming Addr[1:0]="0" (fixed) Page selection Others:0 (recommended) PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure) Protection bit programming Flash area Protection bit selection (Table 15-18) Fixed to "0". Protection bit selection Addr[1:0]="0" (fixed) Others:0 (recommended) (Table 15-18) PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure) Protection bit erase Flash area Protection bit selection "0" is recommended. (Table 15-19) Addr[1:0]="0" (fixed) Others:0 (recommended) [TMPM333FWFG] BA: Block address (Set the sixth bus write cycle address for block erase operation) Block erase Block selection Addr[1:0]="0" (fixed) , Others:0 (recommended) (Table 15-17) PA: Program page address (Set the fourth bus write cycle address for page programming operation) Auto page programming Addr[1:0]="0" (fixed) Page selection Others:0 (recommended) PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming Protection bit programming Flash area Protection bit selection Fixed to "0". (Table 15-18) Protection bit selection (Table 15-18) Addr[1:0]="0" (fixed) Others:0 (recommended) PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure) Protection bit erase Flash area Protection bit selection Fixed to "0". (Table 15-19) Page 416 Addr[1:0]="0" (fixed) Others:0 (recommended) TMPM333FDFG/FYFG/FWFG As block address, specify any address in the block to be erased. Table 15-17 Block Address Table Block Address (User boot mode) Address (Single boot mode) Size (Kbyte) [TMPM333FDFG/FYFG] 4 0x0000_0000 ~ 0x0000_7FFF 0x3F80_0000 ~ 0x3F80_7FFF 32 5 0x0000_8000 ~ 0x0000_FFFF 0x3F80_0000 ~ 0x3F80_FFFF 32 3 0x0001_0000 ~ 0x0001_FFFF 0x3F81_0000 ~ 0x3F81_FFFF 64 2 0x0002_0000 ~ 0x0003_FFFF 0x3F82_0000 ~ 0x3F83_FFFF 128 1 0x0004_0000 ~ 0x0005_FFFF 0x3F84_0000 ~ 0x3F85_FFFF 128 0 0x0006_0000 ~ 0x0007_FFFF 0x3F86_8000 ~ 0x3F87_FFFF 128 [TMPM333FWFG] 2 0x0000_0000 ~ 0x0000_3FFF 0x3F80_0000 ~ 0x3F80_3FFF 16 3 0x0000_4000 ~ 0x0000_7FFF 0x3F80_4000 ~ 0x3F80_7FFF 16 1 0x0000_8000 ~ 0x0000_FFFF 0x3F80_8000 ~ 0x3F80_FFFF 32 0 0x0001_0000 ~ 0x0001_FFFF 0x3F81_0000 ~ 0x3F81_FFFF 64 Note:As for the addresses from the first to the fifth bus cycles, specify the upper addresses of the blocks to be erased. Table 15-18 Protection Bit Programming Address Table The seventh bus write cycle address Block Protection bit Address [18] Address [17] Address [16] Address [15:11] Address [10] Address [9] Address [8] [TMPM333FDFG/FYFG] Block0 0 0 1 0 0 Block1 0 0 1 0 1 Block2 0 0 1 1 0 Block3 0 0 1 1 1 Block4 0 1 0 0 0 Block5 0 1 0 0 1 Fixed to "0". "0" is recommended. [TMPM333FWFG] Block0 0 0 Block1 0 0 Block2 0 0 Block3 0 0 Fixed to "0". Page 417 0 0 0 1 1 0 1 1 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM333FDFG/FYFG/FWFG Table 15-19 Protection Bit Erase Address Table Block Protection bit Block0 to 3 Block4 to 5 The seventh bus write cycle address [18:17] Address[18] Address[17] 0 0 0 1 Note:The protection bit erase command cannot erase by individual block. Table 15-20 The ID-Read command's fourth bus write cycle ID address (IA) and the data to be read by the following 32-bit data transfer command (ID) IA[15:14] ID[7:0] Code 00b 0x98 Manufacturer code 01b 0x5A Device code Reserved − 10b 0x12 (TMPM333FDFG) 11b 0x12 (TMPM333FYFG) 0x11 (TMPM333FWFG) Page 418 Macro code TMPM333FDFG/FYFG/FWFG 15.3.1.8 Flowchart Start Automatic page programming command sequence (see the flowchart shown below) Address = Address + 0x200 (set by a page) NO The address of the last page? YES Automatic page programming Automatic Page Programming Command Sequence (Address/ Command) 0x54xx/0xAA 0xAAxx/0x55 0x54xx/0xA0 Programming address (page address)/ Programming data (32 bit data) Figure 15-12 Automatic Programming Note:Command sequence is executed by 0x54xx or 0x55xx. Page 419 15. 15.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM333FDFG/FYFG/FWFG Start Automatic chip erase command sequence (see the flowchart shown below) Automatic chip erase completed Automatic chip erase command sequence (address/ command) Automatic block/ multi-block erase command sequence (address/ command) 0x54xx/0xAA 0x54xx/0xAA 0xAAxx/0x55 0xAAxx/0x55 0x54xx/0x80 0x54xx/0x80 0x54xx/0xAA 0x54xx/0xAA 0xAAxx/0x55 0xAAxx/0x55 0x54xx/0x10 Block address/0x30 Figure 15-13 Automatic Erase Note:Command sequence is executed by 0x54xx or 0x55xx. Page 420 TMPM333FDFG/FYFG/FWFG 16. ROM protection 16.1 Outline The TMPM333FDFG/FYFG/FWFG offers two kinds of ROM protection/ security functions. One is a write/ erase-protection function for the internal flash ROM data. The other is a security function that restricts internal flash ROM data readout and debugging. 16.2 Future 16.2.1 Write/ erase-protection function The write/ erase-protection function enables the internal flash to prohibit the writing and erasing operation for each block. To activate the function, write "1" to the corresponding bits to a block to protect. Writing "0" to the bits cancels the protection. The protection settings of the bits can be monitored by the FCFLCS bit. See the chapter "Flash" for programming details. 16.2.2 Security function The security function restricts flash ROM data readout and debugging. This function is available under the conditions shown below. 1. The FCSECBIT bit is set to"1". 2. All the protection bits (the FCFLCS bits) used for the write/erase-protection function are set to "1". Note:The FCSECBIT bit is set to "1" at a power-on reset right after power-on. Note:The TMPM333FYFG is configured with block 2 through 5. Block 0 and 1 require a programming of protection bits when using security function. Table 16-1 shows details of the restrictions by the security function. Table 16-1 Restrictions by the security function Item Details 1) ROM data readout Data can be read from CPU. 2) Debug port Communication of JTAG/SW and trace are prohibited Writing a command to the flash memory is prohibited. 3) Command for flash memory An attempt to erase the contents in the bits used for the write/eraseprotection erases all the protection bits. Page 421 16. 16.3 ROM protection Register 16.3 TMPM333FDFG/FYFG/FWFG Register Base Address = 0x4004_0500 Register name Address(Base+) Security bit register Reserved Flash control register FCSECBIT 0x0000 - 0x0004 FCFLCS 0x0020 Reserved - 0x0024 Reserved - 0x0028 Note:Access to the "Reserved" areas is prohibited. Page 422 TMPM333FDFG/FYFG/FWFG 16.3.1 FCFLCS (Flash control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - BLPRO5 BLPRO4 BLPRO3 BLPRO2 BLPRO1 BLPRO0 0 0 (Note2) (Note2) (Note2) (Note2) (Note2) (Note2) 15 14 13 12 11 10 9 8 bit symbol After reset bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RDY/BSY After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-22 − R Read as 0. 21-16 BLPRO5 to BLPRO0 R Protection for Block5 to 0 (Note 3) 0: disabled 1: enabled Protection status bits Each of the protection bits represents the protection status of the corresponding block. When a bit is set to "1," it indicates that the block corresponding to the bit is protected. When the block is protected, data cannot be written to it. 15-1 − R Read as 0. 0 RDY/BSY R Ready/Busy (Note 1) 0: Auto operating 1:Auto operation terminated Ready/Busy flag bit The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a function bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and outputs "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0" output. By applying a hardware reset, it returns to "1." Note 1: This command must be issued in the ready state. Issuing the command in the busy state may disable both correct command transmission and further command input. To exit from the condition, execute system reset. System reset requires at least 0.5 ms regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. Note 2: The value varies depending on protection applied. Note 3: The FCFLCS[21:20] of TMPM333FWFG have no function. They are read as "0". Page 423 16. 16.3 ROM protection Register TMPM333FDFG/FYFG/FWFG 16.3.2 FCSECBIT(Security bit register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - SECBIT After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type ã@î\ 31-1 − R Read as 0. 0 SECBIT R/W Security bit 0: Disabled 1: Enabled Note:This register is initialized only by power-on reset. Page 424 TMPM333FDFG/FYFG/FWFG 16.4 Writing and erasing 16.4.1 Protection bits Writing and erasing protection bits are available with a single chip mode, single boot mode and writer mode. Writing to the protection bits is done on block-by-block basis. Erasing of the protection bits is done by two groups of the blocks: block 0 through 3 and block 4 through 5. When the settings for all the blocks are "1", erasing must be done after setting the FCSECBIT bit to "0". Setting "1" at that situation erases all the protection bits. To write and erase the protection bits, command sequence is used. See the capter "Flash" for details 16.4.2 Security bit The FCSECBIT bit that activates security function is set to "1" at a power-on reset right after power-on. The bit is rewritten by the following procedure. 1. Write the code 0xa74a9d23 to FCSECBIT register. 2. Write data within 16 clocks from the above.1. Note:The above procedure is enabled only when using 32-bit data transfer command. Page 425 16. 16.4 ROM protection Writing and erasing TMPM333FDFG/FYFG/FWFG Page 426 TMPM333FDFG/FYFG/FWFG 17. Electrical Characteristics 17.1 Absolute Maximum Ratings Parameter Supply voltage Input voltage Low-level output current Per pin Symbol Rating DVDD3 −0.3 to 3.9 AVDD3 −0.3 to 3.9 RVDD3 −0.3 to 3.9 VIN −0.3 to VDD + 0.3 IOL 5 Total ΣIOL 50 High-level Per pin IOH −5 output current Total Power consumption (Ta = 85 °C) Soldering temperature(10 s) Storage temperature Operating Temperature Except during Flash W/E Unit V V mA ΣIOH -50 PD 600 mW TSOLDER 260 °C TSTG −40 to 125 °C TOPR During Flash W/E −20 to 85 °C 0 to 70 Note:Absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no Absolute maximum rating value is exceeded with respect to current, voltage, power consumption, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. Page 427 17. 17.2 Electrical Characteristics DC Electrical Characteristics (1/3) 17.2 TMPM333FDFG/FYFG/FWFG DC Electrical Characteristics (1/3) Ta = −20 to 85 °C Parameter Supply voltage Low-level input voltage Symbol Condition DVDD3 = AVDD3 = RVDD3 DVDD3 fOSC = 8 to 10 MHz (Note2) AVDD3 fsys = 1 to 40 MHz DVSS = AVSS = 0V RVDD3 fs = 30 to 34 kHz PC0 to 3, PD4 to 7 VIL1 PD0 to 3 VIL2 PA2 to 7, PB0, PB3 to 7, PE0, PE4, PF0, PG7, PI0 to 5, PJ4 to 5,PK1 to 2 VIL3 PA0 to 1, PB1 to 2, PE1 to 3, PE5 to 6, PF1 to 7, PG0 to 6, PH0 to 7, PI6 to 7, PJ0 to 3, PJ6 to 7 Min Typ. (Note 1) Max Unit 2.7 − 3.6 V 0.3 AVDD3 2.7 V ≤ AVDD3 ≤ 3.6 V 0.2 AVDD3 0.3 DVDD3 −0.3 VIL4 − 2.7 V ≤ DVDD3 ≤ 3.6 V V 0.2 DVDD3 RESET, NMI, MODE High-level input voltage PK0 VIL5 X1 VIL6 PC0 to 3, PD4 to 7 VIH1 PD0 to 3 VIH2 PA2 to 7, PB0, PB3 to 7, PE0, PE4, PF0, PG7, PI0 to 5, PJ4 to 5,PK1 to 2 VIH3 PA0 to 1, PB1 to 2, PE1 to 3, PE5 to 6, PF1 to 7, PG0 to 6, PH0 to 7, PI6 to 7, PJ0 to 3, PJ6 to 7 0.1 DVDD3 2.7 V ≤ AVDD3 ≤ 3.6 V 0.7 AVDD3 AVDD3 + 0.3 0.8 AVDD3 0.7 DVDD3 − VIH4 2.7 V ≤ DVDD3 ≤ 3.6 V DVDD3 + 0.3 V 0.8 DVDD3 RESET, NMI, MODE PK0 VIH5 X1 VIH6 3.6 0.9 DVDD3 DVDD3 + 0.3 Low-level output voltage VOL IOL = 2 mA DVDD3 ≥ 2.7 V − − 0.4 V High-level output voltage VOH IOH = −2 mA DVDD3 ≥ 2.7 V 2.4 − − V − 0.02 ±5 Input leakage current Output leakage current Except PK0 ILI1 PK0 ILI2 Except PK0 ILO1 PK0 ILO2 Pull-up resister at Reset 0.0 ≤ VIN ≤ DVDD3 0.0 ≤ VIN ≤ AVDD3 0.0 V ≤ VIN ≤ 3.6 V μA 0.2 ≤ VIN ≤ DVDD3 − 0.2 0.2 ≤ VIN ≤ AVDD3 − 0.2 − 0.05 ±10 0.2 V ≤ VIN ≤ 3.4 V RRST DVDD3 = 2.7 V to 3.6 V 30 50 150 kΩ Hysteresis voltage VTH 2.7 V ≤ DVDD3 ≤ 3.6 V 0.3 0.6 − V Programmable pull-up/pull-down resistor PKH DVDD3 = 2.7 V to 3.6 V − 50 150 kΩ Pin capacitance (Except power supply pins) CIO fc = 1 MHz − − 10 pF Note 1: Ta = 25 °C, DVDD3 = RVDD3 = AVDD3 = 3.3 V, unless otherwise noted. Note 2: The same voltage must be supplied to DVDD3, AVDD3, and RVDD3. Page 428 TMPM333FDFG/FYFG/FWFG 17.3 DC Electrical Characteristics (2/3) DVDD3 = AVDD3 = RVDD3 = 2.7 V to 3.6 V, Ta = −20 to 85 °C Parameter Symbol IOL Condition Min Typ. Max Unit − − 2 mA − − 18 mA Total − − 35 mA Per pin − − -2 mA − − -18 mA − − -35 mA Per pin Per group GrL1 = 6 to 12,89pin GrL2 = 15 to 37pin GrL3 = 15=61pin GrL4 = 15 to 37pin ΣIOL2 IOH Per group GrL1 = 6 to 12,89pin GrL2 = 15 to 37pin GrL3 = 15=61pin GrL4 = 15 to 37pin ΣIOH2 Total Note:The same voltage must be supplied to DVDD3, AVDD3, and RVDD3. Page 429 17. 17.4 Electrical Characteristics DC Electrical Characteristics (3/3) 17.4 TMPM333FDFG/FYFG/FWFG DC Electrical Characteristics (3/3) 17.4.1 TMPM333FDFG/TMPM333FYFG DVDD3 = AVDD3 = RVDD3 = 2.7 V to 3.6 V, Ta = −20 to 85 °C Parameter Symbol Condition Min Typ. (Note1) Max 32 42 NORMAL (Note2) Gear 1/1 fsys = 40 MHz − IDLE (Note3) (fOSC = 10 MHz) − 8 13 − 2.5 6 − 55 950 − 55 900 IDD SLOW SLEEP STOP fs = 32.768 kHz − Unit mA μA Note 1: Ta = 25 °C, DVDD3 = AVDD3 = RVDD3 = 3.3 V, unless otherwise noted. Note 2: IDD NORMAL: Measured with the dhrystone ver. 2.1 operated in FLASH. All functions operates excluding A/D. Note 3: IDD IDLE: Measured with all functions stopped.The currents flow through DVDD3, AVDD3 and RVDD3 are included. 17.4.2 TMPM333FWFG DVDD3 = AVDD3 = RVDD3 = 2.7 V to 3.6 V, Ta = −20 to 85 °C Parameter Symbol Condition Min Typ. (Note1) Max NORMAL (Note2) Gear 1/1 fsys = 40 MHz − 26 32 IDLE (Note3) (fOSC = 10 MHz) − 8 12.5 − 2.5 5.5 − 55 900 − 45 850 SLOW SLEEP STOP IDD fs = 32.768 kHz − Unit mA μA Note 1: Ta = 25 °C, DVDD3 = AVDD3 = RVDD3 = 3.3 V, unless otherwise noted. Note 2: IDD NORMAL: Measured with the dhrystone ver. 2.1 operated in FLASH. All functions operates excluding A/D Note 3: IDD IDLE: Measured with all functions stopped.The currents flow through DVDD3, AVDD3 and RVDD3 are included. Page 430 TMPM333FDFG/FYFG/FWFG 17.5 10-bit ADC Electrical Characteristics DVDD3 = AVDD3 = RVDD3 = VREFH = 2.7 V to 3.6 V AVSS = DVSS, Ta = −20 to 85 °C Parameter Analog reference voltage(+) Symbol Condition Min Typ. Max Unit VREFH − 2.7 3.3 3.6 V Analog input voltage VAIN − AVSS − VREFH V Power supply current of analog reference voltage AD conversion − 2.5 5.5 mA IREF − ±0.02 ±5 μA Supply current AD conversion − − 3 mA − ±2 ±3 − ±1 ±2 − ±2 ±4 − ±2 ±4 − ±2 ±3 − ±1 ±2 − ±2 ±4 − ±2 ±4 − ±2 ±3 − ±1 ±2 − ±2 ±4 − ±2 ±4 Non-AD conversion − DVSS = AVSS Except IREF INL error DNL error Offset error AIN resistance ≤ 600 Ω − AIN load capacitance ≤ 30 pF Conversion time ≥ 1.15 μs Full-scale error INL error DNL error Offset error AIN resistance ≤ 600 Ω − AIN load capacitance ≤ 0.1 μF Conversion time ≥ 1.15 μs Full-scale error INL error DNL error Offset error AIN resistance ≤ 10 kΩ − AIN load capacitance ≥ 0.1 μF Conversion time ≥ 2.30 μs Full-scale error Note:1LSB = (VREFH − AVSS)/1024 [V] Note:Peripheral functions are disable. Page 431 LSB 17. 17.6 Electrical Characteristics AC Electrical Characteristics 17.6 TMPM333FDFG/FYFG/FWFG AC Electrical Characteristics 17.6.1 AC measurement condition The AC characteristics data of this chapter is measured under the following conditions unless otherwise noted ・ Output levels: High = 0.8 × DVDD3, Low = 0.2 × DVDD3 ・ Input levels: Refer to low-level input voltage and high-level input voltage in "DC Electrical Characteristics". ・ Load capacity: CL = 30pF 17.6.2 Serial Channel (SIO/UART) 17.6.2.1 I/O Interface mode In the table below, the letter x represents the SIO operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. (1) SCLK input mode Parameter Symbol Equation 40 MHz Min Max Min Max SCLK Clock High width (input) tSCH 3x − 75 − SCLK Clock Low width (input) tSCL 3x − 75 − SCLK cycle tSCY tSCH + tSCL − 150 − Output Data ← SCLK rise or fall (Note 1) SCLK rise → Output Data hold or fall(Note1) Valid Data input ← SCLK rise or fall(Note1) SCLK rise → Input Data hold or fall(Note1) −45 tOSS tSCY/2 − 3x− 45 − tOHS tSCY/2 − 75 − tSRD 30 − 30 − tHSR x + 30 − 55 − (Note2) Unit − ns Note 1: SCLK rise or fall …Measured relative to the programmed active edge of SCLK. Note 2: Keep this value positive by adjusting SCLK cycle. Page 432 TMPM333FDFG/FYFG/FWFG (2) SCLK output mode Parameter Symbol Equation 40 MHz Min Max Min Max tSCY 4x − 100 − Output Data ← SCLK rise tOSS tSCY/2 − 20 − 30 − SCLK rise → Output hold Data hold tOHS tSCY/2 − 20 − 30 − Valid Data Input ← SCLK rise tSRD 45 − 45 − SCLK rise → Input Data hold tHSR 0 − 0 − SCLK cycle (programmable) tSCY SCLK (Output Mode/ Input High Mode) Unit ns tSCH tSCL SCLK (Input Low Mode) tOSS OUTPUT DATA TxD INPUT DATA RxD tOHS 0 1 tSRD 2 3 tHSR 0 VALID 1 2 VALID VALID Page 433 3 VALID 17. 17.6 Electrical Characteristics AC Electrical Characteristics 17.6.3 TMPM333FDFG/FYFG/FWFG Serial Bus Interface(I2C/SIO) 17.6.3.1 I2C Mode In the table below, the letter x represents the I2C operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. n denotes the value of n programmed into the SCK (SCL output frequency select) field in the SBIxCR. Symbol Parameter Equation Standard Mode Fast Mode Unit Min Max Min Max Min Max tSCL 0 − 0 100 0 400 kHz Hold time for START condition tHD; STA − − 4.0 − 0.6 − μs SCL Low width (Input) (Note 1) tLOW − − 4.7 − 1.3 − μs SCL High width (Input) (Note 2) tHIGH − − 4.0 − 0.6 − μs Setup time for a repeated START condition tSU; STA (Note5) − 4.7 − 0.6 − μs Data hold time (Input) (Note 3, 4) tHD; DAT − − 0.0 − 0.0 − μs Data setup time tSU; DAT − − 250 − 100 − ns Setup time for a STOP condition tSU; STO − − 4.0 − 0.6 − μs tBUF (Note5) − 4.7 − 1.3 − μs SCL clock frequency Bus free time between stop condition and start condition Note 1: SCL clock Low width (output) = (2n - 1 + 58)/x Note 2: SCL clock High width (output) = (2n - 1 + 12)/x On I2C-bus specification, Maximum Speed of Standard Mode is 100kHz, Fast mode is 400khz. Internal SCL Frequency setting should comply with Note1 & Note2 shown above. Note 3: The output data hold time is equal to 12x of internal SCL. Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. However, this SBI does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the SCL and SDA lines. Note 5: Software -dependent Note 6: The Philips I2C-bus specification instructs that if the power supply to a Fast-mode device is switched off, the SDA and SCL I/O pins must be floating so that they don't obstruct the bus lines. However, this SBI does not satisfy this requirement. tSCL tf tLOW tr tHIGH SCL tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF SDA S Sr S: Start condition Sr: Repeated start condition P: Stop condition Page 434 P TMPM333FDFG/FYFG/FWFG 17.6.3.2 Clock-Synchronous 8-Bit SIO mode In the table below, the letter x represents the I2C operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. (1) SCK Input Mode (The electrical specifications below are for an SCK signal with a 50% duty cycle.) Parameter Symbol Equation 40 MHz Min Max Min Max SCK Clock High width (input) tSCH 4x − 100 − SCK Clock Low width (input) tSCL 4x − 100 − SCK cycle tSCY tSCH + tSCL − 200 − −20 Output Data ← SCK rise tOSS tSCY/2 − 3x − 45 − SCK rise → Output Data hold tOHS tSCY/2 + x − 125 − Valid Data input ← SCK rise tSRD 30 − x − 5 − SCK rise → Input Data hold tHSR 30 − 30 − Unit − (Note) ns Note:Keep this value positive by adjusting SCK cycle. (2) SCK Output Mode (The electrical specifications below are for an SCK signal with a 50% duty cycle.) Parameter Symbol Equation 40 MHz Min Max Min Max SCK cycle (programmable) tSCY 16x − 400 − Output Data ← SCK rise tOSS tSCY/2 − 20 − 180 − SCK rise → Output Data hold tOHS tSCY/2 − 20 − 180 − Valid Data input ← SCK rise tSRD 45 − 45 − SCK rise → Input Data hold tHSR 0 − 0 − tSCY tSCL tOSS INPUT DATA SI ns tSCH SCK OUTPUT DATA SO Unit tOHS 0 1 tSRD 2 3 tHSR 1 2 VALID VALID 0 VALID Page 435 3 VALID 17. 17.6 Electrical Characteristics AC Electrical Characteristics 17.6.4 TMPM333FDFG/FYFG/FWFG Event Counter In the table below, the letter x represents the TMRB operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. Parameter 17.6.5 Equation Symbol 40 MHz Min Max Min Max Unit Clock Low pulse width tVCKL 2x + 100 − 150 − ns Clock High pulse width tVCKH 2x + 100 − 150 − ns Capture In the table below, the letter x represents the TMRB operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. Parameter 17.6.6 Equation Symbol 40 MHz Min Max Min Max Unit Low pulse width tCPL 2x + 100 − 150 − ns High pulse width tCPH 2x + 100 − 150 − ns External Interrupt In the table below, the letter x represents the fsys cycle time. 1. Except STOP release interrupts Parameter Equation Symbol 40 MHz Min Max Min Max Unit INT0 to 7 low level pulse width tINTAL x + 100 − 125 − ns INT0 to 7 high level pulse width tINTAH x + 100 − 125 − ns 2. STOP release interrupts Symbol Min Max Unit INT0 to 7 low level pulse width tINTBL 125 − ns INT0 to 7 high level pulse width tINTBH 125 − ns Parameter Page 436 TMPM333FDFG/FYFG/FWFG 17.6.7 NMI Parameter NIM low level pulse width 17.6.8 Symbol Min Max Unit tINTCL 100 − ns SCOUT Pin AC Characteristic Parameter Symbol Equation 40 MHz Min Max Min Max Unit High pulse width tSCH 0.5T − 5 − 7.5 − ns Low pulse width tSCL 0.5T − 5 − 7.5 − ns Note:In the above table, the letter T represents the cycle time of the SCOUT output clock. tSCH SCOUT Page 437 tSCL 17. 17.6 Electrical Characteristics AC Electrical Characteristics 17.6.9 TMPM333FDFG/FYFG/FWFG Debug Communication 17.6.9.1 SWD Interface Symbol Min Max Unit CLK cycle Tdck 83.33 − ns CLK rise →Output data hold Td1 4 − ns CLK rise → Output data valid Td2 − 30 ns Input data valid ←CLK rise Tds 20 − ns CLK rise → Input data hold Tdh 15 − ns Symbol Min Max Unit CLK cycle Tdck 100 − ns CLK fall →Output data hold Td3 4 − ns CLK fall → Output data valid Td4 − 50 ns Input data valid ←CLK rise Tds 20 − ns CLK rise → Input data hold Tdh 15 − ns Parameter 17.6.9.2 JTAG Interface Parameter Tdck CLK INPUT (SWCLK) (TCK) Td2 Td1 OUTPUT DATA (SWDIO) Td4 Td3 OUTPUT DATA (TDO) INPUT DATA (SWDIO) (TMS/TDI) Tds Tdh Page 438 TMPM333FDFG/FYFG/FWFG 17.6.10 ETM Trace Symbol Min Max Unit ttclk 50 − ns TRACEDATA valid ← TRACECLK rise tsetupr 2 − ns TRACECLK rise → TRACEDATA hold tholdr 1 − ns TRACEDATA valid ← TRACECLK fall tsetupf 2 − ns TRACECLK fall → TRACEDATA hold tholdf 1 − ns Parameter TRACECLK cycle ttclk TRACECLK tsetupf TRACEDATA 0 to 3 17.7 tholdf 0 tsetupr tholdr 1 2 3 Flash Characteristics 17.7.1 Rewriting Parameter Condition Guarantee on DVDD3 = AVDD3 = RVDD3 = 2.7 V to 3.6 V Flash-memory rewriting Ta = 0 to 70 °C Page 439 Min Typ. Max Unit − − 100 Times 17. 17.8 Electrical Characteristics Recommended Oscillation Circuit 17.8 TMPM333FDFG/FYFG/FWFG Recommended Oscillation Circuit X1 X2 Figure 17-1 High-frequency oscillation connection Note:To obtain a stable oscillation, load capacity and the position of the oscillator must be configured properly. Since these factors are strongly affected by substratepatterns, please evaluate oscillation stability using the substrate you use. The TX03 has been evaluated by the oscillator vender below. Please refer this information when selecting external parts 17.8.1 Ceramic oscillator The TX03 recommends the high-frequency oscillator by Murata Manufacturing Co., Ltd. Please refer to the following URL for details. http://www.murata.co.jp 17.8.2 Crystal oscillator The TX03 recommends the high-frequency oscillator by KYOCERA KINSEKI Corporation. Please refer to the following URL for details http://www.kinseki.co.jp Page 440 TMPM333FDFG/FYFG/FWFG 17.9 Handling Precaution 17.9.1 Solderability Test parameter Test condition Note Use of Sn-37Pb solder Bath Solder bath temperature = 230°C, Dipping time = 5 seconds Solderability The number of times = one, Use of R-type flux Pass: Use of Sn-3.0Ag-0.5Cu solder bath solderability rate until forming ≥ 95% Solder bath temperature = 245°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux 17.9.2 Power-on sequence The power supply must be raised (from 0V to 2.7V) at a speed of 0.37ms/V or slower. The power-on sequence must consider the time for the internal regulator and oscillator to be stableIn the .In the TX03, the internal regulator requires at least 700 μs to be stable. The time required to achieve stable oscillation varies with system. At cold reset, the external reset pin must be kept "Low" for a duration of time sufficiently long enough for the internal regulator and oscillator to be stable. Figure 17-2 shows the power-on sequence. RVDD3, DVDD3, AVDD3 2.7 V 0V 700 µs(min.) 0.37ms/V (min.) RESET High-speed oscillation 12 cycle(min.) Figure 17-2 Power-on sequence Page 441 17. 17.9 Electrical Characteristics Handling Precaution TMPM333FDFG/FYFG/FWFG Page 442 TMPM333FDFG/FYFG/FWFG 18. Port Section Equivalent Circuit Schematic Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The input protection resistance ranges from several tens of Ω to several hundreds of Ω. Damping resistors X2 and XT2 are shown with a typical value. 18.1 PA0, PB1 to 2, PE1 to 3, PE5 to 6, PF1 to 7, PG0 to 6, PH0 to 7, PI6 to 7, PJ0 to 3, PJ6 to 7 Output Data P-ch Programmable Pull-up Resistor Output Enable N-ch Pull-up Enable I/O Port Input Data Schmitt Input Enable 18.2 PA1 Output Data P-ch Output Enable N-ch Pull-down Enable I/O Port Input Data Schmitt Input Enable Programmable Pull-down Resistor Page 443 18. 18.3 Port Section Equivalent Circuit Schematic PA2 to 7, PB0, PB3 to 7, PE0, PE4, PF0, PG7, PI0 to 5, PJ4 to 5, PK1 to 2 TMPM333FDFG/FYFG/FWFG PA2 to 7, PB0, PB3 to 7, PE0, PE4, PF0, PG7, PI0 to 5, PJ4 to 5, PK1 to 18.3 2 Output Data P-ch Programmable Pull-up Resistor Output Enable N-ch Pull-up Enable I/O Port Input Data Input Enable 18.4 PC0 to 3, PD4 to 7 Programmable Pull-up Resistor Pull-up Enable Input Port Input Data Input Enable Input AIN 18.5 PD0 to 3 Programmable Pull-up Resistor Pull-up enable Schmitt Input Port Input Data Input Enable Input AIN Page 444 TMPM333FDFG/FYFG/FWFG 18.6 PK0 Output Data N-ch Output Enable Schmitt I/O Port Input Data Input Enable 18.7 NMI, MODE Input Data Input Port Schmitt 18.8 RESET P-ch Reset Input Port Schimitt Page 445 18. 18.9 Port Section Equivalent Circuit Schematic X1, X2 18.9 TMPM333FDFG/FYFG/FWFG X1, X2 fosc Oscillator Circuit X2 2kΩ (typ.) High-frequency Oscillation Enable P-ch N-ch X1 18.10 XT1, XT2 fs Oscillator Circuit XT2 300kΩ (typ.) Low-frequency Oscillation Enable 18.11 XT1 VREFH, AVSS VREFON P-ch VREFH String Resistor AVSS Page 446 TMPM333FDFG/FYFG/FWFG 19. Package Dimensions Type: LQFP100-P-1414-0.50H Unit: mm Dimensions 㻝㻢㻚㻜 㼼㻜㻚㻞 㻝㻠㻚㻜 㼼㻜㻚㻝 㻡㻝 㻣㻡 㻝㻠㻚㻜 㼼㻜㻚㻝 㻝㻢㻚㻜 㼼㻜㻚㻞 㻡㻜 㻣㻢 㻔 㻝㻚㻜 㻕 㻵㻺㻰㻱㼄 㻝㻜㻜 㻞㻢 㻝 㻞㻡 㻗㻜㻚㻜㻣 㻌㻌 㻌㻜㻚㻜㻤㻌㻌㻹㻌 㻝㻚㻠 㻙㻜㻚㻜㻡 㻗㻜㻚㻝㻡 㻜㻚㻞 㻙㻜㻚㻜㻟 㻜㻚㻝 㼼㻜㻚㻜㻡 㻿 㻜㻚㻜㻤 㻿 Page 447 㻝㻚㻣 㻹㻭㼄 㻜㻚㻡 㻔 㻝㻚㻜 㻕 Package Dimensions TMPM333FDFG/FYFG/FWFG Pin detail 㻔 㻜㻚㻡 㻕 㻜㻚㻞㻡 㻗㻜㻚㻜㻣㻡 㻜㻚㻝㻞㻡 㻙㻜㻚㻜㻟㻡 19. 㻜䡚㻤㼻 㻜㻚㻠㻡 䡚㻜㻚㻣㻡 Page 448 RESTRICTIONS ON PRODUCT USE Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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