TMPM361F10FG(C,J)

32 Bit RISC Microcontroller TX03 Series TMPM361F10FG ©TOSHIBA CORPORATION 2011 All Rights Reserved TMPM361F10FG ************************************************************************************************************************* ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* R TMPM361F10FG Important Notices Make sure to read read this chapter before using the product. 1 Serial bus interface There are restrictions on the use of I2C bus mode when the multi-master function is used. 1.1 Description When the multi-master function is used in I2C bus mode, if these masters start the communications simultaneously, the following phenomena may occur: 1. Communications may be locked up. 2. SCL pulse widths shorten; therefore these pulses may not satisfy I2C Specifications. 1.2 Condition These phenomena occur only when the multi-master function is used in I2C bus mode. If a single master is used, these phenomena do not occur. 1.3 Workaround There is no workaround for these phenomena. Perform recovery process by software. 1.4 How to Recover from These Phenomena Perform recovery process by software. By using a timer, add timeout process to check whether communication is in a lock-up state. An example of recovery process: 1. Start a timer count synchronously with start of the transmission. 2. If a serial interface interrupt (INTSBIx) does not occur in a certain period, the MCU determines the timeout. 3. If the MCU determines the timeout, communications may be locked up. Perform software reset on the serial bus interface circuit. This circuit is initialized to release communication from the lock up state. 4. Resend transmission data. Mostly, Process 1 to 4 are enough to recovery; however if the multiple products are connected to the same bus line, add a delay time between each product's recovery process before Process 4 (resending data) is performed. This delay makes a time difference between each master; therefore bus collision can be avoided when the data is sent again. 2015/1 Important Notices TMPM361F10FG Example: Recovery process after a timeout is detected. Timeout Perform software reset Am I master device? i = Self ID×10 No (*optional) Software timer (--i) == 0 ? No No Bus is free? Other device established communication. Communication starts 2015/1 Back to the main routine TMPM361F10FG Introduction: Notes on the description of SFR (Special Function Register) under this specification An SFR (Special Function Register) is a control register for periperal circuits (IP). The SFR addressses of IPs are described in the chapter on memory map, and the details of SFR are given in the chapter of each IP. Definition of SFR used in this specification is in accordance with the following rules. a. SFR table of each IP as an example ・ SFR tables in each chapter of IP provides register names, addresses and brief descriptions. ・ All registers have a 32-bit unique address and the addresses of the registers are defined as follows, with some exceptions: "Base address + (Unique) address" Base Address = 0x0000_0000 Register name Control register Address(Base+) SAMCR 0x0004 0x000C Note: SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) + unique address (0x0004)). Note: The register shown above is an example for explanation purpose and not for demonstration purpose. This register does not exist in this microcontroller. b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and functions. TMPM361F10FG 1.2.2 SAMCR(Control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 9 15 14 13 12 11 10 bit symbol - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol MODE After reset 0 0 0 0 Bit Bit Symbol TDATA 0 0 1 Type 0 Function 31-10 − R "0" can be read. 9-7 MODE[2:0] R/W Operation mode settings 000 : Sample mode 0 001 : Sample mode 1 010 : Sample mode 2 011 : Sample mode 3 The settings other than those above: Reserved 6-0 Note: TDATA[6:0] W Transmitted data The Type is divided into three as shown below. R/W c. 8 MODE READ WRITE R READ W WRITE Data descriptopn Meanings of symbols used in the SFR description are as shown below. ・ x:channel numbers/ports ・ n,m:bit numbers d. Register descriptoption Registers are described as shown below. ・ Register name Exmaple: SAMCR="000" or SAMCR="000" indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width). TMPM361F10FG Revision History Date Revision Comment 2011/6/20 1 First Release 2013/5/31 2 Contents Revised Table of Contents Introduction: Notes on the description of SFR (Special Function Register) under this specification TMPM361F10FG 1.1 1.2 1.3 1.4 1.5 Features......................................................................................................................................1 Block Diagram...........................................................................................................................4 Pin layout (Top view)................................................................................................................5 Pin names and Functions...........................................................................................................6 Pin Numbers and Power Supply Pins.....................................................................................12 2. Processor Core 2.1 2.2 2.3 Information on the processor core..........................................................................................13 Configurable Options..............................................................................................................13 Exceptions/ Interruptions.........................................................................................................14 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.5 2.6 Number of Interrupt Inputs...............................................................................................................................................14 Number of Priority Level Interrupt Bits...........................................................................................................................14 SysTick..............................................................................................................................................................................14 SYSRESETREQ................................................................................................................................................................14 LOCKUP...........................................................................................................................................................................14 Auxiliary Fault Status register..........................................................................................................................................14 Events......................................................................................................................................15 Power Management.................................................................................................................15 Exclusive access......................................................................................................................15 3. Debug Interface 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Specification Overview...........................................................................................................17 SW-DP.....................................................................................................................................17 ETM.........................................................................................................................................17 Pin functions............................................................................................................................18 Peripheral Functions in Halt Mode.........................................................................................19 Reset Vector Break..................................................................................................................19 Connection with a Debug Tool...............................................................................................19 4. Memory Map 4.1 Memory Map...........................................................................................................................21 4.1.1 4.2 Memory map of the TMPM361F10FG............................................................................................................................22 SFR area detail........................................................................................................................23 i 5. Reset 5.1 5.2 Cold reset.................................................................................................................................25 Warm reset...............................................................................................................................27 5.2.1 5.3 Reset period.......................................................................................................................................................................27 After reset................................................................................................................................27 6. Clock / Mode Control 6.1 6.2 Features....................................................................................................................................29 Registers..................................................................................................................................30 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 Register List.......................................................................................................................................................................30 CGSYSCR (System control register)................................................................................................................................31 CGOSCCR (Oscillation control register).........................................................................................................................32 CGSTBYCR (Standby control register)...........................................................................................................................33 CGPLLSEL (PLL Selection Register)..............................................................................................................................34 CGCKSEL (System clock selection register)...................................................................................................................35 Clock control...........................................................................................................................36 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 Clock Type........................................................................................................................................................................36 Initial Values after Reset...................................................................................................................................................36 Clock system Diagram......................................................................................................................................................37 Warm-up function..............................................................................................................................................................38 Clock Multiplication Circuit (PLL)..................................................................................................................................41 6.3.5.1 6.3.5.2 6.3.5.3 6.3.5.4 6.3.6 System Clock.....................................................................................................................................................................44 6.3.6.1 6.3.6.2 6.3.6.3 6.3.7 6.3.8 6.4 Prescaler Clock Control.....................................................................................................................................................46 System Clock Pin Output Function..................................................................................................................................46 Mode Transitions...............................................................................................................................................................47 Operation Mode.......................................................................................................................48 6.5.1 6.5.2 6.6 High-speed clock Low-speed clock Setting system clock Modes and Mode Transitions..................................................................................................47 6.4.1 6.5 How to configure the PLL function Changing PLL multiplying Start PLL sequence Multiplying value change sequence NORMAL mode................................................................................................................................................................48 SLOW mode......................................................................................................................................................................48 Low Power Consumption Modes............................................................................................49 6.6.1 IDLE Mode (IDLE2, IDLE1)...........................................................................................................................................49 6.6.1.1 6.6.1.2 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 IDLE2 mode IDLE1 mode SLEEP mode......................................................................................................................................................................50 STOP mode........................................................................................................................................................................50 BACKUP mode (BACKUP STOP, BACKUP SLEEP)..................................................................................................51 Low power Consumption Mode Setting...........................................................................................................................51 Operational Status in Each Mode.....................................................................................................................................52 Releasing the Low Power Consumption Mode................................................................................................................53 Warm-up............................................................................................................................................................................56 Clock Operation in Mode Transition................................................................................................................................58 6.6.9.1 6.6.9.2 6.6.9.3 6.6.9.4 Transition Transition Transition Transition of of of of operation operation operation operation modes modes modes modes : : : : NORMAL → STOP → NORMAL NORMAL → SLEEP → NORMAL SLOW → STOP → SLOW SLOW → SLEEP → SLOW 7. Exceptions 7.1 ii Overview..................................................................................................................................61 7.1.1 7.1.2 Exception types..................................................................................................................................................................61 Handling Flowchart...........................................................................................................................................................62 7.1.2.1 7.1.2.2 7.1.2.3 7.1.2.4 7.2 7.3 7.4 7.5 Request and Detection Handling and Branch to the Interrupt Service Routine (Pre-emption) an ISR exit Reset Exceptions.....................................................................................................................68 Non-Maskable Interrupts (NMI).............................................................................................68 SysTick....................................................................................................................................68 Interrupts..................................................................................................................................69 7.5.1 Interrupt Sources................................................................................................................................................................69 7.5.1.1 7.5.1.2 7.5.1.3 7.5.1.4 7.5.1.5 7.5.1.6 7.5.2 Interrupt route Generation Transmission Precautions when using external interrupt pins List of Interrupt Sources Active level Interrupt Handling.............................................................................................................................................................75 7.5.2.1 7.5.2.2 7.5.2.3 7.5.2.4 7.5.2.5 7.5.2.6 7.6 Exception Exception Executing Exception Flowchart Preparation Detection by Clock Generator Detection by CPU CPU processing Interrupt Service Routine (ISR) Exception / Interrupt-Related Registers..................................................................................81 7.6.1 7.6.2 Register List.......................................................................................................................................................................81 NVIC Registers..................................................................................................................................................................82 7.6.2.1 7.6.2.2 7.6.2.3 7.6.2.4 7.6.2.5 7.6.2.6 7.6.2.7 7.6.2.8 7.6.2.9 7.6.2.10 7.6.2.11 7.6.2.12 7.6.2.13 7.6.2.14 7.6.2.15 7.6.2.16 7.6.2.17 7.6.2.18 7.6.2.19 7.6.2.20 7.6.2.21 7.6.2.22 7.6.2.23 7.6.2.24 7.6.2.25 7.6.3 SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register SysTick Calibration Value Register Interrupt Set-Enable Register 1 Interrupt Set-Enable Register 2 Interrupt Set-Enable Register 3 Interrupt Set-Enable Register 4 Interrupt Clear-Enable Register 1 Interrupt Clear-Enable Register 2 Interrupt Clear-Enable Register 3 Interrupt Clear-Enable Register 4 Interrupt Set-Pending Register 1 Interrupt Set-Pending Register 2 Interrupt Set-Pending Register 3 Interrupt Set-Pending Register 4 Interrupt Clear-Pending Register 1 Interrupt Clear-Pending Register 2 Interrupt Clear-Pending Register 3 Interrupt Clear-Pending Register 4 Interrupt Priority Register Vector Table Offset Register Application Interrupt and Reset Control Register System Handler Priority Register System Handler Control and State Register Clock generator registers.................................................................................................................................................111 7.6.3.1 7.6.3.2 7.6.3.3 7.6.3.4 7.6.3.5 7.6.3.6 7.6.3.7 7.6.3.8 CGIMCGA (CG Interrupt Mode Control Register A) CGIMCGB (CG Interrupt Mode Control Register B) CGIMCGD (CG Interrupt Mode Control Register D) CGIMCGE (CG Interrupt Mode Control Register E) CGIMCGF (CG Interrupt Mode Control Register F) CGICRCG (CG Interrupt Request Clear Register) CGNMIFLG (NMI Flag Register) CGRSTFLG (Reset Flag Register) 8. Input / Output Ports 8.1 Port Functions........................................................................................................................123 8.1.1 8.1.2 8.1.3 8.2 Function list.....................................................................................................................................................................123 Port Registers Outline.....................................................................................................................................................126 Port states in STOP Mode...............................................................................................................................................127 Port functions.........................................................................................................................128 iii 8.2.1 Port A (PA0 to PA7).......................................................................................................................................................128 8.2.1.1 8.2.1.2 8.2.1.3 8.2.1.4 8.2.1.5 8.2.1.6 8.2.1.7 8.2.1.8 8.2.2 Port B (PB0 to PB7)........................................................................................................................................................133 8.2.2.1 8.2.2.2 8.2.2.3 8.2.2.4 8.2.2.5 8.2.2.6 8.2.2.7 8.2.2.8 8.2.3 Port J Circuit Type Port J register PJDATA (Port J data register) PJFR2 (Port J function register 1) PJPUP (Port J pull-up control register) PJIE (Port J input control register) Port L (PL0 to PL7)........................................................................................................................................................166 8.2.8.1 8.2.8.2 8.2.8.3 8.2.8.4 8.2.8.5 8.2.8.6 8.2.8.7 8.2.8.8 8.2.8.9 8.2.8.10 iv Port I Circuit Type Port I register PIDATA (Port I data register) PICR (Port I output control register) PIFR1 (Port I function register 1) PIOD (Port I open drain control register) PIPUP (Port I pull-up control register) PIIE (Port I input control register) Port J (PJ0 to PJ7)...........................................................................................................................................................162 8.2.7.1 8.2.7.2 8.2.7.3 8.2.7.4 8.2.7.5 8.2.7.6 8.2.8 Port G Circuit Type Port G register PGDATA (Port G data register) PGCR (Port G output control register) PGFR1 (Port G function register 1) PGFR2 (Port G function register 2) PGFR3 (Port G function register 3) PGOD (Port G open drain control register) PGPUP (Port G pull-up control register) PGIE (Port G input control register) Port I (PI0 to PI3)............................................................................................................................................................156 8.2.6.1 8.2.6.2 8.2.6.3 8.2.6.4 8.2.6.5 8.2.6.6 8.2.6.7 8.2.6.8 8.2.7 Port F Circuit Type Port F Register PFDATA (Port F data register) PFCR (Port F output control register) PFFR1 (Port F function register 1) PFOD (Port F open drain control register) PFPUP (Port F pull-up control register) PFIE (Port F input control register) Port G (PG0 to PG7).......................................................................................................................................................149 8.2.5.1 8.2.5.2 8.2.5.3 8.2.5.4 8.2.5.5 8.2.5.6 8.2.5.7 8.2.5.8 8.2.5.9 8.2.5.10 8.2.6 Port E Circuit Type Port E register PEDATA (Port E data register) PECR (Port E output control register) PEFR1 (Port E function register 1) PEFR2 (Port E function register 2) PEFR3 (Port E function register 3) PEOD (Port E open drain control register) PEPUP (Port E pull-up control register) PEIE (Port E input control register) Port F (PF0 to PF4).........................................................................................................................................................144 8.2.4.1 8.2.4.2 8.2.4.3 8.2.4.4 8.2.4.5 8.2.4.6 8.2.4.7 8.2.4.8 8.2.5 Port B Circuit Type Port B Register PBDATA (Port B data register) PBCR (Port B output control register) PBFR1 (Port B function register) PBOD (Port B open drain control register) PBPUP (Port B pull-up control register) PBIE (Port B input control register) Port E (PE0 to PE7)........................................................................................................................................................138 8.2.3.1 8.2.3.2 8.2.3.3 8.2.3.4 8.2.3.5 8.2.3.6 8.2.3.7 8.2.3.8 8.2.3.9 8.2.3.10 8.2.4 Port A Circuit Type Port A Register PADATA (Port A data register) PACR (Port A output control register) PAFR1 (Port A function register 1) PAOD (Port A open drain control register) PAPUP (Port A pull-up control register) PAIE (Port A input control register) Port L Circut Type Port L register PLDATA (Port L data register) PLCR (Port L output control register) PLFR1 (Port K function register 1) PLFR2 (Port L function register 2) PLFR3 (Port L function register 3) PLOD (Port L open drain control register) PLPUP (Port L pull-up control register) PLIE (Port L input control register) 8.2.9 Port M (PM0 to PM7).....................................................................................................................................................172 8.2.9.1 8.2.9.2 8.2.9.3 8.2.9.4 8.2.9.5 8.2.9.6 8.2.9.7 8.2.9.8 8.2.9.9 8.2.9.10 8.2.10 Port N (PN0 to PN3).....................................................................................................................................................178 8.2.10.1 8.2.10.2 8.2.10.3 8.2.10.4 8.2.10.5 8.2.10.6 8.2.10.7 8.2.10.8 8.2.10.9 8.2.10.10 8.2.11 Port N Circuit Type Port N register PNDATA (Port N data register) PNCR (Port N output control register) PNFR1 (Port N function register 1) PNFR2 (Port N function register 2) PNFR3 (Port N function register 3) PNOD (Port N open drain control register) PNPUP (Port N pull-up control register) PNIE (Port N input control register) Port P (PP0 to PP6).......................................................................................................................................................185 8.2.11.1 8.2.11.2 8.2.11.3 8.2.11.4 8.2.11.5 8.2.11.6 8.2.11.7 8.2.11.8 8.2.11.9 8.3 Port Circuit Type Port M register PMDATA (Port M data register) PMCR (Port M output control register) PMFR1 (Port M function register 1) PMFR2 (Port M function register 2) PMFR3 (Port M function register 3) PMOD (Port M open drain control register) PMPUP (Port M pull-up control register) PMIE (Port M input control register) Port P Circuit Type Port P register PPDATA (Port P data register) PPCR (Port P output control register) PPFR1 (Port P function register 1) PPFR2 (Port P function register 2) PPOD (Port P open drain control register) PPPUP (Port P pull-up control register) PPIE (Port P input control register) Block Diagrams of Ports.......................................................................................................191 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16 8.3.17 8.3.18 8.3.19 8.3.20 8.3.21 8.3.22 8.3.23 8.3.24 8.3.25 8.3.26 8.3.27 8.3.28 8.3.29 8.3.30 8.3.31 8.3.32 8.3.33 8.3.34 8.3.35 8.3.36 8.3.37 8.3.38 Port Types........................................................................................................................................................................191 Type T1............................................................................................................................................................................193 Type T2............................................................................................................................................................................194 Type T3............................................................................................................................................................................195 Type T4............................................................................................................................................................................196 Type T5............................................................................................................................................................................197 Type T6............................................................................................................................................................................198 Type T7............................................................................................................................................................................199 Type T8............................................................................................................................................................................200 Type T9..........................................................................................................................................................................201 Type T10........................................................................................................................................................................202 Type T11........................................................................................................................................................................203 Type T12........................................................................................................................................................................204 TypeT13.........................................................................................................................................................................205 Type T14........................................................................................................................................................................206 Type T15........................................................................................................................................................................207 TypeT16.........................................................................................................................................................................208 Type T17........................................................................................................................................................................209 Type T18........................................................................................................................................................................210 Type T19........................................................................................................................................................................211 Type T20........................................................................................................................................................................212 Type T21........................................................................................................................................................................213 Type T22........................................................................................................................................................................214 Type T23........................................................................................................................................................................215 Type T24........................................................................................................................................................................216 Type T25........................................................................................................................................................................217 TypeT26.........................................................................................................................................................................218 Type T27........................................................................................................................................................................219 Type T28........................................................................................................................................................................220 Type T29........................................................................................................................................................................221 Type T30........................................................................................................................................................................222 Type T31........................................................................................................................................................................223 Type T32........................................................................................................................................................................224 Type T33........................................................................................................................................................................225 Type T34........................................................................................................................................................................226 Type T35........................................................................................................................................................................227 Type T36........................................................................................................................................................................228 Type T37........................................................................................................................................................................229 v 8.3.39 8.3.40 8.4 Type T38........................................................................................................................................................................230 Type T39........................................................................................................................................................................231 Appendix (Port setting List)..................................................................................................232 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 Port A setting...................................................................................................................................................................232 Port B Setting..................................................................................................................................................................233 Port E Setting..................................................................................................................................................................234 Port F Setting...................................................................................................................................................................235 Port G Setting..................................................................................................................................................................236 Port I Setting....................................................................................................................................................................237 Port J Setting...................................................................................................................................................................238 Port L Setting..................................................................................................................................................................239 Port M Setting.................................................................................................................................................................240 Port N setting.................................................................................................................................................................241 Port P Setting.................................................................................................................................................................242 9. DMA Controller(DMAC) 9.1 9.2 9.3 9.4 Overview................................................................................................................................243 DMA transfer type.................................................................................................................244 Block diagram.......................................................................................................................245 Product information of TMPM361F10FG............................................................................246 9.4.1 9.4.2 9.4.3 9.4.4 9.5 Description of Registers........................................................................................................248 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.8 9.5.9 9.5.10 9.5.11 9.5.12 9.5.13 9.5.14 9.5.15 9.5.16 9.5.17 9.6 Peripheral function supported with Peripheral to Peripheral Transfer..........................................................................246 DMA request...................................................................................................................................................................246 Interrupt request...............................................................................................................................................................246 Base address of registers.................................................................................................................................................247 DMAC register list..........................................................................................................................................................248 DMACxIntStatus (DMAC Interrupt Status Register)....................................................................................................249 DMACxIntTCStatus (DMAC Interrupt Terminal Count Status Register)....................................................................250 DMACxIntTCClear (DMAC Interrupt Terminal Count Clear Register).......................................................................251 DMACxIntErrorStatus (DMAC Interrupt Error Status Register)..................................................................................252 DMACxIntErrClr (DMAC Interrupt Error Clear Register)...........................................................................................253 DMACxRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register)....................................................254 DMACxRawIntErrorStatus (DMAC Raw Error Interrupt Status Register)..................................................................255 DMACxEnbldChns (DMAC Enabled Channel Register)..............................................................................................256 DMACxSoftBReq (DMAC Software Burst Request Register)...................................................................................257 DMACxSoftSReq (DMAC Software Single Request Register)..................................................................................259 DMACxConfiguration (DMAC Configuration Register).............................................................................................261 DMACxCnSrcAddr (DMAC Channelx Source Address Register).............................................................................262 DMACxCnDestAddr (DMAC Channelx Destination Address Register)....................................................................263 DMACxCnLLI (DMAC Channelx Linked List Item Register)...................................................................................264 DMACxCnControl (DMAC Channeln Control Register)............................................................................................265 DMACxCnConfiguration (DMAC Channel n Configuration Register)......................................................................267 Special Functions...................................................................................................................269 9.6.1 9.6.2 Scatter/gather function.....................................................................................................................................................269 Linked list operation........................................................................................................................................................270 10. Static Memory Controller 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 vi Function Overview..............................................................................................................273 Block diagram.....................................................................................................................274 Description of Registers......................................................................................................275 SFR List.........................................................................................................................................................................275 SMCMDMODE (Mode Register).................................................................................................................................276 smc_memif_cfg (SMC Memory Interface Configuration Register)............................................................................277 smc_direct_cmd (SMC Direct Command Register).....................................................................................................278 smc_set_cycles (SMC Set Cycles Register).................................................................................................................279 smc_set_opmode (SMC Set Opmode Register)...........................................................................................................280 smc_sram_cycles0_0 (SMC SRAM Cycles Registers 0 ).....................................................................................281 10.3.8 smc_sram_cycles0_1 (SMC SRAM Cycles Registers 0 ).....................................................................................282 10.3.9 smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 ).....................................................................................283 10.3.10 smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 )...................................................................................284 10.3.11 smc_opmode0_0 (SMC Opmode Registers 0).....................................................................................................285 10.3.12 smc_opmode0_1 (SMC Opmode Registers 0).....................................................................................................286 10.3.13 smc_opmode0_2 (SMC Opmode Registers 0).....................................................................................................287 10.3.14 smc_opmode0_3 (SMC Opmode Registers 0).....................................................................................................288 10.4 External Bus Cycle .............................................................................................................289 10.4.1 Multiplex mode..............................................................................................................................................................289 10.4.1.1 10.4.1.2 10.4.1.3 10.5 tRC / tCEOE setting example tWC / tWP setting example tTR setting example Connection example for external memory..........................................................................292 11. 16-bit Timer / Event Counters (TMRB) 11.1 11.2 11.3 11.4 Outline.................................................................................................................................293 Differences in the Specifications........................................................................................294 Configuration.......................................................................................................................296 Registers..............................................................................................................................298 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.4.9 11.4.10 11.4.11 11.4.12 11.4.13 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 11.5.9 11.6 11.6.1 11.6.2 11.6.3 11.6.4 11.7 11.7.1 11.7.2 11.7.3 11.7.4 Register list according to channel.................................................................................................................................298 TBxEN (Enable register)...............................................................................................................................................299 TBxRUN (RUN register)..............................................................................................................................................300 TBxCR (Control register)..............................................................................................................................................301 TBxMOD (Mode register).............................................................................................................................................302 TBxFFCR (Flip-flop control register)...........................................................................................................................304 TBxST (Status register).................................................................................................................................................305 TBxIM (Interrupt mask register)...................................................................................................................................306 TBxUC (Up counter capture register)..........................................................................................................................307 TBxRG0 (Timer register 0).........................................................................................................................................308 TBxRG1 (Timer register 1).........................................................................................................................................308 TBxCP0 (Capture register 0)......................................................................................................................................309 TBxCP1 (Capture register 1)......................................................................................................................................309 Description of Operations for Each Circuit........................................................................310 Prescaler.........................................................................................................................................................................310 Up-counter (UC)............................................................................................................................................................316 Timer registers (TBxRG0, TBxRG1)...........................................................................................................................316 Capture...........................................................................................................................................................................317 Capture registers (TBxCP0, TBxCP1)..........................................................................................................................317 Up-counter capture register (TBxUC)..........................................................................................................................317 Comparators (CP0, CP1)...............................................................................................................................................317 Timer Flip-flop (TBxFF0).............................................................................................................................................317 Capture interrupt (INTCAPx0, INTCAPx1).................................................................................................................317 Description of Operations for Each Mode..........................................................................318 16-bit interval Timer Mode...........................................................................................................................................318 16-bit Event Counter Mode...........................................................................................................................................318 16-bit PPG (Programmable Pulse Generation) Output Mode......................................................................................319 Timer synchronous mode..............................................................................................................................................321 Applications using the Capture Function............................................................................322 One-shot pulse output triggered by an external pulse..................................................................................................322 Frequency measurement................................................................................................................................................324 Pulse width measurement..............................................................................................................................................324 Time Difference Measurement......................................................................................................................................325 12. Serial Channel (SIO/UART) 12.1 12.2 12.3 Overview..............................................................................................................................327 Difference in the Specification of SIO Modules................................................................327 Configuration.......................................................................................................................328 vii 12.4 Registers Description...........................................................................................................329 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.4.7 12.4.8 12.4.9 12.4.10 12.4.11 12.4.12 12.4.13 12.5 12.6 Registers List in Each Channel.....................................................................................................................................329 SCxEN (Enable Register)..............................................................................................................................................330 SCxBUF (Buffer Register)............................................................................................................................................331 SCxCR (Control Register)............................................................................................................................................332 SCxMOD0 (Mode Control Register 0).........................................................................................................................333 SCxMOD1 (Mode Control Register 1).........................................................................................................................334 SCxMOD2 (Mode Control Register 2).........................................................................................................................335 SCxBRCR (Baud Rate Generator Control Register), SCxBRADD (Baud Rate Generator Control Register 2)...... 337 SCxFCNF (FIFO Configuration Register)....................................................................................................................339 SCxRFC (RX FIFO Configuration Register).............................................................................................................341 SCxTFC (TX FIFO Configuration Register) (Note2)................................................................................................342 SCxRST (RX FIFO Status Register)..........................................................................................................................343 SCxTST (TX FIFO Status Register)...........................................................................................................................344 Operation in Each Mode.....................................................................................................345 Data Format.........................................................................................................................346 12.6.1 12.6.2 Data Format List............................................................................................................................................................346 Parity Control................................................................................................................................................................347 12.6.2.1 12.6.2.2 12.6.3 12.7 Transmission Receiving Data STOP Bit Length...........................................................................................................................................................347 Clock Control......................................................................................................................348 12.7.1 12.7.2 Prescaler.........................................................................................................................................................................348 Serial Clock Generation Circuit....................................................................................................................................354 12.7.2.1 12.7.2.2 12.8 Baud Rate Generator Clock Selection Circuit Transmit / Receive Buffer and FIFO..................................................................................358 12.8.1 12.8.2 12.8.3 Configuration.................................................................................................................................................................358 Transmit / Receive Buffer.............................................................................................................................................358 FIFO...............................................................................................................................................................................358 12.9 Status Flag...........................................................................................................................359 12.10 Error Flag...........................................................................................................................359 12.10.1 12.10.2 12.10.3 12.11 12.11.1 12.11.2 OERR Flag..................................................................................................................................................................359 PERR Flag...................................................................................................................................................................360 FERR Flag...................................................................................................................................................................360 Receive..............................................................................................................................361 Receive Counter..........................................................................................................................................................361 Receive Control Unit...................................................................................................................................................361 12.11.2.1 12.11.2.2 12.11.3 Receive Operation.......................................................................................................................................................361 12.11.3.1 12.11.3.2 12.11.3.3 12.11.3.4 12.11.3.5 12.11.3.6 12.12 12.12.1 12.12.2 Transmission Counter..................................................................................................................................................366 Transmission Control..................................................................................................................................................366 12.14.1 RX Interrupt.................................................................................................................................................................371 Single Buffer / Double Buffer FIFO TX interrupt.................................................................................................................................................................372 12.14.2.1 12.14.2.2 viii Operation of Transmission Buffer Transmit FIFO Operation I/O interface Mode/Transmission by SCLK Output Underrun Error Handshake Function..........................................................................................................370 Interrupt / Error Generation Timing.................................................................................371 12.14.1.1 12.14.1.2 12.14.2 I/O interface Mode UART Mode Transmit Operation......................................................................................................................................................367 12.12.3.1 12.12.3.2 12.12.3.3 12.12.3.4 12.13 12.14 Receive Buffer Receive FIFO Operation I/O interface mode with SCLK output Read Received Data Wake-up Function Overrun Error Transmission......................................................................................................................366 12.12.2.1 12.12.2.2 12.12.3 I/O interface mode UART Mode Single Buffer / Double Buffer FIFO 12.14.3 Error Generation..........................................................................................................................................................373 12.14.3.1 12.14.3.2 12.15 12.16 UART Mode I/O Interface Mode Software Reset...................................................................................................................373 Operation in Each Mode...................................................................................................374 12.16.1 Mode 0 (I/O Interface Mode)......................................................................................................................................374 12.16.1.1 12.16.1.2 12.16.1.3 12.16.2 12.16.3 12.16.4 Transmitting Data Receive Transmit and Receive (Full duplex) Mode 1 (7-bit UART Mode).......................................................................................................................................385 Mode 2 (8-bit UART Mode).......................................................................................................................................385 Mode 3 (9-bit UART Mode).......................................................................................................................................386 12.16.4.1 12.16.4.2 Wake-up Function Protocol 13. Synchronous Serial Port (SSP) 13.1 13.2 13.3 Overview..............................................................................................................................389 Block Diagram.....................................................................................................................390 Register................................................................................................................................391 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 13.3.9 13.3.10 13.3.11 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.5 13.5.1 13.5.2 13.5.3 13.6 13.6.1 13.6.2 13.6.3 Register List...................................................................................................................................................................391 SSPCR0(Control register 0)..........................................................................................................................................392 SSPCR1(Control register1)...........................................................................................................................................393 SSPDR(Data register)....................................................................................................................................................394 SSPSR(Status register)..................................................................................................................................................395 SSPCPSR (Clock prescale register)..............................................................................................................................396 SSPIMSC (Interrupt enable/disable register)................................................................................................................397 SSPRIS (Pre-enable interrupt status register)...............................................................................................................398 SSPMIS (Post-enable interrupt status register)............................................................................................................399 SSPICR (Interrupt clear register)................................................................................................................................400 SSPxDMACR (DMA control register).......................................................................................................................400 Overview of SSP.................................................................................................................401 Clock prescaler..............................................................................................................................................................401 Transmit FIFO...............................................................................................................................................................401 Receive FIFO.................................................................................................................................................................401 Interrupt generation logic..............................................................................................................................................402 DMA interface...............................................................................................................................................................404 SSP operation......................................................................................................................405 Initial setting for SSP....................................................................................................................................................405 Enabling SSP.................................................................................................................................................................405 Clock ratios....................................................................................................................................................................405 Frame Format......................................................................................................................406 SSI frame format...........................................................................................................................................................407 SPI frame format...........................................................................................................................................................408 Microwire frame format................................................................................................................................................410 14. Serial Bus Interface (I2C/SIO) 14.1 14.2 14.2.1 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 Configuration.......................................................................................................................414 Register................................................................................................................................415 Registers for each channel............................................................................................................................................415 I2C Bus Mode Data Format................................................................................................416 Control Registers in the I2C Bus Mode..............................................................................417 SBIxCR0(Control register 0)........................................................................................................................................417 SBIxCR1(Control register 1)........................................................................................................................................418 SBIxCR2(Control register 2)........................................................................................................................................420 SBIxSR (Status Register)..............................................................................................................................................421 SBIxBR0(Serial bus interface baud rate register 0).....................................................................................................422 SBIxDBR (Serial bus interface data buffer register)....................................................................................................422 ix SBIxI2CAR (I2Cbus address register)..........................................................................................................................423 14.4.7 14.5 Control in the I2C Bus Mode..............................................................................................424 14.5.1 Serial Clock...................................................................................................................................................................424 14.5.1.1 14.5.1.2 14.5.2 14.5.3 14.5.4 14.5.5 14.5.6 14.5.7 14.5.8 14.5.9 14.5.10 14.5.11 14.5.12 14.5.13 14.5.14 14.5.15 14.5.16 14.6 Clock source Clock Synchronization Setting the Acknowledgement Mode............................................................................................................................425 Setting the Number of Bits per Transfer......................................................................................................................425 Slave Addressing and Address Recognition Mode......................................................................................................425 Operating mode.............................................................................................................................................................425 Configuring the SBI as a Transmitter or a Receiver....................................................................................................426 Configuring the SBI as a Master or a Slave.................................................................................................................426 Generating Start and Stop Conditions..........................................................................................................................426 Interrupt Service Request and Release.........................................................................................................................427 Arbitration Lost Detection Monitor............................................................................................................................427 Slave Address Match Detection Monitor....................................................................................................................429 General-call Detection Monitor...................................................................................................................................429 Last Received Bit Monitor..........................................................................................................................................429 Data Buffer Register (SBIxDBR)...............................................................................................................................429 Baud Rate Register (SBIxBR0)..................................................................................................................................430 Software Reset.............................................................................................................................................................430 Data Transfer Procedure in the I2C Bus ModeI2C............................................................431 14.6.1 14.6.2 Device Initialization......................................................................................................................................................431 Generating the Start Condition and a Slave Address...................................................................................................431 14.6.2.1 14.6.2.2 14.6.3 Transferring a Data Word.............................................................................................................................................433 14.6.3.1 14.6.3.2 14.6.4 14.6.5 14.7 Master mode Slave mode Master mode ( = "1") Slave mode ( = "0") Generating the Stop Condition......................................................................................................................................438 Restart Procedure...........................................................................................................................................................438 Control register of SIO mode..............................................................................................440 14.7.1 14.7.2 14.7.3 14.7.4 14.7.5 14.7.6 14.8 SBIxCR0(control register 0).........................................................................................................................................440 SBIxCR1(Control register 1)........................................................................................................................................441 SBIxDBR (Data buffer register)...................................................................................................................................442 SBIxCR2(Control register 2)........................................................................................................................................443 SBIxSR (Status Register)..............................................................................................................................................444 SBIxBR0 (Baud rate register 0)....................................................................................................................................445 Control in SIO mode...........................................................................................................446 14.8.1 Serial Clock...................................................................................................................................................................446 14.8.1.1 14.8.1.2 14.8.2 Clock source Shift Edge Transfer Modes..............................................................................................................................................................448 14.8.2.1 14.8.2.2 14.8.2.3 14.8.2.4 8-bit 8-bit 8-bit Data transmit mode receive mode transmit/receive mode retention time of the last bit at the end of transmission 15. Consumer Electronics Control (CEC) 15.1 15.1.1 15.1.2 15.1.3 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 x Outline.................................................................................................................................453 Reception.......................................................................................................................................................................453 Transmission..................................................................................................................................................................453 Precautions.....................................................................................................................................................................453 Block Diagram.....................................................................................................................454 Registers..............................................................................................................................455 Register List...................................................................................................................................................................455 CECEN (CEC Enable Register)....................................................................................................................................456 CECADD (Logical Address Register ).........................................................................................................................457 CECRESET (Software Reset Register)........................................................................................................................458 CECREN (Receive Enable Register)............................................................................................................................459 CECRBUF (Receive Buffer Register)..........................................................................................................................460 CECRCR1 (Receive Control Register 1)......................................................................................................................461 CECRCR2 (Receive Control Register 2)......................................................................................................................463 CECRCR3 (Receive Control Register 3 )....................................................................................................................465 CECTEN (Transmit Enable Register).........................................................................................................................467 CECTBUF (Transmit Buffer Register).......................................................................................................................468 CECTCR (Transmit Control Register).......................................................................................................................469 CECRSTAT (Receive Interrupt Status Register).......................................................................................................471 CECTSTAT (Transmit Interrupt Status Register)......................................................................................................472 CECFSSEL(CEC Sampling Clock Select Register)...................................................................................................473 15.3.10 15.3.11 15.3.12 15.3.13 15.3.14 15.3.15 15.4 Operations............................................................................................................................474 15.4.1 15.4.2 Sampling clock..............................................................................................................................................................474 Reception.......................................................................................................................................................................474 15.4.2.1 15.4.2.2 15.4.2.3 15.4.2.4 15.4.2.5 15.4.2.6 15.4.3 Basic Operation Preconfiguration Enabling Reception Detecting Error Interrupt Details of reception error Stopping Reception Transmission..................................................................................................................................................................483 15.4.3.1 15.4.3.2 15.4.3.3 15.4.3.4 15.4.3.5 15.4.3.6 15.4.4 Basic Operation Preconfiguration Detecting Transmission Error Details of Transmission Error Stopping Transmission Retransmission Software Reset...............................................................................................................................................................488 16. Remote control signal preprocessor(RMC) 16.1 Basic operation....................................................................................................................489 16.1.1 16.2 16.3 Reception of Remote Control Signal............................................................................................................................489 Block Diagram.....................................................................................................................489 Registers..............................................................................................................................490 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.3.9 16.3.10 16.3.11 16.3.12 16.3.13 16.3.14 16.3.15 16.4 Register List...................................................................................................................................................................490 RMCEN(Enable Register).............................................................................................................................................491 RMCREN(Receive Enable Register)............................................................................................................................492 RMCRBUF1(Receive Data Buffer Register 1)............................................................................................................493 RMCRBUF2(Receive Data Buffer Register 2)............................................................................................................493 RMCRBUF3(Receive Data Buffer Register 3)............................................................................................................494 RMCRCR1(Receive Control Register 1)......................................................................................................................495 RMCRCR2(Receive Control Register 2) ....................................................................................................................496 RMCRCR3(Receive Control Register 3) ....................................................................................................................497 RMCRCR4(Receive Control Register 4) ..................................................................................................................498 RMCRSTAT(Receive Status Register) .....................................................................................................................499 RMCEND1(Receive End bit Number Register 1) ....................................................................................................500 RMCEND2(Receive End bit Number Register 2) ....................................................................................................500 RMCEND3(Receive End bit Number Register 3) ....................................................................................................501 RMCFSSEL(Source Clock selection Register) .........................................................................................................502 Operation Description.........................................................................................................503 16.4.1 Reception of Remote Control Signal............................................................................................................................503 16.4.1.1 16.4.1.2 16.4.1.3 16.4.1.4 16.4.1.5 16.4.1.6 16.4.1.7 16.4.1.8 Sampling clock Basic operation Preparation Enabling Reception Stopping Reception Receiving Remote Control Signal without Leader in Waiting Leader A Leader only with Low Width Receiving a Remote Control Signal in a Phase Method 17. Watchdog Timer(WDT) 17.1 17.2 17.2.1 17.2.2 17.3 Configuration.......................................................................................................................513 Register................................................................................................................................514 WDMOD(Watchdog Timer Mode Register) ...............................................................................................................514 WDCR (Watchdog Timer Control Register)................................................................................................................516 Operations............................................................................................................................517 xi 17.3.1 17.3.2 17.4 Basic Operation.............................................................................................................................................................517 Operation Mode and Status...........................................................................................................................................517 Operation when malfunction (runaway) is detected...........................................................518 17.4.1 17.4.2 17.5 INTWDT interrupt generation.......................................................................................................................................518 Internal reset generation................................................................................................................................................519 Control register....................................................................................................................520 17.5.1 17.5.2 17.5.3 Watchdog Timer Mode Register (WDMOD)...............................................................................................................520 Watchdog Timer Control Register(WDCR).................................................................................................................520 Setting example.............................................................................................................................................................521 17.5.3.1 17.5.3.2 17.5.3.3 17.5.3.4 Disabling control Enabling control Watchdog timer clearing control Detection time of watchdog timer 18. Key-on Wakeup 18.1 18.2 18.3 Outline.................................................................................................................................523 Block Diagram.....................................................................................................................523 Register in detail..................................................................................................................524 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 18.3.7 18.3.8 18.3.9 18.4 18.5 Register list....................................................................................................................................................................524 KWUPCR0 (Control register 0)....................................................................................................................................524 KWUPCR1 (Control register 1)....................................................................................................................................525 KWUPCR2 (Control register 2)....................................................................................................................................526 KWUPCR3 (Control register 3)....................................................................................................................................527 KWUPPKEY (Port monitor register)...........................................................................................................................528 KWUPCNT (Pull-up cycle register).............................................................................................................................529 KWUPCLR (All interrupt request clear register).........................................................................................................530 KWUPINT (Interrupt monitor register)........................................................................................................................531 Key-on Wakeup Operation..................................................................................................532 Pull-up Function..................................................................................................................533 18.5.1 18.5.2 18.6 In case of using KWUP inputs with pull-up enabled...................................................................................................533 In case of using KWUP inputs with pull-up disabled..................................................................................................534 KWUP input Detection Timing..........................................................................................535 19. Backup module 19.1 19.2 19.3 Features................................................................................................................................537 Block Diagram.....................................................................................................................537 BACKUP Mode Operation.................................................................................................538 19.3.1 Operable peripherals in the BACKUP mode................................................................................................................538 19.3.1.1 19.3.1.2 19.3.1.3 19.3.1.4 Transition to the BACKUP mode Backup Transition Flow Transition Flowchart BACKUP Mode Timing Chart 20. Analog / Digital Converter (ADC) 20.1 20.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 20.3.7 xii Outline.................................................................................................................................543 Configuration.......................................................................................................................544 Registers..............................................................................................................................545 Register list....................................................................................................................................................................545 ADCBAS (Conversion Accuracy Setting Register).....................................................................................................546 ADCLK (Conversion Clock Setting Register).............................................................................................................547 ADMOD0 (Mode Control Register 0)..........................................................................................................................549 ADMOD1 (Mode Control Register 1)..........................................................................................................................550 ADMOD2 (Mode Control Register 2) .........................................................................................................................551 ADMOD3 (Mode Control Register 3)..........................................................................................................................553 20.3.8 ADMOD4 (Mode Control Register 4) .........................................................................................................................554 20.3.9 ADMOD5 (Mode Control Register 5)..........................................................................................................................555 20.3.10 ADREG08 (Conversion Result Register 08)..............................................................................................................556 20.3.11 ADREG19 (AD Conversion Result Register 19).......................................................................................................557 20.3.12 ADREG2A (AD Conversion Result Register 2A).....................................................................................................558 20.3.13 ADREG3B (AD Conversion Result Register 3B)......................................................................................................559 20.3.14 ADREG4C (AD Conversion Result Register 4C)......................................................................................................560 20.3.15 ADREG5D (AD Conversion Result Register 5D).....................................................................................................561 20.3.16 ADREG6E (AD Conversion Result Register 6E)......................................................................................................562 20.3.17 ADREG7F (AD Conversion Result Register 7F).......................................................................................................563 20.3.18 ADREGSP (AD Conversion Result Register SP)......................................................................................................564 20.3.19 ADCMP0 (AD Conversion Result Comparison Register 0)......................................................................................565 20.3.20 ADCMP1 (AD Conversion Result Comparison Register 1)......................................................................................565 20.4 Description of Operations...................................................................................................566 20.4.1 20.4.2 Analog Reference Voltage............................................................................................................................................566 AD Conversion Mode...................................................................................................................................................566 20.4.2.1 20.4.2.2 20.4.3 20.4.4 20.4.5 Normal AD conversion Top-priority AD conversion AD Monitor Function....................................................................................................................................................567 Selecting the Input Channel..........................................................................................................................................568 AD Conversion Details.................................................................................................................................................568 20.4.5.1 20.4.5.2 20.4.5.3 20.4.5.4 20.4.5.5 20.4.5.6 20.4.5.7 Starting AD Conversion AD Conversion Top-priority AD conversion during normal AD conversion Stopping Repeat Conversion Mode Reactivating normal AD conversion Conversion completion Interrupt generation timings and AD conversion result storage register 21. Real Time Clock (RTC) 21.1 21.2 21.3 Function...............................................................................................................................575 Block Diagram.....................................................................................................................575 Detailed Description Register.............................................................................................576 21.3.1 21.3.2 21.3.3 Register List...................................................................................................................................................................576 Control Register.............................................................................................................................................................576 Detailed Description of Control Register.....................................................................................................................578 21.3.3.1 21.3.3.2 21.3.3.3 21.3.3.4 21.3.3.5 21.3.3.6 21.3.3.7 21.3.3.8 21.3.3.9 21.3.3.10 21.3.3.11 21.4 Operational Description.......................................................................................................585 21.4.1 21.4.2 21.4.3 21.5 RTCSECR (Second column register (for PAGE0 only)) RTCMINR (Minute column register (PAGE0/1)) RTCHOURR (Hour column register(PAGE0/1)) RTCDAYR (Day of the week column register(PAGE0/1)) RTCDATER (Day column register (for PAGE0/1 only)) RTCMONTHR (Month column register (for PAGE0 only)) RTCMONTHR (Selection of 24-hour clock or 12-hour clock (for PAGE1 only)) RTCYEARR (Year column register (for PAGE0 only)) RTCYEARR (Leap year register (for PAGE1 only)) RTCPAGER(PAGE register(PAGE0/1)) RTCRESTR (Reset register (for PAGE0/1)) Reading clock data........................................................................................................................................................585 Writing clock data.........................................................................................................................................................585 Entering the Low Power Consumption Mode..............................................................................................................587 Alarm function.....................................................................................................................588 21.5.1 21.5.2 21.5.3 "Low" pulse (when the alarm register corresponds with the clock)...........................................................................588 1Hz cycle "Low" pulse..................................................................................................................................................589 16Hz cycle "Low" pulse................................................................................................................................................589 22. Flash 22.1 22.1.1 22.1.2 22.2 Flash Memory......................................................................................................................591 Features..........................................................................................................................................................................591 Block Diagram of the Flash Memory Section..............................................................................................................593 Operation Mode...................................................................................................................594 xiii 22.2.1 22.2.2 Reset Operation.............................................................................................................................................................595 User Boot Mode (Single chip mode)............................................................................................................................595 22.2.2.1 22.2.2.2 22.2.3 (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1-B) Method 2: Transferring a Programming Routine from an External Host Single Boot Mode..........................................................................................................................................................604 22.2.3.1 22.2.4 22.2.5 22.2.6 22.2.7 22.2.8 22.2.9 (2-A) Using the Program in the On-Chip Boot ROM Configuration for Single Boot Mode............................................................................................................................607 Memory Map.................................................................................................................................................................607 Interface specification....................................................................................................................................................609 Data Transfer Format....................................................................................................................................................610 Restrictions on internal memories.................................................................................................................................610 Transfer Format for Boot Program...............................................................................................................................610 22.2.9.1 22.2.9.2 22.2.9.3 22.2.9.4 22.2.10 RAM Transfer Show Flash Memory SUM Transfer Format for the Show Product Information Chip Erase and Protect Bit Erase Operation of Boot Program.........................................................................................................................................617 22.2.10.1 22.2.10.2 22.2.10.3 22.2.10.4 22.2.10.5 22.2.10.6 22.2.10.7 22.2.10.8 22.2.10.9 22.2.11 22.3 RAM Transfer Command Show Flash Memory SUM Command Show Product Information Command Chip and Protection Bit Erase Command Acknowledge Responses Determination of a Serial Operation Mode Password Calculation of the Show Flash Memory Sum Command Checksum Calculation General Boot Program Flowchart...............................................................................................................................631 On-board Programming of Flash Memory (Rewrite/Erase)...............................................632 22.3.1 Flash Memory................................................................................................................................................................632 22.3.1.1 22.3.1.2 22.3.1.3 22.3.1.4 22.3.1.5 22.3.1.6 22.3.2 Block Configuration Basic Operation Reset (Hardware reset) Commands Flash control / status register List of Command Sequences Address bit configuration for bus write cycles.............................................................................................................642 22.3.2.1 Flowchart 23. ROM protection 23.1 23.2 23.2.1 23.2.2 23.3 23.3.1 23.3.2 23.4 23.4.1 23.4.2 Outline.................................................................................................................................647 Features................................................................................................................................647 Write/ erase-protection function....................................................................................................................................647 Security function............................................................................................................................................................647 Register................................................................................................................................648 FCFLCS (Flash control register)...................................................................................................................................649 FCSECBIT(Security bit register)..................................................................................................................................650 Writing and erasing.............................................................................................................651 Protection bits................................................................................................................................................................651 Security bit.....................................................................................................................................................................651 24. RAM Interface 24.1 24.1.1 Register List.........................................................................................................................653 RCWAIT(RAM Interface Register) .............................................................................................................................653 25. Port Section Equivalent Circuit Schematic 25.1 25.2 xiv PA0 to 7, PB0 to 7, PP1, PP3 to 5.....................................................................................655 PE0 to 7, PF0 to 4, PG0 to 7, PI0, PL0 to 7, PM0 to 7, PN0 to 3, PP0, PP2, PP6..........655 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.10 25.11 PI1........................................................................................................................................656 PI2, PI3................................................................................................................................656 PJ0 to 7................................................................................................................................656 RESET, NMI.......................................................................................................................657 MODE, SWCLK.................................................................................................................657 SWDIO................................................................................................................................657 X1, X2.................................................................................................................................658 XT1, XT2..........................................................................................................................658 VREFH, AVSS..................................................................................................................658 26. Electrical Characteristics 26.1 26.2 26.3 26.4 26.5 26.6 Absolute Maximum Ratings................................................................................................659 DC Electrical Characteristics (1/3).....................................................................................660 DC Electrical Characteristics (2/3).....................................................................................661 DC Electrical Characteristics (3/3).....................................................................................662 10-bit ADC Electrical Characteristics.................................................................................663 AC Electrical Characteristics..............................................................................................664 26.6.1 26.6.2 AC measurement condition...........................................................................................................................................664 Static memory controller (SMC)...................................................................................................................................665 26.6.2.1 26.6.2.2 26.6.2.3 26.6.3 Serial Interface (SIO/UART)........................................................................................................................................668 26.6.3.1 26.6.4 I2C Mode Clock-Synchronous 8-Bit SIO mode SSP Controller (SSP)....................................................................................................................................................674 26.6.5.1 26.6.5.2 26.6.6 I/O Interface mode Serial Bus Interface (I2C/SIO)......................................................................................................................................671 26.6.4.1 26.6.4.2 26.6.5 Basic Bus cycle (Read) BASIC Bus Cycle (Write) Example of Read / Write cycle SSP SPI mode (Master) SSP SPI mode (Slave) 16-bit timer / even counter............................................................................................................................................678 26.6.6.1 26.6.6.2 Event counter Capture 26.6.7 External Interrupt...........................................................................................................................................................679 26.6.8 NMI................................................................................................................................................................................679 26.6.9 SCOUT Pin AC Characteristic.....................................................................................................................................679 26.6.10 Debug communication.................................................................................................................................................680 26.6.11 ETM Trace...................................................................................................................................................................681 26.7 Flash Characteristics............................................................................................................681 26.7.1 26.8 Erase / Write Characteristics.........................................................................................................................................681 Oscillation Circuit...............................................................................................................682 26.8.1 26.8.2 26.8.3 26.9 Ceramic oscillator..........................................................................................................................................................682 Crystal oscillator............................................................................................................................................................682 Precaution for designing printed circuit boad...............................................................................................................683 Handling Precaution............................................................................................................684 26.9.1 Notice of Power Supply................................................................................................................................................684 26.9.1.1 26.9.1.2 Notice of Power on Notice of Power on again 27. Package Dimensions xv xvi TMPM361F10FG TMPM361F10FG The TMPM361F10FG is a 32-bit RISC microprocessor series with an ARM Cortex-M3 microprocessor core. Product name TMPM361F10FG ROM (FLASH) 1024 Kbyte RAM Package 64 Kbyte P-LQFP100-1414-0.50H Features of the TMPM361F10FG are as follows : 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb-2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ New 32-bit Thumb instructions for improved performance ・ New Thumb mixed 16- / 32-bit instruction set can produce faster, more efficient code. b. Both high performance and low power consumption have been achieved. [High performance] ・ Both high performance and low power consumption have been achieved. ・ Division takes between 2 and 12 cycles depending on dividend and devisor [Low Power consumption] ・ Optimized design using a low power consumption library ・ Standby function that stops the operation of the micro controller core c. High-speed interrupt response suitable for real-time control ・ An interruptible long instruction ・ Stack push automatically handled by hardware 2. On Chip program memory and data memory ・ On chip RAM : 64Kbyte ・ On chip Flash ROM : 1024Kbyte 3. Static memory controller (SMC) ・ Up to 16Mbytes access area (Program / Data) ・ External data bus (Multiplex bus) : 16-bit data bus width ・ Chip select / Wait controller : 4 channels 4. DMA controller (DMAC) : 2 channels Transfer can support on chip Memory / Peripheral I/O / External memory Page 1 2013/5/31 1.1 Features TMPM361F10FG 5. 16-bit timer / event counter (TMRB) : 16 channels ・ 16-bit interval timer mode ・ 16-bit event counter mode ・ 16-bit PPG output (4channel timer can start synchronously) ・ Input capture function 6. Watchdog timer (WDT) : 1 channel Watchdog timer generates a reset or a non-maskable interrupt (NMI). 7. Serial channnel (SIO/UART) : 5 channels Either UART mode or I/O interface can be selected (4byte FIFO equipped) 8. Serial bus interface (I2C/SIO) : 3 channels Either I2C bus mode or synchronous 8-bit SIO mode can be selected. 9. I2C bus : 1 channel 10. Synchronous serial port (SSP) : 1 channel ・ Communication protocol that includes SPI: 3 types (SPI/SSI/Microwire) ・ Baud rate: Master mode: 16Mbps (max.), Slave mode: 5.3Mbps (max.) 11. CEC function (CEC) : 1 channel Transmision and reception per 1 byte 12. Remote control signal preprocessor (RMC) : 1 channel Can receive up to 72bit data at a time 13. 10-bit AD converter (ADC) : 8 channels ・ Start up with 16-bit timer ・ Fixed channel / scan mode ・ Single / repeat mode ・ AD monitoring 2 channels ・ Conversion time 1.15 μsec (@ fsys = 40 MHz) 14. Key-on wake-up (KWUP) : 4 channels Dynamic pull-up 15. Real time clock (RTC) : 1channel ・ Clock (hour, minute and second) ・ Calendar (month, week, date and leap year) ・ Alarm (Alarm output) ・ Alarm interrupt 16. BACKUP module (BUPMD) Low power consumption can be realized by shutdown the power supply except specific part. - BACKUP RAM : 8KB 2013/5/31 Page 2 TMPM361F10FG - Port keep (Keep port status when BACKUP mode is set) CEC Function Remote control signal preprocessor function Key-on wake-up function Real time clock function 17. Interrupt source ・ Internal 54 factors : The order of precedence can be set over 7 levels. (execpt the watchdog timer interrupt) ・ External 10 factors : The order of precedence can be set over 7 levels. 18. Non-maskable interrupt (NMI) Non-maskable interrupt (NMI) is generated by a watchdog timer or a NMI pin. 19. Input / output ports (PORT) : 76 pins I/O pin : 68 pins Input pin : 8 pins 20. Low power consumption mode IDLE2, IDLE1, SLEEP, STOP, SLOW, BACKUP (BACKUP SLEEP, BACKUP STOP) 21. Clock generator (CG) ・ On chip PLL (Quadrupled or octuple can be selected.) ・ Clock gear function : The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 22. Endian Little endian 23. Debug interface SWD / SWV / TRACE (DATA 4bit) 24. Maximum operating frequency : 64MHz 25. Operating voltage range 2.7 V to 3.6 V (with on-chip regulator) 26. Temperature range ・ -20 degrees to 85 degrees (except Flash writing / erasing) ・ 0 degrees to 70 degrees (during Flash writing / erasing) 27. Package P-LQFP100-1414-0.50H (14 mm x 14 mm, 0.5 mm pitch) Page 3 2013/5/31 1.2 Block Diagram 1.2 TMPM361F10FG Block Diagram ETM Cortex-M3 SWD NVIC DMA Controller AHB Lite Bus Matrix FLASH (1MB) CG RAM (56KB) PORT Backup RAM (8KB) WDT AHB to I/O Bridge AHB Lite Bus 0 SMC RTC 16bit Timer (16 ch) SIO/UART (4byte FIFO) (5ch) I2C/SIO (3ch) I2C 10bit ADC (8ch) BOOT ROM CEC RMC (1ch) KWUP AHB to APB Bridge SSP Figure 1-1 TMPM361F10FG Block Diagram 2013/5/31 Page 4 100 Page 5 25 20 15 85 10 5 55 60 65 70 75 RVDD3 XT1 XT2 DVDD3A X1 DVSS X2 DVDD3B DVSS PI2/INTE PI3/INTF NMI TEST1 TEST2 PI0/BOOT Pl1/CEC AVDD3 PJ0/AIN0 PJ1/AIN1 PJ2/AIN2 PJ3/AIN3/ADTRG PJ4/AIN4/KWUP0 PJ5/AIN5/KWUP1 PJ6/AIN6/KWUP2 PJ7/AIN7/KWUP3 1 PG7/INT7/WDTOUT PG6/SCK2/CS3 PG5/SCL2/SI2/TB9IN1 PG4/SDA2/SO2/TB9IN0 PG3/INT6/CS1 PG2/SCK1/CS0 PG1/SCL1/SI1/TB7IN1 PG0/SDA1/SO1/TB7IN0 PF4/TRACEDATA3 PF3/TRACEDATA2 PF2/TEACEDATA1 PF1/TRACEDATA0/SWV PF0/TRACECLK SWCLK SWDIO DVSS DVDD3B PE7/INT5/SCOUT PE6/A23/SCLK0/CTS0 PE5/A22/RXD0 PE4/A21/TXD0 PE3/A20/TB6IN1 PE2/A19/TB6IN0 PE1/A18/TB5IN1 PE0/A17/TB5IN0 1.3 AVSS VREFH RESET MODE PL0/SDA0/SO0/TB0OUT PL1/SCL0/SI0/TB1OUT PL2/SCK0/TB2OUT PL3/INT0/TB3OUT PL4/TXD1/TB4OUT/SDA3 PL5/RXD1/TB5OUT/SCL3 PL6/SCLK1/TB6OUT/CTS1 PL7/INT1/TB7OUT DVSS PM0/SCLK2/TB1N0/CTS2 PM1/TXD2/TB1IN1 PM2/RXD2/ALARM PM3/INT2/TB3OUT PM4/SCLK3/CTS3 PM5/TXD3 PM6/RXD3 PM7/INT3 PN0/TXD4 PN1/RXD4 PN2/SCLK4/TB2IN0/CTS4 PN3/INT4/TB2N1/RMC0 TMPM361F10FG Pin layout (Top view) Figure 1-2 shows the pin layout of TMPM361F10FG. 50 80 45 TMPM361F10FG 40 90 35 Top View 95 30 PB7/AD15 PB6/AD14 PB5/AD13 PB4/AD12 PB3/AD11 PB2/AD10 PB1/AD9 PB0/AD8 PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4 PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0 DVSS DVDD3B PP6/ALE PP5/OE/SPFSS PP4/WE/SPCLK PP3/BLS1/SPDI PP2/BLS0/SPDO PP1 PP0/CS2 Figure 1-2 Pin Layout (LQFP100) 2013/5/31 1.4 Pin names and Functions 1.4 TMPM361F10FG Pin names and Functions Table 1-1 sort input and output pins of TMPM361F10FG by pin or port. Table 1-1 Pin Names and Functions Sorted by Pin (1/6) Type Pin No. PS 1 AVSS - PS 2 VREFH - Function 3 RESET Input Control 4 MODE Input PL0 I/O I/O port Function 5 SDA0/SO0 I/O Data in I2C mode / Data in SIO mode TB0OUT Output 16-bit timer / event counter output PL1 I/O I/O port SCL0/SI0 I/O Clock in I2C mode / Data in SIO mode TB1OUT Output 16-bit timer / event counter output PL2 I/O I/O port SCK0 I/O Clock in SIO mode TB2OUT Output 16-bit timer / event counter output PL3 I/O I/O port INT0 Input External interrupt pin TB3OUT Output 16-bit timer / event counter output PL4 I/O I/O port TXD1 Output Serial channel sending serial data TB4OUT Output 16-bit timer / event counter output SDA3 I/O I2C data PL5 I/O I/O port RXD1 Input Serial channel receiving serial data TB5OUT Output 16-bit timer / event counter output SCL3 I/O I2C clock PL6 I/O I/O port SCLK1 I/O Serial channel clock pin TB6OUT Output 16-bit timer / event counter output CTS1 Input Serial channel handshake input pin PL7 I/O I/O port INT1 Input External interrupt pin TB7OUT Output 16-bit timer / event counter output DVSS - GND pin Function Function Function Function Function Function Function PS 2013/5/31 6 7 8 9 10 11 12 13 PIn Name Input / Output Function GND pin for AD converter (note) AVSS must be connected to GND even if the AD converter is not used. Power supply pin for AD converter (note) VREFH must be connected to power supply even if AD converter is not used. Reset input pin (note) With a pull-up and a noise filter (about 30 ns (typ.)) Mode pin (note) MODE pin must be connected to GND. Page 6 TMPM361F10FG Table 1-1 Pin Names and Functions Sorted by Pin (2/6) Type Function Function Function Function Function Pin No. 14 15 16 17 18 Function 19 Function 20 Function 21 Function 22 Function 23 Function Function 24 25 Function 26 Function 27 Function 28 Function 29 PIn Name Input / Output Function PM0 I/O I/O port SCLK2 I/O Serial channel clock pin TB1IN0 Input Inputting the 16-bit timer / event countercapture trigger CTS2 Input Serial channel handshake input pin PM1 I/O I/O port TXD2 Output Serial channel sending serial data TB1IN1 Input Inputting the 16-bit timer / event countercapture trigger PM2 I/O I/O port RXD2 Input Serial channel receiving serial data ALARM Output Alarm output PM3 I/O I/O port INT2 Input External interrupt pin TB3OUT Output 16-bit timer / event counter output PM4 I/O I/O port SCLK3 I/O Serial channel clock pin CTS3 Input Serial channel handshake input pin PM5 I/O I/O port TXD3 Output Serial channel sending serial data PM6 I/O I/O port RXD3 Input Serial channel receiving serial data PM7 I/O I/O port INT3 Input External interrupt pin PN0 I/O I/O port TXD4 Output Serial channel sending serial data PN1 I/O I/O port RXD4 Input Serial channel receiving serial data PN2 I/O I/O port SCLK4 I/O Serial channel clock pin TB2IN0 Input Inputting the 16-bit timer / event countercapture trigger CTS4 Input Serial channel handshake input pin PN3 I/O I/O port INT4 Input External interrupt pin TB2IN1 Input Inputting the 16-bit timer / event countercapture trigger RMC0 Input Inputting signal to remote controller PP0 I/O I/O port CS2 Output Chip select pin PP1 I/O I/O port PP2 I/O I/O port BLS0 Output Byte lane pin SPDO Output SSP data output pin PP3 I/O I/O port BLS1 Output Byte lane pin SPDI Input SSP data input pin Page 7 2013/5/31 1.4 Pin names and Functions TMPM361F10FG Table 1-1 Pin Names and Functions Sorted by Pin (3/6) Type Pin No. Function 30 Function 31 PIn Name Input / Output Function PP4 I/O I/O port WE Output Write strobe pin SPCLK I/O SSP clock pin PP5 I/O I/O port OE Output Output enable pin SPFSS I/O SSP frame / slave select pin PP6 I/O I/O port ALE Output Address latch enable pin Function 32 PS 33 DVDD3B - Power supply pin PS 34 DVSS - GND pin Function 35 PA0 I/O I/O port AD0 I/O Address and data bus Function 36 PA1 I/O I/O port AD1 I/O Address and data bus Function 37 PA2 I/O I/O port AD2 I/O Address and data bus Function 38 PA3 I/O I/O port AD3 I/O Address and data bus Function 39 PA4 I/O I/O port AD4 I/O Address and data bus Function 40 PA5 I/O I/O port AD5 I/O Address and data bus Function 41 PA6 I/O I/O port AD6 I/O Address and data bus Function 42 PA7 I/O I/O port AD7 I/O Address and data bus Function 43 PB0 I/O I/O port AD8 I/O Address and data bus Function 44 PB1 I/O I/O port AD9 I/O Address and data bus Function 45 PB2 I/O I/O port AD10 I/O Address and data bus Function 46 PB3 I/O I/O port AD11 I/O Address and data bus Function 47 PB4 I/O I/O port AD12 I/O Address and data bus Function 48 PB5 I/O I/O port AD13 I/O Address and data bus Function 49 PB6 I/O I/O port AD14 I/O Address and data bus Function 50 PB7 I/O I/O port AD15 I/O Address and data bus 2013/5/31 Page 8 TMPM361F10FG Table 1-1 Pin Names and Functions Sorted by Pin (4/6) Type Pin No. Function 51 Function Function Function Function Function Function Function 52 53 54 55 56 57 58 PIn Name Input / Output Function PE0 I/O I/O port A17 Output Address bus TB5IN0 Input Inputting the 16-bit timer / event countercapture trigger PE1 I/O I/O port A18 Output Address bus TB5IN1 Input Inputting the 16-bit timer / event countercapture trigger PE2 I/O I/O port A19 Output Address bus TB6IN0 Input Inputting the 16-bit timer / event countercapture trigger PE3 I/O I/O port A20 Output Address bus TB6IN1 Input Inputting the 16-bit timer / event countercapture trigger PE4 I/O I/O port A21 Output Address bus TXD0 Output Serial channel sending serial data PE5 I/O I/O port A22 Output Address bus RXD0 Input Serial channel receiving serial data PE6 I/O I/O port A23 Output Address bus SCLK0 I/O Serial channel clock pin CTS0 Input Serial channel handshake input pin PE7 I/O I/O port INT5 Input External interrupt pin SCOUT Output Internal clock output pin PS 59 DVDD3B - Power supply pin PS 60 DVSS - GND pin Debug 61 SWDIO I/O Debug pin Debug 62 SWCLK I/O Debug pin PF0 I/O I/O port TRACECLK Output Debug pin PF1 I/O I/O port TRACEDATA0 Output Debug pin SWV Output Debug pin PF2 I/O I/O port TRACEDATA1 Output Debug pin PF3 I/O I/O port TRACEDATA2 Output Debug pin PF4 I/O I/O port TRACEDATA3 Output Debug pin Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug 63 64 65 66 67 Page 9 2013/5/31 1.4 Pin names and Functions TMPM361F10FG Table 1-1 Pin Names and Functions Sorted by Pin (5/6) Type Pin No. Function 68 Function Function Function Function Function Function Function 69 70 71 72 73 74 75 PIn Name Input / Output Function PG0 I/O I/O port SDA1/SO1 I/O Data in I2C mode / Data in SIO mode TB7IN0 Input Inputting the 16-bit timer / event countercapture trigger PG1 I/O I/O port SCL1/SI1 I/O Clock in I2C mode / Data in SIO mode TB7IN1 Input Inputting the 16-bit timer / event countercapture trigger PG2 I/O I/O port SCK1 I/O Clock in SIO mode CS0 Output Chip select pin PG3 I/O I/O port INT6 Input External interrupt pin CS1 Output Chip select pin PG4 I/O I/O port SDA2/SO2 I/O Data in I2C mode / Data in SIO mode TB9IN0 Input Inputting the 16-bit timer / event countercapture trigger PG5 I/O I/O port SCL2/SI2 I/O Clock in I2C mode / Data in SIO mode TB9IN1 Input Inputting the 16-bit timer / event countercapture trigger PG6 I/O I/O port SCK2 I/O Clock in SIO mode CS3 Output Chip select pin PG7 I/O I/O port INT7 Input External interrupt pin WDTOUT Output Watchdog timer output pin PS 76 RVDD3 - Power supply pin Clock 77 XT1 Input Connected to a low-speed oscillator. Clock 78 XT2 Output Connected to a low-speed oscillator. PS 79 DVDD3A - Power supply pin Clock 80 X1 Input Connected to a high-speed oscillator. PS 81 DVSS - GND pin Clock 82 X2 Output Connected to a high-speed oscillator. PS 83 DVDD3B - Power supply pin PS 84 DVSS - GND pin Function 85 PI2 I/O I/O port INTE Input External interrupt pin Function 86 PI3 I/O I/O port INTF Input External interrupt pin 2013/5/31 Page 10 TMPM361F10FG Table 1-1 Pin Names and Functions Sorted by Pin (6/6) Type Pin No. Control 87 NMI Input Control 88 TEST1 - Control 89 TEST2 - PI0 I/O BOOT Input PI1 I/O I/O port CEC I/O CEC pin Function 90 Function 91 PIn Name Input / Output Function Non-maskable interrupt (note) With a noise filter (about 30ns (typical value)) TEST pin (note) TEST pin must be left OPEN. TEST pin (note) TEST pin must be left OPEN. I/O port Setting boot pin TMPM361F10FG goes into single boot mode by sampling "Low" at the rising edge of a RESET pin. (note) Nch open drain port PS 92 Function 93 Function 94 Function 95 Function 96 Function Function Function Function 97 98 99 100 Power suppy pin for the AD converter AVDD3 - PJ0 Input Input port AIN0 Input Analog input PJ1 Input Input port AIN1 Input Analog input PJ2 Input Input port AIN2 Input Analog input PJ3 Input Input port AIN3 Input Analog input ADTRG Input External trigger input for AD converter PJ4 Input Input port AIN4 Input Analog input KWUP0 Input Key-on wake-up pin PJ5 Input Input port AIN5 Input Analog input KWUP1 Input Key-on wake-up pin PJ6 Input Input port AIN6 Input Analog input KWUP2 Input Key-on wake-up pin PJ7 Input Input port AIN7 Input Analog input KWUP3 Input Key-on wake-up pin (note) AVDD3 must be connected to power supply even if AD converter is not used. Page 11 2013/5/31 1.5 Pin Numbers and Power Supply Pins 1.5 TMPM361F10FG Pin Numbers and Power Supply Pins Table 1-2 PIn Numbers and Power Supplies Power supply 2013/5/31 Voltage range Pin No. PIn mane PA,PB,PE,PF,PG,PI,PL,PM,PN,PP DVDD3B 33,59,83 DVDD3A 79 X1,X2 AVDD3 92 PJ RVDD3 76 − 2.7 to 3.6V Page 12 XT1,XT2,RESET,NMI,MODE TMPM361F10FG 2. Processor Core The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor core). For information on the operations of this processor core, please refer to the "Cortex-M3 Technical Reference Manual" issued by ARM Limited.This chapter describes the functions unique to the TX03 series that are not explained in that document. 2.1 Information on the processor core The following table shows the revision of the processor core in the TMPM361F10FG. Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M series processors" in the following URL: http://infocenter.arm.com/help/index.jsp 2.2 Product Name Core Revision TMPM361F10FG r2p0 Configurable Options The Cortex-M3 core has optional blocks. The optional blocks of the revision r2p0 are ETM™, MPU and WIC. The following table shows the configurable options in the TMPM361F10FG. Implementation Configurable Options Two literal comparators FPB Six instruction comparators DWT Four comparators ITM Present MPU Absent ETM Present AHB-AP Present AHB Trace Macrocell Interface Absent TPIU Present WIC Absent Debug Port Serial wire Page 13 2013/5/31 2. 2.3 Processor Core Exceptions/ Interruptions 2.3 TMPM361F10FG Exceptions/ Interruptions Exceptions and interruptions are described in the following section. 2.3.1 Number of Interrupt Inputs The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM361F10FG has 64 interrupt inputs. The number of interrupt inputs is reflected in bit of NVIC register. In this product, if read bit, 0x01 is read out. 2.3.2 Number of Priority Level Interrupt Bits The Cortex-M3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits. TMPM361F10FG has 3 priority level interrupt bits. The number of priority level interrupt bits is used for assigning a priority level in the interrupt priority registers and system handler priority registers. 2.3.3 SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. For the detail of SysTick exception, refer to the section of "SysTick" in the exception and the register of SysTick in the NVIC register. 2.3.4 SYSRESETREQ The Cortex-M3 core outputs SYSRESETREQ signal when bit of Application Interrupt and Reset Control Register are set. TMPM361F10FG provides the same operation when SYSRESETREQ signal are output. Note:The reset operation by can not used while in SLOW mode. 2.3.5 LOCKUP When irreparable exception generates, the Cortex-M3 core outputs LOCKUP signal to show a serious error included in software. TMPM361F10FG does not use this signal. To return from LOCKUP status, it is necessary to use non-maskable interruput (NMI) or reset. 2.3.6 Auxiliary Fault Status register The Cortex-M3 core provides auxiliary fault status registers to supply additional system fault information to software. However, TMPM361F10FG is not defined this function. If auxiliary fault status register is read, always "0x0000_0000" is read out. 2013/5/31 Page 14 TMPM361F10FG 2.4 Events The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV instruction execution. If an event is input, the core returns from low-power consumption mode caused by WFE instruction. TMPM361F10FG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 Power Management The Cortex-M3 core provides power management system which uses SLEEPING signal and SLEEPDEEP signal. SLEEPDEEP signals are output when bit of System Control Register is set. These signals are output in the following circumstances: -Wait-For-Interrupt (WFI) instruction execution -Wait-For-Event (WFE) instruction execution -the timing when interrupt-service-routine (ISR) exit in case that bit of System Control Register is set. TMPM361F10FG does not use SLEEPDEEP signal so that bit must not be set. And also event signal is not used so that please do not use WFE instruction. For detail of power management, refer to the Chapter "Clock/Mode control." 2.6 Exclusive access In Cortex-M3 core, the DCode bus system supports exclusive access. However TMPM361F10FG does not use this function. Page 15 2013/5/31 2. 2.6 Processor Core Exclusive access 2013/5/31 TMPM361F10FG Page 16 TMPM361F10FG 3. Debug Interface 3.1 Specification Overview The TMPM361F10FG contains the Serial Wire Debug Port (SW-DP) unit for interfacing with the debugging tools and the Embedded Trace MacrocellTM (ETM) unit for instruction trace output. Trace data output to the dedicated pins (TRACEDATA[3:0]) via the on-chip Trace Port Interface Unit (TPIU). For details about SW-DP, ETM and TPIU, refer to "Cortex-M3 Technical Reference Manual". 3.2 SW-DP SW-DP supports the two-pin Serial Wire Debug Port (SWCLK, SWDIO). 3.3 ETM ETM supports four data signal pin (TRACEDATA[3:0]), one clock signal pin (TRACECLK) and trace output from SWV. Page 17 2013/5/31 3. Debug Interface 3.4 Pin functions 3.4 TMPM361F10FG Pin functions The debug interface pin can also be used as general purpose port (PF0 to PF4). Table 3-1 SW-DP,ETM Debug Function SW-DP pin name Port name SW debug function I/O Comments Serial Wire Data Input/Output SWDIO − I/O SWCLK − Input TRACECLK PF0 Output TRACEDATA0 / SWV PF1 Output TRACEDATA1 PF2 Output TRACE DATA Output1 TRACEDATA2 PF3 Output TRACE DATA Output2 TRACEDATA3 PF4 Output TRACE DATA Output3 (Always pull-up) Serial Wire Clock (Always pull-down) TRACE Clock Output TRACE DATA Output0 / Serial Wire Viewer Output After reset, PF0 to PF4 pins are configured as general purpose ports. The functions of the debug interface pins need to be programmed as required. Table 3-2 summarizes the debug interface pin functions and related port settings after reset. Table 3-2 The Debug Interface Pins functions and Related Port Setting after Reset Port Name (Bit Name) Value of related port setting after reset Debug Function Function Input Output Pull-up Pull-down (PxFR) (PxIE) (PxCR) (PxPUP) (PxPDN) PF0 TRACECLK 0 0 0 0 − PF1 TRACEDATA0 / SWV 0 0 0 0 − PF2 TRACEDATA1 0 0 0 0 − PF3 TRACEDATA2 0 0 0 0 − PF4 TRACEDATA3 0 0 0 0 − − : Don’t care 2013/5/31 Page 18 TMPM361F10FG 3.5 Peripheral Functions in Halt Mode When the Cortex-M3 core enters in the halt mode, the watch-dog timer (WDT) automatically stops. Other peripheral functions continue operate. 3.6 Reset Vector Break TMPM330FDFG/FYFG/FWFG is prohibited from transmission with debug tools while reset caused by RESET pin is effective.When setting a stop by using reset vector, set the following procedure after reset; set break points from the debug tools, then set the application interrupt and the bit of the reset control register to reset again. Note:Do not reset with in SLOW mode. 3.7 Connection with a Debug Tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are connected with external pull-up or pull-down, please pay attention to input level. Page 19 2013/5/31 3. 3.7 Debug Interface Connection with a Debug Tool 2013/5/31 TMPM361F10FG Page 20 TMPM361F10FG 4. Memory Map 4.1 Memory Map The memory maps for the TMPM361F10FG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. The special function register (SFR) indicates I/O ports and control registers for the peripheral function. The SRAM and SFR regions are all included in the bit-band region. The CPU register region is the processor core’s internal register region. For more information on the each region, see the "Cortex-M3 Technical Reference Manual". Note that access to regions indicated as "Fault" causes a memory fault if memory faults are enabled or a hard fault if memory faults are disabled. Do not access the vendor-specific region. Page 21 2013/5/31 4. 4.1 Memory Map Memory Map 4.1.1 TMPM361F10FG Memory map of the TMPM361F10FG Figure 4-1 shows the memory map of the TMPM361F10FG. [))))B)))) Vender-Specific [(B [()B)))) CPU Register Region [(B Fault [))B)))) [B External Bus Area Fault [))B)))) [))B) SFR Fault [)B))) [&B SFR Fault [B))) [B SFR Fault [B))) [B SFR Fault [B)))) [B( [B'))) [B Backup RAM (8K) Internal RAM (56K) Fault [)B)))) [B Internal ROM (1024K) Figure 4-1 Memory map 2013/5/31 Page 22 TMPM361F10FG 4.2 SFR area detail This section contains the list of addresses in the SFR are (0x4000_0000 to 0x4000_5FFF, 0x4004_0000 to 0x4004_1FFF, 0x400C_0000 to 0x400F_4FFF, 0x41FF_F000 to 0x41FF_FFFF) assigned to peripheral function. Access to the Reserved areas in the Table 4-1 is prohibited. As for the SFR area, reading the areas not described in the Table 4-1 yields undefined value. Writing these area is ignored. Table 4-1 SFR area detail Start Address 0x4000_0000 0x4000_1000 End Address 0x4000_0FFF 0x4000_1FFF Peripheral DMAC SMC 0x4000_2000 0x4000_2FFF Reserved 0x4000_3000 0x4000_3FFF Reserved 0x4000_4000 0x4000_5FFF Reserved 0x4004_0000 0x4004_0FFF SSP 0x4004_1000 0x4004_1FFF Reserved 0x400C_0000 0x400D_0000 0x400C_FFFF Port Reserved 0x4000_0028 to 0x4000_0034 to 0x4000_002F 0x4000_0037 0x4000_0500 to 0x4000_050F 0x4000_0FE0 to 0x4000_0FFF 0x4000_1000 to 0x4000_1003 0x4000_1008 to 0x4000_100F 0x4000_1020 to 0x4000_1023 0x4000_1200 to 0x4000_1207 0x4000_1E00 to 0x4000_1E0B 0x4000_1FE0 to 0x4000_1FFF 0x4000_3058 to 0x4000_305F 0x4004_0028 to 0x4004_0FFF 0x400C_0200 to 0x400C_03FF 0x400C_0700 to 0x400C_07FF 0x400C_0A00 to 0x400C_0AFF 0x400C_0E00 to 0x400C_0EFF 0x400D_FFFF Timer B (16ch) 0x400E_0000 0x400E_04FF I2C/SIO(3ch) / I2C(1ch) 0x400E_0400 to 0x400E_041F 0x400E_1000 0x400E_1BFF SIO/UART(5ch) 0x400E_1500 - 0x400E_1BFF 0x400E_2000 0x400E_203F CEC 0x400E_3000 0x400E_31FF RMC(1ch) 0x400F_0000 0x400F_005B ADC(8ch) 0x400F_1000 0x400F_108F KWUP 0x400F_2000 0x400F_2007 WDT 0x400F_3000 0x400F_300F RTC 0x400F_4000 0x400F_4037 CG 0x41FF_F000 0x41FF_F03F FLASH 0x41FF_F040 0x41FF_F057 Reserved 0x41FF_F058 0x41FF_F05B RAMWAIT 0x41FF_F060 0x41FF_F093 Reserved 0x41FF_F0A0 0x41FF_F0BB Reserved 0x41FF_F100 0x41FF_F103 SMCMOD Page 23 0x400E_3100 to 0x400E_313F 0x400F_001C to 0x400F_001F 0x400F_0024 to 0x400F_002F 0x400F_1010 to 0x400F_107F 0x400F_4028 to 0x400F_402D 0x400F_4036 to 0x4000_4FFF 0x41FF_F000 to 0x41FF_F007 0x41FF_F014 to 0x41FF_F017 0x41FF_F018 to 0x41FF_F01B 0x41FF_F024 to 0x41FF_F02C 0x41FF_F033 to 0x41FF_F037 0x400F_300D 2013/5/31 4. 4.2 Memory Map SFR area detail 2013/5/31 TMPM361F10FG Page 24 TMPM361F10FG 5. Reset The TMPM361F10FG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from , refer to "Cortex-M3 Technical Reference Manual". Note:Do not reset with in SLOW mode. 5.1 Cold reset The power-on sequence must consider the time for the internal regulator and oscillator to be stable. In the TMPM361F10FG, the internal regulator requires at least 700 μs to be stable. The time required to achieve stable oscillation varies with system. At cold reset, the external reset pin must be kept "Low" for a duration of time sufficiently long enough for the internal regulator and oscillator to be stable. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400μs. Figure 5-1 shows the power-on sequence. RVDD3, DVDD3A, DVDD3B, AVDD3 2.7 V 0V 0.1ms/V (min.) 700 μs(min.) RESET (External reset) High-speed oscillation 12 cycle (min.) 400 μs(min.) Internal reset The case where it takes 700 μs or more for stable oscillation RESET (External reset) High-speed oscillation 12 cycle(min.) 400 μs(min.) Internal reset Figure 5-1 Cold Reset Sequence Page 25 2013/5/31 5. 5.1 Reset Cold reset TMPM361F10FG Note 1: The power supply must be raised (from 0V to 2.7V) at a speed of 0.1ms/V or slower. Note 2: Turn on the power while the RESET pin is fixed to "Low". When all the power supplies are stabilized within operating voltage, release the reset. 2013/5/31 Page 26 TMPM361F10FG 5.2 Warm reset 5.2.1 Reset period As a precondition, ensure that the power supply voltage is within the operating range and the internal highfrequency oscillator is providing stable oscillation. To reset the TMPM361F10FG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400μs. 5.3 After reset A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal function registers. The processor core's system debug components (FPB, DWT, ITM) register, the clock generator's CGRSTFLG register and the FCSECBIT register are initialized by a only cold reset. After reset, the PLL multiplication circuit is inactive and must be enabled in the CGPLLSEL register if needed. When the reset exception handling is completed, the program branches to the reset interrupt service routine. Note:The reset operation may alter the internal RAM state. Page 27 2013/5/31 5. 5.3 Reset After reset 2013/5/31 TMPM361F10FG Page 28 TMPM361F10FG 6. Clock / Mode Control 6.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL clock multiplication circuit and oscillator. There is also the low power consumption mode which can reduce power consumption by mode transitions. This chapter describes how to control clock operating modes and mode transitions. The clock/mode control block has the following functions: ・ ・ ・ ・ Controls the system clock Controls the prescaler clock Controls the PLL multiplication circuit Controls the warm-up timer In addition to NORMAL mode, the TMPM361F10FG can operate low power mode to reduce power consumption according to its usage conditions. Page 29 2013/5/31 6. 6.2 Clock / Mode Control Registers 6.2 TMPM361F10FG Registers 6.2.1 Register List The following table shows the CG-related registers and addresses. Base Address = 0x400F_4000 Register name Address (Base+) System control register 2013/5/31 CGSYSCR 0x0000 Oscillation control register CGOSCCR 0x0004 Standby control register CGSTBYCR 0x0008 PLL selection register CGPLLSEL 0x000C System clock selection register CGCKSEL 0x0010 Page 30 TMPM361F10FG 6.2.2 CGSYSCR (System control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 - - - FCSTOP - - bit symbol After reset 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 bit symbol - - FPSEL1 FPSEL0 - After reset 0 0 0 0 0 0 2 7 6 5 4 3 bit symbol - - - - - After reset 0 0 0 0 0 Bit 16 SCOSEL Bit Symbol Type PRCK 0 0 1 0 GEAR 0 0 0 Function 31-24 − R Read as "0". 23 − R/W Write as "0". 22-21 − R Read as "0". 20 FCSTOP R/W Stops AD converter clock 0: Operated 1: Stopped It is possible to stop AD converter clock. After reset, AD converter clock is operated. If this bit is set to "1", make sure to confirm that AD conversion is finished or stopped. 19-18 − R Read as "0". 17-16 SCOSEL[1:0] R/W SCOUT output 00: fs 01: fsys/2 10: fsys 11: φT0 Enables to output the specified clock from SCOUT pin. 15-14 − R Read as "0". 13 FPSEL1 R/W Selects φT0 source clock 0: clock selected by 1: fs 12 FPSEL0 R/W Selects fperiph source clock 0: fgear 1: fc 11 − R Read as "0". 10- 8 PRCK[2:0] R/W Prescaler clock 000: fperiph 100: fperiph/16 001: fperiph/2 101: fperiph/32 010: fperiph/4 110: Reserved 011: fperiph/8 111: Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as "0". 2-0 GEAR[2:0] R/W High-speed gear clock (fgear) 000: fc 100: fc/2 001: Reserved 101: fc/4 010: Reserved 110: fc/8 011: Reserved 111: Reserved Page 31 2013/5/31 6. 6.2 Clock / Mode Control Registers TMPM361F10FG 6.2.3 CGOSCCR (Oscillation control register) 31 30 29 28 27 26 25 24 1 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - bit symbol WUPT After reset bit symbol WUPT After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 - - - - XTEN XEN 0 0 0 0 0 0 1 1 bit symbol WUPTL After reset 7 6 5 4 3 2 1 0 bit symbol - - - - WUPSEL PLLON WUEF WUEON After reset 0 0 1 1 0 0 0 0 Bit 31-20 Bit Symbol WUPT[11:0] Type R/W Function Specifies count time of the warm-up timer. Warm-up counter value for high-speed Warm-up counter value for low-speed (Upper 12 bits) The warm-up counter for high-speed is 16-bit counter and one for low-speed is 18-bit counter. Lower 4 bits of the both counter are masked. Upper 12 bits for high-speed, lower 14 bits for low-speed are compared with warm-up counter. 19-16 − R Read as "0". 15-14 WUPTL[1:0] R/W Specifies count time of the warm-up timer. 13-12 − R/W Write as "0". 11-10 − R Read as "0". 9 XTEN R/W Low-speed oscillator Warm-up counter value for low-speed (Lower 2 bits) 0: Stop 1:Oscillation 8 XEN R/W High-speed oscillator 0: Stop 1:Oscillation 7-4 − R/W Write as "0011". 3 WUPSEL R/W Warm-up counter 0: High-speed (fosc) 1: Low-speed (fs) Specifies the oscillator to warm-up. A clock generated by the specified oscillator is used for the warm-up timer count. 2 PLLON R/W PLL operation 0: Stop 1: Oscillation 1 WUEF R Status of warm-up timer (WUP) 0: Warm-up completed. 1: Warm-up operation Enable to monitor the status of the warm-up timer. 0 WUEON W Operation of warm-up timer 0: don't care 1: Starting warm-up Enables to start the warm-up timer. Read as "0". Note 1: Regarding to warm-up time, refer to "6.3.4 Warm-up function". Note 2: After setting PLL multiplying value, to keep CGOSCCR = "0" (PLL stop) over 100 μs is needed as the PLL initializing stable time. 2013/5/31 Page 32 TMPM361F10FG 6.2.4 CGSTBYCR (Standby control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - PTKEEP DRVE bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - RXTEN RXEN After reset 0 0 0 0 0 0 0 1 2 1 0 7 6 5 4 3 bit symbol - - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type STBY 0 1 1 Function 31-18 − R Read as "0". 17 PTKEEP R/W I/O port control in the Backup mode. 0: Output the contents of output latch. 1: Hold the port state when CGSTBYCR is changed from "0" to "1". 16 DRVE R/W Pin status in STOP mode (note) 0: Inactive 1: Active 15-10 − R Read as "0". 9 RXTEN R/W Low-speed oscillator operation after releasing the STOP mode. 0: Stop 1: Oscillation 8 RXEN R/W High-speed oscillator operation after releasing the STOP mode. 0: Stop 1: Oscillation 7-3 − R Read as "0". 2-0 STBY[2:0] R/W Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE2 100: Reserved 101: BACKUP STOP 110: BACKUP SLEEP 111: IDLE1 Note 1: I/O Ports which hold their state when CGSTBYCR is changed from "0" to "1" are all port except for port I, J, L, M and N. In regarding to release CGSTBYCR, refer to section of "Backup module". Note 2: The value which is shown reserved in above table must be not set. Page 33 2013/5/31 6. 6.2 Clock / Mode Control Registers TMPM361F10FG 6.2.5 CGPLLSEL (PLL Selection Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 1 1 1 0 0 1 7 6 5 4 3 2 1 0 - - PLLSEL 1 1 0 bit symbol RS After reset bit symbol ND After reset Bit - 0 Bit Symbol 0 0 1 Type 1 IS C2S 0 Function 31-16 − R Read as "0". 15-12 RS[3:0] R/W Clock multiplied by PLL 0111: 4 times 1010: 8 times Others: Reserved 11 − R Read as "0". 10-9 IS[1:0] R/W Clock multiplied by PLL 00: 8 times 01: 4 times Others: Reserved 8 C2S R/W Clock multiplied by PLL 0: 4 times 1: 8 times 7-3 ND[4:0] R/W Clock multiplied by PLL 00011: 4 times 00111: 8 times Others: Reserved 2-1 − R/W Write as "1". 0 PLLSEL R/W Use PLL 0: fosc 1: fPLL Specifies use or disuse of the clock multiplied by the PLL. fosc is automatically set after reset. Resetting is required when using the PLL. Note 1: Select PLL multiplying value which is shown Table 6-1. Note 2: Select PLL multiplying value when CGOSCCR = "0" (PLL stop). Note 3: After setting PLL multiplying value, to keep (CGOSCCR = "0" (PLL stop) over 100 μs is needed as the PLL initializing stable time. 2013/5/31 Page 34 TMPM361F10FG 6.2.6 CGCKSEL (System clock selection register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - SYSCK SYSCKFLG After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as "0". 1 SYSCK R/W System clock (fsys) 0: fgear 1: fs Enable to specify the system clock. Before modifying , fgear and fs must be stable. 0 SYSCKFLG R System clock status 0: fgear 1: fs Shows the status of the system clock. Switching the oscillator with generates time lag to complete. If the output of the oscillator specified in is read out by , the switching has been completed. Page 35 2013/5/31 6. 6.3 Clock / Mode Control Clock control 6.3 TMPM361F10FG Clock control 6.3.1 Clock Type Each clock is defined as follows : fosc : Clock input from the X1 and X2 pins fs : Clock input from the XT1 and XT2 pins (low-speed clock) fPLL : Clock quadrupled or octupled by PLL fc : Clock specified by CGPLLSEL (high-speed clock) fgear : Clock specified by CGSYSCR (gear clock) fsys : Clock specified by CGCKSEL (system clock) fperiph : Clock specified by CGSYSCR φT0 : Clock specified by CGSYSCR (Prescaler clock) The gear clock fgear and the prescaler clock φT0 are dividable as follows. 6.3.2 Gear clock : fc, fc/2, fc/4, fc/8 Prescaler clock : fs, fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 Initial Values after Reset Reset operation initializes the clock configuration as follows. High-speed oscillator : oscillating Low-speed oscillator : oscillating PLL (Phase locked loop circuit) : stop High-speed clock gear : fc (no frequency dividing) Reset operation causes all the clock configurations excluding the low-speed clock (fs) to be the same as fosc. fc = fosc fsys = fosc φT0 = fosc 2013/5/31 Page 36 TMPM361F10FG 6.3.3 Clock system Diagram Figure 6-1 shows the clock system diagram. The input clocks selector shown with an arrow are set as default after reset. CGOSCCR CGOSCCR CGOSCCR Operation after reset warming-up timer FCSTOP ADC conversion clock CGSYSCR CGOSCCR fperiph (๟ㄝI/O߳) fgear CGPLLSEL CGOSCCR Starts oscillation after reset X1 X2 High-speed oscillation fc PLL fsys CGSYSCR 1/2 1/4 1/8 fosc CGCKSEL fPLL XT1 XT2 Low-speed oscillation CGOSCCR Starts oscillation after reset CGOSCCR Stops after releasing reset fs fs ‫ޣ‬SysTick external reference clock‫ޤ‬ CPU 1/32 CGSYSCR φT0 fperiph 1/2 1/4 1/8 1/16 1/32 CGSYSCR ‫ޣ‬Peripheral I/O prescaler input‫ޤ‬ TMRB, SIO ‫ޣ‬AHB-Bus I/O‫ޤ‬ CPU, ROM, RAM, SMC, DMAC,BOOT ROM ‫ޣ‬APB-Bus I/O‫ޤ‬ ‫ޓ‬SSP ‫ޣ‬IO-Bus I/O‫ޤ‬ TMRB, WDT, RTC, SIO, SBI, CEC, RMC, ADC, PORT fsys 1/2 fs CGSYSCR ‫ޣ‬RTC‫ޤ‬ Sec. counter ‫ޣ‬CEC, RMC‫ޤ‬ Sampling clock SCOUT Figure 6-1 Clock Block Diagram Page 37 2013/5/31 6. 6.3 Clock / Mode Control Clock control 6.3.4 TMPM361F10FG Warm-up function The warm-up function secures the stability time for the oscillator and the PLL with the warm-up timer. Refer to "6.6.8 Warm-up" for more detail. How to use the warm-up function is described. 1. Specify the count up clock Specify the count up clock for the warm-up counter in the CGOSCCR. 2. Specify the warm-up counter value The warm-up time can be calculated by following formula with round 4 bit off, set to bit of Number of warm-up cycles = Warm-up time Warm-up clock cycle 3. Start warm-up function and confirm the completion of warm-up When CGOSCCR is set to "1", the warm-up start a count up. The CGOSCCR is used to confirm the start and completion of warm-up. =1 shows under warmup and =0 shows completion of warm-up. For the clock changing, current system clock can be monitored in CGCKSEL. 2013/5/31 Page 38 TMPM361F10FG The following shows the warm-up setting and example. 1. In transition from SLOW mode to NORMAL mode, set 5ms for warm-up time when using 8MHz oscillator for high-frequency The value of warm-up conter is shown below. Warm-up time = Warm-up clock cycle 5ms 1/8MHz = 40,000 cyclesZ% The warm-up counter for high-frequency is 16 bits and the lower 4 bits of these is ignored. Therefore, the upper 12 bits of 0x9C40, 0x9C4 is set to CGOSCCR. Transition from SLOW mode to NORMAL mode CGOSCCR = "0x9C4" : Warm-up time setting Read CGOSCCR : Confirm warm-up time reflecting CGOSCCR="1" : Enable high-speed oscillation (fosc) CGOSCCR="1" : Enable warm-up counting (WUP) Read CGOSCCR : Wait for "0" (end of WUP) CGOSCCR="0" : system clock changed to high-speed (fgear) Read CGOSCCR : Wait for "0" (the current clock is fgear) CGOSCCR="0" : Disable the low-speed oscillation (fs) (In dual clock mode, it’s not required.) 2. Intransition from NORMAL mode to SLOW mode, set 1s for warm-up time when using 32.768kHz oscillator for low-frequency The value of warm-up conter is shown below. Warm-up time Warm-up clock cycle = 1s 1/32.768kHz = 32,768 cycles = 0x8000 The warm-up counter for low-frequency is 18 bits and the lower 4 bits of these is ignored. Therefore, the upper 14 bits of 0x8000, 0x0800 is set to CGOSCCR. Page 39 2013/5/31 6. 6.3 Clock / Mode Control Clock control TMPM361F10FG Transmission from NORMAL mode to SLOW mode CGOSCCR = "0x200" : Warm-up time setting (Upper 12 bits) CGOSCCR = "00" : Warm-up time setting (Lower 2 bits) Read CGOSCCR : Check warm-up time setting CGOSCCR="1" : Enable low-speed oscillation (fs) CGOSCCR="1" : Select XT1 for warm-up clock CGOSCCR="1" : Enable warm-up counting (WUP) Read CGOSCCR : Wait for "0" (end of WUP) CGOSCCR="1" : system clock changed to low-speed (fs) Read CGOSCCR : Wait for "1" (the current clock is fs) CGOSCCR="0" : Disable the high-speed oscillation (fc) (In dual clock mode, it’s not required.) Note 1: It is not required the warm-up time in using the external clock to be stabled. Note 2: The warm-up timer operates according to the oscillation clock, and it may contain errors if there is any fluctuation in the oscillation frequency. Therefore, the warm-up time should be taken as approximate time. Note 3: After setting warm-up count value to OSCCR, wait until confirming of the value to be reflected, then change to the standby mode by WFI instruction. Note 4: When switching the system clock, ensure that the switching has been completed by reading the CGCKSEL. 2013/5/31 Page 40 TMPM361F10FG 6.3.5 Clock Multiplication Circuit (PLL) This circuit outputs the fPLL clock that is quadruple / octuple of the high-speed oscillator output clock (fosc). As a result, the input frequency to oscillator can be low, and the internal clock be made high-speed. 6.3.5.1 How to configure the PLL function The PLL is disabled after reset. To enable the PLL, set CGPLLSEL to multiplying value when CGOSCCR is "0". And set to "1" after 100μs for initialize time of PLL. After 200μs for lock-up time elapses, set CGPLLSEL to "1", fPLL which is multipupied by 4 or 8 from fosc is used. The PLL requires a certain amount of time to be stabilized, which should be secured using the warmup function or other methods. As for the 4 or 8 multiplying value, only the following setting are permitted. 6.3.5.2 Multiplying 4 0111 00 0 0_0011 8 1010 01 1 0_0111 Changing PLL multiplying When number of multiplication is changed, firstly set "0" to CGPLLSEL. Secondly read CGPLLSEL to check the setting in which multiplication clock is not used (CGPLLSEL="0). Thirdly, set "0" to . Modify CGPLLSEL to multiplying value. And set to "1" after 100μs for initilize time of PLL. After 200μs for lock-up time elapses, Set CGPLLSEL to "1". Page 41 2013/5/31 6. 6.3 Clock / Mode Control Clock control 6.3.5.3 TMPM361F10FG Start PLL sequence Initial value after reset CGPLLSEL = "0" (Not use PLL) CGOSCCR = "0" (PLL stop) CGPLLSEL = "4 times" PLL multiplying value setting CGPLLSEL = multiplying value Initialize time takes 100μs for initialize time of PLL PLL operation CGOSCCR = "1" (PLLì starts) Lock-up time takes 200μs for lock-up time PLL setting CGPLLSEL = "1" (PLL used) Possible to use the multiplied system clock 2013/5/31 Page 42 TMPM361F10FG 6.3.5.4 Multiplying value change sequence PLL setting CGPLLSEL = "0" (Not use PLL) Confirm that CGPLLSEL is "0". PLL operation CGOSCCR = "0" (PLL stops) PLL multiplying value setting CGPLLSEL = multiplying value Initialize time takes 100μs for initialize time of PLL PLL operation CGOSCCR = "1" (PLL starts) Lock-up time takes 200μs for lock-up time PLL setting CGPLLSEL = "1" (PLL used) Possible to use the multiplied system clock Page 43 2013/5/31 6. 6.3 Clock / Mode Control Clock control TMPM361F10FG 6.3.6 System Clock The TMPM361F10FG offers two selectable system clocks: low-speed or high-speed. 6.3.6.1 High-speed clock The high-speed clock is used by multiplying. Frequency Source clock High-speed Oscillator 8 to 16MHz oscillation External clock 8 to 16MHz Using PLL Not use, 4 or 8 multiplying Note:Regarding PLL multiplying and the frequency of high-speed oscillation, refer to Table 6-1. The clock devided by CGSYSCR is used for a system clock. CGSYSCR can be modified in operation, a several time is needed for changing the clock. The setting example of operation frequency depended on PLL multiplying and the clock gear setting is shown bellow. Table 6-1 The setting example of operation frequency depended on PLL multiplying and the clock gear setting (Unit : MHz) Input freq. X1, X2 PLL Multiplying Min. operating freq. Max. operating freq. After reset Clock gear (CG) PLL = @ ON (PLL = OFF, CG = 1/1) 1/1 1/2 1/4 Clock gear (CG) PLL = @ OFF 1/8 1/1 1/2 1/4 1/8 8 32 8 32 16 8 4 8 4 2 1 9 36 9 36 18 9 4.5 9 4.5 2.25 1.13 40 10 40 20 10 5 10 5 2.5 1.25 10 12 4 1 48 12 48 24 12 6 12 6 3 1.5 13.5 54 13.5 54 27 13.5 6.75 13.5 6.75 3.37 1.69 16.0 64 16.0 64 32 16 8 16 8 4 2 64 8 64 32 16 8 8 4 2 1 8 8 1 Note 1: When ADC is used, ADCLK shold be equal or less than 40MHz by setting ADCLK. 6.3.6.2 Low-speed clock The frequency which can be inputted from XT1 and XT2 shown below. Table 6-2 Range of Low Speed Frequency Input frequency range Minimum operating frequency Maximum operating frequency 30 to 34 (kHz) 30 kHz 34 kHz Note:CEC uses fs for a sampling clock. If CEC is used, fs must be within 32.768kHz±4％. 2013/5/31 Page 44 TMPM361F10FG 6.3.6.3 Setting system clock To select system clock is used by CGOSCCR and CGCKSEL. After selecting system clock, set CGPLLSEL and CGOSCCR for PLL and CGSYSCR for clock gear. How to set system clock is shown below. How to set system clock Initial value after reset CGOSCCR = "1" (Enable high-speed oscillation) CGOSCCR = "1" (Enable low-speed oscillation) CGCKSEL = "0" (Selects fgear for system clock) CGOSCCR = "0" (stops PLL) CGPLLSEL = "0" (fosc used) CGSYSCR = "000" (Not divided) Case of using high-speed clock Case of low-speed clock It is possible to use it as it is. CGOSCCR = "1" (Selects low-speed clock) CGCKSEL = "1" (Selects low-speed clock for system clock) Confirm that CGCKSEL is "1". CGOSCCR ="0" (Stops high-speed oscillatir. In dual clock mode, it’s not required.) PLL setup When low-speed clock is used as fsys, the usage of PLL function and clock gear are prohibited. & Clock gear setting Page 45 2013/5/31 6. 6.3 Clock / Mode Control Clock control 6.3.7 TMPM361F10FG Prescaler Clock Control Peripheral I/O has a prescaler for dividing a clock. As the clock φT0 to be input to each prescaler, the "fperiph" clock specified in the CGSYSCR can be divided according to the setting in the CGSYSCR. After the controller is reset, fperiph/1 is selected as φT0. Note:To use the clock gear, ensure that you make the time setting such that prescaler output φTn from each peripheral function is slower than fsys (φTn ≤ fsys). Do not switch the clock gear while the timer counter or other peripheral function is operating. 6.3.8 System Clock Pin Output Function TMPM361F10FG enables to output the system clock from a pin. The SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral I/O φT0. Note 1: The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaranteed. Note 2: When fsys is output from SCOUT pin, SCOUT pin outputs the unexpected waveform just after changing clock gear. In the case of influencing to system by the unexpected waveform, the output of SCOUT pin shold be disabled when changing theclock gear. The output clock is selected by setting the CGSYSCR. The setting to use as SCOUT pin, refer to "Input/Output port". Table 6-3 shows the pin status in each mode when the SCOUT pin is set to the SCOUT output. Table 6-3 SCOUT Output Status in Each Mode Low power consumption mode Mode SCOUT selection NORMAL SLOW CGSYSCR = "00" 2013/5/31 SLEEP Output the fs clock = "01" Output the fsys/2 clock = "10" Output the fsys clock = "11" IDLE2,1 Output the φT0 clock Fixed "0" or "1" Page 46 STOP/BACKUP TMPM361F10FG 6.4 Modes and Mode Transitions 6.4.1 Mode Transitions The NORMAL mode and the SLOW mode use the high-speed and low-speed clocks for the system clock respectively. The IDLE2/1, SLEE, STOP and BACKUP modes can be used as the low power consumption mode that enables to reduce power consumption by halting processor core operation. When the low-speed clock is not used, the SLOW, SLEEP and BACKUP SLEEP modes cannot be used. TMPM361F10FG has a BACKUP mode. This mode can reduce power consumption of full width by shutdown main power supply of almost function except particular one. Figure 6-2 shows mode transition diagram. For a detail of sleep-on-exit, refer to "Cortex-M3 Technical Reference Manual". Reset After reset IDLE1 Mode IDLE2 mode Instruction/ sleep on exit Instruction/ sleep on exit Interrupt (Power on shut down block and perform internal reset) (note 1) Interrupt Interrupt (note 1) Interrupt (Power on shut down block and perform internal reset) (note 1) NORMAL mode Instruction/ sleep on exit Instruction/ sleep on exit Interrupt (note 1) Interrupt (note 1) Instruction/ sleep on exit Instruction STOP mode Instruction/ sleep on exit Instruction Instruction/ sleep on exit Instruction/ sleep on exit Interrupt Interrupt (note 1) Instruction/ sleep on exit BACKUP STOP mode SLEEP mode Instruction/ sleep on exit BACKUP SLEEP mode SLOW mode Interrupt (Power on shut down block and perform internal reset) (note 1) Interrupt (Power on shut down block and perform internal reset) (note 1) Figure 6-2 Mode Transition Diagram Note 1: The warm-up is needed. The warm-up time must be set in NORMAL or SLOWmodes before changing to STOP, SLEEP and BACKUP modes. Regarding warm-up time, refer to "6.6.8 Warm-up". Note 2: When the low-speed clock is not used, the SLOW, SLEEP and BACKUP SLEEP modes can not be used. Note 3: Transition from SLOW mode to IDLE2 and IDLE1 mode is not available. Page 47 2013/5/31 6. 6.5 Clock / Mode Control Operation Mode 6.5 TMPM361F10FG Operation Mode NORMAL mode and SLOW mode are available. The features of each mode are described in the following section. 6.5.1 NORMAL mode This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock. It is shifted to the NORMAL mode after reset. The low-speed clock can also be used. 6.5.2 SLOW mode This mode is to operate the CPU core and the peripheral hardware by using the low-speed clock with highspeed clock stopped. The SLOW mode reduces power consumption compared to the NORMAL mode. This mode allows some peripheral functions to operate. Ther peripheral functions which can be operated are shown in Table 6-6. Note:In the SLOW mode, be sure not to perform reset using the Application Interrupt and Reset Control Register of the Cortex-M3 NVIC register. 2013/5/31 Page 48 TMPM361F10FG 6.6 Low Power Consumption Modes The TMPM361F10FG has low power consumption modes: IDLE1, IDLE2, SLEEP, STOP and BACKUP. To shift to the low power consumption mode, specify the mode in the system control register CGSTBYCR and execute the WFI (Wait For Interrupt) instruction.In this case, execute reset (Except BACKUP mode) or generate the interrupt to release the mode. Releasing by the interrupt requires settings in advance. See the chapter "Exceptions" for details. Note 1: The TMPM361F10FG does not offer any event for releasing the low power consumption mode. Transition to the low power consumption mode by executing the WFE (Wait For Event) instruction is prohibited. Note 2: The TMPM361F10FG does not support the low power consumption mode configured with the SLEEPDEEP bit in the Cortex-M3 core. Setting the bit of the system control register is prohibited. Note 3: Do not release BACKUP mode by reset. The features of each mode are described as follows. 6.6.1 IDLE Mode (IDLE2, IDLE1) CPU is stopped in this mode. Each peripheral function has one bit in its control register for enabling or disabling operation in the IDLE mode. When the IDLE mode is enabled, peripheral functions for which operation in the IDLE mode is disabled stop operation and hold the state at that time. The following peripheral functions can be enabled or disabled in the IDLE mode. For setting details, see the chapter on each peripheral function. ・ ・ ・ ・ ・ 16-bit timer / event counter (TMRB) Serial channel (SIO/UART) Serial bus interface (I2C/SIO) AD converter (ADC) Watchdog timer (WDT) Note:Pay attention that the counter of watch dog timer function can not be cleared by CPU while in IDLE mode. 6.6.1.1 IDLE2 mode In the IDLE2 mode, CPU stops. Operation frequency range and the peripherals performance are equivalent for the normal mode besides power consumption is reduced compared to the NOMAL mode. 6.6.1.2 IDLE1 mode The IDLE1 mode is decreased power supply ability than IDEL2 to realize low power consumption. Using the IDLE1 mode, the conditions are refer to "Table 6-6 Operational Status in Each Mode" and Operation frequency must be set as follows; fsys=1MHz (fosc=8MHz, PLL multiplier circuit stop, clock gear 1/8). Page 49 2013/5/31 6. 6.6 Clock / Mode Control Low Power Consumption Modes 6.6.2 TMPM361F10FG SLEEP mode In the SLEEP mode, the external low-speed oscillator, RTC, CEC, RMC and key-on wakeup can be operated. By releasing the SLEEP mode, the device returns to the preceding mode of the SLEEP mode and starts operation. 6.6.3 STOP mode All the internal circuits including the internal oscillator are brought to a stop in the STOP mode. By releasing the STOP mode, the device returns to the preceding mode of the STOP mode and starts operation. The STOP mode enables to select the pin status by setting the CGSTBYCR. Table 6-4 shows the pin status in the STOP mode. Table 6-4 Pin States in the STOP mode Pin name Not port = 0 Input only × × X2, XT2 Output only "High" level output "High" level output Input only ο ο Input ο ο Output × Depends on PxCR[m] Input ο ο Output × Depends on PxCR[m] Input × Depends on PxIE[m] PL3, PL7, PM3, PM7, PN3, PE7, PG3, PG7, PI2, PI3 (When used as interrupt pin PxFRn=1 and input is enabled PxIE=1) (note) PJ4,PJ5, PJ6, PJ7 (When used as KWUP pin PxFRn=1 and input is enabled PxIE=1) (note) PF0, PF1, PF2, PF3, PF4 (When used as trace data output pin xFRn=1) (note) PA7 to PA0, PB7 to PB0, PE6 to PE0, PP6 to PP2, PP0 (When used as external bus pin PxFRn=1. Only data bus pin and input is enabled PxIE =1) (note) other port pin Output Input Depends on (PxCR[m]) ο Output ο Depends on (PxCR[m]) Input × Depends in PxIE[m] Output × Depends in PxCR[m] ο : Input or output enabled. × : Input or output disabled. Note:x : port number / m : corresponding bit / n: function register number 2013/5/31 = 1 X1, XT1 RESET, NMI, MODE Port I/O Page 50 TMPM361F10FG 6.6.4 BACKUP mode (BACKUP STOP, BACKUP SLEEP) BACKUP mode realizes the lowest power consumption by cutting off the internal power regulator. About more details, refer to the BACKUP module. 6.6.5 Low power Consumption Mode Setting The low power consumption mode is specified by the setting of the CGSTBYCR . Table 6-5 shows the mode setting in the . Table 6-5 Low power consumption mode setting CGSTBYCR Mode STOP 001 SLEEP 010 IDLE2 011 BACKUP STOP 101 BACKUP SLEEP 110 IDLE1 111 Note:Except setting above is prohibited. Page 51 2013/5/31 6. 6.6 Clock / Mode Control Low Power Consumption Modes 6.6.6 TMPM361F10FG Operational Status in Each Mode Table 6-6 shows the operational status in each mode. Table 6-6 Operational Status in Each Mode BACKUP BACKUP SLEEP STOP − × × − − × × − − × × ο (note 6) ο (note 6) ο (note 2) Δ (note 3) Δ (note 2 / 3) Δ # (note 5) − (note 5) − (note 5) × × Δ # − − × × # Δ # − − × × ο Δ # − − × × ο # Δ # − − × × SSP ο # − − − − × × KWUP ο ο ο (note 4) ο (note 4) ο ο (note 4) Δ Δ (note 4) CEC ο ο Δ Δ ο − Δ − RMC ο ο Δ Δ ο − Δ − RTC ο ο ο ο ο − Δ − CG ο ο ο ο ο ο ο ο PLL ο * Δ # # # #,× #,× High-speed oscillator (fc) ο Δ ο ο − − − − Low-speed oscillator (fs) ο ο ・ ・ ο − ο − Main RAM ο ο ο ο ο ο × × ο ο ο ο ο ο ο ο NORMAL SLOW IDLE2 Processor core ο ο − DMAC ο − SMC ο − I/O port ο ADC SIO/UART IDLE1 SLEEP STOP − − ο − ο − ο o (note 6) ο # (note 5) ο # I2C/SIO ο TMRB ο WDT Block BACKUP RAM (note 2) (note 1) ο : Operating − : Clock stopped automatically after the setting mode. (note7) Δ : Operating / stopped can be selected by software. # : Before enter the setting mode, must stop these module operations by software. × : After transition the setting mode, power down these module automatically. * : After transition the setting mode, must stop these module operations by software. ・ : Before enter the setting mode, operating / stopped can be selected by software. Note 1: In IDLE1 and SLOW mode, the particuler peripheral function shown in Table 6-6 must be stopped. In IDLE1 mode, TMPM361F10FG must be operated on maximam frequency of fsys = 1MHz (fosc=8MHz, PLL stopped, clock gear 1/8). Note 2: It depends on CGSTBYCR. Note 3: It depends on CGSTBYCR. Note 4: When low-speed oscillator is stopped or stopped automatically, only static pull-up will be valid. Note 5: Before transition the setting mode, clear ADMO1D to "0". Note 6: Port state before transition the low power consumption mode is kept. Note 7: The clock supplied to the module is stopped automatically after transition the setting mode. Therefore, transit the setting mode after comfirming the stop of the each module. 2013/5/31 Page 52 TMPM361F10FG 6.6.7 Releasing the Low Power Consumption Mode The low power consumption mode except BACKUP mode can be released by an interrupt request, NonMaskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown in Table 6-7. Page 53 2013/5/31 6. 6.6 Clock / Mode Control Low Power Consumption Modes TMPM361F10FG Table 6-7 Release Source in Each Mode Low power consumption mode Interrupt Release source IDLE2 IDLE1 (note 1) BACKUP SLEEP STOP BACKUP SLEEP STOP (note 2) (note 2) INT0 to 4, E, F (note 3) ο ο ο ο ο ο INT5 to INT7 (note 3) ο ο ο ο × × INTRTC ο ο ο × ο × INTTB0 to F ο × × × × × INTCAP10 to 20,50 to 70, 90 ο × × × × × INTCAP 11 to 21,51 to 71,91 ο × × × × × INTRX0 to 4, INTTX0 to 4 ο × × × × × INTSBI0 to 3 ο × × × × × INTCECRX, INTCECTX ο ο ο × ο (note 5) × INTRMCRX0 ο ο ο × ο × INTAD / INTADHP / INTADM0, 1 ο × × × × × INTKWUP ο ο ο ο ο ο SysTick interrupt ο ο × × × × NMI (INTWDT) ο × × × × × NMI (NMI pin) ο × ο ο × × RESET (RESET pin) ο ο ο ο × × ο : Starts the interrupt handling after the mode is released. (The reset initializes the LSI) × : Unavailable Note 1: Refer to "6.6.8 Warm-up" about warm-up time. Note 2: After releasing BACKUP mode, initialize the circuit except BACKUP module. Note 3: To release the low power consumption mode by using the level mode interrupt, keep the level until the interrupt handling is started. Changing the level before then will prevent the interrupt handling from starting properly. Note 4: For shifting to the low power consumption mode, set the CPU to prohibit all the interrupts other than the release source. If not, releasing may be executed by an unspecified for wake up. Note 5: INTCECRX (CEC reception interrupt) is source trigger for wake up in the BACKUP SLEEP mode. But INTCECTX (CEC transmission interrupt) is not trigger for wake up in the BACKUP SLEEP mode. Note 6: To shift from NORMAL mode to IDLE1 mode, Warm-up time requires more than 100μs. If not, recovery time of MCU internal system is not done when the return from IDLE1 mode. ・ Release by interrupt request To release the low power consumption mode by an interrupt, the CPU must be set in advance to detect the interrupt. In addition to the setting in the CPU, the clock generator must be set to detect the interrupt to be used to release the SLEEP and STOP modes. ・ Release by Non-Maskable Interrupt (NMI) There are two kinds of NMI sources: WDT interrupt (INTWDT) and NMI pin. INTWDT can only be used in the IDLE2 mode. The NMI pin can be used to release all the lower power consumption modes except BACKUP and IDLE1 mode. ・ Release by reset Any low power consumption mode except BACKUP mode can be released by reset from the RESET pin. After that, the mode switches to the NORMAL mode and all the registers are initialized as is the case with normal reset. Note that releasing from the STOP mode by reset does not induce the automatic warm-up. Keep the reset signal valid until the oscillator operation becomes stable. ・ Release by SysTick interrupt SysTick interrupt can only be used in the IDLE mode. 2013/5/31 Page 54 TMPM361F10FG Note: Do not release BACKUP mode by reset. Refer to "Interrupts" in "Exceptions" for detail. Page 55 2013/5/31 6. 6.6 Clock / Mode Control Low Power Consumption Modes 6.6.8 TMPM361F10FG Warm-up Mode transition may require the warm-up so that the internal oscillator provides stable oscillation. In the mode transition from STOP to the NORMAL / SLOW or from IDLE1 / SLEEP to NORMAL, the warm-up counter is activated automatically. And then the system clock output is started after the elapse of configured warm-up time. It is necessary to select a oscillator to be used for warm-up in the CGOSCCR and to set a warmup time in the CGOSCCR before executing the instruction to enter the STOP / IDLE1 / SLEEP mode. In the transition from NORMAL to SLOW / SLEEP, the warm-up is required so that the internal oscillator to stabilize if the low-speed clock is disabled. Enable the low-speed clock and then activate the warm-up by software. In the transition from SLOW to NORMAL when the high-speed clock is disabled, enable the high-speed clock and then activate the warm-up. Table 6-8 shows whether the warm-up setting of each mode transition is required or not. 2013/5/31 Page 56 TMPM361F10FG Table 6-8 Warm-up setting in mode transition Mode transition Warm-up setting NORMAL → IDLE2, 1 Not required NORMAL → SLEEP Not required (note 1) NORMAL → SLOW Not required (note 1) NORMAL → STOP Not required NORMAL → BACKUP SLEEP Not required (note 1) NORMAL → BACKUP STOP Not required SLOW → NORMAL Not required (note 2) SLOW → SLEEP Not required SLOW → STOP Not required SLOW → BACKUP SLEEP Not required SLOW → BACKUP STOP Not required IDLE2 → NORMAL Not required IDLE1 → NORMAL High-speed oscillator : equal or more than 100μs SLEEP → NORMAL High-speed oscillator : Setting value of warm-up time Auto-warm-up (note 3) Auto-warm-up SLEEP → SLOW Not required Auto-warm-up STOP → NORMAL High-speed oscillator : Setting value of warm-up time Auto-warm-up STOP → SLOW Low-speed oscillator :Setting value of warm-up time BACKUP SLEEP → NORMAL High-speed oscillator : equal or more than 500μs BACKUP STOP → NORMAL High-speed oscillator : equal or more than 500μs BACKUP SLEEP → SLOW Low-speed oscillator : equal or more than 2.5ms BACKUP STOP → SLOW Low-speed oscillator : equal or more than 2.5ms Auto-warm-up (note 3) Auto-warm-up (note 3) Auto-warm-up (note 3) Auto-warm-up (note 3) Note 1: If the low-speed clock is disabled, enable the low-speed clock and then activate the warm-up by software. Note 2: If the high-speed clock is disabled, enable the high-speed clock and then activate the warm-up by software. Note 3: Do not set value of warm-up time less than the specified value. Note 4: Returning to normal mode by reset does not induce the automatic warm-up. Keep the reset signal valid until the oscillator operation becomes stable. Page 57 2013/5/31 6. 6.6 Clock / Mode Control Low Power Consumption Modes 6.6.9 TMPM361F10FG Clock Operation in Mode Transition The clock operation in mode transition are described Chapter 6.6.9.1 to 6.6.9.4. 6.6.9.1 Transition of operation modes : NORMAL → STOP → NORMAL When returning to the NORMAL mode from the STOP mode, the warm-up is activated automatically. It is necessary to set the warm-up time before entering the STOP mode. Returning to the NORMAL mode by reset does not induce the automatic warm-up. Keep the reset signal asserted until the oscillator operation becomes stable. WFI excute/ sleep on exit Release event occurs NORMAL Mode STOP NORMAL fosc Warm-up fsys (System clock) System clock stops 6.6.9.2 High-speed clock starts oscillating Warm-up starts Warm-up completes. System clock starts. Transition of operation modes : NORMAL → SLEEP → NORMAL When returning the NORMAL mode from the SLEEP mode, the warm-up is activated automatically. It is necessary to set the warm-up time before entering the SLEEP mode. Returning to the NORMAL mode by reset does not induce the automatic warm-up. Keep the reset signal asserted until the operation becomes stable. WFI excute/ sleep on exit Mode Release event occurs NORMAL SLEEP NORMAL fosc Warm-up fsys (System clock) fs (Low-speed clock) Oscillation continues System clock stops 2013/5/31 High-speed clock starts oscillating Warm-up starts Page 58 Warm-up completes. System clock starts. TMPM361F10FG 6.6.9.3 Transition of operation modes : SLOW → STOP → SLOW The warm-up is activated automatically. It is necessary to set the warm-up time before entering the STOP mode. WFI excute/ sleep on exit Release event occurs SLOW Mode STOP SLOW fs Warm-up fsys (System clock=fs) System clock stops 6.6.9.4 Low-speed clock starts oscillating Warm-up starts Warm-up completes System clock starts Transition of operation modes : SLOW → SLEEP → SLOW The low-speed clock continues oscillation in the SLEEP mode. There is no need to make a warm-up setting. WFI excute/ sleep on exit Mode Release event occurs SLOW SLEEP SLOW fs fsys (System clock=fs) System clock stops System clock starts Page 59 2013/5/31 6. 6.6 Clock / Mode Control Low Power Consumption Modes 2013/5/31 TMPM361F10FG Page 60 TMPM361F10FG 7. Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to "Cortex-M3 Technical Reference Manual" if needed. 7.1 Overview Exceptions have close relation to the CPU core. Refer to "Cortex-M3 Technical Reference Manual" if needed. There are two types of exceptions: those that are generated when some error condition occurs or when an instruction to generate an exception is executed; and those that are generated by hardware, such as an interrupt request signal from an external pin or peripheral function. All exceptions are handled by the Nested Vectored Interrupt Controller (NVIC) in the CPU according to the respective priority levels. When an exception occurs, the CPU stores the current state to the stack and branches to the corresponding interrupt service routine (ISR). Upon completion of the ISR, the information stored to the stack is automatically restored. 7.1.1 Exception types The following types of exceptions exist in the Cortex-M3. For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Reset Non-Maskable Interrupt (NMI) Hard Fault Memory Management Bus Fault Usage Fault SVCall (Supervisor Call) Debug Monitor PendSV SysTick External Interrupt Page 61 2013/5/31 7. Exceptions 7.1 Overview TMPM361F10FG 7.1.2 Handling Flowchart The following shows how an exception/interrupt is handled. In the following descriptions, indicates software handling. indicates hardware handling. Each step is described later in this chapter. Processing Detection by CG/CPU Handling by CPU Description The CG/CPU detects the exception request. See Section 7.1.2.1 The CPU handles the exception request. Section 7.1.2.2 Branch to ISR Execution of ISR Return from exception 2013/5/31 The CPU branches to the corresponding interrupt service routine (ISR). Necessary processing is executed. Section 7.1.2.4 The CPU branches to another ISR or returns to the previous program. Section 7.1.2.4 Page 62 TMPM361F10FG 7.1.2.1 Exception Request and Detection (1) Exception occurrence Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. An exception occurs when the CPU executes an instruction that causes an exception or when an error condition occurs during instruction execution. An exception also occurs by an instruction fetch from the Execute Never (XN) region or an access violation to the Fault region. An interrupt request is generated from an external interrupt pin or peripheral function.For interrupts that are used for releasing a standby mode, relevant settings must be made in the clock generator. For details, refer to "7.5 Interrupts". (2) Exception detection If multiple exceptions occur simultaneously, the CPU takes the exception with the highest priority. Table 7-1 shows the priority of exceptions. "Configurable" means that you can assign a priority level to that exception. Memory Management, Bus Fault and Usage Fault exceptions can be enabled or disabled. If a disabled exception occurs, it is handled as Hard Fault. Table 7-1 Exception Types and Priority No. Exception type Priority Description 1 Reset −3 (highest) Reset pin, WDT or SYSRETREQ 2 Non-Maskable Interrupt −2 NMI pin or WDT 3 Hard Fault −1 Fault that cannot activate because a higher-priority fault is being handled or it is disabled 4 Memory Management Configurable 5 Bus Fault Configurable Access violation to the Hard Fault region of the memory map 6 Usage Fault Configurable Undefined instruction execution or other faults related to instruction execution 7~10 Exception from the Memory Protection Unit (MPU) (Note 1) Instruction fetch from the Execute Never (XN) region Reserved − 11 SVCall Configurable System service call with SVC instruction 12 Debug Monitor Configurable Debug monitor when the CPU is not faulting 13 Reserved − 14 PendSV Configurable Pendable system service request 15 SysTick Configurable Notification from system timer 16~ External interrupt Configurable External interrupt pin or peripheral function (Note2) Note 1: This product does not contain the MPU. Note 2: External interrupts have different sources and numbers in each product. For details, see"7.5.1.5 List of Interrupt Sources". Page 63 2013/5/31 7. Exceptions 7.1 Overview TMPM361F10FG (3) Priority setting ・ Priority level The external interrupt priority is set to the interrupt priority register and other exceptions are set to bit in the system handler priority register. The configuration can be changed, and the number of bits required for setting the priority varies from 3 bits to 8 bits depending on products. Thus, the range of priority values you can specify is different depending on products. In the case of 8-bit configuration, the priority can be configured in the range from 0 to 255. The highest priority is "0". If multiple elements with the same priority exist, the smaller the number, the higher the priority becomes. Note: bit is defined as a 3-bit configuration with this product. ・ Priority grouping The priority group can be split into groups. By setting the of the application interrupt and reset control register, can be divided into the pre-emption priority and the sub priority. A priority is compared with the pre-emption priority. If the priority is the same as the preemption priority, then it is compared with the sub priority. If the sub priority is the same as the priority, the smaller the exception number, the higher the priority. The Table 7-2 shows the priority group setting. The pre-emption priority and the sub priority in the table are the number in the case that is defined as an 8-bit configuration. Table 7-2 Priority grouping setting setting Number of Pre-emption Subpriority pre-emption field field priorities Number of subpriorities 000 [7:1] [0] 128 2 001 [7:2] [1:0] 64 4 010 [7:3] [2:0] 32 8 011 [7:4] [3:0] 16 16 100 [7:5] [4:0] 8 32 101 [7:6] [5:0] 4 64 110 [7] [6:0] 2 128 111 None [7:0] 1 256 Note:If the configuration of is less than 8 bits, the lower bit is "0". For the example, in the case of 3-bit configuration, the priority is set as and is "00000". 2013/5/31 Page 64 TMPM361F10FG 7.1.2.2 Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) When an exception occurs, the CPU suspends the currently executing process and branches to the interrupt service routine. This is called "pre-emption". (1) Stacking When the CPU detects an exception, it pushes the contents of the following eight registers to the stack in the following order : ・ ・ ・ ・ ・ Program Counter (PC) Program Status Register (xPSR) r0 to r3 r12 Link Register (LR) The SP is decremented by eight words by the completion of the stack push.The following shows the state of the stack after the register contents have been pushed. Old SP → xPSR PC LR r12 r3 r2 r1 SP → (2) r0 fetching an ISR The CPU enables instruction to fetch the interrupt processing with data store to the register. Prepare a vector table containing the top addresses of ISRs for each exception.After reset, the vector table is located at address 0x0000_0000 in the Code area.By setting the Vector Table Offset Register, you can place the vector table at any address in the Code or SRAM space. The vector table should also contain the initial value of the main stack. (3) Late-arriving If the CPU detects a higher priority exception before executing the ISR for a previous exception, the CPU handles the higher priority exception first. This is called "late-arriving". A late-arriving exception causes the CPU to fetch a new vector address for branching to the corresponding ISR, but the CPU does not newly push the register contents to the stack. (4) Vector table The vector table is configured as shown below. Page 65 2013/5/31 7. Exceptions 7.1 Overview TMPM361F10FG You must always set the first four words (stack top address, reset ISR address, NMI ISR address, and Hard Fault ISR address). Set ISR addresses for other exceptions if necessary. Exception Offset 7.1.2.3 Contents Setting 0x00 Reset Initial value of the main stack Required 0x04 Reset ISR address Required 0x08 Non-Maskable Interrupt ISR address Required 0x0C Hard Fault ISR address Required 0x10 Memory Management ISR address Optional 0x14 Bus Fault ISR address Optional 0x18 Usage Fault ISR address Optional 0x1C to 0x28 Reserved 0x2C SVCall ISR address Optional 0x30 Debug Monitor ISR address Optional 0x34 Reserved 0x38 PendSV ISR address Optional 0x3C SysTick ISR address Optional 0x40 External Interrupt ISR address Optional Executing an ISR An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the user. An ISR may need to include code for clearing the interrupt request so that the same interrupt will not occur again upon return to normal program execution. For details about interrupt handling, see "7.5 Interrupts". If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons the currently executing ISR and services the newly detected exception. 2013/5/31 Page 66 TMPM361F10FG 7.1.2.4 Exception exit (1) Execution after returning from an ISR When returning from an ISR, the CPU takes one of the following actions : ・ Tail-chaining If a pending exception exists and there are no stacked exceptions or the pending exception has higher priority than all stacked exceptions, the CPU returns to the ISR of the pending exception. In this case, the CPU skips the pop of eight registers and push of eight registers when exiting one ISR and entering another. This is called "tail-chaining". ・ Returning to the last stacked ISR If there are no pending exceptions or if the highest priority stacked exception is of higher priority than the highest priority pending exception, the CPU returns to the last stacked ISR. ・ Returning to the previous program If there are no pending or stacked exceptions, the CPU returns to the previous program. (2) Exception exit sequence When returning from an ISR, the CPU performs the following operations : ・ Pop eight registers Pops the eight registers (PC, xPSR, r0 to r3, r12 and LR) from the stack and adjust the SP. ・ Load current active interrupt number Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. ・ Select SP If returning to an exception (Handler Mode), SP is SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 67 2013/5/31 7. 7.2 Exceptions Reset Exceptions 7.2 TMPM361F10FG Reset Exceptions Reset exceptions are generated from the following three sources. Use the Reset Flag (CGRSTFLG) Register of the Clock Generator to identify the source of a reset. ・ External reset pin A reset exception occurs when an external reset pin changes from "Low" to "High". ・ Reset exception by WDT The watchdog timer (WDT) has a reset generating feature. For details, see the chapter on the WDT. ・ Reset exception by SYSRESETREQ A reset can be generated by setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register. Note: 7.3 Do not reset with in SLOW mode. Non-Maskable Interrupts (NMI) Non-maskable interrupts are generated from the following two sources. Use the NMI Flag (CGNMIFLG) Register of the clock generator to identify the source of a non-maskable interrupt. ・ External NMI pin A non-maskable interrupt is generated when an external NMI pin changes from "High" to "Low". ・ Non-maskable interrupt by WDT The watchdog timer (WDT) has a non-maskable interrupt generating feature. For details, see the chapter on the WDT. 7.4 SysTick SysTick provides interrupt features using the CPU's system timer. When you set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Control and Status Register, the counter loads with the value set in the Reload Value Register and begins counting down.When the counter reaches "0", a SysTick exception occurs.You may be pending exceptions and use a flag to know when the timer reaches "0". The SysTick Calibration Value Register holds a reload value for counting 10 ms with the system timer. The count clock frequency varies with each product, and so the value set in the SysTick Calibration Value Register also varies with each product. Note:In this product, fosc by 32 is used as external reference clock. 2013/5/31 Page 68 TMPM361F10FG 7.5 Interrupts This chapter describes routes, sources and required settings of interrupts. The CPU is notified of interrupt requests by the interrupt signal from each interrupt source. It sets priority on interrupts and handles an interrupt request with the highest priority. Interrupt requests for clearing a standby mode are notified to the CPU via the clock generator. Therefore, appropriate settings must be made in the clock generator. 7.5.1 Interrupt Sources 7.5.1.1 Interrupt route Figure 7-1 shows an interrupt request route. The interrupts issued by the peripheral function that is not used to release standby are directly input to the CPU (route1). The peripheral function interrupts used to release standby (route 2) and interrupts from the external interrupt pin (route 3) are input to the clock generator and are input to the CPU through the logic for releasing standby (route 4 and 5). If interrupts from the external interrupt pins are not used to release standby, they are directly input to the CPU, not through the logic for standby release (route 6). Peripheral function Interrupt requestձ յ CPU մ ն External interrupt pin 0 ճ Port Exiting standby mode 1 ղ Clock generator Peripheral function Figure 7-1 Interrupt Route 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. Page 69 2013/5/31 7. Exceptions 7.5 Interrupts TMPM361F10FG ・ From external pin Set the port control register so that the external pin can perform as an interrupt function pin. ・ From peripheral function Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. ・ By setting Interrupt Set-Pending Register (forced pending) An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pending Register. 7.5.1.3 Transmission An interrupt signal from an external pin or peripheral function is directly sent to the CPU unless it is used to exit a standby mode. Interrupt requests from interrupt sources that can be used for clearing a standby mode are transmitted to the CPU via the clock generator. For these interrupt sources, appropriate settings must be made in the clock generator in advance. External interrupt sources not used for exiting a standby mode can be used without setting the clock generator. 7.5.1.4 Precautions when using external interrupt pins If you use external interrupts, be aware the followings not to generate unexpected interrupts. If input disabled (PxIE="0"), inputs from external interrupt pins are "High". Also, if external interrupts are not used as a trigger to release standby (route 6 of Figure 7-1), input signals from the external interrupt pins are directly sent to the CPU. Since the CPU recognizes "High" input as an interrupt, interrupts occur if corresponding interrupts are enabled by the CPU as inputs are being disabled. To use the external interrupt without setting it as a standby trigger, set the interrupt pin input as "Low" and enable it. Then, enable interrupts on the CPU. 2013/5/31 Page 70 TMPM361F10FG 7.5.1.5 List of Interrupt Sources Table 7-3 shows the list of interrupt sources. Table 7-3 List of Interrupt Sources active level Interrupt Source No. (Releasing standby and interrupt) 0 INT0 Interrupt pin 0 1 INT1 Interrupt pin 1 2 INT2 Interrupt pin 2 3 INT3 Interrupt pin 3 4 INT4 Interrupt pin 4 5 INT5 Interrupt pin 5 6 INT6 Interrupt pin 6 7 INT7 Interrupt pin 7 8 Reserved - 9 Reserved - 10 Reserved - 11 Reserved - 12 Reserved - 13 Reserved - 14 INTE Interrupt pin E 15 INTF Interrupt pin F 16 INTRX0 Serial channel reception 0 interrupt 17 INTTX0 Serial channel transmission 0 interrupt 18 INTRX1 Serial channel reception 1 interrupt 19 INTTX1 Serial channel transmission 1 interrupt 20 INTRX2 Serial channel reception 2 interrupt 21 INTTX2 Serial channel transmission 2 interrupt 22 INTRX3 Serial channel reception 3 interrupt 23 INTTX3 Serial channel transmission 3 interrupt 24 INTRX4 Serial channel reception 4 interrupt 25 INTTX4 Serial channel transmission 4 interrupt 26 INTSBI0 Serial bus interface 0 interrupt 27 INTSBI1 Serial bus interface 1 interrupt 28 INTCECRX CEC reception interrupt 29 INTCECTX CEC transmission interrupt 30 INTRMCRX Remote control signal reception interrupt 31 Reserved - 32 INTRTC RTC interrupt 33 INTKWUP Key-on wake-up interrupt 34 INTSBI2 Serial bus interface 2 interrupt 35 INTSBI3 Serial bus interface 3 interrupt 36 Reserved - 37 INTADHP Highest priority AD conversion complete interrupt 38 INTADM0 AD conversion monitoring function 0 interrupt 39 INTADM1 AD conversion monitoring function 1 interrupt 40 INTTB0 16-bit timer /event counter 0 match detection interrupt 41 INTTB1 16-bit timer /event counter 1 match detection interrupt CG interrupt mode control register CGIMCGA Selectable CGIMCGB - - Selectable CGIMCGD Rising edge CGIMCGE - - Falling edge High level Page 71 CGIMCGF 2013/5/31 7. Exceptions 7.5 Interrupts TMPM361F10FG Table 7-3 List of Interrupt Sources active level No. 2013/5/31 Interrupt Source (Releasing standby and interrupt) 42 INTTB2 16-bit timer /event counter 2 match detection interrupt 43 INTTB3 16-bit timer /event counter 3 match detection interrupt 44 INTTB4 16-bit timer /event counter 4 match detection interrupt 45 INTTB5 16-bit timer /event counter 5 match detection interrupt 46 INTTB6 16-bit timer /event counter 6 match detection interrupt 47 INTTB7 16-bit timer /event counter 7 match detection interrupt 48 INTTB8 16-bit timer /event counter 8 match detection interrupt 49 INTTB9 16-bit timer /event counter 9 match detection interrupt 50 INTTBA 16-bit timer /event counter A match detection interrupt 51 INTTBB 16-bit timer /event counter B match detection interrupt 52 INTTBC 16-bit timer /event counter C match detection interrupt 53 INTTBD 16-bit timer /event counter D match detection interrupt 54 INTTBE 16-bit timer /event counter E match detection interrupt 55 INTTBF 16-bit timer /event counter F match detection interrupt 56 Reserved - 57 Reserved - 58 INTAD AD conversion completion interrupt 59 INTSSPO SSP interrupt 60 Reserved - 61 Reserved - 62 Reserved - 63 Reserved - 64 Reserved - 65 Reserved - 66 Reserved - 67 Reserved - 68 Reserved - 69 Reserved - 70 Reserved - 71 Reserved - 72 Reserved - 73 Reserved - 74 INTCAP10 16-bit timer /event counter 1 input capture interrupt 0 75 INTCAP11 16-bit timer /event counter 1 input capture interrupt 1 76 INTCAP20 16-bit timer /event counter 2 input capture interrupt 0 Page 72 CG interrupt mode control register TMPM361F10FG Table 7-3 List of Interrupt Sources active level No. Interrupt Source (Releasing standby and interrupt) 77 INTCAP21 16-bit timer /event counter 2 input capture interrupt 1 78 Reserved - 79 Reserved - 80 INTCAP50 16-bit timer /event counter 5 input capture interrupt 0 81 INTCAP51 16-bit timer /event counter 5 input capture interrupt 1 82 INTCAP60 16-bit timer /event counter 6 input capture interrupt 0 83 INTCAP61 16-bit timer /event counter 6 input capture interrupt 1 84 INTCAP70 16-bit timer /event counter 7 input capture interrupt 0 85 INTCAP71 16-bit timer /event counter 7 input capture interrupt 1 86 INTCAP90 16-bit timer /event counter 9 input capture interrupt 0 87 INTCAP91 16-bit timer /event counter 9 input capture interrupt 1 88 Reserved - 89 Reserved - 90 Reserved - 91 Reserved - 92 Reserved - 93 Reserved - 94 Reserved - 95 Reserved - 96 Reserved - 97 Reserved - 98 INTDMACERR DMA error status interrupt 99 INTDMACTC0 DMA terminal count status interrupt Page 73 CG interrupt mode control register 2013/5/31 7. Exceptions 7.5 Interrupts TMPM361F10FG 7.5.1.6 Active level The active level indicates which change in signal of an interrupt source triggers an interrupt. The CPU recognizes interrupt signals in "High" level as interrupt. Interrupt signals directly sent from peripheral functions to the CPU are configured to output "High" to indicate an interrupt request. Active level is set to the clock generator for interrupts which can be a trigger to release standby. Interrupt requests from peripheral functions are set as rising-edge or falling-edge triggered. Interrupt requests from interrupt pins can be set as level-sensitive ("High" or "Low") or edge-triggered (rising or falling). If an interrupt source is used for clearing a standby mode, setting the relevant clock generator register is also required. Enable the CGIMCGx bit and specify the active level in the CGIMCGx bits. You must set the active level for interrupt requests from each peripheral function as shown in Table 7-3 An interrupt request detected by the clock generator is notified to the CPU with a signal in "High" level. Note:For the CEC reception / transmission, remote control signal reception and real time clock interrupts, set the bit to "1" and specify the active level, even when they are not used for clearing a standby mode. 2013/5/31 Page 74 TMPM361F10FG 7.5.2 Interrupt Handling 7.5.2.1 Flowchart The following shows how an interrupt is handled. The following shows how an exception/interrupt is handled. In the following descriptions, indicates hardware handling. indicates software handling. Processing Details See Set the relevant NVIC registers for detecting interrupts. Set the clock generator as well if each interrupt source is used to clear a standby mode. Setting for detection ο Common setting NVIC registers ο setting to clear standby mode Clock generator "7.5.2.2 Preparation" Execute an appropriate setting to send the interrupt signal depending on the interrupt type. setting for sending interrupt signal ο Setting for interrupt from external pin Port ο Setting for interrupt from peripheral function Peripheral function (See the chapter of each peripheral function for details.) Interrupt generation Not clearing standby mode An interrupt request is generated. Clearing standby mode CG detects interrupt (clearing standby mode) Interrupt lines used for clearing a standby mode are connected to the CPU via the clock generator. "7.5.2.3 Detection by Clock Generator" The CPU detects the interrupt. CPU detects interrupt. If multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. "7.5.2.4 Detection by CPU" The CPU handles the interrupt. "7.5.2.5 CPU processing" CPU handles interrupt. The CPU pushes register contents to the stack before entering the ISR. Page 75 2013/5/31 7. Exceptions 7.5 Interrupts TMPM361F10FG Processing ISR execution Details See Program for the ISR. Clear the interrupt source if needed. "7.5.2.6 Interrupt Service Routine (ISR)" Return to preceding program 2013/5/31 Configure to return to the preceding program of the ISR. Page 76 TMPM361F10FG 7.5.2.2 Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following order basically. Disable the interrupt by the CPU. Configure from the farthest route from the CPU. Then enable the interrupt by the CPU. To configure the clock generator, you must follow the order indicated here not to cause any unexpected interrupt. First, configure the precondition. Secondly, clear the data related to the interrupt in the clock generator and then enable the interrupt. The following sections are listed in the order of interrupt handling and describe how to configure them. 1. Disabling interrupt by CPU 2. CPU registers setting 3. Preconfiguration (1) (Interrupt from external pin) 4. Preconfiguration (2) (Interrupt from peripheral function) 5. Preconfiguration (3) (Interrupt Set-Pending Register) 6. Configuring the clock generator 7. Enabling interrupt by CPU (1) Disabling interrupt by CPU To make the CPU for not accepting any interrupt, write "1" to the corresponding bit of the PRIMASK Register. All interrupts and exceptions other than non-maskable interrupts and hard faults can be masked. Use "MSR" instruction to set this register. Interrupt mask register PRIMASK ← "1"(Interrupt disabled) Note 1: PRIMASK register cannot be modified by the user access level. Note 2: If a fault causes when "1" is set to the PRIMASK register, it is treated as a hard fault. (2) CPU registers setting You can assign a priority level by writing to field in an Interrupt Priority Register of the NVIC register. Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.Priority level 0 is the highest priority level.If multiple sources have the same priority, the smallest-numbered interrupt source has the highest priority. Page 77 2013/5/31 7. Exceptions 7.5 Interrupts TMPM361F10FG You can assign grouping priority by using the in the Application Interrupt and Reset Control Register. NVIC register ← "prioryty" ← "group priority" (This is configurable if required.) Note:"n" indicates the corresponding exceptions/interrupts. This product uses three bits for assigning a priority level. (3) Preconfiguration (1) (Interrupt from external pin) Set "1" to the port function register of the corresponding pin. Setting PxFRn[m] allows the pin to be used as the function pin. Setting PxIE[m] allows the pin to be used as the input port. Port register PxFRn ← "1" PxIE ← "1" Note:x: port number / m: corresponding bit / n: function register number In modes other than STOP mode, setting PxIE to enable input enables the corresponding interrupt input regardless of the PxFR setting. Be careful not to enable interrupts that are not used. Also, be aware of the description of "7.5.1.4 Precautions when using external interrupt pins". (4) Preconfiguration (2) (Interrupt from peripheral function) The setting varies depending on the peripheral function to be used. See the chapter of each peripheral function for details. (5) Preconfiguration (3) (Interrupt Set-Pending Register) To generate an interrupt by using the Interrupt Set-Pending Register, set "1" to the corresponding bit of this register. NVIC register Interrupt Set-Pending [m] ← "1" Note:m: corresponding bit (6) Configuring the clock generator For an interrupt source to be used for exiting a standby mode, you need to set the active level and enable interrupts in the CGIMCG register of the clock generator. The CGIMCG register is capable of configuring each source. Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the interrupt to be used to the CGICRCG register.See "7.6.3.6 CGICRCG (CG Interrupt Request Clear Register)" for each value. 2013/5/31 Page 78 TMPM361F10FG Interrupt requests from external pins can be used without setting the clock generator if they are not used for exiting a standby mode. However, an "High" pulse or "High"-level signal must be input so that the CPU can detect it as an interrupt request. Also, be aware of the description of "7.5.1.4 Precautions when using external interrupt pins". Clock generator register CGIMCGn ← active level CGICRCG ← Value corresponding to the interrupt to be used CGIMCGn ← "1" (interrupt enabled) Note:n: register number / m: number assigned to interrupt source (7) Enabling interrupt by CPU Enable the interrupt by the CPU as shown below. Clear the suspended interrupt in the Interrupt Clear-Pending Register. Enable the intended interrupt with the Interrupt Set-Enable Register. Each bit of the register is assigned to a single interrupt source. Writing "1" to the corresponding bit of the Interrupt Clear-Pending Register clears the suspended interrupt. Writing "1" to the corresponding bit of the Interrupt Set-Enable Register enables the intended interrupt. To generate interrupts in the Interrupt Set-Pending Register setting, factors to trigger interrupts are lost if pending interrupts are cleared. Thus, this operation is not necessary. At the end, PRIMASK register is zero cleared. NVIC register Interrupt Clear-Pending [m] ← "1" Interrupt Set-Pending [m] ← "1" ← "0" Interrupt mask register PRIMASK Note 1: m : corresponding bit Note 2: PRIMASK register cannot be modified by the user access level. 7.5.2.3 Detection by Clock Generator If an interrupt source is used for exiting a standby mode, an interrupt request is detected according to the active level specified in the clock generator, and is notified to the CPU. An edge-triggered interrupt request, once detected, is held in the clock generator. A level-sensitive interrupt request must be held at the active level until it is detected, otherwise the interrupt request will cease to exist when the signal level changes from active to inactive. When the clock generator detects an interrupt request, it keeps sending the interrupt signal in "High" level to the CPU until the interrupt request is cleared in the CG Interrupt Request Clear (CGICRCG) Register. If a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt request in the ISR. Page 79 2013/5/31 7. Exceptions 7.5 Interrupts TMPM361F10FG 7.5.2.4 Detection by CPU The CPU detects an interrupt request with the highest priority. 7.5.2.5 CPU processing On detecting an interrupt, the CPU pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack then enter the ISR. 7.5.2.6 Interrupt Service Routine (ISR) An ISR requires specific programming according to the application to be used. This section describes what is recommended at the service routine programming and how the source is cleared. (1) Pushing during ISR An ISR normally pushes register contents to the stack and handles an interrupt as required. The Cortex-M3 core automatically pushes the contents of PC, PSR, r0-r3, r12 and LR to the stack. No extra programming is required for them. Push the contents of other registers if needed. Interrupt requests with higher priority and exceptions such as NMI are accepted even when an ISR is being executed. We recommend you to push the contents of general-purpose registers that might be rewritten. (2) Clearing an interrupt source If an interrupt source is used for clearing a standby mode, each interrupt request must be cleared with the CG Interrupt Request Clear (CGICRCG) Register. If an interrupt source is set as level-sensitive, an interrupt request continues to exist until it is cleared at its source. Therefore, the interrupt source must be cleared. Clearing the interrupt source automatically clears the interrupt request signal from the clock generator. If an interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding value in the CGICRCG register. When an active edge occurs again, a new interrupt request will be detected. 2013/5/31 Page 80 TMPM361F10FG 7.6 Exception / Interrupt-Related Registers The CPU's NVIC registers and clock generator registers described in this chapter are shown below with their respective addresses. 7.6.1 Register List Base Address = 0xE000_E000 NVIC registers Register name Address SysTick Control and Status Register 0x0010 SysTick Reload Value Register 0x0014 SysTick Current Value Register 0x0018 SysTick Calibration Value Register 0x001C Interrupt Set-Enable Register 1 0x0100 Interrupt Set-Enable Register 2 0x0104 Interrupt Set-Enable Register 3 0x0108 Interrupt Set-Enable Register 4 0x010C Interrupt Clear-Enable Register 1 0x0180 Interrupt Clear-Enable Register 2 0x0184 Interrupt Clear-Enable Register 3 0x0188 Interrupt Clear-Enable Register 4 0x018C Interrupt Set-Pending Register 1 0x0200 Interrupt Set-Pending Register 2 0x0204 Interrupt Set-Pending Register 3 0x0208 Interrupt Set-Pending Register 4 0x020C Interrupt Clear-Pending Register 1 0x0280 Interrupt Clear-Pending Register 2 0x0284 Interrupt Clear-Pending Register 3 0x0288 Interrupt Clear-Pending Register 4 0x028C Interrupt Priority Register 0x0400 to 0x0460 Vector Table Offset Register 0x0D08 Application Interrupt and Reset Control Register 0x0D0C System Handler Priority Register 0x0D18, 0x0D1C, 0x0D20 System Handler Control and State Register 0x0D24 Clock generator register Base Address = 0x400F_4000 Register name Address CG Interrupt Request Clear Register CGICRCG 0x0014 NMI Flag Register CGNMIFLG 0x0018 Reset Flag Register CGRSTFLG 0x001C CG Interrupt Mode Control Register A CGIMCGA 0x0020 CG Interrupt Mode Control Register B CGIMCGB 0x0024 Reserved - 0x0028 CG Interrupt Mode Control Register D CGIMCGD 0x002C CG Interrupt Mode Control Register E CGIMCGE 0x0030 CG Interrupt Mode Control Register F CGIMCGF 0x0034 Reserved - 0x0038 Reserved - 0x003C Note:Access to the "Reserved" areas is prohibited. Page 81 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2 TMPM361F10FG NVIC Registers 7.6.2.1 SysTick Control and Status Register bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - COUNTFLAG After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - CLKSOURCE TICKINT ENABLE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-17 − R Read as 0. 16 COUNTFLAG R/W 0: Timer not counted to 0 1: Timer counted to 0 Returns "1" if timer counted to "0" since last time this was read. Clears on read of any part of the SysTick Control and Status Register. 15-3 − R Read as 0. 2 CLKSOURCE R/W 0: External reference clock (fosc/32) (Note) 1 TICKINT R/W 1: CPU clock (fsys) 0: Do not pend SysTick 1: Pend SysTick 0 ENABLE R/W 0: Disable 1: Enable If "1" is set, it reloads with the value of the Reload Value Register and starts operation. Note:In this product, fosc by 32 is used as external reference clock. 2013/5/31 Page 82 TMPM361F10FG 7.6.2.2 SysTick Reload Value Register bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 bit symbol RELOAD After reset Undefined 15 14 13 12 bit symbol RELOAD After reset Undefined 7 6 5 4 bit symbol RELOAD After reset Undefined Bit Bit Symbol Type Function 31-24 − R Read as 0, 23-0 RELOAD R/W Reload value Set the value to load into the SysTick Current Value Register when the timer reaches "0". 7.6.2.3 bit symbol After reset SysTick Current Value Register 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 bit symbol CURRENT After reset Undefined 15 14 13 12 bit symbol CURRENT After reset Undefined 7 6 5 4 bit symbol CURRENT After reset Undefined Bit Bit Symbol Type Function 31-24 − R Read as 0. 23-0 CURRENT R/W [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears it to 0. Clearing this register also clears the bit of the SysTick Control and Status Register. Page 83 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.4 TMPM361F10FG SysTick Calibration Value Register bit symbol 31 30 29 28 27 26 25 24 NOREF SKEW - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol TENMS After reset bit symbol TENMS After reset 0 0 0 0 1 0 0 1 7 6 5 4 3 2 1 0 1 1 0 0 0 1 0 0 bit symbol TENMS After reset Bit Bit Symbol Type Function 31 NOREF R 0: Reference clock provided 30 SKEW R 29-24 − R Read as 0. 23-0 TENMS R Calibration value 1: No reference clock 0: Calibration value is 10 ms. 1: Calibration value is not 10ms. Reload value to use for 10 ms timing (0x9C4) by external reference clock (Note). Note:In the case of a multishot, please use -1. 2013/5/31 Page 84 TMPM361F10FG 7.6.2.5 Interrupt Set-Enable Register 1 31 bit symbol - After reset bit symbol 27 26 25 24 SETENA SETENA SETENA SETENA (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 - - - - - - 0 0 0 0 0 0 SETENA SETENA (Interrupt 15) (Interrupt 14) 0 0 7 6 5 4 3 2 1 0 SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2) (Interrupt 1) (Interrupt 0) 0 0 0 0 0 0 0 0 After reset Bit 28 SETENA SETENA After reset bit symbol 29 SETENA (Interrupt 23) After reset bit symbol 30 SETENA Bit Symbol Type Function 31 − R/W Write as 0. 30-14 SETENA R/W Interrupt number [30:14:] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 13-8 − R/W Write as 0. 7-0 SETENA R/W Interrupt number [7:0] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 85 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.6 TMPM361F10FG Interrupt Set-Enable Register 2 31 bit symbol - After reset bit symbol - - 27 26 SETENA SETENA (Interrupt 59) (Interrupt 58) 25 24 - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 54) (Interrupt 53) (Interrupt 52) (Interrupt 51) (Interrupt 50) (Interrupt 49) (Interrupt 48) 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) 0 0 0 0 0 0 0 0 4 7 6 5 SETENA SETENA SETENA (Interrupt 39) (Interrupt 38) (Interrupt 37) 0 0 0 After reset Bit - 28 SETENA After reset bit symbol 29 (Interrupt 55) After reset bit symbol 30 Bit Symbol 0 Type 3 2 1 0 SETENA SETENA SETENA SETENA (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) 0 0 0 0 Function 31-28 − R/W Write as 0. 27-26 SETENA R/W Interrupt number [59:58] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 25-24 − R/W Write as 0. 23-5 SETENA R/W Interrupt number [55:37] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 4 − R/W Write as 0. 3-0 SETENA R/W Interrupt number [35:32] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 86 TMPM361F10FG 7.6.2.7 Interrupt Set-Enable Register 3 bit symbol After reset bit symbol 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 SETENA SETENA SETENA SETENA SETENA SETENA SETENA SETENA (Interrupt 87) (Interrupt 86) (Interrupt 85) (Interrupt 84) (Interrupt 83) (Interrupt 82) (Interrupt 81) (Interrupt 80) After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - After reset 0 SETENA SETENA SETENA SETENA (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-24 − R/W Write as 0. 23-16 SETENA R/W Interrupt number [87:80] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 15-14 − R/W Write as 0. 13-10 SETENA R/W Interrupt number [77:74] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 9-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 87 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.8 TMPM361F10FG Interrupt Set-Enable Register 4 bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type SETENA SETENA (Interrupt 99) (Interrupt 98) 0 0 Function 31-4 − R Read as 0, 3-2 SETENA R/W Interrupt number [99:98] [Write] 1: Enable [Read] 0: Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" to a bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 1-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 88 TMPM361F10FG 7.6.2.9 Interrupt Clear-Enable Register 1 31 bit symbol - After reset bit symbol 27 26 25 24 CLRENA CLRENA CLRENA CLRENA (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 - - - - - - 0 0 0 0 0 0 CLRENA CLRENA (Interrupt 15) (Interrupt 14) 0 0 7 6 5 4 3 2 1 0 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2 (Interrupt 1) (Interrupt 0) 0 0 0 0 0 0 0 0 After reset Bit 28 CLRENA CLRENA After reset bit symbol 29 CLRENA (Interrupt 23) After reset bit symbol 30 CLRENA Bit Symbol Type Function 31 − R/W Write as 0. 30-14 CLRENA R/W Interrupt number [30:14] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 13-8 − R/W Write as 0. 7-0 CLRENA R/W Interrupt number [7:0] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 89 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.10 TMPM361F10FG Interrupt Clear-Enable Register 2 31 bit symbol - After reset bit symbol - - 27 26 CLRENA CLRENA (Interrupt 59) (Interrupt 58) 25 24 - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 54) (Interrupt 53) (Interrupt 52) (Interrupt 51) (Interrupt 50) (Interrupt 49) (Interrupt 48) 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) 0 0 0 0 0 0 0 0 4 7 6 5 CLRENA CLRENA CLRENA (Interrupt 39) (Interrupt 38) (Interrupt 37) 0 0 0 After reset Bit - 28 CLRENA After reset bit symbol 29 (Interrupt 55) After reset bit symbol 30 Bit Symbol 0 Type 3 2 1 0 CLRENA CLRENA CLRENA CLRENA (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) 0 0 0 0 Function 31-28 − R/W Write as 0. 27-26 CLRENA R/W Interrupt number [59:58] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 25-24 − R/W Write as 0. 23-5 CLRENA R/W Interrupt number [55:37] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 4 − R/W Write as 0. 3-0 CLRENA R/W Interrupt number [35:32] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 2013/5/31 Page 90 TMPM361F10FG Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 91 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.11 Interrupt Clear-Enable Register 3 bit symbol After reset bit symbol TMPM361F10FG 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA CLRENA (Interrupt 87) (Interrupt 86) (Interrupt 85) (Interrupt 84) (Interrupt 83) (Interrupt 82) (Interrupt 81) (Interrupt 80) After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - After reset 0 CLRENA CLRENA CLRENA CLRENA (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-24 − R/W Write as 0. 23-16 CLRENA R/W Interrupt number [87:80] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 15-14 − R/W Write as 0. 13-10 CLRENA R/W Interrupt number [77:74] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 9-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 92 TMPM361F10FG 7.6.2.12 Interrupt Clear-Enable Register 4 bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type CLRENA CLRENA (Interrupt 99) (Interrupt 98) 0 0 Function 31-4 − R Read as 0, 3-2 CLRENA R/W Interrupt number [99:98] [Write] 1: Disabled [Read] 0: Disabled 1: Enable Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" to a bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. 1-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 93 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.13 TMPM361F10FG Interrupt Set-Pending Register 1 31 30 29 28 27 26 25 24 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) bit symbol - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol After reset bit symbol After reset bit symbol After reset Bit SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 23) (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 - - - - - - Undefined Undefined Undefined Undefined Undefined Undefined SETPEND SETPEND (Interrupt 15) (Interrupt 14) Undefined Undefined 7 6 5 4 3 2 1 0 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2 (Interrupt 1) (Interrupt 0) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol Type Function 31 − R/W Write as 0. 30-14 SETPEND R/W Interrupt number [30:14] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 13-8 − R/W Write as 0. 7-0 SETPEND R/W Interrupt number [7:0] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 94 TMPM361F10FG 7.6.2.14 Interrupt Set-Pending Register 2 31 30 29 28 27 26 SETPEND SETPEND (Interrupt 59) (Interrupt 58) 25 24 - - bit symbol - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol After reset bit symbol After reset bit symbol After reset SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 55) (Interrupt 54) (Interrupt 53) (Interrupt 52) (Interrupt 51) (Interrupt 50) (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 4 7 6 5 SETPEND SETPEND SETPEND (Interrupt 39) (Interrupt 38) (Interrupt 37) Undefined Undefined Undefined Undefined Page 95 3 2 1 0 SETPEND SETPEND SETPEND SETPEND (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) Undefined Undefined Undefined Undefined 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers Bit Bit Symbol TMPM361F10FG Type Function 31-28 − R/W Write as 0. 27-26 SETPEND R/W Interrupt number [59:58] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 25-24 − R/W Write as 0. 23-5 SETPEND R/W Interrupt number [55:37] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 4 − R/W Write as 0. 3-0 SETPEND R/W Interrupt number [35:32] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 96 TMPM361F10FG 7.6.2.15 Interrupt Set-Pending Register 3 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND SETPEND (Interrupt 87) (Interrupt 86) (Interrupt 85) (Interrupt 84) (Interrupt 83) (Interrupt 82) (Interrupt 81) (Interrupt 80) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - After reset Undefined bit symbol After reset SETPEND SETPEND SETPEND SETPEND (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 31-24 − R/W Write as 0. 23-16 SETPEND R/W Interrupt number [87:80] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 15-14 − R/W Write as 0. 13-10 SETPEND R/W Interrupt number [77:74] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 9-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 97 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.16 bit symbol After reset TMPM361F10FG Interrupt Set-Pending Register 4 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - After reset 0 0 0 0 Undefined Undefined Bit Bit Symbol Type SETPEND SETPEND (Interrupt 99) (Interrupt 98) Undefined Undefined Function 31-4 − R Read as 0, 3-2 SETPEND R/W Interrupt number [99:98] [Write] 1: Pend [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" to a corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. 1-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 98 TMPM361F10FG 7.6.2.17 Interrupt Clear-Pending Register 1 31 30 29 28 27 26 25 24 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 30) (Interrupt 29) (Interrupt 28) (Interrupt 27) (Interrupt 26) (Interrupt 25) (Interrupt 24) bit symbol - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol After reset bit symbol After reset bit symbol After reset Bit CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 23) (Interrupt 22) (Interrupt 21) (Interrupt 20) (Interrupt 19) (Interrupt 18) (Interrupt 17) (Interrupt 16) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 - - - - - - Undefined Undefined Undefined Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 15) (Interrupt 14) Undefined Undefined 7 6 5 4 3 2 1 0 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 7) (Interrupt 6) (Interrupt 5) (Interrupt 4) (Interrupt 3) (Interrupt 2) (Interrupt 1) (Interrupt 0) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Symbol Type Function 31 − R/W Write as 0. 30-14 CLRPEND R/W Interrupt number [30:14] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 13-8 − R/W Write as 0. 7-0 CLRPEND R/W Interrupt number [7:0] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 99 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.18 TMPM361F10FG Interrupt Clear-Pending Register 2 31 30 29 28 27 26 CLRPEND CLRPEND (Interrupt 59) (Interrupt 58) 25 24 - - bit symbol - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol After reset bit symbol After reset bit symbol After reset 2013/5/31 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 55) (Interrupt 54) (Interrupt 53) (Interrupt 52) (Interrupt 51) (Interrupt 50) (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 47) (Interrupt 46) (Interrupt 45) (Interrupt 44) (Interrupt 43) (Interrupt 42) (Interrupt 41) (Interrupt 40) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 4 7 6 5 CLRPEND CLRPEND CLRPEND (Interrupt 39) (Interrupt 38) (Interrupt 37) Undefined Undefined Undefined Undefined Page 100 3 2 1 0 CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 35) (Interrupt 34) (Interrupt 33) (Interrupt 32) Undefined Undefined Undefined Undefined TMPM361F10FG Bit Bit Symbol Type Function 31-28 − R/W Write as 0. 27-26 CLRPEND R/W Interrupt number [59:58] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 25-24 − R/W Write as 0. 23-5 CLRPEND R/W Interrupt number [55:37] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 4 − R/W Write as 0. 3-0 CLRPEND R/W Interrupt number [35:32] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 101 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.19 TMPM361F10FG Interrupt Clear-Pending Register 3 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 87) (Interrupt 86) (Interrupt 85) (Interrupt 84) (Interrupt 83) (Interrupt 82) (Interrupt 81) (Interrupt 80) Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - After reset Undefined bit symbol After reset CLRPEND CLRPEND CLRPEND CLRPEND (Interrupt 77) (Interrupt 76) (Interrupt 75) (Interrupt 74) Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 31-24 − R/W Write as 0. 23-16 CLRPEND R/W Interrupt number [87:80] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 15-14 − R/W Write as 0. 13-10 CLRPEND R/W Interrupt number [77:74] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 9-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". 2013/5/31 Page 102 TMPM361F10FG 7.6.2.20 bit symbol After reset Interrupt Clear-Pending Register 4 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - After reset 0 0 0 0 Undefined Undefined Bit Bit Symbol Type CLRPEND CLRPEND (Interrupt 99) (Interrupt 98) Undefined Undefined Function 31-4 − R Read as 0, 3-2 CLRPEND R/W Interrupt number [99:98] [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending Each bit corresponds to the specified number can force interrupts into the pending state and determines which interrupts are currently pending. Writing "1" to a bit in this register clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. 1-0 − R/W Write as 0. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources". Page 103 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.21 TMPM361F10FG Interrupt Priority Register Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 31 24 23 16 15 8 7 0 0xE000_E400 PRI_3 PRI_2 PRI_1 PRI_0 0xE000_E404 PRI_7 PRI_6 PRI_5 PRI_4 0xE000_E408 − − − − 0xE000_E40C PRI_15 PRI_14 − − 0xE000_E410 PRI_19 PRI_18 PRI_17 PRI_16 0xE000_E414 PRI_23 PRI_22 PRI_21 PRI_20 0xE000_E418 PRI_27 PRI_26 PRI_25 PRI_24 0xE000_E41C − PRI_30 PRI_29 PRI_28 0xE000_E420 PRI_35 PRI_34 PRI_33 PRI_32 0xE000_E424 PRI_39 PRI_38 PRI_37 − 0xE000_E428 PRI_43 PRI_42 PRI_41 PRI_40 0xE000_E42C PRI_47 PRI_46 PRI_45 PRI_44 0xE000_E430 PRI_51 PRI_50 PRI_49 PRI_48 0xE000_E434 PRI_55 PRI_54 PRI_53 PRI_52 0xE000_E438 PRI_59 PRI_58 − − 0xE000_E43C − − − − 0xE000_E440 − − − − 0xE000_E444 − − − − 0xE000_E448 PRI_75 PRI_74 − − 0xE000_E44C − − PRI_77 PRI_76 0xE000_E450 PRI_83 PRI_82 PRI_81 PRI_80 0xE000_E454 PRI_87 PRI_86 PRI_85 PRI_84 0xE000_E458 − − − − 0xE000_E45C − − − − 0xE000_E460 PRI_99 PRI_98 − − The number of bits to be used for assigning a priority varies with each product. This product uses three bits for assigning a priority. The following shows the fields of the Interrupt Priority Registers for interrupt numbers 0 to 3. The Interrupt Priority Registers for all other interrupt numbers have the identical fields. Unused bits return "0" when read, and writing to unused bits has no effect. 2013/5/31 Page 104 TMPM361F10FG 31 30 bit symbol After reset 26 25 24 − − − − 0 0 0 0 0 0 0 22 21 20 19 18 17 16 PRI_2 15 bit symbol − − − − − 0 0 0 0 0 0 0 14 13 12 11 10 9 8 − − − − − PRI_1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 − − − − − 0 0 0 0 0 bit symbol PRI_0 After reset 27 − 0 0 After reset 28 23 bit symbol After reset Bit 29 PRI_3 0 Bit Symbol 0 0 Type Function 31-29 PRI_3 R/W Priority of interrupt number 3 28-24 − R Read as 0. 23-21 PRI_2 R/W Priority of interrupt number 2 20-16 − R Read as 0. 15-13 PRI_1 R/W Priority of interrupt number 1 12-8 − R Read as 0. 7-5 PRI_0 R/W Priority of interrupt number 0 4-0 − R Read as 0. Page 105 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.22 TMPM361F10FG Vector Table Offset Register 31 30 29 - - TBLBASE bit symbol After reset 28 27 26 25 24 TBLOFF 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol TBLOFF After reset bit symbol TBLOFF After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBLOFF - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-30 − R Read as 0, 29 TBLBASE R/W Table base The vector table is in: 0: Code space 1: SRAM space 28-7 TBLOFF R/W Offset value Set the offset value from the top of the space specified in TBLBASE. The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for up to 16 interrupts.For more interrupts, you must adjust the alignment by rounding up to the next power of two. 6-0 2013/5/31 − R Read as 0, Page 106 TMPM361F10FG 7.6.2.23 Application Interrupt and Reset Control Register 31 30 29 bit symbol 28 27 26 25 24 VECTKEY/VECTKEYSTAT After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol ENDIANESS - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - SYSRESET VECTCLR REQ ACTIVE After reset 0 0 0 0 0 0 0 bit symbol Bit 31-16 15 VECTKEY/VECTKEYSTAT Bit Symbol VECTKEY Type R/W PRIGROUP Register key [Write] Writing to this register requires 0x5FA in the field. VECTKEYSTAT (Read) [Read] Read as 0xFA05. R/W 0 Function (Written) / ENDIANESS VECTRESET Endianness bit: (Note1) 1: Big endian 0: Little endianl 14-11 − R Read as 0, 10-8 PRIGROUP R/W Interrupt priority grouping 000: seven bits of pre-emption priority, one bit of subpriority 001: six bits of pre-emption priority, two bits of subpriority 010: five bits of pre-emption priority, three bits of subpriority 011: four bits of pre-emption priority, four bits of subpriority 100: three bits of pre-emption priority, five bits of subpriority 101: two bits of pre-emption priority, six bits of subpriority 110: one bit of pre-emption priority, seven bits of subpriority 111: no pre-emption priority, eight bits of subpriority The bit configuration to split the interrupt priority register into pre-emption priority and sub priority. 7-3 − R Read as 0, 2 SYSRESET R/W System Reset Request REQ 1 1=CPU outputs a SYSRESETREQ signal. (note2) VECTCLR R/W ACTIVE Clear active vector bit 1: clear all state information for active NMI, fault, and interrupts. 0: do not clear. This bit self-clears. It it the responsibility of the application to reinitialize the stack. 0 VECTRESET R/W System Reset bit 1: reset system. 0: do not reset system. Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this bit is also zero cleared. Note 1: Little-endian is the default memory format for this product. Note 2: When SYSRESETREQ is output, warm reset is performed on this product. is cleared by warm reset. Page 107 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.2.24 TMPM361F10FG System Handler Priority Register Each exception is provided with eight bits of a System Handler Priority Register. The following shows the addresses of the System Handler Priority Registers corresponding to each exception. 24 23 31 PRI_7 16 15 8 7 0 PRI_6 PRI_5 PRI_4 (Usage Fault) (Bus Fault) (Memory Management) PRI_10 PRI_9 PRI_8 PRI_15 PRI_14 PRI_13 (SysTick) (PendSV) 0xE000_ED18 PRI_11 0xE000_ED1C (SVCall) 0xE000_ED20 PRI_12 (Debug Monitor) The number of bits to be used for assigning a priority varies with each product. This product uses three bits for assigning a priority. The following shows the fields of the System Handler Priority Registers for Memory Management, Bus Fault and Usage Fault. Unused bits return "0" when read, and writing to unused bits has no effect. 31 30 bit symbol After reset 25 24 - - - 0 0 0 0 0 0 0 21 20 19 18 17 16 - - - - - 0 0 0 0 0 0 0 14 13 12 11 10 9 8 - - - - - 15 bit symbol PRI_5 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - - 0 0 0 0 0 0 bit symbol PRI_4 0 Bit Symbol 0 Type Function 31-29 PRI_7 R/W Reserved 28-24 − R Read as 0, 23-21 PRI_6 R/W Priority of Usage Fault 20-16 − R Read as 0, 15-13 PRI_5 R/W Priority of Bus Fault 12-8 − R Read as 0, 7-5 PRI_4 R/W Priority of Memory Management 4-0 − R Read as 0, 2013/5/31 26 - 22 PRI_6 After reset 27 - 0 0 After reset 28 23 bit symbol After reset Bit 29 PRI_7 Page 108 TMPM361F10FG 7.6.2.25 System Handler Control and State Register 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - USGFAULT BUSFAULT MEMFAULT ENA ENA ENA After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SYSTICKACT PENDSVACT - 0 0 0 3 2 bit symbol SVCALL BUSFAULT MEMFAULT USGFAULT PENDED PENDED PENDED PENDED 0 0 0 0 7 6 5 4 After reset bit symbol SVCALLACT - - - After reset 0 0 0 0 Bit Bit Symbol Type ACT 0 0 ACT 0 1 0 BUSFAULT MEMFAULT ACT ACT 0 0 Function 31-19 − R Read as 0, 18 USGFAULT R/W Usage Fault ENA USGFAULT MONITOR 0: Disabled 1: Enabled 17 BUSFAUL R/W TENA Bus Fault 0: Disable 1: Enable 16 MEMFAULT R/W ENA Memory Management 0: Disable 1: Enable 15 SVCALL R/W SVCall 0: Not pended PENDED 1: Pended 14 BUSFAULT R/W Bus Fault 0: Not pended PENDED 1: Pended 13 MEMFAULT R/W PENDED Memory Management 0: Not pended 1: Pended 12 USGFAULT R/W PENDED Usage Fault 0: Not pended 1: Pended 11 SYSTICKACT R/W SysTick 0: Inactive 1: Active 10 PENDSVACT R/W PendSV 0: Inactive 1: Active 9 − R Read as 0, 8 MONITORACT R/W Debug monitor 0: Inactive 1: Active 7 SVCALLACT R/W SVCall 0: Inactive 1: Active 6-4 − R Read as 0, Page 109 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers Bit 3 Bit Symbol USGFAULT TMPM361F10FG Type R/W ACT Function Usage Fault 0: Inactive 1: Active 2 − R Read as 0, 1 BUSFAULT R/W Bus Fault ACT 0: Inactive 1: Active 0 MEMFAULT ACT R/W Memory management 0: Inactive 1: Active Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not repair stack contents. 2013/5/31 Page 110 TMPM361F10FG 7.6.3 Clock generator registers 7.6.3.1 CGIMCGA (CG Interrupt Mode Control Register A) 31 bit symbol 30 - After reset 29 28 27 EMCG3 26 EMST3 25 24 - INT3EN 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 - INT2EN 1 0 0 0 Undefined 0 13 12 11 10 9 8 - INT1EN bit symbol - After reset 0 0 EMCG2 15 14 EMST2 bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INT0EN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCG1 EMST1 EMCG0 0 1 EMST0 Type Function 31 − R Read as 0, 30-28 EMCG3[2:0] R/W active level setting of INT3 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 27-26 EMST3[1:0] R active level of INT3 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 25 − R Reads as undefined. 24 INT3EN R/W INT3 clear input 0: Disable 1: Enable 23 − R Read as 0, 22-20 EMCG2[2:0] R/W active level setting of INT2 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 19-18 EMST2[1:0] R active level of INT2 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 17 − R Reads as undefined. 16 INT2EN R/W INT2 clear input 0:Disable 1: Enable 15 − R Read as 0, Page 111 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers Bit 14-12 Bit Symbol EMCG1[2:0] TMPM361F10FG Type R/W Function active level setting of INT1 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 11-10 EMST1[1:0] R active level of INT1 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 9 − R Reads as undefined. 8 INT1EN R/W INT1 clear input 0: Disable 1: Enable 7 − R Read as 0, 6-4 EMCG0[2:0] R/W active level setting of INT0 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 3-2 EMST0[1:0] R active level of INT0 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 1 − R Reads as undefined. 0 INT0EN R/W INT0 clear input 0: Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. 2013/5/31 Page 112 TMPM361F10FG 7.6.3.2 CGIMCGB (CG Interrupt Mode Control Register B) 31 bit symbol 30 - After reset 29 28 27 EMCG7 26 EMST7 25 24 - INT7EN 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 - INT6EN 1 0 0 0 Undefined 0 13 12 11 10 9 8 - INT5EN bit symbol - After reset 0 0 EMCG6 15 14 EMST6 bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INT4EN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCG5 EMST5 EMCG4 0 1 EMST4 Type Function 31 − R Read as 0, 30-28 EMCG7[2:0] R/W active level setting of INT7 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 27-26 EMST7[1:0] R active level of INT7 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 25 − R Reads as undefined. 24 INT7EN R/W INT7 clear input 0: Disable 1: Enable 23 − R Read as 0, 22-20 EMCG6[2:0] R/W active level setting of INT6 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 19-18 EMST6[1:0] R active level of INT6 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 17 − R Reads as undefined. 16 INT6EN R/W INT6 clear input 0:Disable 1: Enable 15 − R Read as 0, 14-12 EMCG5[2:0] R/W active level setting of INT5 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge Page 113 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers Bit 11-10 Bit Symbol EMST5[1:0] TMPM361F10FG Type R Function active level of INT5 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 9 − R Reads as undefined. 8 INT5EN R/W INT5 clear input 0: Disable 1: Enable 7 − R Read as 0, 6-4 EMCG4[2:0] R/W active level setting of INT4 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 3-2 EMST4[1:0] R active level of INT4 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 1 − R Reads as undefined. 0 INT4EN R/W INT4 clear input 0: Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. 2013/5/31 Page 114 TMPM361F10FG 7.6.3.3 CGIMCGD (CG Interrupt Mode Control Register D) 31 bit symbol 30 - After reset 29 28 27 EMCGF 26 EMSTF 25 24 - INTFEN 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 bit symbol - - INTEEN After reset 0 0 EMCGE 1 0 0 EMSTE 0 Undefined 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset 0 0 1 0 0 0 Undefined 0 Bit Bit Symbol Type Function 31 − R Read as 0, 30-28 EMCGF[2:0] R/W active level setting of INTF standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 27-26 EMSTF[1:0] R active level of INTF standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 25 − R Reads as undefined. 24 INTFEN R/W INTF clear input 0: Disable 1: Enable 23 − R Read as 0, 22-20 EMCGE[2:0] R/W active level setting of INTE standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge 19-18 EMSTE[1:0] R active level of INTE standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 17 − R Reads as undefined. 16 INTEEN R/W INTE clear input 0: Disable 1: Enable 15 − R Read as 0, 14-12 − R/W Write optional value. 11-10 − R Read as 0, 9 − R Read as undefined. 8 − R/W Write as 0. 7 − R Read as 0, 6-4 − R/W Write optional value. Page 115 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers Bit Bit Symbol TMPM361F10FG Type Function 3-2 − R Read as 0, 1 − R Read as undefined. 0 − R/W Write as 0. Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. 2013/5/31 Page 116 TMPM361F10FG 7.6.3.4 CGIMCGE (CG Interrupt Mode Control Register E) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 1 0 0 0 Undefined 0 23 22 21 20 19 18 17 16 - INTIEN 1 0 0 0 Undefined 0 13 12 11 10 9 8 - INTHEN bit symbol - After reset 0 0 EMCGI 15 14 EMSTI bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INTGEN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCGH EMSTH EMCGG 0 1 EMSTG Type Function 31 − R Read as 0, 30-28 − R/W Write optional value. 27-26 − R Read as 0, 25 − R Read as undefined. 24 − R/W Write as 0. 23 − R Read as 0, 22-20 EMCGI[2:0] R/W active level setting of INTRMCRX standby clear request. Set it as shown below. 011: Rising edge 19-18 EMSTI[1:0] R R active level of INTRMCRX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge 17 − R Read as undefined. 16 INTIEN R/W INTRMCRX clear input 0:Disable 1: Enable 15 − R Read as 0, 14-12 EMCGH[2:0] R/W active level setting of INTCECTX standby clear request. Set it as shown below. 011: Riseing edge 11-10 EMSTH[1:0] R active level of INTCECTX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge 9 − R Read as undefined 8 INTHEN R/W INTCECTX Clear input 0:Disable 1: Enable 7 − R Read as 0, 6-4 EMCGG[2:0] R/W active level setting of INTCECRX standby clear request. Set it as shown below. 011: Rising edge Page 117 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers Bit 3-2 Bit Symbol EMSTG[1:0] TMPM361F10FG Type R Function active level of INTCECRX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge 1 − R Read as undefined. 0 INTGEN R/W INTCECRX Clear input 0:Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. 2013/5/31 Page 118 TMPM361F10FG 7.6.3.5 CGIMCGF (CG Interrupt Mode Control Register F) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 - INTLEN bit symbol - After reset 0 0 1 0 0 0 Undefined 0 7 6 5 4 3 2 1 0 - INTKEN 0 0 0 Undefined 0 bit symbol - After reset 0 Bit Bit Symbol EMCGL EMSTL EMCGK 0 1 EMSTK Type Function 31-15 − R Read as 0, 14-12 EMCGL[2:0] R/W active level setting of INTKWUP standby clear request Set it as shown below. 001: "H" level 11-10 EMSTL[1:0] R active level of INTKWUP standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 9 − R Read as undefined. 8 INTLEN R/W INTKWUP clear input 0: Disable 1: Enable 7 − R Read as 0, 6-4 EMCGK[2:0] R/W active level setting of INTRTC standby clear request Set it as shown below. 010: Falling edge 3-2 EMSTK[1:0] R active level of INTRTC standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 1 − R Read as undefined. 0 INTKEN R/W INTRTC clear input 0: Disable 1: Enable Note 1: is effective only when is set to "100" for both rising and falling edge. The active level used for the reset of standby can be checked by referring . If interrupts are cleared with the CGICRCG register, is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the . Setting them simultaneously is prohibited. Page 119 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.3.6 bit symbol After reset TMPM361F10FG CGICRCG (CG Interrupt Request Clear Register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol - - - After reset 0 0 0 Bit Bit Symbol ICRCG Type Function 31-5 − R Read as 0, 4-0 ICRCG[4:0] W Clear interrupt requests. 0_0000: INT0 0_1000: Reserved 1_0000: INTCECRX 0_0001: INT1 0_1001: Reserved 1_0001: INTCECTX 0_0010: INT2 0_1010: Reserved 1_0010: INTRMCRX 0_0011: INT3 0_1011: Reserved 1_0011: Reserved 0_0100: INT4 0_1100: Reserved 1_0100: INTRTC 0_0101: INT5 0_1101: Reserved 1_0101: INTKWUP 0_0110: INT6 0_1110: INTE 1_0110 to 1_1111: Reserved 0_0111: INT7 0_1111: INTF Read as 0. 2013/5/31 0 Page 120 TMPM361F10FG 7.6.3.7 CGNMIFLG (NMI Flag Register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - NMIFLG1 NMIFLG0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as 0, 1 NMIFLG1 R NMI source generation flag 0: not applicable 1:generated from NMI pin. 0 NMIFLG0 R NMI source generation flag 0: not applicable 1: generated from WDT Note: are cleared to "0" when they are read. Page 121 2013/5/31 7. 7.6 Exceptions Exception / Interrupt-Related Registers 7.6.3.8 TMPM361F10FG CGRSTFLG (Reset Flag Register) bit symbol After pin reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After pin reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After pin reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - SYSRSTF BUPRSTF WDTRSTF PINRSTF PONRSTF After pin reset 0 0 0 0 0 0 1 1 Bit Bit Symbol Type Function 31-5 − R Read as 0, 4 SYSRSTF R/W Debug reset flag (Note1) 0: "0" is written 1: Reset from SYSRESETREQ 3 BUPRSTF R/W BACKUP reset flag 0: "0" is written 1: Reset from BACKUP mode release 2 WDTRSTF R/W WDT reset flag 0: "0" is written 1: Reset from WDT 1 PINRSTF R/W RESET pin flag 0: "0" is written 1: Reset from RESET pin 0 PONRSTF R/W Power-on flag 0: "0" is written 1: Reset from power-on reset Note 1: This flag indicates a reset generated by the SYSRESETREQ bit of the Application Interrupt and Reset Control Register of the CPU's NVIC. Note 2: This product has power-on reset circuit and this register is initialized only by power-on reset. Therefore, "1" is set to the bit in initial reset state right after power-on. Note that this bit is not set by the second and subsequent resets and this register is not cleared automatically. Write "0" to clear the register. 2013/5/31 Page 122 TMPM361F10FG 8. Input / Output Ports 8.1 Port Functions 8.1.1 Function list TMPM361F10FG has 76 ports. Besides the ports function, these ports can be used as I/O pins for peripheral functions. Table 8-1 shows the port function table. Table 8-1 Port Function List Port PIn Input / Output Programmable Pullup Schmitt Noise Input Filter Programmable Open-drain Pull-down Function pin Port A PA0 I/O Pull-up − − ο D0 / AD0 PA1 I/O Pull-up − − ο D1 / AD1 PA2 I/O Pull-up − − ο D2 / AD2 PA3 I/O Pull-up − − ο D3 / AD3 PA4 I/O Pull-up − − ο D4 / AD4 PA5 I/O Pull-up − − ο D5 / AD5 PA6 I/O Pull-up − − ο D6 / AD6 PA7 I/O Pull-up − − ο D7 / AD7 PB0 I/O Pull-up − − ο D8 / AD8 PB1 I/O Pull-up − − ο D9 / AD9 PB2 I/O Pull-up − − ο D10 / AD10 PB3 I/O Pull-up − − ο D11 / AD11 PB4 I/O Pull-up − − ο D12 / AD12 PB5 I/O Pull-up − − ο D13 / AD13 PB6 I/O Pull-up − − ο D14 / AD14 PB7 I/O Pull-up − − ο D15 / AD15 PE0 I/O Pull-up ο − ο A17 , TB5IN0 PE1 I/O Pull-up ο − ο A18 , TB5IN1 PE2 I/O Pull-up ο − ο A19 , TB6IN0 PE3 I/O Pull-up ο − ο A20 , TB6IN1 PE4 I/O Pull-up ο − ο A21 , TXD0 PE5 I/O Pull-up ο − ο A22 , RXD0 PE6 I/O Pull-up ο − ο A23 , SCLK0 , CTS0 PE7 I/O Pull-up ο ο ο INT5 , SCOUT PF0 I/O Pull-up ο − ο TRACECLK PF1 I/O Pull-up ο − ο TRACEDATA0 , SWV PF2 I/O Pull-up ο − ο TRACEDATA1 PF3 I/O Pull-up ο − ο TRACEDATA2 PF4 I/O Pull-up ο − ο TRACEDATA3 Port B Port E Port F Page 123 2013/5/31 8. 8.1 Input / Output Ports Port Functions TMPM361F10FG Table 8-1 Port Function List Port PIn Input / Output Programmable Pullup Schmitt Noise Input Filter Programmable Open-drain Pull-down Function pin Port G PG0 I/O Pull-up ο − ο SDA1/ SO1 , TB7IN0 PG1 I/O Pull-up ο − ο SCL1/ SI1 , TB7IN1 PG2 I/O Pull-up ο − ο SCK1 , CS0 PG3 I/O Pull-up ο ο ο INT6 , CS1 PG4 I/O Pull-up ο − ο SDA2/ SO2 , TB9IN0 PG5 I/O Pull-up ο − ο SCL2/ SI2 , TB9IN1 PG6 I/O Pull-up ο − ο SCK2 , CS3 PG7 I/O Pull-up ο ο ο INT7 , WDTOUT PI0 I/O Pull-up ο − ο BOOT PI1 I/O − ο − ο(Note3) CEC PI2 I/O ο ο ο INTE PI3 I/O ο ο ο INTF PJ0 Input Pull-up ο − − AIN0 PJ1 Input Pull-up ο − − AIN1 PJ2 Input Pull-up ο − − AIN2 PJ3 Input Pull-up ο − − AIN3 , ADTRG PJ4 Input Pull-up ο ο − AIN4 , KWUP0 PJ5 Input Pull-up ο ο − AIN5 , KWUP1 PJ6 Input Pull-up ο ο − AIN6 , KWUP2 PJ7 Input Pull-up ο ο − AIN7 , KWUP3 PL0 I/O Pull-up ο − ο SDA0/ SO0 , TB0OUT PL1 I/O Pull-up ο − ο SCL0/ SI0 , TB1OUT PL2 I/O Pull-up ο − ο SCK0 , TB2OUT PL3 I/O Pull-up ο ο ο INT0 , TB3OUT PL4 I/O Pull-up ο − ο TXD1 , TB4OUT , SDA3 PL5 I/O Pull-up ο − ο RXD1 , TB5OUT , SCL3 PL6 I/O Pull-up ο − ο SCLK1 , TB6OUT , CTS1 PL7 I/O Pull-up ο ο ο INT1 , TB7OUT PM0 I/O Pull-up ο − ο SCLK2 , TB1IN0 , CTS2 PM1 I/O Pull-up ο − ο TXD2 , TB1IN1 PM2 I/O Pull-up ο − ο RXD2 , ALARM PM3 I/O Pull-up ο ο ο INT2 , TB3OUT PM4 I/O Pull-up ο − ο SCLK3 , CTS3 PM5 I/O Pull-up ο − ο TXD3 PM6 I/O Pull-up ο − ο RXD3 PM7 I/O Pull-up ο ο ο INT3 PN0 I/O Pull-up ο − ο TXD4 Port I Pull-up (Note2) Pull-up (Note2) Port J Port L Port M Port N 2013/5/31 Page 124 TMPM361F10FG Table 8-1 Port Function List Port PIn Input / Output Programmable Pullup Schmitt Noise Input Filter Programmable Open-drain Pull-down Function pin PN1 I/O Pull-up ο − ο RXD4 PN2 I/O Pull-up ο − ο SCLK4 , TB2IN0 , CTS4 PN3 I/O Pull-up ο ο ο INT4 , TB2IN1 , RMC PP0 I/O Pull-up ο − ο CS2 PP1 I/O Pull-up − − ο − PP2 I/O Pull-up ο − ο BLS0 , SPDO PP3 I/O Pull-up − − ο BLS1 , SPDI PP4 I/O Pull-up − − ο WE , SPCLK PP5 I/O Pull-up − − ο OE , SPFSS PP6 I/O Pull-up ο − ο ALE Port P ο : Exist - : Not exist Note 1: The noise elimination width of the noise filter is approximately 30 ns under typical conditions. Note 2: The port is always pulled-up in spite of PIPUP. Note 3: N-ch open drain port Page 125 2013/5/31 8. 8.1 Input / Output Ports Port Functions 8.1.2 TMPM361F10FG Port Registers Outline The following registers need to be configured to use ports. ・ PxDATA: Port x data register To read / write port data. ・ PxCR: Port x output control register To control output. PxIE needs to be configured to control input. ・ PxFRn: Port x function register n To set function. An assigned function can be activated by setting "1". ・ PxOD: Port x open drain control register To control the programmable open drain. Programmable open drain is function to be materialized pseudo-open-drain by setting the PxOD. When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control programmable pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE : Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. 2013/5/31 Page 126 TMPM361F10FG 8.1.3 Port states in STOP Mode Input and output in STOP mode are enabled / disabled by the CGSTBYCR . If PxIE or PxCR is enabled with =1, input or output is enabled respectively in STOP mode.If =0, both input and output are disabled in STOP mode except for some ports even if PxIE or PxCR are enabled. Table 8-2 shows the pin conditions in STOP mode. Table 8-2 Port conditions in STOP mode Pin name Excluding port I/O = 0 = 1 X1, XT1 Input only × × X2, XT2 Output only "High" Level Output "High"Level Output Input only ο ο Input ο ο Output × Depend on PxCR[m] Input ο ο Output × Depend on PxCR[m] Input × Depend on PxCR[m] RESET, NMI, MODE PL3, PL7, PM3, PM7, PN3, PE7, PG3, PG7, , PI2, PI3 (When used for interrupt (PxFRn=1) and input is enabled (PxIE=1)) (Note) PJ4,PJ5, PJ6, PJ7 (When used for KWUP (PxFRn=1) and input is enabled (PxIE=1)) (Note) Port PF0, PF1, PF2, PF3, PF4 (When used for trace data output (PxFRn=1)) (Note) PA7-PA0, PB7-PB0, PE6-PE0, PP6-PP2, PP0 (When used for external bus (PxFRn=1) and input is enabled for data bus (PxIE=1)) (Note) Other ports Output Input Depend on PxCR[m] ο Output ο Depend on PxCR[m] Input × Depend on PxCR[m] Output × Depend on PxCR[m] ο : Input or output enabled × : Input or output disabled Note:"x" indicates a port number, "m" a corresponding bit and "n" a function register number. Page 127 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2 TMPM361F10FG Port functions This chapter describes the port registers detail. This chapter describes only "circuit type" reading circuit configuration. For detailed circuit diagram, refer to "8.3 Block Diagrams of Ports". 8.2.1 Port A (PA0 to PA7) The port A is a general-purpose, 8-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port A performs the external bus interface. Reset initializes all bits of the port A as general-purpose ports with input, output and pull-up disabled. If this port is used for the external bus function, PACR, PAFR1 and PAIE must be set to "1". The port A has a types of function register. If you use the port A as a general-purpose port, set "0" to the corresponding bit of the a registers. If you use the port A as other than a general-purpose port, set "1" to the corresponding bit of the function register. 8.2.1.1 Type 8.2.1.2 Port A Circuit Type 7 6 5 4 3 2 1 0 T1 T1 T1 T1 T1 T1 T1 T1 Port A Register Base Address = 0x400C_0000 Register name Address (Base+) Port A data register PADATA 0x0000 Port A output control register PACR 0x0004 Port A function register 1 PAFR1 0x0008 Port A open drain control register PAOD 0x0028 Port A pull-up control register PAPUP 0x002C PAIE 0x0038 Port A input control register 2013/5/31 Page 128 TMPM361F10FG 8.2.1.3 bit symbol After reset PADATA (Port A data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PA7 to PA0 R/W Port A data register 8.2.1.4 bit symbol After reset PACR (Port A output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7C PA6C PA5C PA4C PA3C PA2C PA1C PA0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PA7C to PA0C R/W Output 0: Disable 1: Enable Page 129 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.1.5 PAFR1 (Port A function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7F1 PA6F1 PA5F1 PA4F1 PA3F1 PA2F1 PA1F1 PA0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PA7F1 R/W 0 : PORT 1 : D7, AD7 6 PA6F1 R/W 0: PORT 1: D6, AD6 5 PA5F1 R/W 0: PORT 1: D5, AD5 4 PA4F1 R/W 3 PA3F1 R/W 2 PA2F1 R/W 1 PA1F1 R/W 0 PA0F1 R/W 0: PORT 1: D4, AD4 0: PORT 1: D3, AD3 0: PORT 1: D2, AD2 0: PORT 1: D1, AD1 0: PORT 1: D0, AD0 2013/5/31 Page 130 TMPM361F10FG 8.2.1.6 PAOD (Port A open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7OD PA6OD PA5OD PA4OD PA3OD PA2OD PA1OD PA0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31 to 8 − R Read as "0". 7 to 0 PA7OD to PA0OD R/W 0 : CMOS 8.2.1.7 1 : Open-drain PAPUP (Port A pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7UP PA6UP PA5UP PA4UP PA3UP PA2UP PA1UP PA0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PA7UP to PA0UP R/W Pull-Up 0: Disable 1: Enable Page 131 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.1.8 bit symbol After reset PAIE (Port A input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PA7IE PA6IE PA5IE PA4IE PA3IE PA2IE PA1IE PA0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PA7IE to PA0IE R/W Input 0: Disable 1: Enable 2013/5/31 Page 132 TMPM361F10FG 8.2.2 Port B (PB0 to PB7) The port B is a general-purpose, 8-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port B performs the external bus interface. Reset initializes all bits of the port B as general-purpose ports with input, output and pull-up disabled. The port B has a types of function register. If you use the port B as a general-purpose port, set "0" to the corresponding bit of the a registers. If you use the port B as other than a general-purpose port, set "1" to the corresponding bit of the function register. 8.2.2.1 Type 8.2.2.2 Port B Circuit Type 7 6 5 4 3 2 1 0 T1 T1 T1 T1 T1 T1 T1 T1 Port B Register Base Address = 0x400C_0100 Register name Address (Base+) Port B data register PBDATA 0x0000 Port B output control register PBCR 0x0004 Port B function register 1 PBFR1 0x0008 Port B open drain control register PBOD 0x0028 Port B pull-up control register PBPUP 0x002C PBIE 0x0038 Port B input control register Page 133 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.2.3 bit symbol After reset PBDATA (Port B data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PB7 to PB0 R/W Port B data register 8.2.2.4 bit symbol After reset PBCR (Port B output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7C PB6C PB5C PB4C PB3C PB2C PB1C PB0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PB7C to PB0C R/W Output 0: Disable 1: Enable 2013/5/31 Page 134 TMPM361F10FG 8.2.2.5 PBFR1 (Port B function register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7F1 PB6F1 PB5F1 PB4F1 PB3F1 PB2F1 PB1F1 PB0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PB7F1 R/W 0 : PORT 1 : D15, AD15 6 PB6F1 R/W 0: PORT 1: D14, AD14 5 PB5F1 R/W 0: PORT 1: D13, AD13 4 PB4F1 R/W 3 PB3F1 R/W 2 PB2F1 R/W 1 PB1F1 R/W 0 PB0F1 R/W 0: PORT 1: D12, AD12 0: PORT 1: D11, AD11 0: PORT 1: D10, AD10 0: PORT 1: D9, AD9 0: PORT 1: D8, AD8 Page 135 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.2.6 PBOD (Port B open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7OD PB6OD PB5OD PB4OD PB3OD PB2OD PB1OD PB0OD After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PB7OD to PB0OD R/W 0 : CMOS 8.2.2.7 1 : Open-drain PBPUP (Port B pull-up control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7UP PB6UP PB5UP PB4UP PB3UP PB2UP PB1UP PB0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PB7UP to PB0UP R/W Pull-up 0: Disable 1: Enable 2013/5/31 Page 136 TMPM361F10FG 8.2.2.8 bit symbol After reset PBIE (Port B input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PB7IE PB6IE PB5IE PB4IE PB3IE PB2IE PB1IE PB0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PB7IE to PB0IE R/W Input 0: Disable 1: Enable Page 137 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.3 TMPM361F10FG Port E (PE0 to PE7) The port E is a general-purpose, 8-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port E performs the external bus interface, the serial channel, external signal interrupt, the 16-bit timer / counter and clock output function. Reset initializes all bits of the port E as general-purpose ports with input, output and pull-up disabled. The Port E has three types of of function register. If you use the port E as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port E as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the some function registers at the same time. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PxFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.3.1 Type 8.2.3.2 Port E Circuit Type 7 6 5 4 3 2 1 0 T6 T4 T3 T2 T3 T3 T3 T3 Port E register Base Address = 0x400C_0400 Register name Address (Base+) Port E data register PEDATA 0x0000 Port E output control register PECR 0x0004 Port E function register 1 PEFR1 0x0008 Port E function register 2 PEFR2 0x000C Port E function register 3 PEFR3 0x0010 Port E open drain control register PEOD 0x0028 Port E pull-up control register PEPUP 0x002C PEIE 0x0038 Port E input control register 2013/5/31 Page 138 TMPM361F10FG 8.2.3.3 bit symbol After reset PEDATA (Port E data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PE7 to PE0 R/W Port E data register 8.2.3.4 bit symbol After reset PECR (Port E output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7C PE6C PE5C PE4C PE3C PE2C PE1C PE0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PE7C to PE0C R/W Output 0: Disable 1: Enable Page 139 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.3.5 PEFR1 (Port E function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PE6F1 PE5F1 PE4F1 PE3F1 PE2F1 PE1F1 PE0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 − R/W Write "0". 6 PE6F1 R/W 0: PORT 5 PE5F1 R/W 4 PE4F1 R/W 3 PE3F1 R/W 2 PE2F1 R/W 1:A23 0: PORT 1: A22 0: PORT 1: A21 0: PORT 1: A20 0: PORT 1: A19 1 PE1F1 R/W 0: PORT 1: A18 0 PE0F1 R/W 0: PORT 1: A17 2013/5/31 Page 140 TMPM361F10FG 8.2.3.6 PEFR2 (Port E function register 2) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7F2 PE6F2 PE5F2 PE4F2 PE3F2 PE2F2 PE1F2 PE0F2 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PE7F2 R/W 0 : PORT 1 : INT5 6 PE6F2 R/W 0: PORT 1:SCLK0 5 PE5F2 R/W 0: PORT 1: RXD0 4 PE4F2 R/W 3 PE3F2 R/W 2 PE2F2 R/W 1 PE1F2 R/W 0 PE0F2 R/W 0: PORT 1: TXD0 0 : PORT 1 : TB6IN1 0: PORT 1: TB6IN0 0: PORT 1: TB5IN1 0: PORT 1: TB5IN0 Page 141 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.3.7 PEFR3 (Port E function register 3) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7F3 PE6F3 - - - - - - After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PE7F3 R/W 0 : PORT 6 PE6F3 R/W 5-4 − R/W Write "0". 3 to 0 − R Read as "0". 1 : SCOUT 0 : PORT 1 : CTS0 8.2.3.8 PEOD (Port E open drain control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7OD PE6OD PE5OD PE4OD PE3OD PE2OD PE1OD PE0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PE7OD to PE0OD R/W 0 : CMOS 2013/5/31 1 : Open-drain Page 142 TMPM361F10FG 8.2.3.9 PEPUP (Port E pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7UP PE6UP PE5UP PE4UP PE3UP PE2UP PE1UP PE0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PE7UP to PE0UP R/W Pull-up 0: Disable 1: Enable 8.2.3.10 PEIE (Port E input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PE7IE PE6IE PE5IE PE4IE PE3IE PE2IE PE1IE PE0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PE7IE to PE0IE R/W Intput 0: Disable 1: Enable Page 143 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.4 TMPM361F10FG Port F (PF0 to PF4) The port F is a general-purpose, 5-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port F performs the debug interface function. Reset initializes all bits of the port F as general-purpose ports with input, output and pull-up disabled. The Port F has one types of of function register. If you use the port F as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port F as other than a general-purpose port, set "1" to the corresponding bit of the function register. 8.2.4.1 Type 8.2.4.2 Port F Circuit Type 7 6 5 4 3 2 1 0 − − − T7 T7 T7 T7 T7 Port F Register Base Address = 0x400C_0500 Register name Address (Base+) Port F data register PFDATA 0x0000 Port F output control register PFCR 0x0004 Port F function register 1 PFFR1 0x0008 Port F open drain control register PFOD 0x0028 Port F pull-up control register PFPUP 0x002C PFIE 0x0038 Port F input control register 2013/5/31 Page 144 TMPM361F10FG 8.2.4.3 bit symbol After reset PFDATA (Port F data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PF4 PF3 PF2 PF1 PF0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol TypF Function 31-5 − R Read as "0". 4-0 PF4 to PF0 R/W Port F data register 8.2.4.4 bit symbol After reset PFCR (Port F output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PF4C PF3C PF2C PF1C PF0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-5 − R Read as "0". 4-0 PF4C to PF0C R/W Output 0: Disable 1: Enable Page 145 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.4.5 PFFR1 (Port F function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PF4F1 PF3F1 PF2F1 PF1F1 PF0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-5 − R Read as "0". 4 PF4F1 R/W 0: PORT 3 PF3F1 R/W 2 PF2F1 R/W 1 PF1F1 R/W 1: TRACEDATA3 0: PORT 1: TRACEDATA2 0: PORT 1: TRACEDATA1 0: PORT 1: TRACEDATA0 / SWV 0 PF0F1 R/W 0: PORT 1: TRACECLK 2013/5/31 Page 146 TMPM361F10FG 8.2.4.6 PFOD (Port F open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PF4OD PF3OD PF2OD PF1OD PF0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-5 − R Read as "0". 4-0 PF4OD to PF0OD R/W 0 : CMOS 8.2.4.7 1 : Open-drain PFPUP (Port F pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PF4UP PF3UP PF2UP PF1UP PF0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-5 − R Read as "0". 4-0 PF4UP to PF0UP R/W Pull-up 0: Disable 1: Enable Page 147 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.4.8 bit symbol After reset PFIE (Port F input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PF4IE PF3IE PF2IE PF1IE PF0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-5 − R Read as "0". 4-0 PF4IE to PF0IE R/W Input 0: Disable 1: Enable 2013/5/31 Page 148 TMPM361F10FG 8.2.5 Port G (PG0 to PG7) The port G is a general-purpose, 8-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port G performs the serial bus interface, the external signal interrupt, 16bit timer / event counter , the external bus interface and Watch-dog timer output functions. Reset initializes all bits of the port G as general-purpose ports with input, output and pull-up disabled. The Port G has three types of of function register. If you use the port G as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port G as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the three function registers at the same time. To use the external interrupt input for releasing STOP mode, select this function in the PGFR1 and enable input in the PGIE register. These settings enable the interrupt input even if the CGSTBYCR bit in the clock / mode control block is set to stop driving of pins during STOP mode. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PxFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.5.1 Type 8.2.5.2 Port G Circuit Type 7 6 5 4 3 2 1 0 T11 T9 T8 T8 T10 T9 T8 T8 Port G register Base Address = 0x400C_0600 Register name Address (Base+) Port G data register PGDATA 0x0000 Port G output control register PGCR 0x0004 Port G function register 1 PGFR1 0x0008 Port G function register 2 PGFR2 0x000C Port G function register 3 PGFR3 0x0010 Port G open drain control register PGOD 0x0028 Port G pull-up control register PGPUP 0x002C PGIE 0x0038 Port G input control register Page 149 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.5.3 bit symbol After reset PGDATA (Port G data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PG7 to PG0 R/W Port G data register 8.2.5.4 bit symbol After reset PGCR (Port G output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7C PG6C PG5C PG4C PG3C PG2C PG1C PG0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PG7C to PG0C R/W Output 0: Disable 1: Enable 2013/5/31 Page 150 TMPM361F10FG 8.2.5.5 PGFR1 (Port G function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7F1 PG6F1 PG5F1 PG4F1 PG3F1 PG2F1 PG1F1 PG0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PG7F1 R/W 0: PORT 1:INT7 6 PG6F1 R/W 0: PORT 1: SCK2 5 PG5F1 R/W 0: PORT 1: SCL2 / SI2 4 PG4F1 R/W 3 PG3F1 R/W 2 PG2F1 R/W 1 PG1F1 R/W 0 PG0F1 R/W 0: PORT 1: SDA2 / SO2 0: PORT 1: INT6 0: PORT 1: SCK1 0: PORT 1: SCL1 / SI1 0: PORT 1: SDA1 / SO1 Page 151 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.5.6 PGFR2 (Port G function register 2) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - PG5F2 PG4F2 - - PG1F2 PG0F2 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-6 − R/W Write "0". 5 PG5F2 R/W 0: PORT 4 PG4F2 R/W 1: TB9IN1 0: PORT 1: TB9IN0 3-2 − R Read as "0". 1 PG1F2 R/W 0: PORT 0 PG0F2 R/W 1: TB7IN1 0: PORT 1: TB7IN0 2013/5/31 Page 152 TMPM361F10FG 8.2.5.7 PGFR3 (Port G function register 3) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7F3 PG6F3 - - PG3F3 PG2F3 - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PG7F3 R/W 0 : PORT 6 PG6F3 R/W 5-4 − R Read as "0". 3 PG3F3 R/W 0 : PORT 1 : WDTOUT 0 : PORT 1 : CS3 1 : CS1 2 PG2F3 R/W 1 to 0 − R 0 : PORT 1 : CS0 Read as "0". Page 153 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.5.8 PGOD (Port G open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7OD PG6OD PG5OD PG4OD PG3OD PG2OD PG1OD PG0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PG7OD to PG0OD R/W 0 : CMOS 8.2.5.9 PGPUP (Port G pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 1 : Open-drain 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7UP PG6UP PG5UP PG4UP PG3UP PG2UP PG1UP PG0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PG7UP to PG0UP R/W Pull-up 0: Disable 1: Enable 2013/5/31 Page 154 TMPM361F10FG 8.2.5.10 PGIE (Port G input control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PG7IE PG6IE PG5IE PG4IE PG3IE PG2IE PG1IE PG0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PG7IE to PG0IE R/W Input 0: Disable 1: Enable Page 155 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.6 TMPM361F10FG Port I (PI0 to PI3) The port I is a general-purpose, 4-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port I performs the external signal interrupt input, CEC input and the operation mode setting. Reset initializes PI0 as general-purpose ports with input, output and pull-up disabled. Reset initializes PI1, PI2 and PI3 as general-purpose ports with input, output disabled. Pull-up is enabled for PI2, PI3. PI1 is N-ch open-drain ports. The Port I has one types of of function register. If you use the port I as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port I as other than a general-purpose port, set "1" to the corresponding bit of the function register. While RESET pin is "Low", input and pull-up of PI0(BOOT) are enabled. At the rising edge of RESET pin, if PI0(BOOT) is "High", TMPM361F10FG enters the single chip mode and boots from the on chip Flash ROM. If PI0(BOOT) is "Low", TMPM361F10FG enters the single boot mode and boots from the on chip BOOTROM. For details of the single boot mode, refer to "Flash memory operation". Note:In modes other than STOP mode, interrupt input is enabled regardless of the PxFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.6.1 Type 8.2.6.2 Port I Circuit Type 7 6 5 4 3 2 1 0 − − − − T16 T16 T15 T14 Port I register Base Address = 0x400C_0800 Register name Address (Base+) Port I data register PIDATA 0x0000 Port I output control register PICR 0x0004 Port I function register 1 PIFR1 0x0008 Port I open drain control register PIOD 0x0028 Port I pull-up control register PIPUP 0x002C PIIE 0x0038 Port I input control register 2013/5/31 Page 156 TMPM361F10FG 8.2.6.3 PIDATA (Port I data register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PI3 PI2 PI1 PI0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3-0 PI3 to PI0 R/W Port I data register Page 157 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.6.4 bit symbol After reset PICR (Port I output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PI3C PI2C PI1C PI0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3-0 PI3C-PI0C R/W Output 0: Disable 1: Enable 2013/5/31 Page 158 TMPM361F10FG 8.2.6.5 PIFR1 (Port I function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PI3F1 PI2F1 PI1F1 - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3 PI3F1 R/W 0: PORT 2 PI2F1 R/W 1 PI1F1 R/W 0 − R/W 1: INTF 0: PORT 1: INTE 0: PORT 1: CEC Write "0". Page 159 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.6.6 PIOD (Port I open drain control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PI3OD PI2OD - PI0OD After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3-2 PI3OD-PI2OD R/W 0 : CMOS 1 − R Read as "0". 0 PI0OD R/W 0 : CMOS 1 : Open-drain 1 : Open-drain 8.2.6.7 PIPUP (Port I pull-up control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 16 23 22 21 20 19 18 17 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - PI0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 − R Read as "0". 0 PI0UP R/W Pull-up 0: Disable 1: Enable 2013/5/31 Page 160 TMPM361F10FG 8.2.6.8 bit symbol After reset PIIE (Port I input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PI3IE PI2IE PI1IE PI0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3-0 PI3IE-PI0IE R/W Input 0: Disable 1: Enable Page 161 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.7 TMPM361F10FG Port J (PJ0 to PJ7) The port J is an 8-bit input port. Besides the general-purpose input function, the port J performs the AD converter and the key-on wake-up function. Reset initializes all bits of the port J as general-purpose ports with input and pull-up disabled. The Port J has one types of of function register. If you use the port J as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port J as other than a general-purpose port, set "1" to the corresponding bit of the function register. Note:Unless you use all the bits of port J as analog input pins, conversion accurary may be reduced.Be sure to verify that this causes no problem on your system. 8.2.7.1 Type 8.2.7.2 Port J Circuit Type 7 6 5 4 3 2 1 0 T19 T19 T19 T19 T18 T17 T17 T17 Port J register Base Address = 0x400C_0900 Register name Address (Base+) Port J data register PJDATA 0x0000 Port J function register 2 PJFR2 0x000C Port J pull-up control register PJPUP 0x002C PJIE 0x0038 Port J input control register 2013/5/31 Page 162 TMPM361F10FG 8.2.7.3 bit symbol After reset PJDATA (Port J data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 After reset 1 1 1 1 1 1 1 1 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PJ7 to PJ0 R Port J data register Page 163 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.7.4 PJFR2 (Port J function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7F2 PJ6F2 PJ5F2 PJ4F2 PJ3F2 - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PJ7F2 R/W 0: PORT 6 PJ6F2 R/W 5 PJ5F2 R/W 4 PJ4F2 R/W 1: KWUP3 0: PORT 1: KWUP2 0: PORT 1: KWUP1 0: PORT 1: KWUP0 3 PJ3F2 R/W 0: PORT 1: ADTRG 2-0 2013/5/31 − R Read as "0". Page 164 TMPM361F10FG 8.2.7.5 PJPUP (Port J pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7UP PJ6UP PJ5UP PJ4UP PJ3UP PJ2UP PJ1UP PJ0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PJ7UP to PJ0UP R/W Pull-up 0: Disable 1: Enable 8.2.7.6 PJIE (Port J input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PJ7IE PJ6IE PJ5IE PJ4IE PJ3IE PJ2IE PJ1IE PJ0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PJ7IE to PJ0IE R/W Input 0: Disable 1: Enable Page 165 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.8 TMPM361F10FG Port L (PL0 to PL7) The port L is a general-purpose, 8-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port L performs the serial channel , the serial bus interface, the external signal interrupt input and 16bit timer / event counter function. Reset initializes all bits of the port L as general-purpose ports with input, output and pull-up disabled. The Port L has three types of of function register. If you use the port L as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port L as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the some function registers at the same time. Note:: In modes other than STOP mode, interrupt input is enabled regardless of the PxFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.8.1 Type 8.2.8.2 Port L Circut Type 7 6 5 4 3 2 1 0 T21 T24 T23 T22 T21 T20 T20 T20 Port L register Base Address = 0x400C_0B00 Register name Address (Base+) Port L data register PLDATA 0x0000 Port L output control register PLCR 0x0004 Port L function register 1 PLFR1 0x0008 Port L function register 2 PLFR2 0x000C Port L function register 3 PLFR3 0x0010 Port L open drain control register PLOD 0x0028 Port L pull-up control register PLPUP 0x002C PLIE 0x0038 Port L input control register 2013/5/31 Page 166 TMPM361F10FG 8.2.8.3 bit symbol After reset PLDATA (Port L data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PL7 to PL0 R/W Port L data register 8.2.8.4 bit symbol After reset PLCR (Port L output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7C PL6C PL5C PL4C PL3C PL2C PL1C PL0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PL7C to PL0C R/W Output 0: Disable 1: Enable Page 167 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.8.5 PLFR1 (Port K function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7F1 PL6F1 PL5F1 PL4F1 PL3F1 PL2F1 PL1F1 PL0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PL7F1 R/W 0: PORT 1:INT1 6 PL6F1 R/W 0: PORT 1: SCLK1 5 PL5F1 R/W 0: PORT 1: RXD1 4 PL4F1 R/W 3 PL3F1 R/W 2 PL2F1 R/W 1 PL1F1 R/W 0 PL0F1 R/W 0: PORT 1: TXD1 0: PORT 1: INT0 0: PORT 1: SCK0 0: PORT 1: SCL0 / SI0 0: PORT 1: SDA0 / SO0 2013/5/31 Page 168 TMPM361F10FG 8.2.8.6 PLFR2 (Port L function register 2) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7F2 PL6F2 PL5F2 PL4F2 PL3F2 PL2F2 PL1F2 PL0F2 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PL7F2 R/W 0: PORT 1: TB7OUT 6 PL6F2 R/W 0: PORT 1: TB6OUT 5 PL5F2 R/W 0: PORT 1: TB5OUT 4 PL4F2 R/W 3 PL3F2 R/W 2 PL2F2 R/W 1 PL1F2 R/W 0 PL0F2 R/W 0: PORT 1: TB4OUT 0: PORT 1: TB3OUT 0: PORT 1: TB2OUT 0: PORT 1: TB1OUT 0: PORT 1: TB0OUT Page 169 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.8.7 PLFR3 (Port L function register 3) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PL6F3 PL5F3 PL4F3 - - - - After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6 PL6F3 R/W 0 : PORT 5 PL5F3 R/W 4 PL4F3 R/W 3-0 − R 1 : CTS1 0 : PORT 1 : SCL3 0 : PORT 1 : SDA3 8.2.8.8 Read as "0". PLOD (Port L open drain control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7OD PL6OD PL5OD PL4OD PL3OD PL2OD PL1OD PL0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PL7OD to PL0OD R/W 0 : CMOS 2013/5/31 1 : Open-drain Page 170 TMPM361F10FG 8.2.8.9 PLPUP (Port L pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7UP PL6UP PL5UP PL4UP PL3UP PL2UP PL1UP PL0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PL7UP to PL0UP R/W Pull-up 0: Disable 1: Enable 8.2.8.10 PLIE (Port L input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PL7IE PL6IE PL5IE PL4IE PL3IE PL2IE PL1IE PL0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PL7IE to PL0IE R/W Input 0: Disable 1: Enable Page 171 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.9 TMPM361F10FG Port M (PM0 to PM7) The port M is a general-purpose, 8-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port M performs the serial channel, the external signal interrupt input,16bit timer / event counter and the alarm output function. Reset initializes all bits of the port M as general-purpose ports with input, output and pull-up disabled. The Port M has three types of of function register. If you use the port M as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port M as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the some function registers at the same time. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PxFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.9.1 Type 8.2.9.2 Port Circuit Type 7 6 5 4 3 2 1 0 T30 T29 T28 T27 T21 T23 T26 T25 Port M register Base Address = 0x400C_0C00 Register name Address (Base+) Port M data register PMDATA 0x0000 Port M output control register PMCR 0x0004 Port M function register 1 PMFR1 0x0008 Port M function register 2 PMFR2 0x000C Port M function register 3 PMFR3 0x0010 Port M open drain control registert PMOD 0x0028 Port M pull-up control register PMPUP 0x002C PMIE 0x0038 Port M input control register 2013/5/31 Page 172 TMPM361F10FG 8.2.9.3 bit symbol After reset PMDATA (Port M data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PM7 to PM0 R/W Port M data register 8.2.9.4 bit symbol After reset PMCR (Port M output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PM7C PM6C PM5C PM4C PM3C PM2C PM1C PM0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PM7C to PM0C R/W Output 0: Disable 1: Enable Page 173 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.9.5 PMFR1 (Port M function register 1) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PM7F1 PM6F1 PM5F1 PM4F1 PM3F1 PM2F1 PM1F1 PM0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 PM7F1 R/W 0: PORT 1: INT3 6 PM6F1 R/W 0: PORT 1: RXD3 5 PM5F1 R/W 0: PORT 1: TXD3 4 PM4F1 R/W 3 PM3F1 R/W 2 PM2F1 R/W 1 PM1F1 R/W 0 PM0F1 R/W 0: PORT 1: SCLK3 0: PORT 1: INT2 0: PORT 1: RXD2 0: PORT 1: TXD2 0: PORT 1: SCLK2 2013/5/31 Page 174 TMPM361F10FG 8.2.9.6 PMFR2 (Port M function register 2) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PM3F2 PM2F2 PM1F2 PM0F2 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3 PM3F2 R/W 0: PORT 2 PM2F2 R/W 1 PM1F2 R/W 0 PM0F2 R/W 1: TB3OUT 0: PORT 1: ALARM 0: PORT 1: TB1IN1 0: PORT 1: TB1IN0 Page 175 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.9.7 PMFR3 (Port M function register 3) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - PM4F3 - - - PM0F3 After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-5 − R Read as "0". 4 PM4F3 R/W 0 : PORT 3-1 − R Read as "0". 0 PM0F3 R/W 0 : PORT 1 : CTS3 1 : CTS2 8.2.9.8 PMOD (Port M open drain control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 16 23 22 21 20 19 18 17 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PM7OD PM6OD PM5OD PM4OD PM3OD PM2OD PM1OD PM0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PM7OD to PM0OD R/W 0 : CMOS 2013/5/31 1 : Open-drain Page 176 TMPM361F10FG 8.2.9.9 PMPUP (Port M pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PM7UP PM6UP PM5UP PM4UP PM3UP PM2UP PM1UP PM0UP After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PM7UP to PM0UP R/W Pull-up 0: Disable 1: Enable 8.2.9.10 PMIE (Port M input control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol PM7IE PM6IE PM5IE PM4IE PM3IE PM2IE PM1IE PM0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-0 PM7IE to PM0IE R/W Input 0: Disable 1: Enable Page 177 2013/5/31 8. 8.2 Input / Output Ports Port functions 8.2.10 TMPM361F10FG Port N (PN0 to PN3) The port N is a general-purpose, 4-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port N performs the serial channel, the external signal interrupt input, 16bit timer / counter and the remote control signal preprocessor input function. Reset initializes all bits of the port N as general-purpose ports with input, output and pull-up disabled. The Port N has three types of of function register. If you use the port N as a general-purpose port, set "0" to the corresponding bit of the three registers. If you use the port N as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the some function registers at the same time. Note:In modes other than STOP mode, interrupt input is enabled regardless of the PxFR register setting if input is enabled in PxIE. Make sure to disable unused interrupts when programming the device. 8.2.10.1 Type 8.2.10.2 Port N Circuit Type 7 6 5 4 3 2 1 0 − − − − T30 T25 T29 T28 Port N register Base Address = 0x400C_0D00 Register name Address (Base+) Port N data register PNDATA 0x0000 Port N output control register PNCR 0x0004 Port N function register 1 PNFR1 0x0008 Port N function register 2 PNFR2 0x000C Port N function register 3 PNFR3 0x0010 Port N open drain control registert PNOD 0x0028 Port N pull-up control register PNPUP 0x002C PNIE 0x0038 Port N input control register 2013/5/31 Page 178 TMPM361F10FG 8.2.10.3 bit symbol After reset PNDATA (Port N data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3 PN2 PN1 PN0 After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-4 − R/W Write "0". 3-0 PN3 to PN0 R/W Port N data register 8.2.10.4 PNCR (Port N output control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 16 23 22 21 20 19 18 17 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3C PN2C PN1C PN0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-4 − R/W Write "0". 3-0 PN3C to PN0C R/W Output 0: Disable 1: Enable Page 179 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.10.5 bit symbol After reset PNFR1 (Port N function register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3F1 PN2F1 PN1F1 PN0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-4 − R/W Write "0". 3 PN3F1 R/W 0: PORT 2 PN2F1 R/W 1: INT4 0: PORT 1: SCLK4 1 PN1F1 R/W 0: PORT 1: RXD4 0 PN0F1 R/W 0: PORT 1: TXD4 2013/5/31 Page 180 TMPM361F10FG 8.2.10.6 bit symbol After reset PNFR2 (Port N function register 2) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3F2 PN2F2 - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-6 − R/W Write "0". 5-4 − R Read as "0". 3 PN3F2 R/W 0: PORT 1: TB2IN1 2 PN2F2 R/W 1-0 − R 0: PORT 1: TB2IN0 Read as "0". Page 181 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.10.7 bit symbol After reset PNFR3 (Port N function register 3) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3F3 PN2F3 - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-6 − R/W Write "0". 5-4 − R Read as "0". 3 PN3F3 R/W 0 : PORT 1 : RMC 2 PN2F3 R/W 1 to 0 − R 0 : PORT 1 : CTS4 2013/5/31 Read as "0". Page 182 TMPM361F10FG 8.2.10.8 PNOD (Port N open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3OD PN2OD PN1OD PN0OD After reset 0 0 0 0 0 0 0 0 26 25 24 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-4 − R/W Write "0". 3-0 PN3OD to PN0OD R/W 0 : CMOS 8.2.10.9 1 : Open-drain PNPUP (Port N pull-up control register) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3UP PN2UP PN1UP PN0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-4 − R/W Write "0". 3-0 PN3UP to PN0UP R/W Pull-up 0: Disable 1: Enable Page 183 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.10.10 bit symbol After reset PNIE (Port N input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PN3IE PN2IE PN1IE PN0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-4 − R/W Write "0". 3-0 PN3IE to PN0IE R/W Input 0: Disable 1: Enable 2013/5/31 Page 184 TMPM361F10FG 8.2.11 Port P (PP0 to PP6) The port P is a general-purpose, 7-bit input / output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input / output function, the port P performs the external bus interface, and SSP function. Reset initializes all bits of the port P as general-purpose ports with input, output and pull-up disabled. The Port P has two types of of function register. If you use the port P as a general-purpose port, set "0" to the corresponding bit of the two registers. If you use the port P as other than a general-purpose port, set "1" to the corresponding bit of the function register. Do not set "1" to the both function registers at the same time. 8.2.11.1 Type 8.2.11.2 Port P Circuit Type 7 6 5 4 3 2 1 0 − T5 T35 T34 T33 T32 T31 T5 Port P register Base Address = 0x400C_0F00 Register name Address (Base+) Port P data register PPDATA 0x0000 Port P output control register PPCR 0x0004 Port P function register 1 PPFR1 0x0008 Port P function register 2 PPFR2 0x000C Port P open drain control register PPOD 0x0028 Port P pull-up control register PPPUP 0x002C PPIE 0x0038 Port P input control register Page 185 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.11.3 bit symbol After reset PPDATA (Port P data register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PP6 PP5 PP4 PP3 PP2 PP1 PP0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6-0 PP6 to PP0 R/W Port P data register 8.2.11.4 bit symbol After reset PPCR (Port P output control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PP6C PP5C PP4C PP3C PP2C PP1C PP0C After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6-0 PP6C to PP0C R/W Output 0: Disable 1: Enable 2013/5/31 Page 186 TMPM361F10FG 8.2.11.5 bit symbol After reset PPFR1 (Port P function register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PP6F1 PP5F1 PP4F1 PP3F1 PP2F1 PP1F1 PP0F1 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6 PP6F1 R/W 0: PORT 1: ALE 5 PP5F1 R/W 0: PORT 1: OE 4 PP4F1 R/W 0: PORT 1: WE 3 PP3F1 R/W 0: PORT 2 PP2F1 R/W 1 PP1F1 R/W Write "0". 0 PP0F1 R/W 0: PORT 1: BLS1 0: PORT 1: BLS0 1: CS2 Page 187 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.11.6 bit symbol After reset PPFR2 (Port P function register 2) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - PP5F2 PP4F2 PP3F2 PP2F2 - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-6 − R Read as "0". 5 PP5F2 R/W 0: PORT 4 PP4F2 R/W 3 PP3F2 R/W 2 PP2F2 R/W 1: SPFSS 0: PORT 1: SPCLK 0: PORT 1: SPDI 0: PORT 1: SPDO 1-0 2013/5/31 − R Read as "0". Page 188 TMPM361F10FG 8.2.11.7 PPOD (Port P open drain control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PP6OD PP5OD PP4OD PP3OD PP2OD PP1OD PP0OD After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6-0 PP6OD to PP0OD R/W 0 : CMOS 8.2.11.8 1 : Open-drain PPPUP (Port P pull-up control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PP6UP PP5UP PP4UP PP3UP PP2UP PP1UP PP0UP After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6-0 PP6UP to PP0UP R/W Pull-up 0: Disable 1: Enable Page 189 2013/5/31 8. 8.2 Input / Output Ports Port functions TMPM361F10FG 8.2.11.9 bit symbol After reset PPIE (Port P input control register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - PP6IE PP5IE PP4IE PP3IE PP2IE PP1IE PP0IE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as "0". 6-0 PP6IE to PP0IE R/W Input 0: Disable 1: Enable 2013/5/31 Page 190 TMPM361F10FG 8.3 Block Diagrams of Ports 8.3.1 Port Types The ports are classified as shown below. Please refer to the following pages for the block diagrams of each port type. Dot lines in the figure indicate the part of the equivalent circuit described in the "Block diagrams of ports". Table 8-3 Function lists Type Input/ Output Function1 Function2 Function3 Analog Pull-up Programmable open-drain Note T1 I/O I/O − − − R ο T2 I/O Output Output − − R ο T3 I/O Output Input − − R ο T4 I/O Output I/O Input − R ο T5 I/O Output − − − R ο T6 I/O Input (int) Output − − R ο T7 I/O Output − − − R ο T8 I/O I/O Input − − R ο T9 I/O I/O − Input − R ο T10 I/O Input (int) − Input − R ο T11 I/O Input (int) − Output − R ο T12 I/O I/O Input − − R ο T13 I/O Input (int) Input − − R ο T14 I/O − − − − R ο BOOT input enabled during reset T15 I/O Input − − − − − Nch open drain port T16 I/O Input (int) − − − NoR ο T17 Input − − − ο R − T18 Input Input − − ο R − T19 Input Input − − ο R − T20 I/O I/O Output − − R ο T21 I/O Input Output − − R ο T22 I/O Output Output − − R ο T23 I/O Input Output − − R ο T24 I/O I/O Output Input − R ο T25 I/O I/O Input Input − R ο T26 I/O Output Input − − R ο T27 I/O I/O − Output − R ο T28 I/O Output − − − R ο T29 I/O Input − − − R ο T30 I/O Input (int) − − − R ο T31 I/O − − − − R ο T32 I/O Output Output − − R ο T33 I/O Output Input − − R ο T34 I/O Output I/O − − R ο T35 I/O Output − − − R ο int : Interrupt input R : Forced disable during reset - : Not exist NoR : Unaffected by reset o : exist Page 191 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports TMPM361F10FG Table 8-3 Function lists Type Input/ Output Function1 Function2 Function3 Analog Pull-up Programmable open-drain T36 I/O Output Output Output − R ο T37 I/O Output Input Input − R ο T38 I/O I/O Output Output − R ο I/O Input Input Output − R ο T39 int : Interrupt input R : Forced disable during reset - : Not exist NoR : Unaffected by reset o : exist 2013/5/31 Page 192 Note TMPM361F10FG 8.3.2 Type T1 Drive Disable in STOP Mode (Set by ) SMC Data Output Enable PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 Internal data bus PxFR1 (Function Control) Function 1 Output PxDATA (Output Latch) I/O Port 0 PxOD (Open-drain Control) PxIE (Input Control) SMC Data Input enable 0 1 Port Read Function input Figure 8-1 Port Type T1 Page 193 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.3 TMPM361F10FG Type T2 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function 1 Output 1 Function Output 2 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-2 Port Type T2 2013/5/31 Page 194 TMPM361F10FG 8.3.4 Type T3 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) PxFR2 (Function Control) Internal data bus Function Control 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-3 Port Type T3 Page 195 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.5 TMPM361F10FG Type T4 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) PxFR3 (Function Control) Function Output 2 1 Function Output 1 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input 1 Function Input 2 Figure 8-4 Port Type T4 2013/5/31 Page 196 TMPM361F10FG 8.3.6 Type T5 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-5 Port Type T5 Page 197 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.7 TMPM361F10FG Type T6 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-6 Port Type T6 2013/5/31 Page 198 TMPM361F10FG 8.3.8 Type T7 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-7 Port Type T7 Page 199 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.9 TMPM361F10FG Type T8 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input 1 Function Input 2 Figure 8-8 Port Type T8 2013/5/31 Page 200 TMPM361F10FG 8.3.10 Type T9 Drive Disable in STOP Mode (Set by ) PxPUP (ࣉࣝ࢔ࢵࣉไᚚ) (Pull-up Control) 1 PxCR (Output (ฟຊไᚚ) Control) RESET 0 PxFR1 (Function (ᶵ⬟ไᚚ) Control) Internal data bus PxFR3 (Function Control) Function Output 1 1 Function Output 3 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-9 Port Type T9 Page 201 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.11 TMPM361F10FG Type T10 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR3 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-10 Port Type T10 2013/5/31 Page 202 TMPM361F10FG 8.3.12 Type T11 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR3 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-11 Port Type T11 Page 203 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.13 TMPM361F10FG Type T12 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open drain control) PxIE (Input Control) 0 1 Port Read Function Input 1 Function Input 2 Figure 8-12 Port Type T12 2013/5/31 Page 204 TMPM361F10FG 8.3.14 TypeT13 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) I/O Port PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Function Input Figure 8-13 Port Type T13 Page 205 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.15 TMPM361F10FG Type T14 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) Internal data bus PxCR (Output Control) RESET PxDATA (Output Latch) I/O Port PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read BOOT Figure 8-14 Port Type T14 2013/5/31 Page 206 TMPM361F10FG 8.3.16 Type T15 Drive Disable in STOP Mode (Set by ) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus Function Output 1 1 I/O Port 0 PxDATA (Output Latch) Open Drain PxIE (Input Control) 0 1 Port Read Figure 8-15 Port Type T15 Page 207 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.17 TMPM361F10FG TypeT16 Drive Disable in STOP Mode (Set by ) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus Pull up 㸦Output㸧 I/O Port PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-16 Port Type T16 2013/5/31 Page 208 TMPM361F10FG 8.3.18 Type T17 Drive Disable in STOP Mode (Set by ) RESET PxPUP (ࣉࣝ࢔ࢵࣉไᚚ) (Pull-up Control) Internal data bus Input Port PxIE (Input Control) Port Read Analog Input Figure 8-17 Port Type T17 Page 209 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.19 TMPM361F10FG Type T18 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) RESET Internal data bus Input Port PxFR2 (Function Control) PxIE (Input Control) Port Read Function Input Analog Input Figure 8-18 Port Type T18 2013/5/31 Page 210 TMPM361F10FG 8.3.20 Type T19 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) RESET Internal data bus Input Port PxFR2 (Function Control) PxIE (Input Control) Port Read Interrupt Input Noise Filter (QV7\S) Analog Input Figure 8-19 Port Type T19 Page 211 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.21 TMPM361F10FG Type T20 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 2 1 Function 1 Output 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-20 Port Type T20 2013/5/31 Page 212 TMPM361F10FG 8.3.22 Type T21 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-21 Port Type T21 Page 213 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.23 TMPM361F10FG Type T22 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function 1 Output 1 Function 1 Output 2 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-22 Port Type T22 2013/5/31 Page 214 TMPM361F10FG 8.3.24 Type T23 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function 1 Output I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-23 Port Type T23 Page 215 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.25 TMPM361F10FG Type T24 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) PxFR3 (Function Control) Function Output 1 1 Function Output 2 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read FunctionI nput 3 Function Input 1 Figure 8-24 Port Type T24 2013/5/31 Page 216 TMPM361F10FG 8.3.26 Type T25 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) PxFR3 (Function Control) Function 1 Output I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input 1 Function Input 2 Function Input 3 Figure 8-25 Port Type T25 Page 217 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.27 TMPM361F10FG TypeT26 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-26 Port Type T26 2013/5/31 Page 218 TMPM361F10FG 8.3.28 Type T27 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR3 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input 1 Function Input 3 Figure 8-27 Port Type T27 Page 219 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.29 TMPM361F10FG Type T28 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus Function 1 Output I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-28 Port Type T28 2013/5/31 Page 220 TMPM361F10FG 8.3.30 Type T29 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus I/O Port PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input 1 Figure 8-29 Port Type T29 Page 221 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.31 TMPM361F10FG Type T30 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus I/O Port PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Interrupt Input Noise Filter (QV7\S) Figure 8-30 Port Type T30 2013/5/31 Page 222 TMPM361F10FG 8.3.32 Type T31 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET Internal data bus I/O Port PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-31 Port Type T31 Page 223 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.33 TMPM361F10FG Type T32 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 2 1 Function 1 Output 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-32 Port Type T32 2013/5/31 Page 224 TMPM361F10FG 8.3.34 Type T33 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-33 Port Type T33 Page 225 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.35 TMPM361F10FG Type T34 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output 1 1 Function Output 2 1 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-34 Port Type T34 2013/5/31 Page 226 TMPM361F10FG 8.3.36 Type T35 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function 1 Output 1 Function 1 Output 2 I/O Port 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-35 Port Type T35 Page 227 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.37 TMPM361F10FG Type T36 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) PxFR3 (Function Control) Function 1 Function 1 Output 2 Function 1 Output 3 Output 1 0 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Figure 8-36 Port Type T36 2013/5/31 Page 228 I/O Port TMPM361F10FG 8.3.38 Type T37 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) RESET 0 PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) Function Output PxFR3 (Function Control) 1 I/O Port 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input 1 Function Input 2 Figure 8-37 Port Type T37 Page 229 2013/5/31 8. 8.3 Input / Output Ports Block Diagrams of Ports 8.3.39 TMPM361F10FG Type T38 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) 1 PxCR (Output Control) 0 RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) PxFR3 (Function Control) Function Output 1 1 Function Output 2 1 Function Output 3 1 I/O Port 0 0 0 PxDATA (Output Latch) PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Figure 8-38 Port Type T38 2013/5/31 Page 230 TMPM361F10FG 8.3.40 Type T39 Drive Disable in STOP Mode (Set by ) PxPUP (Pull-up Control) PxCR (Output Control) RESET PxFR1 (Function Control) Internal data bus PxFR2 (Function Control) I/O Port PxFR3 (Function Control) Function 1 Output PxDATA (Output Latch) 0 PxOD (Open-drain Control) PxIE (Input Control) 0 1 Port Read Function Input Interrupt Input Noise Filter (QV7\S) Figure 8-39 Port Type T39 Page 231 2013/5/31 8. 8.4 Input / Output Ports Appendix (Port setting List) 8.4 TMPM361F10FG Appendix (Port setting List) The following table shows the register setting for each function. Initialization of the ports where the ο does not exist in the "After reset" field is set to "0" for all register settings. Setting for the bit "×" can be arbitrarily-specified. 8.4.1 Port A setting Table 8-4 Port Setting List (Port A) Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 2013/5/31 Port Type T1 T1 T1 T1 T1 T1 T1 T1 Function After PACR PAFR1 PAOD PAPUP PAIE Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input Port 0 0 × × 1 Output Port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 reset Page 232 TMPM361F10FG 8.4.2 Port B Setting Table 8-5 Port Setting List (Port B) Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Port Type T1 T1 T1 T1 T1 T1 T1 T1 Function After PBCR PBFR1 PBOD PBPUP PBIE Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 Data (I/O) / Address data (I/O) 1 1 × × 1 reset Page 233 2013/5/31 8. 8.4 Input / Output Ports Appendix (Port setting List) 8.4.3 TMPM361F10FG Port E Setting Table 8-6 Port Setting List (Port E) Pin PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 2013/5/31 Port Type T3 T3 T3 T3 T2 T3 T4 T6 Function After PECR PEFR1 PEFR2 PEFR3 PEOD PEPUP PEIE Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 TB5IN0 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 TB5IN1 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 TB6IN0 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 TB6IN1 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 TXD0 (Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 RXD0 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 Address (Output) 1 1 0 0 × × 0 SCLK0 (Input) 0 0 1 0 × × 1 SCLK0 (Output) 1 0 1 0 × × 0 CTS0 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT5 (Input) 0 0 1 0 × × 1 SCOUT (Output) 1 0 0 1 × × 0 reset Page 234 TMPM361F10FG 8.4.4 Port F Setting Table 8-7 Port Setting List (Port F) Pin PF0 PF1 PF2 PF3 PF4 Port T7 T7 T7 T7 T7 After Function PFCR PFFR1 PFOD PFPUP PFIE Input port 0 0 × × 1 Output port 1 0 × × 0 TRACECLK (Output) 1 1 × × 0 Input port 0 0 × × 1 Output port 1 0 × × 0 TRACEDATA0/SWV (Output) 1 1 × × 0 Input port 0 0 × × 1 Output port 1 0 × × 0 TRACEDATA1 (Output) 1 1 × × 0 Input port 0 0 × × 1 Output port 1 0 × × 0 TRACEDATA2 (Output) 1 1 × × 0 Input port 0 0 × × 1 Output port 1 0 × × 0 TRACEDATA3 (Output) 1 1 × × 0 Type reset Page 235 2013/5/31 8. 8.4 Input / Output Ports Appendix (Port setting List) 8.4.5 TMPM361F10FG Port G Setting Table 8-8 Port Setting List (Port G) Pin PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 2013/5/31 Port Type T8 T8 T9 T10 T8 T8 T9 T11 Function After PGCR PGFR1 PGFR2 PGFR3 PGOD PGPUP PGIE Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SO1 (Output) 1 1 0 0 × × 0 SDA1 (I/O) 1 1 0 0 1 × 1 TB7IN0 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SI1 (Input) 0 1 0 0 × × 1 SCL1 (I/O) 1 1 0 0 1 × 1 TB7IN1 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCK1 (Input) 0 1 0 0 × × 1 SCK1 (Output) 1 1 0 0 × × 0 CTS0 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT6 (Input) 0 1 0 0 × × 1 CTS1 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SO2 (Output) 1 1 0 0 × × 0 SDA2 (I/O) 1 1 0 0 1 × 1 TB9IN0 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SI2 (Input) 0 1 0 0 × × 1 SCL2 (I/O) 1 1 0 0 1 × 1 TB9IN1 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCK2 (Input) 0 1 0 0 × × 1 SCK2 (Output) 1 1 0 0 × × 0 CTS3 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT7 (Input) 0 1 0 0 × × 1 WDTOUT (Output) 1 0 0 1 × × 0 reset Page 236 TMPM361F10FG 8.4.6 Port I Setting Table 8-9 Port Setting List (Port I) Pin PI0 PI1 PI2 PI3 Port Type T14 T15 T16 T16 Function After PICR PIFR1 PIOD PIPUP PIIE Input port 0 0 × × 1 Output port 1 0 × × 0 Input port 0 0 × × 1 Output port 1 0 × × 0 CEC (Input) 0 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 INTE (Input) 0 1 × × 1 Input port 0 0 × × 1 Output port 1 0 × × 0 INTF (Input) 0 1 × × 1 reset Note:The PI0 input and pull-up are enabled and act as BOOT input pin while a RESET is in "Low" state. Page 237 2013/5/31 8. 8.4 Input / Output Ports Appendix (Port setting List) 8.4.7 TMPM361F10FG Port J Setting Table 8-10 Port Setting List (Port J) Pin PJ0 PJ1 T17 T17 PJ2 T17 PJ3 T18 PJ4 PJ5 PJ6 PJ7 2013/5/31 Port Type T19 T19 T19 T19 Function After PJFR2 PJPUP PJIE Input port 0 × 1 Analog input 0 0 0 Input port 0 × 1 Analog input 0 0 0 Input port 0 × 1 Analog input 0 0 0 Input port 0 × 1 Analog input 0 0 0 ADTRG (Input) 1 × 1 Input port 0 × 1 Analog input 0 0 0 KWUP0 (Input) 1 × 1 Input port 0 × 1 Analog input 0 0 0 KWUP1 (Input) 1 × 1 Input port 0 × 1 Analog input 0 0 0 KWUP2 (Input) 1 × 1 Input port 0 × 1 Analog input 0 0 0 KWUP3 (Input) 1 × 1 Page 238 reset TMPM361F10FG 8.4.8 Port L Setting Table 8-11 Port Setting List (Port L) Pin PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 Port Type T20 T20 T20 T21 T22 T23 T24 T21 Function After PLCR PLFR1 PLFR2 PLFR3 PLOD PLPUP PLIE Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SO0 (Output) 1 1 0 0 × × 0 SDA0 (I/O) 1 1 0 0 1 × 1 TB0OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SI0 (Input) 0 1 0 0 × × 1 SCL0 (I/O) 1 1 0 0 1 × 1 TB1OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCK0 (Input) 0 1 0 0 × × 1 SCK0 (Output) 1 1 0 0 × × 0 TB2OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT0 (Input) 0 1 0 0 × × 1 TB3OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 TXD1 (Output) 1 1 0 0 × × 0 SDA3 (I/O) 1 0 0 1 1 × 1 TB4OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 RXD1 (Input) 0 1 0 0 × × 1 SCL3 (I/O) 1 0 0 1 1 × 1 TB5OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCLK1 (Input) 0 1 0 0 × × 1 SCLK1 (Output) 1 1 0 0 × × 0 TB6OUT(Output) 1 0 1 0 × × 0 CTS1 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT1 (Input) 0 1 0 0 × × 1 TB7OUT(Output) 1 0 1 0 × × 0 reset Page 239 2013/5/31 8. 8.4 Input / Output Ports Appendix (Port setting List) 8.4.9 TMPM361F10FG Port M Setting Table 8-12 Port Setting List (Port M) Pin PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 2013/5/31 Port Type T25 T26 T23 T21 T27 T28 T29 T30 Function After PMCR PMFR1 PMFR2 PMFR3 PMOD PMPUP PMIE Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCLK2 (Input) 0 1 0 0 × × 1 SCLK2 (Output) 1 1 0 0 × × 0 TB1IN0 (Input) 0 0 1 0 × × 1 CTS2 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 TXD2 (Output) 1 1 0 0 × × 0 TB1IN1 (Input) 0 0 1 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 RXD2 (Input) 0 1 0 0 × × 1 ALARM (Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT2 (Input) 0 1 0 0 × × 1 TB3OUT(Output) 1 0 1 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCLK3 (Input) 0 1 0 0 × × 1 SCLK3 (Output) 1 1 0 0 × × 0 CTS3 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 TXD3 (Output) 1 1 0 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 RXD3 (Input) 0 1 0 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT3 (Input) 0 1 0 0 × × 1 reset Page 240 TMPM361F10FG 8.4.10 Port N setting Table 8-13 Port Setting List (Port N) Pin PN0 PN1 PN2 PN3 Port Type T28 T29 T25 T30 Function After PNCR PNFR1 PNFR2 PNFR3 PNOD PNPUP PNIE Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 TXD4 (Output) 1 1 0 0 × × 0 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 RXD2 (Input) 0 1 0 0 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 SCLK4 (Input) 0 1 0 0 × × 1 SCLK4 (Output) 1 1 0 0 × × 0 TB2IN0 (Input) 0 0 1 0 × × 1 CTS4 (Input) 0 0 0 1 × × 1 Input port 0 0 0 0 × × 1 Output port 1 0 0 0 × × 0 INT4 (Input) 0 1 0 0 × × 1 TB2IN1 (Input) 0 0 1 0 × × 1 RMC (Input) 0 0 0 1 × × 1 reset Page 241 2013/5/31 8. 8.4 Input / Output Ports Appendix (Port setting List) 8.4.11 TMPM361F10FG Port P Setting Table 8-14 Port Setting List (Port P) Pin PP0 PP1 PP2 PP3 PP4 PP5 PP6 2013/5/31 Port Type T5 T31 T32 T33 T34 T35 T5 Function After PPCR PPFR1 PPFR2 PPOD PPPUP PPIE Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 CS2 (Output) 1 1 0 × × 0 Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 BLS0 (Output) 1 1 0 × × 0 SPDO (Output) 1 0 1 × × 0 Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 BLS1 (Output) 1 1 0 × × 0 SPDI (Input) 0 0 1 × × 1 Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 WE (Output) 1 1 0 × × 0 SPCLK (Input) 0 0 1 × × 1 SPCLK (Output) 1 0 1 × × 0 Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 OE (Output) 1 1 0 × × 0 SPFSS (Input) 0 0 1 × × 1 SPFSS (Output) 1 0 1 × × 0 Input port 0 0 0 × × 1 Output port 1 0 0 × × 0 ALE (Output) 1 1 0 × × 0 reset Page 242 TMPM361F10FG 9. DMA Controller(DMAC) 9.1 Overview The table below lists its major functions. Table 9-1 DMA controller functions (1 Unit) Item Function Description Number of channels 2ch - Number of DMA request - DMA Start up trigger Bus master Priority FIFO 16 Hardware start Started with DMA request for peripheral circuit. Software start Started with a write to the DMACxSoftBReq register. 32bit × 1 (AHB) Fixed Low : CH1 4word × 2ch (1word = 32bit) Bus width 8/16/32bit Burst size 1/4/8/16/32/64/128/256 Number of transfers up to 4095 Address - High : CH0 Transfer source address Transfer destination address Endian Littleendian is supported. Transfer type Peripheral to Memory Settable individually for transfer source and destination. increment not increment increment not increment It is possible to specify whether Source and Destination addresses should increment or should not increment. (Address wrapping is not supported.) When "Memory to Memory" is selected, hardware start for DMA startup is not supported. Memory to Peripheral Refer to the DMACxCnConfiguration for more information. Memory to Memory Peripheral to Peripheral Particular peripheral can be assigned as Source or Distination when "Peripheral to Peripheral" is selected. Regarding to peripheral assigned, refer to "9.4.1 Peripheral function supported with Peripheral to Peripheral Transfer". TMPM361F10FG does not support Peripheral to Peripheral. Interrupt function Transfer end interrupt (INTDMACxTC) - Error interrupt (INTDMACxERR) Special Function Scatter/gather function - Page 243 2013/5/31 9. 9.2 DMA Controller(DMAC) DMA transfer type 9.2 TMPM361F10FG DMA transfer type Table 9-2 DMA transfer type No. DMA transfer type 1 Memory to Peripheral 2 Peripheral to Memory Circuit generated DMA DMA request type request Peripheral (Destination) Burst request Peripheral Burst request / (Source) single request Description In case of 1word transmission, set to the "1" for burst size of DMA controller. If the amount of transfer data is not an integral multiple of the burst size, both burst and single request can be used. If amount of transfer data is more or equal than burst size, the single request is ignored and the burst transfer is used. If it becomes less than burst size, the single transfer is used. Enabling the DMAC starts data transfer without DMAC request. 3 4 Memory το Μemory DMAC None Peripheral Burst request / (Source) single request (Select Memory to Memory mode, set DMACxCnConfiguration to "1") When All transfer data is transferred completely or when the DMAC channel is disabled, DMAC is stopped. Transfer size (1)An integral multiple of the burst size Peripheral to Peripheral Peripheral (Destination) Burst request (2)Not an integral multiple of the burst size Source Destination Burst request Burst request Burst request / single request - Note:When much data is transferred in memory to memory, we recommend that a lower priority channel is used. If a lower priority channel is used, a higher priority channel can be started to transfer during a lower priority channel is transferring. If a higher priority channel is used, a lower priority channel can not be started to transfer during a higher priority channel is transferring. 2013/5/31 Page 244 TMPM361F10FG 9.3 Block diagram DMACx channel0,1 AHB CPU Data AHB slave I/F DMA requested (Request No.[15] to [0]) Control logic and register Burst requested DMA request and response I/F DMA requested Channel logic and register AHB master I/F Interrupt request Single requested (Request No.[15] to [0]) INTDMACxERR INTDMACxTC DMAC0CLR[15:0] Figure 9-1 DMAC Block diagram Page 245 2013/5/31 9. 9.4 DMA Controller(DMAC) Product information of TMPM361F10FG 9.4 TMPM361F10FG Product information of TMPM361F10FG 9.4.1 Peripheral function supported with Peripheral to Peripheral Transfer Peripheral functions (Register) supported with Peripheral to Peripheral Transfer are shown below. TMPM361F10FG does not support Peripheral to Peripheral Transfer. 9.4.2 DMA request DMA request against each DMA request no. are shown as bellows. Table 9-3 DMA request factor Corresponding peripheral DMA ch0,ch1 request No. Burst request Single request 0 SIO0/UART0 Transmission / Reception − 1 SIO1/UART1 Transmission / Reception − 2 SIO2/UART2 Transmission / Reception − 3 SIO3/UART3 Transmission / Reception − 4 SIO4/UART4 Transmission / Reception − 5 − − 6 − − 7 − − 8 − − 9 − − 10 − − 11 − − 12 SSP Transmission 13 SSP Reception 14 15 9.4.3 2013/5/31 − SSP Reception − − Normal AD Conversion End − Interrupt request Transfer complete interrupt Error interrupt INTDMACTC INTDMACERR Page 246 TMPM361F10FG 9.4.4 Base address of registers Base Address 0x4000_0000 Page 247 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5 TMPM361F10FG Description of Registers 9.5.1 DMAC register list The function and address for each register are shown bellow. Register Name Address (Base+) DMAC Interrupt Status Register DMAC Interrupt Terminal Count Status Register DMAC Interrupt Terminal Count Clear Register DMACxIntStaus 0x0000 DMACxIntTCStatus 0x0004 DMACxIntTCClear 0x0008 DMAC Interrupt Error Status Register DMACxIntErrorStatus 0x000C DMAC Interrupt Error Clear Register DMACxIntErrClr 0x0010 DMACxRawIntTCStatus 0x0014 DMAC Raw Interrupt Terminal Count Status Register DMAC Raw Error Interrupt Status Register DMACxRawIntErrorStatus 0x0018 DMACxEnbldChns 0x001C DMAC Software Burst Request Register DMACxSoftBReq 0x0020 DMAC Software Single Request Register DMACxSoftSReq 0x0024 - 0x0028 DMAC Enabled Channel Register Reserved Reserved - 0x002C DMACxConfiguration 0x0030 - 0x0034 DMAC Channel0 Source Address Register DMACxC0SrcAddr 0x0100 DMAC Channel0 Destination Address Register DMACxC0DestAddr 0x0104 DMACxC0LLI 0x0108 DMAC Configuration Register Reserved DMAC Channel0 Linked List Item Register DMAC Channel0 Control Register DMACxC0Control 0x010C DMACxC0Configuration 0x0110 DMAC Channel1 Source Address Register DMACxC1SrcAddr 0x0120 DMAC Channel1 Destination Address Register DMACxC1DestAddr 0x0124 DMACxC1LLI 0x0128 DMACxC1Control 0x012C DMACxC1Configuration 0x0130 DMAC Channel0 Configuration Register DMAC Channel1 Linked List Item Register DMAC Channel1 Control Register DMAC Channel 1 Configuration Register Note 1: Access the registers by using word (32bit) reads and word writes. Note 2: Access to the "Reserved" area is prohibited. Note 3: For the registers prepared for every channel, if the channel structure is the same, unit number is expressed as "x" and channel number is expresses as "n". Note 4: When the register which is not assigned with an each channel is read after the register which is assigned with an each channel is written, one machine cycle is inserted between the instructions or read the register which is not assigned with an each channel twice. 2013/5/31 Page 248 TMPM361F10FG 9.5.2 DMACxIntStatus (DMAC Interrupt Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - IntStatus1 IntStatus0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 IntStatus1 R Status of DMAC channel 1 transfer end interrupt. 0 : Interrupt not requested 1 : Interrupt requested Status of the DMAC interrupt generation after passing through the transfer end interrupt enable register and error interrupt enable register. An interrupt is requested when there is a transfer error or when the counter completes counting. 0 IntStatus0 R Status of DMAC channel 0 interrupt generation. 0 : Interrupt not requested 1 : Interrupt requested Status of the DMAC interrupt generation after passing through the transfer end interrupt enable register and error interrupt enable register. An interrupt is requested when there is a transfer error or when the counter completes counting. DMA transfer end DMACIntTCStatus (Masked transfer end interrupt) DMACxCnConfiguration DMA transfer error DMACIntErrorStatus (Masked transfer error interrupt) DMACxCnConfiguration DMACIntStatus DMACRawIntTCStatus (Raw transfer end interrupt) DMACRawIntErrorStatus (Raw transfer error interrupt) Figure 9-2 Interrupt-related block diagram Page 249 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5.3 TMPM361F10FG DMACxIntTCStatus (DMAC Interrupt Terminal Count Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - IntTCStatus1 IntTCStatus0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 IntTCStatus1 R Status of DMAC channel 1 transfer end interrupt. 0 : Interrupt not requested 1 : Interrupt requested The status of post-enable transfer end interrupt generation. 0 IntTCStatus0 R Status of DMAC channel 0 transfer end interrupt. 0 : Interrupt not requested 1 : Interrupt requested The status of post-enable transfer end interrupt generation. 2013/5/31 Page 250 TMPM361F10FG 9.5.4 DMACxIntTCClear (DMAC Interrupt Terminal Count Clear Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - IntTCClear1 IntTCClear0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 IntTCClear1 W Clear DMAC channel 1 transfer end interrupt. 0 : Do nothing 1 : Clear The DMACxIntTCStatus will be cleared when "1" is written. 0 IntTCClear0 W Clear DMAC channel 0 transfer end interrupt. 0 : Do nothing 1 : Clear The DMACxIntTCStatus will be cleared when "1" is written. Page 251 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5.5 TMPM361F10FG DMACxIntErrorStatus (DMAC Interrupt Error Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - IntErrStatus1 IIntErrStatus0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 IntErrStatus1 R Status of DMAC channel 1 error interrupt generation. 0 : Interrupt not requested 1 : Interrupt requested Shows error interrupt status after enabled. 0 IntErrStatus0 R Status of DMAC channel 0 error interrupt generation. 0 : Interrupt not requested 1 : Interrupt requested Shows error interrupt status after enabled. 2013/5/31 Page 252 TMPM361F10FG 9.5.6 DMACxIntErrClr (DMAC Interrupt Error Clear Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - IntErrClr1 IntErrClr0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 IntErrClr1 W Clear DMAC channel 1 transfer end interrupt. 0 : Do nothing 1 : Clear The DMACxIntErrorStatus will be cleared when "1" is written. 0 IntErrClr0 W Clear DMAC channel 0 transfer end interrupt. 0 : Do nothing 1 : Clear The DMACxIntErrorStatus will be cleared when "1" is written. Page 253 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5.7 TMPM361F10FG DMACxRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - RawIntTCS1 RawIntTCS0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 RawIntTCS1 R Status of DMAC channel 1 pre-enable transfer end interrupt generation 0 : Interrupt not requested 1 : Interrupt requested 0 RawIntTCS0 R Status of DMAC channel 0 pre-enable transfer end interrupt generation 0 : Interrupt not requested 1 : Interrupt requested 2013/5/31 Page 254 TMPM361F10FG 9.5.8 DMACxRawIntErrorStatus (DMAC Raw Error Interrupt Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - RawIntErrS1 RawIntErrS0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 RawIntErrS1 R Status of DMAC channel 1 pre-enable error interrupt. 0 : Interrupt not requested 1 : Interrupt requested 0 RawIntErrS0 R Status of DMAC channel 0 pre-enable error interrupt. 0 : Interrupt not requested 1 : Interrupt requested Page 255 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5.9 TMPM361F10FG DMACxEnbldChns (DMAC Enabled Channel Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - EnabledCH1 EnabledCH0 After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 EnabledCH1 R DMA channel 1 enable status. 0 : Disable 1 : Enable After finishing all the total transfer number of times in DMACxCnControl register (the value becomes the zero), the this flag is clearded. 0 EnabledCH0 R DMA channel 0 enable status. 0 : Disable 1 : Enable After finishing all the total transfer number of times in DMACxCnControl register (the value becomes the zero), the this flag is clearded. 2013/5/31 Page 256 TMPM361F10FG 9.5.10 DMACxSoftBReq (DMAC Software Burst Request Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol SoftBReq15 SoftBReq14 SoftBReq13 SoftBReq12 SoftBReq11 SoftBReq10 SoftBReq9 SoftBReq8 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SoftBReq7 SoftBReq6 SoftBReq5 SoftBReq4 SoftBReq3 SoftBReq2 SoftBReq1 SoftBReq0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-16 - - Write as zero. 15 SoftBReq15 R/W DMA burst request by software (Request No. [15]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 14 SoftBReq14 R/W DMA burst request by software (Request No. [14]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 13 SoftBReq13 R/W DMA burst request by software (Request No. [13]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 12 SoftBReq12 R/W DMA burst request by software (Request No. [12]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 11 SoftBReq11 R/W DMA burst request by software (Request No. [11]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 10 SoftBReq10 R/W DMA burst request by software (Request No. [10]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 9 SoftBReq9 R/W DMA burst request by software (Request No. [9]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested Page 257 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers Bit 8 Bit Symbol SoftBReq8 TMPM361F10FG Type R/W Function DMA burst request by software (Request No. [8]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 7 SoftBReq7 R/W DMA burst request by software (Request No. [7]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 6 SoftBReq6 R/W DMA burst request by software (Request No. [6]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 5 SoftBReq5 R/W DMA burst request by software (Request No. [5]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 4 SoftBReq4 R/W DMA burst request by software (Request No. [4]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 3 SoftBReq3 R/W DMA burst request by software (Request No. [3]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 2 SoftBReq2 R/W DMA burst request by software (Request No. [2]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 1 SoftBReq1 R/W DMA burst request by software (Request No. [1]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested 0 SoftBReq0 R/W DMA burst request by software (Request No. [0]) Read : 0 :Stopping DMA burst transfer 1 : running DMA burst transfer Write: 0 : invaild 1 : DMA burst requested Note 1: Do not execute DMA requests by software and hardware at the same time. Note 2: Refer to "9.4.2 DMA request" for DMA request number. Clear "0" to bit corresponded with the DMA request number which has no burst request. 2013/5/31 Page 258 TMPM361F10FG 9.5.11 DMACxSoftSReq (DMAC Software Single Request Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol SoftSReq15 SoftSReq14 SoftSReq13 SoftSReq12 SoftSReq11 SoftSReq10 SoftSReq9 SoftSReq8 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SoftSReq7 SoftSReq6 SoftSReq5 SoftSReq4 SoftSReq3 SoftSReq2 SoftSReq1 SoftSReq0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-16 - - Write as zero. 15 SoftSReq15 R/W DMA single request by software (Request No. [15]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 14 SoftSReq14 R/W DMA single request by software (Request No. [14]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 13 SoftSReq13 R/W DMA single request by software (Request No. [13]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 12 SoftSReq12 R/W DMA single request by software (Request No. [12]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 11 SoftSReq11 R/W DMA single request by software (Request No. [11]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 10 SoftSReq10 R/W DMA single request by software (Request No. [10]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 9 SoftSReq9 R/W DMA single request by software (Request No. [9]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 8 SoftSReq8 R/W DMA single request by software (Request No. [8]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested Page 259 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers Bit 7 Bit Symbol SoftSReq7 TMPM361F10FG Type R/W Function DMA single request by software (Request No. [7]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 6 SoftSReq6 R/W DMA single request by software (Request No. [6]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 5 SoftSReq5 R/W DMA single request by software (Request No. [5]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 4 SoftSReq4 R/W DMA single request by software (Request No. [4]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 3 SoftSReq3 R/W DMA single request by software (Request No. [3]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 2 SoftSReq2 R/W DMA single request by software (Request No. [2]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 1 SoftSReq1 R/W DMA single request by software (Request No. [1]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested 0 SoftSReq0 R/W DMA single request by software (Request No. [0]) Read : 0 :Stopping DMA single transfer 1 : running DMA single transfer Write: 0 : invaild 1 : DMA single requested Note 1: Do not execute DMA requests by software and hardware at the same time. Note 2: Refer to "9.4.2 DMA request" for DMA request number. Clear "0" to bit corresponded with the DMA request number which has no single request. 2013/5/31 Page 260 TMPM361F10FG 9.5.12 DMACxConfiguration (DMAC Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - M E After reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 - - Write as zero. 1 M R/W Write as zero. 0 E R/W DMA circuit control 0 : Stop 1 : Operate When circuit stops, the registers for the DMA circuit cannot be written or read. When operating the DMA, always set ="1". Page 261 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5.13 TMPM361F10FG DMACxCnSrcAddr (DMAC Channelx Source Address Register) 31 30 29 28 0 0 0 0 23 22 21 20 bit symbol After reset Bit 31-0 24 0 0 0 0 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 SrcAddr bit symbol After reset 25 SrcAddr bit symbol After reset 26 SrcAddr bit symbol After reset 27 SrcAddr 0 Bit Symbol SrcAddr[31:0] 0 0 0 Type R/W Function Sets a DMA transfer source address. Make sure to confirm the source address and the bit width before setting. The below are the restrictions in setting of source address bit width. Source address bit width Setting of least significant address DMACxCnControl 000 : Byte (8 bits) no restriction 001 : Half word (16 bits) Setting as multiples of 2, (0x0,0x02,0x4,0x06,0x8,0xA,0xC…) 010 : Word (32 bits) Setting as multiples of 4, (0x0,0x4,0x8,0xC…) Because enabling channel "n" (DMACxCnConfiguration="1") updates the data written in the registers, set DMACxCnSrcAddr before enabling the channels. When the DMA is operating, the value in the DMACxCnSrcAddr register sequentially changes, so the read values are not fixed. And do not update DMACxCnSrcAddr during transfer. To change DMACxCnSrcAddr, be sure to disable the channel "n" (DMACxCnConfiguration="0") before change. 2013/5/31 Page 262 TMPM361F10FG 9.5.14 DMACxCnDestAddr (DMAC Channelx Destination Address Register) 31 30 29 28 0 0 0 0 23 22 21 20 bit symbol After reset Bit 31-0 24 0 0 0 0 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 DestAddr bit symbol After reset 25 DestAddr bit symbol After reset 26 DestAddr bit symbol After reset 27 DestAddr 0 Bit Symbol DestAddr[31:0] 0 0 0 Type R/W Function Sets a DMA transfer destination address. Make sure to confirm the destination address and the bit width before setting. The below are the restrictions in setting of destination address bit width. Destination address bit width Setting of least significant address DMACxCControl 000 : Byte (8 bits) no restriction 001 : Half word (16 bits) Setting as multiples of 2, (0x0,0x02,0x4,0x06,0x8,0xA,0xC…) 010 : Word (32 bits) Setting as multiples of 4, (0x0,0x4,0x8,0xC…) Do not update DMACxCnDestAddr during transfer. To change DMACxCnDestAddr, be sure to disable the channel "n" (DMACxCnConfiguration="0") before change. Page 263 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers 9.5.15 TMPM361F10FG DMACxCnLLI (DMAC Channelx Linked List Item Register) 31 30 29 28 0 0 0 0 23 22 21 20 bit symbol bit symbol 25 24 0 0 0 0 19 18 17 16 LLI After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - Undefined Undefined bit symbol LLI After reset bit symbol LLI After reset Bit 26 LLI After reset 31-2 27 0 Bit Symbol LLI[29:0] 0 0 0 Type R/W 0 0 Function Sets the first address of the next transfer information. Set a value smaller than 0xFFFF_FFF0. When = 0, LLI is the last chain. After DMA transfer finishes, the DMA channel is disabled. 1-0 - R/W Write as zero. Note:For detailed operation, see "9.6 Special Functions". 2013/5/31 Page 264 TMPM361F10FG 9.5.16 DMACxCnControl (DMAC Channeln Control Register) 31 30 29 28 27 26 25 24 bit symbol I - - - DI SI - - After reset 0 Undefined Undefined Undefined 0 0 Undefined Undefined 22 21 20 19 18 17 16 23 bit symbol After reset Dwidth Swidth 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 3 2 1 0 0 0 0 0 bit symbol DBSize After reset 0 0 0 0 SBSize TransferSize 7 6 5 4 bit symbol After reset Bit 31 DBSize TransferSize 0 Bit Symbol I 0 0 0 Type R/W Function Register for enabling a transfer interrupt. 0 : Disable 1 : Enable The transfer end interrupt is generated by setting ="1" and DMACxCnConfiguration="1". When the scatter/gather function is used in the last transfer DMAC setting flow and by setting this bit to enable, to generate the transfer end interrupt is enable only at the last transfer. To generate interrupt during normal transfer, set this bit to "1" and change to enable mode. 30-28 - W Write as zero. 27 DI R/W Increment the transfer destination address 0 : Do not increment 1 : Increment 26 SI R/W Increment the transfer source address 0 : Do not increment 1 : Increment 25-24 - W Write as zero. 23-21 Dwidth[2:0] R/W Transfer destination bit width. 000 : Byte (8 bits) 001 : Half-word (16 bits) 010 : Word (32 bits) other: Reserved Refer to Table 9-4 for the setting value. 20-18 Swidth[2:0] R/W Transfer source bit width 000: Byte (8 bits) 001: Half-word (16 bits) 010 : Word (32 bits) other: Reserved Refer to Table 9-4 for the setting value. 17-15 DBSize[2:0] R/W Transfer destination burst size: (Note 1) 000: 1 beat 100: 32 beats 001: 4 beats 101: 64 beats 010: 8 beats 110: 128 beats 011: 16 beats 111: 256 beats Refer to Table 9-4 for the setting value. Page 265 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers Bit 14-12 Bit Symbol SBSize[2:0] TMPM361F10FG Type R/W Function Transfer source burst size: (Note 1) 000: 1 beat 100: 32 beats 001: 4 beats 101: 64 beats 010: 8 beats 110: 128 beats 011: 16 beats 111: 256 beats Refer to Table 9-4 for the setting value. 11-0 TransferSize [11:0] R/W Set the total number of transfers. Amount of transfer data per a bit width specified by transfer source bit witdth (4 bytes / 2 bytes / 1byte) is set into . Because the burst size shows amount of transfer data at every DMA request internally, amount of transfer data is never changed even if any burst size is set when transfer source bit width and total number of transfers are not changed. The value of is decremented to 0 by the DMA transferring. If this is read, the value which is the number of data not to transfer. The total number of transfers is used as the unit for the transfer source bit width. For examples: When ="000" (8bit), the number of transfers is expressed in the units of byte. When ="001" (16bit), the number of transfers is expressed in the units of half word. When ="010" (32bit), the number of transfers is expressed in the units of word. Note:The burst size to be set with DBsize and SBsize has no connections with the HBURST for the AHB bus. Table 9-4 How to decide the value of ,, , / Set the number so that the following expression is satisfied: Transfer source bit width × Total number of transfers = Transfer destination bit width × N (N : Integer number) (ex.1) Bit width of transfer source:8 bit, bit width of transfer destination:32 bit, total number of transfers:25 times 8 bit × 25 times = 200 bit (25 byte) N = 200 ÷ 32 = 6.25 word Since 6.25 is not an integer number, the above setting is invalid. If the transfer source bit width is smaller than the transfer destination bit width, care must be taken when setting the total number of transfers. (ex.2) Bit width of transfer source :32 bit, bit width of transfer destination:16 bit, total number of transfers: 13 times 32 bit × 13 times = 416 bit (13 word) N = 416 ÷ 16 = 26 half_word Since 26 is an integer number, the above setting is valid. / When "Peripheral to Memory" or "Memory to Peripheral" is performed, peripheral circuits generates DMA request signal to indicate the preparation is ready. This signal triggers to execute data transfers. (In the case of "Memory to Memory", only software start is used.) Set the burst size to define the amount of data transferred from peripherals per DMA request signal. This register is used with FIFO buffer that can be contained multiple data. 2013/5/31 Page 266 TMPM361F10FG 9.5.17 DMACxCnConfiguration (DMAC Channel n Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - Halt Active Lock After reset Undefined Undefined Undefined Undefined Undefined 0 0 0 15 14 13 12 11 10 9 8 bit symbol ITC IE After reset 0 0 0 0 0 Undefined 0 6 5 4 3 2 1 7 bit symbol DestPeripheral After reset Bit FlowCntrl 0 Bit Symbol - 0 DestPeripheral SrcPeripheral Undefined 0 0 Type 0 0 E 0 0 0 Function 31-19 - W Write as zero. 18 Halt R/W Controls accepting a DMA request 0 : Accept a DMA request 1 : Ignore a DMA request 17 Active R Indicates whether data is present in the channel FIFO. 0 : No data exists in the FIFO 1 : Data exists in the FIFO 16 Lock R/W Sets a locked transfer (Non-divided transfer). 0 : Disable locked transfer 1: Enable locked transfer When locked transfer is enabled, as many burst transfers as specified are consecutively executed without releasing the bus. For detailed operation, see "9.6 Special Functions". 15 ITC R/W Transfer end interrupt enable register. 0 : Disable interrupt 1 : Enable interrupt 14 IE R/W Error interrupt enable register 0 :Disable interrupt 1: Enable interrupt 13-11 FlowCntrl[2:0] R/W Sets transfer method Transfer method setting value 000: Memory to Memory (Note) 001: Memory to Peripheral 010: Peripheral to Memory 011 to 111: Reserved 10 - W Write as zero. 9-6 DestPeripheral R/W Sets transfer destination peripheral (Note 2) Refer to "9.4.2 DMA request". [3:0] When a memory is the transfer destination, this setting is ignored. 5 - W Write as zero. 4-1 SrcPeripheral R/W Sets transfer source peripheral (Note 2) [3:0] Refer to "9.4.2 DMA request". When a memory is the transfer source, this setting is ignored. Page 267 2013/5/31 9. 9.5 DMA Controller(DMAC) Description of Registers Bit 0 Bit Symbol E TMPM361F10FG Type R/W Function Channel enable 0 : Disable 1 : Enable This bit can be used to enable/disable the channels. (This bit works as start bit when "Memory to Memory" is selected.) Amount of transfer data specified by DMACxCnControl is completed, the corresponding is cleared to "0" automatically. Disabling channels during transfer loses the data in the FIFO. Initialize all the channels before restart. To pause the transfer, stop the DMA request by using the , and poll the data until the becomes "0" and then disable the channel with the bit. Note 1: When "Memory to Memory" is selected, hardware start for DMA startup is not supported. Write "1" for starting transfer. Note 2: When DMACxENableChns is enabled and the corresponding DMACxCnConfiguration is set to "1", write them after channel enable bit (E:bit0) is clear to "0". Without this, in the case of the slave error is occurred when writing them, the error is recovered by reset. Regarding slave error, when the width and address of transfer have mismatch, this error is occurred. 2013/5/31 Page 268 TMPM361F10FG 9.6 Special Functions 9.6.1 Scatter/gather function When removing a part of image data and transferring it, image data cannot be handled as consecutive data, and the address changes dramatically depending on the special rule. Since DMA can transfer data only by using consecutive addresses, it is necessary to make required settings at locations where addresses changes. Addresses are not continuous. A part of screen image is cut out. Screen data Screen image The scatter/gather function can consecutively operate DMA settings (transfer source address, destination address, number of transfers, and transfer bus width) by re-loading them each time a specified number of DMA executions have completed via a pre-set "Linked List" where the CPU does not need to control the operation. Setting "1" in the DMACxCnLLI register enables/disables the operation. The items that can be set with Linked List are configured with the following 4 words: 1. DMACxCnSrcAddr 2. DMACxCnDestAddr 3. DMACxCnLLI 4. DMACxCnControl They can be used with the interrupt operation. An interrupt depends on the count end interrupt enable bit of the DMACxCnControl register, and can be generated at the end of each LLI. When this bit is used, a condition can be added even during transfer using LLI to perform branch operation, etc. To clear the interrupt, control the appropriate bit of the DMACxIntTCClear register. Page 269 2013/5/31 9. 9.6 DMA Controller(DMAC) Special Functions 9.6.2 TMPM361F10FG Linked list operation To operate the scatter/gather function, a transfer source and source data areas need to be defined by creating a set of Linked Lists first. Each setting is called LLI (LinkedList). Each LLI controls the transfer of one block of data. Each LLI indicates normal DMA setting and controls transfer of successive data. Each time each DMA transfer is complete, the next LLI setting will be loaded to continue the DMA operation (Daisy Chain). An example of the setting is shown below. 1. The first DMA transfer setting should be made directly in the DMA register. 2. The second and subsequent DMA transfer settings should be written in the addresses of the memory set in "next LLI AddressX." 3. To stop up to N'th DMA transfer, set "next LLI AddressX" to 0x0000_0000. Directly specified in the DMA setting registers +0 +4 +8 +C LLI address2 LLI addressN Source Address1 Destination Address1 Source Address2 Destination Address2 Source AddressN Destination AddressN Next LLI Address2 Next LLI Address3 Control register value Control register value Source memory image ࣭࣭࣭ Control register value Destination memory image When transferring data in the area enclosed by the square 0x002000 0x0A000 0x0B000 0x0C000 2013/5/31 0x00000000 Page 270 0x00E000 TMPM361F10FG Setting register Setting parameter +0 DMACxCnSrcAddr :0x0A200 +4 DMACxCnDestAddr :Destination address 1 +8 DMACxCnLLI :0x200000 +C DMACxCnControl :Set the number of burst transfers and the number of transfers, etc. Linked List 0x200000 +4 +8 +C 0x0B200(SrcAddr) Dest Addr2 0x200010 Control register value 0x200010 +4 +8 +C 0x0C200(SrcAddr) Dest Addr3 0x00000000 Control register value Page 271 ←Indicates that a sequence of transfers ends with this LLI. 2013/5/31 9. 9.6 DMA Controller(DMAC) Special Functions 2013/5/31 TMPM361F10FG Page 272 TMPM361F10FG 10. Static Memory Controller TMPM361F10FG contains static memory (NOR type Flash memory and SRAM) controller with asynchronous access. Note 1: Execute the WFI instruction after confirming the external memory access is completed. Note 2: The external memory can not be used as a FIFO becase the dummy read cycle in the reading cycle from an external bus may be occurred. 10.1 Function Overview Outline function is shown in Table 10-1. Table 10-1 Out line function of Static memory Controller Item Supported Memory type and bus connection Asynchronous access memory (NOR Flash memory, SRAM, etc.) Data bus width 16bit data bus width Multiplex bus supported 64MB access area is supported and divide into four CS signal and area. CS0 : 0x6000_0000 to 0x60FF_FFFF (16MB) Memory map CS1 : 0x6100_0000 to 0x61FF_FFFF (16MB) CS2 : 0x6200_0000 to 0x62FF_FFFF (16MB) CS3 : 0x6300_0000 to 0x63FF_FFFF (16MB) Timing adjustment Can be controlled AC timing by registers. Clock (SMCCLK) fsys / 2 External control signals Multiplex bus : AD0 to AD15, A17 to A23, OE, WE, ALE, CS0 to CS3, BLS0, BLS1 Page 273 2013/5/31 10. 10.2 Static Memory Controller Block diagram 10.2 TMPM361F10FG Block diagram The block diagram of SMC is shown as below. Memory Domain AHB Domain APB slave I/F Memory Manager EBI I/F Format SMC I/F Memory I/F PAD I/F NOR Flash SRAM memory I/F Figure 10-1 SMC Block Diagram 2013/5/31 Page 274 TMPM361F10FG 10.3 Description of Registers 10.3.1 SFR List The following lists the SFRs. Base Address = 0x4000_1000 Register name Address (Base+) Reserved SMC Memory Interface Configuration Register - 0x0000 smc_memif_cfg 0x0004 Reserved - 0x0008 Reserved - 0x000C SMC Direct Command Register smc_direct_cmd 0x0010 SMC Set Cycles Register smc_set_cycles 0x0014 smc_set_opmode 0x0018 SMC Set Opmode Register Reserved SMC SRAM Cycles Registers SMC Opmode Registers SMC SRAM Cycles Registers SMC Opmode Registers SMC SRAM Cycles Registers SMC Opmode Registers SMC SRAM Cycles Registers SMC Opmode Registers - 0x0020 smc_sram_cycles0_0 0x0100 smc_opmode0_0 0x0104 smc_sram_cycles0_1 0x0120 smc_opmode0_1 0x0124 smc_sram_cycles0_2 0x0140 smc_opmode0_2 0x0144 smc_sram_cycles0_3 0x0160 smc_opmode0_3 0x0164 - 0x0200 to 0x0204,0x0E00 to 0x0E08,0x0FE0 to 0x0FFC Reserved Base Address = 0x41FF_F100 Register name Address (Base+) SMC Mode Register SMCMDMODE 0x0000 Note 1: Access the registers by using word reads and word writes. Note 2: Do not access at reserved address. Page 275 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.2 TMPM361F10FG SMCMDMODE (Mode Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol - - - - - - - After reset 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7-1 − R/W Write as "0". 0 IFSMCMUXMD R/W SMC memory bus mode setting 1:Multiplex bus mode Note 1: Do not change during SMC operation. Note 2: Set to "1". 2013/5/31 Page 276 0 IFSMC MUXMD 0 TMPM361F10FG 10.3.3 smc_memif_cfg (SMC Memory Interface Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 5 4 3 2 1 0 7 6 bit symbol - - After reset Undefined Undefined Bit Bit Symbol memory_width 0 memory_chips 1 Type 1 0 1 Function 31-6 − R Read as undefined. 5-4 memory_width R Maximum external SMC memory bus width [1:0] 1 memory_type 01 : 16 bits Others : Don't care 3-2 memory_chips R The number of supported memory CS 00 : 1 chip [1:0] 01 : 2 chip 10 : 3 chip 11 : 4 chip 1-0 memory_type [1:0] R Supported memory types : SRAM When is "1", read as "11". Others : Don't care Page 277 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.4 TMPM361F10FG smc_direct_cmd (SMC Direct Command Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol chip_select - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 cmd_type chip_select bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 31-26 − W Write as "0". 25-23 chip_select[2:0] W CS selection 000 : CS0 001 : CS1 010 : CS2 011 : CS3 100 to 111 : Setting prohibition Select objective Chip Select terminal 22-21 cmd_type[1:0] W Update set_opmode register and set_cycles register value 10 : Update registers Others : Setting prohibition 20-0 − W Write as "0". Start Set smc_set_cycle register as timing parameter and set smc_set_opmode as operation mode Select the external ChipSelect and set smc_direct_cmd register then updating End 2013/5/31 Page 278 TMPM361F10FG 10.3.5 smc_set_cycles (SMC Set Cycles Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 19 18 17 23 22 21 20 bit symbol - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Undefined Undefined bit symbol After reset Set_t4 Bit Set_t2 Set_t1 Undefined Bit Symbol Undefined 16 Set_t4 Set_t3 bit symbol After reset Set_t5 Set_t0 Undefined Undefined Type Undefined Undefined Function 31-20 − W Write as "0". 19-17 Set_t5[2:0] W Set value of tTR 000 : Setting prohibition 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 16-14 Set_t4[2:0] W Set value of tPC 000 : Setting prohibition 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock Page access is not supported in multiplex bus mode. tPC is effective only separate bus mode. 13-11 Set_t3[2:0] W Set value of tWP (note) 000 : Setting prohibition 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock In multiplex mode, write pulse width (tWP) increase for one more clock pulse against for value of . 10-8 Set_t2[2:0] W Set value of tCEOE (note) 000 : Setting prohibition 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 7-4 Set_t1[3:0] W Set value of tWC (note) 0000 : Setting prohibition 0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock 3-0 Set_t0[3:0] W Set value of tRC (note) 0000 : Setting prohibition 0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock This register is provided to adjust the access cycle of static memory and should be set to satisfy the A.C. specifications of the memory to be used. Adjust base clock is SMCCLK : fsys/2. To validate SMC set cycles register setting, it is necessary to execute update register command on smc_direct_cmd register. Note:It needs to keep below relation. , Multiplex bus mode :(tWP + SMCCLK × 3 clock) ≤ tWC , Multiplex bus mode :(tCEOE + SMCCLK × 1 clock) ≤ tRC Page 279 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.6 TMPM361F10FG smc_set_opmode (SMC Set Opmode Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - set_adv - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 5 4 3 2 1 0 7 6 bit symbol - - After reset Undefined Undefined Bit Bit Symbol set_rd_bl Undefined Undefined Type Undefined Undefined set_mw Undefined Undefined Function 31-12 − W Write as "0". 11 set_adv W ALE signal 1 : Address latch enable (ALE) used (select when multiplex bus mode is used.) 10-6 − W Write as "0". 5-3 set_rd_bl[2:0] W Setting bits for Burst length of data read 000 : 1 beat 001 : 4 beats Others : Reserved 2 − W Write as "0". 1-0 set_mw[1:0] W Holding register of the memory data bus width set value 01 : 16 bits Others : Reserved Setting bits for data bus width. To validate SMC set opmode register settings, it is necessary to execute update register command on smc_direct_cmd register. Note:Set to "1". 2013/5/31 Page 280 TMPM361F10FG 10.3.7 smc_sram_cycles0_0 (SMC SRAM Cycles Registers 0 ) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 19 18 17 16 23 22 21 20 bit symbol - - - - After reset Undefined Undefined Undefined Undefined 0 0 1 0 15 14 13 12 11 10 9 8 bit symbol - - After reset 1 0 7 6 bit symbol 1 Bit Symbol - t_wp t_ceoe 1 1 0 0 5 4 3 2 t_wc After reset Bit t_tr 1 1 1 1 0 0 0 t_rc 0 0 Type 1 1 Function 31-20 − W Write as "0". 19-17 t_tr[2:0] R Turn around cycle time 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 16-14 − R Read as undefined. 13-11 t_wp[2:0] R WE pulse cycle time 10-8 t_ceoe[2:0] R 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock Delay cycle time to OE assert 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 7-4 t_wc[3:0] R Write cycle time 0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock 3-0 t_rc[3:0] R Read cycle time 0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock Page 281 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.8 TMPM361F10FG smc_sram_cycles0_1 (SMC SRAM Cycles Registers 0 ) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 19 18 17 16 23 22 21 20 bit symbol - - - - After reset Undefined Undefined Undefined Undefined 0 0 1 0 15 14 13 12 11 10 9 8 bit symbol - - After reset 1 0 7 6 bit symbol 1 Bit Symbol t_ceoe 1 0 0 5 4 3 2 1 0 0 Type 1 Function − W Write as "0". 19-17 t_tr[2:0] R Turn around cycle time 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 16-14 − R Read as undefined. 13-11 t_wp[2:0] R WE pulse cycle time 10-8 t_ceoe[2:0] R 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock Delay cycle time to OE assert 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock t_wc[3:0] R Write cycle time 0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock 3-0 t_rc[3:0] R Read cycle time 0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock 2013/5/31 1 1 1 0 0 0 t_rc 31-20 7-4 - t_wp 1 t_wc After reset Bit t_tr Page 282 1 TMPM361F10FG 10.3.9 smc_sram_cycles0_2 (SMC SRAM Cycles Registers 0 ) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 19 18 17 16 23 22 21 20 bit symbol - - - - After reset Undefined Undefined Undefined Undefined 0 0 1 0 15 14 13 12 11 10 9 8 bit symbol - - After reset 1 0 7 6 bit symbol 1 Bit Symbol - t_wp t_ceoe 1 1 0 0 5 4 3 2 t_wc After reset Bit t_tr 1 1 1 1 0 0 0 t_rc 0 0 Type 1 1 Function 31-20 − W Write as "0". 19-17 t_tr[2:0] R Turn around cycle time 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 16-14 − R Read as undefined. 13-11 t_wp[2:0] R WE pulse cycle time 10-8 t_ceoe[2:0] R 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock Delay cycle time to OE assert 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 7-4 t_wc[3:0] R Write cycle time 0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock 3-0 t_rc[3:0] R Read cycle time 0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock Page 283 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.10 TMPM361F10FG smc_sram_cycles0_3 (SMC SRAM Cycles Registers 0 ) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 19 18 17 16 23 22 21 20 bit symbol - - - - After reset Undefined Undefined Undefined Undefined 0 0 1 0 15 14 13 12 11 10 9 8 bit symbol - - After reset 1 0 7 6 bit symbol 1 Bit Symbol t_ceoe 1 0 0 5 4 3 2 1 0 0 Type 1 Function − W Write as "0". 19-17 t_tr[2:0] R Turn around cycle time 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock 16-14 − R Read as undefined. 13-11 t_wp[2:0] R WE pulse cycle time 10-8 t_ceoe[2:0] R 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock Delay cycle time to OE assert 001 to 111 : SMCCLK × 1 clock to SMCCLK × 7 clock t_wc[3:0] R Write cycle time 0011 to 1111 : SMCCLK × 3 clock to SMCCLK × 15 clock 3-0 t_rc[3:0] R Read cycle time 0010 to 1111 : SMCCLK × 2 clock to SMCCLK × 15 clock 2013/5/31 1 1 1 0 0 0 t_rc 31-20 7-4 - t_wp 1 t_wc After reset Bit t_tr Page 284 1 TMPM361F10FG 10.3.11 smc_opmode0_0 (SMC Opmode Registers 0) 31 30 29 28 26 25 24 0 1 1 0 0 0 0 0 23 22 21 - - - 20 19 18 17 16 - - - - - bit symbol 27 address_match After reset bit symbol After reset 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol - - - - adv - - - After reset Undefined Undefined Undefined Undefined 1 Undefined Undefined Undefined 5 4 3 2 1 7 6 bit symbol - - After reset Undefined Undefined Bit Bit Symbol rd_bl 0 0 Type 0 Undefined 0 mw 1 0 Function 31-24 address_match [7:0] R Start address of CS0 area 23-16 − R Read as "0xFF". 15-12 − R Read as undefined. 11 adv R Address latch enable signal Read as "0x60". 0 : Address latch enable signal (ALE) not used 1 : Address latch enable signal (ALE) used 10-6 − R Read as undefined. 5-3 rd_bl[2:0] R Burst length of data read 000 : 1 beat 001 : 4 beats 010 to 111 : Don't care 2 − R Read as undefined. 1-0 mw[1:0] R Data bus width of CS0 01 : 16 bits Others : Don't care Note:Do not access the external memory area except set CS area. Page 285 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.12 TMPM361F10FG smc_opmode0_1 (SMC Opmode Registers 0) 31 30 29 28 26 25 24 0 1 1 0 0 0 0 1 23 22 21 - - - 20 19 18 17 16 - - - - - bit symbol 27 address_match After reset bit symbol After reset 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol - - - - adv - - - After reset Undefined Undefined Undefined Undefined 1 Undefined Undefined Undefined 5 4 3 2 1 7 6 bit symbol - - After reset Undefined Undefined Bit Bit Symbol rd_bl 0 0 Type 0 Function 31-24 address_match [7:0] R Start address of CS1 area 23-16 − R Read as "0xFF". 15-12 − R Read as undefined. 11 adv R Address latch enable signal Read as "0x61". 0 : Address latch enable signal (ALE) not used 1 : Address latch enable signal (ALE) used 10-6 − R Read as undefined. 5-3 rd_bl[2:0] R Burst length of data read 000 : 1 beat 001 : 4 beats 010 to 111 : Don't care 2 − R Read as undefined. 1-0 mw[1:0] R Data bus width of CS1 01 : 16 bits Others : Don't care Note:Do not access the external memory area except set CS area. 2013/5/31 Page 286 Undefined 0 mw 1 0 TMPM361F10FG 10.3.13 smc_opmode0_2 (SMC Opmode Registers 0) 31 30 29 28 26 25 24 0 1 1 0 0 0 1 0 23 22 21 - - - 20 19 18 17 16 - - - - - bit symbol 27 address_match After reset bit symbol After reset 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol - - - - adv - - - After reset Undefined Undefined Undefined Undefined 1 Undefined Undefined Undefined 5 4 3 2 1 7 6 bit symbol - - After reset Undefined Undefined Bit Bit Symbol rd_bl 0 0 Type 0 Undefined 0 mw 1 0 Function 31-24 address_match [7:0] R Start address of CS2 area 23-16 − R Read as "0xFF". 15-12 − R Read as undefined. 11 adv R Address latch enable signal Read as "0x62". 0 : Address latch enable signal (ALE) not used 1 : Address latch enable signal (ALE) used 10-6 − R Read as undefined. 5-3 rd_bl[2:0] R Burst length of data read 000 : 1 beat 001 : 4 beats 010 to 111 : Don't care 2 − R Read as undefined. 1-0 mw[1:0] R Data bus width of CS2 01 : 16 bits Others : Don't care Note:Do not access the external memory area except set CS area. Page 287 2013/5/31 10. 10.3 Static Memory Controller Description of Registers 10.3.14 TMPM361F10FG smc_opmode0_3 (SMC Opmode Registers 0) 31 30 29 28 26 25 24 0 1 1 0 0 0 1 1 23 22 21 - - - 20 19 18 17 16 - - - - - bit symbol 27 address_match After reset bit symbol After reset 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 bit symbol - - - - adv - - - After reset Undefined Undefined Undefined Undefined 1 Undefined Undefined Undefined 5 4 3 2 1 7 6 bit symbol - - After reset Undefined Undefined Bit Bit Symbol rd_bl 0 0 Type 0 Function 31-24 address_match [7:0] R Start address of CS3 area 23-16 − R Read as "0xFF". 15-12 − R Read as undefined. 11 adv R Address latch enable signal Read as "0x63". 0 : Address latch enable signal (ALE) not used 1 : Address latch enable signal (ALE) used 10-6 − R Read as undefined. 5-3 rd_bl[2:0] R Burst length of data read 000 : 1 beat 001 : 4 beats 010 to 111 : Don't care 2 − R Read as undefined. 1-0 mw[1:0] R Data bus width of CS3 01 : 16 bits Others : Don't care Note:Do not access the external memory area except set CS area. 2013/5/31 Page 288 Undefined 0 mw 1 0 TMPM361F10FG 10.4 External Bus Cycle 10.4.1 Multiplex mode 10.4.1.1 tRC / tCEOE setting example tRC =4, tCEOE =1 (smc_set_cycles = 0x0002B1C4) smc_set_cycles Setting value tTR tPC tWP tCEOE tWC tRC 31-20 19-17 16-14 13-11 10-8 7-4 3-0 - Set_t5[2:0] Set_t4[2:0] Set_t3[2:0] Set_t2[2:0] Set_t1[3:0] Set_t0[3:0] 0 001(1) 010(2) 110(6) 001(1) 1100(C) 0100(4) SMCCLK (Internal CLK) tRC CS0 OE tCEOE WE ALE Addr[23:17] A[23:1] D[15:0] XX Addr[16:1] Data[15:0] XX Figure 10-2 Asynchronous Read Page 289 2013/5/31 10. 10.4 Static Memory Controller External Bus Cycle 10.4.1.2 TMPM361F10FG tWC / tWP setting example tWC =5, tWP =1 (smc_set_cycles = 0x00028B5C) smc_set_cycles Setting value tTR tPC tWP tCEOE tWC tRC 31-20 19-17 16-14 13-11 10-8 7-4 3-0 - Set_t5[2:0] Set_t4[2:0] Set_t3[2:0] Set_t2[2:0] Set_t1[3:0] Set_t0[3:0] 0 001(1) 010(2) 001(1) 011(3) 0101(5) 1100(C) SMCCLK (Internal CLK) tWC CS0 OE tWP +1 WE ALE Addr[23:17] A[23:1] D[15:0] XX Addr[16:1] Data[15:0] BLS0 BLS1 Figure 10-3 Asynchronous Write 2013/5/31 Page 290 XX TMPM361F10FG 10.4.1.3 tTR setting example tTR =1 (smc_set_cycles = 0x00029144) smc_set_cycles Setting value SMCCLK (Internal CLK) tTR tPC tWP tCEOE tWC tRC 31-20 19-17 16-14 13-11 10-8 7-4 3-0 - Set_t5[2:0] Set_t4[2:0] Set_t3[2:0] Set_t2[2:0] Set_t1[3:0] Set_t0[3:0] 0 001(1) 010(2) 010(2) 001(1) 0100(4) 0100(4) tRC tWC CS0 OE tTR tCEOE tWP +1 WE ALE Addr1[23:17] A[23:1] D[15:0] Addr1[16:1] Addr2[23:17] Data1[15:0] XX Addr2[16:1] Data2[15:0] Figure 10-4 Asynchronous Read and Asynchronous Write Page 291 2013/5/31 10. 10.5 Static Memory Controller Connection example for external memory 10.5 TMPM361F10FG Connection example for external memory Below figures show connection example for external 16bit NOR-Flash and 16bit SRAM. TMPM361F10FG 16bit NOR-Flash CS0 CE WE WE OE OE AD[15:0] D[15:0] D ALE Q A[16:1] LE A17 A17 ࣭ ࣭ ࣭ ࣭ ࣭ ࣭ ࣭ ࣭ A23 A23 16bit SRAM WE OE CE D[15:0] A[16:1] A17 CS1 ࣭ ࣭ ࣭ A23 BLS0 LB BLS1 UB Figure 10-5 Connection example for external 16bit SRAM and NOR-Flash (Multiplex mode) 2013/5/31 Page 292 TMPM361F10FG 11. 16-bit Timer / Event Counters (TMRB) 11.1 Outline TMRB operate in the following four operation modes: ・ ・ ・ ・ 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation mode (PPG) Timer synchronous mode The use of the capture function allows TMRB to perform the following three measurements. ・ ・ ・ ・ One shot pulse output by an external trigger Frequency measurement Pulse width measurement Time difference measurement In the following explanation of this section, "x" indicates a channel number. Page 293 2013/5/31 11. 11.2 16-bit Timer / Event Counters (TMRB) Differences in the Specifications 11.2 TMPM361F10FG Differences in the Specifications TMPM361F10FG contains 16-channel of TMRB. Each channel functions independently and the channels operate in the same way except for the differences in their specification as shown in Table 11-1. Some of the channels can put the capture trigger and the synchronous start trigger on other channels. 1. The flip-flop output of TMRB 0, 4, 8 and C can be used as the capture trigger of other channels. ・ TB0OUT → available for TMRB5 through TMRB7 ・ TB4OUT → available for TMRB1 through TMRB3 ・ TB8OUT → available for TMRBD through TMRBF ・ TBCOUT → available for TMRB9 through TMRBB 2. The start trigger of the timer synchronous mode (with TBxRUN) ・ TMRB0 → can start TMRB0 through TMRB3 synchronously ・ TMRB4 → can start TMRB4 through TMRB7 synchronously ・ TMRB8 → can start TMRB8 through TMRBB synchronously ・ TMRBC → can start TMRBC through TMRBF synchronously Note: 2013/5/31 TMRB8 to TMRBF do not have timer output. Page 294 TMPM361F10FG Table 11-1 Differences in the Specifications of TMRB Modules External pins Specification External clock / Channel TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 TMRB5 TMRB6 TMRB7 TMRB8 TMRB9 capture trigger input pins Trigger function between timers Timer flip-flop output pin Interrupt trigger Synchronous start trigger channel Capture interrupt interrupt − INTTB0 Capture TMRB Signal Signal − TB0OUT − TMRB0 TB1OUT TB4OUT TMRB0 TB2OUT TB4OUT TMRB0 TB3OUT TB4OUT TMRB0 − INTTB3 TB4OUT − TMRB4 − INTTB4 TB0OUT TMRB4 TB0OUT TMRB4 TB7OUT TB0OUT TMRB4 − − TMRB8 − − TMRB8 − TMRB8 − INTTBA − TMRB8 − INTTBB TB1IN0 TB1IN1 TB2IN0 TB2IN1 − (Connect to SCLK3) − TB5IN0 TB5OUT TB5IN1 (Connect to SIO0 to SIO3) TB6IN0 TB6OUT TB6IN1 (Connect to SIO4) TB7IN0 TB7IN1 − TB9IN0 TB9IN1 − INTCAP10 INTCAP11 INTCAP20 INTCAP21 INTCAP50 INTCAP51 INTCAP60 INTCAP61 INTCAP70 INTCAP71 − INTCAP90 INTCAP91 INTTB1 INTTB2 INTTB5 INTTB6 INTTB7 INTTB8 INTTB9 TMRBA − TMRBB − TMRBC − − − TMRBC − INTTBC TMRBD − − − TMRBC − INTTBD TMRBE − − − TMRBC − INTTBE TMRBF − − − TMRBC − INTTBF (Connect to CEC) − (Connect to RMC) Page 295 2013/5/31 Run/ clear 2013/5/31 4 Page 296 TBxMOD φT16 Match detect TBxCR Register buffer1 Timer register1 TBxRG1 Comparator (CP1) Match detect Interrupt mask register TBxIM Register 1 interrupt mask Register 0 interrupt mask Overflow interrupt mask Figure 11-1 TMRBx Block Diagram (x= 0 to 2, 4 to F) Internal data bus 16-bit up-counter (UC) Timer flip-flop control TBxFF0 Timer flip-flop Status register TBxST Register 1 interrupt output Register 0 interrupt output Overflow interrupt output Register buffer0 Timer register0 TBxRG0 Comparator (CP0) Run/clear Capture register1 TBxCP1 TBxMOD Up-counter Capture register TBxUC TMRBx interrupt INTTBx Timer flip-flop output TBxOUT Capture Interrupt INTCAPx1 Capture Interrupt INTCAPx0 Configuration Synchronous Synchronous start trigger start trigger input output TBxCR TBxCR φT1 φT4 φT16 Capture register0 TBxCP0 Count clock TBxMOD TBxMOD Capture control φT4 8 16 32 Prescaler / Up-counter control TBxRUN φT1 2 11.3 TBxOUT TBxIN0 TBxIN1 Prescaler clock: φT0 11.3 Internal data bus 11. 16-bit Timer / Event Counters (TMRB) TMPM361F10FG Configuration Each channel consists of a 16-bit up-counter, two 16-bit timer registers (double-buffered), two 16-bit capture registers, two comparators, a capture input control, a timer flip-flop and its associated control circuit.Timer operation modes and the timer flip-flop are controlled by a register. TB4OUT Prescaler clock: φT0 Run/ clear 4 Page 297 TB3MOD φT16 TB3CR Register buffer1 Timer register1 TB3RG1 Comparator (CP1) Internal data bus 16-bit up-counter (UC) Match detect Interrupt mask register TB3IM Register 1 interrupt mask Register 0 interrupt mask Overflow interrupt mask Register buffer0 Timer register0 TB3RG0 Comparator (CP0) Run/clear Counter clock Timer flip-flop counter TB3FF0 Timer flip-flop Status regiaster TB3ST Register 1 interrupt output Register 0 interrupt output Overflow interrupt output Synchronous Synchronous start trigger star trigger input output TB3CR TB3CR φT1 φT4 φT16 SCLK3 Capture register 1 TB3CP1 TB3MOD Up-counter Capture register TB3UC Match detect Capture register 0 TB3CP0 TB3MOD TB3MOD Capture control φT4 8 16 32 Prescaler / Up-counter control TB3RUN φT1 2 Internal data bus TMRB3 interrupt INTTB3 Timer flip-flop output TB3OUT TMPM361F10FG Figure 11-2 TMRBx Block Diagram (x= 3) 2013/5/31 11. 11.4 16-bit Timer / Event Counters (TMRB) Registers 11.4 TMPM361F10FG Registers 11.4.1 Register list according to channel The following table shows the register names and addresses of each channel. Channel x Base Address Channel 0 0x400D_0000 Channel 1 0x400D_0100 Channel 2 0x400D_0200 Channel 3 0x400D_0300 Channel 4 0x400D_0400 Channel 5 0x400D_0500 Channel 6 0x400D_0600 Channel 7 0x400D_0700 Channel 8 0x400D_0800 Channel 9 0x400D_0900 Channel A 0x400D_0A00 Channel B 0x400D_0B00 Channel C 0x400D_0C00 Channel D 0x400D_0D00 Channel E 0x400D_0E00 Channel F 0x400D_0F00 Register name (x=0 to F) Enable register RUN register Control register 0x0000 TBxRUN 0x0004 TBxCR 0x0008 Mode register TBxMOD 0x000C Flip-flop control register TBxFFCR 0x0010 Status register TBxST 0x0014 Interrupt mask register TBxIM 0x0018 Up counter capture register 2013/5/31 Address (Base+) TBxEN TBxUC 0x001C Timer register 0 TBxRG0 0x0020 Timer register 1 TBxRG1 0x0024 Capture register 0 TBxCP0 0x0028 Capture register 1 TBxCP1 0x002C Page 298 TMPM361F10FG 11.4.2 TBxEN (Enable register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBEN - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 TBEN R/W TMRBx operation 0: Disable 1: Enable Specifies the TMRB operation. When the operation is disabled, no clock is supplied to the other registers in the TMRB module. This can reduce power consumption. (This disables reading from and writing to the other registers except TBxEN register.) To use the TMRB, enable the TMRB operation (set to "1") before programming each register in the TMRB module. If the TMRB operation is executed and then disabled, the settings will be maintained in each register. 6-0 − R Read as "0". Page 299 2013/5/31 11. 11.4 16-bit Timer / Event Counters (TMRB) Registers TMPM361F10FG 11.4.3 TBxRUN (RUN register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - TBPRUN - TBRUN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as "0". 2 TBPRUN R/W Prescaler operation 0: Stop & clear 1: Count 1 − R Read as "0". 0 TBRUN R/W Count operation 0: Stop & clear 1: Count Note:When the counter is stopped (="0") and TBxUC is read, the value which was captured when the counter was operated is read. 2013/5/31 Page 300 TMPM361F10FG 11.4.4 TBxCR (Control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TBWBF - TBSYNC - I2TB - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0" 7 TBWBF R/W Double buffer 0: Disable 1: Enable 6 − R/W Write as "0". 5 TBSYNC R/W Synchronous mode switching 0: individual (unit of channel) 1: synchronous 4 − R Read as "0". 3 I2TB R/W Operation at IDLE mode 0: Stop 1:Operation 2 − R Read as "0". 1-0 − R/W Write as "0". Note:Do not modify TBxCR during operating TMRB. Page 301 2013/5/31 11. 11.4 16-bit Timer / Event Counters (TMRB) Registers TMPM361F10FG 11.4.5 TBxMOD (Mode register) x=0 to 2, 4 to F bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - TBCP After reset 0 0 1 Bit Bit Symbol TBCPM 0 Type TBCLE 0 0 TBCLK 0 0 Function 31-7 − R Read as "0". 6 − R/W Write as "0". 5 TBCP Capture control by software 0: Capture by software W 1: Don’t care When "0" is written, the capture register 0 (TBxCP0) takes count value. Read as "1". 4-3 TBCPM[1:0] R/W Capture timing 00: Disable 01: TBxIN0↑ TBxIN1↑ Takes count values into capture register 0 (TBxCP0) upon rising of TBxIN0 pin input. Takes count values into capture register 1 (TBxCP1) upon rising of TBxIN1 pin input. 10: TBxIN0↑ TBxIN0↓ Takes count values into capture register 0 (TBxCP0) upon rising of TBxIN0 pin input. Takes count values into capture register 1 (TBxCP1) upon falling of TBxIN0 pin input. 11: TBxOUT↑ TBxOUT↓ Takes count values into capture register 0 (TBxCP0) upon rising of 16-bit timer match output (TBxOUT) and into capture register 1 (TBxCP1) upon falling of TBxOUT. (TMRB1 to 3: TB4OUT , TMRB5 to 7: TB0OUT , TMRB9 to B: TBCOUT , TMRBD to F: TB8OUT) 2 TBCLE R/W Up-counter control 0: Disables clearing of the up-counter. 1: Enables clearing of the up-counter. Clears and controls the up-counter. When "0" is written, it disables clearing of the up-counter. When "1" is written, it clears up counter when there is a match with Timer Regsiter1 (TBxRG1). 1-0 TBCLK[1:0] R/W Selects the TMRBx source clock. 00: TBxIN0 pin input 01: φT1 10: φT4 11: φT16 Note:TMRB0, 3, 4, 8 and A does not have TBxIN0 input and TBxIN1 input. 2013/5/31 Page 302 TMPM361F10FG x=3 bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - TBCLE After reset 0 0 1 0 0 0 Bit Bit Symbol Type TBCLK 0 0 Function 31-7 − R Read as "0". 6 − R/W Write as "0". 5 − W Write as "1". 4-3 − R/W Write as "00". 2 TBCLE R/W Up-counter control 0: Disables clearing of the up-counter. 1: Enables clearing of the up-counter. Clears and controls the up-counter. When "0" is written, it disables clearing of the up-counter. When "1" is written, it clears up counter when there is a match with Timer Regsiter1 (TBxRG1). 1-0 TBCLK[1:0] R/W Selects the TMRBx source clock. 00: SCLK3 pin input 01: φT1 10: φT4 11: φT16 Page 303 2013/5/31 11. 11.4 16-bit Timer / Event Counters (TMRB) Registers TMPM361F10FG 11.4.6 TBxFFCR (Flip-flop control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 1 7 6 5 4 3 2 bit symbol - - TBC1T1 TBC0T1 TBE1T1 TBE0T1 After reset 1 1 0 0 0 0 Bit Bit Symbol Type 0 TBFF0C 1 1 Function 31-8 − R Read as "0". 7-6 − R Read as "1". 5 TBC1T1 R/W TBxFF0 reverse trigger when the up-counter value is taken into the TBxCP1. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when the up-counter value is taken into the Capture register 1 (TBxCP1). 4 TBC0T1 R/W TBxFF0 reverse trigger when the up-counter value is taken into the TBxCP0. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when the up-counter value is taken into the Capture register 0 (TBxCP0). 3 TBE1T1 R/W TBxFF0 reverse trigger when the up-counter value is matched with TBxRG1. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when the up-counter value is matched with the Timer register 1 (TBxRG1). 2 TBE0T1 R/W TBxFF0 reverse trigger when the up-counter value is matched with TBxRG0. 0: Disable trigger 1: Enable trigger By setting "1", the timer-flip-flop reverses when an up-counter value is matched with the Timer register 0 (TBxRG0). 1-0 TBFF0C[1:0] R/W TBxFF0 control 00: Invert Reverses the value of TBxFF0 (reverse by using software). 01: Set Sets TBxFF0 to "1". 10: Clear Clears TBxFF0 to "0". 11: Don't care * This is always read as "11". Note:Do not modify TBxFFCR during operating TMRB. 2013/5/31 Page 304 TMPM361F10FG 11.4.7 TBxST (Status register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - INTTBOF INTTB1 INTTB0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as "0". 2 INTTBOF R Overflow flag 0:No overflow occurs 1:Overflow occurs When an up-counter is overflow, "1" is set. 1 INTTB1 R Match flag (TBxRG1) 0:No detection of a mach 1:Detects a match with TBxRG1 When a match with the timer register 1 (TBxRG1) is detected, "1" is set. 0 INTTB0 R Match flag (TBxRG0) 0:No match is detected 1:Detects a match with TBxRG0 When a match with the timer register 0 (TBxRG0) is detected, "1" is set. Note 1: The factors only which is not masked by TBxIM output interrupt request to the CPU. Even if the mask setting is done, the flag is set. Note 2: The flag is cleared by reading the TBxST register.To clear the flag, TBxST register should be read. Page 305 2013/5/31 11. 11.4 16-bit Timer / Event Counters (TMRB) Registers TMPM361F10FG 11.4.8 TBxIM (Interrupt mask register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - TBIMOF TBIM1 TBIM0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as "0". 2 TBIMOF R/W Overflow interrupt mask 0:Disable 1:Enable Sets the up-counter overflow interrupt to disable or enable. 1 TBIM1 R/W Match interrupt mask (TBxRG1) 0:Disable 1:Enable Sets the match interrupt mask with the Timer register 1 (TBxRG1) to enable or disable. 0 TBIM0 R/W Match interrupt mask (TBxRG0) 0:Disable 1:Enable Sets the match interrupt mask with the Timer register 0 (TBxRG0) to enable or disable. Note:Even if TBxIM setting is done, TBxST is set. 2013/5/31 Page 306 TMPM361F10FG 11.4.9 TBxUC (Up counter capture register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After reset TBUC bit symbol After reset Bit TBUC 0 Bit Symbol 0 0 0 Type Function 31-16 − R Read as "0". 15-0 TBUC[15:0] R Captures a value by reading up-counter out. If TBxUC is read, current up-counter value can be captured. Note:When the counter is operated and TBxUC is read, the value of the up counter is captured and read. Page 307 2013/5/31 11. 11.4 16-bit Timer / Event Counters (TMRB) Registers TMPM361F10FG 11.4.10 TBxRG0 (Timer register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After reset TBRG0 bit symbol After reset Bit TBRG0 0 Bit Symbol 0 0 0 Type Function 31-16 − R Read as "0". 15-0 TBRG0[15:0] R/W Sets a value comparing to the up-counter. 11.4.11 bit symbol After reset TBxRG1 (Timer register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset TBRG1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 bit symbol After reset Bit TBRG1 Bit Symbol Type Function 31-16 − R Read as "0". 15-0 TBRG1[15:0] R/W Sets a value comparing to the up-counter. 2013/5/31 Page 308 TMPM361F10FG 11.4.12 TBxCP0 (Capture register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined 26 25 24 bit symbol After reset TBCP0 bit symbol After reset Bit TBCP0 Undefined Bit Symbol Undefined Undefined Undefined Type Function 31-16 − R Read as "0". 15-0 TBCP0[15:0] R A value captured from the up-counter is read. 11.4.13 TBxCP1 (Capture register 1) 31 30 29 28 27 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset TBCP1 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined bit symbol After reset Bit TBCP1 Bit Symbol Type Function 31-16 − R Read as "0". 15-0 TBCP1[15:0] R A value captured from the up-counter is read. Page 309 2013/5/31 11. 11.5 16-bit Timer / Event Counters (TMRB) Description of Operations for Each Circuit 11.5 TMPM361F10FG Description of Operations for Each Circuit The channels operate in the same way, except for the differences in their specifications as shown in Table 11-1. 11.5.1 Prescaler There is a 4-bit prescaler to generate the source clock for up-counter UC. The prescaler input clock φT0 is fs, fperiph/1, fperiph/2, fperiph/4, fperiph/8, fperiph/16 or fperiph/32 selected by CGSYSCR in the CG. The peripheral clock, fperiph, is either fgear, a clock selected by CGSYSCR in the CG, or fc, which is a clock before it is divided by the clock gear. The operation or the stoppage of a prescaler is set with TBxRUN where writing "1" starts counting and writing "0" clears and stops counting. Below tables show prescaler output clock resolutions. Table 11-2 Prescaler Output Clock Resolutions (fc = 64MHz, fs = 32.768kHz) Select φT0 CGSYSCR Select peripheral clock CGSYSCR Select gear clock CGSYSCR 000 (fc) 100 (fc/2) 0 0 (fgear) 101 (fc/4) 110 (fc/8) 2013/5/31 Select prescaler clock Prescaler output clock function CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.0312 μs) fc/23 (0.125 μs) fc/25 (0.5 μs) 001 (fperiph/2) fc/2 (0.0625 μs) fc/2 (0.25 μs) fc/26 (1.0 μs) 010 (fperiph/4) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 011 (fperiph/8) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 100 (fperiph/16) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 000 (fperiph/1) fc/2 (0.0625 μs) fc/2 (0.25 μs) fc/26 (1.0 μs) 001 (fperiph/2) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 010 (fperiph/4) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 100 (fperiph/16) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 101 (fperiph/32) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 000 (fperiph/1) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/27 (2.0 μs) 001 (fperiph/2) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 010 (fperiph/4) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 011 (fperiph/8) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) 100 (fperiph/16) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 101 (fperiph/32) fc/2 (4.0 μs) 000 (fperiph/1) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 001 (fperiph/2) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 010 (fperiph/4) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) 011 (fperiph/8) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 100 (fperiph/16) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0 μs) 101 (fperiph/32) fc/2 (8.0 μs) fc/2 fc/213 (128.8 μs) Page 310 2 5 2 5 3 6 8 6 9 4 7 4 7 5 8 fc/2 10 (16.0 μs) 8 11 (32.0 μs) fc/212 (64.0 μs) TMPM361F10FG Table 11-2 Prescaler Output Clock Resolutions (fc = 64MHz, fs = 32.768kHz) Select φT0 CGSYSCR Select peripheral clock CGSYSCR Select gear clock CGSYSCR 000 (fc) 100 (fc/2) 0 1 (fc) 101 (fc/4) 110 (fc/8) 1 * * Select prescaler clock Prescaler output clock function CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.0312 μs) fc/23 (0.125 μs) fc/25 (0.5 μs) 001 (fperiph/2) fc/2 (0.0625 μs) fc/2 (0.25 μs) fc/26 (1.0 μs) 010 (fperiph/4) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 011 (fperiph/8) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 100 (fperiph/16) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 000 (fperiph/1) − fc/23 (0.125 μs) fc/25 (0.5 μs) 001 (fperiph/2) fc/2 (0.0625 μs) fc/2 (0.25 μs) fc/26 (1.0 μs) 010 (fperiph/4) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 011 (fperiph/8) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/28 (4.0 μs) 100 (fperiph/16) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 000 (fperiph/1) − fc/2 (0.125 μs) fc/25 (0.5 μs) 001 (fperiph/2) − fc/24 (0.25 μs) fc/26 (1.0 μs) 010 (fperiph/4) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 011 (fperiph/8) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/28 (4.0 μs) 100 (fperiph/16) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 000 (fperiph/1) − − fc/25 (0.5 μs) 001 (fperiph/2) − fc/24 (0.25 μs) fc/26 (1.0 μs) 010 (fperiph/4) − fc/2 (0.5 μs) fc/27 (2.0 μs) 011 (fperiph/8) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 100 (fperiph/16) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 101 (fperiph/32) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) * fs/2 (61μs) fs/23 (244 μs) fc/25 (977 μs) 2 5 2 4 4 6 4 7 4 6 3 6 5 8 Note 1: The prescaler output clock φTn must be selected so that φTn < fsys is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while the timer is operating. Note 3: "." denotes a setting prohibited. "*" denotes a don’t care. Page 311 2013/5/31 11. 11.5 16-bit Timer / Event Counters (TMRB) Description of Operations for Each Circuit TMPM361F10FG Table 11-3 Prescaler Output Clock Resolutions (fc = 48MHz, fs = 32.768kHz) Select φT0 CGSYSCR Select peripheral clock CGSYSCR Select gear clock CGSYSCR 000 (fc) 100 (fc/2) 0 0 (fgear) 101 (fc/4) 110 (fc/8) 2013/5/31 Select prescaler clock Prescaler output clock function CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.04 μs) fc/23 (0.17 μs) fc/25 (0.66 μs) 001 (fperiph/2) fc/2 (0.08 μs) fc/2 (0.33 μs) fc/26 (1.33 μs) 010 (fperiph/4) fc/23 (0.17 μs) fc/25 (0.66 μs) fc/27 (2.67 μs) 011 (fperiph/8) fc/24 (0.33 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 100 (fperiph/16) fc/2 (0.66 μs) fc/2 (2.67 μs) fc/29 (10.67 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.33 μs) 000 (fperiph/1) fc/22 (0.08 μs) fc/24 (0.33 μs) fc/26 (1.33 μs) 001 (fperiph/2) fc/2 (0.17 μs) fc/2 (0.66 μs) fc/27 (2.67 μs) 010 (fperiph/4) fc/24 (0.33 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 011 (fperiph/8) fc/2 (0.66 μs) fc/2 (2.67 μs) fc/29 (10.67 μs) 100 (fperiph/16) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.33 μs) 101 (fperiph/32) fc/27 (2.67 μs) fc/29 (10.67 μs) fc/211 (42.67 μs) 000 (fperiph/1) fc/2 (0.17 μs) fc/2 (0.66 μs) fc/27 (2.67 μs) 001 (fperiph/2) fc/24 (0.33 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 010 (fperiph/4) fc/25 (0.66 μs) fc/27 (2.67 μs) fc/29 (10.67 μs) 011 (fperiph/8) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/210 (21.33 μs) 100 (fperiph/16) fc/27 (2.67 μs) fc/29 (10.67 μs) fc/211 (42.67 μs) 101 (fperiph/32) fc/28 (5.33 μs) fc/210 (21.33 μs) fc/212 (85.33 μs) 000 (fperiph/1) fc/2 (0.33 μs) fc/2 (1.33 μs) fc/28 (5.33 μs) 001 (fperiph/2) fc/25 (0.66 μs) fc/27 (2.67 μs) fc/29 (10.67 μs) 010 (fperiph/4) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/210 (21.33 μs) 011 (fperiph/8) fc/27 (2.67 μs) fc/29 (10.67 μs) fc/211 (42.67 μs) 100 (fperiph/16) fc/28 (5.33 μs) fc/210 (21.33 μs) fc/212 (85.33 μs) 101 (fperiph/32) fc/2 (10.67 μs) fc/2 fc/213 (170.67 μs) Page 312 2 5 3 5 3 6 4 6 9 4 7 5 7 5 8 6 8 11 (42.67 μs) TMPM361F10FG Table 11-3 Prescaler Output Clock Resolutions (fc = 48MHz, fs = 32.768kHz) Select φT0 CGSYSCR Select peripheral clock CGSYSCR Select gear clock CGSYSCR 000 (fc) 100 (fc/2) 0 1 (fc) 101 (fc/4) 110 (fc/8) 1 * * Select prescaler clock Prescaler output clock function CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.04 μs) fc/23 (0.17 μs) fc/25 (0.66 μs) 001 (fperiph/2) fc/2 (0.08 μs) fc/2 (0.33 μs) fc/26 (1.33 μs) 010 (fperiph/4) fc/23 (0.17 μs) fc/25 (0.66 μs) fc/27 (2.67 μs) 011 (fperiph/8) fc/24 (0.33 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 100 (fperiph/16) fc/2 (0.66 μs) fc/2 (2.67 μs) fc/29 (10.67 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.33 μs) 000 (fperiph/1) − fc/23 (0.17 μs) fc/25 (0.66 μs) 001 (fperiph/2) fc/2 (0.08 μs) fc/2 (0.33 μs) fc/26 (1.33 μs) 010 (fperiph/4) fc/23 (0.17 μs) fc/25 (0.66 μs) fc/27 (2.67 μs) 011 (fperiph/8) fc/2 (0.33 μs) fc/2 (1.33 μs) fc/28 (5.33 μs) 100 (fperiph/16) fc/25 (0.66 μs) fc/27 (2.67 μs) fc/29 (10.67 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.33 μs) 000 (fperiph/1) − fc/2 (0.17 μs) fc/25 (0.66 μs) 001 (fperiph/2) − fc/24 (0.33 μs) fc/26 (1.33 μs) 010 (fperiph/4) fc/23 (0.17 μs) fc/25 (0.66 μs) fc/27 (2.67 μs) 011 (fperiph/8) fc/2 (0.33 μs) fc/2 (1.33 μs) fc/28 (5.33 μs) 100 (fperiph/16) fc/25 (0.66 μs) fc/27 (2.67 μs) fc/29 (10.67 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.33 μs) 000 (fperiph/1) − − fc/25 (0.66 μs) 001 (fperiph/2) − fc/24 (0.33 μs) fc/26 (1.33 μs) 010 (fperiph/4) − fc/2 (0.66 μs) fc/27 (2.67 μs) 011 (fperiph/8) fc/24 (0.33 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 100 (fperiph/16) fc/25 (0.66 μs) fc/27 (2.67 μs) fc/29 (10.67 μs) 101 (fperiph/32) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/210 (21.33 μs) * fs/2 (61μs) fs/23 (244 μs) fc/25 (977 μs) 2 5 2 4 4 6 4 7 4 6 3 6 5 8 Note 1: The prescaler output clock φTn must be selected so that φTn < fsys is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while the timer is operating. Note 3: "." denotes a setting prohibited. "*" denotes a don’t care. Page 313 2013/5/31 11. 11.5 16-bit Timer / Event Counters (TMRB) Description of Operations for Each Circuit TMPM361F10FG Table 11-4 Prescaler Output Clock Resolutions (fc = 32MHz,fs = 32.768kHz) Select φT0 CGSYSCR Select peripheral clock CGSYSCR Select gear clock CGSYSCR 000 (fc) 100 (fc/2) 0 0 (fgear) 101 (fc/4) 110 (fc/8) 2013/5/31 Select prescaler clock Prescaler output clock function CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) 001 (fperiph/2) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 010 (fperiph/4) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 011 (fperiph/8) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 100 (fperiph/16) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 101 (fperiph/32) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 000 (fperiph/1) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 001 (fperiph/2) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 010 (fperiph/4) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 011 (fperiph/8) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 100 (fperiph/16) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 101 (fperiph/32) fc/2 (16.0 μs) fc/2 fc/213 (256.0 μs) Page 314 2 5 3 5 3 6 4 6 9 4 7 5 7 5 8 6 8 11 (64.0 μs) TMPM361F10FG Table 11-4 Prescaler Output Clock Resolutions (fc = 32MHz,fs = 32.768kHz) Select φT0 CGSYSCR Select peripheral clock CGSYSCR Select gear clock CGSYSCR 000 (fc) 100 (fc/2) 0 1 (fc) 101 (fc/4) 110 (fc/8) 1 * * Select prescaler clock Prescaler output clock function CGSYSCR φT1 φT4 φT16 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) − fc/23 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) − fc/2 (0.25 μs) fc/25 (1.0 μs) 001 (fperiph/2) − fc/24 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 000 (fperiph/1) − − fc/25 (1.0 μs) 001 (fperiph/2) − fc/24 (0.5 μs) fc/26 (2.0 μs) 010 (fperiph/4) − fc/2 (1.0 μs) fc/27 (4.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 101 (fperiph/32) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) * fs/2 (61μs) fs/23 (244 μs) fc/25 (977 μs) 2 5 2 4 4 6 4 7 4 6 3 6 5 8 Note 1: The prescaler output clock φTn must be selected so that φTn < fsys is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while the timer is operating. Note 3: "." denotes a setting prohibited. "*" denotes a don’t care. Page 315 2013/5/31 11. 11.5 16-bit Timer / Event Counters (TMRB) Description of Operations for Each Circuit 11.5.2 TMPM361F10FG Up-counter (UC) UC is a 16-bit binary counter. ・ Source clock UC source clock, specified by TBxMOD, can be selected from either three types - φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TBxIN0 pin. ・ Counter start / stop Counter operation is specified by TBxRUN. UC starts counting if = "1", and stops counting and clears counter value if = "0". ・ Timing to clear UC 1. When a match is detected. By setting TBxMOD = "1", UC is cleared if when the comparator detects a match between counter value and the value set in TBxRG1. UC operates as a free-running counter if TBxMOD = "0". 2. When UC stops UC stops counting and clears counter value if TBxRUN = "0". ・ UC overflow If UC overflow occurs, the INTTBx overflow interrupt is generated. 11.5.3 Timer registers (TBxRG0, TBxRG1) TBxRG0 and TBxRG1 are registers for setting values to compare with up-counter values and two registers are built into each channel. If the comparator detects a match between a value set in this timer register and that in a UC up-counter, it outputs the match detection signal. TBxRG0 and TBxRG1 are consisted of the double-buffered configuration which are paired with register buffers. The double buffering is disabled in the initial state. Controlling double buffering disable or enable is specified by TBxCR bit. If = "0", the double buffering becomes disable. If = "1", it becomes enable. When the double buffering is enabled, a data transfer from the register buffer to the timer register (TBxRG0/1) is done in the case that UC is matched with TBxRG1.When the counter is stopped even if double buffering is enabled, the double buffering operates as a single buffer, and an immediate data can be written to the TBxRG0 and TBxRG1. 2013/5/31 Page 316 TMPM361F10FG 11.5.4 Capture This is a circuit that controls the timing of latching values from the UC up-counter into the TBxCP0 and TBxCP1 capture registers. The timing with which to latch data is specified by TBxMOD. Software can also be used to import values from the UC up-counter into the capture register; specifically, UC values are taken into the TBxCP0 capture register each time "0" is written to TBxMOD. 11.5.5 Capture registers (TBxCP0, TBxCP1) This register captures an up-counter (UC) value. 11.5.6 Up-counter capture register (TBxUC) Other than the capturing functions shown above, the current count value of the UC can be captured by reading the TBxUC registers. 11.5.7 Comparators (CP0, CP1) This register compares with the up-counter (UC) and the value setting of the Timer Register (TBxRG0 and TBxRG1) to detect whether there is a match or not. If a match is detected, INTTBx is generated. 11.5.8 Timer Flip-flop (TBxFF0) The timer flip-flop (TBxFF0) is reversed by a match signal from the comparator and a latch signal to the capture registers. It can be enabled or disabled to reverse by setting the TBxFFCR. The value of TBxFF0 becomes undefined after a reset. The flip-flop can be reversed by writing "00" to TBxFFCR. It can be set to "1" by writing "01," and can be cleared to "0" by writing "10." The value of TBxFF0 can be output to the Timer output pin (TBxOUT). If the timer output is performed, the corresponding port settings must be programmed beforehand. 11.5.9 Capture interrupt (INTCAPx0, INTCAPx1) Interrupts INTCAPx0 and INTCAPx1 can be generated at the timing of latching values from the UC up-counter into the TBxCP0 and TBxCP1 capture registers. The interrupt timing is specified by the CPU. Page 317 2013/5/31 11. 11.6 16-bit Timer / Event Counters (TMRB) Description of Operations for Each Mode 11.6 TMPM361F10FG Description of Operations for Each Mode 11.6.1 16-bit interval Timer Mode In the case of generating constant period interrupt, set the interval time to the Timer register (TBxRG1) to generate the INTTBx interrupt. 7 6 5 4 3 2 1 0 TBxEN ← 1 X X X X X X X Enables TMRBx operation. TBxRUN ← X X X X X 0 X 0 Stops count operation. Interrupt Set-Enable Register ← * * * * * * * * Permits INTTBx interrupt by setting corresponding bit to "1". TBxFFCR ← X X 0 0 0 0 1 1 Disable to TBxFF0 reverse trigger TBxMOD ← X 0 1 0 0 1 * * Changes to prescaler output clock as input clock. Specifies capture function to disable. (** = 01, 10, 11) TBxRG1 TBxRUN ← * * * * * * * * ← * * * * * * * * ← * * * * * 1 X 1 Specifies a time interval. (16 bits) Starts TMRBx. Note:X; Don’t care −; No change 11.6.2 16-bit Event Counter Mode It is possible to make it the event counter by using an input clock as an external clock (TBxIN0 pin input). The up-counter counts up on the rising edge of TBxIN0 pin input. It is possible to read the count value by capturing value using software and reading the captured value. 7 6 5 4 3 2 1 0 TBxEN ← 1 X X X X X X X TBxRUN ← X X X X X 0 X 0 Set PORT registers. Enables TMRBx operation. Stops count TMRBx. Allocates corresponding port to TBxIN0. TBxFFCR ← X X 0 0 0 0 1 1 Disable to TBxFF0 reverse trigger. TBxMOD ← X 0 1 0 0 0 0 0 Changes to TBxIN0 as an input clock. TBxRUN ← * * * * * 1 X 1 Starts TMRBx. TBxMOD ← X 0 0 0 0 0 0 0 Software capture is done. Note:X; Don’t care −; No change 2013/5/31 Page 318 TMPM361F10FG 11.6.3 16-bit PPG (Programmable Pulse Generation) Output Mode Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active Programmable square waves can be output from the TBxOUT pin by triggering the timer flip-flop (TBxFF) to reverse when the set value of the up-counter (UC) matches the set values of the timer registers (TBxRG0 and TBxRG1). Note that the set values of TBxRG0 and TBxRG1 must satisfy the following requirement: Set value of TBxRG0 < Set value of TBxRG1 Match with TBxRG0 (INTTBx interrupt) Match with TBxRG1 (INTTBx interrupt) TBxOUT pin Figure 11-3 Example of Output of Programmable Pulse Generation (PPG) In this mode, by enabling the double buffering of TBxRG0, the value of register buffer 0 is shifted into TBxRG0 when the set value of the up-counter matches the set value of TBxRG1. This facilitates handling of small duties. Match with TBxRG0 Up-counter= Q1 Up-counter= Q2 Match with TBxRG1 Trigger to shift to TBxRG0 TBxRG0 (Compare value) Q1 Register buffer Q2 Q2 Q3 Write TBxRG0 TBxRG1 (Compare value) Register buffer Q4 Q5 Q5 Q6 Write TBxRG Figure 11-4 Register Buffer Operation Page 319 2013/5/31 11. 11.6 16-bit Timer / Event Counters (TMRB) Description of Operations for Each Mode TMPM361F10FG The block diagram of this mode is shown below. TBxOUT (PPGฟຊ) TBxRUN Selector TBxIN0 φT1 φT4 φT16 16-bit up-counter UC F/F (TBxFF0) Clear Match 16-bit comparetor Selector 16-bit comparetor Selector TBxRG0 Write TBxRG0 TBxRG1 Write TBxRG1 Register buffer0 Register buffer1 TBxCR TBxCR Internal data bus Figure 11-5 Block Diagram of 16-bit PPG Mode Each register in the 16-bit PPG output mode must be programmed as listed below. 7 6 5 4 3 2 1 0 TBxEN ← 1 X X X X X X X TBxRUN ← X X X X X 0 X 0 Stops count operation. TBxCR ← 0 0 − X − X 0 0 Disable double buffering. TBxRG0 ← * * * * * * * * Specifies a duty. (16 bits)) ← * * * * * * * * TBxRG1 ← * * * * * * * * ← * * * * * * * * ← 1 0 − X − X 0 0 TBxCR Enables TMRBx operation. Specifies a cycle. (16 bits) Enables the TBxRG0 double buffering. (Changes the duty / cycle when the INTTBx interrupt is generated) TBxFFCR ← X X 0 0 1 TBxMOD ← X 0 1 0 0 1 1 0 Specifies to trigger TBxFF0 to reverse when a match with TBxRG0 or TBxRG1 is detected, and sets the initial value of TBxFF0 to "0". 1 * * Designates the prescaler output clock as the input clock, and disables the capture function. (** = 01, 10, 11) Set PORT registers. TBxRUN ← Allocates corresponding port to TBxOUT. * * * * * 1 X 1 Starts TMRBx. Note:X; Don’t care −; No change 2013/5/31 Page 320 TMPM361F10FG 11.6.4 Timer synchronous mode This mode enables the timers to start synchronously. If the mode is used with PPG output, the output can be applied to drive a motor. TMRB is consisted of pairs of 4-channel TMRB. If one channel starts, remaining 3 channels can be start synchronously. In the TMPM361F10FG, the following combinations allow to use. Start trigger channel Synchronous operation channel (Master channel) (Slave channel) TMRB0 TMRB1, TMRB2, TMRB3 TMRB4 TMRB5, TMRB6, TMRB7 TMRB8 TMRB9, TMRBA, TMRBB TMRBC TMRBD, TMRBE, TMRBF Use of the timer synchronous mode is specified in TBxCR bit. ・ = "0" : Timer operates individually. ・ = "1" : Timers operates synchronously. Set "0" to the bit in the master channel. If = "1" is set in the slave channel, the start timing is synchronized with master channel start timing. Setting of start timing for TBxRUN bit in the slave channel is not required. Page 321 2013/5/31 11. 11.7 16-bit Timer / Event Counters (TMRB) Applications using the Capture Function 11.7 TMPM361F10FG Applications using the Capture Function The capture function can be used to develop many applications, including those described below: 1. One-shot pulse output triggered by an external pulse 2. Frequency measurement 3. Pulse width measurement 4. Time difference measurement 11.7.1 One-shot pulse output triggered by an external pulse One-shot pulse output triggered by an external pulse is carried out as follows: The 16-bit up-counter is made to count up by putting it in a free-running state using the prescaler output clock. An external pulse is input through the TBxIN0 pin. A trigger is generated at the rising of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (TBxCP0). The CPU must be programmed so that an interrupt INTCAPx0 is generated at the rising of an external trigger pulse. This interrupt is used to set the timer registers (TBxRG0) to the sum of the TBxCP0 value (c) and the delay time (d), (c + d), and set the timer registers (TBxRG1) to the sum of the TBxRG0 values and the pulse width (p) of one-shot pulse, (c + d + p). TBxRG1 change must be completed before the next match. In addition, the timer flip-flop control registers(TBxFFCR) must be set to "11". This enables triggering the timer flip-flop (TBxFF0) to reverse when UC matches TBxRG0 and TBxRG1. This trigger is disabled by the INTTBx interrupt after a one-shot pulse is output. Symbols (c), (d) and (p) used in the text correspond to symbols c, d and p in "Figure 11-6 One-shot Pulse Output (With Delay)". Put the counter in a free-running state. Count clock (Internal clock) c+d c TBxIN0 pin input (External trigger pulse) Match with TBxRG0 Match with TBxRG1 c+d+p Taking data into capture register (TBxCP0) INTCAPx0 INTTBx generation generation INTTBx generation Enable reverse Enable reverse Timer output TBxOUT pin Disable reverse when data is taken into TBxCP0 Delay time (d) Pulse width (p) Figure 11-6 One-shot Pulse Output (With Delay) 2013/5/31 Page 322 TMPM361F10FG The followings show the settings in the case that 2 ms width one-shot pulse is output after 3ms by triggering TBxIN0 input at the rising edge. (φT1 is selected for counting.) 7 6 5 4 3 2 1 0 [Main processing] Capture setting by TBxIN0 Set PORT registers. Allocates corresponding port to TBxIN0. TBxEN ← 1 X X X X X X X TBxRUN ← X X X X X 0 X 0 Stops count operation. Changes source clock to φT1. Fetches a count value into the TBxCP0 at the rising edge of TBxIN0. TBxMOD ← X 0 1 0 1 0 0 1 TBxFFCR ← X X 0 0 0 0 1 0 Enables TMRBx operation. Clears TBxFF0 reverse trigger and disables. Set PORT registers. Allocates corresponding port to TBxOUT. Interrupt Set-Enable Register ← * * * * * * * * Permits to generate interrupts specified by INTCAPx0 interrupt corresponding bit by setting to "1". TBxRUN ← * * * * * 1 X 1 Starts the TMRBx module. Sets count value. (TBxCAP0 + 3ms/φT1) [Processing of INTCAPx0 interrupt service routine] Pulse output setting TBxRG0 TBxRG1 ← * * * * * * * * ← * * * * * * * * ← * * * * * * * * ← * * * * * * * * X X − − 1 1 − − X X X X X 1 0 1 Masks except TBxRG1 correspondence interrupt. * * Permits to generate interrupt specified by INTTBx interrupt corresponding bit setting to "1". − − Clears TBxFF0 reverse trigger setting. * Prohibits interrupts specified by INTTBx interrupt corresponding bit by setting to "1". TBxFFCR ← TBxIM ← Interrupt Set-Enable Register ← * * * * * * Sets count value.(TBxCAP0 + (3+2)ms/φT1) Reverses TBxFF0 if UC consistent with TBxRG0 and TBxRG1. [Processing of INTTBx interrupt service routine] Output disable TBxFFCR ← Interrupt enable clear register ← X * X * − − * * 0 * 0 * * Note:X; Don’t care −; No change If a delay is not required, TBxFF0 is reversed when data is taken into TBxCP0, and TBxRG1 is set to the sum of the TBxCP0 value (c) and the one-shot pulse width (p), (c + p), by generating the INTCAPx0 interrupt. TBxRG1 change must be completed before the next match. TBxFF0 is enabled to reverse when UC matches with TBxRG1, and is disabled by generating the INTTBx interrupt. Count clock (Internal clock) c+p c TBxIN0 pin input (External trigger pulse) Match with TBxRG1 Taking data into the capture register TBxCP0 INTCAPx0 INTTBx generation generation Taking data into the capture register TBxCP1. Enable reverse Timer outut TBxOUT pin Enable reverse when data is taken into TBxCP0. Pulse width (p) Disable reverse when data is taken into TBxCP1. Figure 11-7 One-shot Pulse Output Triggered by an External Pulse (Without Delay) Page 323 2013/5/31 11. 11.7 16-bit Timer / Event Counters (TMRB) Applications using the Capture Function 11.7.2 TMPM361F10FG Frequency measurement The frequency of an external clock can be measured by using the capture function. To measure frequency, another 16-bit timer is used in combination with the 16-bit event counter mode. As an example, we explain with TMRB5 and TMRB0. TB0OUT of the 16-bit timer TMRB0 is used to specify the measurement time. TMRB5 count clock selects TB5IN0 input and performs count operation by using external clock input. If TB5MOD is set "11", TMRB5 count clock takes the counter value into the TB5CP0 at the rising edge of TB0OUT and takes the counter value into TB5CP1 at the falling edge of TB0OUT. This setting allows a count value of the 16-bit up-counter UC to be taken into the capture register (TB5CP0) upon rising of a timer flip-flop output (TB0OUT) of the 16-bit timer (TMRB0), and an UC counter value to be taken into the capture register (TB5CP1) upon falling of TB0OUT of the 16-bit timer (TMRB0). A frequency is then obtained from the difference between TB5CP0 and TB5CP1 based on the measurement, by generating the INTTB0 16-bit timer interrupt. For example, if the difference between TB5CP0 and TB5CP1 is 100 and the level width setting value of TB0OUT is 0.5 s, the frequency is 200 Hz (100 ÷ 0.5 s = 200 Hz). Count clock (TB5IN0 pin input) C1 C2 TB0OUT Taking data into TB5CP0 C1 Taking data into TB5CP1 C1 C2 C2 INTTB0 Figure 11-8 Frequency Measurement 11.7.3 Pulse width measurement By using the capture function, the "High" level width of an external pulse can be measured. Specifically, by putting it in a free-running state using the prescaler output clock, an external pulse is input through the TBxIN0 pin and the up-counter (UC) is made to count up. A trigger is generated at each rising and falling edge of the external pulse by using the capture function and the value of the up-counter is taken into the capture registers (TBxCP0, TBxCP1). The CPU must be programmed so that INTCAPx1 is generated at the falling edge of an external pulse input through the TBxIN0 pin. The "High" level pulse width can be calculated by multiplying the difference between TBxCP0 and TBxCP1 by the clock cycle of an internal clock. For example, if the difference between TBxCP0 and TBxCP1 is 100 and the cycle of the prescaler output clock is 0.5 μs, the pulse width is 100 × 0.5 μs = 50 μs. Caution must be exercised when measuring pulse widths exceeding the UC maximum count time which is dependant upon the source clock used. The measurement of such pulse widths must be made using software. 2013/5/31 Page 324 TMPM361F10FG The "Low" level width of an external pulse can also be measured. In such cases, the difference between C2 generated the first time and C1 generated the second time is initially obtained by performing the second stage of INTCAPx0 interrupt processing as shown in "Figure 11-9 Pulse Width Measurement" and this difference is multiplied by the cycle of the prescaler output clock to obtain the "Low" level width. 3UHVFDOHURXWSXW FORFN C1 C2 TBxIN0SLQLQSXW H[WHUQDOSXOVH Taking data into TBxCP0 C1 C1 Taking data into TBxCP1 C2 C2 INTCAPx0 INTCAPx1 Figure 11-9 Pulse Width Measurement 11.7.4 Time Difference Measurement The time difference of two events can be measured by the capture function. The up-counter (UC) is made to count up by putting it in a free-running state using the prescaler output clock. The value of UC is taken into the capture register (TBxCP0) at the rising edge of the TBxIN0 pin input pulse. The CPU must be programmed to generate INTCAPx0 interrupt at this time. The value of UC is taken into the capture register (TBxCP1) at the rising edge of the TBxIN1 pin input pulse. The CPU must be programmed to generate INTCAPx1 interrupt at this time. The time difference can be calculated by multiplying the difference between TBxCP1 and TBxCP0 by the clock cycle of an internal clock. Prescaler output clock C1 C2 TBxIN0 pin input TBxIN1 pin input Taking data into TBxCP0 Taking data into TBxCP1 INTCAPx0 INTCAPx1 Time difference Figure 11-10 Time Difference Measurement Page 325 2013/5/31 11. 11.7 16-bit Timer / Event Counters (TMRB) Applications using the Capture Function 2013/5/31 TMPM361F10FG Page 326 TMPM361F10FG 12. Serial Channel (SIO/UART) 12.1 Overview This device has two modes for the serial channel, one is the synchronous communication mode (I/O interface mode), and the other is the asynchronous communication mode (UART mode). Their features are described as follows. ・ Transfer Clock - Generate the transfer clock by dividing the peripheral clock (φT0) frequency into 1/2, 1/8, 1/32, 1/128. - The prescaler output clock frequency can be divided by each of the numbers from 1 to 16. - The prescaler output frequency can be divided by each of the numbers from 1, N+m/16 (N=2-15, m=1-15), and 16. (only UART mode) - The system clock is usable. (only UART mode) ・ Double buffer / FIFO The double buffer function and the FIFO buffers (total of transmit and receive) can be used up to 4bytes. ・ I/O Interface mode - Transfer Mode : the half duplex (transmit / receive) and the full duplex - Clock : Output (fixed rising edge) / Input (selectable rising / falling edge) - A time interval can be set within a range where continuous transmission is performed. ・ UART Mode - Data length : 7, 8, 9 bits - Add parity bit (to be against 9 bits data length) - Serial links to use wake-up function - Handshaking function with CTS pin In the following explanation, "x" represents channel number. 12.2 Difference in the Specification of SIO Modules TMPM361F10FG has 5 channels. Each channel function is independent. The pins and interrupts for each channel are assigned as follows. Table 12-1 Differences for each channels of SIO Modules Pin name Interrupt Timer for serial clock DMA INTTX0 TB5OUT support INTRX1 INTTX1 TB5OUT support PM0 INTRX2 INTTX2 TB5OUT support PM4 INTRX3 INTTX3 TB5OUT support PN2 INTRX4 INTTX4 TB6OUT support Receive Transmit interrupt interrupt PE6 INTRX0 PL5 PL6 PM1 PM2 PM5 PM6 PN0 PN1 TXD RXD CTS / SCLK channel 0 PE4 PE5 channel 1 PL4 channel 2 channel 3 channel 4 Page 327 2013/5/31 12. 12.3 Serial Channel (SIO/UART) Configuration 12.3 TMPM361F10FG Configuration Figure 12-1 shows SIO block diagram. Prescaler φT0 4 2 φT1 8 φT4 16 32 64 128 φT16 φT64 Serial clock generation circuit SCxBRCR TBxOUT (from TMRBx) SCxBRCR SCxBRADD Selector SCxMOD0 Selector Divider UART ࡕ࡯࠼ SCxBRCR Selector φT1 φT4 φT16 φT64 SIOCLK SCxMOD0 Baud rate generator fsys Selector ÷2 SCLKx input I/O interface mode DMA clear (SIODMACLR) SCxCR I/O interface mode DMA request (SIODMAREQ) SCLKx output Interrupt request(INTRXx) Interrupt request (INTTXx) DMA control SCxMOD0 Receive counter (only at UART÷16) Serial channel interrupt control (only at UART÷16) TXDCLK RXDCLK SCxMOD0 Transmission control Receive control Transmit control CTSx SCxCR SCxMOD0 RXDx Receive shifit register RB8 Receive buffer (SCxBUF) Parity control Transmit shift register TB8 Transmit buffer (SCxBUF) Error Flag SCxCR FIFO control Internal data bus Internal data bus FIFO control Internal data bus Figure 12-1 SIO Block Diagram 2013/5/31 Page 328 TXDx TMPM361F10FG 12.4 Registers Description 12.4.1 Registers List in Each Channel The below table shows registers and addresses for each register. Channel x Base Address Channel0 0x400E_1000 Channel1 0x400E _ 1100 Channel2 0x400E _ 1200 Channel3 0x400E _ 1300 Channel4 0x400E _ 1400 Register name (x=0 to 4) Address(Base+) Enable register SCxEN 0x0000 Buffer register SCxBUF 0x0004 Control register SCxCR 0x0008 Mode control register 0 SCxMOD0 0x000C Baud rate generator control register SCxBRCR 0x0010 SCxBRADD 0x0014 Baud rate generator control register 2 Mode control register 1 SCxMOD1 0x0018 Mode control register 2 SCxMOD2 0x001C RX FIFO configuration register SCxRFC 0x0020 TX FIFO configuration register SCxTFC 0x0024 RX FIFO status register SCxRST 0x0028 SCxTST 0x002C SCxFCNF 0x0030 TX FIFO status register FIFO configuration register Note 1: Do not modify any control register when data is being transmitted or received. Note 2: Do not clear SCxMOD0 when data is being received. Note 3: Do not clear SCxMOD1 when data is being transmitted. Page 329 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description 12.4.2 TMPM361F10FG SCxEN (Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - SIOE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 − R Read as "0". 0 SIOE R/W SIO operation 0: disable 1: Operation Specifies the SIO operation. To use the SIO, set = "1". When the operation is disabled, no clock is supplied to the other registers in the SIO module. This can reduce the power consumption. If the SIO operation is executed and then disabled, the settings will be maintained in each register except for SCxTFC. Note 1: In case that SCxEN="0" (Stop SIO operation) or the operation mode is changed to IDLE mode with SCxMOD1="0" (Stop SIO operation in IDLE mode), SCxTFC is initiailzed again. Note 2: In the DMA transfer using transmit / receive interrupt of SIO, firstly generate software reset by setting SCxMOD2, next, enable DMAC (DMA request waiting state), and then start transmit / receive of SIO. 2013/5/31 Page 330 TMPM361F10FG 12.4.3 SCxBUF (Buffer Register) SCxBUF works as a transmit buffer or FIFO for write operation and as a receive buffer or FIFO for read operation. 31 30 29 28 27 26 25 bit symbol - - - - - - - 24 - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After reset Bit TB / RB 0 Bit Symbol 0 0 0 Type Function 31-8 − R Read as "0". 7-0 TB[7:0] / RB [7:0] R/W [write] TB :Transmit buffer / FIFO [read] RB : Receive buffer / FIFO Page 331 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description 12.4.4 TMPM361F10FG SCxCR (Control Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol RB8 EVEN PE OERR PERR FERR SCLKS IOC After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as "0". 7 RB8 R Receive data bit 8 (For UART) 6 EVEN R/W 9th bit of the received data in the 9 bits UART mode. Parity (For UART) 0: Odd 1: Even Selects even or odd parity. "0" :odd parity, "1" : even parity The parity bit can be used only in the 7-bit or 8-bit UART mode. 5 PE R/W Adding parity (for UART) 0: Disabled 1: Enabled Controls enabling / disabling parity The parity bit can be used only in the 7-bit or 8-bit UART mode. 4 OERR R Overrun error flag (Note) 0: Normal operation 1: Error 3 PERR R Parity / Underrun error flag (Note) 0: Normal operation 1: Error 2 FERR R Framing error flag (Note) 0: Normal operation 1: Error 1 SCLKS R/W Selecting input clock edge (For I/O Interface) Set to "0" in the clock output mode. 0: Data in the transmit buffer is sent to TXDx pin one bit at a time on the falling edge of SCLKx. Data from RXDx pin isrecieved in the recieve buffer one bit at a time on the rising edge of SCLKx. In this case, the SCLKx starts from high level. 1: Data in the transmit buffer is sent to TXDx pin one bit at a time on the rising edge of SCLKx. Data from RXDx pin isrecieved in the recieve buffer one bit at a time on the falling edge of SCLKx. In this case, the SCLKx starts from low level. 0 IOC R/W Selecting clock (For I/O Interface) 0: Baud rate generator 1: SCLK pin input 2013/5/31 Page 332 TMPM361F10FG 12.4.5 SCxMOD0 (Mode Control Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol TB8 CTSE RXE WU After reset 0 0 0 0 Bit Bit Symbol Type SM 0 0 SC 0 0 0 Function 31-8 − R Read as "0". 7 TB8 R/W Transmit data bit 8 (For UART) Writes the 9th bit of transmit data in the 9 bits UART mode. 6 CTSE R/W Handshake function control (For UART) 0: CTS disabled 1: CTS enabled Controls handshake function. Setting "1" enables handshake function using CTS pin. 5 RXE R/W Receive control (Note1) (Note2) 0: Disabled 1: Enabled 4 WU R/W Wake-up function (For UART) 0: Disabled 1: Enabled This function is available only at 9-bit UART mode. In other mode, this function has no meaning. When it is set to be enabled, Interrupt occurs only when RB9 = "1" at 9-bit in the UART mode. 3-2 SM[1:0] R/W Specifies transfer mode. 00: I/O interface mode 01: 7-bit length UART mode 10: 8-bit length UART mode 11: 9-bit length UART mode 1-0 SC[1:0] R/W Serial transfer clock (For UART) 00: Timer TB 9OUT Refer to Table 12-1. 01: Baud rate generator 10: Internal clock fsys 11: External clock (SCLK input) (As for the I/O interface mode, the serial transfer clock can be set in the control register (SCxCR). Note 1: Set after specifying each of mode registers (SCxMOD0, SCxMOD1, SCxMOD2). Note 2: Do not clear SCxMOD0 when data is being received. Page 333 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description 12.4.6 TMPM361F10FG SCxMOD1 (Mode Control Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 4 3 2 1 0 bit symbol I2SC After reset 0 Bit Bit Symbol 5 FDPX 0 TXE 0 0 Type SINT 0 0 0 0 Function 31-8 − R Read as "0". 7 I2SC R/W IDLE 0: Stop 1: Operate Specifies the IDLE mode operation. 6-5 FDPX[1:0] R/W Transfer mode setting 00: Transfer prohibited 01: Half duplex (Receive) 10: Half duplex (Transmit) 11: Full duplex Configures the transfer mode in the I/O interface mode. Also configures the FIFO if it is enabled. In the UART mode, it is used only to specify the FIFO configuration. TXE 4 R/W Transmit control (Note1) (Note2) 0: Disabled 1: Enabled This bit enables transmission and is valid for all the transfer modes. 3-1 SINT[2:0] R/W Interval time of continuous transmission (For I/O interface) 000: None 001: 1SCLK 010: 2SCLK 011: 4SCLK 100: 8SCLK 101: 16SCLK 110: 32SCLK 111: 64SCLK This parameter is valid only for the I/O interface mode when SCLK pin output is selected. In other modes, this function has no meaning. Specifies the interval time of continuous transmission when double buffering or FIFO is enabled in the I/O interface mode. 0 − R/W Write to "0". Note 1: Specify all the modes first and then enable the bit. Note 2: Do not stop the transmit operation (by setting = "0") when data is being transmitted. Note 3: In the DMA transfer using transmit / receive interrupt of SIO, the full duplex transmission can not be used. Note 4: In case that SCxEN="0" (Stop SIO operation) or the operation mode is changed to IDLE mode with SCxMOD1="0" (Stop SIO operation in IDLE mode), SCxTFC is initiailzed again. 2013/5/31 Page 334 TMPM361F10FG 12.4.7 SCxMOD2 (Mode Control Register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol TBEMP RBFLL TXRUN SBLEN DRCHG WBUF After reset 1 0 0 0 0 0 Bit Bit Symbol Type 0 SWRST 0 0 Function 31-8 − R Read as "0". 7 TBEMP R Transmit buffer empty flag. 0: Full 1: Empty If double buffering is disabled, this flag is insignificant. This flag shows that the transmit double buffers are empty. When data in the transmit double buffers is moved to the transmit shift register and the double buffers are empty, this bit is set to "1". Writing data again to the double buffers sets this bit to "0". 6 RBFLL R Receive buffer full flag. 0: Empty 1: Full If double buffering is disabled, this flag is insignificant. This is a flag to show that the receive double buffers are full. When a receive operation is completed and received data is moved from the receive shift register to the receive double buffers, this bit changes to "1" while reading this bit changes it to "0". 5 TXRUN R In transmission flag 0: Stop 1: Operate This is a status flag to show that data transmission is in progress. and bits indicate the following status. 1 − Transmission in progress 1 Transmission completed 0 Wait state with data in transmit buffer. 0 4 SBLEN R/W Status STOP bit (For UART) 0: 1-bit 1: 2-bit This specifies the length of transmission stop bit in the UART mode. On the receive side, the decision is made using only a single bit regardless of the setting. 3 DRCHG R/W Setting transfer direction 0: LSB first 1: MSB first Specifies the direction of data transfer in the I/O interface mode. In the UART mode, set this bit to LSB first. 2 WBUF R/W Double buffer 0: Disabled 1: Enabled This parameter enables or disables the transmit / receive double buffers to transmit (in both SCLK output / input modes) and receive (in SCLK output mode) data in the I/O interface mode and to transmit data in the UART mode. When receiving data in the I/O interface mode (SCLK input) and UART mode, double buffering is enabled in both case that "0" or "1" is set to bit. Page 335 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description Bit 1-0 TMPM361F10FG Bit Symbol SWRST[1:0] Type R/W Function Software reset Overwriting "01" in place of "10" generates a software reset. When this software reset is executed, the following bits are initialized and the transmit/receive circuit, the transmit circuit and the FIFO become initial state (see Note1 and Note2). Register Bit SCxMOD0 SCxMOD1 SCxMOD2 , , SCxCR , , Note 1: While data transmission is in progress, any software reset operation must be executed twice in succession. Note 2: A software reset requires 2 clocks-duration at the time between the end of recognition and the start of execution of software reset instruction. 2013/5/31 Page 336 TMPM361F10FG 12.4.8 SCxBRCR (Baud Rate Generator Control Register), SCxBRADD (Baud Rate Generator Control Register 2) The division ratio of the baud rate generator can be specified in the registers shown below. SCxBRCR bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 5 4 3 2 1 0 0 0 7 6 bit symbol - BRADDE After reset 0 0 Bit Bit Symbol BRCK 0 BRS 0 Type 0 0 Function 31-8 − R Read as "0". 7 − R/W Write to "0". 6 BRADDE R/W N + (16 − K)/16 divider function (For UART) 0: Disabled 1: Enabled This division function can only be used in the UART mode. 5-4 BRCK[1:0] R/W Select input clock to the baud rate generator. 00: φT1 01: φT4 10: φT16 11: φT64 3-0 BRS[3:0] R/W Division ratio "N" 0000: 16 0001: 1 0010: 2 : 1111: 15 Page 337 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description TMPM361F10FG SCxBRADD 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 16 23 22 21 20 19 18 17 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol - - - - After reset 0 0 0 0 Bit Bit Symbol Type BRK Function 31-4 − R Read as "0". 3-0 BRK[3:0] R/W Specify K for "N + (16 − K)/16" division (For UART) 0000: Prohibited 0001: K = 1 0010: K = 2 : 1111: K = 15 Table 12-2 lists the setting of baud rate generator division ratio. Table 12-2 Setting division ratio = "0" = "1" (Note1) (Only UART mode) Specify "N" (Note2) (Note3) No setting required Division ratio Divide by N Specify "K" (Note4) N+ (16 − K) division 16 Note 1: To use the "N + (16 - K)/16" division function, be sure to set to "1" after setting the K value to . The "N + (16 - K)/16" division function can only be used in the UART mode. Note 2: As a division ratio, 1 ("0001") or 16 ("0000") can not be applied to N when using the "N + (16 - K)/ 16" division function in the UART mode. Note 3: The division ratio "1" of the baud rate generator can be specified only when the double buffering is used in the I/O interface mode. Note 4: Specifying "K = 0" is prohibited. 2013/5/31 Page 338 TMPM361F10FG 12.4.9 SCxFCNF (FIFO Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - RFST TFIE RFIE RXTXCNT CNFG After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as "0". 7-5 - R/W Be sure to write "000". 4 RFST R/W Bytes used in RX FIFO 0: Maximum 1: Same as FILL level of RX FIFO When RX FIFO is enabled, the number of RX FIFO bytes to be used is selected (Note1) 0: The maximum number of bytes of the FIFO configured (see also ). 1: Same as the fill level for receive interrupt generation specified by SCxRFC 3 TFIE R/W TX interrupt for TX FIFO 0:Disabled 1:Enabled When TX FIFO is enabled, transmit interrupts are enabled or disabled by this parameter. 2 RFIE R/W RX interrupt for RX FIFO 0:Disabled 1:Enabled When RX FIFO is enabled, receive interrupts are enabled or disabled by this parameter. 1 RXTXCNT R/W Automatic disable of RXE / TXE 0: None 1: Auto disabled Controls automatic disabling of transmission and reception. Setting "1" enables to operate as follows 0 CNFG R/W Half duplex RX When receive shift register, the receive buffer and the RX FIFO are filled, SCxMOD0 is automatically set to "0" to inhibit further reception. Half duplex TX When the TX FIFO, the transmit buffer and the transmit shift register is empty, SCxMOD1 is automatically set to "0" to inhibit further transmission. Full duplex When either of the above two conditions is satisfied, TXE/RXE are automatically set to "0" to inhibit further transmission and reception. Enables FIFO 0: Disabled 1: Enabled Enabled bit for FIFO. (note2) If is set to "1", the SCxMOD1 setting automatically configures FIFO as follows: Half duplex RX RX FIFO 4 bytes Half duplex TX TX FIFO 4 bytes Full duplex RX FIFO 2 bytes + TX FIFO 2 bytes Note 1: Regarding TX FIFO, the maximum number of bytes being configured is always available. The available number of bytes is the bytes already written to the TX FIFO. Note 2: The FIFO can not use in 9bit UART mode. Page 339 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description TMPM361F10FG Note 3: In the DMA transfer using transmit / receive interrupt of SIO, the FIFO function can not be used. 2013/5/31 Page 340 TMPM361F10FG 12.4.10 SCxRFC (RX FIFO Configuration Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol RFCS RFIS - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 RIL 0 0 Function 31-8 − R Read as "0". 7 RFCS W RX FIFO clear (Note1) 1: Clear When SCxRFC is set to "1", the receive FIFO is cleared and SCxRST is "000". And also the read pointer is initialized. 6 RFIS R/W Select interrupt generation condition 0: when the data reaches to the specified fill level. 1: when the data reaches to the specified fill level or the data exceeds the specified fill level at the time data is read. 5-2 − R Read as "0". 1-0 RIL[1:0] R/W FIFO fill level to generate RX interrupts Half duplex Full duplex 00 4 bytes 2 bytes 01 1 byte 1 byte 10 2 bytes 2 bytes 11 3 bytes 1 byte Note 1: To use TX/RX FIFO buffer, TX / RX FIFO must be cleared after setting the SIO transfer mode (half duplex / full duplex) and enabling FIFO (SCxFCNF = "1"). Note 2: DMA transfer is not started by an interrupt generated in the fill level of FIFO. Page 341 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description TMPM361F10FG 12.4.11 SCxTFC (TX FIFO Configuration Register) (Note2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol TFCS TFIS - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 TIL 0 0 Function 31-8 − R Read as "0". 7 TFCS W TX FIFO clear (Note1) 1: Clear When SCxTST is set to "1", the transmit FIFO is cleared and SCxTST is "000". And also the write pointer is initialized. 6 TFIS R/W Selects interrupt generation condition. 0: An interrupt is generated when the data reaches to the specified fill level. 1: An interrupt is generated when the data reaches to the specified fill level or the data can not reach the specified fill level at the time data is read. 5-2 − R Read as "0". 1-0 TIL[1:0] R/W Fill level which transmit interrupt is occurred. Half duplex Full duplex 00 Empty Empty 01 1 byte 1 byte 10 2 bytes Empty 11 3 bytes 1 byte Note 1: To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode (half duplex/full duplex) and enabling FIFO (SCxFCNF = "1"). Note 2: After you perform the following operations, configure the SCxTFC register again. SCxEN = "0" (SIO operation stop) Conditions are as follows:SCxMOD1 = "0" (operation is prohibited in IDLE mode) and releasing the low power consumption mode which is started by the WFI (Wait For Interrupt) instruction. Note 3: DMA transfer is not started by an interrupt generated in the fill level of FIFO. 2013/5/31 Page 342 TMPM361F10FG 12.4.12 SCxRST (RX FIFO Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol ROR - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type RLVL 0 0 0 Function 31-8 − R Read as "0". 7 ROR R RX FIFO Overrun (Note) 0: Not generated 1: Generated 6-3 − R Read as "0". 2-0 RLVL[2:0] R Status of RX FIFO fill level 000: Empty 001: 1 byte 010: 2 bytes 011: 3 bytes 100: 4 bytes Note:The bit is cleared to "0" when receive data is read from the SCxBUF register. Page 343 2013/5/31 12. 12.4 Serial Channel (SIO/UART) Registers Description TMPM361F10FG 12.4.13 SCxTST (TX FIFO Status Register) 31 30 29 28 27 26 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TUR - - - - After reset 1 0 0 0 0 Bit Bit Symbol Type TLVL 0 Function 31-8 − R Read as "0". 7 TUR R TX FIFO Under run (Note) 0: Not generated 1: Generated 6-3 − R Read as "0". 2-0 TLVL[2:0] R Status of TX FIFO level 000: Empty 001: 1 byte 010: 2 byte 011: 3 byte 100: 4 byte Note:The bit is cleared to "0" when transmit data is written to the SCxBUF register. 2013/5/31 25 Page 344 0 0 TMPM361F10FG 12.5 Operation in Each Mode Table 12-3 shows the modes and data format. Table 12-3 Mode and Data format Mode Mode type Data length Transfer direction Specifies whether to use parity bits STOP bit length (Transmit) Mode 0 Synchronous communication mode 8 bit LSB first / MSB first - - (IO interface mode) Mode 1 Mode 2 Mode 3 Asynchronous communication mode (UART mode) 7 bit 8 bit ο LSB first 9bit ο 1 bit or 2 bit × Mode 0 is synchronous communication and can be used to extend I/O. This mode transmits and receives data in synchronization with SCLK. SCLK can be used for both input and output. The direction of data transfer can be selected from LSB first and MSB first. This mode is not allowed either to add a parity or STOP bits. The mode 1, mode 2 and mode 3 are asynchronous modes and the transfer direction is fixed to the LSB first. Parity bits can be added in the mode 1 and mode 2. The mode 3 has a wake-up function in which the master controller can start up slave controllers via the serial link (multi-controller system). STOP bit in transmission can be selected from 1 bit and 2 bits. The STOP bit length in reception is fixed to a one bit. Page 345 2013/5/31 12. 12.6 Serial Channel (SIO/UART) Data Format 12.6 TMPM361F10FG Data Format 12.6.1 Data Format List Figure 12-2 shows data format. ● Mode 0 (I/O interface mode) / LSB first bit 0 1 2 3 4 5 6 7 3 2 1 0 Transmission direction ● Mode 0 (I/O interface mode) / MSB first bit 7 6 5 4 Transmission direction ● ● ● Mode 1 (7 bits UART mode) Without parity start bit 0 1 2 3 4 5 6 stop With parity start bit 0 1 2 3 4 5 6 parity stop Mode 2 (8bits UART mode) Without parity start bit 0 1 2 3 4 5 6 7 stop With parity start bit 0 1 2 3 4 5 6 7 parity stop stop Mode 3 (9bits UART mode) start bit 0 1 2 3 4 5 6 7 8 start bit 0 1 2 3 4 5 6 7 bit 8 bit 8 = 1 represents address. (select code) bit 8 = 0 represents data. Figure 12-2 Data Format 2013/5/31 Page 346 stop (Wake-up) TMPM361F10FG 12.6.2 Parity Control The parity bit can be added only in the 7- or 8-bit UART mode. Setting "1" to SCxCR enables the parity. The SCxCR selects either even or odd parity. 12.6.2.1 Transmission Upon data transmission, the parity control circuit automatically generates the parity with the data in the transmit buffer. After data transmission is complete, the parity bit will be stored in SCxBUF in the 7-bit UART mode SCxMOD in the 8-bit UART mode. The and settings must be completed before data is written to the transmit buffer. 12.6.2.2 Receiving Data If the received data is moved from the receive shift register to the receive buffer, a parity is generated. In the 7-bit UART mode, the generated parity is compared with the parity stored in SCxBUF, while in the 8-bit UART mode, it is compared with the one in SCxCR. If there is any difference, a parity error occurs and the of the SCxCR register is set to "1". In use of the FIFO, indicates that a parity error was generated in one of the received data. 12.6.3 STOP Bit Length The length of the STOP bit in the UART transmission mode can be selected from one bit or two bits by setting the SCxMOD2. The length of the STOP bit data is determined as one-bit when it is received regardless of the setting of this bit. Page 347 2013/5/31 12. 12.7 Serial Channel (SIO/UART) Clock Control 12.7 TMPM361F10FG Clock Control 12.7.1 Prescaler There is a 7-bit prescaler to divide a prescaler input clock φT0 by 2, 8, 32 and 128. Use the CGSYSCR register in the clock / mode control block to select the input clock φT0 of the prescaler. The prescaler becomes active only when the baud rate generator is selected as a transfer clock by SCxMOD0 = "01". Table 12-4 (operation frequency 64MHz), Table 12-5 (operation frequency 48MHz) and Table 12-6 (operation frequency 32MHz) show the resolution of the input clock to the baud rate generator. Table 12-4 Clock resolution to the Baud Rate Generator fc = 64 MHz, fs = 32.768kHz φT0 selection CGSYSCR Peripheral clock selection Clock gear value CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 0 (fgear) 101 (fc/4) 110 (fc/8) 2013/5/31 Prescaler clock selection Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0312 μs) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 001 (fperiph/2) fc/22 (0.0625 μs) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 010 (fperiph/4) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 011 (fperiph/8) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 100 (fperiph/16) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/211 (32.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0 μs) 000 (fperiph/1) fc/22 (0.0625 μs) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 010 (fperiph/4) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 011 (fperiph/8) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/212 (64.0 μs) 101 (fperiph/32) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) fc/213 (128.0 μs) 000 (fperiph/1) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 001 (fperiph/2) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) 010 (fperiph/4) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 011 (fperiph/8) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 100 (fperiph/16) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) fc/213 (128.0 μs) 101 (fperiph/32) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0μs) fc/214 (256.0 μs) 000 (fperiph/1) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) 001 (fperiph/2) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (12.8 μs) fc/211 (32.0 μs) 010 (fperiph/4) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0μs) 011 (fperiph/8) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/2 100 (fperiph/16) fc/28 (4.0 μs) 101 (fperiph/32) fc/29 (8.0 μs) 3 5 3 6 4 6 4 7 Page 348 5 7 5 8 6 8 6 7 9 7 10 8 10 (16.0 μs) 8 fc/212 (64.0μs) (32.0 μs) fc/213 (128.0 μs) fc/210 (16.0 μs) fc/212 (64.0μs) fc/214 (256.0 μs) fc/211 (32.0 μs) fc/213 (128.0 μs) fc/215 (512.0 μs) 9 11 TMPM361F10FG Table 12-4 Clock resolution to the Baud Rate Generator fc = 64 MHz, fs = 32.768kHz φT0 selection CGSYSCR Peripheral clock selection Clock gear value CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 1 (fc) 101 (fc/4) 110 (fc/8) 1 Prescaler clock selection * * Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (00312 μs) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) 001 (fperiph/2) fc/2 (0.0625 μs) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/28 (4.0 μs) 010 (fperiph/4) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 011 (fperiph/8) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) 100 (fperiph/16) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0 μs) 000 (fperiph/1) − fc/2 (0.125 μs) fc/2 (0.5 μs) fc/27 (2.0 μs) 001 (fperiph/2) fc/22 (0.0625 μs) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 010 (fperiph/4) fc/23 (0.125 μs) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) 011 (fperiph/8) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/210 (16.0 μs) 100 (fperiph/16) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0 μs) 000 (fperiph/1) − fc/2 (0.2 μs) fc/2 (0.8 μs) fc/27 (3.2 μs) 001 (fperiph/2) − fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 010 (fperiph/4) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 011 (fperiph/8) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 100 (fperiph/16) fc/25 (0.5 μs) fc/27 (2.0 μs) fc/29 (8.0 μs) fc/211 (32.0 μs) 101 (fperiph/32) fc/2 (1.0 μs) fc/2 (4.0 μs) 000 (fperiph/1) − − fc/25 (0.8 μs) fc/27 (2.0 μs) 001 (fperiph/2) − fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) 010 (fperiph/4) − fc/2 (0.5 μs) fc/2 (2.0 μs) fc/29 (8.0 μs) 011 (fperiph/8) fc/24 (0.25 μs) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) 100 (fperiph/16) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/211 (32 μs) 101 (fperiph/32) fc/26 (1.0 μs) fc/28 (4.0 μs) fc/210 (16.0 μs) fc/212 (64.0 μs) * fs/2 (61μs) fs/23 (244 μs) fs/25 (977 μs) fs/27 (3.91 ms) 2 4 4 3 6 5 4 6 3 6 3 5 8 5 7 6 8 5 8 5 7 fc/2 10 (16.0 μs) 7 9 fc/212 (64.0 μs) Note 1: The prescaler output clock φTn must be selected so that the relationship "φTn ≤ fsys/2" is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while SIO is operating. Note 3: The "−" indicates that the setting is prohibited and the "*" indicates don’t care in the above table. Page 349 2013/5/31 12. 12.7 Serial Channel (SIO/UART) Clock Control TMPM361F10FG Table 12-5 Clock resolution to the Baud Rate Generator fc = 48 MHz, fs = 32.768kHz φT0 selection CGSYSCR Peripheral clock selection Clock gear value CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 0 (fgear) 101 (fc/4) 110 (fc/8) 2013/5/31 Prescaler clock selection Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0417 μs) fc/23 (0.167 μs) fc/25 (0.667 μs) fc/27 (2.67 μs) 001 (fperiph/2) fc/2 (0.0833 μs) fc/2 (0.333 μs) fc/2 (1.33 μs) fc/28 (5.33 μs) 010 (fperiph/4) fc/23 (0.167 μs) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) 011 (fperiph/8) fc/2 (0.333 μs) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/210 (21.3 μs) 100 (fperiph/16) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) fc/212 (85.3 μs) 000 (fperiph/1) fc/2 (0.0833 μs) fc/2 (0.333 μs) fc/2 (1.33 μs) fc/28 (5.33 μs) 001 (fperiph/2) fc/23 (0.167 μs) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) 010 (fperiph/4) fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) 011 (fperiph/8) fc/2 (0.667 μs) fc/2 (2.67 μs) fc/2 (10.7 μs) fc/211 (42.7 μs) 100 (fperiph/16) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) fc/212 (85.3 μs) 101 (fperiph/32) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) fc/213 (171 μs) 000 (fperiph/1) fc/2 (0.167 μs) fc/2 (0.667 μs) fc/2 (2.67 μs) fc/29 (10.7 μs) 001 (fperiph/2) fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) 010 (fperiph/4) fc/2 (0.667 μs) fc/2 (2.67 μs) fc/2 (10.7 μs) fc/211 (42.7 μs) 011 (fperiph/8) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) fc/212 (85.3 μs) 100 (fperiph/16) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) fc/213 (171 μs) 101 (fperiph/32) fc/2 (5.33 μs) fc/2 fc/2 (85.3μs) fc/214 (341 μs) 000 (fperiph/1) fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) 001 (fperiph/2) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) 010 (fperiph/4) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/2 (21.3 μs) fc/212 (85.3 μs) 011 (fperiph/8) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) fc/213 (171 μs) 100 (fperiph/16) fc/2 (5.33 μs) fc/2 fc/2 (85.3μs) fc/214 (341 μs) 101 (fperiph/32) fc/29 (10.7 μs) fc/211 (42.7 μs) fc/213 (171 μs) fc/215 (683 μs) 2 4 2 5 3 5 8 6 8 Page 350 4 6 4 7 5 7 10 (21.3 μs) 8 10 (21.3 μs) 6 8 6 9 7 9 12 10 12 TMPM361F10FG Table 12-5 Clock resolution to the Baud Rate Generator fc = 48 MHz, fs = 32.768kHz φT0 selection CGSYSCR Peripheral clock selection Clock gear value CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 1 (fc) 101 (fc/4) 110 (fc/8) 1 Prescaler clock selection * * Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0417 μs) fc/23 (0.167 μs) fc/25 (0.667 μs) fc/27 (2.67 μs) 001 (fperiph/2) fc/2 (0.0833 μs) fc/2 (0.333 μs) fc/2 (1.33 μs) fc/28 (5.33 μs) 010 (fperiph/4) fc/23 (0.167 μs) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) 011 (fperiph/8) fc/2 (0.333 μs) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/210 (21.3 μs) 100 (fperiph/16) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) fc/212 (85.3 μs) 000 (fperiph/1) − fc/2 (0.167 μs) fc/2 (0.667 μs) fc/27 (2.67 μs) 001 (fperiph/2) fc/22 (0.0833 μs) fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 010 (fperiph/4) fc/23 (0.167 μs) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) 011 (fperiph/8) fc/2 (0.333 μs) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/210 (21.3 μs) 100 (fperiph/16) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) fc/212 (85.3 μs) 000 (fperiph/1) − fc/2 (0.167 μs) fc/2 (0.667 μs) fc/27 (2.67 μs) 001 (fperiph/2) − fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 010 (fperiph/4) fc/2 (0.167 μs) fc/2 (0.667 μs) fc/2 (2.67 μs) fc/29 (10.7 μs) 011 (fperiph/8) fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) 100 (fperiph/16) fc/25 (0.667 μs) fc/27 (2.67 μs) fc/29 (10.7 μs) fc/211 (42.7 μs) 101 (fperiph/32) fc/2 (1.33 μs) fc/2 (5.33 μs) fc/2 (21.3 μs) fc/212 (85.3 μs) 000 (fperiph/1) − − fc/25 (0.667 μs) fc/27 (2.67 μs) 001 (fperiph/2) − fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) 010 (fperiph/4) − fc/2 (0.667 μs) fc/2 (2.67 μs) fc/29 (10.7 μs) 011 (fperiph/8) fc/24 (0.333 μs) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) 100 (fperiph/16) fc/2 (0.667 μs) fc/2 (2.67 μs) fc/2 (10.7 μs) fc/211 (42.7 μs) 101 (fperiph/32) fc/26 (1.33 μs) fc/28 (5.33 μs) fc/210 (21.3 μs) fc/212 (85.3 μs) * fs/2 (61μs) fs/23 (244 μs) fs/25 (977 μs) fs/27 (3.91 ms) 2 4 4 3 6 5 4 6 3 6 3 5 8 5 7 6 8 5 8 5 7 10 7 9 Note 1: The prescaler output clock φTn must be selected so that the relationship "φTn ≤ fsys/2" is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while SIO is operating. Note 3: The "−" indicates that the setting is prohibited and the "*" indicates don’t care in the above table. Page 351 2013/5/31 12. 12.7 Serial Channel (SIO/UART) Clock Control TMPM361F10FG Table 12-6 Clock resolution to the Baud Rate Generator fc = 32 MHz, fs = 32.768kHz φT0 selection CGSYSCR Peripheral clock selection Clock gear value CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 0 (fgear) 101 (fc/4) 110 (fc/8) 2013/5/31 Prescaler clock selection Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 001 (fperiph/2) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 010 (fperiph/4) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 011 (fperiph/8) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 100 (fperiph/16) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 101 (fperiph/32) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 000 (fperiph/1) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 001 (fperiph/2) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 010 (fperiph/4) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 011 (fperiph/8) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 100 (fperiph/16) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 101 (fperiph/32) fc/2 (8.0 μs) fc/2 fc/2 fc/214 (512.0 μs) 000 (fperiph/1) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 001 (fperiph/2) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 010 (fperiph/4) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/2 (32.0 μs) fc/212 (128.0 μs) 011 (fperiph/8) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) 100 (fperiph/16) fc/2 (8.0 μs) fc/2 fc/2 (128.0 μs) fc/214 (512.0 μs) 101 (fperiph/32) fc/29 (16.0 μs) fc/211 (64.0 μs) fc/213 (256.0 μs) fc/215 (1024 μs) 2 4 2 5 3 5 8 6 8 Page 352 4 6 4 7 5 7 10 (32.0 μs) 8 10 (32.0 μs) 6 8 6 9 7 9 12 10 12 (128.0 μs) TMPM361F10FG Table 12-6 Clock resolution to the Baud Rate Generator fc = 32 MHz, fs = 32.768kHz φT0 selection CGSYSCR Peripheral clock selection Clock gear value CGSYSCR CGSYSCR CGSYSCR 000 (fc) 100 (fc/2) 0 1 (fc) 101 (fc/4) 110 (fc/8) 1 Prescaler clock selection * * Prescaler output clock resolution φT1 φT4 φT16 φT64 000 (fperiph/1) fc/21 (0.0625 μs) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/2 (0.125 μs) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) − fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) fc/22 (0.125 μs) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/23 (0.25 μs) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/2 (0.5 μs) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) 000 (fperiph/1) − fc/2 (0.25 μs) fc/2 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) − fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) fc/2 (0.25 μs) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/25 (1.0 μs) fc/27 (4.0 μs) fc/29 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/2 (2.0 μs) fc/2 (8.0 μs) fc/2 fc/212 (128.0 μs) 000 (fperiph/1) − − fc/25 (1.0 μs) fc/27 (4.0 μs) 001 (fperiph/2) − fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) 010 (fperiph/4) − fc/2 (1.0 μs) fc/2 (4.0 μs) fc/29 (16.0 μs) 011 (fperiph/8) fc/24 (0.5 μs) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) 100 (fperiph/16) fc/2 (1.0 μs) fc/2 (4.0 μs) fc/2 (16.0 μs) fc/211 (64.0 μs) 101 (fperiph/32) fc/26 (2.0 μs) fc/28 (8.0 μs) fc/210 (32.0 μs) fc/212 (128.0 μs) * fs/2 (61μs) fs/23 (244 μs) fs/25 (977 μs) fs/27 (3.91 ms) 2 4 4 3 6 5 4 6 3 6 3 5 8 5 7 6 8 5 8 5 7 10 (32.0 μs) 7 9 Note 1: The prescaler output clock φTn must be selected so that the relationship "φTn ≤ fsys/2" is satisfied (so that φTn is slower than fsys). Note 2: Do not change the clock gear while SIO is operating. Note 3: The "−" indicates that the setting is prohibited and the "*" indicates don’t care in the above table. Page 353 2013/5/31 12. 12.7 Serial Channel (SIO/UART) Clock Control 12.7.2 TMPM361F10FG Serial Clock Generation Circuit The serial clock circuit is a block to generate transmit and receive clocks (SIOCLK) and consists of the circuits in which clocks can be selected by the settings of the baud rates generator and modes. 12.7.2.1 Baud Rate Generator The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate. (1) Buad Rate Generator input clock The input clock of the baud rate generator is selected from the prescaler outputs divided by 2, 8, 32 and 128. This input clock is selected by setting the SCxBRCR. (2) Baud Rate Generator output clock The frequency division ratio of the output clock in the baud rate generator is set by SCxBRCR and SCxBRADD. The following frequency divide ratios can be used; 1/N frequency division in the I/O interface mode, either 1/N or N + (16-K)/16 in the UART mode. The table below shows the frequency division ratio which can be selected. Mode Divide Function Setting Divide by N Divide by K SCxBRCR SCxBRCR SCxBRADD Divide by N 1 to 16 (Note) - Divide by N 1 to 16 - N + (16-K)/16 division 2 to 15 1 to 15 I/O interface UART Note:1/N (N=1)frequency division ratio can be used only when a double buffer is enabled. 12.7.2.2 Clock Selection Circuit A clock can be selected by setting the modes and the register. Modes can be specified by setting the SCxMOD0. The input clock in I/O interface mode is selected by setting SCxCR. The clock in UART mode is selected by setting SCxMOD0. (1) Transfer Clock in I/O interface mode Table 12-7 shows clock selection in I/O interface mode. 2013/5/31 Page 354 TMPM361F10FG Table 12-7 Clock selection in I/O interface Mode Input / Output Mode Clock edge selection selection SCxMOD0 SCLK output Clock of use SCxCR SCxCR Set to "0" (Fixed to the rising edge) Divided by 2 of the baud rate generator output Rising edge SCLK input rising edge Falling edge SCLK input falling edge I/O interface mode SCLK input To get the highest baud rate, the baud rate generator must be set as below. Note:When deciding clock settings, make sure that AC electrical character is satisfied. ・ Clock / mode control block settings - fc = 40MHz - fgear = 40MHz (CGSYSCR = "000" : fc selected) - φT0=40Mhz (CGSYSCR="000" : 1 division ratio) ・ SIO settings (if double buffer is used) - Clock (SCxBRCR = "00" : φT1 selected) = 20MHz - Divided clock frequency (SCxBRCR = "0001":1 division ratio) = 20MHz 1 division ratio can be selected if double buffer is used. In this case, baud rate is 10Mbps because 20MHz is divided by 2. ・ SIO settings (if double buffer is not used) - Clock (SCxBRCR = "00":φT1 selected) = 20MHz - Divided clock frequency (SCxBRCR = "0010" : 2 division ratio) = 10MHz 2 division ratio is the highest if double buffer is not used. In this case, baud rate is 5Mbps because 10MHz is divided by 2. To use SCLK input, the following conditions must be satisfied. ・ If double buffer is used - SCLK cycle > 6/fsys The highest buad rate is less than 40 ÷ 6 = 6.66 Mbps. ・ If double buffer is not used - SCLK cycle > 8/fsys The highest baud rate is less than 40 ÷ 8 = 5.0 Mbps. (2) Transfer clock in the UART mode Table 12-8 shows the clock selection in the UART mode. In the UART mode, selected clock is divided by 16 in the receive counter or the transmit counter before use. Page 355 2013/5/31 12. 12.7 Serial Channel (SIO/UART) Clock Control TMPM361F10FG Table 12-8 Clock selection in UART Mode Mode Clock selection SCxMOD0 SCxMOD0 Timer output Baud rate generator UART Mode fsys SCLK input The examples of baud rate in each clock settings. ・ If baud rate generator is used. - fc = 40MHz - fgear = 40MHz (CGSYSCR = "000" : fc selected) - φT0 = 40MHz (CGSYSCR = "000" : 1 division ratio) - Clock = φT1 = 20MHz (SCxBRCR = "00" : φT1 selected) The highest baud rate is 1.25MHz because 20MHz is divided by 16. Table 12-9 shows examples of baud rate when the baud rate generator is used with the following clock settings. ・ fc = 9.8304MHz ・ fgear = 9.8304MHz (CGSYSCR = "000" : fc selected) ・ ΦT0 = 4.9152MHz (CGSYSCR = "001" : 2 division ratio) Table 12-9 Example of UART Mode Baud Rate (Using the Baud Rate Generator) fc [MHz] 9.830400 Division ratio N φT1 φT4 φT16 φT64 (SCxBRCR) (fc/4) (fc/16) (fc/64) (fc/256) 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 8 19.200 4.800 1.200 0.300 16 9.600 2.400 0.600 0.150 Unit : kbps ・ If the SCLK input is used To use SCLK input, the following conditions must be satisfied. - SCLK cycle > 2/fsys The highest baud rate must be less than 40 ÷ 2 ÷ 16 = 1.25 Mbps. ・ If fsys is used Since the highest value of fsys is 40MHz, the highest baud rate is 40 ÷ 16 = 2.5Mbps. ・ If timer output is used To enable the timer output, the following condition must be set: a timer flip-flop output inverts when the value of the counter and that of TBxRG1 match. The SIOCLK clock frequency is "Setting value of TBxRG1 × 2". Baud rate can be obtained by using the following formula. 2013/5/31 Page 356 TMPM361F10FG Baud rate calculation Transfer rate = Clock frequency selected by CGSYSCR (TBxRG1 × 2) × 2 × 16 In the case the timer prescaler clock fT1(2 divition ratio) is selected One clock cycle is a period that the timer flip-flop is inverted twice. Table 12-10 shows the examples of baud rates when the timer output is used with the following clock settings. ・ fc = 32MHz / 9.8304MHz / 8MHz ・ fgear = 32MHz / 9.8304MHz / 8MHz (CGSYSCR = "000" :fc selected) ・ φT0 = 16MHz / 4.9152MHz / 4MHz (CGSYSCR = "001" :2 division) ・ Timer count clock = 4MHz / 1.2287MHz / 1MHz (TBxMOD = "01" :φT1 selected) Table 12-10 Example of UART Mode Baud Rate (Using the Timer Output) TBxRG setting fc 32MHz 9.8304MHz 8MHz 0x0001 250 76.8 62.5 0x0002 125 38.4 31.25 0x0003 - 25.6 - 0x0004 62.5 19.2 15.625 0x0005 50 15.36 12.5 0x0006 - 12.8 - 0x0008 31.25 9.6 - 0x000A 25 7.68 6.25 0x0010 15.625 4.8 - 0x0014 12.5 3.84 3.125 Unit : kbps Page 357 2013/5/31 12. 12.8 Serial Channel (SIO/UART) Transmit / Receive Buffer and FIFO 12.8 TMPM361F10FG Transmit / Receive Buffer and FIFO 12.8.1 Configuration Figure 12-3 shows the configuration of transmit buffer, receive buffer and FIFO. Appropriate settings are required for using buffer and FIFO. The configuration may be predefined depending on the mode. RXD Receive shift register Transmit shift register Receive buffer Transmit buffer TXD Transmit FIFO First stage Receive FIFO First stage Second stage Second stage Third stage Third stage Fourth stage Fourth stage Figure 12-3 The Configuration of Buffer and FIFO 12.8.2 Transmit / Receive Buffer Transmit buffer and receive buffer are double-buffered. The buffer configuration is specified by SCxMOD2. In the case of using a receive buffer, if SCLK input is set to generate clock output in the I/O interface mode or the UART mode is selected, it’s double buffered despite the settings. In other modes, it’s according to the settings. Table 12-11 shows correlation between modes and buffers. Table 12-11 Mode and buffer Composition SCxMOD2 Mode UART "1" Transmit Single Double Receive Double Double Transmit Single Double (SCLK input) Receive Double Double I/O interface Transmit Single Double (SCLK output) Receive Single Double I/O interface 12.8.3 "0" FIFO In addition to the double buffer function above described, 4-byte FIFO can be used. To enable FIFO, enable the double buffer by setting SCxMOD2 to "1" and SCxFCNF to "1". The FIFO buffer configuration is specified by SCxMOD1. 2013/5/31 Page 358 TMPM361F10FG Note:To use TX/RX FIFO buffer, TX/RX FIFO must be cleared after setting the SIO transfer mode (half duplex/ full duplex) and enabling FIFO (SCxFCNF = "1"). Table 12-12 shows correction between modes and FIFO. Table 12-12 Mode and FIFO Composition 12.9 SCxMOD1 RX FIFO TX FIFO Half duplex RX "01" 4byte - Half duplex TX "10" - 4byte Full duplex "11" 2byte 2byte Status Flag The SCxMOD2 register has two types of flag. This bit is significant only when the double buffer is enabled. is a flag to show that the receive buffer is full. When one frame of data is received and the data is moved from the receive shift register to the receive buffers, this bit changes to "1" while reading this bit changes it to "0". shows that the transmit buffers are empty. When data in the transmit buffers is moved to the transmit shift register, this bit is set to "1" When data is set to the transmit buffers, the bit is cleared to "0". 12.10 Error Flag Three error flags are provided in the SCxCR register. The meaning of the flags is changed depending on the modes. The table below shows the meaning in each mode. These flags are cleared to "0" after reading the SCxCR register. Mode UART Flag Overrun error Parity error Framing error Underrun error I/O interface (SCLK input) Overrun error (When using double buffer or FIFO) Fixed to "0" Fixed to "0" (When a double buffer and FIFO unused) I/O interface (SCLK output) 12.10.1 Undefined Undefined Fixed to "0" OERR Flag In both UART and I/O interface modes, this bit is set to "1" when an error is generated by completing the reception of the next frame of receive data before the receive buffer has been read. If the receive FIFO is enabled, the received data is automatically moved to the receive FIFO and no overrun error will be generated until the receive FIFO is full (or until the usable bytes are fully occupied). In the I/O interface with SCLK output mode, the SCLK output stops upon setting the flag. Page 359 2013/5/31 12. Serial Channel (SIO/UART) 12.10 Error Flag TMPM361F10FG Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the overrun flag. 12.10.2 PERR Flag This flag indicates a parity error in the UART mode and an under-run error in the I/O interface mode. In the UART mode, is set to "1" when the parity generated from the received data is different from the parity received. In the I/O interface mode, is set to "1" under the following conditions when a double buffer is enabled. In the SCLK input mode, is set to "1" when the SCLK is input after completing data output of the transmit shift register with no data in the transmit buffer. In the SCLK output mode, is set to "1" after completing output of all data and the SCLK output stops. Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the underrun flag. 12.10.3 FERR Flag A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at around the center. Regardless of the stop bit length settings in the SCxMOD2register, the stop bit status is determined by only 1. This bit is fixed to "0" in the I/O interface mode. 2013/5/31 Page 360 TMPM361F10FG 12.11 Receive 12.11.1 Receive Counter The receive counter is a 4-bit binary counter and is up-counted by SIOCLK. In the UART mode, sixteen SIOCLK clock pulses are used in receiving a single data bit and the data symbol is sampled at the seventh, eighth, and ninth pulses. From these three samples, majority logic is applied to decide the received data. 12.11.2 Receive Control Unit 12.11.2.1 I/O interface mode In the SCLK output mode with SCxCR set to "0", the RXD pin is sampled on the rising edge of the shift clock outputted to the SCLK pin. In the SCLK input mode with SCxCR set to "1", the serial receive data RXD pin is sampled on the rising or falling edge of SCLK input signal depending on the SCxCR setting. 12.11.2.2 UART Mode The receive control unit has a start bit detection circuit, which is used to initiate receive operation when a normal start bit is detected. 12.11.3 Receive Operation 12.11.3.1 Receive Buffer The received data is stored by 1 bit in the receive shift register. When a complete set of bits has been stored, the interrupt INTTRX is generated. When the double buffer is enabled, the data is moved to the receive buffer (SCxBUF) and the receive buffer full flag (SCxMOD2) is set to "1". The receive buffer full flag is "0" cleared by reading the receive buffer. The receive buffer flag does not have any value for the single buffer. Page 361 2013/5/31 12. Serial Channel (SIO/UART) 12.11 Receive TMPM361F10FG Receive shift register Receive buffer DATA 1 DATA 1 RX interrupt (INTRXx) SCxMOD2 Read Figure 12-4 Receive Buffer Operation 2013/5/31 Page 362 TMPM361F10FG 12.11.3.2 Receive FIFO Operation When FIFO is enabled, the received data is moved from receive buffer to receive FIFO and the receive buffer full flag is cleared immediately. An interrupt will be generated according to the SCxRFC setting. Note:When the data with parity bit are received in UART mode by using the FIFO, the parity error flag is shown the occurring the parity error in the received data. The configurations and operations in the half duplex RX mode are described as follows. SCxMOD1[6:5] =01 :Transfer mode is set to half duplex mode SCxFCNF[4:0] = 10111 :Automatically inhibits continuous reception after reaching the fill level. : The number of bytes to be used in the receive FIFO is the same as the interrupt generation fill level. SCxRFC[1:0] = 00 :The fill level of FIFO in which generated receive interrupt is set to 4-byte SCxRFC[7:6] = 11 :Clears receive FIFO and sets the condition of interrupt generation. After setting of the above FIFO configuration, the data reception is started by writing "1" to the SCxMOD0. When the data is stored all in the receive shift register, receive buffer and receive FIFO, SCxMOD0 is automatically cleared and the receive operations finished. In the above condition, if the cutaneous reception after reaching the fill level is enabled, it becomes possible to receive a data continuously by reading the data in the FIFO. Receive shift register Receive buffer Receive FIFO First stage Second stage DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA1 DATA2 DATA3 DATA4 DATA5 DATA1 DATA5 DATA2 DATA3 DATA4 DATA4 DATA4 DATA1 DATA2 DATA3 DATA3 DATA3 DATA1 DATA2 DATA2 DATA2 DATA1 DATA1 DATA1 Third stage Fourth stage RX interrupt (INTRXx) SCxMOD2 SCxMOD0 Figure 12-5 Receive FIFO Operation Page 363 2013/5/31 12. Serial Channel (SIO/UART) 12.11 Receive TMPM361F10FG 12.11.3.3 I/O interface mode with SCLK output In the I/O interface mode and SCLK output setting, SCLK output stops when all received data is stored in the receive buffer and FIFO. Thus, in this mode, the overrun error flag has no meaning. The timing of SCLK output stop and re-output depends on receive buffer and FIFO. (1) Case of single buffer Stop SCLK output after receiving a data. In this mode, I/O interface can transfer each data with the transfer device by hand-shake. When the data in a buffer is read, SCLK output restarts. (2) Case of double buffer Stop SCLK output after receiving the data into a receive shift register and a receive buffer. When the data is read, SCLK output restarts. (3) Case of FIFO Stop SCLK output after receiving the data into a shift register, received buffer and FIFO. When one byte data is read, the data in the received buffer is transferred into FIFO and the data in the receive shift register is transferred into the received buffer and SCLK output restarts. And if SCxFCNFis set to "1", SCLK stops and receive operation stops with clearing SCxMOD0 bit, too. 12.11.3.4 Read Received Data In spite of enabling or disabling FIFO, read the received data from the receive buffer (SCxBUF). When receive FIFO is disabled, the buffer full flag SCxMOD2 is cleared to "0" by this reading. In the case of the next data can be received in the receive shift register before reading a data from the receive buffer. The parity bit to be added in the 8-bit UART mode as well as the most significant bit in the 9-bit UART mode will be stored in SCxCR. When the receive FIFO is available, the 9-bit UART mode is prohibited because up to 8-bit data can be stored in FIFO. In the 8-bit UART mode, the parity bit is lost but parity error is determined and the result is stored in SCxCR. 12.11.3.5 Wake-up Function In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wakeup function SCxMOD0 to "1". In this case, the interrupt INTRXx will be generated only when SCxCR is set to "1". 2013/5/31 Page 364 TMPM361F10FG 12.11.3.6 Overrun Error When FIFO is disabled, the overrun error occurs and an overrun error is without completing reading data before receiving the next data. When an overrun error occurs, a content of receive buffer and SCxCR is not lost, but a content of receive shift register is lost. When FIFO is enabled, overrun error is occurred and set overrun flag by no reading the data before moving the next data into received buffer when FIFO is full. In this case, the contents of FIFO are not lost. In the I/O interface mode with SCLK output setting, the clock output automatically stops, so this flag has no meaning. Note:When the mode is changed from I/O interface SCLK output mode to the other mode, read SCxCR and clear overrun flag. Page 365 2013/5/31 12. Serial Channel (SIO/UART) 12.12 Transmission 12.12 TMPM361F10FG Transmission 12.12.1 Transmission Counter The transmit counter is a 4-bit binary counter and is counted by SIOCLK as in the case of the receive counter. In UART mode, it generates a transmit clock (TXDCLK) on every 16th clock pulse. SIOCLK 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK Figure 12-6 Generation of Transmission Clock in UART Mode 12.12.2 Transmission Control 12.12.2.1 I/O interface Mode In the SCLK output mode with SCxCR set to "0", each bit of data in the transmit buffer is outputted to the TXD pin on the falling edge of the shift clock outputted from the SCLK pin. In the SCLK input mode with SCxCR set to "1", each bit of data in the transmit buffer is outputted to the TXD pin on the rising or falling edge of the SCLK input signal according to the SCxCR setting. 12.12.2.2 UART Mode When the transmit data is written in the transmit buffer, data transmission is initiated on the rising edge of the next TXDCLK and the transmit shift clock signal is also generated. 2013/5/31 Page 366 TMPM361F10FG 12.12.3 Transmit Operation 12.12.3.1 Operation of Transmission Buffer If double buffering is disabled, the CPU writes data only to Transmit shift Buffer and the transmit interrupt INTTXx is generated upon completion of data transmission. If double buffering is enabled (including the case the transmit FIFO is enabled), data written to the transmit buffer is moved to the transmit shift register. The INTTXx interrupt is generated at the same time and the transmit buffer empty flag (SCxMOD2) is set to "1". This flag indicates that the next transmit data can be written. When the next data is written to the transmit buffer, the flag is cleared to "0". Write data DATA 1 Transmit buffer Transmit shift register DATA 2 DATA 1 TX interrupt (INTTXx) SCxMOD2 Figure 12-7 Operation of Transmission Buffer (Double buffer is enabled) 12.12.3.2 Transmit FIFO Operation When FIFO is enabled, the maximum 5-byte data can be stored using the transmit buffer and FIFO. Once transmission is enabled, data is transferred to the transmit shift register from the transmit buffer and start transmission. If data exists in the FIFO, the data is moved to the transmit buffer immediately, and the flag is cleared to "0". Note:To use TX FIFO buffer, TX FIFO must be cleared after setting the SIO transfer mode (half duplex/ full duplex) and enabling FIFO (SCxFCNF="1"). Settings and operations to transmit 4-byte data stream by setting the transfer mode to half duplex are shown as below. SCxMOD1[6:5] =10 :Transfer mode is set to half duplex. SCxFCNF[4:0] = 11011 :Transmission is automatically disabled if FIFO becomes empty. :The number of bytes to be used in the receive FIFO is the same as the interrupt :generation fill level. SCxTFC[1:0] = 00 :Sets the interrupt generation fill level to "0". SCxTFC[7:6] = 11 :Clears receive FIFO and sets the condition of interrupt generation. SCxFCNF[0] = 1 :Enable FIFO After above settings are configured, data transmission can be initiated by writing 5 bytes of data to the transmit buffer or FIFO, and setting the SCxMOD1 bit to "1". When the last transmit data is moved to the transmit buffer, the transmit FIFO interrupt is generated. When transmission of the last data is completed, the clock is stopped and the transmission sequence is terminated. Page 367 2013/5/31 12. Serial Channel (SIO/UART) 12.12 Transmission TMPM361F10FG Once above settings are configured, if the transmission is not set as auto disabled, the transmission should lasts writing transmit data. Transmit FIFO fourth stage DATA 5 Third stage DATA 4 DATA 5 Second stage DATA 3 DATA 4 DATA 5 DATA 2 DATA 3 DATA 4 DATA 5 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 1 DATA 2 DATA 3 DATA 4 First stage Transmit buffer Transmit shift register DATA 5 SCxMOD1 SCxMOD2 Transmit interrupt (INTTXx) 12.12.3.3 I/O interface Mode/Transmission by SCLK Output If SCLK is set to generate clock in the I/O interface mode, the SCLK output automatically stops when all data transmission is completed and underrun error will not occur. The timing of suspension and resume of SCLK output is different depending on the buffer and FIFO usage. (1) Single Buffer The SCLK output stops each time one frame of data is transferred. Handshaking for each data with the other side of communication can be enabled. The SCLK output resumes when the next data is written in the buffer. (2) Double Buffer The SCLK output stops upon completion of data transmission of the transmit shift register and the transmit buffer. The SCLK output resumes when the next data is written in the buffer. (3) FIFO The transmission of all data stored in the transmit shift register, transmit buffer and FIFO is completed, the SCLK output stops. The next data is written, SCLK output resumes. If SCxFCNF is configured, SCxMOD0 bit is cleared at the same time as SCLK stop and the transmission stops. 2013/5/31 Page 368 TMPM361F10FG 12.12.3.4 Underrun Error If the transmit FIFO is disabled in the I/O interface SCLK input mode and if no data is set in transmit buffer before the next frame clock input, which occurs upon completion of data transmission from transmit shift register, an under-run error occurs and SCxCR is set to "1". In the I/O interface mode with SCLK output setting, the clock output automatically stops, so this flag has no meaning/ Note:Before switching the I/O interface SCLK output mode to other modes, read the SCxCR register and clear the underrun flag. Page 369 2013/5/31 12. Serial Channel (SIO/UART) 12.13 Handshake Function 12.13 TMPM361F10FG Handshake Function The function of the handshake is to enable frame-by-frame data transmission by using the CTS (Clear to send) pin and to prevent overrun errors. This function can be enabled or disabled by SCxMOD0. When the CTS pin is set to "High" level, the current data transmission can be completed but the next data transmission is suspended until CTS pin returns to the "Low" level. However in this case, the INTTXx interrupt is generated in the normal timing, the next transmit data is written in the transmit buffer, and it waits until it is ready to transmit data. Note 1: If the CTS signal is set to "High" during transmission, the next data transmission is suspended after the current transmission is completed. Note 2: Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to "Low". Although no RTS pin is provided, a handshake control function can easily implemented by assigning one bit of the port for the RTS function. By setting the port to "High" level upon completion of data reception (in the receive interrupt routine), the transmit side can be requested to suspend data transmission. TXD RXD CTS RTS (Any port) Transmit side Receive side Figure 12-8 Handshake Function Data write to transmit buffer or shift register CTS Transmission is suspended during b this period. a 13 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TXDCLK Start bit TXD Figure 12-9 CTS Signal timing 2013/5/31 Page 370 Bit 0 TMPM361F10FG 12.14 Interrupt / Error Generation Timing 12.14.1 RX Interrupt Figure 12-10 shows the data flow of receive operation and the route of read. RXD Receive shift register (1)Reading in the single buffer configuration : An interrupt is generated after receiving all bits. If the receive buffer is emply, the data is moved. Receive buffer (2)Reading in the doule buffer configuration : An interrupt is generated when the data is moved to the receive buffer. If the RX FIFO is not full, the data is moved. Receive FIFO First stage second stage Third stage (3)Reading in use the FIFO : An interrupt is generated When the data is moved to the FIFO or when reading the FIFO. Fourth stage Figure 12-10 Receive Buffer / FIFO Configuration Diagram 12.14.1.1 Single Buffer / Double Buffer RX interrupts are generated at the time depends on the transfer mode and the buffer configurations, which are given follows. UART modes Buffer Configuration I/O interface modes Immediately after the raising / falling edge of the last SCLK Single Buffer − Double Buffer Around the center of the first stop bit (Rising or falling is determined according to SCxCR setting.) Immediately after the raising / falling edge of the last SCLK (Rising or falling is determined according to SCxCR setting.) On data transfer from the shift register to the buffer by reading buffer. Note:Interrupts are not generated when an overrun error occurs. 12.14.1.2 FIFO In use of FIFO, receive interrupt is generated on the condition that the following either operation and SCxRFC setting are established. ・ Reception completion of all bits of one frame ・ Reading FIFO Interrupt conditions are decided by the SCxRFC settings as described in Table 12-13. Table 12-13 Receive Interrupt Conditions in use of FIFO SCxRFC Interrupt conditions "0" "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation." "1" "The fill level of FIFO" is greater than or equal to "the fill level of FIFO interruption generation." Page 371 2013/5/31 12. Serial Channel (SIO/UART) 12.14 Interrupt / Error Generation Timing 12.14.2 TMPM361F10FG TX interrupt Figure 12-11 shows the data flow of transmit operation and the route of read. TXD Transmit shift register (1)Writing in the single buffer configuration : An interrupt is generated after transmitting all bits. If the shift register is empty, the data is moved. Transmit buffer (2)Writing in the double buffer configuration : An interrupt is generated when the data is moved to the transmit shift register. If the transmit buffer is empty, the data is moved. TX FIFO First stage Second stage Third stage (3)Writing in use the FIFO : An interrupt is generated When the data is moved to the transmit buffer or when wrting to the FIFO. Fourth stage Figure 12-11 Transmit Buffer / FIFO Configuration Diagram 12.14.2.1 Single Buffer / Double Buffer TX interrupts are generated at the time depends on the transfer mode and the buffer configurations, which are given as follows. Buffer Configuration UART modes I/O interface modes Immediately after the raising / falling edge of the last SCLK Single Buffer Just before the stop bit is sent Double Buffer When a data is moved from the transmit buffet to the transmit shift register. (Rising or falling is determined according to SCxCR setting.) Note:If double buffer is enabled, a interrupt is also generated when the data is moved from the buffer to the shift register by writing to the buffer. 12.14.2.2 FIFO In use of FIFO, transmit interrupt is generated on the condition that the following either operation and SCxTFC setting are established. ・ Transmission completion of all bits of one frame. ・ Writing FIFO Interrupt conditions are decided by the SCxTFC settings as described in Table 12-14. Table 12-14 Transmit Interrupt conditions in use of FIFO 2013/5/31 SCxTFC Interrupt condition "0" "The fill level of FIFO" is equal to "the fill level of FIFO interruption generation." "1" "The fill level of FIFO" is smaller than or equal to "the fill level of FIFO interruption generation." Page 372 TMPM361F10FG 12.14.3 Error Generation 12.14.3.1 UART Mode 7 bits Modes 9 bits 8 bits 7 bits + parity 8bits + parity Framing error Around the center of stop bit Overrun error Parity Error 12.14.3.2 − Around center of parity bit I/O Interface Mode Overrun error Underrun error Immediately after the raising / falling edge of the last SCLK (Rising or falling is determined according to SCxCR setting.) Immediately after the rising or falling edge of the next SCLK. (Rising or falling is determined according to SCxCR setting.) Note:Over-run error and Under-run error have no meaning in SCLK output mode. 12.15 Software Reset Software reset is generated by writing SCxMOD2 as "10" followed by "01". As a result, SCxMOD0, SCxMOD1, SCxMOD2, SCxCR are initialized. And the receive circuit, the transmit circuit and the FIFO become initial state. Other states are maintained. Page 373 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode 12.16 TMPM361F10FG Operation in Each Mode 12.16.1 Mode 0 (I/O Interface Mode) Mode 0 consists of two modes, the SCLK output mode to output synchronous clock and the SCLK input mode to accept synchronous clock from an external source. The following operational descriptions are for the case use of FIFO is disabled. For details of FIFO operation, refer to the previous sections describing receive/transmit FIFO functions. 12.16.1.1 Transmitting Data (1) SCLK Output Mode ・ If the transmit double buffer is disabled (SCxMOD2 = "0") Data is output from the TXD pin and the clock is output from the SCLK pin each time the CPU writes data to the transmit buffer. When all data is output, an interrupt (INTTXx) is generated. ・ If the transmit double buffer is enabled (SCxMOD2 = "1") Data is moved from the transmit buffer to the transmit shift register when the CPU writes data to the transmit buffer while data transmission is halted or when data transmission from the transmit buffer (shift register) is completed. Simultaneously, the transmit buffer empty flag SCxMOD2 is set to "1", and the INTTXx interrupt is generated. When data is moved from the transmit buffer to the transmit shift register, if the transmit buffer has no data to be moved to the transmit shift register, INTTXx interrupt is not generated and the SCLK output stops. 2013/5/31 Page 374 TMPM361F10FG Transmit data write timing SCLK output TXD bit 0 bit 1 bit 6 bit 7 bit 0 (INTTXx interrupt request) = "0" (if double buffering is disabled) Transmit data write timing SCLK output TXD bit 0 bit 1 bit 6 bit 7 bit 0 (INTTXx interrupt request) TBEMP = "1" (If double buffering is enabled and there is data in buffer) Transmit data write timing SCLK output TXD bit 0 bit 1 bit 6 bit 7 (INTTXx interrupt request) TBEMP = "1" (if double buffering is enabled and there is no data in buffer) Figure 12-12 Transmit Operation in the I/O Interface Mode (SCLK Output Mode) Page 375 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode (2) TMPM361F10FG SCLK Input Mode ・ If double buffering is disabled (SCxMOD2 = "0") If the SCLK is input in the condition where data is written in the transmit buffer, 8-bit data is outputted from the TXD pin. When all data is output, an interrupt INTTXx is generated. The next transmit data must be written before the timing point "A" as shown in Figure 12-13. ・ If double buffer is enabled (SCxMOD2 = "1") Data is moved from the transmit buffer to the transmit shift register when the CPU writes data to the transmit buffer before the SCLK input becomes active or when data transmission from the transmit shift register is completed. Simultaneously, the transmit buffer empty flag SCxMOD2 is set to "1", and the INTTXx interrupt is generated. If the SCLK input becomes active while no data is in the transmit buffer, although the internal bit counter is started, an under-run error occurs and 8-bit dummy data (0xFF) is sent. 2013/5/31 Page 376 TMPM361F10FG A Transmit data write timing SCLK input (=0 Rising edge mode) SCLK input (=1 Falling edge mode) TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 bit 0 bit 1 (INTTXx interrupt request) = "0" (if double buffering is disabled) A Transmit data write timing SCLK input (=0 Rising edge mode) SCLK input (=1 Falling edge mode) TXD bit 0 bit 1 bit 5 bit 6 bit 7 (INTTXx interrupt request) TBEMP = "1" (if double beffering is enabled and there is data in beffer2) A Transmit data write timing SCLK input (=0 Rising edge mode) SCLK input (=1 Falling edge mode) TXD bit 0 bit 1 bit 5 bit 6 bit 7 1 1 (INTTXx interrupt request) TBEMP PERR (Function to detect underrun error) = "1" (if double buffering is enabled and there is no data in buffer2) Figure 12-13 Transmit Operation in the I/O Interface Mode (SCLK Input Mode) Page 377 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode 12.16.1.2 TMPM361F10FG Receive (1) SCLK Output Mode The SCLK output can be started by setting the receive enable bit SCxMOD0 to "1". ・ If double buffer is disabled (SCxMOD2 = "0") A clock pulse is outputted from the SCLK pin and the next data is stored into the shift register each time the CPU reads received data. When all the 8 bits are received, the INTRXx interrupt is generated. ・ If double buffer is enabled (SCxMOD2 = "1") Data stored in the shift register is moved to the receive buffer and the receive buffer can receive the next frame. A data is moved from the shift register to the receive buffer, the receive buffer full flag SCxMOD2 is set to "1" and the INTRXx is generated. While data is in the receive buffer, if the data cannot be read from the receive buffer before completing reception of the next 8 bits, the INTRXx interrupt is not generated and the SCLK output stops. In this state, reading data from the receive buffer allows data in the shift register to move to the receive buffer and thus the INTRXx interrupt is generated and data reception resumes. 2013/5/31 Page 378 TMPM361F10FG Receive data read timing SCLK output bit 0 RXD bit 1 bit 7 bit 6 bit 0 (INTRX interrupt request) = "0" (if double buffering is disabled) Receive data read timing SCLK output RXD bit 7 bit 0 bit 1 bit 6 bit 7 bit 0 (INTRX interrupt request) RBFLL = "1" (if double buffering is enabled and data is read from buffer) Receive data read timing SCLK output RXD bit 7 bit 0 bit 1 bit 6 bit 7 (INTRX interrupt request) RBFLL = "1" (if double beffering is enabled and data con not be read from beffer) Figure 12-14 Receive Operation in the I/O Interface Mode (SCLK Output Mode) Page 379 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode TMPM361F10FG (2) SCLK Input Mode In the SCLK input mode, receiving double buffering is always enabled, the received frame can be moved to the receive buffer from the shift register, and the receive buffer can receive the next frame successively. The INTRXx receive interrupt is generated each time received data is moved to the receive buffer. Receive data read timing SCLK input (=”0” Rising mode) SCLK input (=”1” falling mode) RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 6 bit 7 bit 0 (INTRXx interrupt request) RBFLL If data is read from buffer Receive data read timing SCLK input (=”0” Rising mode) SCLK input (=”1” falling mode) RXD bit 0 bit 1 bit 5 (INTRXx interrupt request) RBFLL OERR If data can not be read from buffer Figure 12-15 Receive Operation in the I/O Interface Mode (SCLK Input Mode) 2013/5/31 Page 380 TMPM361F10FG 12.16.1.3 Transmit and Receive (Full duplex) (1) SCLK Output Mode ・ If SCxMOD2 is set to "0" and the double buffers are disabled SCLK is outputted when the CPU writes data to the transmit buffer. Subsequently, 8 bits of data are shifted into receive buffer and the INTRXx receive interrupt is generated. Concurrently, 8 bits of data written to the transmit buffer are outputted from the TXD pin, the INTTXx transmit interrupt is generated when transmission of all data bits has been completed. Then, the SCLK output stops. The next round of data transmission and reception starts when the data is read from the receive buffer and the next transmit data is written to the transmit buffer by the CPU. The order of reading the receive buffer and writing to the transmit buffer can be freely determined. Data transmission is resumed only when both conditions are satisfied. ・ If SCxMOD2 is set to "1" and the double buffers are enabled SCLK is outputted when the CPU writes data to the transmit buffer. 8 bits of data are shifted into the receive shift register, moved to the receive buffer, and the INTRXx interrupt is generated. While 8 bits of data is received, 8 bits of transmit data is outputted from the TXD pin. When all data bits are sent out, the INTTXx interrupt is generated and the next data is moved from the transmit buffer to the transmit shift register. If the transmit buffer has no data to be moved to the transmit buffer (SCxMOD2 = 1) or when the receive buffer is full (SCxMOD2 = 1), the SCLK output is stopped. When both conditions, receive data is read and transmit data is written, are satisfied, the SCLK output is resumed and the next round of data transmission and reception is started. Page 381 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode TMPM361F10FG Receive data read timing Transmit data write timing SCLK output TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "0" (if double beffering is disabled) Receive data read timing Transmit data write timing SCLK output TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "1" (if double buffering is enabled) Receive data read timing Transmit data write timing SCLK output TXD bit 0 bit 1 bit 5 bit 6 bit 7 RXD bit 0 bit 1 bit 5 bit 6 bit 7 (INTTXx interrupt request) (INTRXx interrupt request) = "1" (if double buffering is enabled) Figure 12-16 Transmit / Receive Operation in the I/O Interface Mode (SCLK Output Mode) 2013/5/31 Page 382 TMPM361F10FG (2) SCLK Input Mode ・ If SCxMOD2 is set to "0" and the transmit double buffer is disabled When receiving data, double buffer is always enabled regardless of the SCxMOD2 settings. 8-bit data written in the transmit buffer is outputted from the TXD pin and 8 bit of data is shifted into the receive buffer when the SCLK input becomes active.The INTTXx interrupt is generated upon completion of data transmission. The INTTRXx interrupt is generated when the data is moved from shift register to receive buffer after completion of data reception. Note that transmit data must be written into the transmit buffer before the SCLK input for the next frame (data must be written before the point A in Figure 10-17). Data must be read before completing reception of the next frame data. ・ If SCxMOD2 is set to "1" and the double buffer is enabled. The interrupt INTRXx is generated at the timing the transmit buffer data is moved to the transmit shift register after completing data transmission from the transmit shift register. At the same time, data received is shifted to the shift register, it is moved to the receive buffer, and the INTRXx interrupt is generated. Note that transmit data must be written into the transmit buffer before the SCLK input for the next frame (data must be written before the point A in Figure 12-17). Data must be read before completing reception of the next frame data. Upon the SCLK input for the next frame, transmission from transmit shift register (in which data has been moved from transmit buffer) is started while receive data is shifted into receive shift register simultaneously. If data in receive buffer has not been read when the last bit of the frame is received, an overrun error occurs. Similarly, if there is no data written to transmit buffer when SCLK for the next frame is input, an under-run error occurs. Page 383 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode TMPM361F10FG Receive data read timing A Transmit data write timign SCLK input TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "0" (if double buffering is disabled) Receive data read timing A Transmit data write timign SCLK input TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) = "1" (if double buffering is enabled with no errors) Receive data read timing A Transmit data write timign SCLK input TXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 RXD bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 (INTTXx interrupt request) (INTRXx interrupt request) PERR (Underrun error) = "1" (if double buffering is enabled with error generation) Figure 12-17 Transmit / Receive Operation in the I/O Interface Mode (SCLK Input Mode) 2013/5/31 Page 384 TMPM361F10FG 12.16.2 Mode 1 (7-bit UART Mode) The 7-bit UART mode can be selected by setting the serial mode control register (SCxMOD) to "01". In this mode, parity bits can be added to the transmit data stream; the serial mode control register (SCxCR) controls the parity enable/disable setting. When is set to "1" (enable), either even or odd parity may be selected using the SCxCR bit. The length of the stop bit can be specified using SCxMOD2. The following table shows the control register settings for transmitting in the following data format. start bit 0 1 2 3 4 5 6 even parity stop 7UDQVPLVVLRQGLUHFWLRQ7UDQVPLVVLRQUDWHRI bps @fc = 9.8304 MHz) Clocking condition SCxMOD0 System clock : High-speed (fc) High-speed clock gear : x1 (fx) Prescaler clock : fperiph/2 (fperiph = fsys) ← 7 6 5 4 3 2 1 0 x 0 - 0 0 1 0 1 Set 7-bit UART mode SCxCR ← x 1 1 x x x 0 0 Even parity enabled SCxBRCR ← 0 0 1 0 0 1 0 0 Set 2400bps SCxBUF ← * * * * * * * * Set transmit data x : don’t care - : no change 12.16.3 Mode 2 (8-bit UART Mode) The 8-bit UART mode can be selected by setting SCxMOD0 to "10". In this mode, parity bits can be added and parity enable/disable is controlled using SCxCR. If = "1" (enabled), either even or odd parity can be selected using SCxCR. The control register settings for receiving data in the following format are as follows : start bit 0 1 2 3 4 5 6 7 odd parity stop 7UDQVPLVVLRQGLUHFWLRQ (Transmission rate of 9600 bps @fc = 9.8304 MHz) Clocking condition System clock : High-speed (fc) High-speed clock gear : x1 (fc) Prescaler clock : fperiph/2 (fperiph = fsys) Page 385 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode TMPM361F10FG SCxMOD0 ← 7 6 5 4 3 2 1 0 x 0 0 0 1 0 0 1 Set 8-bit UART mode SCxCR ← x 0 1 x x x 0 0 Odd parity enabled SCxBRCR ← 0 0 0 1 0 1 0 0 Set 9600bps SCxMOD0 ← - - 1 - - - - - Reception enabled x : don’t care - : no change 12.16.4 Mode 3 (9-bit UART Mode) The 9-bit UART mode can be selected by setting SCxMOD0 to "11". In this mode, parity bits must be disabled (SCxCR = "0"). The most significant bit (9th bit) is written to bit 7 of the serial mode control register 0 (SCxMOD0) for transmitting data. The data is stored in bit 7 of the serial control register SCxCR. When writing or reading data to/from the buffers, the most significant bit must be written or read first before writing or reading to/from SCxBUF. The stop bit length can be specified using SCxMOD2. 12.16.4.1 Wake-up Function In the 9-bit UART mode, slave controllers can be operated in the wake-up mode by setting the wakeup function control bit SCxMOD0 to "1". In this case, the interrupt INTRXx will be generated only when SCxCR is set to "1". Note:The TXD pin of the slave controller must be set to the open drain output mode using the ODE register. TXD RXD Master TXD RXD TXD Slave1 RXD Slave2 TXD RXD Slave3 Figure 12-18 Serial Links to Use Wake-up Function 2013/5/31 Page 386 TMPM361F10FG 12.16.4.2 Protocol 1. Select the 9-bit UART mode for the master and slave controllers. 2. Set SCxMOD to "1" for the slave controllers to make them ready to receive data. 3. The master controller is to transmit a single frame of data that includes the slave controller select code (8 bits). In this, the most significant bit (bit 8) must be set to "1". start bit 0 1 2 3 4 5 6 7 8 stop "1" Select cide of the slave controller 4. Each slave controller receives the above data frame; if the code received matches with the controller’s own select code, it clears the bit to "0". 5. The master controller transmits data to the designated slave controller (the controller of which SCxMOD bit is cleared to "0"). In this, the most significant bit (bit 8) must be set to "0". start bit 0 1 2 3 4 5 6 7 bit 8 stop "0" Data 6. The slave controllers with the bit set to "1" ignore the receive data because the most significant bit (bit 8) is set to "0" and thus no interrupt (INTRXx) is generated.Also, the slave controller with the bit set to "0" can transmit data to the master controller to inform that the data has been successfully received. Page 387 2013/5/31 12. Serial Channel (SIO/UART) 12.16 Operation in Each Mode 2013/5/31 TMPM361F10FG Page 388 TMPM361F10FG 13. Synchronous Serial Port (SSP) 13.1 Overview This LSI contains the SSP (Synchronous Serial Port) with 1 channel. This channel has the following features. Three types of synchronous serial ports including the SPI Communication protocol ・ Motorola SPI (SPI) frame format ・ TI synchronous (SSI) frame format ・ National Microwire (Microwire) frame format Operation mode Master/slave mode Transmit FIFO 16bits wide / 8 tiers deep Receive FIFO 16bits wide / 8 tiers deep Transmitted/received data size 4 to 16 bits Transmit interrupt Interrupt type Receive interrupt Receive overrun interrupt Time-out interrupt Communication speed In master mode fsys (64MHz)/ 4 (max. 16Mbps) In slave mode fsys (64MHz)/ 12 (max. 5.3Mbps) DMA Internal test function Control pin Supported The internal loopback test mode is available. SPCLK,SPFSS,SPDO,SPDI Page 389 2013/5/31 13. 13.2 Synchronous Serial Port (SSP) Block Diagram 13.2 TMPM361F10FG Block Diagram SSP SSPCLKDIV Clock prescaler fsys Tx/Rx param Write data [15:0] 㸿㹎㹀 AHB interface and register Read data [15:0] SP reception (DMA clear) SP transmission (DMA clear) SP reception (DMA request: single) SP reception (DMA request: burst) SP transmission (DMA request: single㸧 SP 16bit㹖8 Transmit FIFO SPDI TXD[15:0] Transmission/ reception logic RXD[15:0] 16bit㹖8 Receive FIFO Reception buffer processing request Timeout Overrun DMA transfer request transmission (DMA request: burst) INTSSP Interrupt request Figure 13-1 SSP block diagram 2013/5/31 SPFSS Transmission buffer processing request DMA interface Page 390 SPDO SPCLK FIFO status and interrupt generation TMPM361F10FG 13.3 Register 13.3.1 Register List Base Address = 0x4004_0000 Register Name Address (Base+) Control register 0 SSPCR0 0x0000 Control register 1 SSPCR1 0x0004 Receive FIFO (read) and transmit FIFO (write) data register SSPDR 0x0008 Status register SSPSR 0x000C Clock prescale register SSPCPSR 0x0010 Interrupt enable/disable register SSPIMSC 0x0014 Pre-enable interrupt status register SSPRIS 0x0018 Post-enable interrupt status register SSPMIS 0x001C Interrupt clear register SSPICR 0x0020 DMA control register Reserved SSPDMACR 0x0024 - 0x0028 to 0x0FFC Note 1: These registers in the above table allows to access only word (32 bits) basis. Note 2: Access to the "Reserved" area is prohibited. Page 391 2013/5/31 13. 13.3 Synchronous Serial Port (SSP) Register TMPM361F10FG 13.3.2 SSPCR0(Control register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 After Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SPH SPO After Reset 0 0 0 0 bit symbol Bit SCR Bit Symbol FRF DSS 0 0 0 Type 0 Function 31-16 − W Write as "0". 15-8 SCR[7:0] R/W For serial clock rate setting. Parameter : 0x00 to 0xFF. Bits to generate the SSP transmit bit rate and receive bit rate. This bit rate can be obtained by the following equation. Bit rate = fsys / ( × (1+ )) is an even number between 2 to 254, which is programmed by the SSPCPSR register, and takes a value between 0 to 255. 7 SPH R/W SPCLK phase: 0 : Captures data at the 1st clock edge. 1 : Captures data at the 2nd clock edge. This is applicable to Motorola SPI frame format only. Refer to Section "Motorola SPI frame format" 6 SPO R/W SPCLK polarity: 0:SPCLK is in Low state. 1:SPCLK is in High state. This is applicable to Motorola SPI frame format only. Refer to Section "Motorola SPI frame format" 5-4 FRF[1:0] R/W Frame format: 00: SPI frame format 01: SSI serial frame format 10: Microwire frame format 11: Reserved, undefined operation 3-0 DSS[3:0] R/W Data size select: 0000: Reserved, undefined operation 1000: 9 bits data 0001: Reserved, undefined operation 1001: 10 bits data 0010: Reserved, undefined operation 1010: 11 bits data 0011: 4 bits data 1011: 12 bits data 0100: 5 bits data 1100: 13 bits data 0101: 6 bits data 1101: 14 bits data 0110: 7 bits data 1110: 15 bits data 0111: 8 bits data 1111: 16 bits data Note:Set a clock prescaler to SSPCR0 = 0x00 , SSPCPSR = 0x02, when slave mode is selected. 2013/5/31 Page 392 TMPM361F10FG 13.3.3 SSPCR1(Control register1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - SOD MS SSE LBM After Reset Undefined Undefined Undefined Undefined 0 0 0 0 Bit Bit Symbol Type Function 31-4 − W Write as "0". 3 SOD R/W Slave mode SPDO output control: 0: Enable 1: Disable Slave mode output disable. This bit is relevant only in the slave mode (="1"). 2 MS R/W Master/slave mode select: (Note) 0: Device configured as a master. 1: Device configured as a slave. 1 SSE R/W SSP enable/disable 0: Disable 1: Enable 0 LBM R/W Loop back mode 0: Normal serial port operation enabled. 1: Output of transmit serial shifter is connected to input of receive serial shifter internally. Note:This bit is for switching between master and slave. Be sure to configure in the following steps in slave mode and in transmission. 1) Set to slave mode :=1 2) Set transmit data in FIFO :=0x**** 3) Set SSP to Enable. :=1 Page 393 2013/5/31 13. 13.3 Synchronous Serial Port (SSP) Register TMPM361F10FG 13.3.4 SSPDR(Data register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After Reset DATA bit symbol After Reset Bit DATA 0 Bit Symbol 0 0 0 Type Function 31-16 − W Write as "0". 15-0 DATA[15:0] R/W Transmit/receive FIFO data: 0x0000 to 0xFFFF Read: Receive FIFO Write: Transmit FIFO If the data size used in the program is less than 16bits, write the data to fit LSB.The transmit control circuit ignores unused bits of MSB side. The receive control circuit receives the data to fit LSB automatically. 2013/5/31 Page 394 TMPM361F10FG 13.3.5 SSPSR(Status register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - BSY RFF RNE TNF TFE After Reset Undefined Undefined Undefined 0 0 0 1 1 Bit Bit Symbol Type Function 31-5 − W Write as "0". 4 BSY R Busy flag: 0: Idle 1: Busy ="1" indicates that the SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. 3 RFF R Receive FIFO full flag: 0: Receive FIFO is not full. 1: Receive FIFO is full. 2 RNE R Receive FIFO empty flag: 0: Receive FIFO is empty. 1: Receive FIFO is not empty. 1 TNF R Transmit FIFO full flag: 0: Transmit FIFO is full. 1: Transmit FIFO is not full. 0 TFE R Transmit FIFO empty flag: 0: Transmit FIFO is not empty. 1: Transmit FIFO is empty. Page 395 2013/5/31 13. 13.3 Synchronous Serial Port (SSP) Register TMPM361F10FG 13.3.6 SSPCPSR (Clock prescale register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After Reset Bit CPSDVSR 0 Bit Symbol 0 0 0 Type Function 31-8 − W Write as "0". 7-0 CPSDVSR[7:0] R/W Clock prescale divisor: Set an even number from 2 to 254. Clock prescale divisor: Must be an even number from 2 to 254, depending on the frequency of fsys. The least significant bit always returns zero when read. Note:Set a clock prescaler to SSPCR0 = 0x00 , SSPCPSR = 0x02, when slave mode is selected. 2013/5/31 Page 396 TMPM361F10FG 13.3.7 SSPIMSC (Interrupt enable/disable register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - TXIM RXIM RTIM RORIM After Reset Undefined Undefined Undefined Undefined 0 0 0 0 Bit Bit Symbol Type Function 31-4 − W Write as "0". 3 TXIM R/W Transmit FIFO interrupt enable: 0: Disable 1: Enable Enable or disable a conditional interrupt to occur if the transmit FIFO is half empty or less. 2 RXIM R/W Receive FIFO interrupt enable: 0: Disable 1: Enable Enable or disable a conditional interrupt to occur if the receive FIFO is half full or less. 1 RTIM R/W Receive time-out interrupt enable: 0: Disable 1: Enable Enable or disable a conditional interrupt to indicate that data exists in the receive FIFO to the time-out period and data is not read. 0 RORIM R/W Receive overrun interrupt enable: 0: Disable 1: Enable Enable or disable a conditional interrupt to indicate that data was written when the receive FIFO was in the full condition. Page 397 2013/5/31 13. 13.3 Synchronous Serial Port (SSP) Register TMPM361F10FG 13.3.8 SSPRIS (Pre-enable interrupt status register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - TXRIS RXRIS RTRIS RORRIS After Reset Undefined Undefined Undefined Undefined 1 0 0 0 Bit Bit Symbol Type Function 31-4 − W Write as "0". 3 TXRIS R Pre-enable transmit interrupt flag: 0: Interrupt not present 1: Interrupt present 2 RXRIS R Pre-enable receive interrupt flag: 0: Interrupt not present 1: Interrupt present 1 RTRIS R Pre-enable timeout interrupt flag: 0: Interrupt not present 1: Interrupt present 0 RORRIS R Pre-enable overrun interrupt flag: 0: Interrupt not present 1: Interrupt present 2013/5/31 Page 398 TMPM361F10FG 13.3.9 SSPMIS (Post-enable interrupt status register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - TXMIS RXMIS RTMIS RORMIS After Reset Undefined Undefined Undefined Undefined 0 0 0 0 Bit Bit Symbol Type Function 31-4 − W Write as "0". 3 TXMIS R Post-enable transmit interrupt flag: 0: Interrupt not present 1: Interrupt present 2 RXMIS R Post-enable receive interrupt flag: 0: Interrupt not present 1: Interrupt present 1 RTMIS R Post-enable time-out interrupt flag: 0: Interrupt not present 1: Interrupt present 0 RORMIS R Post-enable overrun interrupt flag: 0: Interrupt not present 1: Interrupt present Page 399 2013/5/31 13. 13.3 Synchronous Serial Port (SSP) Register TMPM361F10FG 13.3.10 SSPICR (Interrupt clear register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - RTIC RORIC After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Bit Bit Symbol Type Function 31-2 − W Write as "0". 1 RTIC W Clear the time-out interrupt flag: 0: Invalid 1: Clear 0 RORIC W Clear the overrun interrupt flag: 0: Invalid 1: Clear 13.3.11 SSPxDMACR (DMA control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit symbol - - - - - - TXDMAE RXDMAE After Reset Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Bit Bit Symbol Type Function 31-2 − W Write as "0". 1 TXDMAE R/W Transmit FIFO DMA control: 0:Disable 1:Enable 0 RXDMAE R/W Transmit FIFO DMA control: 0:Disable 1:Enable 2013/5/31 Page 400 TMPM361F10FG 13.4 Overview of SSP This LSI contains the SSP with 1channels. The SSP is an interface that enables serial communications with the peripheral devices with three types of synchronous serial interface functions. The SSP performs serial-parallel conversion of the data received from a peripheral device. The transmit buffers data in the independent 16-bit wide and 8-layered transmit FIFO in the transmit mode, and the receive buffers data in the 16-bit wide and 8-layered receive FIFO in receive mode. Serial data is transmitted via SPDO and received via SPDI. The SSP contains a programmable prescaler to generate the serial output clock SPCLK from the input clock fsys. The operation mode, frame format, and data size of the SSP are programmed in the control registers SSPCR0 and SSPCR1. 13.4.1 Clock prescaler When configured as a master, a clock prescaler comprising two free-running serially linked counters is used to provide the serial output clock SPCLK. You can program the clock prescaler through the SSPCPSR register, to divide fsys by a factor of 2 to 254 in steps of two. Because the least significant bit of the SSPCPSR register is not used, division by an odd number is not possible. The output of the prescaler is further divided by a factor of 1 to 256, which is obtained by adding 1 to the value programmed in the SSPCR0 register, to give the master output clock SPCLK. Bitrate = fsys / (×(1+)) fsys Clock prescaler SSPCLKDIV Divider circuit 1+ Clock invert trigger Clock initial value (Depends on the setting) 13.4.2 Toggle circuit SPCLK Transmit FIFO This is a 16-bit wide, 8-layered transmit FIFO buffer, which is shared in master and slave modes. 13.4.3 Receive FIFO This is a 16-bit wide 8-layered receive FIFO buffer, which is shared in master and slave modes. Page 401 2013/5/31 13. 13.4 Synchronous Serial Port (SSP) Overview of SSP 13.4.4 TMPM361F10FG Interrupt generation logic The interrupts, each of which can be masked separately, are generated. Transmit interrupt A conditional interrupt to occur when the transmit FIFO has free space more than (including half) of the entire capacity. (Number of valid data items in the transmit FIFO ≤ 4) Receive interrupt A conditional interrupt to occur when the receive FIFO has valid data more than half (including half) the entire capacity. (Number of valid data items in the receive FIFO ≥ 4) Time-out interrupt A conditional interrupt to indicate that the data exists in the receive FIFO to the time-out period. Overrun interrupt Conditional interrupts indicating that data is written to receive FIFO when it is full. Also, The individual masked sources are combined into a single interrupt. When any of the above interrupts is asserted, the combined interrupt INTSSP is asserted. Pre-enable transmit interrupt Post-enable transmit interrupt TXIM㸦mask㸧 Pre-enable receive interrupt Post-enable receive interrupt RXIM(mask㸧 Pre-enable timeout interrupt RTM(mask㸧 Pre-enable receive overrun interrupt INTSSP Post-enable receive timeout interrupt Post-enable receive overrun interrupt RORIM(mask㸧 a. Transmit interrupt The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO. The transmit interrupt is also generated when the SSP operation is disabled (SSPCR1 = "0"). The first transmitted data can be written in the FIFO by using this interrupt. b. Receive interrupt The receive interrupt is asserted when there are four or more valid entries in the receive FIFO. c. Time-out interrupt The time-out interrupt is asserted when the receive FIFO is not empty and the SSP has remained idle for a fixed 32-bit period (bit rate). This mechanism ensures that the user is aware that data is still present in the receive FIFO and requires servicing. This operation occurs in both master and slave modes. When the time-out interrupt is generated, read all data from the receive FIFO. Even if all the data is not read, data can be transmitted / received if the receive FIFO has a free space and the number of data to be transmitted does not exceed the free space of the receive FIFO. When transfer starts, the timeout interrupt will be cleared. If data is transmitted / received when the receive FIFO has no free space, the time-out interrupt will not be cleared and an overrun interrupt will be generated. 2013/5/31 Page 402 TMPM361F10FG SPCLK Receive FIFO empty flag SSPSR During data transfer Internal down counter enable bit rate Receive timeout interrupt enable SSPIMSC Receive timeout interrupt SSPMIS Page 403 2013/5/31 13. 13.4 Synchronous Serial Port (SSP) Overview of SSP TMPM361F10FG d. Overrun interrupt When the next data (9th data item) is received when the receive FIFO is already full, an overrun interrupt is generated immediately after transfer. The data received after the overrun interrupt is generated (including the 9th data item) will become invalid and be discarded. However, if data is read from the receive FIFO while the 9th data item is being received (before the interrupt is generated), the 9th received data will be written in the receive FIFO as valid data. To perform transfer properly when the overrun interrupt has been generated, write "1" to SSPICR register, and then read all data from the receive FIFO. Even if all the data is not read, data can be transmitted / received if the receive FIFO has free space and the number of data to be transmitted does not exceed the free space of the receive FIFO. Note that if the receive FIFO is not read (provided that the receive FIFO is not empty) within a certain 32-bit period (bit rate) after the overrun interrupt is cleared, a time-out interrupt will be generated. 13.4.5 DMA interface The DMA operation of the SSP is controlled through SSPxDMACR register. When there are more data than the watermark level (half of the FIFO) in the receive FIFO, the receive DMA request is asserted. When the amount of data left in the transmit FIFO is less than the watermark level (half of the FIFO), the transmit DMA request is asserted. To clear the transmit/receive DMA request, an input pin for the transmit/receive DMA request clear signals, which are asserted by the DMA controller, is provided. Set the DMA burst length to four words. Note:For the remaining three words, the SSP does not assert the burst request. Each request signal remains asserted until the relevant DMA clear signal is asserted. After the request clear signal is deasserted, a request signal can become active again, depending on the conditions described above. All request signals are deasserted if the SSP is disabled or the DMA enable signal is cleared. The following table shows the trigger points for DMABREQ, for both the transmit and receive FIFOs. Burst length 2013/5/31 Watermark level Transmit (number of empty locations) Receive (number of filled locations) 1/2 4 4 Page 404 TMPM361F10FG 13.5 SSP operation 13.5.1 Initial setting for SSP Settings for the SSP communication protocol must be made with the SSP disabled. Control registers SSPCR0 and SSPCR1 need to configure this SSP as a master or slave operating under one of the following protocols. In addition, make the settings related to the communication speed in the clock prescale registers SSPCPSR and SSPCR0 . This SSP supports the following protocols: ・ SPI ・ SSI ・ Microwire 13.5.2 Enabling SSP The transfer operation starts when the operation is enabled with the transmitted data written in the transmit FIFO, or when transmitted data is written in the transmit FIFO with the operation enabled. However, if the transmit FIFO contains only four or fewer entries when the operation is enabled, a transmit interrupt will be generated. This interrupt can be used to write the initial data. Note:When the SSP is in the SPI slave mode and the SPFSS pin is not used, be sure to transmit data of one byte or more in the FIFO before enabling the operation. If the operation is enabled with the transmit FIFO empty, the transfer data will not be output correctly. 13.5.3 Clock ratios When setting a frequency for fsys , the following conditions must be met. ・ In master mode fSPCLK (maximum) → fsys /4 fSPCLK (minimum) → fsys /(254×256) ・ In slave mode fSPCLK (maximum) → fsys /12 fSPCLK (minimum) → fsys /(254×256) Note:The maximum baud-rate in the master mode is equal or less than 16Mbps. Page 405 2013/5/31 13. 13.6 Synchronous Serial Port (SSP) Frame Format 13.6 TMPM361F10FG Frame Format Each frame format is between 4 and 16 bits wide depending on the size of data programmed, and is transmitted starting from the MSB. ・ Serial clock (SPCLK) Signals remain "Low" in the SSI and Microwire formats and as inactive in the SPI format while the SSP is in the idle state. In addition, data is output at the set bit rate only during data transmission. ・ Serial frame (SPFSS) In the SPI and Microwire frame formats, signals are set to "Low" active and always asserted to "Low" during frame transmission. In the SSI frame format, signals are asserted only during 1 bit rate before each frame transmission. In this frame format, output data is transmitted at the rising edge of SPCLK and the input data is received at its falling edge. Refer to Section "13.6.1" to "13.6.3" for details of each frame format. 2013/5/31 Page 406 TMPM361F10FG 13.6.1 SSI frame format In this mode, the SSP is in idle state, SPCLK and SPFSS are forcedly set to "Low", and the transmit data line SPDO becomes Hi-Z. When data is written in the transmit FIFO, the master outputs "High" pulses of 1 SPCLK to the SPFSS line. The transmitted data will be transferred from the transmit FIFO to the transmit serial shift register. Data of 4 to 16 bits will be output from the SPDO pin at the next rising edge of SPCLK. Likewise, the received data will be input starting from the MSB to the SPDI pin at the falling edge of SPCLK. The received data will be transferred from the serial shift register into the receive FIFO at the rising edge of SPCLK after its LSB data is latched. SPCLK SPFSS SPDO SPDI Hi-Z(Note1㸧 Hi-Z(Note1㸧 MSB LSB Hi-Z(Note2㸧 MSB LSB Hi-Z(Note2㸧 4 to 16 bit Figure 13-2 SSI frame format (transmission/reception during single transfer) SPCLK SPFSS SPDO SPDI LSB MSB LSB MSB LSB MSB LSB MSB 4 to 16bit Figure 13-3 SSI frame format (transmission/reception during continuous transfer) Note 1: When transmission is disable, SPDO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. Page 407 2013/5/31 13. 13.6 Synchronous Serial Port (SSP) Frame Format TMPM361F10FG 13.6.2 SPI frame format The SPI interface has 4 lines. SPFSS is used for slave selection. One of the main features of the SPI format is that the and bits in the SSPCR0 register can be used to set the SPCLK operation timing. SSPCR0 is used to set the level at which SPCLK in idle state is held. SSPCR0 is used to select the clock edge at which data is latched. SSPCR0 SSPCR0 0 "Low" state Capture data at the 1st clock edge. 1 "High" state Capture data at the 2nd clock edge. SPCLK SPFSS SPDO SPDI Hi-Z(Note1㸧 MSB LSB Hi-Z(Note2) MSB LSB Hi-Z(Note1㸧 Hi-Z(Note2㸧 Figure 13-4 SPI frame format (single transfer, ="0" & ="0") SPCLK SPFSS SPDO SPDI LSB MSB LSB LSB Hi-Z(Note2) MSB LSB MSB Hi-Z(Note2) MSB 㸲 to 16bit Figure 13-5 SPI frame format (continuous transfer,="0" & ="0") Note 1: When transmission is disable, SPDO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to valid the voltage level. Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to valid the voltage level. 2013/5/31 Page 408 TMPM361F10FG With this setting ="0", during the idle period: ・ The SPCLK signal is set to "Low". ・ SPFSS is set to "High". ・ The transmit data line SPDO is set to "Low". If the SSP is enabled and valid data exists in the transmit FIFO, the SPFSS master signal driven by "Low" notifies of the start of transmission. This enables the slave data in the SPDI input line of the master. When a half of the SPCLK period has passed, valid master data is transferred to the SPDO pin. Both the master data and slave data are now set. When another half of SPCLK has passed, the SPCLK master clock pin becomes "High". After that, the data is captured at the rising edge of the SPCLK signal and transmitted at its falling edge. In the single transfer, the SPFSS line will return to the idle "High" state when all the bits of that data word have been transferred, and then one cycle of SPCLK has passed after the last bit was captured. However, for continuous transfer, the SPFSS signal must be pulsed at HIGH between individual data word transfers. This is because change is not enabled when the slave selection pin freezes data in its peripheral register and the bit is logical 0. Therefore, to enable writing of serial peripheral data, the master device must drive the SPFSS pin of the slave device between individual data transfers. When the continuous transfer is completed, the SPFSS pin will return to the idle state when one cycle of SPCLK has passed after the last bit is captured. Page 409 2013/5/31 13. 13.6 Synchronous Serial Port (SSP) Frame Format 13.6.3 TMPM361F10FG Microwire frame format The Microwire format uses a special master/slave messaging method, which operates in half-duplex mode. In this mode, when a frame begins, an 8-bit control message is transmitted to the slave. During this transmission, no incoming data is received by the SSP. After the message has been transmitted, the slave decodes it, and after waiting one serial clock after the last bit of the 8-bit control message has been sent, it responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. SPCLK SPFSS SPDO Hi-Z(Note1㸧 LSB MSB Hi-Z(Note1㸧 8bit SPDI LSB MSB Hi-Z(Note2㸧 Hi-Z(Note2㸧 4 to 16bit Figure 13-6 Microwire frame format (single transfer) Note 1: When transmission is disabled, SPDO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to fix the voltage level. Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to fix the voltage level. Though the Microwire format is similar to the SPI format, it uses the master/slave message transmission method for half-duplex communications. Each serial transmission is started by an 8-bit control word, which is sent to the off-chip slave device. During this transmission, the SSP does not receive input data. After the message has been transmitted, the off-chip slave decodes it, and after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. With this configuration, during the idle period: ・ The SPCLK signal is set to "Low". ・ SPFSS is set to "High". ・ The transmit data line SPDO is set to "Low". A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SPFSS causes the value stored in the bottom entry of the transmit FIFO to be transferred to the serial shift register for the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SPDO pin. SPFSS remains "Low" and the SPDI pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SPCLK. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSP. Each bit is driven onto SPDI line on the falling edge of SPCLK. The SSP in turn latches each bit on the rising edge of SPCLK. At the end of the frame, for single transfers, the SPFSS signal is pulled "High" one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. 2013/5/31 Page 410 TMPM361F10FG Note:The off-chip slave device can tristate the receive line either on the falling edge of SPCLK after the LSB has been latched by the receive shifter, or when the SPFSS pin goes "High". SPCLK SPFSS SPDO LSB MSB Hi-Z(Note1㸧 LSB Hi-Z(Note1㸧 8bit SPDI Hi-Z(Note2㸧 MSB LSB Hi-Z(Note2㸧 MSB 4 to 16bit Figure 13-7 Microwire frame format (continuous transfer) Note 1: When transmission is disabled, SPDO terminal doesn't output and is high impedance status. This terminal needs to add suitable pull-up/down resistance to fix the voltage level. Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance status, this terminal needs to add suitable pull-up/down resistance to fix the voltage level. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SPFSS line is continuously asserted (held Low) and transmission of data occurs back to back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SPCLK, after the LSB of the frame has been latched into the SSP. Note:[Example of connection] The SSP does not support dynamic switching between the master and slave in the system. Each sample SSP is configured and connected as either a master or slave. Page 411 2013/5/31 13. 13.6 Synchronous Serial Port (SSP) Frame Format 2013/5/31 TMPM361F10FG Page 412 TMPM361F10FG 14. Serial Bus Interface (I2C/SIO) The TMPM361F10FG contains 4 Serial Bus Interface (I2C/SIO) channels, in which the following two operating modes are included: ・ I2C bus mode (with multi-master capability) ・ Clock-synchronous 8-bit SIO mode In the I2C bus mode, the I2C/SIO is connected to external devices via SCL and SDA. In the clock-synchronous 8-bit SIO mode, the I2C/SIO is connected to external devices via SCK, SI and SO. The following table shows the programming required to put the I2C/SIO in each operating mode. Table 14-1 Port settings for using serial bus interface channel Operating mode pin I2C SCL0 :PL1 bus mode SDA0 :PL0 SBI0 Port Function Register Port Output Control Register Port Input Control Register Port Open Drain Output Control Register PLFR1[1:0] = 11 PLCR[1:0] = 11 PLIE[1:0] = 11 PLOD[1:0] = 11 PLCR[2:0] = 101(SCK0 output) PLIE[2:0] = 010(SCK0 output) PLCR[2:0] = 001(SCK0 input) PLIE[2:0] = 110(SCK0 input) PGCR[1:0] = 11 PGIE[1:0] = 11 PGCR[2:0] = 101(SCK1 output) PGIE[2:0] = 010(SCK1 output) PGCR[2:0] = 001(SCK1 input) PGIE[2:0] = 110(SCK1 input) PGCR[5:4] = 11 PGIE[5:4] = 11 PGCR[6:4] = 101(SCK2 output) PGIE[6:4] = 010(SCK2 output) PGCR[6:4] = 001(SCK2 input) PGIE[6:4] = 110(SCK2 input) PLFR3[5:4] = 11 PLCR[5:4] = 11 PLIE[5:4] = 11 PLOD[5:4] = 11 - - - - SCK0 :PL2 SIO mode SI0 :PL1 PLFR1[2:0] = 111 SO0 :PL0 I2C SCL1 :PG1 bus mode SDA1 :PG0 SBI1 PGFR1[1:0] = 11 SCK1 :PG2 SIO mode SI1 :PG1 PGFR1[2:0] = 111 SO1 :PG0 I2C SCL2 :PG5 bus mode SDA2 :PG4 SBI2 PGFR1[5:4] = 11 SCK2 :PG6 SIO mode SI2 :PG5 PGFR1[6:4] = 111 SO2 :PG4 I2C SCL3 :PL5 bus mode SDA3 :PL4 SBI3 PLOD[2:0] = xxx PGOD[1:0] = 11 PGOD[2:0] = xxx PGOD[5:4] = 11 PGOD[6:4] = xxx SCK3 :SIO mode SI3 :SO3 :- Note:x: Don't care Page 413 2013/5/31 14. 14.1 Serial Bus Interface (I2C/SIO) Configuration 14.1 TMPM361F10FG Configuration The configuration is shown in Figure 14-1. INTSBIx interrupt request SCL SCK SIO clock control fsys Frequency Divider Noise canceller I2C bus clock synchronization + control SBIxCR2 / SBIxSR Control register2/ Status register Input/ Output control SIO data control Transfer control circuit Shift register SBIxI2CA I2C bus address register SBIxDBR Data buffer register I2C bus data control SO SI Noise canceller SBIxCR0,1 SBIxBR0 Control register0, 1 Baud rate register0 Figure 14-1 (I2C/SIO) Block Interface 2013/5/31 Page 414 SDA SCKx SDAx SOx SCLx SIx TMPM361F10FG 14.2 Register The following registers control the serial bus interface and provide its status information for monitoring. The register below performs different functions depending on the mode. For details, refer to "14.4 Control Registers in the I2C Bus Mode" and "14.7 Control register of SIO mode". 14.2.1 Registers for each channel The tables below show the registers and register addresses for each channel. Channel x Base Address Channel0 0x400E_0000 Channel1 0x400E_0100 Channel2 0x400E_0200 Channel3 0x400E_0300 Register name(x=0,1,2,3,) Address(Base+) Control register 0 SBIxCR0 0x0000 Control register 1 SBIxCR1 0x0004 Data buffer register SBIxDBR 0x0008 SBIxI2CAR 0x000C I2C bus address register Control register 2 SBIxCR2 (writing) Status register SBIxSR (reading) Baud rate register 0 SBIxBR0 Page 415 0x0010 0x0014 2013/5/31 14. Serial Bus Interface (I2C/SIO) 14.3 I2C Bus Mode Data Format 14.3 TMPM361F10FG I2C Bus Mode Data Format Figure 14-2 shows the data formats used in the I2C bus mode. (a) Addressing format 8 bit S Slave address 1 RA / C WK 1 to 8 bits 1 1 to 8 bits Data A C K Data Once 1 A CP K Repeated (b) Addressing format (with repeated start condition) 8 bit S Slave address 1 RA / C WK Once 1 to 8 bits 1 A CS K Data Repeated 8 bit Slave address 1 1 to 8 bits RA / C WK Once Repeated (c) Free data format (master-transmitter to slave-receiver) S 8 bit 1 1 to 8 bits 1 1 to 8 bits Data A C K Data A C K Data Once 1 A CP K Repeated Note) S : Start condition R/W : Direction bit ACK : Acknowledge bit P : Stop condition Figure 14-2 I2C Bus Mode Data Formats 2013/5/31 Page 416 Data 1 A CP K TMPM361F10FG 14.4 Control Registers in the I2C Bus Mode The following registers control the serial bus interface in the I2C bus mode and provide its status information for monitoring. 14.4.1 SBIxCR0(Control register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SBIEN - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 SBIEN R/W Serial bus interface operation 0:Disable 1:Enable To use the serial bus interface, enable this bit first. For the first time in case of setting to enable, the relevant SBI registers can be read or written. Since all clocks except SBIxCR0 stop if this bit is disabled, power consumption can be reduced by disabling this bit. If this bit is disabled after it’s been enabled once, the settings of each register are retained. 6-0 - R Read as 0. Note:To use the serial bus interface, enable this bit first. Page 417 2013/5/31 14. 14.4 Serial Bus Interface (I2C/SIO) Control Registers in the I2C Bus Mode 14.4.2 TMPM361F10FG SBIxCR1(Control register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol BC After reset Bit 0 Bit Symbol 0 ACK - SCK2 SCK1 0 1 0 0 0 Type Function 31-8 - R Read as 0. 7-5 BC[2:0] R/W Select the number of bits per transfer (Note 1) When = 0 4 ACK R/W Data When = 1 Data Number of clock cycles length Number of clock cycles length 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 Master mode 0: Acknowledgement clock pulse is not generated. 1: Acknowledgement clock pulse is generated. Slave mode 0: Acknowledgement clock pulse is not counted. 1: Acknowledgement clock pulse is counted. 3 - R Read as 1. 2-1 SCK[2:1] R/W Select internal SCL output clock frequency (Note 2). 0 SCK[0] W 000 n=5 615 kHz 001 n=6 471 kHz 010 n=7 320 kHz 011 n=8 195 kHz 100 n=9 110 kHz 101 n = 10 58 kHz 110 n = 11 30 kHz 111 SWRMON R reserved On reading : Software reset status monitor 0:Software reset operation is in progress. 1:Software reset operation is not in progress. 2013/5/31 Page 418 System Clock: fsys ( = 64MHz ) Clock gear : fc/1 Frequency = fsys [Hz] 2n + 72 0 SCK0 / SWRMON 1(Note3) TMPM361F10FG Note 1: Clear to "000" before switching the operation mode to the SIO mode. Note 2: For details on the SCL line clock frequency, refer to "14.5.1 Serial Clock". Note 3: After a reset, the bit is read as "1". However, if the SIO mode is selected at the SBIxCR2 register, the initial value of the bit is "0". Note 4: The initial value for selecting a frequency is =000 and is independent of the read initial value. Note 5: When ="001" and ="0" in master mode, SCL line may be fixed to "L" by falling edge of SCL line after generation of STOP condition and the other master devices can not use the bus. In the case of bus which is connected with several master devices, the bumber of bits per transfer should be set equal or more than 2 before generation of STOP condition. Page 419 2013/5/31 14. 14.4 Serial Bus Interface (I2C/SIO) Control Registers in the I2C Bus Mode 14.4.3 TMPM361F10FG SBIxCR2(Control register 2) This register serves as SBIxSR register by reading it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol MST TRX BB PIN After reset 0 0 0 1 Bit Bit Symbol Type SBIM 0 0 SWRST 0 0 Function 31-8 - R Read as 0. 7 MST W Select master/slave 0: Slave mode 1: Master mode 6 TRX W Select transmit/ receive 0: Receive 1: Transmit 5 BB W Start/stop condition generation 0: Stop condition generated 1: Start condition generated 4 PIN W Clear INTSBIx interrupt request 0: − 1: Clear interrupt request 3-2 SBIM[1:0] W Select serial bus interface operating mode (Note) 00: Port mode (Disables a serial bus interface output) 01: SIO mode 10: I2C bus mode 11: Reserved 1-0 SWRST[1:0] W Software reset generation Write "10" followed by "01" to generate a reset. When writing, set to "10"; I2Cbus mode. Note:Make sure that modes are not changed during a communication session.Ensure that the bus is free before switching the operating mode to the port mode. Ensure that the port is at the "High" level before switching the operating mode from the port mode to the I2C bus or clocksynchronous 8-bit SIO mode. 2013/5/31 Page 420 0 TMPM361F10FG 14.4.4 SBIxSR (Status Register) This register serves as SBIxCR2 by writing to it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol MST TRX BB PIN AL AAS ADO LRB After reset 0 0 0 1 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 MST R Master/slave selection monitor 0: Slave mode 1: Master mode 6 TRX R Transmit/receive selection monitor 0: Receive 1: Transmit 5 BB R I2C bus state monitor 0: Free 1: Busy 4 PIN R INTSBIx interrupt request monitor 0:Interrupt request generated 1: Interrupt request cleared 3 AL R Arbitration lost detection 0: − 1:Detected 2 AAS R Slave address match detection 0: − 1: Detected (This bit is set when the general call is detected as well.) 1 ADO R General call detection 0: − 1:Detected 0 LRB R Last received bit monitor 0:Last received bit "0" 1:Last received bit "1" Page 421 2013/5/31 14. 14.4 Serial Bus Interface (I2C/SIO) Control Registers in the I2C Bus Mode 14.4.5 TMPM361F10FG SBIxBR0(Serial bus interface baud rate register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - I2SBI - - - - - - After reset 1 0 1 1 1 1 1 0 24 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 - R Read as 1. 6 I2SBI R/W Operation at the IDLE mode 0: Stop 1: Operate 5-1 - R Read as 1. 0 - R/W Be sure to write "0". 14.4.6 SBIxDBR (Serial bus interface data buffer register) 31 30 29 28 27 26 25 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol DB After reset Bit 0 0 Bit Symbol 0 0 Type Function 31-8 - R Read as 0. 7-0 DB[7:0] R (Receive)/ W (Transmit) Receive data / Transmit data Note 1: The transmission data must be written in to the register from the MSB (bit 7). The received data is stored in the LSB. Note 2: Since SBIxBDR has independent buffers for writing and reading, a written data cannot be read. Thus, readmodify-write instructions, such as bit manipulation, cannot be used. 2013/5/31 Page 422 TMPM361F10FG 14.4.7 SBIxI2CAR (I2Cbus address register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol SA After reset Bit 0 Bit Symbol 0 0 0 Type 0 ALS 0 0 0 0 Function 31-8 - R Read as 0. 7-1 SA[6:0] R/W Set the slave address when the SBI acts as a slave device. 0 ALS R/W Specify address recognition mode. 0: Recognize its slave address. 1: Do not recognize its slave address (free-data format). Note 1: Please set the bit 0 of I2C bus address register SBIxI2CAR to "0", except when you use a free data format. It operates as a free data format when setting it to "1". Selecting the master fixes to transmission. Selecting the slave fixes to reception. Note 2: Do not set SBIxI2CAR to "0x00" in slave mode. (If SBIxI2CAR is set to "0x00", it’s recognized that the slave address matches the START byte ("0x01") of the I2C standard received in slave mode.) Page 423 2013/5/31 14. Serial Bus Interface (I2C/SIO) 14.5 Control in the I2C Bus Mode 14.5 TMPM361F10FG Control in the I2C Bus Mode 14.5.1 Serial Clock 14.5.1.1 Clock source SBIxCR1 specifies the maximum frequency of the serial clock to be output from the SCL pin in the master mode. tHIGH tLOW 1/fscl SBIxCR1 tLOW = 2n-1/fsys + 58/fsys tHIGH = 2n-1/fsys + 14/fsys fscl = 1/(tLOW + tHIGH) fsys = n 2 + 72 000 001 010 011 100 101 110 n 5 6 7 8 9 10 11 Figure 14-3 Clock source Note:The maximum speeds in the standard and high-speed modes are specified to 100kHz and 400kHz respectively following the communications standards. Notice that the internal SCL clock frequency is determined by the fsys used and the calculation formula shown above. 14.5.1.2 Clock Synchronization The I2C bus is driven by using the wired-AND connection due to its pin structure. The first master that pulls its clock line to the "Low" level overrides other masters producing the "High" level on their clock lines. This must be detected and responded by the masters producing the "High" level. Clock synchronization assures correct data transfer on a bus that has two or more master. For example, the clock synchronization procedure for a bus with two masters is shown below. Wait for “High”level period counting Start “High” level period counting Internal SCL output (Master A) Reset “High”level period counting Internal SCL output (Master B) SCL line a b c Figure 14-4 Example of Clock Synchronization At the point a, Master A pulls its internal SCL output to the "Low" level, bringing the SCL bus line to the "Low" level. Master B detects this transition, resets its "High" level period counter, and pulls its internal SCL output level to the "Low" level. 2013/5/31 Page 424 TMPM361F10FG Master A completes counting of its "Low" level period at the point b, and brings its internal SCL output to the "High" level. However, Master B still keeps the SCL bus line at the "Low" level, and Master A stops counting of its "High" level period counting.After Master A detects that Master B brings its internal SCL output to the "High" level and brings the SCL bus line to the "High" level at the point c, it starts counting of its "High" level period. After that Master finishes counting the "High" level period, the Master pulls the SCL pin to "Low" and the SCL bus line becomes "Low". This way, the clock on the bus is determined by the master with the shortest "High" level period and the master with the longest "Low" level period among those connected to the bus. 14.5.2 Setting the Acknowledgement Mode Setting SBIxCR1 to "1" selects the acknowledge mode.When operating as a master, the SBI adds one clock for acknowledgment signal. In slave mode, the clock for acknowledgement signals is counted. In transmitter mode, the SBI releases the SDAx pin during clock cycle to receive acknowledgement signals from the receiver. In receiver mode, the SBI pulls the SDAx pin to the "Low" level during the clock cycle and generates acknowledgement signals. Also in slave mode, if a general-call address is received, the SBI pulls the SDAx pin to the "Low" level during the clock cycle and generates acknowledgement signals. By setting to "0", the non-acknowledgment mode is activated. When operating as a master, the SBI does not generate clock for acknowledgement signals. In slave mode, the clock for acknowledgement signals is counted. 14.5.3 Setting the Number of Bits per Transfer SBIxCR1 specifies the number of bits of the next data to be transmitted or received. Under the start condition, is set to "000", causing a slave address and the direction bit to be transferred in a packet of eight bits. At other times, keeps a previously programmed value. 14.5.4 Slave Addressing and Address Recognition Mode Setting "0" to SBIxI2CAR and a slave address in SBIxI2CAR sets addressing format, and then the SBI recognizes a slave address transmitted by the master device and receives data in the addressing format. If is set to "1", the SBI does not recognize a slave address and receives data in the free data format. In the case of free data format, a slave address and a direction bit are not recognized; they are recognized as data immediately after generation of the start condition. 14.5.5 Operating mode The setting of SBIxCR2 controls the operating mode. To operate in I2C mode, ensure that the serial bus interface pins are at "High" level before setting to "10". Also, ensure that the bus is free before switching the operating mode to the port mode. Page 425 2013/5/31 14. Serial Bus Interface (I2C/SIO) 14.5 Control in the I2C Bus Mode 14.5.6 TMPM361F10FG Configuring the SBI as a Transmitter or a Receiver Setting SBIxCR2 to "1" configures the SBI as a transmitter. Setting to "0" configures the SBI as a receiver. At the slave mode: ・ when data is transmitted in the addressing format. ・ when the received slave address matches the value specified at SBIxI2CAR. ・ when a general-call address is received; i.e., the eight bits following the start condition are all zeros. If the value of the direction bit (R/W) is "1", is set to "1" by the hardware. If the bit is "0", is set to "0". As a master device, the SBI receives acknowledgement from a slave device. If the direction bit of "1" is transmitted, is set to "0" by the hardware. If the direction bit is "0", changes to "1". If the SBI does not receive acknowledgement, retains the previous value. is cleared to "0" by the hardware when it detects the stop condition on the bus or the arbitration lost. If SBI is used in free data format, is not changed by the hardware. 14.5.7 Configuring the SBI as a Master or a Slave Setting SBIxCR2 to "1" configures the SBI to operate as a master device. Setting to "0" configures the SBI as a slave device. is cleared to "0" by the hardware when it detects the stop condition on the bus or the arbitration lost. 14.5.8 Generating Start and Stop Conditions When SBIxSR is "0", writing "1" to SBIxCR2 causes the SBI to start a sequence for generating the start condition and to output the slave address and the direction bit prospectively written in the data buffer register. must be set to "1" in advance. SCLx pin 1 2 3 4 5 6 7 8 SDAx pin A6 A5 A4 A3 A2 A1 A0 R/W Start condition Slave address and direction bit 9 Acknowledgement signal Figure 14-5 Generating the Start Condition and a Slave Address When is "1", writing "1" to and "0" to causes the SBI to start a sequence for generating the stop condition on the bus. The contents of should not be altered until the stop condition appears on the bus. 2013/5/31 Page 426 TMPM361F10FG If SCL bus line is pulled "Low" by other devices when the stop condition is generated, the stop condition is generated after the SCL line is released. SCL line SDA line Stop condition Figure 14-6 Generating the Stop Condition SBIxSR can be read to check the bus state. is set to "1" when the start condition is detected on the bus (the bus is busy), and cleared to "0" when the stop condition is detected (the bus is free). 14.5.9 Interrupt Service Request and Release In master mode, a serial bus interface request (INTSBIx) is generated when the transfer of the number of clock cycles set by and is completed. In slave mode, INTSBIx is generated under the following conditions. ・ After output of the acknowledge signal which is generated when the received slave address matches the slave address set to SBIxI2CAR. ・ After the acknowledge signal is generated when a general-call address is received. ・ When the slave address matches or a data transfer is completed after receiving a general-call address. In the address recognition mode ( = "0"), INTSBIx is generated when the received slave address matches the values specified at SBIxI2CAR or when a general-call (eight bits data following the start condition is all "0") is received. When an interrupt request (INTSBIx) is generated, SBIxCR2 is cleared to "0". While is cleared to "0", the SBI pulls the SCL line to the "Low" level. is set to "1" when data is written to or read from SBIxDBR. It takes a period of tLOW for the SCL line to be released after is set to "1". When the program writes "1" to , it is set to "1". However, writing "0" does not clear this bit to "0". Note:When arbitration is lost in master mode, is not cleared to "0" if the slave address does not match (INTSBIx is generated). 14.5.10 Arbitration Lost Detection Monitor The I2C bus has the multi-master capability (there are two or more masters on a bus), and requires the bus arbitration procedure to ensure correct data transfer. A master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no start condition occurring on the SDA and SCL lines.The I2C-bus arbitration takes place on the SDA line. The arbitration procedure for two masters on a bus is shown below. Page 427 2013/5/31 14. Serial Bus Interface (I2C/SIO) 14.5 Control in the I2C Bus Mode TMPM361F10FG Up until the point a, Master A and Master B output the same data. At the point a, Master A outputs the "Low" level and Master B outputs the "High" level. Then Master A pulls the SDA bus line to the "Low" level because the line has the wired-AND connection. When the SCL line goes high at the point b, the slave device reads the SDA line data, i.e., data transmitted by Master A. At this time, data transmitted by Master B becomes invalid. This condition of Master B is called "Arbitration Lost". Master B releases its SDA pin, so that it does not affect the data transfer initiated by another master. If two or more masters have transmitted exactly the same first data word, the arbitration procedure continues with the second data word. SCL (Line) Internal SDA output (masterA) Loses arbitration and sets the internal SDA output to “1”. Internal SDA output(master B) SDA Line a b Figure 14-7 Lost Arbitration A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line. If there is a difference between these two values, Arbitration Lost occurs and SBIxSR is set to "1". When is set to "1", SBIxSR are cleared to "0", causing the SBI to operate as a slave receiver.Therefore, the serial bus interface circuit stops the clock output during data transfer after is set to "1". is cleared to "0" when data is written to or read from SBIxDBR or data is written to SBIxCR2. 2013/5/31 Page 428 TMPM361F10FG Internal SCL output 1 2 3 D7A D6A D5A 4 5 6 7 8 9 1 2 3 4 MasterA Internal SDA output D4A D3A D2A D1A D0A D7A' D6A' D5A' D4A' Clock output dstops here Internal SCL output 1 2 3 4 MasterB InternalSDA output D7B D6B Internal SDA output is fixed to "High"level . due to Arbitration Lost of Master B. Access to SBIxDBR or SBIxCR2 Figure 14-8 Example of Master B Lost Arbitration (D7A = D7B, D6A = D6B) 14.5.11 Slave Address Match Detection Monitor When the SBI operates as a slave device in the address recognition mode (SBIxI2CAR="0"), SBIxSR is set to "1" on receiving the general-call address or the slave address that matches the value specified at SBIxI2CAR. When is "1", is set to "1" when the first data word has been received. is cleared to "0" when data is written to or read from SBIxDBR. 14.5.12 General-call Detection Monitor When the SBI operates as a slave device, SBIxSR is set to "1" when it receives the general-call address; i.e., the eight bits following the start condition are all zeros. is cleared to "0" when the start or stop condition is detected on the bus. 14.5.13 Last Received Bit Monitor SBIxSR is set to the SDA line value that was read at the rising of the SCL line. In the acknowledgment mode, reading SBIxSR immediately after generation of the INTSBIx interrupt request causes ACK signal to be read. 14.5.14 Data Buffer Register (SBIxDBR) Reading or writing SBIxDBR initiates reading received data or writing transmitted data. When the SBI is acting as a master, setting a slave address and a direction bit to this register generates the start condition. Page 429 2013/5/31 14. Serial Bus Interface (I2C/SIO) 14.5 Control in the I2C Bus Mode 14.5.15 TMPM361F10FG Baud Rate Register (SBIxBR0) The SBIxBR0 register determines if the SBI operates or not when it enters the IDLE mode. This register must be programmed before executing an instruction to switch to the standby mode. 14.5.16 Software Reset If the serial bus interface circuit locks up due to external noise, it can be initialized by using a software reset. Writing "10" followed by "01" to SBIxCR2 generates a reset signal that initializes the serial bus interface circuit. When writing, set to "10"; I2Cbus mode. After a reset, all control registers and status flags are initialized to their reset values. When the serial bus interface is initialized, is automatically cleared to "0". Note:A software reset causes the SBI operating mode to switch from the I2C mode to the port mode. 2013/5/31 Page 430 TMPM361F10FG 14.6 Data Transfer Procedure in the I2C Bus ModeI2C 14.6.1 Device Initialization First, program SBIxCR1. Writing "000" to SBIxCR1 at the time. Next, program SBIxI2CAR by specifying a slave address at and an address recognition mode at . ( must be cleared to "0" when using the addressing format). To configure the Serial Bus Interface as a slave receiver, ensure that the serial bus interface pin is at "High" first. Then write "0" to SBIxCR2, "1" to , "10" to and "0" to the bit 1 and 0. Note:Initialization of the serial bus interface circuit must be completed within a period that any device does not generate start condition after all devices connected to the bus were initialized. If this rule is not followed, data may not be received correctly because other devices may start transfer before the initialization of the serial bus interface circuit is completed. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 0 0 X 0 X X X Specifies ACK and SCL clock. SBIxI2CAR ← X X X X X X X X Specifies a slave address and an address recognition mode. SBIxCR2 ← 0 0 0 1 1 0 0 0 Configures the SBI as a slave receiver. Note:X; Don’t care 14.6.2 Generating the Start Condition and a Slave Address 14.6.2.1 Master mode In the master mode, the following steps are required to generate the start condition and a slave address. First, ensure that the bus is free ( = "0"). Then, write "1" to SBIxCR1 to select the acknowledgment mode. Write to SBIxDBR a slave address and a direction bit to be transmitted. When = "0", writing "1111" to SBIxCR2 generates the start condition on the bus. Following the start condition, the SBI generates nine clocks from the SCL pin. The SBI outputs the slave address and the direction bit specified at SBIxDBR with the first eight clocks, and releases the SDA line in the ninth clock to receive an acknowledgment signal from the slave device. The INTSBIx interrupt request is generated on the falling of the ninth clock, and is cleared to "0". In the master mode, the SBI holds the SCL line at the "Low" level while is = "0". changes its value according to the transmitted direction bit at generation of the INTSBIx interrupt request, provided that an acknowledgment signal has been returned from the slave device. Note:To output salve address, check with software that the bus is free before writing to SBIxDBR. If this rule is not followed, data being output on the bus may get ruined. Page 431 2013/5/31 14. 14.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C TMPM361F10FG Settings in main routine 7 6 5 Reg. ← Reg. ← Reg. e 0x20 if Reg. ≠ 0x00 4 3 2 1 0 SBIxSR Ensures that the bus is free. Then SBIxCR1 ← X X X 1 0 X X X Selects the acknowledgement mode. SBIxDBR ← X X X X X X X X Specifies the desired slave address and direction. SBIxCR2 ← 1 1 1 1 1 0 0 0 Generates the start condition. Example of INTSBI0 interrupt routine Clears the interrupt request. Processing End of interrupt 14.6.2.2 Slave mode In the slave mode, the SBI receives the start condition and a slave address. After receiving the start condition from the master device, the SBI receives a slave address and a direction bit from the master device during the first eight clocks on the SCL line. If the received address matches its slave address specified at SBIxI2CAR or is equal to the general-call address, the SBI pulls the SDA line to the "Low" level during the ninth clock and outputs an acknowledgment signal. The INTSBIx interrupt request is generated on the falling of the ninth clock, and is cleared to "0". In the slave mode, the SBI holds the SCL line at the "Low" level while is "0". SCLx pin 1 2 3 4 5 6 7 8 9 SDAx pin A6 A5 A4 A3 A2 A1 A0 R/W ACK Start condition Slave address + Direction bit Acknowledgement from slave device INTSBIx interrupt request Master output Slave output Figure 14-9 Generation of the Start Condition and a Slave Address 2013/5/31 Page 432 TMPM361F10FG 14.6.3 Transferring a Data Word At the end of a data word transfer, the INTSBIx interrupt is generated to test to determine whether the SBI is in the master or slave mode. 14.6.3.1 Master mode ( = "1") Test to determine whether the SBI is configured as a transmitter or a receiver. (1) Transmitter mode ( = "1") Test . If is "1", that means the receiver requires no further data. The master then generates the stop condition as described later to stop transmission. If is "0", that means the receiver requires further data.If the next data to be transmitted has eight bits, the data is written into SBIxDBR. If the data has different length, and are programmed and the transmit data is written into SBIxDBR.Writing the data makes to "1", causing the SCL pin to generate a serial clock for transferring a next data word, and the SDA pin to transfer the data word. After the transfer is completed, the INTSBIx interrupt request is generated, is cleared to "0", and the SCL pin is pulled to the "Low" level. To transmit more data words, test again and repeat the above procedure. INTSBIx interrupt if MST = 0 Then go to the slave-mode processing. if TRX = 0 Then go to the receiver-mode processing. if LRB = 0 Then go to processing for generating the stop condition. SBIxCR1 ← X X X X 0 X X X Specifies the number of bits to be transmitted and specify whether ACK is required. SBIxDBR ← X X X X X X X X Writes the transmit data. End of interrupt processing. Note:X; Don’t care Page 433 2013/5/31 14. 14.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C SCLx pin TMPM361F10FG 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Wite to SBIxDBR SDAx pin Acknowledgement from receiver INTSBIx interrupt request Master output Slave output Figure 14-10 = "000",= "1" (Transmitter Mode) (2) Receiver mode ( = "0") If the next data to be transmitted has eight bits, the transmit data is written into SBIxDBR. If the data has different length, and are programmed and the received data is read from SBIxDBR to release the SCL line. (The data read immediately after transmission of a slave address is undefined.)On reading the data, is set to "1", and the serial clock is output to the SCL pin to transfer the next data word.In the last bit, when the acknowledgment signal becomes the "Low" level, "0" is output to the SDA pin. After that, the INTSBIx interrupt request is generated, and is cleared to "0", pulling the SCL pin to the "Low" level.Each time the received data is read from SBIxDBR, one-word transfer clock and an acknowledgement signal are output. Read the received data SCLx pin 1 2 3 4 5 6 7 8 9 SDAx pin D7 D6 D5 D4 D3 D2 D1 D0 ACK Next D7 Acknowledgment signal to transmitter INTSBIx interrupt request Master output Slave output Figure 14-11 = "000",= "1" (Receiver Mode) To terminate the data transmission from the transmitter, must be cleared to "0" immediately before reading the data word second to last. This disables generation of an acknowledgment clock for the last data word. When the transfer is completed, an interrupt request is generated. After the interrupt processing, must be set to "001" and the data must be read so that a clock is generated for 1-bit transfer. At this time, the master receiver holds the SDA bus line at the "High" level, which signals the end of transfer to the transmitter as an acknowledgment signal. 2013/5/31 Page 434 TMPM361F10FG In the interrupt processing for terminating the reception of 1-bit data, the stop condition is generated to terminate the data transfer. SCLx pin 9 SDAx pin 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 1 Acknowlegment signal to transmitter “High” INTSBIx interrupt request Read receive data aftwer clear to “0” Read receive data after set to “001”. Master output Slave output Figure 14-12 Terminating Data Transmission in the Master Receiver Mode Example: When receiving N data word INTSBIx interrupt (after data transmission) 7 6 5 4 3 2 1 0 X X X 0 X X X SBIxCR1 ← X Reg. ← SBIxDBR Sets the number of bits of data to be received and specify whether ACK is required. Reads dummy data. End of interrupt INTSBIx interrupt (first to (N-2)th data reception) 7 Reg. ← 6 5 4 3 2 1 0 SBIxDBR Reads the first to (N-2)th data words. End of interrupt INTSBIx interrupt ((N-1)th data reception) 7 6 5 4 3 2 1 0 SBIxCR1 ← X X X 0 0 X X X Reg. ← SBIxDBR Disables generation of acknowledgement clock. Reads the (N-1)th data word. End of interrupt INTSBIx interrupt (Nth data reception) 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 0 1 0 0 X X X Reg. ← SBIxDBR Disables generation of acknowledgement clock. Reads the Nth data word. End of interrupt INTSBIx interrupt (after completing data reception) Processing to generate the stop condition. Terminates the data transmission. End of interrupt Note:X; Don’t care Page 435 2013/5/31 14. 14.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C 14.6.3.2 TMPM361F10FG Slave mode ( = "0") In the slave mode, the SBI generates the INTSBIx interrupt request on four occasions: 1) when the SBI has received any slave address from the master. 2) when the SBI has received a general-call address. 3) when the received slave address matches its address. 4) when a data transfer has been completed in response to a general-call. Also, if the SBI detects Arbitration Lost in the master mode, it switches to the slave mode. Upon the completion of data word transfer in which Arbitration Lost is detected, the INTSBIx interrupt request is generated, is cleared to "0", and the SCL pin is pulled to the "Low" level. When data is written to or read from SBIxDBR or when is set to "1", the SCLx pin is released after a period of tLOW. In the slave mode, the normal slave mode processing or the processing as a result of Arbitration Lost is carried out. SBIxSR, , and are tested to determine the processing required. "Table 14-2 Processing in Slave Mode"shows the slave mode states and required processing. Example: When the received slave address matches the SBI's own address and the direction bit is "1" in the slave receiver mode. INTSBIx interrupt if TRX = 0 Then go to other processing. if AL = 0 Then go to other processing. if AAS = 0 Then go to other processing. SBIxCR1 ← X X X 1 0 X X X Sets the number of bits to be transmitted. SBIxDBR ← X X X X X X X X Sets the transmit data. Note:X; Don’t care 2013/5/31 Page 436 TMPM361F10FG Table 14-2 Processing in Slave Mode 1 1 0 1 0 1 State 0 0 In the slave transmitter mode, the SBI has completed a transmission of one data word. 1 1/0 Arbitration Lost is detected while a slave address is being transmitted, and the SBI receives either a slave address with the direction bit "0" or a generalcall address transmitted by another master. 0 0 1 1/0 In the slave receiver mode, the SBI received either a slave address with the direction bit "0" or a generalcall address transmitted by the master. 0 1/0 In the slave receiver mode, the SBI has completed a reception of a data word. 0 1 0 0 Processing Arbitration Lost is detected while the slave address was being transmitted and the SBI received a slave address with the direction bit "1" transmitted by anSet the number of bits in a data word to other master. and write the transmit data into SBIxDBR. In the slave receiver mode, the SBI received a slave address with the direction bit "1" transmitted by the master. Arbitration Lost is detected while a slave address or a data word is being transmitted, and the transfer is terminated. Page 437 Test LRB. If it has been set to "1", that means the receiver does not require further data. Set to 1 and reset to 0 to release the bus. If has been reset to "0", that means the receiver requires further data. Set the number of bits in the data word to and write the transmit data to the SBIxDBR. Read the SBIxDBR (a dummy read) to set to 1, or write "1" to . Set the number of bits in the data word to and read the received data from SBIxDBR. 2013/5/31 14. 14.6 Serial Bus Interface (I2C/SIO) Data Transfer Procedure in the I2C Bus ModeI2C 14.6.4 TMPM361F10FG Generating the Stop Condition When SBIxSR is "1", writing "1" to SBIxCR2 and "0" to causes the SBI to start a sequence for generating the stop condition on the bus. Do not alter the contents of until the stop condition appears on the bus. If another device is holding down the SCL bus line, the SBI waits until the SCL line is released. After that, the SDA pin goes "High", causing the stop condition to be generated. SBIxCR2 ← 7 6 5 4 3 2 1 0 1 1 0 1 1 0 0 0 Generates the stop condition. "1"→ "1"→ "0"→ "1"→ Stop condition SCLx pin SDAx pin (Read) Figure 14-13 Generating the Stop Condition 14.6.5 Restart Procedure Restart is used when a master device changes the data transfer direction without terminating the transfer to a slave device.The procedure of generating a restart in the master mode is described below. First, write SBIxCR2 to "0" and write "1" to to release the bus. At this time, the SDAx pin is held at the "High" level and the SCLx pin is released. Because no stop condition is generated on the bus, other devices recognize that the bus is busy. Then, test SBIxSR and wait until it becomes "0" to ensure that the SCLx pin is released. Next, test and wait until it becomes "1" to ensure that no other device is pulling the SCLx bus line to the "Low" level. Once the bus is determined to be free by following the above procedures, follow the procedures described in "14.6.2 Generating the Start Condition and a Slave Address"to generate the start condition. To satisfy the setup time of restart, at least 4.7μs wait period (in the standard mode) must be created by the software after the bus is determined to be free. Note 1: Do not write to "0" when it is "0". (Restart cannot be initiated.) Note 2: When the master device is acting as a receiver, data transmission from the slave device which serves as a transmitter must be completed before generating a restart. To complete data transfer, slave device must receive a "High" level acknowledge signal. For this reason, before generating a restart becomes "1", the rising edge of the SCL line is not detected even = 2013/5/31 Page 438 TMPM361F10FG "1" is confirmed by following the restart procedure. To check the status of the SCL line, read the port. SBIxCR2 ← 7 6 5 4 3 2 1 0 0 0 0 1 1 0 0 0 Releases the bus. if SBIxSR ≠ 0 Checks that the SCL pin is released. Then if SBIxSR ≠ 1 Checks that no other device is pulling the SCL pin to the "Low". Then 4.7 μs Wait SBIxCR1 ← X X X 1 0 X X X Selects the acknowledgment mode. SBIxDBR ← X X X X X X X X Sets the desired slave address and direction. SBIxCR2 ← 1 1 1 1 1 0 0 0 Generates the start condition. Note:X; Don’t care "0"→ "0"→ "0"→ "1"→ "1"→ "1"→ "1"→ "1"→ 4.7 ms (min.) Start condition SCL(Bus) SCL pin 9 SDA pin Figure 14-14 Timing Chart of Generating a Restart Page 439 2013/5/31 14. 14.7 Serial Bus Interface (I2C/SIO) Control register of SIO mode 14.7 TMPM361F10FG Control register of SIO mode The following registers control the serial bus interface in the clock-synchronous 8-bit SIO mode and provide its status information for monitoring. 14.7.1 SBIxCR0(control register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SBIEN - - - - - - - After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 SBIEN R/W Serial bus interface operation. 0:Disable 1: Enable Enable this bit before using the serial bus interface. If this bit is disabled, power consumption can be reduced because all clocks except SBIxCR0 stop. If the serial bus interface operation is enabled and then disabled, the settings will be maintained in each register. 6-0 2013/5/31 - R Read as 0. Page 440 TMPM361F10FG 14.7.2 SBIxCR1(Control register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol SIOS SIOINH After reset 0 0 Bit Bit Symbol SIOM - 0 0 SCK 1 Type 0 0 0(Note 1) Function 31-8 - R Read as 0. 7 SIOS R/W Transfer Start/Stop 0: Stop 1: Start 6 SIOINH R/W Transfer 0: Continue 1: Forced termination 5-4 SIOM[1:0] R/W Select transfer mode 00: Transmit mode 01: Reserved 10:Transmit/receive mode 11:Receive mode 3 - R Read as 1. 2-0 SCK[2:0] R/W On writing : Select serial clock frequency. (Note 1) 000 n=3 4 MHz 001 n=4 2 MHz 010 n=5 1 MHz 011 n=6 500 kHz 100 n=7 250 kHz Clock gear: fc/1 101 n=8 125 kHz Frequency = 110 n=9 62.5 kHz 111 − System clock: fsys ( = 64MHz ) fsys/2 2n [Hz] External clock Note 1: After a reset, the bit is read as "1". However, if the SIO mode is selected at the SBIxCR2 register, the initial value is read as "0". In this document, the value written in the column "after reset" is the value after setting the SIO mode in the initial state. The descriptions of the SBIxCR2 register and the SBIxSR register are the same. Note 2: Set to "0" and to "1" before programming the transfer mode and the serial clock. Page 441 2013/5/31 14. 14.7 Serial Bus Interface (I2C/SIO) Control register of SIO mode 14.7.3 TMPM361F10FG SBIxDBR (Data buffer register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol DB After reset Bit 0 0 Bit Symbol 0 0 Type Function 31-8 - R Read as 0. 7-0 DB[7:0] R Receive data W Transmit data Note 1: The transmission data must be written in to the register from the MSB (bit 7). The received data is stored in the LSB. Note 2: Since SBIxDBR has independent buffers for writing and reading, a written data cannot be read. Thus, readmodify-write instructions, such as bit manipulation, cannot be used. 2013/5/31 Page 442 TMPM361F10FG 14.7.4 SBIxCR2(Control register 2) This register serves as SBIxSR register by writing to it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 3 2 1 0 7 6 5 4 bit symbol - - - - After reset 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) Bit Bit Symbol Type SBIM 0 0 - - 1(Note 1) 1(Note 1) Function 31-8 - R Read as "0". 7-4 - R Read as 1. (Note 1) 3-2 SBIM[1:0] W Select serial bus interface operating mode (Note 2) 00: Port mode 01: SIO mode 10: I2Cbus mode 11: Reserved 1-0 - R Read as 1. (Note 1) Note 1: In this document, the value written in the column "after reset" is the value after setting the SIO mode in the initial state. Note 2: Make sure that modes are not changed during a communication session. Page 443 2013/5/31 14. 14.7 Serial Bus Interface (I2C/SIO) Control register of SIO mode 14.7.5 TMPM361F10FG SBIxSR (Status Register) This register serves as SBIxCR2 by writing to it. 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - SIOF SEF - - After reset 1(Note 1) 1(Note 1) 1(Note 1) 1(Note 1) 0 0 1(Note 1) 1(Note 1) Bit Bit Symbol Type Function 31-8 - R Read as 0. 7-4 - R Read as 1.(Note 1) 3 SIOF R Serial transfer status monitor. 0: Completed 1: In progress 2 SEF R Shift operation status monitor 0: Completed. 1: In progress 1-0 - R Read as 1. (Note 1) Note:In this document, the value written in the column "after reset" is the value after setting the SIO mode in the initial state. 2013/5/31 Page 444 TMPM361F10FG 14.7.6 SBIxBR0 (Baud rate register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - I2SBI - - - - - - After reset 1 0 1 1 1 1 1 0 Bit Bit Symbol Type Function 31-8 - R Read as 0. 7 - R Read as 1. 6 I2SBI R/W Operation in IDLE mode. 0: Stop 1: Operate 5-1 - R Read as 1. 0 - R/W Make sure to write "0". Page 445 2013/5/31 14. 14.8 Serial Bus Interface (I2C/SIO) Control in SIO mode 14.8 TMPM361F10FG Control in SIO mode 14.8.1 Serial Clock 14.8.1.1 Clock source Internal or external clocks can be selected by programming SBIxCR1. (1) Internal clocks In the internal clock mode, one of the seven frequencies can be selected as a serial clock, which is output to the outside through the SCKx pin. At the beginning of a transfer, the SCKx pin output becomes the "High" level. If the program cannot keep up with this serial clock rate in writing the transmit data or reading the received data, the SBI automatically enters a wait period. During this period, the serial clock is stopped automatically and the next shift operation is suspended until the processing is completed. $XWRPDWLFZDLW SCKx pin output SOx pin output :ULWHWKH WUDQVPLWGDWD 1 a0 2 3 7 8 a1 a2 a5 a6 a7 a 1 2 6 7 b0 b1 b4 b5 b6 b 8 1 b7 c0 2 3 c1 c2 c Figure 14-15 Automatic Wait (2) External clock ( = "111") The SBI uses an external clock supplied from the outside to the SCKx pin as a serial clock. For proper shift operations, the serial clock at the "High" and "Low" levels must have the pulse widths as shown below. SCKx pin fSCKL fSCKH fSCKL, fSCKH > 4/fsys Figure 14-16 Maximum Transfer Frequency of External Clock Input 2013/5/31 Page 446 TMPM361F10FG 14.8.1.2 Shift Edge Leading-edge shift is used in transmission. Trailing-edge shift is used in reception. - Leading-edge shift Data is shifted at the leading edge of the serial clock (or the falling edge of the SCKx pin input/output). - Trailing-edge shift Data is shifted at the trailing edge of the serial clock (or the rising edge of the SCKx pin input/output). SCKx pin SOx pin Shift register bit 0 bit 1 bit 2 bit 3 bit 4 76543210 *7654321 **765432 ***76543 ****7654 bit 5 bit 6 bit 7 *****765 ******76 *******7 bit 5 bit 6 bit 7 (a) Leading-edge SCKx pin SIx pin Shift register bit 0 ******** bit 1 0******* bit 2 10****** bit 3 210***** bit 4 3210**** 43210*** 543210** 6543210* 76543210 (b) Trailing-edge Figure 14-17 Shift Edge Page 447 2013/5/31 14. 14.8 Serial Bus Interface (I2C/SIO) Control in SIO mode 14.8.2 TMPM361F10FG Transfer Modes The transmit mode, the receive mode or the transmit/receive mode can be selected by programming SBIxCR1. 14.8.2.1 8-bit transmit mode Set the control register to the transmit mode and write the transmit data to SBIxDBR. After writing the transmit data, writing "1" to SBIxCR1 starts the transmission. The transmit data is moved from SBIxDBR to a shift register and output to the SO pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the transmit data is transferred to the shift register, SBIxDBR becomes empty, and the INTSBIx (buffer-empty) interrupt is generated, requesting the next transmit data. In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if next data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared when SBIxDBR is loaded with the next transmit data. In the external clock mode, SBIxDBR must be loaded with data before the next data shift operation is started. Therefore, the data transfer rate varies depending on the maximum latency between when the interrupt request is generated and when SBIxDBR is loaded with data in the interrupt service program. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting SBIxSR to "1" to the falling edge of SCK. Transmission can be terminated by clearing to "0" or setting to "1" in the INTSBIx interrupt service program. If is cleared, remaining data is output before transmission ends. The program checks SBIxSR to determine whether transmission has come to an end. is cleared to "0" at the end of transmission. If is set to "1", the transmission is aborted immediately and is cleared to "0". When in the external clock mode, must be cleared to "0" before next data shifting. If does not be cleared to "0" before next data shifting, SBI output dummy data and stopped. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 0 0 0 X X X Selects the transmit mode. SBIxDBR ← X X X X X X X X Writes the transmit data. SBIxCR1 ← 1 0 0 0 0 X X X Starts transmission. X X X X X X X Writes the transmit data. INTSBIx interrupt SBIxDBR 2013/5/31 ← X Page 448 TMPM361F10FG is cleared SCKx pin(output) SOx pin a0 * a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 b6 b7 INTSBIx interrupt request SBIxDBR a b (a) Internal clock :ULWHWKHWUDQVPLWGDWD is cleared. SCKx pin(input) SOx pin a0 * a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 INTSBIx interrupt request SBIxDBR a b (b)External clock :ULWHWKHWUDQVPLWGDWD Figure 14-18 Transmit Mode Example: Example of programming (external clock) to terminate transmission by 7 6 5 4 3 2 1 0 if SBIxSR ≠ 0 Recognizes the completion of the transmission. Then Recognizes "1" is set to the SCK pin by monitoring the port. if SCK ≠ 1 Then SBIxCR1 ← 0 0 0 0 0 1 1 1 Page 449 Completes the transmission by setting = 0. 2013/5/31 14. 14.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM361F10FG 14.8.2.2 8-bit receive mode Set the control register to the receive mode. Then writing "1" to SBIxCR1 enables reception.Data is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the shift register is loaded with the 8-bit data, it transfers the received data to SBIxDBR and the INTSBIx (buffer-full) interrupt request is generated to request reading the received data. The interrupt service program then reads the received data from SBIxDBR. In the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the received data is read from SBIxDBR. In the external clock mode, shift operations are executed in synchronization with the external clock. The maximum data transfer rate varies, depending on the maximum latency between generating the interrupt request and reading the received data Reception can be terminated by clearing to "0" or setting to "1" in the INTSBIx interrupt service program. If is cleared, reception continues until all the bits of received data are written to SBIxDBR. The program checks SBIxSR to determine whether reception has come to an end. is cleared to "0" at the end of reception. After confirming the completion of the reception, last received data is read. If is set to "1", the reception is aborted immediately and is cleared to "0". (The received data becomes invalid, and there is no need to read it out.) Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 1 1 0 X X X Selects the receive mode. SBIxCR1 ← 1 0 1 1 0 X X X Starts reception. INTSBIx interrupt Reg. 2013/5/31 ← SBIxDBR Reads the received data. Page 450 TMPM361F10FG Clear SCKx pin(output) SIx pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSBIx interrupt request SBIxDBR a b Read receive data Read receive data Figure 14-19 Receive Mode (Example: Internal Clock) 14.8.2.3 8-bit transmit/receive mode Set the control register to the transfer/receive mode. Then writing the transmit data to SBIxDBR and setting SBIxCR1 to "1" enables transmission and reception.The transmit data is output through the SOx pin at the falling of the serial clock, and the received data is taken in through the SI pin at the rising of the serial clock, with the least-significant bit (LSB) first. Once the shift register is loaded with the 8bit data, it transfers the received data to SBIxDBR and the INTSBIx interrupt request is generated.The interrupt service program reads the received data from the data buffer register and writes the next transmit data. Because SBIxDBR is shared between transmit and receive operations, the received data must be read before the next transmit data is written. In the internal clock operation, the serial clock will be automatically in the wait state until the received data is read and the next transmit data is written. In the external clock mode, shift operations are executed in synchronization with the external serial clock. Therefore, the received data must be read and the next transmit data must be written before the next shift operation is started.The maximum data transfer rate for the external clock operation varies depending on the maximum latency between when the interrupt request is generated and when the transmit data is written. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting to "1" to the falling edge of SCK. Transmission and reception can be terminated by clearing to "0" or setting SBIxCR1 to "1" in the INTSBIx interrupt service program. If is cleared, transmission and reception continue until the received data is fully transferred to SBIxDBR. The program checks SBIxSR to determine whether transmission and reception have come to an end. is cleared to "0" at the end of transmission and reception.If is set to "1", the transmission and reception is aborted immediately and is cleared to "0". Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing transmission and reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. Page 451 2013/5/31 14. 14.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM361F10FG is cleard. SCKx pin(output) SOx pin * SIx pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 INTSBIx interrupt request SBIxDBR c a Write the transmitted data(a) Read the received data(c) b Write the transmitted data(b) d Read the received data(d) Figure 14-20 Transmit/Receive Mode (Example: Internal Clock) 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 1 0 0 X X X Selects the transmit mode. SBIxDBR ← X X X X X X X X Writes the transmit data. SBIxCR1 ← 1 0 1 0 0 X X X Starts reception/transmission. INTSBIx interrupt Reg. ← SBIxDBR SBIxDBR ← X 14.8.2.4 X Reads the received data. X X X X X X Writes the transmit data. Data retention time of the last bit at the end of transmission Under the condition SBIxCR1= "0", the last bit of the transmitted data retains the data of SCK rising edge as shown below. Transmit mode and transmit/receive mode are the same. SCKx pin SOx pin bit 6 Bit 7 of end of transmitted word tSODH = Min. 4/fsys [s] Figure 14-21 Data retention time of the last bit at the end of transmission 2013/5/31 Page 452 TMPM361F10FG 15. Consumer Electronics Control (CEC) 15.1 Outline The CEC function transmits and receives data that conforms to Consumer Electronics Control (hereafter referred to as CEC) protocol. It can operate conformably to HDMI 1.3a specifications. 15.1.1 Reception ・ Clock sampling at fs clock or TBAOUT which is output of 16bit Timer/Event counters -Adjustable noise canceling time ・ Data reception per 1byte -Flexible data sampling point -Data reception is available even when an address discrepancy is detected. ・ Error detection -Cycle error (min./max.) -ACK collision -Waveform error 15.1.2 Transmission ・ Data transmission per 1byte -Triggered by auto-detection of bus free state ・ Flexible waveform -Adjustable rising edge and cycle ・ Error detection -Arbitration lost -ACK response error 15.1.3 Precautions When data reception at logical address discrepancy is enabled(CECRCR1 = "1"), if the initiator sends a new message beginning with the start bit without having sent the last block with EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt is generated. Then, the receive operation is performed in the usual way. Page 453 2013/5/31 2013/5/31 Receive Control Registers 㧔CECREN) 㧔CECRCR1 - 3) Page 454 Receive Buffer 㧔CECRBUF) Shift Register Figure 15-1 Block Diagram of CEC Transmit error flag 㧔CECTSTAT) Internal data bus Receive error flag 㧔CECRSTAT) Interrupt control Whole control Transmit Buffer 㧔CECTBUF) Shift Register Transmit Control Transmit Control Register 㧔CECTEN) 㧔CECTCR) Sampling Clock Selected Register (CECFSSEL) System clock 㧔fsys) Receive Interrupt (INTCECRX) Transmit Interrupt (INTCECTX) 16 bit timer flip-flop output 㧔TBAOUT) Low-speed clock 㧔fs) 15.2 Receive Control Noise filter Sampling clock 15.2 CEC 15. Consumer Electronics Control (CEC) Block Diagram TMPM361F10FG Block Diagram Figure 15-1 shows the Block Diagram of CEC TMPM361F10FG 15.3 Registers 15.3.1 Register List The control registers and address for CEC are as follows. Base Address = 0x400E_2000 Registers Address (Base+) CEC Enable Register CECEN 0x0000 Logical Address Register CECADD 0x0004 Software Reset Register CECRESET 0x0008 Receive Enable Register CECREN 0x000C Receive Buffer Register CECRBUF 0x0010 Receive Control Register 1 CECRCR1 0x0014 Receive Control Register 2 CECRCR2 0x0018 Receive Control Register 3 CECRCR3 0x001C Transmit Enable Register CECTEN 0x0020 Transmit Buffer Register CECTBUF 0x0024 Transmit Control Register CECTCR 0x0028 Receive Interrupt Status Register CECRSTAT 0x002C Transmit Interrupt Status Register CECTSTAT 0x0030 CEC Sampling Clock Selected Register CECFSSEL 0x0034 Page 455 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG 15.3.2 CECEN (CEC Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - CECEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-3 − R Read as 0. 2 − R/W Write "0". 1 − R/W Write as "1". 0 CECEN R/W CEC operation 0 : Disabled 1 : Enabled Specifies the CEC operation. Enable CEC before using. When the CEC operation is disabled, no clocks are supplied to the CEC module except for the CECEN register. Thus power consumption can be reduced. When CEC is disabled after it was enabled, each register setting is maintained. 2013/5/31 Page 456 TMPM361F10FG 15.3.3 CECADD (Logical Address Register ) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After reset CECADD[15:8] bit symbol After reset Bit CECADD[7:0] 0 Bit Symbol 0 0 0 Type Function 31-16 − R Read as 0. 15-0 CECADD[15:0] R/W Logical address 15 to 0 Specifies the logical address assigned to CEC. Multiple addresses can be set simultaneously since each bit corresponds with each address. Note:A broadcast message is received regardless of the register setting. By allocating a logical address of a device to 15, logical "0" is sent as an ACK response to the broadcast message. Page 457 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG 15.3.4 CECRESET (Software Reset Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - CECRESET After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type FUnction 31-1 − R Read as 0 0 CECRESET W Software reset 0: Disabled 1: Enabled Stops all the CEC operation and initializes the register. Setting this bit to "1" affects as follows: Reception: Stops immediately. The received data is discarded. Transmission (including the CEC line): Stops immediately. Register: All the registers other than CECEN are initialized. Read as 0. 2013/5/31 Page 458 TMPM361F10FG 15.3.5 CECREN (Receive Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - CECREN After reset 0 0 0 0 0 0 0 Undefined Bit Bit Symbol Type Function 31-1 − R Read as 0 0 CECREN R/W Reception control [Write] 0 : Disabled 1 : Enabled [Read] 0 : Stopped 1 : In operation Controls the reception operation of CEC. Writing "0" or "1" to this bit enables or disables data reception. This bit becomes ready for data reception by writing "1". The state of the reception circuit is monitored by reading this bit. It enables you to check if what you set has properly been reflected. Note 1: Enable the bit after setting the CECRCR1, CECRCR2 and CECRCR3. Note 2: It takes a little time to reflect the setting of the bit to the circuit. Make sure that the register is under suspension when you try to change settings or to enable disableed-settings. Page 459 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG 15.3.6 CECRBUF (Receive Buffer Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - CECACK CECEOM After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol CECRBUF After reset Bit 0 Bit Symbol 0 0 0 Type Function 31-10 − R Read as 0. 9 CECACK R ACK bit 8 CECEOM R 7-0 CECRBUF[7:0] R Reads the received ACK bit. EOM bit Reads the received EOM bit. Received data Reads one byte of data received. The bit 7 is the MSB. Note 1: Writing to this register is ignored. Note 2: Read this register as soon as a receive interrupt is generated. The subsequent reading data may not be ensured. 2013/5/31 Page 460 TMPM361F10FG 15.3.7 CECRCR1 (Receive Control Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - CECACKDIS After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - bit symbol After reset - CECLNC 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 5 4 3 bit symbol - After reset 0 0 7 6 bit symbol - After reset 0 Bit CECHNC Bit Symbol CECMIN - CECDAT 0 CECMAX 0 2 CECTOUT 0 0 Type 0 0 0 1 0 CECRIHLD CECOTH 0 0 0 Function 31-25 − R Read as 0. 24 CECACKDIS R/W Logical "0" as ACK response 0: send 1: not send Specifies if logical "0" is sent or not as an ACK response to the data block when destination address corresponds with the address set in the logical address register. (Logical "0" is sent to the header block as an ACK response regardless of the bit setting when detecting the addresses corresponding) 23-22 − R Read as 0. 21-20 CECHNC[1:0] R/W The number of "High" samplings for noise cancellation. 00: None 01: 1/fs (two consecutive fs clocks observed.) 10: 2/fs (three consecutive fs clocks observed.) 11: 3/fs (four consecutive fs clocks observed.) (one time of fs clock observed.) Specifies the time of the noise cancellation for each 1/fs when detecting "High". It is considered as noise if "High"s of the same number as the specified cycles are not sampled. 19 − R Read as 0. 18-16 CECLNC[2:0] R/W The number of "Low" samplings for noise cancellation. 000: None (one time of fs clock observed.) 100: − (Reserved) 001: 1/fs (two consecutive fs clocks observed) 101: − (Reserved) 010: 2/fs (three consecutive fs clocks observed) 110: − (Reserved) 011: 3/fs (four consecutive fs clocks observed.) 111: − (Reserved) Specifies the time of the noise cancellation for each 1/fs when detecting "Low". It is considered as noise if "Low"s of the same number as the specified cycles are not sampled. 15 − R Read as 0. 14-12 CECMIN[2:0] R/W Time to identify as minimum cycle error 000: 67/fs (approx.2.045ms) 100: 001: 67/fs + 1/fs 101: 67/fs − 2/fs 010: 67/fs + 2/fs 110: 67/fs − 3/fs 011: 67/fs + 3/fs 111: 67/fs − 4/fs 67/fs − 1/fs Specifies the minimum time to identify a valid bit. Base time is 67/fs (approx.2.045) ms. Enables to specify it between the ranges −4/fs to +3/fs by the unit of 1/fs. An interrupt is generated and "Low" is output to CEC for approx. 3.63 ms when one bit cycle is shorter than the specified time. 11 − R Read as 0. Page 461 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG Bit 10-8 Bit Symbol CECMAX[2:0] Type R/W Function Time to identify as maximum cycle error 000: 90/fs (approx. 2.747ms) 100: 001: 90/fs + 1/fs 101: 90/fs − 2/fs 010: 90/fs + 2/fs 110: 90/fs − 3/fs 011: 90/fs + 3/fs 111: 90/fs − 4/fs 90/fs − 1/fs Specifies the maximum time to identify as a valid bit. Base time is 90/fs (approx.2.747 ms). Enables to specify it between the ranges −4/fs to +3/fs by the unit of 1/fs. An interrupt is generated when one bit cycle is longer than the specified time. 7 − R Read as 0. 6-4 CECDAT[2:0] R/W Point of determining the data as 0 or 1. 000: 34/fs (approx. 1.038ms) 100: 001: 34/fs + 2/fs 101: 34/fs − 4/fs 010: 34/fs + 4/fs 110: 34/fs − 6/fs 011: 34/fs + 6/fs 111: Reserved 34/fs − 2/fs Specifies the point of determining the data as logical "0" or logical "1". Base time is 34/fs (approx.1.038 ms). Enables to specify it within ±6/fs by the unit of 2/fs. 3-2 CECTOUT[1:0] R/W Cycle to identify timeout 00: 1 bit cycle 01: 2 bit cycle 10: 3 bit cycle 11: Reserved Specifies the time to determine a timeout. Enables to specify it between 1 bit and 3 bits for each bit cycle. This setting is used to detect a timeout when the bit is valid. 1 CECRIHLD R/W Error interrupt suspend 0: Not suspended 1: Suspended Specifies whether to suspend a receive error interrupt (maximum cycle error, buffer overrun and waveform error). Setting "1" generates no interrupt at the error detection. If data continues to an ACK bit, an ACK response is executed by a reversed logic. If the subsequent bits are interrupted, it is determined as a timeout, based on the setting in . After the ACK response or the timeout determination, an interrupt is generated. 0 CECOTH R/W Data reception at logical address discrepancy 0: Not received 1: Received Specifies whether to receive data when the destination address does not correspond with the address set in the CECADD register. Note 1: The settings in , and are also used in receiving an ACK response at transmission. Note 2: Changing the configurations during transmission or reception may harm its proper operation. Before the change, set the CECREN bit to disable the reception and read the bit and the CECTEN bit to ensure that the operation is stopped. Note 3: A broadcast message is received regardless of the register setting. Note 4: must be used under the same setting as CECTCR. 2013/5/31 Page 462 TMPM361F10FG 15.3.8 CECRCR2 (Receive Control Register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 5 4 3 2 bit symbol - After reset 0 0 7 6 bit symbol - After reset 0 Bit CECSWAV3 - CECSWAV1 0 Bit Symbol CECSWAV2 - 0 0 Type 0 0 1 0 CECSWAV0 0 0 0 0 Function 31-15 − R Read as 0. 14-12 CECSWAV3[2:0] R/W Max. cycle to detect start bit. 000: 154/fs (approx. 4.700 ms) 100: 154/fs + 4/fs 001: 154/fs + 1/fs 101: 154/fs + 5/fs 001: 154/fs + 2/fs 110: 154/fs + 6/fs 011: 154/fs + 3/fs 111: 154/fs + 7/fs 11 − R Read as 0. 10-8 CECSWAV2[2:0] R/W Min. cycle to detect start bit. 000: 141/fs (approx. 4.303 ms) 100: 141/fs − 4/fs 001: 141/fs − 1/fs 101: 141/fs − 5/fs 001: 141/fs − 2/fs 110: 141/fs − 6/fs 011: 141/fs − 3/fs 111: 141/fs − 7/fs 7 − R Read as 0. 6-4 CECSWAV1[2:0] R/W Max. time of start bit rising timing. 000: 128/fs (approx. 3.906 ms) 100: 128/fs + 4/fs 001: 128/fs + 1/fs 101: 128/fs + 5/fs 001: 128/fs + 2/fs 110: 128/fs + 6/fs 011: 128/fs + 3/fs 111: 128/fs + 7/fs 3 − R Read as 0. 2-0 CECSWAV0[2:0] R/W Min. time of start bit rising timing. 000: 115/fs (approx. 3.510 ms) 100: 115/fs − 4/fs 001: 115/fs − 1/fs 101: 115/fs − 5/fs 001: 115/fs − 2/fs 110: 115/fs − 6/fs 011: 115/fs − 3/fs 111: 115/fs − 7/fs : Specifies the cycles to detect a start bit. : is for the maximum cycles. The base time is 154/fs (approx.4.700 ms). Enables to specify it between the ranges 0 to +7/fs by the unit of 1/fs. is for the minimum cycles. The base time is 141/fs (approx.4.303 ms). Enables to specify it between the ranges 0 to -7/fs by the unit of 1/fs. : Specifies the rising timing of a start bit in its detection. : is for the maximum time of the rising timing. The base time is 128/fs (approx.3.906 ms). Enables to specify it between the ranges 0 to +7/fs by the unit of 1/fs. is for the minimum time of the rising timing. The base time is 115/fs (approx.3.510 ms). Enables to specify it between the ranges 0 to -7/fs by the unit of 1/fs. Page 463 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG Note:Changing the configurations during reception may harm its proper operation. Before the change, set CECREN to disable the reception and read the bit to ensure that the operation is stopped. 2013/5/31 Page 464 TMPM361F10FG 15.3.9 CECRCR3 (Receive Control Register 3 ) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset - CECWAV3 - CECWAV2 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - After reset 0 0 CECWAV1 0 0 0 0 CECWAV0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - CECWAVEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-23 − R Read as 0. 22-20 CECWAV3[2:0] R/W The latest rising timing of logical "0" determined as proper waveform. 000: 56/fs (approx. 1.709 ms) 100: 56/fs + 4/fs 001: 56/fs + 1/fs 101: 56/fs + 5/fs 001: 56/fs + 2/fs 110: 56/fs + 6/fs 011: 56/fs + 3/fs 111: 56/fs + 7/fs 19 − R Read as 0. 18-16 CECWAV2[2:0] R/W The fastest rising timing of logical "0" deterrmined as proper. 000: 43/fs (approx.1.312 ms) 100: 43/fs − 4/fs 001: 43/fs − 1/fs 101: 43/fs − 5/fs 010: 43/fs − 2/fs 110: 43/fs − 6/fs 011: 43/fs − 3/fs 111: 43/fs − 7/fs 15 − R Read as 0. 14-12 CECWAV1[2:0] R/W The latest rising timing of logical "1" determined as proper waveform. 000: 26/fs (approx. 0.793 ms) 100: 26/fs + 4/fs 001: 26/fs + 1/fs 101: 26/fs + 5/fs 001: 26/fs + 2/fs 110: 26/fs + 6/fs 011: 26/fs + 3/fs 111: 26/fs + 7/fs 11 − R Read as 0 10-8 CECWAV0[2:0] R/W The fastest rising timing of logical "1" determined as proper. 000: 13/fs (approx. 0.396 ms) 100: 13/fs − 4/fs 001: 13/fs − 1/fs 101: 13/fs − 5/fs 010: 13/fs − 2/fs 110: 13/fs − 6/fs 011: 13/fs − 3/fs 111: 13/fs − 7/fs 7-2 − R Read as 0. 1 CECRSTAEN R/W Start bit detection 1: Enable 0: Disable Detects a reception of start bit and generates interrupt. 0 CECWAVEN R/W Waveform error detection 1: Enable 0: Disable Detects a received waveform does not identical to the one defined and generates waveform error interrupt. If enabled, an error is detected according to the setting of . Page 465 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG : This setting is enabled when the bit is set to "1". By setting these bits, an error is detected if rising edge of the received waveform comes later than that of proper logical "0". Base time is 56/fs (approx. 1.709ms). Enables to specify it between the ranges 0 to +7/fs by the unit of 1/fs. The received waveform is considered to be an error if a rising edge is not detected from the start point of the bit to the value specified in . : This setting is enabled when the bit is set to "1". : By setting these bits, an error is detected if rising edge of the received waveform comes faster than logical "0" and later than that of proper logical "1". Base time for bit is 26/fs (approx. 0.793ms). Enables to specify it between the ranges 0 to +7/fs by the unit of 1/fs. Base time for bit is 43/fs (approx.1.312ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/fs. If a rising edge is detected during bit and bit setting, an error occurs. : This setting is enabled when the bit is set to "1". By setting these bits, an error is detected if rising edge of the received waveform comes faster than that of proper logical "1". Base time is 13/fs (approx. 0.396ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/fs. The received waveform is considered to be an error if a rising edge is not detected from a start point of the bit to the value specified in . Note:Changing the configurations during reception may harm its proper operation. Before the change, set CECREN to disable the reception and read the bit to ensure that the operation is stopped. 2013/5/31 Page 466 TMPM361F10FG 15.3.10 CECTEN (Transmit Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - CECTRANS CECTEN After reset 0 0 0 0 0 0 0 Undefined Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 CECTRANS R Transmission state 0: not in progress 1:in progress Indicates whether the transmission is in progress or not. It indicates "1" upon starting the transmission of the start bit. It indicates "0" if transmission is completed or an interrupt is generated. Writing to this bit is ignored. 0 CECTEN W Transmission control 0: Disable 1: Enable Controls the CEC transmission. Writing this bit enables or disables the transmission. Writing "1" to this bit initiates the transmission. This bit is automatically cleared by a transmit completion interrupt or an error interrupt. Note 1: Set after setting the CECTBUF and CECTCR register. Note 2: Stop transmission and reception before changing the settings or enabling the transmission and reception. Page 467 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG 15.3.11 CECTBUF (Transmit Buffer Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - CECTEOM After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol After reset Bit CECTBUF 0 Bit Symbol 0 0 0 Type Function 31-9 − R Read as 0. 8 CECTEOM R/W EOM bit 7-0 CECTBUF[7:0] R/W Specifies the EOM bit to transmit. Transmitted data Specifies a byte of data to transmit. The bit 7 is the MSB. 2013/5/31 Page 468 TMPM361F10FG 15.3.12 CECTCR (Transmit Control Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol After reset - CECSTRS - 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 3 2 1 0 0 0 bit symbol - After reset 0 0 0 CECDTRS CECDPRD 7 6 5 4 bit symbol - - - CECBRD After reset 0 0 0 0 Bit CECSPRD Bit Symbol Type CECFREE 0 0 Function 31-23 − R Read as 0. 22-20 CECSTRS[2:0] R/W Rising timing of start bit. 000: Base time 100: Base time− 4/fs 001: Base time− 1/fs 101: Base time− 5/fs 010: Base time− 2/fs 110: Base time− 6/fs 011: Base time− 3/fs 111: Base time− 7/fs Specifies the rising timing of a start bit. Base time is 121/fs (approx. 3.693 ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/ fs. 19 − R Read as 0. 18-16 CECSPRD[2:0] R/W Start bit cycle 000: Base time 100: Base time− 4/fs 001: Base time− 1/fs 101: Base time− 5/fs 010: Base time− 2/fs 110: Base time− 6/fs 011: Base time− 3/fs 111: Base time− 7/fs Specifies a cycle of a start bit. Base time is 147/fs (approx. 4.486 ms). Enables to specify it between the ranges 0 to −7/fs by the unit of 1/ fs. 15 − R Read as 0. 14-12 CECDTRS[2:0] R/W Rising timing of data bit. 000: Base time 100: Reserved 001: Base time− 1/fs 101: Reserved 010: Base time− 2/fs 110: Reserved 011: Base time− 3/fs 111: Reserved Specifies the rising timing of a data bit Base time is 20/fs (approx. 0.610 ms, when logical "1") or 49/fs (approx. 1.495 ms, when logical "0"). Enables to specify it between the ranges 0 to −3/fs by the unit of 1/fs. 11-8 CECDPRD[2:0] R/W Data bit cycle 0000: Base time 1000: Base time− 8/fs 0001: Base time− 1/fs 1001: Base time− 9/fs 0010: Base time− 2/fs 1010: Base time− 10/fs 0011: Base time− 3/fs 1011: Base time− 11/fs 0100: Base time− 4/fs 1100: Base time− 12/fs 0101: Base time− 5/fs 1101: Base time− 13/fs 0110: Base time− 6/fs 1110: Base time− 14/fs 0111: Base time− 7/fs 1111: Base time− 15/fs Specifies a cycle of a data bit. Base time is 79/fs (approx. 2.411 ms). Enables to specify it between the ranges 0 to −15/fs by the unit of 1/ fs. Page 469 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG Bit Bit Symbol Type Function 7-5 − R Read as 0. 4 CECBRD R/W Broadcast transmission 0: Not broadcast transmission 1: Broadcast transmission Set this bit to "1" when transmitting a broadcast message. 3-0 CECFREE[3:0] R/W Time of bus to be free 0000: 1bit cycle 1000: 9bit cycle 0001: 2bit cycle 1001: 10bit cycle 0010: 3bit cycle 1010: 11bit cycle 0011: 4bit cycle 1011: 12bit cycle 0100: 5bit cycle 1100: 13bit cycle 0101: 6bit cycle 1101: 14bit cycle 0110: 7bit cycle 1110: 15bit cycle 0111: 8bit cycle 1111: 16bit cycle Specifies time of a bus to be free that checked before transmission. Start transmission after checking the CEC line kept inactive during the specified cycles. Note: must be used under the same setting as CECRCR1. 2013/5/31 Page 470 TMPM361F10FG 15.3.13 CECRSTAT (Receive Interrupt Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - CECRIWAV CECRIOR CECRIACK CECRIMIN CECRIMAX CECRISTA CECRIEND After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-7 − R Read as 0. 6 CECRIWAV R Interrupt flag 0: No wave form error 1: Wave form error Indicates that waveform error is detected. The error occurs when waveform error detection is enabled in CECRCR3 . 5 CECRIOR R Interrupt flag 0: No receive buffer overrun 1:Receive buffer overrun Indicates the receive buffer receives next data before reading the data that had already been set. 4 CECRIACK R Interrupt flag 0: No ACK collision 1: ACK collision Indicates "0" is detected after the specified time to output ACK bit "0". 3 CECRIMIN R Interrupt flag 0: No minimum cycle error 1:Minimum cycle error Indicates one bit cycle is shorter than the minimum cycle error detection time specified in CECRCR1. 2 CECRIMAX R Interrupt flag 0: No maximum cycle error 1: Maximum cycle error Indicates one bit cycle is longer than the maximum cycle error detection time specified in CECRCR1. 1 CECRISTA R Interrupt flag 0: No start bit detection 1: Start bit detection Indicates a start bit is detected. 0 CECRIEND R Interrupt flag 0: Not one byte data reception completed 1: Completion of 1 byte data reception Indicates 1 byte of data reception is completed. Note:Writing to this bit is ignored. Page 471 2013/5/31 15. 15.3 Consumer Electronics Control (CEC) Registers TMPM361F10FG 15.3.14 CECTSTAT (Transmit Interrupt Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - CECTIUR CECTIACK CECTIAL CECTIEND CECTISTA After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-5 − R Read as 0. 4 CECTIUR R Interrupt flag 0: No transmit buffer underrun 1: Transmit buffer underrun Indicates next data has not set to the transmission buffer within a byte of data transmission. 3 CECTIACK R Interrupt flag 0: No ACK error detection 1: ACK error detection Indicates one of the following conditions occurs. ・When logical "0" is not detected in transmission to the specific address. ・When logical "1" is not detected in transmission of a broadcast message. 2 CECTIAL R Interrupt flag 0: No arbitration lost 1: Arbitration lost occurs Indicates "Low" is detected while outputting "High". 1 CECTIEND R Interrupt flag 0: No data transmission completion 1: data transmission is completed Indicates data transmission including the EOM bit is completed. 0 CECTISTA R Interrupt flag 0: No start transmission 1: Start transmission Indicates 1 byte of data transmission is started. Note:Writing to this bit is ignored. 2013/5/31 Page 472 TMPM361F10FG 15.3.15 CECFSSEL(CEC Sampling Clock Select Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - CECCLK After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 CECCLK R/W CEC sampling clock 0: Low-speed clock (fs) 1: TBAOUT Sets the sampling clock for CEC function.Enables to select either low-speed clock (fs) or timer output as of CEC sampling clock.Timer output range is 30kHz to 34kHz by setting TBAOUT. Note:When changing sampling clock by CECFSSEL register, stop (prohibit) CEC operation by CECEN register once. Then set CECFSSEL register first prior to other CEC related registers after starting (permitting) the CEC operation again. And also in the case of software reset by CECRESET register, set CECFSSEL register first prior to other CEC related registers when changing sampling clock. Page 473 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG 15.4 Operations 15.4.1 Sampling clock CEC lines are sampled by a 32.768kHz of low speed clock (fs) or TBAOUT which is output of 16bit Timer/ Event counters. The sampling clock is configurable with the bits of the CECFSSEL register. 15.4.2 Reception 15.4.2.1 Basic Operation If a start bit is detected, a start bit interruption generates. By generating start bit interruption, CECRSTAT is set. The start bit interrupt is generated when the CECRCR3 is set to "1". If one byte data, EOM bit and ACK bit are received, the received data is stored in CECRBUF register, and a received interruption generates. By generating the received interruption, CECRSTAT is set. In the CECRBUF register, 8 bit data, EOM bit and ACK bit are stored. The ACK bit is not generated in the CEC circuit internally. This bit is generated from a observation of CEC signal same as other data. After one data block is received, receiving operation continues until detecting the last block of data with EOM bit set to"1". Detecting the end of last block, CEC becomes the start bit waiting mode. Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit. The received data is discarded. Note:Regarding data reception, please carefully read "15.1.3 Precautions". Start bit interrupt S 2013/5/31 Receiving interrupt H D1 D2 D3 D4 Page 474 Dn-2 Dn-1 Dn TMPM361F10FG 15.4.2.2 Preconfiguration Before receiving data, reception settings to the Logical Address Register , the Receive Control Register 1 , the Receive Control Register 2 and the Receive Control Register 3 are required. (1) Logical Address Configuration Configure logical address assigned to this product to the CECADD register. Multiple addresses can be set simultaneously since every bit in this register corresponds with each address. Note:A broadcast message is received regardless of the CECADD register setting. By allocating a logical address of a device to 15, logical "0" is sent as an ACK response to the broadcast message. (2) Noise Cancellation Time The noise cancellation time is configurable with the and bits of the CECRCR1 register. It is considered as noise if "High"or "Low"of the same number as the specified value are not sampled.You can configure the time to detect "High" and "Low" respectively. A CEC line is monitored at each rising edge of a sampling clock. In the case that the CEC line is changed from "High" to "Low", the change is fully recognized if "Low"s of the same number as specified in the bit are monitored. In the case that the CEC line is changed from "Low" to "High", the change is fully recognized if "High" of the same number as specified in the bit are sampled. Note:Use in the same settings used for CECTCR. The following illustrates the operation of a case that a noise cancelling is configured as = "10" (3 samplings) and = "011" (4 samplings). By cancelling the noise, a signal "1" shifts to "0" after "0" is sampled four times. The signal "0" shifts to "1" after "1" is sampled three times. = 10 (3 samplings) = 011 (4 samplings) CEC line Sampling clock After sampling After noise cancellation Page 475 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG (3) Cycle error Configure CECRCR1 and bits to detect a cycle error. A cycle error can be detected from each sampling clock cycle between the ranges −4/fs to +3/fs by the unit of 1/fs from the minimum value (67/fs, approx. 2.045ms) or the maximum value (90/fs approx. 2.747ms). Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit. The received data is discarded. (4) Point of Determining Data Configure the CECRCR1 bit for the point of determining the data as "0" or "1". Base time is 34/fs (approx.1.038ms) from the start point and also configurable ±6/fs by the unit of 2/fs. Data sampring timing that specification recommends 0.85 ms 0 ms 0.6 ms Recommended period for data sampling 1.25 ms Reference point for data sampling 1.5 ms 1.05 ms 34/fs ± 6/fs (approx.1.038ms) (5) ACK Response Configuring the CECRCR1 bit enables you to specify if logical "0" is sent or not as an ACK response to the data block when destination address corresponds with the address set in the logical address register. Logical "0" issent to the header block as an ACK response regardless of the bit setting of . The following lists the ACK responses. "Yes" indicates that CEC outputs "0" as a response to the ACK signal from a transmission device (ACK bit: logical "0"). "No" indicates that CEC does not output "0" as a response to the ACK signal from a transmission device (ACK bit: logical "1"). 2013/5/31 Page 476 TMPM361F10FG Header block address Register setting Conformity Discrepancy Yes No "0" (responding logical "0") CECRCR1 "1" (not responding logical "0") Data block address Conformity Discrepancy Yes No No No The following describes the ACK response timing. When the falling edge of the ACK bit from the initiator is detected, this IP outputs "Low" for approximately 1.526 ms. The start time of outputting "Low" is specified with CECRCR1 bit that sets the noise cancelling time. Note:Use in the same settings used for CECTCR. Transmission 0.6±0.2 ms 50/fs (approx.1.526ms) Reception 0/fs - 3/fs (0ms to approx. 0.092ms) (6) Receive Error Interrupt Suspend Configure the CECRCR1 bit to specify if a receive error interrupt (maximum cycle error, buffer overrun and waveform error) is suspended or not. Setting "1" generates no interrupt at the error detection. If data continues to the ACK bit, an ACK response is executed by a reversed logic. If the subsequent bits are interrupted, it is determined as a timeout, based on the setting in of the CECRCR1 register. After the ACK response or the timeout determination, an interrupt is generated. Page 477 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG (7) Cycles to Identify Timeout Configure the CECRCR1 bit to specify the time to determine a timeout. This is used when the setting of a receive error interrupt suspension, which is specified in CECRCR1 , is valid. (8) Data Reception at Logical Address Discrepancy By setting CECRCR1 , you can specify if data is received or not when destination address does not correspond with the address set in the CECADD register. In this case, an ordinary data reception is performed and an interrupt is generated by detecting an error. An ACK response is , however, not performed, neither the header block nor the data block. Note 1: A broadcast message is received regardless of the register setting. Note 2: If the initiator sends a new message beginning with the start bit without having sent the last block with EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt is generated. Then, the receive operation is performed in the usual way. (9) Start Bit Detection Configuring the CECRCR2 register allows you to specify the rising timing and a cycle of the start bit detection respectively. is to specify the fastest start bit rising timing. is to specify the latest start bit rising timing (the period that 1. indicates in the figure shown below). is to specify the minimum cycle of a start bit. is to specify the maximum cycle of a start bit (the period that 2. indicates in the figure shown below). If a rising edge during the period 1. and a falling edge during the period 2. are detected, the start bit is considered to be valid. Permissible value of signal transition timing on specification (Start bit) 0 ms 3.5 ms 3.7 ms 4.3 ms 4.7 ms 1. 2. 115/fs ~ 115/fs - 7/fs (approx.3.510ms) 128/fs ~ 128/fs + 7/fs (approx.3.906ms) 2013/5/31 Page 478 154/fs ~ 154/fs + 7/fs (approx.4.700ms) 141/fs - 7/fs ~ 141/fs (approx.4.303ms) TMPM361F10FG (10) Waveform Error Detection To detect an error when a received waveform is out of the defined tolerance range, configure the CECRCR3 register. An error is detected when the bit of the CECRCR3 register is enabled. You can specify the detection time in the , , and bits. If the rising edge is detected during the period 1. or 2. shown below, or not detected in the timing described in 3., a waveform error interrupt is generated. 1. A period between the beginning of a bit and the fastest logical "1" rising timing 2. A period between the latest logical "1" rising timing and the fastest logical "0" rising timing. 3. The latest logical "0" rising timing. Permissible value of signal transition timing on specification (Data bit) Error detection period 0.4 ms 0.8 ms 0 ms 1. 1.3 ms 1.7 ms 3. 2. 26/fs to 26/fs + 7/fs (approx.0.793ms) 13/fs - 7/fs to 13/fs (approx.0.396ms) Page 479 43/fs - 7/fs to 43/fs (approx.1.312ms) 56/fs to 56/fs + 7/fs (approx.1.709ms) 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG 15.4.2.3 Enabling Reception After configuring the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers, CEC is ready for reception by enabling the CECREN bit. Detecting a start bit initiates the reception. Note:Changing the configurations of the CECADD, CECRCR1, CECRCR2 and CECRCR3 registers during reception may harm its proper operation. Before the change of the registers shown below, set the CECREN bit to disable the reception and read the bit and the CECTEN bit to ensure that the operation is stopped. Register name CECADD CECRCR1 CECRCR2 CECRCR3 15.4.2.4 Bit Symbol Setting item Logical address Noise cancellation time Time to identify cycle error Data reception at logical address discrepancy Start bit detection Waveform error detection (when enabled) Detecting Error Interrupt Detecting an error during data reception causes an error interrupt, and CEC waits for the next start bit. The received data is discarded. It is possible to suspend a receive error interrupt (maximum cycle error, receive buffer overrun and waveform error), continue reception and send the reversed ACK response. You can check the interrupt factor by monitoring the bit of the CECRSTAT register corresponding to interrupts. 15.4.2.5 Details of reception error (1) Cycle error Period between the falling edges of the two sequential bits is measured during reception. If the period does not comply with the specified minimum or maximum value, a cycle error interrupt is generated. A setting of maximum cycle and minimum cycle time is specified by CECRCR1 and bits. Maximum value is 90/fs (approx.2.747ms) and minimum value is 67/fs (approx. 2.045ms). It can be specified between the ranges −4/fs to +3/fs by the unit of 1/fs to detect cycle errors. The CECRSTAT bit or the bit is set if a cycle error interrupt is generated. The minimum cycle error causes CEC to output "Low" for approx. 3.63 ms. Note 1: When minimum cycle error is detected, "Low" is output after "Low" detecting noise cancellation time. 2013/5/31 Page 480 TMPM361F10FG Note 2: If the initiator sends a new message beginning with the start bit without having sent the last block with EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt is generated. For detaled information, refer to "15.1.3 Precautions". (2) ACK Collision At an ACK response, detecting "Low" after the specified period to output generates an ACK collision interrupt or a minimum cycle error interrupt. The ACK collision interrupt sets the CECRSTAT bit. The minimum cycle error interrupt sets the CECRSTAT bit. The following describes the period and method of detection. Detection starts approx. 0.3 ms after the end of the period of outputting "Low" and ends approx 2.0 ms from the starting point (the falling edge) of the ACK bit. At 0.3 ms from the end of the period of outputting "Low", CEC checks if the CEC line is "0" or not. If it is "Low", an ACK collision interrupt is generated. If it is "High", and "Low" is detected during the detection period, the minimum cycle error interrupt is generated. The minimum cycle error causes CEC to output "Low" for approx. 3.63ms. End of “Low” output Beginning of ACK bit Detection period 0.3 ms 2.0 ms (3) Receive Buffer Overrun A receive buffer overrun interrupt is generated when the next data reception is completed before reading the data stored in the receive buffer. The interrupt sets the CECRSTAT bit. (4) Waveform Error A waveform error occurs when waveform error detection is enabled in CECRCR3. Detecting a waveform, which does not identical to the defined, results in the waveform error. The interrupt is generated. The interrupt sets the CECRSTAT bit. Page 481 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG (5) Suspending Receive Error Interrupt You can specify if a maximum cycle error, a buffer overrun and a waveform error to be suspended without generating an interrupt when an erro is detected. This can be set in the CECRCR1 bit. To enable the setting, a timeout setting with the CECRCR1 bit is required. Under suspend-enable condition, if CEC keeps receiving the next bit and the entire reception including the ACK bit is completed, CEC generates an interrupt after a reversed ACK response is executed. "1" is set to the bits of the CECRSTAT register: the bit that indicates the reception completion, and the bits corresponding to the detected errors. If the reception of the next bit is interrupted, CEC starts to measure the timeout period, and an interrupt is generated after the timeout. "1" is set to the bits of the CECRSTAT register corresponding to the detected error. The timeout is measured from the end of the last bit received as is the case with wait time of a bus to be free in transmission. The information that the interrupts are suspended is held until the EOM bit is received or the timeout occurs. Thus, an interrupt is generated in each reception of a byte of data if multiple bytes are received while interrupts are suspended. "1" is set to the bits of the CECRSTAT register: the bit that indicates the reception completion, and the bits corresponding to the detected errors. The flags of the suspended interrupts and the reception completion are set to the bits of the CECRSTAT register. Note 1: A minimum cycle error interrupt is generated upon detecting a minimum cycle error in the next received bit while interrupts are suspended. "Low" is output to CEC for approx. 3.63 ms. The flags of the suspended interrupts and the minimum cycle error are set to the bits of the CECRSTAT register. Note 2: If an interrupt other than a minimum cycle error interrupt is generated while interrupts are suspended, CEC continues reception until the ACK response or the timeout. All the flags of the detected interrupts are set to the bits of the CECRSTAT register. 15.4.2.6 Stopping Reception Writing "0" to the CECREN bit disables data reception. If the data reception is disabled during data reception, receiving operation stops and the received data is discarded. Note:If the reception is disabled while "Low" is sent as a signal of minimum cycle error, the "Low" output is stopped as well. 2013/5/31 Page 482 TMPM361F10FG 15.4.3 Transmission 15.4.3.1 Basic Operation In the transmission setting, the CEC firstly confirms the bus free wait status; it checks whether a CEC falling edge signal does not exit for specified bit cycles, and then sends a start bit. The confirmation of bus free wait is performed all the time. Thus once bus free wait condition is satisfied, a transmission will start soon when transmission setting is done. After transmitting a start bit, CEC transmits one byte data and EOM data that are stored in the transmit buffer to the shift register. When the transmission of the first bit of the one byte data begins, transmission interrupt is generates, and CECTSTAT is set. After transmission interrupt generation, next one byte data is prepared to the transmit data buffer. One byte data transmission completes in order of transmission of 8 bits data, EOM bit, ACK bit transmission and ACK bit response confirmation. Data transmission continues until EOM is set to "1". If EOM is set to "1", the end of transmission interrupt generates after confirmation of data, EOM, ACK bit transmission and ACK bit response. By the end of transmission interrupt generates, CECTSTAT is set. Interrupt generation ends a series of transmission process, and CECTEN is cleared. If an error is generated during transmission, an error interrupt is generates to stop transmission. Even if reception is enabled, no reception is executed during transmission. Transmit interrupt (beginning of transmission) S H D1 D2 D3 D4 Transmit interrupt (end of transmission) Dn-2 Dn-1 Dn Wait for bus to be free Page 483 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG 15.4.3.2 Preconfiguration Before transmitting data, transmission settings to the Transmit Control Register (CECTCR) and the Transmit Buffer Register (CECTBUF) are required. (1) Bus Free Wait Time Specify the bus free wait time in the CECTCR bits. It can be specified in a range of 1 to 16 bit cycles. Counting of the bus free wait time begins one bit cycle after the falling edge of the final bit. If the signal stays high for the specified number of bit cycles, transmission starts. 1bit cycle (2) Bus free wait time Beginning of transmission Transmitting Broadcast Message Set the CECTCR bit when transmitting a broadcast message.If this bit is set, logical "0" response during an ACK cycle results in an error.If not, logical "1" response during an ACK cycle results in an error. (3) Adjusting Transmission Waveform Both start bit and data bit are capable of adjusting the rising timing and cycle. With the CECTCR bits, the timing can be specified between the defined fastest rising/cycle timing and the reference value. The following figures show how the waveforms differ according to the configurations of the start bit, logical "0" and logical "1". Note:Use in the same settings used for CECRCR1. 2013/5/31 Page 484 TMPM361F10FG 121/fs - 7/fs to 121/fs (approx.3.693 ms) Start bit 147/fs - 7/fs to 147/fs (approx.4.486 ms) 49/fs - 3/fs to 49/fs (approx.1.495 ms) Logical "0" 79/fs - 15/fs to 79/fs (approx.2.411 ms) 20/fs - 3/fs to 20/fs (approx.0.610 ms) Logical "1" 79/fs - 15/fs to 79/fs (approx.2.411 ms) (4) Preparing Transmission Data Configure a byte of transmission data and EOM data with the CECTBUF register. Page 485 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations TMPM361F10FG 15.4.3.3 Detecting Transmission Error Error detection during transmission generates an interrupt and stops transmission. It clears the CECTEN bit. To identify an error factor, the CECTSTAT register has bits that correspond with each interrupt. You can identify the interrupt factor by checking these bits. Note:An attempt to stop transmission by an error may cause an improper waveform output to CEC. This is because output is stopped immediately after the error occurs. 15.4.3.4 Details of Transmission Error (1) Arbitration Lost An arbitration lost error occurs when CEC detects "Low" on completion of appropriate low duration. Detecting an arbitration lost error sets the CECTSTAT bit. Two types of the arbitration lost detection periods are shown below. Detection period “0” output time Start bit Data bit EOMbit 0.3 ms Beginning of the next bit 1.7 ms 2.0 ms Detection period ACK bit Maximum “0” output time 0.3 ms 2013/5/31 Page 486 Cycle setting : CECTCR TMPM361F10FG (2) ACK error An ACK error interrupt occurs when an ACK response does not conform to the configuration specified in the CECTCR bit. When the ACK error interrupt occurs, the CECTSTAT bit is set. The ACK error is detected in the following cases. Configuration = 0 Broadcast transmission?: No = 1 Broadcast transmission?: Yes (3) Determined as an ACK error when ACK response is logical "1" ACK response is logical "0" Transmit Buffer Underrun A transmit buffer underrun error is caused by the following sequence. 1. Data in the transmit buffer is transmit to the shift register. 2. An interrupt occurs. 3. A byte of data is transmitted. 4. No data is set to the transmit buffer before starting transmission of a byte of subsequent data. When an underrun error occurs, the CECTSTAT bit is set. (4) Order of ACK Error and Transmit Buffer Overrun If interrupt factors of the ACK error and transmit buffer underrun are detected at the end of transmission of a byte of data, the transmit buffer underrun has priority. The transmit buffer underrun interrupt occurs first and then the ACK error interrupt occurs. 15.4.3.5 Stopping Transmission To stop transmission, send data including the EOM bit that indicates "1". This generates a transmit completion interrupt. Please note that proper operation is not ensured if the start bit of transmission is set to "0" during transmission. 15.4.3.6 Retransmission Transmission is stopped by error detection. To retry the transmission, configure the condition and data of starting the transmission. Page 487 2013/5/31 15. 15.4 Consumer Electronics Control (CEC) Operations 15.4.4 TMPM361F10FG Software Reset The entire CEC function can be initialized by software. Setting "1" to the CECRESET bit causes the following operations. ・ Reception : Immediately stops. The received data is discarded. ・ Transmission : Immediately stops including output to the CEC line. ・ Register : All the registers other than CECEN are initialized. Please note that software reset during transmission may cause the CEC line waveform that does not identical to the defined. 2013/5/31 Page 488 TMPM361F10FG 16. Remote control signal preprocessor(RMC) 16.1 Basic operation Remote control signal preprocessor (hereafter referred to as RMC) receives a remote control signal of which carrier is removed. 16.1.1 Reception of Remote Control Signal ・ ・ ・ ・ 16.2 A sampling clock can be selected from either low frequency clock (32.768kHz) or Timer output. Noise canceling time can be adjusted. Leader detection Batch reception up to 72bit of data Block Diagram Figure 16-1 shows the block diagram of RMC. RMC Sampling clock ) （fs/ TBBOUT Noise filter RMC reception interrupt (INTRMCRX) Received control Shift register Interrupt control Receive buffer (RMCRBUF1 - 3) Receive error flag (RMCRSTAT) Receive control Register (RMCREN) (RMCRCR1 - 4) (RMCEND1- 3) (RMCFSSEL) System clock （fsys) Internal databus Figure 16-1 Block diagram of RMC Page 489 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers 16.3 TMPM361F10FG Registers 16.3.1 Register List Addresses and names of RMC control registers are shown below. Base Address = 0x400E_3000 Register Address(Base+) Enable Register RMCEN 0x0000 RMCREN 0x0004 Receive Data Buffer Register 1 RMCRBUF1 0x0008 Receive Data Buffer Register 2 RMCRBUF2 0x000C Receive Data Buffer Register 3 RMCRBUF3 0x0010 Receive Control Register 1 RMCRCR1 0x0014 Receive Control Register 2 RMCRCR2 0x0018 Receive Control Register 3 RMCRCR3 0x001C Receive Control Register 4 RMCRCR4 0x0020 Receive Status Register RMCRSTAT 0x0024 Receive End bit Number Register 1 RMCEND1 0x0028 Receive End bit Number Register 2 RMCEND2 0x002C Receive End bit Number Register 3 RMCEND3 0x0030 Source Clock selection Register RMCFSSEL 0x0034 Receive Enable Register 2013/5/31 Page 490 TMPM361F10FG 16.3.2 RMCEN(Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RMCEN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 − R/W Write as "1". 0 RMCEN R/W Controls RMC operation. 0: Disabled 1:Enabled To allow RMC to function, enable the RMCEN bit first. If the operation is disabled, all the clocks for RMC except for the enable register are stopped, and it can reduce power consumption. If RMC is enabled and then disabled, the settings in each register remain intact. Page 491 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers TMPM361F10FG 16.3.3 RMCREN(Receive Enable Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RMCREN After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 RMCREN R/W Reception 0: Disabled 1: Enabled Controls reception of RMC. Setting this bit to "1" enables reception. Note:Enable the bit after setting the RMCRCR1, RMCRCR2, and RMCRCR3. 2013/5/31 Page 492 TMPM361F10FG 16.3.4 RMCRBUF1(Receive Data Buffer Register 1) 31 30 29 0 0 0 23 22 21 bit symbol After reset Bit 31-0 25 24 0 0 0 0 0 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 7 6 5 RMCRBUF(Received data 15 to 8bit) bit symbol After reset 26 RMCRBUF(Received data 23 to 16 bit) bit symbol After reset 27 RMCRBUF(Received data 31 to 24 bit) bit symbol After reset 28 0 0 0 0 0 4 3 2 1 0 0 0 0 26 25 24 RMCRBUF(Received data 7 to 0 bit) 0 Bit Symbol RMCRBUF[31:0] 0 0 0 0 Type R Function Received data (31 to 0 bit) Reads 4 bytes of received data. (31 to 0 bit) 16.3.5 RMCRBUF2(Receive Data Buffer Register 2) 31 30 29 0 0 0 23 22 21 bit symbol After reset Bit 31-0 0 0 0 0 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 7 6 5 RMCRBUF(Received data 47 to 40 bit) bit symbol After reset 0 RMCRBUF(Received data 55 to 48 bit) bit symbol After reset 27 RMCRBUF(Received data 63 to 54 bit) bit symbol After reset 28 0 0 0 0 0 4 3 2 1 0 0 0 0 RMCRBUF(Received data 39 to 32 bit) 0 Bit Symbol RMCRBUF[63:32] 0 0 0 Type R 0 Function Received data (63 to 32 bit) Reads 4 bytes of received data. (63 to 32 bit) Page 493 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers TMPM361F10FG 16.3.6 RMCRBUF3(Receive Data Buffer Register 3) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 bit symbol RMCRBUF(Received data 71 to 64 bit) After reset Bit 0 Bit Symbol 0 0 0 Type 0 Function 31-8 - R Read as 0. 7-0 RMCRBUF[71:64] R Received data (71 to 64 bit). Reads 1 byte of received data. (71 to 64 bit). Note:The received bit is stored in the data buffer register in MSB-first order, and the last received bit is stored in the LSB (bit 0). If the remote control signal is received in the LSB first algorithm, the received data is stored in reverse sequence. 2013/5/31 Page 494 TMPM361F10FG 16.3.7 RMCRCR1(Receive Control Register 1) 31 30 29 28 0 0 0 0 23 22 21 20 bit symbol After reset Bit 24 0 0 0 0 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 RMCLLMAX bit symbol After reset 25 RMCLCMIN bit symbol After reset 26 RMCLCMAX bit symbol After reset 27 RMCLLMIN 0 Bit Symbol 0 0 0 Type 31-24 RMCLCMAX[7:0] R/W 23-16 RMCLCMIN[7:0] R/W Function Specifies a maximum cycle of leader detection. Calculating formula of the maximum cycle: × 4/fs [s]. Specifies a minimum cycle of leader detection. Calculating formula of the minimum cycle: × 4/fs [s]. 15-8 RMCLLMAX[7:0] R/W Specifies a maximum low width of leader detection. Calculating formula of the maximum low width: × 4/fs [s] 7-0 RMCLLMIN[7:0] R/W Specifies a minimum low width of leader detection. Calculating formula for the minimum low width: × 4/fs [s] When RMCRCR2 = 1, a value of the low-pulse width is less than the specified value, it is defined as data bit. Note:When you configure the register, you must follow the rule shown below. Leader Low width + High width Rules > > > > Only high width = 0x00 = don't care = 0x00 No Leader = don't care = don't care = don't care Page 495 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers TMPM361F10FG 16.3.8 RMCRCR2(Receive Control Register 2) 31 30 bit symbol RMCLIEN RMCEDIEN - - After reset 0 0 0 0 23 22 21 20 - - - - bit symbol After reset 29 28 25 24 - - RMCLD RMCPHM 0 0 0 0 19 18 17 16 - - - - 0 0 0 0 0 0 0 0 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 1 1 1 1 bit symbol RMCLL bit symbol RMCDMAX After reset 31 26 15 After reset Bit 27 1 Bit Symbol RMCLIEN 1 1 1 Type R/W Function Leader detection interrupt 0: Not generated 1: Generated 30 RMCEDIEN R/W Remote control input falling edge interrupt 0: Not generated 1: Generated 29-26 − R Read as 0. 25 RMCLD R/W Receiving remote control signal with or without leader 0: Disabled 1: Enabled 24 RMCPHM R/W Receiving a remote control signal by a phase modulation 0: Not receiving a remote control signal by a phase modulation. (receive by a cycle modulation) 1: Receive remote control signal by a fixed-frequency pulse modulation. To receive a fixed-frequency remote control signal by a pulse modulation, set this bit to "1". 23-16 − R Read as 0. 15-8 RMCLL[7:0] R/W Excess low width that triggers reception completion and interrupt generation. 0000_0000 to 1111_1110: Reception completion and interrupt generation at × 1/fs [s]. 1111_1111: not to use as the trigger 7-0 RMCDMAX[7:0] R/W Maximum data bit cycle that triggers reception completion and interrupt generation. 0000_0000 to 1111_1110: Reception completion and interrupt generation at × 1/fs [s]. 1111_1111: not to use as the trigger 2013/5/31 Page 496 TMPM361F10FG 16.3.9 RMCRCR3(Receive Control Register 3) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 3 2 1 0 0 0 0 bit symbol - After reset 0 0 0 0 7 6 5 4 bit symbol - After reset 0 Bit Bit Symbol RMCDATH RMCDATL 0 0 0 Type 0 Function 31-15 - R Read as 0. 14-8 RMCDATH[6:0] R/W Larger threshold to determine a signal pattern in a phase method Calculating formula of the threshold: × 1/fs [s] Specifies a larger threshold (within a range of 1.5T and 2T) to determine a pattern of remote control signal in a phase method. If the measured cycle exceeds the threshold, the bit is determined as "10". If not, the bit is determined as "01". 7 - R Read as 0. 6-0 RMCDATL[6:0] R/W Threshold to determine 0 or 1 smaller threshold to determine a signal pattern in a phase method. Calculating formula of the threshold: × 1/fs [s] Specifies two kinds of thresholds: a threshold to determine whether a data bit is 0 or 1; a smaller threshold (within a range of 1T and 1.5T) to determine a pattern of remote control signal in a phase method. As for the determination of data bit, if the measured cycle exceeds the threshold, the bit is determined as "1". If not, the bit is determined as "0". Calculating formula of the threshold: × 1/fs [s]. As for the determination of a remote control signal pattern in a phase method, if the measured cycle exceeds the threshold, the bit is determined as "01". If not, the bit is determined as "00". Note:If the bit of the Receive Control Register 2 is "0", are not enabled. The bits are enabled when is "1". Page 497 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers TMPM361F10FG 16.3.10 RMCRCR4(Receive Control Register 4) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol RMCPO - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type RMCNC 0 0 Function 31-8 − R Read as 0. 7 RMCPO R/W Remote control input signal 0: Not reversed 1: Reversed 6-4 − R Read as 0. 3-0 RMCNC[3:0] R/W Specifies noise cancellation time. 0000: No cancellation 0001 to 1111: cancellation Calculating formula of noise cancellation time: × 1/fs [s] 2013/5/31 Page 498 TMPM361F10FG 16.3.11 RMCRSTAT(Receive Status Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol RMCRLIF RMCLOIF RMCDMAXIF RMCEDIF - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol RMCRLDR After reset 0 0 0 0 Bit Bit Symbol RMCRNUM 0 0 0 Type 0 Function 31-16 − R Read as 0. 15 RMCRLIF R Interrupt source flag 0: No leader detection interrupt generated. 1: Leader detection interrupt generated. 14 RMCLOIF R Interrupt source flag 0: No low width detection interrupt generated. 1: Low width detection interrupt generated. 13 RMCDMAXIF R Interrupt source flag 0: No maximum data bit cycle interrupt generated. 1: Maximum data bit cycle interrupt generated. 12 RMCEDIF R Interrupt source flag 0: No falling edge interrupt generated. 1: Falling edge interrupt generated. 11-8 − R Read as 0. 7 RMCRLDR R Leader detection. 0: Disable leader detection. 1: Enable leader detection. 6-0 RMCRNUM[6:0] R The number of received data bit 000_0000:no data bit (only with leader) 000_0001 to 100_1000: 1 to 72bit 100_1001 to 111_1111: 73bit and more Indicates the number of bits received as remote control signal data. The number cannot be monitored during reception. On completion of reception, the number is stored. Note 1: This register is updated every time an interrupt is generated.Writing to this register is ignored. Note 2: RMC keeps receiving 73 bit or more data unless reception is completed by detecting the maximum data bit cycle or the excess low width. In this case, the received data in the data buffer may not be ensured. Page 499 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers TMPM361F10FG 16.3.12 RMCEND1(Receive End bit Number Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 25 24 bit symbol - After reset 0 Bit Bit Symbol RMCEND1 0 0 0 0 Type Function 31-7 - R Read as 0. 6-0 RMCEND1[6:0] R/W Specifies that the number of receive data bit 000_0000 : No specifically the receive data bit 000_0001 to 100_1000 : Specifies that the number of receive data bit(1 to 72bit) 100_1001 to 111_1111 : Don’t set the value 16.3.13 RMCEND2(Receive End bit Number Register 2) 31 30 29 28 27 26 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 bit symbol - After reset 0 Bit Bit Symbol RMCEND2 Type 0 Function 31-7 - R Read as 0. 6-0 RMCEND2[6:0] R/W Specifies that the number of receive data bit 000_0000 : No specifically the receive data bit 000_0001 to 100_1000 : Specifies that the number of receive data bit(1 to 72bit) 100_1001 to 111_1111 : Don’t set the value 2013/5/31 Page 500 TMPM361F10FG 16.3.14 RMCEND3(Receive End bit Number Register 3) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 bit symbol - After reset 0 Bit Bit Symbol RMCEND3 0 0 0 Type 0 Function 31-7 - R Read as 0. 6-0 RMCEND3[6:0] R/W Specifies the number of receive data bit 000_0000 : No specifically the receive data bit 000_0001 to 100_1000 : Specifies that the number of receive data bit(1 to 72bit) 100_1001 to 111_1111 : Don’t set the value Note 1: As specified to RMCEND1, RMCEND2 and RMCEND3, it is able to set three kinds of the receive data bit. Note 2: To use the RMCEND1, RMCEND2 and RMCEND3 is in combination with the maximum data bit cycle. Page 501 2013/5/31 16. 16.3 Remote control signal preprocessor(RMC) Registers TMPM361F10FG 16.3.15 RMCFSSEL(Source Clock selection Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RMCCLK After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-1 - R Read as 0. 0 RMCCLK R/W Specifies that Sampling clock of RMC function 0 : Low frequency Clock (32.768kHz) 1 : Timer output(TBBOUT) For the Sampling of RMC function, It is able to set the Low Frequency Clock (32.768kHz) or Timer output (TBBOUT). The Setting range of Timer output by TBBOUT is from 30 to 34kHz. Note:To Change the sampling clock by using the RMCFSSEL, disable the RMC operation first by using the RMCEN. Then, enable it again, and set the RMCFSSEL before setting other RMC registers. 2013/5/31 Page 502 TMPM361F10FG 16.4 Operation Description 16.4.1 Reception of Remote Control Signal 16.4.1.1 Sampling clock A remote control signal is sampled by using low-speed 32.768kHz clock (fs). 16.4.1.2 Basic operation RMC set RMCRSTAT bit when a leader is detected. At this time, if you set the RMCRCR2 bit, leader detection will generate a leader detection interrupt. When a leader detection interrupt occurs, RMCRSTAT bit is set. After the leader detecting, each data bit is determined as "0" or "1" in sequence. The results are stored in RMCRBUF1, RMCRBUF2 and RMCRBUF3 registers up to 72 bits. By setting RMCRCR2< RMCEDIEN> bit, a remote control signal input falling edge interrupt can be generated in each falling edge of data bit. When a remote control signal input falling edge interrupt is generated, RMCRSTAT< RMCEDIF > bit is set. Data reception stops when the maximum data bit cycle is detected annd low-width matches the setting value, and then, an interrupt occurs. If , nad of the register RMCxEND1, RMCxEND2 and RMCEND3 have been configured, data reception stops and an interrupt occurs only in the case that the number of bits received before maximum data bit cycle is detected. The condition of RMC can be checked by reading the remote control receive status register. To check the status of RMC if reception is completed, read the remote control receive status register. On completion of reception, RMC is waiting for the next leader. By setting RMC to receive a signal without a leader, RMC recognizes the received as data and starts reception without detecting a leader. If the next data reception is completed before reading the preceding received data, the preceding data is overwritten by the next one. Data reception completed by dstecting the max data bit cycle Waiting for leader The maximum data bit cycle interrupt Capable of receiving data up to 72bit Waiting for leader Detecting leader Specified period of a maximum data bit cycle Page 503 2013/5/31 16. 16.4 Remote control signal preprocessor(RMC) Operation Description 16.4.1.3 TMPM361F10FG Preparation Before starting receiving process, configure how to receive remote control signal using the Remote Control Signal Receive Control Registers (RMCRCR1, RMCRCR2 and RMCRCR3, RMCRCR4). (1) Settings of Noise Cancelling Time Configure noise cancelling time with the RMCRCR4 bit. Noise canceling is applied to remote control signals sampled by the sampling clock. RMC monitors a sampled remote control signal in each rising edge of a sampling clock. If "High" is monitored, RMC recognizes that the signal was changed to "Low" after monitoring cycles of "Low"s specified in . If "Low" is monitored, RMC recognizes that the signal was changed to "High" after monitoring cycles of "High" specified in . The following figure shows how RMC operates according to the noise cancel setting of = "0011" (3 cycles). Subsequent to noise cancellation, the signal is changed from "High" to "Low" upon monitoring 3 cycles of "Low", and the signal is changed from "Low" to "High" upon monitoring 3 cycles of "High". = 0011 (3 cycle) Sampling clock RXIN pin Noise After sampling After noise cancellation 2013/5/31 Page 504 TMPM361F10FG (2) Settings of Detecting Leader Set the leader cycle and a low width of the leader to RMCRCR1 bits. When you configure those above, follow the rule shown below. Leader Low width + High Width Rules > > > > Only high width = 0y00000000 = don't care = 0y00000000 No leader = don't care = don't care = don't care The following shows a leader waveform and the RMCRCR1 register settings. Leader detection interrupt Maximum cycle Minimum cycle cycle Waiting for leader Low width Minimum low width Maximum low width If you want to generate an interrupt when detecting a leader, configure the RMCRCR2 bit. A remote control signal without a leader cannot generate a leader detection interrupt. Page 505 2013/5/31 16. 16.4 Remote control signal preprocessor(RMC) Operation Description TMPM361F10FG (3) Setting of 0/1 determination data bit Based on a falling edge cycle, the data bit is determined as 0 or 1. There are two kinds of determinations: 1. Determination by threshold. Configure a threshold value to RMCRCR3 bit which determines data bit as "0" or "1." If the determination value is equal to threshold value or more, it is determined as "1." If the determination value is less than threshold value, it is determined as "0." 2. Determination by falling edge interrupt inputs. By setting "1" to the RMCRCR2 bit, a remote control signal input falling edge interrupt can be generated in each falling edge of the data bit. Using this interrupt together with a timer enables the determination to be done by software. The followings shows the determination model of data bit. Threshold of 0/1 detemination is set to 2.5T with the bit. T T T T T T T T T T Remote control input falling edge interrupt Data bit waveform Threshold of 0/1 determination detemination result "0" "1" "0" As for data bit determination of a remote control signal in a phase method, see"16.4.1.8 Receiving a Remote Control Signal in a Phase Method". 2013/5/31 Page 506 TMPM361F10FG (4) Settings of Reception Completion To complete data reception, settings of detecting the maximum data bit cycle and excess low width are required. If multiple factors are specified, reception is completed by the factor detected first. Make sure to configure the reception completion settings. 1. Completetion by the maximum data bit cycle To complete reception by detecting a maximum data bit cycle, you need to configure the RMCRCR2 bits. If the falling edge of the data bit cycle isn't monitored after time specified as threshold in the bits, a maximum data bit cycle is detected. The detection completes reception and generates an interrupt.After interrupt inputs generated, RMCRSTAT< RMCDMAXIF > bit is set to "1". To complete reception by setting the number of receive data is set a RMCEND 1 to 3 register of each , , .In this case when the number of set reception bit agreed with the number of bit which received at the time of the outbreak of MAX on the number of receive data is set a RMCEND 1 to 3 register of each , , , it occurs by an MAX interrupt in data bit period. As specified to RMCEND3 to 1, it is able to set three kinds of the receive data bit. When it can receive the Maximum Data bit , the number of bit is not match the setting value in , , , it wait for Leader Reception. The maximum data bit cycle interrupt Threshold: If the falling edge of the data bit cycle is not monitored after time specified as threshold,a maximum data bit cycle is detected. The detection completes reception and generates an interrupt. 2. Completetion by detecting low width To complete reception by detecting the low width, you need to configure the RMCRCR2 bits. After the falling edge of the data bit is detected, if the signal stays low longer than specified, excess low width is detected. The detection completes reception and generates an interrupt. After interrupt inputs generated, RMCRSTAT bit is set to "1." Page 507 2013/5/31 16. 16.4 Remote control signal preprocessor(RMC) Operation Description TMPM361F10FG Excess low width detection interrupt. Threshold: Excess low width is detected when signal stay low longer than specified. 2013/5/31 Page 508 TMPM361F10FG 16.4.1.4 Enabling Reception By enabling the RMCREN bit after configuring the RMCRCR1, RMCRCR2, RMCRCR3 and RMCRCR4 registers, RMC is ready for reception. Detecting a leader initiates reception. Note:Changing the configurations of the RMCRCR1, RMCRCR2, RMCRCR3 and RMCRCR4 registers during reception may harm their proper operation. Be careful if you change them during reception. 16.4.1.5 Stopping Reception RMC stops reception by clearing the RMCREN bit to "0" (reception disabled). Clearing this bit during reception stops reception immediately and the received data is discarded. 16.4.1.6 Receiving Remote Control Signal without Leader in Waiting Leader Setting RMCRCR2 enables RMC to receive signals with or without a leader. By setting RMCRCR2 , RMC starts receiving data if it recognizes a signal of which low width is shorter than a maximum low width of leader detection specified in the RMCRCR1 bits. RMC keeps receiving data until the final data bit is received. If RMCRCR2 is enabled, the same settings of error detection, reception completion and data bit determination of 0 or 1 are applied regardless of whether a signal has a leader or not. Thus receivable remote control signals are limited. RMCRCR2 = 1 Waiting for leader Leader waveform RMC starts receiving data by receiving a signal which is less than the minimum low pulse width. Maximum data bit cycle is detected if a signal stays low shorter than specified and longer than a maximum data bit cycle. Minimum low width Maximum data bit cycle Page 509 2013/5/31 16. 16.4 Remote control signal preprocessor(RMC) Operation Description 16.4.1.7 TMPM361F10FG A Leader only with Low Width The figure shown below illustrates a remote control signal that starts with a leader of which waveform only has low width. This signal starts with a leader that only has low width and a data bit cycle starts from the rising edge. To enable the signal, it must be sent after being reversed by setting the RMCRCR4 bit to "1". This is because RMC is configured to detect a data bit cycle from the falling edge To detect a leader, configure only low-pulse width of the leader with the =0y0000 _ 0000,>. In this case, the value of is set as "don't care". To detect whether data "0" or data "1", configure the threshold of 0/1 detection with the RMCRCR3 . The maximum data bit cycle is configured with the of the RMCRCR2. To complete data reception, configure the maximum data bit cycle with of the RMCRCR2, and configure the low-pulse width detection with . After detecting the maximum data bit cycle and confirming the low-pulse with which is specified after receiving the last bit, receiving data is completed. The RMC generates an interrupt and waits for the next leader. Remote control signal waveform (input from RXIN) Leader detection interrupt Witing for a leader Final bit Low width detection interrupt Reversed remote control signal waveform Low period Leader Waiting for a next leader Detecting maximum data bit cycle completes reception. 16.4.1.8 Receiving a Remote Control Signal in a Phase Method RMC is capable of receiving a remote control signal in a phase method of which signal cycle is fixed. A signal in the phase method has three waveform patterns (see the figure shown below). By setting two thresholds a remote control signal pattern is determined. RMC converts the signal into data "0" or "1". On completion of reception, received data "0" and "1" are stored in the RMCRBUF1, RMCRBUF 2 and RMCRBUF3. 2013/5/31 Page 510 TMPM361F10FG By setting RMCRCR2 = "1", RMC enables to receive a remote control signal in the phase method. Each threshold can be configured with the RMCRCR3 bits and bits. Two thresholds are used to distinguish three waveform patterns. On condition that a cycle between two falling edges is "T", three patterns show cycles of 1T, 1.5T and 2T. Details of the two thresholds are shown below. Determined by Threshold Register bits to set Threshold 1 Pattern 1 & pattern 2 1T to 1.5T RMCRCR3 Threshold 2 Pattern 2 & pattern 3 1.5T to 2T RMCRCR3 To determine a remote control signal in the phase method, three patterns of data waveform and preceding data are required. In addition, the signal needs to start from data "11". Waveform pattern in phase method Cycle T Pattern1 Pattern2 Pattern3 Remote control signal data in phase method Data"1" Data"0" Page 511 A pulse shape in cycle indicates whether it is data "0" or data "1". 2013/5/31 16. 16.4 Remote control signal preprocessor(RMC) Operation Description TMPM361F10FG Remote control signal in phase method Remote control signal The first two bits of data need to be “11”. 2013/5/31 Page 512 TMPM361F10FG 17. Watchdog Timer(WDT) The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or other disturbances and remedying them to return the CPU to normal operation. If the watchdog timer detects a runaway, it generates a INTWDT interrupt or reset. Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI). Also, the watchdog timer notifies of the detecting malfunction to the external peripheral devices from the watchdog timer pin (WDTOUT) by outputting "Low". 17.1 Configuration Figure 17-1shows the block diagram of the watchdog timer. WDMOD RESET pin To internal reset Watchdog timer out control WDTOUT Watchdog timer interrupt INTWDT 225/fsys 223/fsys 221/fsys 217/fsys 215/fsys fsys 219/fsys Selector WDMOD Q Binary counter R S Reset Internal reset Write “0x4E” Write “0xB1” WDMOD Watch dog timer Control Register WDCR Internal data bus Figure 17-1 Block Diagram of the Watchdog Timer Page 513 2013/5/31 17. 17.2 Watchdog Timer(WDT) Register TMPM361F10FG 17.2 Register The followings are the watchdog timer control registers and addresses. Base Address = 0x400F_2000 Register name Address(Base+) Watchdog Timer Mode Register Watchdog Timer Control Register 17.2.1 WDMOD 0x0000 WDCR 0x0004 WDMOD(Watchdog Timer Mode Register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - I2WDT RESCR - 0 0 0 1 0 bit symbol WDTE After reset 1 Bit Bit Symbol WDTP 0 0 Type Function 31-8 − R Read as 0. 7 WDTE R/W Enable/Disable control 0:Disable 1:Enable 6-4 WDTP[2:0] R/W Selects WDT detection time(Refer toTable 17-1) 000: 215/fsys 100: 223/fsys 001: 217/fsys 101: 225/fsys 010: 219/fsys 110:Setting prohibited. 011: 221/fsys 111:Setting prohibited. 3 − R Read as 0. 2 I2WDT R/W Operation when IDLE mode 0: Stop 1:In operation 1 RESCR R/W Operation after detecting malfunction 0: INTWDT interrupt request generates. (Note) 1: Reset 0 − R/W Write 0. Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI). 2013/5/31 Page 514 TMPM361F10FG Table 17-1 Detection time of watchdog timer (fc = 64MHz) WDMOD Clock gear value CGSYSCR 000 001 010 011 100 101 000 (fc) 0.51 ms 2.05 ms 8.19 ms 32.77 ms 131.07 ms 524.29 ms 100 (fc/2) 1.02 ms 4.10 ms 16.38 ms 65.54 ms 262.14 ms 1.05 s 101 (fc/4) 2.05 ms 8.19 ms 32.77 ms 131.07 ms 524.29 ms 2.10 s 110 (fc/8) 4.10 ms 16.38 ms 65.54 ms 262.14 ms 1.05 s 4.19 s Page 515 2013/5/31 17. 17.2 Watchdog Timer(WDT) Register TMPM361F10FG 17.2.2 WDCR (Watchdog Timer Control Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - bit symbol WDCR After reset Bit - Bit Symbol - - - Type Function 31-8 − R Read as 0. 7-0 WDCR W Disable/Clear code 0xB1:Disable code 0x4E: Clear code Others:Reserved 2013/5/31 Page 516 TMPM361F10FG 17.3 Operations 17.3.1 Basic Operation The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input. Detecting time can be selected between 215, 217, 219 , 221, 223 and 225 by the WDMOD. The detecting time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer out pin (WDTOUT) output "Low". To detect malfunctions (runaways) of the CPU caused by noise or other disturbances, the binary counter of the watchdog timer should be cleared by software instruction before INTWDT interrupt generates. If the binary counter is not cleared, the non-maskable interrupt generates by INTWDT. Thus CPU detects malfunction (runway), malfunction countermeasure program is performed to return to the normal operation. Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices. 17.3.2 Operation Mode and Status The watchdog timer begins operation immediately after a reset is cleared. If not using the watchdog timer, it should be disabled. The watchdog timer cannot be used as the high-speed frequency clock is stopped. Before transition to below modes, the watchdog timer should be disabled.In IDLE2 mode, its operation depends on the WDMOD setting. - STOP mode SLEEP mode SLOW mode BACKUP STOP mode BACKUP SLEEP mode Also, the binary counter is automatically stopped during debug mode. Page 517 2013/5/31 17. 17.4 Watchdog Timer(WDT) Operation when malfunction (runaway) is detected 17.4 TMPM361F10FG Operation when malfunction (runaway) is detected 17.4.1 INTWDT interrupt generation In the Figure 17-2 shows the case that INTWDT interrupt generates (WDMOD="0"). When an overflow of the binary counter occurs, INTWDT interrupt generates. It is a factor of non-maskable interrupt (NMI). Thus CPU detects non-maskable interrupt and performs the countermeasure program. The factor of non-maskable interrupt is the plural. CGNMIFLG identifies the factor of non-maskable interrupts. In the case of INTWDT interrupt, CGNMIFLG is set. When INTWDT interrupt generates, simultaneously the watchdog timer out (WDTOUT) output "Low". WDTOUT becomes "High" by the watchdog timer clearing that is writing clear code 0x4E to the WDCR register. WDT counter n Overflow 0 INTWDT Write of a clear code WDT clear WDTOUT Figure 17-2 INTWDT interrupt generation 2013/5/31 Page 518 TMPM361F10FG 17.4.2 Internal reset generation Figure 17-3 shows the internal reset generation (WDMOD="1"). MCU is reset by the overflow of the binary counter. In this case, reset status continues for 32 states. A clock is initialized so that input clock (fsys) is the same as a high-speed frequency clock (fosc). This means fsys = fosc. Overflow WDT counter n INTWDT Internal reset WDTOUT 32-state (4.0µs @fOSC = fsys = 8 MHz) Figure 17-3 Internal reset generation Page 519 2013/5/31 17. 17.5 Watchdog Timer(WDT) Control register 17.5 TMPM361F10FG Control register The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. 17.5.1 Watchdog Timer Mode Register (WDMOD) 1. Specifying the detection time of the watchdog timer . Set the watchdog timer detecting time to WDMOD. After reset, it is initialized to WDMOD = "000". 2. Enabling/disabling the watchdog timer . When resetting, WDMOD is initialized to "1" and the watchdog timer is enabled. To disable the watchdog timer to protect from the error writing by the malfunction, first bit is set to "0", and then the disable code (0xB1) must be written to WDCR register. To change the status of the watchdog timer from "disable" to "enable," set the bit to "1". 3. Watchdog timer out reset connection This register specifies whether WDTOUT is used for internal reset or interrupt. After reset, WDMOD is initialized to "1", the internal reset is generated by the overflow of binary counter. 17.5.2 Watchdog Timer Control Register(WDCR) This is a register for disabling the watchdog timer function and controlling the clearing function of the binary counter. 2013/5/31 Page 520 TMPM361F10FG 17.5.3 Setting example 17.5.3.1 Disabling control By writing the disable code (0xB1) to this WDCR register after setting WDMOD to "0," the watchdog timer can be disabled and the binary counter can be cleared. 17.5.3.2 7 6 5 4 3 2 1 0 WDMOD ← 0 − − − − − − − Set to "0". WDCR ← 1 0 1 1 0 0 0 1 Writes the disable code (0xB1). Enabling control Set WDMOD to "1". WDMOD 17.5.3.3 ← 7 6 5 4 3 2 1 0 1 − − − − − − − Set to "1". Watchdog timer clearing control Writing the clear code (0x4E) to the WDCR register clears the binary counter and it restarts counting. WDCR 17.5.3.4 ← 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 Writes the clear code (0x4E). Detection time of watchdog timer In the case that 221/fsys is used, set "011" to WDMOD. WDMOD ← 7 6 5 4 3 2 1 0 1 0 1 1 − − − − Page 521 2013/5/31 17. 17.5 Watchdog Timer(WDT) Control register 2013/5/31 TMPM361F10FG Page 522 TMPM361F10FG 18. Key-on Wakeup 18.1 Outline ・ TMPM361F10FG has 4 key input, KWUP0 to KWUP3, which can be used for releasing STOP mode or for external interrupts. Note that interrupt processing is executed with one interrupt factor for 4 inputs. (This is programmed in the CG block) Each key input can be configured to be used or not, by programming (KWUPCRn). ・ The active state of each input can be configured to the rising edge, the falling edge, both edge, the high level or the low level, by programming KWUPCRn. ・ An interrupt request is cleared by programming the key interrupt request clear register KWUPCLR in the interrupt processing. ・ The KWUP input pins have pull-up functions, which can be switched between static pull-up and dynamic pull-up by programming the KWUPCRn. This programming is needed for each of 4 inputs. 18.2 Block Diagram Enable rising edge INTC (Interrupt Controler) Static Pull-up KWUPINT Register Dynamic Pull-up 1 1 KWUP 0 to 3 IPH 1 IPH Level / Edge fs 1 KWUPPKEY Register fs Sampling at the end of DPUP period 1 Enable falling edge Clear by reading flag or claer by writing register High level / Low level IPH IPH Figure 18-1 Key-on Wakeup Block Diagram Page 523 2013/5/31 18. 18.3 Key-on Wakeup Register in detail 18.3 TMPM361F10FG Register in detail 18.3.1 Register list Base Address = 0x400F_1000 Register name Address(Base+) Control register 0 KWUPCR0 0x0000 Control register 1 KWUPCR1 0x0004 Control register 2 KWUPCR2 0x0008 Control register 3 KWUPCR3 0x000C Port monitor register KWUPPKEY 0x0080 Pull-up cycle register KWUPCNT 0x0084 Interrupt all clear register KWUPCLR 0x0088 Interrupt monitor register KWUPINT 0x008C 18.3.2 KWUPCR0 (Control register 0) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - KEY0EN 0 0 0 0 0 bit symbol DPE0 After reset 0 Bit Bit Symbol KEY0 0 1 Type Function 31-8 − R Read as "0". 7 DPE0 R/W Selected static pull-up or dynamic pull-up. 0: Static pull-up 1: Dynamic pull-up 6-4 KEY0[2:0] R/W Selected the input active status of KWUP0. 000:"Low" level 001:"High" level 010: falling edge 011: rising edge 100: Both edge Except above: Reserved 3-1 - R Read as "0". 0 KEY0EN R/W Selected enable or disable KWUP interrupt of KWUP0. 0: Disable 1: Enable 2013/5/31 Page 524 TMPM361F10FG 18.3.3 KWUPCR1 (Control register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol DPE1 - - - KEY1EN After reset 0 0 0 0 0 Bit Bit Symbol KEY1 0 1 0 Type Function 31-8 − R Read as "0". 7 DPE1 R/W Selected static pull-up or dynamic pull-up. 0: Static pull-up 1: Dynamic pull-up 6-4 KEY1[2:0] R/W Selected the input active status of KWUP1. 000:"Low" level 001:"High" level 010: falling edge 011: rising edge 100: Both edge Except above: Reserved 3-1 − R Read as "0". 0 KEY1EN R/W Selected enable or disable KWUP interrupt of KWUP1. 0: Disable 1: Enable Page 525 2013/5/31 18. 18.3 Key-on Wakeup Register in detail TMPM361F10FG 18.3.4 KWUPCR2 (Control register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol DPE2 - - - KEY2EN After reset 0 0 0 0 0 Bit Bit Symbol KEY2 0 1 0 Type Function 31-8 − R Read as "0". 7 DPE2 R/W Selected static pull-up or dynamic pull-up. 0: Static pull-up 1: Dynamic pull-up 6-4 KEY2[2:0] R/W Selected the input active status of KWUP2. 000:"Low" level 001:"High" level 010: falling edge 011: rising edge 100: Both edge Except above: Reserved 3-1 − R Read as "0". 0 KEY2EN R/W Selected enable or disable KWUP interrupt of KWUP2. 0: Disable 1: Enable 2013/5/31 Page 526 TMPM361F10FG 18.3.5 KWUPCR3 (Control register 3) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol DPE3 - - - KEY3EN After reset 0 0 0 0 0 Bit Bit Symbol KEY3 0 1 0 Type Function 31-8 − R Read as "0". 7 DPE3 R/W Selected static pull-up or dynamic pull-up. 0: Static pull-up 1: Dynamic pull-up 6-4 KEY3[2:0] R/W Selected the input active status of KWUP3. 000:"Low" level 001:"High" level 010: falling edge 011: rising edge 100: Both edge Except above: Reserved 3-1 − R Read as "0". 0 KEY3EN R/W Selected enable or disable KWUP interrupt of KWUP3. 0: Disable 1: Enable Page 527 2013/5/31 18. 18.3 Key-on Wakeup Register in detail TMPM361F10FG 18.3.6 KWUPPKEY (Port monitor register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - PKEY3 PKEY2 PKEY1 PKEY0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3-0 PKEY3 to PKEY0 R PORT status 0:"Low" 1:"High" For port status, it can be monitored the external status with KWUPPKEY. The monitoring is sampled in dynamic pull-up period. 2013/5/31 Page 528 TMPM361F10FG 18.3.7 KWUPCNT (Pull-up cycle register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 5 4 3 2 1 0 - - 0 0 7 6 bit symbol - - After reset 0 0 Bit Bit Symbol T2S T1S 0 0 Type 0 0 Function 31-6 − R Read as "0". 5-4 T2S[1:0] R/W Dynamic pull-up cycle 00: 256/fs (7.8 ms @ fs = 32.768 kHz) 01: 512/fs (15.6 ms @ fs = 32.768 kHz) 10: 1024/fs (31.3 ms @ fs = 32.768 kHz) 11: 2048/fs (62.5 ms @ fs = 32.768 kHz) Repeats dynamic pull-up operation for the T2 cycle by . 3-2 T1S[1:0] R/W Dynamic pull-up period 00: 2/fs (61.0 μs @fs = 32.768 kHz) 01: 4/fs (122.1 μs @fs = 32.768 kHz) 10: 8/fs (244.1 μs @fs = 32.768 kHz) 11: 16/fs (488.3 μs @fs = 32.768 kHz) Activate the pull-up during T1 period by , the remaining period is not activated. 1-0 - R Read as "0". Dynamic pull-up operation is as following. T1 T2 Figure 18-2 Dynamic pull-up operation Note 1: Activate fs during the dynamic pull-up used. Note 2: After changed dynamic pull-up setting, wait key input for a T1 period. Page 529 2013/5/31 18. 18.3 Key-on Wakeup Register in detail TMPM361F10FG 18.3.8 KWUPCLR (All interrupt request clear register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 3 2 1 0 0 0 7 6 5 4 bit symbol - - - - After reset 0 0 0 0 Bit Bit Symbol Type KEYCLR 0 Function 31-4 − R Read as "0". 3-0 KEYCLR[3:0] W All interrupt request of KWUP is cleared by writing "1010". Read as "0". 2013/5/31 Page 530 0 TMPM361F10FG 18.3.9 KWUPINT (Interrupt monitor register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - KEYINT3 KEYINT2 KEYINT1 KEYINT0 After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as "0". 3-0 KEYINT3 to KEYINT0 R Interrupt 0:No 1:Yes When KWUPCRn="1" and activated signal into the key-on wakeup port, the corresponding channel of KWUPINT will be set to "1" for the interrupt execution. KWUPINT is read only register, due to the reading this register corresponding bit set to "1" and interrupt request will becleared. That one all can be cleared at once by the KWUPCLR register. When setting the active status to "Level" input by KWUPCRn, KWUPINT corresponding bit for a key-on wakeup is kept "1" in reading without changing a external input setting function to nothing. Page 531 2013/5/31 18. 18.4 Key-on Wakeup Key-on Wakeup Operation 18.4 TMPM361F10FG Key-on Wakeup Operation TMPM361F10FG has 4 key input pins, KEY0 to KEY3. Program the CGIMCGF register in the CG to determine whether to use the key inputs for releasing the STOP mode or for normal interrupts. Setting to "1" causes all the key inputs, KEY0 to KEY3, to be used for interrupts for releasing the STOP mode. Program KWUPCRn to enable or disable interrupt inputs for each key input pin. Also, program KWUPCRn to define the active state of each key input pin to be used. Detection of key inputs is carried out in the KWUP block, and the detection results are notified to the CGIMCGF in the CG as the active high level. Therefore, program CGIMCGF to "001" to determine the detection level to the high level. Setting CGINCGF to "0" (default) configures all the input pins, KEY0 to KEY3 to the normal interrupts. In this case, to be detected interrupt request by the CPU, "High" pulse or "High" level signal must be input. Program KWUPCRn in the same way to enable or disable each key input and define their active states. Writing "1010" to KWUPCLR during interrupt processing clears all the key interrupt requests. Note:If two or more key inputs are generated, all the key input requests will be cleared by clearing interrupt requests. 2013/5/31 Page 532 TMPM361F10FG 18.5 Pull-up Function Each key input has the pull-up function and can be programmed by setting the register in the port. When a static pull-up is set, it can not be depend on KWUPCRn and the pull-up be used. Regarding to dynamic pull-up, refer to "18.3.7 KWUPCNT (Pull-up cycle register)". 18.5.1 In case of using KWUP inputs with pull-up enabled a. When you make the first setting after turning the power on (Example : port J7 withe interrupt at both edge) PJFR2 = 1 : The function is set to KWUP3 PJPUP = 1 : Pull-up on control PJIE = 1 : Enable input function KWUPCR3 = 0 KWUPCR3 = 1 0 0 KWUPCLR = 1 0 1 KWUPCR3 = 1 CGIMCGF = 0 0 1 CGIMCGF = 1 : Disable interrupt : Change active status (both edge) Wait completing pull-up 0 : Clear interrupt request : Enable interrupt : Change active level ("High" level) : Enable INTKWUP b. When changing the active state of KWUP input during operation c. Interrupt enable clear register 2 [1] = 1 : Disable INTKWUP KWUPCR3 = 0 : Disable interrupt KWUPCR3 = 0 0 0 KWUPCLR = 1 0 1 KWUPCR3 = 1 Interrupt priority setting register = * * * Interrupt enable set register 2 [1] = 1 : Change active status ("Low" level) 0 : Clear interrupt request : Enable interrupt : Set interrupt priority (***= 000 to 111) : Enable INTKWUP When enabling KWUP input during operation Interrupt enable clear register 2 [1] = 1 : Disable INTKWUP KWUPCR3 = 0 : Disable interrupt KWUPCR3 = * * * : Set active status (***= 000 to 100) KWUPCLR = 1 KWUPCR3 = 1 Interrupt priority setting register = * Interrupt enable set register 2 [1] = 0 1 0 : Clear interrupt request : Enable interrupt * * : Set interrupt priority (***= 000 to 111) 1 Page 533 : Enable INTKWUP 2013/5/31 18. 18.5 Key-on Wakeup Pull-up Function 18.5.2 TMPM361F10FG In case of using KWUP inputs with pull-up disabled a. When you make the first setting after turning the power on PJFR2 = 1 : The function is set to KWUP3 PJPUP = 0 : Pull-up off control PJIE = 1 : Enable input function KWUPCR3 = 0 : Disable interrupt KWUPCR3 = 0 0 0 KWUPCLR = 1 0 1 KWUPCR3 = 1 CGIMCGF = 0 CGIMCGF = 1 : Set active status ("Low" level) 0 : Clear interrupt request : Interrupt enable 0 1 : Change active level ("High" level) : Enable INTKWUP b. When changing the active sate of KWUP input during operation Interrupt enable clear register 2 [1] = 1 : Disable INTKWUP KWUPCR3 = 0 KWUPCR3 = * * * KWUPCLR = 1 0 1 KWUPCR3 = 1 Interrupt priority setting register = * * * Interrupt enable set register 2 [1] = : Disable interrupt : Change active status (***= 000 to 100) c. 0 : Clear interrupt request : Enable interrupt : Set interrupt priority (***= 000 to 111) 1 :Enable INTKWUP When enabling KWUP input during operation Interrupt enable clear register 2 [1] = 1 : Disable INTKWUP KWUPCR3 = 0 : Disable interrupt KWUPCR3 = * * * : Change active status (***= 000 to 100) 2013/5/31 KWUPCLR = 1 KWUPCR3 = 1 Interrupt priority setting register = * Interrupt enable set register 2 [1] = 1 0 1 0 : Clear interrupt request : Enable interrupt * * : Set interrupt priority (***= 000 to 111) Page 534 : Enable INTKWUP TMPM361F10FG 18.6 KWUP input Detection Timing 1. PJPUP="1", KWUPCRn="0" with always pull-up The active state of each key input can be defined to the high or low level or to the rising or falling edges by setting KWUPCRn. The active state of key inputs are continuously detected. 2. PJPUP="1", KWUPCRn="1" with dynamic pull-up Detection of the active state of each key input (interrupt detection) is carried out at the edge one-clock before fs at the end of the T1 period. Therefore, a key input not shorter than the T2 period is needed.There is a delay up to the T2 period before key input detection. The figure below shows an example of defining the active state to the falling edge. Pull-up (period of T1) Cycle (period of T2) KEY input High or Hi-Z Need more than T2 period (Low period) High or Hi-Z or Low The timing of interrupt KEY input Detection Result of an internal sampling Page 535 2013/5/31 18. 18.6 Key-on Wakeup KWUP input Detection Timing 2013/5/31 TMPM361F10FG Page 536 TMPM361F10FG 19. Backup module 19.1 Features The BACKUP mode, one of the system operation modes, enable the MCU to operate in the low power consumption. By cutting electricity to the entire block, such as CPU or other peripheral IPs, other than the backup module, this mode significantly reduces power consumption. The BACKUP mode contains two modes : - 19.2 BACKUP SLEEP mode (enabling low frequency oscillator) BACKIUP STOP mode (disabling low frequency oscillator) Block Diagram DVDD3B / RVDD3 Regulator PA Backup RAM Regulator and (8KB) Backup Cont. CPU, PB PI Other Logic Flash ROM PE Keep Logic Logic PF CEC,RMC (1024KB) Port KWUP,RTC Main RAM Port Clock Logic Generator PJ PL PM (56KB) PN PLL PG PP AD High-OSC Low-OSC Converter DVSS AVSS AVDD3 VREFH DVDD3A X1 DVSS X2 XT1 XT2 㧦Power shutdown blocks in the BACKUP mode Figure 19-1 Power shutdown blocks in the backup mode Page 537 2013/5/31 19. 19.3 Backup module BACKUP Mode Operation 19.3 TMPM361F10FG BACKUP Mode Operation The BACKUP mode only corresponds to the single chip mode (MCU starts from the built-in flash memory after reset). In the BACKUP mode, single boot mode (MCU starts from built-in boot ROM after reset) is not supported. 19.3.1 Operable peripherals in the BACKUP mode ・ In the BACKUP SLEEP mode Port output, Key-on-wakeup (KWUP), CEC, remote control circuit (RMC), real-time clock (RTC), low speed oscillator, data in BACKUP RAM (8KB) ・ In the BACKUP STOP mode Port output, Key-on-wakeup (KWUP), data in BACKUP RAM (8KB) 19.3.1.1 Transition to the BACKUP mode Figure 19-2 shows the state transition between NORMAL mode, SLOW mode and BACKUP mode (BACKUP SLEEP and BACKUP STOP). The BACKUP mode (BACKUP SLEEP and BACKUP STOP) will return the preceding mode of transition by release source. In addition, each mode changes to the reset processing routine if the reset operation occurs. External reset After reset NORMAL mode Releasing source (Power on shut down block and perform internal reset) Releasing source (Power on shut down block and perform internal reset) Instruction (Note 1) Instruction BACKUP SLEEP mode BACKUP STOP mode Instruction (Power on shut down block and perform internal reset) Releasing source Instruction Instruction Instruction (Power on shut down block and perform internal reset) Releasing source SLOW mode Figure 19-2 BACKUP Mode Transition Diagram Note 1: In case that low-speed oscillator is stopped in the NORMAL mode, make sure to start the low-speed oscillation and confirm the stable oscillation before changing to BACKUP SLEEP mode. Note 2: The program for changing to the BACKUP mode must be executed in the built-in flash ROM or built-in RAM. Note 3: Do not release BACKUP mode by reset. 2013/5/31 Page 538 TMPM361F10FG 19.3.1.2 Backup Transition Flow (1) Preparing for BACKUP mode The preparation program for changing to the backup mode must be executed in the built-in flash ROM or built-in RAM. 1. Stopping peripherals and saving data Both in the NORMAL mode and SLOW mode stop peripheral function including DMAC, SMC and WDT. In case of transition to BACKUP SLEEP mode, no need to stop peripheral functions (CEC, RMC, RTC and KWUP) which are used in BACKUP SLEEP mode. It is necessary to save data to preserved in BACKUP RAM. BACKUP RAM is used only 8KB data from 0x2000_E000 to 0x2000_FFFF. 2. Prohibit the interrupt To prevent from obstruction a transition to BACKUP mode, interrupt request set to disable if needed. It is note that NMI interrupt and INTRTC interrupt request cannot be disabled so that these interrupt requests must be avoided in advance. 3. Setting of port keep function (CGSTBYCR) Port keep function retains the port status of the momentary when CGSTBCR is set to "1". Object ports are A to H, K, O, P, SWDIO, NMI. Port keep function is capable of retaining input enable / disable, port 0 / 1 output status and on / off status of pullup / pull-down register. By these settings made before the transition to the BACKUP mode, port keep function can hold the port status. When using the port keep function, port register of each port must be set properly. The input / output status of port I, J, L, M and N are depend on the port register regardless the port keep function. The interrupt of BACKUP mode is set by using these ports. All unnecessary ports must be set to disable by the input enable control register. 4. Clock related setting and warm up time Stop PLL circuit by setting CGOSCCR="0". Set high-speed clock to fc (1/1) by CGSYSCR="000". Using BACKUP SLEEP is needed for starting lowspeed oscillator by CGOSCCR. In addition, it is necessary to setting warm up time returning from BACKUP mode by CGOSCCR. The warm up time is referred to the section "Clock / Mode control". Page 539 2013/5/31 19. 19.3 Backup module BACKUP Mode Operation (2) TMPM361F10FG Transition to BACKUP mode 1. Setting modes and clearing release source of BACKUP mode By the CGSTBYCR register, set to the BACKUP STOP mode or BACKUP SLEEP mode. 2. Transition to the BACKUP mode Clear the interrupt which releases from BACKUP mode, then execute WFI instruction Precautions for the use of the BACKUP mode (about debug tool) The communication with debug tool is disconnected, if MCU changes to the BACKUP mode. In this case, it is necessary to reconnect to debug tool. (3) Returning from backup mode (Releasing) 1. Releasing source of BACKUP mode Releasing source of BACKUP STOP and BACKUP SLEEP shown as below. BACKUP mode BACKUP STOP BACKUP SLEEP Releasing source of BACKUP mode INT0 to 4, INTKWUP (Static) INT0 to 4, INTKWUP (Dynamic / Static), INTRTC, INTCECRX, INTRMCRX0 2. Releasing operation by releasing source of BACKUP mode If the event of releasing source are received, regulator starts to supply power to the shut down block. Depending on the returned modes, high-speed oscillator and low-speed oscillator will start operation. The warm up timer will starts when the oscillation becomes stable. During warm up time, internal reset signal of power shut down block which returned from BACKUP mode is continuing active level. Internal reset is cleared after warm up time has elapsed, and then MCU returns to the preceding mode of BACKUP mode. Precaution after BACKUP mode released ・ By reading CGRSTFLG register, it can be found which reset are occurred. ・ Make sure to perform the port A, B, E, F, G, and P setting before releasing port keep function by (CGSTBYCR="0"). 2013/5/31 Page 540 TMPM361F10FG 19.3.1.3 Transition Flowchart Normal Operation Stop peripheral function Stop peripherals if needed. Shutdown power suppy in the main block Save backup data Waiting for the interrupt Save data to BACKUP RAM if needed. Interrupt occurs Power-on shutdonw block Disabling interrupt Start high-speed / low-speed oscillation So as not to obstruct the transiton to BACKUP mode, Start warm up timer operation interrupts is disabled if needed. Reset releasing Setting port keep function Check CGRSTFLG register If CGSTBYCR=” 1” , Check if the reset operation made by returning BACKUP. retain port status of spectic port. Perform interrupt setting Setting warm up time Jump to handler. Set warm up time after returning from BACKUP mode Check the BACKUP mode releasing source. Setting clock gear Port setting Stop PLL then set clock gear to fc (1/1). Each port is setting the preceding status before BACKUP mode. Setting BACKUP mode Set BACKUP SLEEP mode or BACKUP STOP mode Releasing port keep status by CGSTBYCR If CGSTBYCR=” 0” , releasing the specific port status. Setting releasing source and change to BACKUP mode Enable interrupt signal to permit the interruption, NORMAL Operation and perform WFI instruction. Figure 19-3 Stare transition flowchart Page 541 2013/5/31 19. 19.3 Backup module BACKUP Mode Operation 19.3.1.4 TMPM361F10FG BACKUP Mode Timing Chart CPU status transition NORMAL Preparation Power suppy Power suppy recorvery time + NORMAL operation period for shutdopnw period reset period operation BACKUP Release source (Positive logic) Internal 1.5V Always-on block ON Internal 1.5V Power shutdonw ON Power suppy shutdown block High-spped Stable oscillation oscillation Oscillation stopped: ࠉBACKUP SLEEPBACKUP STOP Stable oscillation (Internal signal) Low-speed Stable oscillation oscillation Oscillation continued : BACKUP SLEEP Oscillation stopped : BACKUP STOP Stable oscillation (Internal signal) Warm up time Internal RESET (Shutdown block) (Note) High PORT status Port keep External RESET High Figure 19-4 BACKUP mode sequence Note:"Figure 19-4 BACKUP mode sequence" shows the transition modes ; NORMAL→BACKUP STOP→NORMAL or NORMAL→BACKUP SLEEP→NORMAL. In this transition, a clock for warm up counter is used high-speed oscillator. The warm up time must be set 500Éþs or more. 2013/5/31 Page 542 TMPM361F10FG 20. Analog / Digital Converter (ADC) 20.1 Outline TMPM361F10FG has a 10-bit, sequential-conversion analog / digital converter (AD converter). This AD converter is equipped with 8 analog input channel. These 8 analog input channels (pins AIN0~AIN7) are also used as input / output ports. Note 1: To assure conversion accuracy, the specified value must be set to the ADCBAS register. Note 2: If it is necessary to reduce a power current by operating the TMPM361F10FG in IDLE or STOP mode and if either case shown below is applicable, you must first stop the AD converter and then execute the instruction to put the TMPM361F10FG into standby mode. 1. TheTMPM361F10FG must be put into IDLE mode when ADMOD1 is "0". 2. The TMPM361F10FG must be put into STOP mode. Page 543 2013/5/31 Page 544 VREFL (AVSS) fc Channel select control circuit ADCLK DA Converter Comparator - + ADMOD2 Internal data bus ADMOD0 End Normal AD conversion control circuit ADSCN ADS Sample hold ADMOD1 1/1 1/2 1/4 1/8 1/16 VREF Multiplexer VREFH AIN7 AIN0 ADTRG ADCLK Busy 2013/5/31 Scan Repeat AD monitor function interrupt AD monitor function control ADMOD3, 5 INTAD INTADHP INTADM0, 1 TBxRG0 Configuration Figure 20-1 AD Converter Block Diagram Internal data bus AD conversion result register ADCMP0,1 AD conversion result register ADREGSP AD conversion result register ADREG08 to 7F AD conversion end interrupt High priority AD conversion control Start High priority AD conversion end interrupt Interrupt Interval AD start control HPADCE ADMOD4 20.2 End 20.2 Busy 20. Analog / Digital Converter (ADC) TMPM361F10FG Configuration Figure 20-1 shows the block diagram of this AD converter. High priority AD conversion completion interrupt TMPM361F10FG 20.3 Registers 20.3.1 Register list The control registers and addresses of the AD converter are as follows. The AD converter is controlled by the AD mode control registers (ADMOD0 through ADMOD5). The result of AD conversion is stored in the eight AD conversion result registers, ADREG08 through ADREG7F. The highest-priority conversion result is stored in the register ADREGSP. To assure conversion accuracy, the specified value must be set to the ADCBAS register. Base Address = 0x400F_0000 Register name Address (Base+) Conversion Clock Setting Register ADCLK 0x0000 Mode Control Register 0 ADMOD0 0x0004 Mode Control Register 1 ADMOD1 0x0008 Mode Control Register 2 ADMOD2 0x000C Mode Control Register 3 ADMOD3 0x0010 Mode Control Register 4 ADMOD4 0x0014 Mode Control Register 5 ADMOD5 0x0018 Conversion Accuracy Setting Register ADCBAS 0x0020 Reserved - 0x0024 Reserved - 0x0028 Conversion Result Register 08 ADREG08 0x0030 Conversion Result Register 19 ADREG19 0x0034 Conversion Result Register 2A ADREG2A 0x0038 Conversion Result Register 3B ADREG3B 0x003C Conversion Result Register 4C ADREG4C 0x0040 Conversion Result Register 5D ADREG5D 0x0044 Conversion Result Register 6E ADREG6E 0x0048 Conversion Result Register 7F ADREG7F 0x004C Conversion Result Register SP ADREGSP 0x0050 Conversion Result Comparison Register 0 ADCMP0 0x0054 Conversion Result Comparison Register 1 ADCMP1 0x0058 Note:Access to the "Reserved" address is prohibited. Page 545 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.2 ADCBAS (Conversion Accuracy Setting Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 1 0 0 0 bit symbol After reset Bit ADCBAS 0 Bit Symbol 0 1 1 Type Function 31-8 − R Read as "0". 7-0 ADCBAS[7:0] R/W Write as "0x58". Note:To assure conversion accuracy, the specified value (0x0000_0058) must be set to the ADCBAS register. 2013/5/31 Page 546 TMPM361F10FG 20.3.3 ADCLK (Conversion Clock Setting Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol TSH After reset Bit 1 Bit Symbol 0 0 0 ADCLK 0 Type 0 0 0 Function 31-8 − R Read as "0". 7-4 TSH[3:0] R/W Select the AD sample hold time. 1000: 8 conversion clock 1001: 16 conversion clock 1010: 24 conversion clock 1011: 32 conversion clock 0011: 64 conversion clock 1100: 128 conversion clock 1101: 512 conversion clock Others : Reserved 3 − R Read as "0". 2-0 ADCLK[2:0] R/W Select the AD conversion clock 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 Others : Reserved A clock count required for conversion is 46 clocks at the minimum. Examples of sample hold time and conversion time as shown as below. (Example : If fc = 64MHz) Sample hold time Conversion time( setting) 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 1000 (8 conversion clock) 0.125 μs Reserved 1.44μs 2.88μs 5.75μs 11.5μs 1001 (16 conversion clock) 0.25 μs Reserved 1.69μs 3.38μs 6.75μs 13.5μs 1010 (24 conversion clock) 0.375 μs Reserved 1.94μs 3.88μs 7.75μs 15.5μs 1011 (32 conversion clock) 0.5 μs Reserved 2.19μs 4.38μs 8.75μs 17.5μs 0011 (64 conversion clock) 1.0 μs Reserved 3.19μs 6.38μs 12.75μs 25.5μs 1100 (128 conversion clock) 2.0 μs Reserved 5.19μs 10.38μs 20.75μs 41.5μs 1101 (512 conversion clock) 8.0 μs Reserved 17.19μs 34.38μs 68.75μs 137.5μs Page 547 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG (Example : If fc = 40MHz) Sample hold time Conversion time( setting) 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 1000 (8 conversion clock) 0.2 μs 1.15μs 2.3μs 4.6μs 9.2μs 18.4μs 1001 (16 conversion clock) 0.4 μs 1.35μs 2.7μs 5.4μs 10.8μs 21.6μs 1010 (24 conversion clock) 0.6 μs 1.55μs 3.1μs 6.2μs 12.4μs 24.8μs 1011 (32 conversion clock) 0.8 μs 1.75μs 3.5μs 7.0μs 14.0μs 28.0μs 0011 (64 conversion clock) 1.6 μs 2.55μs 5.1μs 10.2μs 20.4μs 40.8μs 1100 (128 conversion clock) 3.2 μs 4.15μs 8.3μs 16.6μs 33.2μs 66.4μs 1101 (512 conversion clock) 12.8 μs 13.75μs 27.5μs 55.0μs 110.0μs 220.0μs Note 1: Do not change the setting of the AD conversion clock during AD conversion. Note 2: Please use at ADCLK≤40MHz. When fosc is 8MHz and PLL is 8 times, fc is 64MHz, in this case, specify except ADCLK="000". 2013/5/31 Page 548 TMPM361F10FG 20.3.4 ADMOD0 (Mode Control Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 bit symbol EOCFN ADBFN - After reset 0 0 0 Bit Bit Symbol 3 ITM 0 0 Type 2 1 0 REPEAT SCAN ADS 0 0 0 Function 31-8 − R Read as "0". 7 EOCFN R Normal AD conversion completion flag (note1) 0: Before or during conversion 1: Completion 6 ADBFN R Normal AD conversion busy flag 0: Conversion stop 1: During conversion 5 − R Read as "0". 4-3 ITM[1:0] R/W Specify interrupt in fixed channel repeat conversion mode (refer to the table below and note 2) 2 REPEAT R/W Specify repeat mode 0: Single conversion mode 1: Repeat conversion mode 1 SCAN R/W Specify scan mode 0: Fixed channel mode 1: Channel scan mode 0 ADS R/W Start AD conversion start (note3) 0: Don't care 1: Start conversion Always read as "0". Specify AD conversion interrupt in fixed channel repeat conversion mode Fixed channel repeat conversion mode = "0", = "1" 00 Generate interrupt once every single conversion. 01 Generate interrupt once every 4 conversions. 10 Generate interrupt once every 8 conversions. 11 Setting prohibited Note 1: This bit is "0" cleared when it is read. Note 2: It is valid only when it’s specified in the fixed channel repeat mode ( ="1", = "0"). Note 3: Conversion must be started after setting the mode. Note 4: When DMA transfer is executed by utilizing AD conversion completion interrupts, perform software reset first. Then startup a DMA operation (DMA request wait mode), and start ADC setting. Page 549 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.5 ADMOD1 (Mode Control Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol VREFON I2AD ADSCN - After reset 0 0 0 0 0 0 Bit Bit Symbol ADCH 0 Type 0 Function 31-8 − R Read as "0". 7 VREFON R/W VREF application control(Note1 and Note2) 0: OFF 1: ON 6 I2AD R/W Specify operation mode in IDLE mode 0: STOP 1: Operation 5 ADSCN R/W Specify operation mode in channel scan mode 0: 4 channel scan 1: 8 channel scan 4 − R/W Write as "0". 3-0 ADCH[3:0] R/W Select analog input channel (Refer to the below table.) Select Analog Input Channel ADMOD0 0 1 1 Fixed channel Channel scan Channel scan ( = 0) ( = 1) ADMOD1 0000 AIN0 AIN0 AIN0 0001 AIN1 AIN0 to AIN1 AIN0 to AIN1 0010 AIN2 AIN0 to AIN2 AIN0 to AIN2 0011 AIN3 AIN0 to AIN3 AIN0 to AIN3 0100 AIN4 AIN4 AIN0 to AIN4 0101 AIN5 AIN4 to AIN5 AIN0 to AIN5 0110 AIN6 AIN4 to AIN6 AIN0 to AIN6 0111 AIN7 AIN4 to AIN7 AIN0 to AIN7 1000 1001 1010 1011 1100 Reserved 1101 1110 1111 Note 1: Before starting AD conversion, write "1" to the bit, wait for 3μs during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0. Note 2: Set to "0" to go into standby mode upon completion of AD conversion. 2013/5/31 Page 550 TMPM361F10FG 20.3.6 ADMOD2 (Mode Control Register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol EOCFHP ADBFHP HPADCE - After reset 0 0 0 0 0 0 Bit Bit Symbol Type HPADCH 0 0 Function 31-8 − R Read as "0". 7 EOCFHP R Top-priority AD conversion completion flag (Note1) 0: Before or during conversion 1: Completion 6 ADBFHP R Top-priority AD conversion BUSY flag 0: During conversion halts 1: During conversion 5 HPADCE R/W Activate top-priority conversion 0: Don't care 1: Start conversion "0" is always read. 4 − R/W Write as "0". 3-0 HPADCH[3:0] R/W Select analog input channel when activating top-priority conversion. (See the table below) Analog input channel when executing top-priority conversion 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 1001 1010 1011 1100 Reserved 1101 1110 1111 Note 1: This bit is "0" cleared when it is read. Page 551 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG Note 2: Specify after selecting channel. 2013/5/31 Page 552 TMPM361F10FG 20.3.7 ADMOD3 (Mode Control Register 3) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 4 3 2 1 7 6 5 bit symbol - - ADOBIC0 After reset 0 0 0 Bit Bit Symbol ADREGS0 0 Type 0 0 ADOBSV0 0 0 0 Function 31-8 − R Read as "0". 7 − R/W Write as "0". 6 − R Read as "0". 5 ADOBIC0 R/W Set the AD monitor function interrupt 0 0 : If the value of the conversion result is smaller than the comparison register 0, an interrupt is generated. 1 : If the value of the conversion result is bigger than the comparison register 0, an interrupt is generated. 4 to 1 ADREGS0[3:0] R/W Select a target conversion result register when using the AD monitor function 0 (See the below table). 0 ADOBSV0 R/W AD monitor function 0 0: Disable 1: Enable Conversion result register to be compared Conversion result register to be compared 0000 ADREG08 0100 ADREG4C 0001 ADREG19 0101 ADREG5D 0010 ADREG2A 0110 ADREG6E 0011 ADREG3B 0111 ADREG7F - - 1xxx ADREGSP Page 553 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.8 ADMOD4 (Mode Control Register 4) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol HADHS HADHTG ADHS ADHTG - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 ADRST 0 0 Function 31-8 − R Read as "0". 7 HADHS R/W H/W source for activating top-priority AD conversion 0: External trigger 1: Match with timer register 0 (TB5RG0) 6 HADHTG R/W H/W for activating top-priority AD conversion 0: Disable 1: Enable 5 ADHS R/W H/W source for activating normal AD conversion (note1) 0: External trigger 1: Match with timer register (TB6RG0) 4 ADHTG R/W H/W for activating normal AD conversion 0: Disable 1: Enable 3-2 − R Read as "0". 1-0 ADRST[1:0] W Overwriting "10" with "01" allows ADC to be software reset.(note 2) Note 1: The external trigger cannot be used for H/W activation of AD conversion when it is used for H/W activation of top priority AD conversion. Note 2: A software reset initializes all the registers except for ADCLK. Note 3: The disables the external trigger used for H/W activation. Therefore "0" cannot be set to and . 2013/5/31 Page 554 TMPM361F10FG 20.3.9 ADMOD5 (Mode Control Register 5) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 4 3 2 1 7 6 5 bit symbol - - ADOBIC1 After reset 0 0 0 Bit Bit Symbol ADREGS1 0 Type 0 0 ADOBSV1 0 0 0 Function 31-6 − R Read as "0". 5 ADOBIC1 R/W Set the AD monitor function interrupt 1. 0: If the value of the conversion result is smaller than the comparison register 1, an interrupt is generated. 1: If the value of the conversion result is bigger than the comparison register 1, an interrupt is generated. 4-1 ADREGS1[3:0] R/W Select a target conversion result register when using the AD monitor function 1 (See the below table). 0 ADOBSV1 R/W AD monitor function1 0: Disable 1: Enable Conversion result register to be compared Conversion result register to be compared 0000 ADREG08 0100 ADREG4C 0001 ADREG19 0101 ADREG5D 0010 ADREG2A 0110 ADREG6E 0011 ADREG3B 0111 ADREG7F − − 1xxx ADREGSP Page 555 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.10 ADREG08 (Conversion Result Register 08) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR0 ADR0RF 0 0 0 0 0 0 bit symbol ADR0 After reset 7 bit symbol ADR0 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR0[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR0 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR0RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. 2013/5/31 Page 556 TMPM361F10FG 20.3.11 ADREG19 (AD Conversion Result Register 19) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR1 ADR1RF 0 0 0 0 0 0 bit symbol ADR1 After reset 7 bit symbol ADR1 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR1[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR1 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR1RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 557 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.12 ADREG2A (AD Conversion Result Register 2A) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR2 ADR2RF 0 0 0 0 0 0 bit symbol ADR2 After reset 7 bit symbol ADR2 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR2[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR2 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR2RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. 2013/5/31 Page 558 TMPM361F10FG 20.3.13 ADREG3B (AD Conversion Result Register 3B) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR3 ADR3RF 0 0 0 0 0 0 bit symbol ADR3 After reset 7 bit symbol ADR3 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR3[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR3 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR3RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 559 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.14 ADREG4C (AD Conversion Result Register 4C) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR4 ADR4RF 0 0 0 0 0 0 bit symbol ADR4 After reset 7 bit symbol ADR4 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR4[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR4 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR4RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. 2013/5/31 Page 560 TMPM361F10FG 20.3.15 ADREG5D (AD Conversion Result Register 5D) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR5 ADR5RF 0 0 0 0 0 0 bit symbol ADR5 After reset 7 bit symbol ADR5 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR5[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR5 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR5RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 561 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.16 ADREG6E (AD Conversion Result Register 6E) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR6 ADR6RF 0 0 0 0 0 0 bit symbol ADR6 After reset 7 bit symbol ADR6 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR6[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR6 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR6RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. 2013/5/31 Page 562 TMPM361F10FG 20.3.17 ADREG7F (AD Conversion Result Register 7F) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVR7 ADR7RF 0 0 0 0 0 0 bit symbol ADR7 After reset 7 bit symbol ADR7 After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADR7[9:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to the Table 20-2 in 20.4.5.7. 5-2 − R Read as "0". 1 OVR7 R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADR7RF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. Page 563 2013/5/31 20. 20.3 Analog / Digital Converter (ADC) Registers TMPM361F10FG 20.3.18 ADREGSP (AD Conversion Result Register SP) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - OVRSP ADRSPRF 0 0 0 0 0 0 bit symbol ADRSP After reset 7 bit symbol ADRSP After reset Bit 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADRSP[9:0] R AD conversion result Top-priority AD conversion result is stored. 5-2 − R Read as "0". 1 OVRSP R Overrun flag 0: Not generated 1: Generated If the conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when it is read. 0 ADRSPRF R AD conversion result storage flag 0:Conversion result is not stored 1: Conversion result is stored. If a conversion result is stored, "1" is set. This bit is "0" cleared when the conversion result is read. Note:Access to this register must be a half word or a word access. 2013/5/31 Page 564 TMPM361F10FG 20.3.19 ADCMP0 (AD Conversion Result Comparison Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0 - - - - - - 0 0 0 0 0 0 bit symbol After reset ADCOM0 7 bit symbol After reset Bit ADCOM0 0 Bit Symbol 0 Type Function 31-16 − R Read as "0". 15-6 ADCOM0[9:0] R/W When AD monitor function 0 is enabled, it sets a value to be compared with the value of the conversion result register specified by ADMOD3. 5-0 − R Read as "0". Note:To write values into this register, the AD monitor function 0 must be disabled (ADMOD3 ="0"). 20.3.20 bit symbol After reset ADCMP1 (AD Conversion Result Comparison Register 1) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol After reset ADCOM1 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - - - 0 0 0 0 0 0 0 bit symbol After reset Bit ADCOM1 0 Bit Symbol Type Function 31-16 − R Read as "0". 15-6 ADCOM1[9:0] R/W When AD monitor function 0 is enabled, it sets a value to be compared with the value of the conversion result register specified by ADMOD5. 5-0 − R Read as "0". Note:To write values into this register, the AD monitor function 1 must be disabled (ADMOD5 ="0"). Page 565 2013/5/31 20. 20.4 Analog / Digital Converter (ADC) Description of Operations 20.4 TMPM361F10FG Description of Operations 20.4.1 Analog Reference Voltage The "High" level of the analog reference voltage shall be applied to the VRFEH pin, and the "Low" shall be applied to the VREFL pin. To start AD conversion, make sure that you first write "1" to the bit, wait for 3 μs during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0 bit. By writing "0" to the ADMOD1 bit, a switched-on state of VREFH - VREFL can be turned into a switched -off state. To switch to the power-consumption mode, set "0" to the bit after conversion. Note:VREFL and AVSS are shared by TMPM361F10FG. 20.4.2 AD Conversion Mode Two types of AD conversion are supported: normal AD conversion and top-priority AD conversion. For normal AD conversion, the following four operation modes are supported. 20.4.2.1 Normal AD conversion For normal AD conversion, the following four operation modes are supported and the operation mode is selected with the ADMOD0. ・ ・ ・ ・ (1) Fixed channel single conversion mode Channel scan single conversion mode Fixed channel repeat conversion mode Channel scan repeat conversion mode Fixed channel single conversion mode If ADMOD0 is set to "00", "AD conversion is performed in the fixed channel single conversion mode. In this mode, AD conversion is performed once for one channel selected. After AD conversion is completed, ADMOD0 is set to "1", ADMOD0 is cleared to "0", and the AD conversion completion interrupt request (INTAD) is generated. is cleared to "0" upon read. (2) Channel scan single conversion mode If ADMOD0 is set to "01", "AD conversion is performed in the channel scan single conversion mode. In this mode, AD conversion is performed once for each scan channel selected. After AD scan conversion is completed, ADMOD0 is set to "1", ADMOD0 is cleared to "0", and the conversion completion interrupt request (INTAD) is generated. is cleared to "0". 2013/5/31 Page 566 TMPM361F10FG (3) Fixed channel repeat conversion mode If ADMOD0 is set to "10", AD conversion is performed in fixed channel repeat conversation mode. In this mode, AD conversion is performed repeatedly for one channel selected. After AD conversion is completed, ADMOD0 is set to "1". ADMOD0 is not cleared to "0". It remains at "1". The timing with which the conversion completion interrupt request (INTAD) is generated can be selected by setting ADMOD0 to an appropriate setting. is set with the same timing as this interrupt INTAD is generated. By reading , it is cleared to "0". (4) Channel scan repeat conversion mode If ADMOD0 is set to "11", AD conversion is performed in the channel scan repeat conversion mode. In this mode, AD conversion is performed repeatedly for a scan channel selected. Each time one AD scan conversion is completed, ADMOD0 is set to "1", and the conversion completion interrupt request (INTAD) is generated. ADMOD0 is cleared to "0". It remains at "1". is cleared to "0" upon read. 20.4.2.2 Top-priority AD conversion By interrupting ongoing normal AD conversion, top-priority AD conversion can be performed. The fixed-channel single conversion is automatically selected, irrespective of the ADMOD0 setting. When conditions to start operation are met, a conversion is performed just once for a channel designated by ADMOD2. When conversion is completed, the top-priority AD conversion completion interrupt (INTADHP) is generated, and ADMOD2 showing the completion of AD conversion is set to "1". returns to "0". EOCFHP flag is cleared to "0" upon read. Top-priority AD conversion activated while top-priority AD conversion is under way is ignored. Note:Top-priority A/D conversion interrupt cannot generate DMA transfer request.To generate DMA transfer request, please use A/D conversion completion interrupt (INTAD). 20.4.3 AD Monitor Function There are two channels of AD monitor function. If ADMOD3 and ADMOD5 are set to "1", the AD monitor function is enabled. If the value of the conversion result register specified by ADMOD3 and ADMOD5 becomes larger or smaller ("Larger" or "Smaller" to be designated by ADMOD3 and ADMOD5) than the value of a comparison register, the AD monitor function interrupt (INTADM0,INTADM1) is generated. This comparison operation is performed each time a result is stored in a corresponding conversion result register. If the conversion result register assigned to perform the AD monitor function is continuously used without reading the conversion result, the conversion result is overwritten. The conversion result storage flag and the overrun flag remain being set. Page 567 2013/5/31 20. 20.4 Analog / Digital Converter (ADC) Description of Operations 20.4.4 TMPM361F10FG Selecting the Input Channel After a reset, ADMOD0 is initialized to "00" and ADMOD1 is initialized to "0000". The channels to be converted are selected according to the operation mode of the AD converter as shown below. 1. Normal AD conversion mode ・ If the analog input channel is used in a fixed state (ADMOD0 = "0") One channel is selected from analog input pins AIN0 through AIN7 by setting ADMOD1 to an appropriate setting. ・ If the analog input channel is used in a scan state (ADMOD0 = "1") One scan mode is selected from the scan modes by setting ADMOD1 and ADSCN to an appropriate setting. 2. Top-priority AD conversion mode One channel is selected from analog input pins from AIN0 through AIN7 by setting ADMOD2 to an appropriate setting. 20.4.5 AD Conversion Details 20.4.5.1 Starting AD Conversion Normal AD conversion is activated by setting ADMOD0 to "1". Top-priority AD conversion is activated by setting ADMOD2 to "1". Four operation modes are made available to normal AD conversion. In performing normal AD conversion, one of these operation modes must be selected by setting ADMOD0 to an appropriate setting. For top-priority AD conversion, only one operation mode can be used: fixed channel single conversion mode. Normal AD conversion can be activated using the H/W activation source selected by ADMOD4, and top-priority AD conversion can be activated using the HW activation source selected by ADMOD4. If bits of and are "0", normal and top-priority AD conversions are activated in response to the input of a falling edge through the ADTRG pin. If these bits are "1", normal AD conversion is activated in response to TB6RG0 generated by the 16-bit timer 6, and top-priority AD conversion is activated in response to TB5RG0 generated by the 16-bit timer 5. To permit H/W activation, set ADMOD4 to "1" for normal AD conversion and set ADMOD4 to "1" for top-priority AD conversion. Software activation is still valid even after H/W activation has been permitted. Note 1: When an external trigger is used for the HW activation source of a top-priority AD conversion, an external trigger cannot be set for activating normal AD conversion H/W. Note 2: TMPM361F10FG disables the external trigger used for H/W activation. Therefore "0" cannot be set to and . 2013/5/31 Page 568 TMPM361F10FG 20.4.5.2 AD Conversion When normal AD conversion starts, the AD conversion Busy flag (ADMOD0) showing that AD conversion is under way is set to "1". When top-priority AD conversion starts, the top-priority AD conversion Busy flag (ADMOD2) showing that AD conversion is underway is set to "1". At that time, the value of the Busy flag ADMOD0 for normal AD conversion before the start of top-priority AD conversions are retained. The value of the conversion completion flag ADMOD0 for normal AD conversion before the start of top-priority AD conversion is retained. . Note:Normal AD conversion must not be activated when top-priority AD conversion is under way. 20.4.5.3 Top-priority AD conversion during normal AD conversion If top-priority AD conversion has been activated during normal AD conversion, ongoing normal AD conversion is suspended, and restarts normal AD conversion after top-priority AD conversion is completed. If ADMOD2 is set to "1" during normal AD conversion, ongoing normal AD conversion is suspended, and the top-priority AD conversion starts; specifically, AD conversion (fixed-channel single conversion) is executed for a channel designated by ADMOD2. After the result of this toppriority AD conversion is stored in the storage register ADREGSP, normal AD conversion is resumed. If H/W activation of top-priority AD conversion is authorized during normal AD conversion, ongoing AD conversion is discontinued when requirements for activation using a H/W activation resource are met, and top-priority AD conversion (fixed-channel single conversion) starts for a channel designated by ADMOD2. After the result of this top-priority AD conversion is stored in the storage register ADREGSP, normal AD conversion is resumed. For example, if channel repeat conversion is activated for channels AIN0 through AIN3 and if is set to "1" during AIN2 conversion, AIN2 conversion is suspended, and conversion is performed for a channel designated by (AIN7 in the case shown below). After the result of conversion is stored in ADREGSP, channel repeat conversion is resumed, starting from AIN2. Top-priority AD has been activated Conversion channel 20.4.5.4 Ch0 Ch1 Ch2 Ch7 Ch2 Ch3 Ch0 Stopping Repeat Conversion Mode To stop the AD conversion operation in the repeat conversion mode (fixed-channel repeat conversion mode or channel scan repeat conversion mode), write "0" to ADMOD0. When ongoing AD conversion is completed, the repeat conversion mode terminates, and ADMOD0 is set to "0". Page 569 2013/5/31 20. 20.4 Analog / Digital Converter (ADC) Description of Operations 20.4.5.5 TMPM361F10FG Reactivating normal AD conversion To reactivate normal AD conversion while the conversion is underway, a software reset (ADMOD3) must be performed before starting AD conversion. The H/W activation method must not be used to reactivate normal AD conversion. 20.4.5.6 Conversion completion (1) Normal AD conversion completion When normal AD conversion is completed, the AD conversion completion interrupt (INTAD) is generated. The result of AD conversion is stored in the storage register is the storage register, and two registers change: the register ADMOD0 which indicates the completion of AD conversion and the register ADMOD0.Interrupt request, conversion register storage register and change with a different timing according to a mode selected. In mode other than fixed-channel repeat conversion mode, conversion results are stored in AD conversion result registers (ADREG08 through ADRG7F) corresponding to a channel. In fixed-channel repeat conversion mode, the conversion results are sequentially stored in storage registers ADREG08 through ADREG7F. However, if interrupt setting on is set to be generated each time one AD conversion is completed, the conversion result is stored only in ADREG08. If interrupt setting on is set to be generated each time four AD conversions are completed, the conversion results are sequentially stored in ADREG08H through ADREG3B.If interrupt setting on is set to be generated each time eight AD conversions are completed, the conversion results are sequentially stored in ADREG08H through ADREG7F. Interrupt requests, flag changes and conversion result registers in each mode are as shown below. ・ Fixed-channel single conversion mode After AD conversion completed, ADMOD0 is set to "1", ADMOD0 is cleared to "0", and the interrupt request is generated. Conversion results are stored a conversion result register correspond to a channel. ・ Channel scan single conversion mode After the channel scan conversion is completed, ADMOD0 is set to "1", ADMOD0 is set to "0", and the interrupt request INTAD is generated. Conversion results are stored a conversion result register correspond to a channel. ・ Fixed-channel repeat conversion mode ADMOD0 is not cleared to "0". It remains at "1". The timing with which the interrupt request INTAD is generated can be selected by setting ADMOD0 to an appropriate setting. ADMOD0 is set with the same timing as this interrupt INTAD is generated. a. One conversion With set to "00", an interrupt request is generated each time one AD conversion is completed. In this case, the conversion results are always stored in the storage register ADREG08. After the conversion result is stored, changes to "1". b. Four conversions 2013/5/31 Page 570 TMPM361F10FG With set to "01", an interrupt request is generated each time four AD conversions are completed. In this case, the conversion results are sequentially stored in the storage register ADREG08 through ADREG3B. After the conversion result is stored in ADREG3B, is set to "1", and the storage of subsequent conversion results starts from ADREG08. c. 8 conversions With set to "10", an interrupt request is generated each time eight AD conversions are completed. In this case, the conversion results are sequentially stored in the storage register ADREG08 through ADREG7F. After the conversion result is stored in ADREG7F, is set to "1", and the storage of subsequent conversion results starts from ADREG08. ・ Channel scan repeat conversion mode Each time one AD conversion is completed, ADMOD0 is set to "1" and interrupt request INTAD is generated. ADMOD0 is not cleared to "0". It remains at "1". AD conversion results are stored in a AD conversion result register corresponding to a channel. (2) Top-priority AD conversion completion After the AD conversion is completed, the top-priority AD conversion completion interrupt (INTADHP) is generated, and ADMOD2 which indicates the completion of top-priority AD conversion is set to "1". AD conversion results are stored in the AD conversion result register SP. (3) Data polling To confirm the completion of AD conversion without using interrupts, data polling can be used. When AD conversion is completed, ADMOD0 is set to "1". To confirm the completion of AD conversion and to obtain the results, poll this bit. AD conversion result storage register must be read by half word or word access. If = "0" and = "1", a correct conversion result has been obtained. Page 571 2013/5/31 20. 20.4 Analog / Digital Converter (ADC) Description of Operations 20.4.5.7 TMPM361F10FG Interrupt generation timings and AD conversion result storage register Table 20-1shows a relation in the following three items: AD conversion modes, interrupt generation timings and flag operations.Table 20-2 shows a relation between analog channel inputs and AD conversion result registers. Table 20-1 Relations in conversion modes, interrupt generation timings and flag operations Scan / repeat mode setting / (ADMOD0) Interrupt generation timing Conversion mode Fixed-channel single conversion Fixed-channel repeat conversion After generation is completed. After conversion is completed. 0 − 00 Each time one conversion is completed. After one conversion is completed. 1 − 01 Each time four conversion is completed. After four conversions are completed. 1 − 10 Each time eight conversion is completed. After eight conversions are completed. 1 − 0 0 − Normal conversion (After the interrupt is generated) 0 set timing ADMOD2 (note) 1 ADMOD0 Channel scan single conversion 0 1 − After scan conversion is completed. After scan conversion is completed. 0 − Channel scan repeat conversion 1 1 − After one scan conversion is completed. After one scan conversion is completed. 1 − − − − After completion is completed. Conversion completion − 0 Top-priority conversion Note:ADMOD0 and ADMOD2 are cleared upon read. Table 20-2 Relation between analog channels input and AD conversion result registers Normal AD conversion Analog input channels AIN0 Fixed channel repeat Other conversion conversion mode mode than those shown on the right side (every one conversion) ADREG08 AIN1 ADREG19 AIN2 ADREG2A AIN3 ADREG3B AIN4 ADREG4C AIN5 ADREG5D AIN6 ADREG6E AIN7 ADREG7F Fixed channel repeat conversion mode Fixed channel repeat conversion mode (every four conversions) (every eight conversions) ADREG08 fixed ADREGSP ADREG08 ω ω ADREG3B ADREG08 ↓ ↓ ↓ ADREG7F Note:To access the conversion result register, use a half-word or a word access. 2013/5/31 Top-priority AD conversion Page 572 TMPM361F10FG Cautions The result value of AD conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. When using analog input pins and ports alternately, do not read and write ports during conversion because the conversion accuracy may be reduced. Also the conversion accuracy may be reduced if the output ports current fluctuate during AD conversion. Please take counteractive measures with the program such as averaging the AD conversion results. Page 573 2013/5/31 20. 20.4 Analog / Digital Converter (ADC) Description of Operations 2013/5/31 TMPM361F10FG Page 574 TMPM361F10FG 21. Real Time Clock (RTC) 21.1 Function 1. Clock (hour, minute and second) 2. Calendar (month, week, date and leap year) 3. Selectable 12 (am/ pm) and 24 hour display 4. Time adjustment + or − 30 seconds (by software) 5. Alarm (alarm output) 6. Alarm interrupt 21.2 Block Diagram Clock (fs) 16 Hz clock Sec.counter 1 Hz clock Alarm register Alarm selector Comparator ALARM INTRTC Clock Internal address bus R/W control Adjust RD Internal data bus WR Data Address Figure 21-1 Block Diagram Note 1: Western calendar year column:This product uses only the final two digits of the year. The year following 99 is 00 years. Please take into account the first two digits when handling years in the western calendar. Note 2: Leap year:A leap year is divisible by 4 excluding a year divisible by 100; the year divisible by 100 is not considered to be a leap year. Any year divisible by 400 is a leap year. This product is considered the year divisible by 4 to be a leap year and does not take into account the above exceptions. It needs adjustments for the exceptions. Page 575 2013/5/31 21. 21.3 Real Time Clock (RTC) Detailed Description Register 21.3 TMPM361F10FG Detailed Description Register 21.3.1 Register List The registers and the addresses related to RTC are shown as below. RTC has two functions, PAGE0 (clock) and PAGE1 (alarm), which share some parts of registers. The PAGE can be selected by setting RTCPAGER. Base Address = 0x4004_0100 Register name Address(Base+) Second column register (only PAGE0) Minute column register Hour column register - (note 1) Day of the week column register Day column register Month column register (PAGE0) Selection register of 24-hour,12-hour (PAGE1) Year column register (PAGE0) Leap year register (PAGE1) PAGE register RTCSECR 0x0000 RTCMINR 0x0001 RTCHOURR 0x0002 - 0x0003 RTCDAYR 0x0004 RTCDATER 0x0005 RTCMONTHR 0x0006 RTCYEARR 0x0007 RTCPAGER 0x0008 - (note 1) - 0x0009 - (note 1) - 0x000A - (note 1) - 0x000B RTCRESTR 0x000C Reserved - 0x000D - (note 1) - 0x000E - (note 1) - 0x000F Reset register Note 1: "0" is read by reading the address. Writing is disregarded. Note 2: Access to the "Reserved" areas is prohibited. 21.3.2 Control Register Reset operation initializes the following registers. ・ RTCPAGER, , ・ RTCRESTR, , , Other clock-related registers are not initialized by reset operation. Before using the RTC, set the time, month, day, day of the week, year and leap year in the relevant registers. Caution is required in setting clock data, adjusting seconds or resetting the clock. Refer to "21.4.3 Entering the Low Power Consumption Mode" for more information. 2013/5/31 Page 576 TMPM361F10FG Table 21-1 PAGE0 (clock function) register Symbol Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function RTCSECR − 40sec. 20sec. 10sec. 8sec. 4sec. 2sec. 1sec. Second column RTCMINR − 40min. 20min. 10min. 8min. 4min. 2min. 1min. Minute column 10hour 8hour 4hour 2hour 1hours Hour column RTCHOURR − − 20hours PM/AM RTCDAYR − − − − − RTCDATER − − Day20 Day10 Day8 Day4 Day2 Day1 Day column RTCMONTHR − − − Oct. Aug. Apr. Feb. Jan. Month column RTCYEARR year 80 year 40 year20 year 10 year 8 year 4 year 2 year 1 − − 1 Hz 16 Hz Clock Alarm enable enable reset reset RTCPAGER RTCRESTR Interrupt enable Day of the week Adjustment Clock Alarm function enable enable − − Day of the week column Year column (lower two columns) PAGE PAGE setting register Reset Always write "1" register Note:Reading RTCSECR, RTCMINR, RTCHOURR, RTCDAYR, RTCMONTHR, RTCYEARR of PAGE0 captures the current state. Table 21-2 PAGE1 (alarm function) registers Symbol Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function RTCSECR − − − − − − − − − RTCMINR − 40min. 20min. 10min. 8min. 4min. 2min. 1min. Minute column 10hour 8hour 4hour 2hour 1hour Hour column RTCHOURR − − 20hours PM/AM RTCDAYR − − − − − RTCDATER − − Day20 Day10 Day8 Day4 Day2 Day1 Day column RTCMONTHR − − − − − − − 24/12 24-hour clock mode − − − RTCYEARR RTCPAGER RTCRESTR Interrupt − − − Adjustment Clock Alarm function enable enable − − 1 Hz 16 Hz Clock Alarm Enable Enable reset reset enable Day of the week − Day of the week column Leap-year setting Always write "1" − Leap-year mode PAGE PAGE setting register Reset register Note 1: Reading RTCMINR, RTCHOURR, RTCDAYR, RTCMONTHR, RTCYEARR of PAGE1 captures the current state. Note 2: RTCSECR, RTCMINR, RTCHOURR, RTCDAYR, RTCDATER, RTCMONTHR, RTCYEARR of PAGE0 and RTCYEARR of PAGE1 (for leap year) must be read twice and compare the data captured. Page 577 2013/5/31 21. 21.3 Real Time Clock (RTC) Detailed Description Register 21.3.3 TMPM361F10FG Detailed Description of Control Register 21.3.3.1 RTCSECR (Second column register (for PAGE0 only)) 7 bit symbol - After reset 0 Bit Bit Symbol 6 5 4 3 2 1 0 Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined SE Undefined Undefined Undefined Undefined Type Functon 7 − R Read as 0. 6-0 SE R/W Setting digit register of second 000_0000 : 00sec. 001_0000 : 10sec. 000_0001 : 01sec. 001_0001 : 11sec. 010_0000 : 20sec. ・ 000_0010 : 02sec. 001_0010 : 12sec. 011_0000 : 30sec. 000_0011 : 03sec. 001_0011 : 13sec. ・ 000_0100 : 04sec. 001_0100 : 14sec. 100_0000 : 40sec. 000_0101 : 05sec. 001_0101 : 15sec. ・ 000_0110 : 06sec. 001_0110 : 16sec. 101_0000 : 50sec. 000_0111 : 07sec. 001_0111 : 17sec. ・ 000_1000 : 08sec. 001_1000 : 18sec. ・ 000_1001 : 09sec. 001_1001 : 19sec. 101_1001 : 59sec. Note:The setting other than listed above is prohibited. 21.3.3.2 RTCMINR (Minute column register (PAGE0/1)) 7 Bit symbol - After reset 0 Bit Bit Symbol 6 5 4 Undefined Undefined Undefined Undefined Type Functon 7 − R Read as 0. 6-0 MI R/W Setting digit register of Minutes. 000_0000 : 00min. 001_0000 : 10min. 000_0001 : 01min. 001_0001 : 11min. ・ 000_0010 : 02min. 001_0010 : 12min. 011_0000 : 30min. 000_0011 : 03min. 001_0011 : 13min. ・ 000_0100 : 04min. 001_0100 : 14min. 100_0000 : 40min. 000_0101 : 05min. 001_0101 : 15min. ・ 000_0110 : 06min. 001_0110 : 16min. 101_0000 : 50min. 000_0111 : 07min. 001_0111 : 17min. ・ 000_1000 : 08min. 001_1000 : 18min. ・ 000_1001 : 09min. 001_1001 : 19min. 101_1001 : 59min. Note:The setting other than listed above is prohibited. 2013/5/31 3 MI Page 578 010_0000 : 20min. TMPM361F10FG 21.3.3.3 RTCHOURR (Hour column register(PAGE0/1)) 24-hour clock mode (RTCMONTHR= "1") (1) 7 6 Bit symbol - - After reset 0 0 Bit Bit Symbol 5 4 3 Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined HO Type Functon 7-6 − R Read as 0. 5-0 HO R/W Setting digit register of Hour. 00_0000 : 0 o’clock 01_0000 : 10 o’clock 10_0000 : 20 o’clock 00_0001 : 1 o’clock 01_0001 : 11 o’clock 10_0001 : 21 o’clock 00_0010 : 2 o’clock 01_0010 : 12 o’clock 10_0010 : 22 o’clock 00_0011 : 3 o’clock 01_0011 : 13 o’clock 10_0011 : 23 o’clock 00_0100 : 4 o’clock 01_0100 : 14 o’clock 00_0101 : 5 o’clock 01_0101 : 15 o’clock 00_0110 : 6 o’clock 01_0110 : 16 o’clock 00_0111 : 7 o’clock 01_0111 : 17 o’clock 00_1000 : 8 o’clock 01_1000 : 18 o’clock 00_1001 : 9 o’clock 01_1001 : 19 o’clock Note:The setting other than listed above is prohibited. (2) 12-hour clock mode (RTCMONTHR = "0") 7 6 Bit symbol - - After reset 0 0 Bit Bit Symbol 5 4 3 Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined HO Type Functon 7-6 − R Read as 0. 5-0 HO R/W Setting digit register of Hour. (AM) (PM) 00_0000 : 0 o’clock 10_0000 : 0 o’clock 00_0001 : 1 o’clock 10_0001 : 1 o’clock 00_0010 : 2 o’clock 10_0010 : 2 o’clock 00_0011 : 3 o’clock 10_0011 : 3 o’clock 00_0100 : 4 o’clock 10_0100 : 4 o’clock 00_0101 : 5 o’clock 10_0101 : 5 o’clock 00_0110 : 6 o’clock 10_0110 : 6 o’clock 00_0111 : 7 o’clock 10_0111 : 7 o’clock 00_1000 : 8 o’clock 10_1000 : 8 o’clock 00_1001 : 9 o’clock 10_1001 : 9 o’clock 01_0000 : 10 o’clock 11_0000 : 10 o’clock 01_0001 : 11 o’clock 11_0001 : 11 o’clock Note:The setting other than listed above is prohibited. Page 579 2013/5/31 21. 21.3 Real Time Clock (RTC) Detailed Description Register 21.3.3.4 TMPM361F10FG RTCDAYR (Day of the week column register(PAGE0/1)) 7 6 5 4 3 Bit symbol - - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type 2 1 0 WE Undefined Undefined Undefined 2 1 0 Undefined Undefined Undefined Function 7-3 − R Read as 0. 2-0 WE R/W Setting digit register of day of the week. 000: Sunday 001: Monday 010: Tuesday 011: Wednesday 100: Thursday 101: Friday 110: Saturday Note:The setting other than listed above is prohibited. 21.3.3.5 RTCDATER (Day column register (for PAGE0/1 only)) 7 6 Bit symbol - - After reset 0 0 Bit Bit Symbol 5 4 3 Undefined Undefined Undefined DA Type Functon 7-6 − R Read as 0. 5-0 DA R/W Setting digit register of day. 01_0000 : 10th day 10_0000 : 20th day 11_0000 : 30th day 00_0001 : 1st day 01_0001 : 11th day 10_0001 : 21th day 11_0001 : 31th day 00_0010 : 2nd day 01_0010 : 12th day 10_0010 : 22th day 00_0011 : 3rd day 01_0011 : 13th day 10_0011 : 23th day 00_0100 : 4th day 01_0100 : 14th day 10_0100 : 24th day 00_0101 : 5th day 01_0101 : 15th day 10_0101 : 25th day 00_0110 : 6th day 01_0110 : 16th day 10_0110 : 26th day 00_0111 : 7th day 01_0111 : 17th day 10_0111 : 27th day 00_1000 : 8th day 01_1000 : 18th day 10_1000 : 28th day 00_1001 : 9th day 01_1001 : 19th day 10_1001 : 29th day Note 1: The setting other than listed above is prohibited. Note 2: Do not set for non-existent days (e.g. 30th Feb.). 2013/5/31 Page 580 TMPM361F10FG 21.3.3.6 RTCMONTHR (Month column register (for PAGE0 only)) 7 6 5 Bit symbol - - - After reset 0 0 0 Bit Bit Symbol 4 3 2 1 0 Undefined Undefined MO Undefined Undefined Type Undefined Functon 7-5 − R Read as 0. 4-0 MO R/W Setting digit register of Month. 0_0001 : January 0_0111 : July 0_0010 : February 0_1000 : August 0_0011 : March 0_1001 : September 0_0100 : April 1_0000 : October 0_0101 : May 1_0001 : November 0_0110 : June 1_0010 : December Note:The setting other than listed above is prohibited. 21.3.3.7 RTCMONTHR (Selection of 24-hour clock or 12-hour clock (for PAGE1 only)) 7 6 5 4 3 2 1 0 bit symbol - - - - - - - MO0 After reset 0 0 0 0 0 0 0 Undefined Bit Bit Symbol Type Function 7-1 − R Read as 0. 0 MO0 R/W 0: 12-hour 1: 24-hour Note:Do not change the RTCMONTHR while the RTC is in operation. Page 581 2013/5/31 21. 21.3 Real Time Clock (RTC) Detailed Description Register 21.3.3.8 TMPM361F10FG RTCYEARR (Year column register (for PAGE0 only)) 7 6 5 4 bit symbol After reset Bit 7-0 3 2 1 0 Undefined Undefined Undefined Undefined YE Undefined Bit Symbol YE Undefined Undefined Undefined Type R/W Function Setting digit register of Year. 0000_0000 : 00 year 0001_0000 : 10 years 0000_0001 : 01 years ・ 0110_0000 : 60 years ・ 0000_0010 : 02 years 0010_0000 : 20 years 0111_0000 : 70 years 0000_0011 : 03 years ・ ・ 0000_0100 : 04 years 0011_0000 : 30 years 1000_0000 : 80 years 0000_0101 : 05 years ・ ・ 0000_0110 : 06 years 0100_0000 : 40 years 1001_0000 : 90 years 0000_0111 : 07 years ・ ・ 0000_1000 : 08 years 01001_0000 : 50 years ・ 0000_1001 : 09 years ・ 1001_1001 : 99 years Note:The setting other than listed above is prohibited. 21.3.3.9 RTCYEARR (Leap year register (for PAGE1 only)) 7 6 5 4 3 2 bit symbol - - - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type Functon 7-2 − R Read as 0. 1-0 LEAP R/W 00 : A leap year 01 : one year after a leap year 10 : two years after a leap year 11 : three years after a leap year 2013/5/31 Page 582 1 0 LEAP Undefined Undefined TMPM361F10FG 21.3.3.10 RTCPAGER(PAGE register(PAGE0/1)) 7 6 5 4 3 2 1 0 Bit symbol INTENA - - ADJUST ENATMR ENAALM - PAGE After reset 0 0 0 0 Undefined Undefined 0 0 Bit 7 Bit Symbol INTENA Type R/W Function INTRTC 0:Disable 1:Enable 6-5 − R Read as 0. 4 ADJUST R/W [Write] 0: Don't care 1: Sets ADJUST request Adjusts seconds. The request is sampled when the sec. counter counts up. If the time elapsed is between 0 and 29 seconds, the sec. counter is cleared to "0". If the time elapsed is between 30 and 59 seconds, the min. counter is carried and sec. counter is cleared to "0". [Read] 0: ADJUST no request 1: ADJUST requested If "1" is read, it indicates that ADJUST is being executed. If "0" is read, it indicates that the execution is finished. 3 ENATMR R/W Clock 0: Disable 1: Enable 2 ENAALM R/W ALARM 0: Disable 1: Enable 1 − R Read as 0. 0 PAGE R/W PAGE selection 0:Selects Page0 1:Selects Page1 Note 1: A read-modify-write operation cannot be porfomed. Note 2: To set interrupt enable bits to , and , you must follow the order specified here. Make sure not to set them at the same time (make sure that there is time lag between interrupt enable and clock/ alarm enable).To change the setting of and , must be disabled first. Example: Clock setting/Alarm setting 7 6 5 4 3 2 1 0 RTCPAGER ← 0 0 0 0 1 1 0 0 Enables Clock and alarm RTCPAGER ← 1 0 0 0 1 1 0 0 Enables interrupt Page 583 2013/5/31 21. 21.3 Real Time Clock (RTC) Detailed Description Register 21.3.3.11 TMPM361F10FG RTCRESTR (Reset register (for PAGE0/1)) 7 6 5 4 3 2 1 0 Bit symbol DIS1HZ DIS16HZ RSTTMR RSTALM - - - - After reset 1 1 0 0 0 1 1 1 Bit 7 Bit Symbol DIS1HZ Type R/W Function 1 Hz 0:Enable 1: Disable 6 DIS16HZ R/W 16 Hz 0: Enable 1: Disable 5 RSTTMR R/W [Write] 0: Don't care 1: Sec.counter reset Resets the sec counter. The equest is sampled using low-speed clock. [Read] 0: No reset request 1: RESET requested If "1" is read, it indicates that RESET is being executed. If "0" is read, it indicates that the execution is finished. 4 RSTALM R/W 0:Don't care 1: Alarm reset Initializes alarm registers (Minute column, hour column, day column and day of the week column) as follows. MInute:00, Hour:00, Day:01, Day of the week:Sunday 3 − R Read as 0. 2-0 − R/W Write "1". Note 1: A read-modify-write operation cannot be performed. The setting of and , RTCPAGER used for alarm, 1Hz interrupt and 16Hz interrupt is shown as below. RTCPAGER Interrupt source signal 1 1 Alarm 0 1 0 1 Hz 1 0 0 1 Others 2013/5/31 Page 584 16 Hz Interrupt not generated. TMPM361F10FG 21.4 Operational Description The RTC incorporates a second counter that generates a 1Hz signal from a 32.768 kHz signal. The second counter operation must be taken into account when using the RTC. 21.4.1 Reading clock data 1. Using 1Hz interrupt The 1Hz interrupt is generated being synchronized with counting up of the second counter. Data can be read correctly if reading data after 1Hz interrupt occurred. 2. Using pair reading There is a possibility that the clock data may be read incorrectly if the internal counter operates carry during reading. To ensure correct data reading, read the clock data twice as shown below. A pair of data read successively needs to match. Start RTCPAGER = "0", then select PAGE0 Clock data reading (1st) Clock data reading (2nd) 1st data = 2nd data NO YES End Figure 21-2 Flowchart of the clock data reading 21.4.2 Writing clock data A carry during writing ruins correct data writing. The following procedure ensures the correct data writing. 1. Using 1 Hz interrupt The 1Hz interrupt is generated by being synchronized with counting up of the second counter. If data is written in the time between 1Hz interrupt and subsequent one second count, it completes correctly. 2. Resetting counter Write data after resetting the second counter. The 1Hz-interrupt is generated one second after enabling the interrupt subsequent to counter reset. Page 585 2013/5/31 21. 21.4 Real Time Clock (RTC) Operational Description TMPM361F10FG The time must be set within one second after the interrupt. Strat RTCPAGER = "0" then select PAGE0 RTCRESTR = "1" then reset counter RTCRESTR = "0" then enable 1Hz interrupt First interrupt (After 1s) NO YES Timer setting End Figure 21-3 Flowchart of the clock data writing 3. Disabling the clock Writing "0" to RTCPAGER disables clock operation including a carry. Stop the clock after the 1Hz-interrupt. The second counter keeps counting. Set the clock again and enable the clock within one second before next 1Hz-interrupt Start Disabling clock Writing the clock data Enabling the clock End Figure 21-4 Flowchart of the disabling clock 2013/5/31 Page 586 TMPM361F10FG 21.4.3 Entering the Low Power Consumption Mode To enter SLEEP mode, in which the system clock stops, after changing clock data, adjusting seconds or resetting the clock, be sure to observe one of the following procedures 1. After changing the clock setting registers, setting the RTCPAGER bit or setting the RTCRESTR bit, wait for one second for an interrupt to be generated. 2. After changing the clock setting registers, setting the RTCPAGER bit or setting the RTCRESTR bit, read the corresponding clock register values, or to make sure that the setting you have made is reflected. Page 587 2013/5/31 21. 21.5 Real Time Clock (RTC) Alarm function 21.5 TMPM361F10FG Alarm function By writing "1" to RTCPAGER, the alarm function of the PAGE1 registers is enabled. One of the following three signals is output to the ALARM pin. 1. "Low" pulse (when the alarm register corresponds with the clock) 2. 1Hz cycle "Low" pulse 3. 16Hz cycle "Low" pulse In any cases shown above, the INTRTC outputs one cycle pulse of low-speed clock. It outputs the INTRTC interrupt request simultaneously. The INTRTC interrupt signal is falling edge triggered. Specify the falling edge as the active state in the CG Interrupt Mode Control Register 21.5.1 "Low" pulse (when the alarm register corresponds with the clock) "Low" pulse is output to the ALARM pin when the values of the PAGE0 clock register and the PAGE1 alarm register correspond. The INTRTC interrupt is generated and the alarm is triggered. The alarm settings Initialize the alarm with alarm prohibited. Write "1" to RTCRESTR. It makes the alarm setting to be 00 minute, 00 hour, 01 day and Sunday. Setting alarm for min., hour, date and day is done by writing data to the relevant PAGE1 register. Enable the alarm with the RTCPAGER bit. Enable the interrupt with the RTCPAGER bit. The following is an example program for outputting an alarm from the ALARM pin at noon (12:00) on Monday 5th. 7 6 5 4 3 2 1 0 RTCPAGER ← 0 0 0 0 1 0 0 1 Disables alarm,sets PAGE1 RTCRESTR ← 1 1 0 1 0 0 0 0 Initializes alarm RTCDAYR ← 0 0 0 0 0 0 0 1 Monday RTCDATER ← 0 0 0 0 0 1 0 1 5th day RTCHOURR ← 0 0 0 1 0 0 1 0 Sets 12 o’clock RTCMINR ← 0 0 0 0 0 0 0 0 Sets 00 min RTCPAGER ← 0 0 0 0 1 1 0 0 Enables alarm RTCPAGER ← 1 0 0 0 1 1 0 0 Enables interrupts The above alarm works in synchronization with the low-speed clock. When the CPU is operating at high frequency oscillation, a maximum of one clock delay at fs (about 30μs) may occur for the time register setting to become valid. Note:To make the alarm work repeatedly (e.g. every Wednesday at 12:00), next alarm must be set during the INTRTC interrupt routine that is generated when the time set for the alarm matches the RTC count. 2013/5/31 Page 588 TMPM361F10FG 21.5.2 1Hz cycle "Low" pulse The RTC outputs a "Low" pulse cycle of low-speed 1Hz clock to the ALARM pin by setting RTCPAGER="1" after setting RTCPAGER= "0", RTCRESTR= "0" and = "1". It generates an INTRTC interrupt simultaneously. 21.5.3 16Hz cycle "Low" pulse The RTC outputs a "Low" pulse cycle of low-speed 16Hz clock to the ALARM pin by setting RTCPAGER="1" after setting RTCPAGER= "0", RTCRESTR= "1" and = "0". It generates an INTRTC interrupt simultaneously. Page 589 2013/5/31 21. 21.5 Real Time Clock (RTC) Alarm function 2013/5/31 TMPM361F10FG Page 590 TMPM361F10FG 22. Flash This section describes the hardware configuration and operation of the flash memory. 22.1 Flash Memory 22.1.1 Features 1. Memory capacity TMPM361F10FG contains flash memory. The memory sizes and configurations are shown in the table below. Independent write access to each block is available. When the CPU is to access the internal flash memory, 32-bit data bus width is used. 2. Write / erase time Writing is executed per page. TMPM361F10FG contains 128 words. Page writing requires 1.25ms (typical) regardless of number of words. A block erase requires 0.1 sec. (typical). The following table shows write and erase time per chip. Note: Product Name Memory size TMPM361F10FG 1024 KB Block Configuration 128 KB 64 KB 32 KB Number of words Write time Erase time 7 1 2 128 2.56 sec 1.0 sec The above values are theoretical values not including data transfer time. The write time per chip depends on the write method to be used by users. 3. Programming method There are two types of the onboard programming mode for users to program (rewrite) the device while it is mounted on the user's board: a. User boot mode The use’s original rewriting method can be supported. b. Single boot mode The rewriting method to use serial data transfer (Toshiba's unique method) can be supported. Page 591 2013/5/31 22. 22.1 Flash Flash Memory TMPM361F10FG 4. Rewriting method The flash memory included in this device is generally compliant with the applicable JEDEC standards except for some specific functions. Therefore, if a user is currently using an external flash memory device, it is easy to implement the functions into this device. Furthermore, the user is not required to build his/her own programs to realize complicated write and erase functions because such functions are automatically performed using the circuits already built-in the flash memory chip. JEDEC compliant functions Modified, added, or deleted functions ・ Automatic programming ・ Automatic chip erase Block protect (only software protection is supported) ・ Automatic block erase Erase resume - suspend function ・ Data polling / toggle bit 5. Protect/ Security Function This device is also implemented with a read-protect function to inhibit reading flash memory data from any external writer device. On the other hand, rewrite protection is available only through command-based software programming; any hardware setting method to apply +12VDC is not supported. See the chapter "ROM protection" for details of ROM protection and security function. Note: 2013/5/31 If a password is set to 0xFF (erased data), it is difficult to protect data securely due to an easy-toguess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. Page 592 TMPM361F10FG 22.1.2 Block Diagram of the Flash Memory Section Internal address bus Internal data bus Internal control bus ROM controller Control Address Data Flash memory Command register Address latch Data latch Column decoder / sense amplifer Row decoder Control circuit (includes automatic sequence control) Flash memory cell Erase block decoder Figure 22-1 Block Diagram of the Flash Memory Section Page 593 2013/5/31 22. 22.2 Flash Operation Mode 22.2 TMPM361F10FG Operation Mode This device has three operation modes including the mode not to use the internal flash memory. Table 22-1 Operation modes Operation mode Operation details Single chip mode After reset is cleared, it starts up from the internal flash memory. Normal mode In this operation mode, two different modes, i.e., the mode to execute user application programs and the mode to rewrite the flash memory onboard the user’s set, are defined.The former is referred to as "normal mode" and the latter "user boot mode". User boot mode A user can uniquely configure the system to switch between these two modes. For example, a user can freely design the system such that the normal mode is selected when the port "A0" is set to "1" and the user boot mode is selected when it is set to "0". A user should prepare a routine as part of the application program to make the decision on the selection of the modes. Single boot mode After reset is cleared, it starts up from the internal Boot ROM (Mask ROM). In the Boot ROM, an algorithm to enable flash memory rewriting on the user’s set through the serial port of this device is programmed. By connecting to an external host computer through the serial port, the internal flash memory can be programmed by transferring data in accordance with predefined protocols. Among the flash memory operation modes listed in the above table, the User Boot mode and the Single Boot mode are the programmable modes. These two modes, the User Boot mode and the Single Boot mode, are referred to as "Onboard Programming" modes where onboard rewriting of internal flash memory can be made on the user's set. Either the Single Chip or Single Boot operation mode can be selected by externally setting the level of the BOOT (PI0) pin while the device is in reset status. Table 22-2 Operating Mode Setting Operation mode Pin RESET BOOT (PI0) Single chip mode 0→1 1 Single boot mode 0→1 0 Reset state Single chip mode Single boot mode Normal mode User boot mode Onboard programming mode User to set the switch method Figure 22-2 Mode Transition Diagram 2013/5/31 Page 594 TMPM361F10FG 22.2.1 Reset Operation To reset the device, ensure that the power supply voltage is within the operating voltage range, that the internal oscillator has been stabilized, and that the RESET input is held at "0" for a minimum duration of 12 system clocks (0.19μs with 64MHz operation; the "1/1" clock gear mode is applied after reset). Note 1: It is necessary to apply "0" to the RESET inputs upon power on for a minimum duration of 700 μs regardless of the operating frequency. Note 2: While flash auto programming or erasing is in progress, at least 0.5 μs of reset period is required regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. 22.2.2 User Boot Mode (Single chip mode) User Boot mode is to use flash memory programming routine defined by users. It is used when the data transfer buses for flash memory program code on the old application and for serial I/O are different. It operates at the single chip mode; therefore, a switch from normal mode in which user application is activated at the single chip mode to User Boot Mode for programming flash is required. Specifically, add a mode judgment routine to a reset program in the user application. The condition to switch the modes needs to be set by using the I/O of TMPM361F10FG in conformity with the user’s system setup condition. Also, flash memory programming routine that the user uniquely makes up needs to be set in the new application. This routine is used for programming after being switched to User Boot Mode. The execution of the programming routine must take place while it is stored in the area other than the flash memory since the data in the internal flash memory cannot be read out during delete / writing mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. Be sure not to cause any exceptions including a non-maskable while User Boot Mode. (1-A) and (1-B) are the examples of programming with routines in the internal flash memory and in the external memory. For a detailed description of the erase and program sequence, refer to "22.3 On-board Programming of Flash Memory (Rewrite/Erase)". Page 595 2013/5/31 22. 22.2 Flash Operation Mode 22.2.2.1 TMPM361F10FG (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1) Step-1 Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMPM361F10FG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Programming routine: Code to download new program code from a host controller and re-program the flash memory (c) Copy routine: Code to copy the data described in (b) from the TMPM361F10FG flash memory to either the TMPM361F10FG on-chip RAM or external memory device. (Host) New Application Program Code (TMPM361F10FG) (I/O) Flash memory Old Application Program Code [Reset Procedure] (a) Mode Judgement Routine (b) Programming Routine RAM (c) Copy Routine 2013/5/31 Page 596 TMPM361F10FG (2) Step-2 The following description is the case that programming routines are installed in the reset processing program. After RESET pin is released, the reset procedure determines whether to put the TMPM361F10FG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be not used while in User Boot mode.) (Host) (TMPM361F10FG) New Application Program Code (I/O) 0 → 1 RESET Flash memory Old Application Program Code Conditions for entering User Boot mode (defined by the user) [Reset Procedure] (a) Mode Judgement Routine (b) Programmming Routine RAM (c) Copy Routine (3) Step-3 Once transition to User Boot mode is occurred, execute the copy routine (c) to copy the flash programming routine (b) to the TMPM361F10FG on-chip RAM. (Host) (TMPM361F10FG) New Application Program Code (I/O) Flash memory Old Application Program Code [Reset Procedure] (b) Programming Routine (a) Mode Judgement Routine (b) Programming Routine (c) Copy Routine RAM Page 597 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG (4) Step-4 Jump program execution to the flash programming routine in the on-chip RAM to clear write or erase protection and erase a flash block containing the old application program code. (Host) (TMPM361F10FG) New Application Program Code (I/O) Flash memory (Erased) [Reset Procedure] (b) Programming Routine (a) Mode Judgement Routine (b) Programming Routine (c) Copy Routine (5) RAM Step-5 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user’s program area must be set. (Host) (TMPM361F10FG) (I/O) Flash memory New Application Program Code [Reset Procedure] (b) Programming Routine (a) Mode Judgement Routine (b) Programming Routine (c) Copy Routine 2013/5/31 RAM Page 598 New Application Program Code TMPM361F10FG (6) Step-6 Set RESET to "0" to reset the TMPM361F10FG. Upon reset, the on-chip flash memory is set to Normal mode. After RESET is released, the CPU will start executing the new application program code. (Host) (TMPM361F10FG) (I/O) 0 → 1 RESET Flash memory New Application Program Code Set to Normal mode [Reset Procedure] (a) Mode Judgement Routine (b) Programming Routine (c) Copy Routine RAM Page 599 2013/5/31 22. 22.2 Flash Operation Mode 22.2.2.2 TMPM361F10FG (1-B) Method 2: Transferring a Programming Routine from an External Host (1) Step-1 Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMPM361F10FG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Transfer routine: Code to download new program code from a host controller Also, prepare a programming routine shown below on the host controller: (c) Programming routine: Code to download new program code from an external host controller and re-program the flash memory (+RVW) New Application Program Code (c) Programming Routine (TMPM361F10FG) (I/O) Flash memory Old Application Program Code [Reset Procedure] (a) Mode Judgement Routine RAM (b) Transfer Routine 2013/5/31 Page 600 TMPM361F10FG (2) Step-2 The following description is the case that programming routines are installed in the reset processing program. After RESET is released, the reset procedure determines whether to put the TMPM361F10FG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be not used while in User Boot mode). New Application Program Code (Host) (c)Programming Routine (TMPM361F10FG) (I/O) 0 → 1 RESET Flash memory Old Application Program Code Conditions for entering User Boot mode (defined by the user) [Reset Procedure] (a) Mode Judgement Routine (b) Transfer Routine (3) RAM Step-3 Once User Boot mode is entered, execute the transfer routine (b) to download the flash programming routine (c) from the host controller to the TMPM361F10FG on-chip RAM. (+RVW) New Application Program Code (c) Programming Routine (TMPM361F10FG) (I/O) Flash memory Old Application Program Code (c) Programming Routine [Reset Procedure] (a) Mode Judgement Routine RAM (b) Transfer Routine Page 601 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG (4) Step-4 Jump program execution to the flash programming routine in the on-chip RAM to clear write or erase protection and erase a flash block containing the old application program code. (Host) New Application Program Code (c) Programming Routine (TMPM361F10FG) (I/O) Flash memory (Erased) (c) Programming Routine [Reset Procedure] (a) Mode Judgement Routine RAM (b) Transfer Routine (5) Step-5 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user program area must be set. (Host) New Application Program Code (c) Programming Routine (TMPM361F10FG) (I/O) Flash memory New Application Program Code (c) Programming Routine [Reset Procedure] (a) Mode Judgement Routine RAM (b) Transfer Routine 2013/5/31 Page 602 TMPM361F10FG (6) Step-6 Set RESET to "0" low to reset the TMPM361F10FG. Upon reset, the on-chip flash memory is set to Normal mode. After RESET is released, the CPU will start executing the new application program code. (Host) (TMPM361F10FG) (I/O) 0 → 1 RESET Flash memory New Application Program Code Set to NORMAL mode [Reset Procedure] (a) Mode Judgement Routine (b) Transfer Routine RAM Page 603 2013/5/31 22. 22.2 Flash Operation Mode 22.2.3 TMPM361F10FG Single Boot Mode In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMPM361F10FG on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it. Single Boot mode allows for serial programming of the flash memory. Channel 4 of the SIO (SIO4) of the TMPM361F10FG is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMPM361F10FG on-chip RAM. Then, the flash memory is re-programmed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO4 and the host must follow the protocol described later. To secure the contents of the flash memory, the validity of the application’s password is verified before a programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the non-maskable interrupt (NMI) must be disabled in Single Boot mode while the flash memory is being erased or programmed. In Single Boot mode, the boot-ROM programs 33are executed in Normal mode. Once re-programming is complete, it is recommended to set the write/erase protection to the relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. 22.2.3.1 (2-A) Using the Program in the On-Chip Boot ROM (1) Step-1 The flash block containing the old version of the program code does not need to be erased before executing the programming routine. Since a programming routine and programming data are transferred via the SIO (SIO4), the SIO4 must be connected to a host controller. Prepare a programming routine (a) on the host controller. (Host) New Application Program Code (a)Programming Routine (TMPM361F10FG) Boot ROM (I/O) SIO4 Flash memory Old Application Program Code (or erased state) RAM 2013/5/31 Page 604 TMPM361F10FG (2) Step-2 Set the RESET pin to "1" to cancel the reset of the TMPM361F10FG when the BOOT pin has already been set to "0". After reset, CPU reboots from the on-chip boot ROM. The 12-byte password transferred from the host controller via SIO4 is firstly compared to the contents of the special flash memory locations. (If the flash block has already been erased, the password is 0xFF). (Host) New Application Proram Code (a) Programming Routine (TMPM361F10FG) Boot ROM (I/O) 0 → 1 RESET SIO4 Flash memory 0 BOOT Old Application Program Code (or erased state) RAM (3) Step-3 If the password is correct, the boot program downloads the programming routine (a) from the host controller into the on-chip RAM of the TMPM361F10FG. The programming routine must be stored in the range from 0x2000_0400 to the end address of RAM. (Host) New Application Program Code (a) Programming Routine (TMPM361F10FG) Boot ROM (I/O) SIO4 Flash memory Old Application Program Code (or erased state) (a) Programming Routine RAM Page 605 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG (4) Step-4 The CPU jumps to the programming routine (a) in the on-chip RAM to erase the flash block containing the old application program code. The Block Erase or Chip Erase command may be used. (Host) New Application Program Code (a) Programming Routine (TMPM361F10FG) Boot ROM (I/O) SIO4 Flash memory (a)Programming Routine Erased RAM (5) Step-5 Next, the programming routine (a) downloads new application program code from the host controller and programs it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user’s program area must be set. In the example below, new program code comes from the same host controller via the same SIO4 channel as for the programming routine. However, once the programming routine has begun to execute in the on-chip RAM, it is free to change the transfer path and the source of the transfer. Create board hardware and a programming routine to suit your particular needs. (Host) New Application Program Code (a) Programming Routine (TMPM361F10FG) Boot ROM (I/O) SIO4 Flash memory New Application Program Code (a) Programming Routine RAM 2013/5/31 Page 606 TMPM361F10FG (6) Step-6 When programming of the flash memory is complete, power off the board and disconnect the cable between the host and the target board. Turn on the power again so that the TMPM361F10FG reboots in Single-Chip (Normal) mode to execute the new program. (Host) (TMPM361F10FG) (I/O) Boot ROM 0 → 1 RESET SIO4 flash memory Set to Single-Chip mode (BOOT=1) New Application Program Code RAM 22.2.4 Configuration for Single Boot Mode To execute the on-board programming, boot the TMPM361F10FG with Single Boot mode following the configuration shown below. BOOT(PI0) = 0 RESET = 0 → 1 Set the RESET input to "0", and set the each BOOT (PI0) pins to values shown above, and then release RESET pin (high). 22.2.5 Memory Map Figure 22-3 shows a comparison of the memory maps in Normal and Single Boot modes. In Single Boot mode, the internal flash memory is mapped to 0x3F80_0000 and later addresses, and the Internal boot ROM (Mask ROM) is mapped to 0x0000_0000 through 0x0000_0FFF. The internal flash memory and RAM addresses of each device are shown below. Product Name Flash Size RAM Size TMPM361F10FG 1024 KB 64 KB Flash Address (Single Chip / Single Boot Mode) 0x0000_0000 to 0x000F_FFFF 0x3F80_0000 to 0x3F8F_FFFF Page 607 RAM Address 0x2000_0000 to 0x2000_FFFF 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG Single Boot Mode Single Chip Mode 0xFFFF_FFFF 0xFFFF_FFFF Internal I/O 0x4000_7FFF Internal I/O 0x4000_0000 0x4000_7FFF 0x4000_0000 Internal Flash ROM (1024 KB) Reserved 0x3F8F_FFFF 0x3F80_0000 0x3F7F_FFFF 0x3F7F_F000 Internal RAM (64 KB) 0x2000_FFFF Internal Flash ROM (1024 KB) 0x000F_FFFF Internal RAM (64 KB) 0x2000_0000 0x2000_0000 Internal BOOT ROM 0x0000_0FFF (4 KB) 0x0000_0000 0x0000_0000 Figure 22-3 Memory Maps for TMPM361F10FG 2013/5/31 0x2000_FFFF Page 608 TMPM361F10FG 22.2.6 Interface specification In Single Boot mode, an SIO channel is used for communications with a programming controller. The same configuration is applied to a communication format on a programming controller to execute the onboard programming. Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. The communication formats are shown below. ・ UART communication Communication channel : SIO channel 4 Serial transfer mode : UART (asynchronous), half -duplex, LSB first Data length : 8 bits Parity bit : None STOP bit : 1 bit Baud rate : Arbitrary baud rate ・ I/O Interface mode Communication channel : SIO channel 4 Serial transfer mode : I/O interface mode, full -duplex, LSB first Synchronization clock (SCLK4) : Input mode Handshaking signal : PN3 configured as an output mode Baud rate : Arbitrary baud rate Table 22-3 Required Pin Connections Interface Pin UART I/O Interface Mode RVDD3 ο ο AVDD3 ο ο DVDD3B ο ο DVDD3A ο ο AVSS ο ο DVSS ο ο Mode-setting pin BOOT (PI0) ο ο Reset pin RESET ο ο TXD4 (PN0) ο ο Power supply pins Communication pin RXD4 (PN1) ο ο SCLK4 (PN2) × ο (Input mode) PN3 × ο (Output mode) Page 609 2013/5/31 22. 22.2 Flash Operation Mode 22.2.7 TMPM361F10FG Data Transfer Format Table 22-4, Table 22-6 to Table 22-9 illustrate the operation commands and data transfer formats at each operation mode. In conjunction with this section, refer to "22.2.10 Operation of Boot Program". Table 22-4 Single Boot Mode Commands 22.2.8 Code Command 0x10 RAM transfer 0x20 Show Flash Memory SUM 0x30 Show Product Information 0x40 Chip and protection bit erase Restrictions on internal memories Single Boot Mode places restrictions on the internal RAM and ROM as shown in Table 22-5. Table 22-5 Restrictions in Single Boot Mode Memory Internal RAM Details A program contained in the BOOT ROM uses the area, through 0x2000_0000 to 0x2000_03FF, as a work area. Store the RAM transfer program from 0x2000_0400 through the end address of RAM. The following addresses are assigned for storing software ID information and passwords. Internal ROM Storing program in these addresses is not recommendable. 0x3F8F_FFF0 to 0x3F8F_FFFF 22.2.9 Transfer Format for Boot Program The following tables shows the transfer format for each Boot program command. Use this section in conjunction with Chapter "22.2.10 Operation of Boot Program". 2013/5/31 Page 610 TMPM361F10FG 22.2.9.1 RAM Transfer Table 22-6 Transfer Format for the RAM Transfer Command Data Transferred from the Controller to the TMPM361F10FG Byte Boot ROM 1 byte Serial operation mode and baud rate For UART mode : 0x86 Baud rate Desired baud rate (Note 1) Data Transferred from the TMPM361F10FG to the Controller − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode - Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode - Normal acknowledge :0x30 3 byte Command code (0x10) − 4 byte − ACK for the command code byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 5 byte Password sequence (12 bytes)) to 0x3F8F_FFF4 to 0x3F8F_FFFF − 16 byte 17 byte Check SUM value for bytes 5 to 16 − 18 byte − ACK for the checksum byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 19 byte RAM storage start address 31 to 24 − 20 byte RAM storage start address 23 to 16 − 21 byte RAM storage start address 15 to 8 − 22 byte RAM storage start address 7 to 0 − 23 byte RAM storage start address 15 to 8 − 24 byte RAM storage start address 7 to 0 − 25 byte Check SUM value for bytes 19 to 24 − 26 byte − ACK for the checksum byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 27 byte RAM storage data − m+ 1 byte Checksum value for bytes 27 to m − m+ 2 byte − ACK for the checksum byte (Note 2) to mbyte - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 RAM m+ 3 byte − Jump to RAM storage start address Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Note 3: The 19th to 25th bytes must be within the RAM address range from 0x2000_0400 through the end address of RAM. Page 611 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG 22.2.9.2 Show Flash Memory SUM Table 22-7 Transfer Format for the Show Flash Memory SUM Command Data Transferred from the Controller to the TMPM361F10FG Byte Boot ROM 1 byte Serial operation mode and baud rate For UART mode : 0x86 Baud rate Desired baud rate (Note 1) Data Transferred from the TMPM361F10FG to the Controller − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode - Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode - Normal acknowledge :0x30 3 byte Command code (0x20) − 4 byte − ACK for the command code byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 5 byte − SUM (upper byte) 6 byte − SUM (lower byte) 7 byte − Checksum value for byte 5 and 6 8 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. 2013/5/31 Page 612 TMPM361F10FG 22.2.9.3 Transfer Format for the Show Product Information Table 22-8 Transfer Format for the Show Product Information Command Data Transferred from the Controller to the TMPM361F10FG Byte Boot ROM 1 byte Serial operation mode and baud rate Desired baud rate (Note 1) For UART mode : 0x86 For I/O Interface mode : 0x30 2 byte Baud rate − Data Transferred from the TMPM361F10FG to the Controller − ACK for the serial operation mode byte ・For UART mode - Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode - Normal acknowledge :0x30 3 byte Command code (0x30) − 4 byte − ACK for the command code byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 5 byte − Flash memory data at address 0x3F8F_FFF0 6 byte − 7 byte − Flash memory data at address 0x3F8F_FFF1 Flash memory data at address 0x3F8F_FFF2î‘ín 8 byte − Flash memory data at address 0x3F8F_FFF3 9 byte − Product name (12-byte ACCII code) to From 9th byte : 20 byte 'TMPM360F1_ _' 21 byte − Password comparison start address (4 bytes) to From 21st byte : 24 byte 0xF4, 0xFF, 0x8F, 0x3F 25 byte − RAM start address (4 bytes) to From 25th byte : 28 byte 0x00, 0x00, 0x00, 0x20 29 byte − Dummy data (4 bytes) to From 29th byte : 32 byte 0x00, 0x00, 0x00, 0x00 33 byte − RAM end address (4bytes) to From 33th byte : 36 byte 0xFF, 0xFF, 0x00, 0x20 37 byte − Dummy date (4bytes) to From 37th byte : 40 byte 0x00, 0x00, 0x00, 0x00 41 byte − Dummy date (4bytes) to From 41st byte 44 byte 0x00, 0x00, 0x00, 0x00 Page 613 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG Table 22-8 Transfer Format for the Show Product Information Command Data Transferred from the Controller to the TMPM361F10FG Byte 45 byte − Baud rate Data Transferred from the TMPM361F10FG to the Controller Dummy data (2 bytes) to From 45th byte : 46 byte 0x00, 0x00 47 byte − Flash memory start address (4 bytes) to From 47th byte : 50 byte 0x00, 0x00, 0x80, 0x3F 51 byte − Flash memory end address (4 bytes) to From 51st byte : 54 byte 0xFF, 0xFF, 0x8F, 0x3F 55 byte − Flash memory block count (2 bytes) to From 55th byte : 56 byte 0x0A, 0x00 57 byte to − Start address of a group of the same-size (16K) flash blocks (4 bytes) 60 byte From 57th byte : 0x00, 0x00, 0x00, 0x00 TMPM361F10FG does not have 16KB block. 61 byte to − Size (in halfwords) of the same-size (16K) flash blocks (4 bytes) 64 byte From 61st byte : 0x00, 0x00, 0x00, 0x00 TMPM361F10FG does not have 16KB block. 65 byte − Number of flash blocks of the same size (16K) (1 byte) 0x00 TMPM361F10FG does not have 16KB block. 66 byte to − Start address of a group of the same-size (32K) flash blocks (4 bytes) 69 byte From 66th byte : 0x00, 0x00, 0x8F, 0x3F 70 byte − to Size (in halfwords) of the same-size (32K) flash blocks (4 bytes) 73 byte From 70th byte : 0x00, 0x40, 0x00, 0x00 74 byte − Number of flash blocks of the same size (32K) (1 byte) 0x02 75 byte to − Start address of a group of the same-size (32K) flash blocks (4 bytes) 78 byte From 75th byte : 0x00, 0x00, 0x81, 0x3F 79 byte − to Size (in halfwords) of the same-size (32K) flash blocks (4 bytes) 82 byte From 79th byte : 0x00, 0x80, 0x00, 0x00 2013/5/31 Page 614 TMPM361F10FG Table 22-8 Transfer Format for the Show Product Information Command Data Transferred from the Controller to the TMPM361F10FG Byte 83 byte − Baud rate Data Transferred from the TMPM361F10FG to the Controller Number of flash blocks of the same size (64K) (1 byte) 0x01 84 byte to − Start address of a group of the same-size (128K) flash blocks (4 bytes) 87 byte From 84th byte : 0x00, 0x00, 0x82, 0x3F 88 byte − Size (in halfwords) of the same-size (128K) flash to blocks (4 bytes) 91 byte From 88th byte : 0x00, 0x00, 0x01, 0x00 92 byte − Number of flash blocks of the same size (128K) (1 byte) 0x07 93 byte − Checksum value for bytes from 5 to 92 94 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second byte must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Page 615 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG 22.2.9.4 Chip Erase and Protect Bit Erase Table 22-9 Transfer Format for the Chip and Protection Bit Erase Command Data Transferred from the Controller to the TMPM361F10FG Byte Boot ROM 1 byte Serial operation mode and baud rate For UART mode : 0x86 Baud rate Desired baud rate (Note 1) Data Transferred from the TMPM361F10FG to the Controller − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode - Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode - Normal acknowledge :0x30 3 byte Command code (0x40) − 4 byte − ACK for the command code byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 5 byte Chip erase command code (0x54) − 6 byte − ACK for the command code byte (Note 2) - Normal acknowledge : 0x10 - Negative acknowledge : 0xX1 - Communication error : 0xX8 7 byte − ACK for the chip erase command code byte - Normal acknowledge : 0x4F - Negative acknowledge : 0x4C 8 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second byte must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. 2013/5/31 Page 616 TMPM361F10FG 22.2.10 Operation of Boot Program When Single Boot mode is selected, the boot program is automatically executed on startup. The boot program offers these four commands, of which the details are provided on the following subsections. 1. RAM Transfer command The RAM Transfer command stores program code transferred from the host controller to the onchip RAM and executes the program once the transfer is successfully completed. The user program RAM space can be assigned to the range from 0x2000_0400 to the end address of RAM, whereas the boot program area (0x2000_0000 to 0x2000_03FF) is unavailable. The user program starts at the assigned RAM address. The RAM Transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. The programming routine must utilize the flash memory command sequences described in Section 22.3. Before initiating a transfer, the RAM Transfer command verifies a password sequence coming from the controller against that stored in the flash memory. Note: If a password is set to 0xFF (erased data), it is difficult to protect data securely due to an easy-toguess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. 2. Show Flash Memory SUM command The Show Flash Memory SUM command adds the entire contents of the flash memory together. The boot program does not provide a command to read out the contents of the flash memory. Instead, the Flash Memory SUM command can be used for software revision management. 3. Show Product Information command The Show Product Information command provides the product name, on-chip memory configuration and the like. This command also reads out the contents of the flash memory locations at addresses shown below. In addition to the Show Flash Memory Sum command, these locations can be used for software revision management. Product name Area TMPM361F10FG 0x3F8F_FFF0 to 0x3F8F_FFF3 4. Flash Memory Chip Erase and Protection Bit Erase command This command erases the entire area of the flash memory automatically. All the blocks in the memory cell and their protection conditions are erased even when any of the blocks are prohibited from writing and erasing. When the command is completed, the FCSECBIT bit is set to "1". This command serves to recover boot programming operation when a user forgets the password. Therefore password verification is not executed. Page 617 2013/5/31 22. 22.2 Flash Operation Mode 22.2.10.1 TMPM361F10FG RAM Transfer Command See Table 22-6 for the transfer format of this command. 1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed description of how the serial operation mode is determined, see "22.2.10.6 Determination of a Serial Operation Mode" described later. If the mode is determined as UART mode, the boot program checks if the baud rate setting can be performed. During the first-byte processing, receiving operation is prohibited. (SC4MOD0=0) ・ To communicate in UART mode The 1st byte is set to "0x86" and is transmitted from the controller to the target board at the specified baud rate by setting UART. If the serial operation mode is determined as UART, then the boot program checks if the baud rate setting can be performed. If that baud rate cannot be set, the boot program aborts and any subsequent communications cannot be done. Please refer to "Baud rate setting" for the method of judging whether the setting of the baud rate is possible. ・ To communicate in I/O Interface mode The 1st byte is set to "0x30" and is transmitted from the controller to the target board at 1/16 of the desired baud rate by the synchronous setting. Same as the 1st byte, a 1/16 of the specified baud rate is used in the 2nd transmission. From the 3rd byte (operation command data), users can transmit data at specified baud rate. In I/O interface mode, CPU considers the reception terminal to be an input port and monitors the level of I/O port. If the baud rate is high or operation frequency is high, CPU may not distinguish the level of I/O port. To avoid this situation, the baud rate is set at the 1/16 of desired baud rate in the I/O interface. When the serial operation mode is determined as I/O Interface mode, SCLK Input mode is set. The controller must ensure that its AC timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the boot program does not check the receive error flag; thus there is no error acknowledge responce (bit 3, 0x08). 2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte where the serial operation mode is set. When 1st byte is determined as UART and can be set at the specified baud rate, data "0x86" is transmitted. When 1st byte is determined as I/O interface, data "0x30" is transmitted. ・ UART mode The 2nd byte is used for distinguishing whether the baud rate can be set. If the baud rate can be set, a value of SC4BRCE is renewed and data "0x86" is sent to the controller. If the baud rate cannot be set, transmit operation is stopped and no data is transmitted. After transmission of 1st byte completed, the controller allows for five seconds of time-out. If it does not receive 0x86 within the allowed time-out period, the controller should give up the communication. Receiving operation is permitted by setting SC4MOD0=1, before loading 0x86 to the SIO transmit buffer. ・ I/O Interface mode The boot program sets a value of the SC4MOD0 and SC4CR registers to configure the the I/O Interface mode and writes 0x30 to the SC4BUF. Then, the SIO4 waits for the SCLK4 signal to come from the controller. After the transmission of the 1st byte completed, the controller should send the SCLK clock to the target board after a certain idle time (several microseconds). This must be done at 1/16 of the desired baud rate. If the 2nd byte, which is from the target board to the controller, is 0x30, then the controller regards it as communication possible. From the 3rd byte, users can transmit data at specified baud rate. Receiving operation is permitted by setting SC4MOD0=1, before loading 0x86 to the SIO. 2013/5/31 Page 618 TMPM361F10FG 3. The 3rd byte transmitted from the controller to the target board is a command. The code for the RAM Transfer command is 0x10. 4. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there is a receive error, the boot program transmits 0xX8 (bit 3) and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 22-4, the boot program echoes it back to the controller. When the RAM Transfer command is received, the boot program echoes back a value of 0x10 and then branches to the RAM Transfer routine. Once this branch is taken, password verification is done. Password verification is detailed in the later Section "Password". If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte password. Each byte is compared to the contents of following addresses in the flash memory. The verification is started with the 5th byte. If the password verification fails, the RAM Transfer routine sets the password error flag. Product name Area TMPM361F10FG 0x3F8F_FFF4 to 0x3F8F_FFFF 6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the checksum value for the 12-byte password, add the 12 bytes together, ignore the carries and caluculate the 8-bit two's complement by using lower 8 bits then transmit this checksum value from the controller. The checksum calculation is described in details in the later Section "Checksum Calculation". 7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th byte. If there is a receive error, the boot program sends back 0x18 (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO4 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure 17th byte data integrity. Adding the series of the 5th to 16th bytes must result in 0x00 (with the carry dropped). In case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. Finally, the password verification result is checked. If the following case is generated, the boot program transmits an acknowledge response (bit 0, 0x11) as a password error and waits for next operation command (3rd byte). ・ Irrespective of the result of the password comparison, all the 12 bytes of a password in the flash memory are the same value other than 0xFF. ・ Not the entire password bytes transmitted from the controller matched those contained in the flash memory. When all the above verification has been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. Page 619 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG 8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the start address of the RAM region where subsequent data (e.g., a flash programming routine) should be stored. The 19th byte corresponds to bits 31 to 24 of the address and the 22nd byte corresponds to bits 7 to 0 of the address. The start address of the stored RAM must be even address. 9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate the number of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte corresponds to bits 15 to 8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7 to 0 of the number of bytes. 10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add all these bytes together, ignore the carries and caluculate the 8-bit two's complement by using lower 8 bits then transmit this checksum value from the controller. The checksum calculation is described in detail in the later Section "22.2.10.9 Checksum Calculation". 11. The 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there is a receive error, the RAM Transfer routine sends back 0x18 and returns to the command wait state (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO4 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 19th to 24th bytes must result in 0x00 (with the carry dropped). In case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ・ The 19th to 25th bytes data must be within the range of 0x2000_0400 to the end address of RAM. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMPM361F10FG. Storage begins at the address specified by the 19th to 22nd bytes and continues for the number of bytes specified by the 23rd to 24th bytes. 13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes together, ignore the carries and calculate the 8-bit two’s complement by using lower 8 bits then transmit this checksum value from the controller. The checksum calculation is described in detail in later Section "22.2.10.9 Checksum Calculation". 14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes. First, the RAM Transfer routine checks for a receive error in the 27th to (m+1) th bytes. If there is a receive error, the RAM Transfer routine sends back 0x18 (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO4 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the carry dropped). In case of a checksum error, the RAM Transfer routine sends back 0x11 (bit 0) to the controller and returns to the command wait state (i.e., the 3rd byte) again. When the above checks have been completed successfully, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 2013/5/31 Page 620 TMPM361F10FG 15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes. 22.2.10.2 Show Flash Memory SUM Command See Table 22-7 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. 2. The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Flash Memory Sum command is 0x20. 3. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there is a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined- they hold the same values as the upper four bits of the previously issued command. When the SIO4 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 22-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command is received, the boot program echoes back a value of 0x20 and then branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the command wait state (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. The Show Flash Memory Sum routine adds all the bytes of the flash memory together. The 5th and 6th bytes, transmitted from the target board to the controller, indicate the upper and lower bytes of this total sum, respectively. For details on sum calculation, see Section "22.2.10.8 Calculation of the Show Flash Memory Sum Command". 5. The 7th byte is a checksum value for the 5th and 6th bytes. To calculate the checksum value, add the 5th and 6th bytes together, ignore the carry and calculate the 8-bit two’s complement by using lower 8 bits then transmit this checksum value from the controller. 6. The 8th byte is the next command code. 22.2.10.3 Show Product Information Command See Table 22-8 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. 2. The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 0x30. 3. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there is a receive error, the boot program transmits 0xX8 (bit 3) and returns to Page 621 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG the command wait state again. In this case, the upper four bits of the acknowledge response are undefined- they hold the same values as the upper four bits of the previously issued command. When the SIO4 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 22-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command is received, the boot program echoes back a value of 0x30 and then branches to the Show Flash Memory Sum routine. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. The 5th to 8th bytes, transmitted from the target board to the controller, are the data read from addresses shown below in the flash memory. Software version management is possible by storing a software ID in these locations. Product name Area TMPM361F10FG 0x3F8F_FFF0 to 0x3F8F_FFF3 5. The 9th to 20th bytes, transmitted from the target board to the controller, indicate the product name as shown below (where [ ] is a space) in ASCII code. Product name Core TMPM361F10FG T, M, P, M, 3, 6, 0, F, 1, _, [ ], _ 6. The 21st to 24th bytes, transmitted from the target board to the controller, indicate the start address of the flash memory area contained the password. Each product has own start address shown below. Starting from the 21st byte, the following values are transmitted. Product name Address TMPM361F10FG 0xF4, 0xFF,0x8F, 0x3F 7. The 25th to 28th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip RAM. TMPM361F10FG has own start address shown below. Starting from the 25th byte, the following values are transmitted. Product name Address TMPM361F10FG 0x00, 0x00,0x00, 0x20 8. The 29th to 32nd bytes, transmitted from the target board to the controller, are dummy data. Starting from the 29th byte, 0x00, 0x00, 0x00, 0x00 are transmitted. 9. The 33rd to 36th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip RAM. TMPM361F10FG has own end address shown below. Starting from the 33th byte, the following values are transmitted. 2013/5/31 Product name Address TMPM361F10FG 0xFF, 0xFF, 0x00, 0x20 Page 622 TMPM361F10FG 10. The 37th to 40th bytes, transmitted from the target board to the controller, are 0x00, 0x00, 0x00 and 0x00. The 41st to 44th bytes, transmitted from the target board to the controller, are 0x00, 0x00, 0x00 and 0x00. 11. The 45th and 46th bytes transmitted are 0x00, 0x00. 12. The 47th to 50th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip flash memory, are 0x00, 0x00, 0x80, and 0x3F. Product name Address TMPM361F10FG 0x00, 0x00,0x80, 0x3F 13. The 51st to 54th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip flash memory. Each product has own end address shown below.Starting from the 51th byte, the following values are transmitted. Product name Address TMPM361F10FG 0xFF, 0xFF, 0x8F, 0x3F 14. The 55th to 56th bytes, transmitted from the target board to the controller, indicate the number of flash blocks available. Each product transmits own number shown below. Starting from the 55th byte, the following values are transmitted. Product Number of flash blocks TMPM361F10FG 0x0A, 0x00 15. The 57th to 92nd bytes, transmitted from the target board to the controller, contain information about the flash blocks. Flash blocks of the same size are treated as a group. Information about the flash blocks indicate the start address of a group, the size of the blocks in that group (in halfwords) and the number of the blocks in that group. The 57th to 65th bytes are the information about the 16-kbyte blocks. The 66th to 74th bytes are the information about the 32kbyte blocks. The 75th to 83rd bytes are the information about the 64-kbyte blocks. The 84th to 92nd bytes are the information about the 128-kbyte blocks. See Table 22-8 for the values of bytes transmitted. 16. The 93rd byte, transmitted from the target board to the controller, is a checksum value for the 5th to 92nd bytes. To calculate the checksum value, add all these bytes together, ignore the carries and calculate the 8-bit two’s complement by using lower 8 bits. 17. The 94th byte is the next command code. Page 623 2013/5/31 22. 22.2 Flash Operation Mode 22.2.10.4 TMPM361F10FG Chip and Protection Bit Erase Command See Table 22-9 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. 2. From the Controller to the TMPM361F10FG The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 0x40. 3. From TMPM361F10FG to the Controller The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. If the 3rd byte is equal to any of the command codes listed in Table 22-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 0x40. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. From the controller to the TMPM361F10FG The 5th byte, transmitted from the target board to the controller, is the Chip Erase Enable command code (0x54). 5. From TMPM361F10FG to the Controller The 6th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. If the 5th byte is equal to any of the command codes to enable erasing, the boot program echoes it back to the controller. When the Chip and Protection Erase command was received, the boot program echoes back a value of 0x54 and then branches to the Chip Erase routine. If the 5th byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 6. From TMPM361F10FG to the Controller The 7th byte indicates whether the Chip Erase command is normally completed or not. At normal completion, completion code (0x4F) is sent. When an error was detected, error code (0x4C) is sent. 2013/5/31 Page 624 TMPM361F10FG 7. The 9th byte is the next command code. Page 625 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG 22.2.10.5 Acknowledge Responses The boot program represents processing states with specific codes. Table 22-10 to show the values of possible acknowledge responses to the received data. The upper four bits of the acknowledge response are equal to those of the command being executed. The 3rd bit indicates a receive error. The 0th bit indicates an invalid command error, a checksum error or a password error. The 1st bit and 2nd bit are always "0". Receive error checking is not done in I/O Interface mode. Table 22-10 ACK Response to the Serial Operation Mode Byte Return Value Meaning 0x86 The SIO can be configured to operate in UART mode. (See Note) 0x30 The SIO can be configured to operate in I/O Interface mode. Note:In the UART mode, if the baud rate setting cannot be set, the communication is stopped without any response. Table 22-11 ACK Response to the Command Byte Return Value 0x?8 (See note) 0x?1 (See note) Meaning A receive error occurred while receiving a command code. An undefined command code was received. (Reception was completed normally.) 0x10 The RAM Transfer command was received. 0x20 The Show Flash Memory Sum command was received. 0x30 The Show Product Information command was received. 0x40 The Chip Erase command was received. Note:The upper four bits of the ACK response are the same as those of the previous command code. Table 22-12 ACK Response to the Checksum Byte Return Value 0xN8 (See note) 0xN1 (See note) 0xN0 (See note) Meaning A receive error occurred. A checksum or password error occurred. The checksum was correct. Note:The upper four bits of the ACK response are the same as those of the operation command code. For example, it is 1 (N ; RAM transfer command data [7:4] ) when password error occurs. Table 22-13 ACK Response to Chip and Protection Bit Erase Byte Return Value 2013/5/31 Meaning 0x54 The Chip Erase enabling command was received. 0x4F The Chip Erase command was completed. 0x4C The Chip Erase command was abnormally completed. Page 626 TMPM361F10FG 22.2.10.6 Determination of a Serial Operation Mode The first byte from the controller determines the serial operation mode. To use UART mode for communications between the controller and the target board, the controller must firstly send a value of 0x86 at a desired baud rate to the target board. To use I/O Interface mode, the controller must send a value of 0x30 at 1/16 of the desired baud rate. Figure 22-4 shows the waveforms for the first byte in each mode. Start Point A bit 0 bit 1 Point B bit 2 bit 3 Point C bit 4 bit 5 bit 6 bit 7 Point D Stop UART (0x86) tAB bit 0 Point A bit 1 tCD bit 2 bit 3 bit 4 Point B bit 5 bit 6 Point C bit 7 Point D I/O Interface (0x30) tAB tCD Figure 22-4 Serial Operation Mode Byte After RESET is released, the boot program monitors the first serial byte from the controller, with the SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Figure 22-5 shows a flowchart describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot program captures timer counts when each time the logic transition occurs in the first serial byte. Consequently, the calculated tAB, tAC and tAD intervals tend to have slight errors. If the transfer goes at a high baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive pin. In particular, I/O Interface mode may have this problem since its baud rate is generally much higher than that for UART mode. To avoid such a situation, the controller should send the first serial byte at 1/16 of the desired baud rate. The flowchart in Figure 22-5 shows how the boot program distinguishes between UART and I/O Interface modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is determined as UART mode. If the length of tAB is greater than the length of tCD, the serial operation mode is determined as I/O Interface mode. Note that if the baud rate is too high or the timer operating frequency is too low, each timer value becomes small. It causes an unintentional behavior of the controller. To prevent this problem, reset UART mode within the programming routine. For example, the serial operation mode may be determined to be I/O Interface mode when the intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should allow for a time-out period within which it expects to receive an echo-back (0x86) from the target board. The controller should give up the communication if it fails to get that echo-back within the allowed time. When I/O Interface mode is utilized, once the first serial byte has been transmitted, the controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowledge response is not 0x30, the controller should give up further communications. When the intended mode is I/O interface mode, the first byte does not have to be 0x30 as long as tAB is greater than tCD as shown above. 0x91, 0xA1 or 0xB1 can be sent as the first byte code to determine the falling edges of Point A and Point C and the rising edges of Point B and Point D. If tAB is greater than tCD and SIO is selected by the resolution of the operation mode determination, the second byte code is 0x30 even though the transmitted code on the first byte is not 0x30 (The first byte code to determine I/O interface mode is described as 0x30). Page 627 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG Start Initialize TMRB0 Prescaler is on.(source clock:φT0) Point A High-to-low transition on serial receive pin ? YES TMRB0 starts counting up Point B Low-to-high transition on serial receive pin ? YES Software-capture and save timer value (tAB) Point C High-to-low transition on serial receive pin ? YES Software-capture and save timer value (tAC) Point D Low-to-high transition on serial receive pin ? YES Software-capture and save timer value (tAD) 16-bit Timer 0 stops countting YES WAC Ӎ tAD? Make backup copy of tAD value Stop operation (infinite wating for RESET) Done Figure 22-5 Serial Operation Mode Byte Reception Flowchart 2013/5/31 Page 628 TMPM361F10FG Start tCD ← tAD  tAC YES WAB > tCD? UART mode I/O interface mode Figure 22-6 Serial Operation Mode Determination Flowchart 22.2.10.7 Password The RAM Transfer command (0x10) causes the boot program to perform password verification. Following an echo-back of the command code, the boot program verifies the contents of the 12-byte password area within the flash memory. The following table shows the password area of each product. Product name Area TMPM361F10FG 0x3F8F_FFF4 to 0x3F8F_FFFF Note:If a password is set to 0xFF (erased data area), it is difficult to protect data securely due to an easy-to-guess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. If all these address locations contain the same bytes of data other than 0xFF, a password area error occurs as shown in Figure 22-7. In this case, the boot program returns an error acknowledge (0x11) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all 0xFFs. Receiving data (5th to 16th bytes) from the controller is compared to the password stored in the flash memory. All of the 12 bytes must match to pass the password verification. Otherwise, a password error occurs, which causes the boot program to reply an error acknowledge in response to the checksum byte (the 17th byte). The password verification is performed even if the security function is enabled. Start Are all bytes the same ? YES Are all bytes equal to 0xFF YES Password area error Password area is normal. Figure 22-7 Password Area Verification Flowchart Page 629 2013/5/31 22. 22.2 Flash Operation Mode TMPM361F10FG 22.2.10.8 Calculation of the Show Flash Memory Sum Command The result of the sum calculation ("byte + byte + byte + ・ ・ ・ ") is responded by a half-word quantity. The Show Flash Memory Sum command adds all 512 Kbytes of the flash memory together and provides the total sum as a halfword quantity. The sum is sent to the controller, with the upper eight bits first, followed by the lower eight bits. Example) 0xA1 0xB2 0xC3 0xD4 22.2.10.9 For the interest of simplicity, assume the depth of the flash memory is four location. Then the sum of the four bytes is calculated as : 0xA1 + 0xB2 + 0xC3 + 0xD4 = 0x02EA Hence, 0x02 is first sent to the controller, followed by 0xEA. Checksum Calculation The checksum byte for a series of bytes of data is calculated by adding the bytes together with ignoring the carries and calculating the 8-bit two’s complement by using lower 8 bits. The Show Flash Memory Sum command and the Show Product Information command perform the checksum calculation. The controller must perform the same checksum operation in transmitting checksum bytes. Example) Assume the Show Flash Memory Sum command provides the upper and lower bytes of the sum as 0xE5 and 0xF6. To calculate the checksum for a series of 0xE5 and 0xF6: Add the bytes together 0xE5 + 0xF6 = 0x1DB Calculate the two’s complement by using lower 8 bits, and that is the checksum byte. Then send 0x25 to the controller. 0 - 0xDB = 0x25 2013/5/31 Page 630 TMPM361F10FG 22.2.11 General Boot Program Flowchart Figure 22-8 shows an overall flowchart of the boot program. Single Boot program starts Initialize Get SIO operation mode  UART SIO operation mode ?  Baud rate setting ? ྠᮇᘧ Can not be set タᐃྍ⬟ Set I/O interface mode Program UART mode and baud rate ACK data ← received data (0x30@I/O interface) ACK data ← received data (0x86@UART) (Send 0x30) Normal response (Send 0x86) Normal response Stop operation Prepare to get a command ACK data ← ACK data & 0xF0 Receive routine Get a command  Yes Receive error ? ACK data ← ACK data 0x08 Transmission routine (Send x8H: receive error) No normally   RAM transfer ? SUM ? YES (0x10)   Show product information? YES (0x20) Chip erase ? YES (0x30) YES (0x40) ACK data ← Received data (0x10) ACK data ← Received data (0x20) ACK data ← Received data (0x30) ACK data ← Received data (0x40) Transmission roiutine (Send 0x10: normal response) Transmission roiutine (Send 0x20: normal response) Transmission roiutine (Send 0x30: normal response) Transmission roiutine (Send 0x40: normal response) RAM transfer processing Show Flash Memory Sum processing Show Product information processing Chip erase processing Command error ACK data ← Received data (0x01) Transmission routine (Send 0xX1: Command error) Processed normally?