TMPM366FYXBG

32 Bit RISC Microcontroller TX03 Series TMPM366FDXBG/FYXBG/FWXBG © 2013 TOSHIBA CORPORATION All Rights Reserved TMPM366FDXBG/FYXBG/FWXBG ************************************************************************************************************************* ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* R TMPM366FDXBG/FYXBG/FWXBG Introduction: Notes on the description of SFR (Special Function Register) under this specification An SFR (Special Function Register) is a control register for periperal circuits (IP). The SFR addressses of IPs are described in the chapter on memory map, and the details of SFR are given in the chapter of each IP. Definition of SFR used in this specification is in accordance with the following rules. a. SFR table of each IP as an example ・ SFR tables in each chapter of IP provides register names, addresses and brief descriptions. ・ All registers have a 32-bit unique address and the addresses of the registers are defined as follows, with some exceptions: "Base address + (Unique) address" Base Address = 0x0000_0000 Register name Control register Address(Base+) SAMCR 0x0004 0x000C Note: SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) + unique address (0x0004)). Note: The register shown above is an example for explanation purpose and not for demonstration purpose. This register does not exist in this microcontroller. b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and functions. TMPM366FDXBG/FYXBG/FWXBG 1.2.2 SAMCR(Control register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 9 15 14 13 12 11 10 bit symbol - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol MODE After reset 0 0 0 0 Bit Bit Symbol TDATA 0 0 1 Type 0 Function 31-10 − R "0" can be read. 9-7 MODE[2:0] R/W Operation mode settings 000 : Sample mode 0 001 : Sample mode 1 010 : Sample mode 2 011 : Sample mode 3 The settings other than those above: Reserved 6-0 Note: TDATA[6:0] W Transmitted data The Type is divided into three as shown below. R/W c. 8 MODE READ WRITE R READ W WRITE Data descriptopn Meanings of symbols used in the SFR description are as shown below. ・ x:channel numbers/ports ・ n,m:bit numbers d. Register descriptoption Registers are described as shown below. ・ Register name Exmaple: SAMCR="000" or SAMCR="000" indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width). TMPM366FDXBG/FYXBG/FWXBG Revision History Date Revision Comment 2011/5/10 Tentative 1 First Release of Revised 2011/10/19 1 First Release 2011/11/17 2 Contents Revised 2013/6/11 3 Contents Revised Table of Contents Introduction: Notes on the description of SFR (Special Function Register) under this specification TMPM366FDXBG/FYXBG/FWXBG 1.1 1.2 1.3 1.4 Features......................................................................................................................................1 Block Diagram...........................................................................................................................4 Pin Layout (Top view)..............................................................................................................5 Pin names and Functions...........................................................................................................6 1.4.1 1.4.2 1.5 Sorted by Pin.......................................................................................................................................................................6 Sorted by Port....................................................................................................................................................................13 Pin Numbers and Power Supply Pins.....................................................................................20 2. Processor Core 2.1 2.2 2.3 Information on the processor core..........................................................................................21 Configurable Options..............................................................................................................21 Exceptions/ Interruptions.........................................................................................................22 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.5 2.6 Number of Interrupt Inputs...............................................................................................................................................22 Number of Priority Level Interrupt Bits...........................................................................................................................22 SysTick..............................................................................................................................................................................22 SYSRESETREQ................................................................................................................................................................22 LOCKUP...........................................................................................................................................................................22 Auxiliary Fault Status register..........................................................................................................................................22 Events......................................................................................................................................23 Power Management.................................................................................................................23 Exclusive access......................................................................................................................23 3. Debug Interface 3.1 3.2 3.3 3.4 3.5 3.6 Specification Overview...........................................................................................................25 SWJ-DP...................................................................................................................................25 ETM.........................................................................................................................................25 Pin Functions...........................................................................................................................26 Peripheral Functions in Halt Mode.........................................................................................27 Connection with a Debug Tool...............................................................................................27 3.6.1 3.6.2 About connection with debug tool....................................................................................................................................27 Important points of using debug interface pins used as general-purpose ports...............................................................27 4. JTAG Interface 4.1 Overview..................................................................................................................................29 i 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 Signal Summary and Connection Example............................................................................30 Outline.....................................................................................................................................31 JTAG Controller and Registers...............................................................................................31 Instruction Register.................................................................................................................32 Boundary Scan Register..........................................................................................................33 Test Access Port (TAP)...........................................................................................................34 TAP Controller........................................................................................................................34 Resetting the TAP Controller..................................................................................................34 State Transitions of the TAP Controller...............................................................................35 Boundary Scan Order............................................................................................................38 Instructions Supported by the JTAG Controller Cells..........................................................39 5. Memory Map 5.1 Memory map...........................................................................................................................43 5.1.1 5.1.2 5.1.3 5.2 Memory map of the TMPM366FD...................................................................................................................................44 Memory map of the TMPM366FY...................................................................................................................................45 Memory map of the TMPM366FW..................................................................................................................................46 SFR area detail........................................................................................................................47 6. Reset 6.1 Initial state...............................................................................................................................49 6.1.1 6.2 6.3 6.3.1 6.4 State before input reset......................................................................................................................................................49 Cold reset.................................................................................................................................49 Warm reset...............................................................................................................................50 Reset period.......................................................................................................................................................................50 After reset................................................................................................................................50 7. Watchdog Timer(WDT) 7.1 7.2 Configuration...........................................................................................................................51 Register....................................................................................................................................52 7.2.1 7.2.2 7.3 Operations................................................................................................................................55 7.3.1 7.3.2 7.4 Basic Operation.................................................................................................................................................................55 Operation Mode and Status...............................................................................................................................................55 Operation when malfunction (runaway) is detected...............................................................56 7.4.1 7.4.2 7.5 WDMOD(Watchdog Timer Mode Register) ...................................................................................................................52 WDCR (Watchdog Timer Control Register)....................................................................................................................54 INTWDT interrupt generation...........................................................................................................................................56 Internal reset generation....................................................................................................................................................57 Control register........................................................................................................................58 7.5.1 7.5.2 7.5.3 Watchdog Timer Mode Register (WDMOD)...................................................................................................................58 Watchdog Timer Control Register(WDCR).....................................................................................................................58 Setting example.................................................................................................................................................................59 7.5.3.1 7.5.3.2 7.5.3.3 7.5.3.4 ii Disabling control Enabling control Watchdog timer clearing control Detection time of watchdog timer 8. Clock/Mode control 8.1 8.2 Features....................................................................................................................................61 Registers..................................................................................................................................62 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.3 Register List.......................................................................................................................................................................62 CGSYSCR (System control register)................................................................................................................................63 CGOSCCR (Oscillation control register).........................................................................................................................64 CGSTBYCR (Standby control register)...........................................................................................................................66 CGPLLSEL (PLL Selection Register)..............................................................................................................................67 CGUSBCTL (USB clock control register).......................................................................................................................68 CGPROTECT (Protect register)........................................................................................................................................69 Clock control...........................................................................................................................70 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Clock Type........................................................................................................................................................................70 Initial Values after Reset...................................................................................................................................................70 Clock system Diagram......................................................................................................................................................71 Warm-up function..............................................................................................................................................................72 Clock Multiplication Circuit (PLL)..................................................................................................................................74 8.3.5.1 8.3.5.2 8.3.5.3 8.3.5.4 8.3.6 System clock......................................................................................................................................................................77 8.3.6.1 8.3.7 8.3.8 8.4 Mode Transitions...............................................................................................................................................................80 Operation mode.......................................................................................................................81 8.5.1 8.6 System Clock setting Prescaler Clock Control.....................................................................................................................................................79 System Clock Pin Output Function..................................................................................................................................79 Modes and Mode Transitions..................................................................................................80 8.4.1 8.5 How to configure the PLL function Change PLL multiplying PLL setup sequence Change PLL multiplying sequence NORMAL mode................................................................................................................................................................81 Low Power Consumption Modes............................................................................................81 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 IDLE mode........................................................................................................................................................................81 STOP1 mode......................................................................................................................................................................82 STOP2 mode......................................................................................................................................................................82 Low power Consumption Mode Setting...........................................................................................................................84 Operational Status in Each Mode.....................................................................................................................................85 Releasing the Low Power Consumption Mode................................................................................................................86 Warm-up............................................................................................................................................................................87 Clock Operations in Mode Transition..............................................................................................................................88 8.6.8.1 8.6.8.2 Transition of operation modes: NORMAL → STOP1 → NORMAL Transition of operation modes: NORMAL → STOP2 → NORMAL 9. Exceptions 9.1 Overview..................................................................................................................................91 9.1.1 9.1.2 Exception Types................................................................................................................................................................91 Handling Flowchart...........................................................................................................................................................92 9.1.2.1 9.1.2.2 9.1.2.3 9.1.2.4 9.2 9.3 9.4 9.5 Exception Exception Executing Exception Request and Detection Handling and Branch to the Interrupt Service Routine (Pre-emption) an ISR exit Reset Exceptions.....................................................................................................................97 Non-Maskable Interrupts (NMI).............................................................................................98 SysTick....................................................................................................................................98 Interrupts..................................................................................................................................99 9.5.1 Interrupt Sources................................................................................................................................................................99 9.5.1.1 9.5.1.2 9.5.1.3 9.5.1.4 9.5.1.5 Interrupt Route Generation Transmission Precautions when using external interrupt pins List of Interrupt Sources iii 9.5.1.6 9.5.2 Active level Interrupt Handling...........................................................................................................................................................104 9.5.2.1 9.5.2.2 9.5.2.3 9.5.2.4 9.5.2.5 9.5.2.6 9.6 Flowchart Preparation Detection by Clock Generator Detection by CPU CPU processing Interrupt Service Routine (ISR) Exception/Interrupt-Related Registers..................................................................................109 9.6.1 9.6.2 Register List.....................................................................................................................................................................109 NVIC Registers................................................................................................................................................................110 9.6.2.1 9.6.2.2 9.6.2.3 9.6.2.4 9.6.2.5 9.6.2.6 9.6.2.7 9.6.2.8 9.6.2.9 9.6.2.10 9.6.2.11 9.6.2.12 9.6.2.13 9.6.2.14 9.6.2.15 9.6.2.16 9.6.2.17 9.6.3 SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register SysTick Calibration Value Register Interrupt Set-Enable Register 1 Interrupt Set-Enable Register 2 Interrupt Clear-Enable Register 1 Interrupt Clear-Enable Register 2 Interrupt Set-Pending Register 1 Interrupt Set-Pending Register 2 Interrupt Clear-Pending Register 1 Interrupt Clear-Pending Register 2 Interrupt Priority Register Vector Table Offset Register Application Interrupt and Reset Control Register System Handler Priority Register System Handler Control and State Register Clock generator registers.................................................................................................................................................129 9.6.3.1 9.6.3.2 9.6.3.3 9.6.3.4 9.6.3.5 9.6.3.6 CGIMCGA(CG Interrupt Mode Control Register A) CGIMCGB(CG Interrupt Mode Control Register B) CGIMCGC(CG Interrupt Mode Control Register C) CGICRCG(CG Interrupt Request Clear Register) CGNMIFLG(NMI Flag Register) CGRSTFLG (Reset Flag Register) 10. Input/Output Ports 10.1 Port Functions......................................................................................................................139 10.1.1 10.1.2 10.1.3 10.2 Function Lists................................................................................................................................................................139 Port Registers Outline...................................................................................................................................................142 Port States in STOP1/STOP2 Mode.............................................................................................................................143 Port functions.......................................................................................................................144 10.2.1 Port A (PA0 to PA7).....................................................................................................................................................144 10.2.1.1 10.2.1.2 10.2.1.3 10.2.1.4 10.2.1.5 10.2.1.6 10.2.1.7 10.2.2 Port B (PB0 to PB7)......................................................................................................................................................149 10.2.2.1 10.2.2.2 10.2.2.3 10.2.2.4 10.2.2.5 10.2.2.6 10.2.2.7 10.2.2.8 10.2.2.9 10.2.3 Port B Register PBDATA (Port B data register) PBCR (Port B output control register) PBFR1 (Port B function register 1) PBFR2 (Port B function register 2) PBFR3 (Port B function register 3) PBOD (Port B open drain control register) PBPUP (Port B pull-up control register) PBIE (Port B input control register) Port C (PC0 to PC2)......................................................................................................................................................156 10.2.3.1 10.2.3.2 10.2.3.3 10.2.3.4 10.2.3.5 10.2.3.6 10.2.3.7 10.2.3.8 10.2.3.9 iv Port A register PADATA (Port A data register) PACR (Port A output control register) PAFR1 (Port A function register 1) PAOD (Port A open drain control register) PAPUP (Port A pull-up control register) PAIE (Port A input control register) Port C Register PCDATA (Port C data register) PCCR (Port C output control register) PCFR1 (Port C function register 1) PCFR2 (Port C function register 2) PCFR3 (Port C function register 3) PCFR4 (Port C function register 4) PCOD (Port C open drain control register) PCPUP (Port C pull-up control register) 10.2.3.10 10.2.4 10.2.4.1 10.2.4.2 10.2.4.3 10.2.4.4 10.2.4.5 10.2.4.6 10.2.4.7 10.2.4.8 10.2.5 Port D Register PDDATA (Port D data register) PDCR (Port D output control register) PDFR2 (Port D function register 2) PDFR3 (Port D function register 3) PDOD (Port D open drain control register) PDPUP (Port D pull-up control register) PDIE (Port D input control register) Port E (PE0 to PE7)......................................................................................................................................................169 10.2.5.1 10.2.5.2 10.2.5.3 10.2.5.4 10.2.5.5 10.2.5.6 10.2.5.7 10.2.5.8 10.2.5.9 10.2.5.10 10.2.5.11 10.2.6 Port F Register PFDATA (Port F data register) PFCR (Port F output control register) PFFR1 (Port F function register 1) PFFR2 (Port F function register 2) PFFR3 (Port F function register 3) PFOD (Port F open drain control register) PFPUP (Port F pull-up control register) PFIE (Port F input control register) Port G (PG0 to PG5).....................................................................................................................................................184 10.2.7.1 10.2.7.2 10.2.7.3 10.2.7.4 10.2.7.5 10.2.7.6 10.2.7.7 10.2.7.8 10.2.7.9 10.2.7.10 10.2.7.11 10.2.8 Port I Register PIDATA (Port I data register) PICR (Port I output control register) PIFR1(Port I function register 1) PIOD (Port H open drain control register) PIPUP (Port I pull-up control register) PIPDN (Port I pull-down control register) PIIE (Port I input control register) Port J (PJ0 to PJ7).......................................................................................................................................................208 10.2.10.1 10.2.10.2 10.2.10.3 10.2.10.4 10.2.10.5 10.2.10.6 10.2.10.7 10.2.11 Port H Register PHDATA (Port H data register) PHCR (Port H output control register) PHFR1 (Port H function register 1) PHFR2 (Port H function register 2) PHFR3 (Port H function register 3) PHFR4 (Port H function register 4) PHOD (Port H open drain control register) PHPUP (Port H pull-up control register) PHIE (Port H input control register) Port I (PI0 to PI7)..........................................................................................................................................................201 10.2.9.1 10.2.9.2 10.2.9.3 10.2.9.4 10.2.9.5 10.2.9.6 10.2.9.7 10.2.9.8 10.2.10 Port G Register PGDATA (Port G data register) PGCR (Port G output control register) PGFR1 (Port G function register 1) PGFR2 (Port G function register 2) PGFR3 (Port G function register 3) PGFR4 (Port G function register 4) PGFR5 (Port G function register 5) PGOD (Port G open drain control register) PGPUP (Port G pull-up control register) PGIE (Port G input control register) Port H (PH0 to PH4).....................................................................................................................................................193 10.2.8.1 10.2.8.2 10.2.8.3 10.2.8.4 10.2.8.5 10.2.8.6 10.2.8.7 10.2.8.8 10.2.8.9 10.2.8.10 10.2.9 Port E Register PEDATA (Port E data register) PECR (Port E output control register) PEFR1 (Port E function register 1) PEFR2 (Port E function register 2) PEFR3 (Port E function register 3) PEFR4 (Port E function register 4) PEFR5 (Port E function register 5) PEOD (Port E open drain control register) PEPUP (Port E pull-up control register) PEIE (Port E input control register) Port F (PF0 to PF7).......................................................................................................................................................177 10.2.6.1 10.2.6.2 10.2.6.3 10.2.6.4 10.2.6.5 10.2.6.6 10.2.6.7 10.2.6.8 10.2.6.9 10.2.7 PCIE (Port C input control register) Port D (PD0 to PD7).....................................................................................................................................................163 Port J Register PJDATA (Port J data register) PJCR (Port J output control register) PJFR2 (Port J function register 2) PJFR3 (Port J function register 3) PJPUP (Port J pull-up control register) PJIE (Port J input control register) Port K (PK0 to PK3)...................................................................................................................................................214 10.2.11.1 10.2.11.2 10.2.11.3 Port K Register PKDATA (Port K data register) PKCR (Port K output control register) v 10.2.11.4 10.2.11.5 10.2.11.6 10.2.11.7 10.3 Block Diagrams of Ports.....................................................................................................220 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 10.3.10 10.3.11 10.4 PKFR2 (Port K function register 2) PKFR3 (Port K function register 3) PKPUP (Port K pull-up control register) PKIE (Port K input control register) Port Types......................................................................................................................................................................220 Type FT1.......................................................................................................................................................................221 Type FT2.......................................................................................................................................................................222 Type FT3.......................................................................................................................................................................223 Type FT4.......................................................................................................................................................................224 Type FT5.......................................................................................................................................................................225 Type FT6.......................................................................................................................................................................226 Type FT7.......................................................................................................................................................................227 Type FT8.......................................................................................................................................................................228 Type FT9.....................................................................................................................................................................229 Type FT10...................................................................................................................................................................230 Appendix (Port setting List)................................................................................................231 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 Port A Setting................................................................................................................................................................231 Port B Setting................................................................................................................................................................232 Port C Setting................................................................................................................................................................233 Port D Setting................................................................................................................................................................234 Port E Setting................................................................................................................................................................235 Port F Setting.................................................................................................................................................................236 Port G Setting................................................................................................................................................................237 Port H Setting................................................................................................................................................................238 Port I Setting..................................................................................................................................................................239 Port J Setting...............................................................................................................................................................240 Port K Setting..............................................................................................................................................................241 11. DMA Controller(DMAC) 11.1 11.2 11.3 11.4 Overview..............................................................................................................................243 DMA transfer type...............................................................................................................244 Block diagram.....................................................................................................................245 Product information of TMPM366FDXBG/FYXBG/FWXBG.........................................246 11.4.1 11.4.2 11.4.3 11.4.4 11.5 Peripheral function supported with Peripheral to Peripheral Transfer........................................................................246 DMA request.................................................................................................................................................................246 Interrupt request.............................................................................................................................................................247 Base address of registers...............................................................................................................................................247 Description of Registers......................................................................................................248 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 11.5.9 11.5.10 11.5.11 11.5.12 11.5.13 11.5.14 11.5.15 11.5.16 11.5.17 11.6 11.6.1 11.6.2 vi DMAC register list........................................................................................................................................................248 DMACxIntStatus (DMAC Interrupt Status Register)..................................................................................................249 DMACxIntTCStatus (DMAC Interrupt Terminal Count Status Register)..................................................................250 DMACxIntTCClear (DMAC Interrupt Terminal Count Clear Register).....................................................................251 DMACxIntErrorStatus (DMAC Interrupt Error Status Register)................................................................................252 DMACxIntErrClr (DMAC Interrupt Error Clear Register).........................................................................................253 DMACxRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register)..................................................254 DMACxRawIntErrorStatus (DMAC Raw Error Interrupt Status Register)................................................................255 DMACxEnbldChns (DMAC Enabled Channel Register)............................................................................................256 DMACxSoftBReq (DMAC Software Burst Request Register).................................................................................257 DMACxSoftSReq (DMAC Software Single Request Register)................................................................................259 DMACxConfiguration (DMAC Configuration Register)...........................................................................................261 DMACxCnSrcAddr (DMAC Channelx Source Address Register)...........................................................................262 DMACxCnDestAddr (DMAC Channelx Destination Address Register)..................................................................263 DMACxCnLLI (DMAC Channelx Linked List Item Register).................................................................................264 DMACxCnControl (DMAC Channeln Control Register)..........................................................................................265 DMACxCnConfiguration (DMAC Channel n Configuration Register)....................................................................267 Special Functions.................................................................................................................269 Scatter/gather function...................................................................................................................................................269 Linked list operation......................................................................................................................................................270 12. External bus interface (EBIF) 12.1 12.2 Overview............................................................................................................................273 Address and Data Pins........................................................................................................274 12.2.1 12.3 Address and Data pin setting........................................................................................................................................274 Data Format.........................................................................................................................275 12.3.1 Little-endian mode.........................................................................................................................................................275 12.3.1.1 12.3.1.2 12.3.1.3 12.4 External Bus Operations (Separete Bus Mode)..................................................................279 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 Basic bus operation.......................................................................................................................................................279 Wait timing....................................................................................................................................................................280 Read and Write Recovery time.....................................................................................................................................282 Chip select recovery time..............................................................................................................................................283 Read and Write setup cycle..........................................................................................................................................284 External Bus Operations (Multiplexed Bus Mode)............................................................285 12.5.1 12.5.2 12.5.3 12.5.4 12.5.5 12.5.6 12.6 Basic bus operation.......................................................................................................................................................285 Wait timing....................................................................................................................................................................286 Time that it takes before ALE is asserted....................................................................................................................288 Read and Write Recovery Time....................................................................................................................................289 Chip select recovery time..............................................................................................................................................289 Read and Write setup cycle..........................................................................................................................................291 Registers..............................................................................................................................292 12.6.1 12.6.2 12.6.3 12.6.4 12.7 Word access Half word access Byte access Registers List.................................................................................................................................................................292 EXBMOD (External Bus Mode Control Register).......................................................................................................293 EXBASx (External Bus Area and Start Address Configuration Register)..................................................................294 EXBCSx (External Bus Chip Select Control Register)................................................................................................295 Connection example for external memory..........................................................................296 12.7.1 12.7.2 Connection Example for external 16-bit SRAM and NOR-Flash (Sparate bus).........................................................296 Connection Example for external 16-bit SRAM and NOR-Flash (Multiplex bus).....................................................297 13. 16-bit Timer/Event Counters(TMRB) 13.1 13.2 13.3 13.4 Outline.................................................................................................................................299 Differences in the Specifications........................................................................................300 Configuration.......................................................................................................................301 Registers..............................................................................................................................302 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 13.4.8 13.4.9 13.4.10 13.4.11 13.4.12 13.4.13 13.4.14 13.5 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 Register list according to channel.................................................................................................................................302 TBxEN (Enable register)...............................................................................................................................................303 TBxRUN(RUN register)................................................................................................................................................304 TBxCR (Control register)..............................................................................................................................................305 TBxMOD (Mode register).............................................................................................................................................306 TBxFFCR (Flip-flop control register)...........................................................................................................................307 TBxST (Status register).................................................................................................................................................308 TBxIM (Interrupt mask register)...................................................................................................................................309 TBxUC (Up counter capture register)..........................................................................................................................310 TBxRG0 (Timer register 0).........................................................................................................................................311 TBxRG1 (Timer register 1).........................................................................................................................................311 TBxCP0 (Capture register 0)......................................................................................................................................312 TBxCP1 (Capture register 1)......................................................................................................................................312 TBxDMA(DMA request enable register)...................................................................................................................313 Description of Operations for Each Circuit........................................................................314 Prescaler.........................................................................................................................................................................314 Up-counter (UC)............................................................................................................................................................318 Timer registers (TBxRG0, TBxRG1)...........................................................................................................................318 Capture...........................................................................................................................................................................319 Capture registers (TBxCP0, TBxCP1)..........................................................................................................................319 vii 13.5.6 13.5.7 13.5.8 13.5.9 13.6 Up-counter capture register (TBxUC)..........................................................................................................................319 Comparators (CP0, CP1)...............................................................................................................................................319 Timer Flip-flop (TBxFF0).............................................................................................................................................319 Capture interrupt (INTCAPx0, INTCAPx1).................................................................................................................319 Description of Operations for Each Mode..........................................................................320 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 13.7 16-bit Interval Timer Mode...........................................................................................................................................320 16-bit Event Counter Mode...........................................................................................................................................320 16-bit PPG (Programmable Pulse Generation) Output Mode......................................................................................321 Timer synchronous mode..............................................................................................................................................323 External trigger count start mode..................................................................................................................................323 Applications using the Capture Function............................................................................324 13.7.1 13.7.2 13.7.3 13.7.4 One-shot pulse output triggered by an external pulse..................................................................................................324 Frequency measurement................................................................................................................................................326 Pulse width measurement..............................................................................................................................................326 Time Difference Measurement......................................................................................................................................327 14. USB Device Controller (USBD) 14.1 14.2 Outline.................................................................................................................................329 System Structure..................................................................................................................330 14.2.1 AHB Bus Bridge (UDC2AB).......................................................................................................................................331 14.2.1.1 14.2.1.2 14.2.1.3 14.2.2 Toshiba USB-Spec2.0 Device Controller (UDC2).......................................................................................................336 14.2.2.1 14.2.2.2 14.2.2.3 14.3 14.4 Features and Functions Specifications of Flags Commands to EP How to connect with the USB bus......................................................................................343 Registers..............................................................................................................................344 14.4.1 UDC2AB Register.........................................................................................................................................................344 14.4.1.1 14.4.1.2 14.4.1.3 14.4.1.4 14.4.1.5 14.4.1.6 14.4.1.7 14.4.1.8 14.4.1.9 14.4.1.10 14.4.1.11 14.4.1.12 14.4.1.13 14.4.1.14 14.4.1.15 14.4.1.16 14.4.1.17 14.4.1.18 14.4.1.19 14.4.1.20 14.4.1.21 14.4.1.22 14.4.2 UDC2AB Register list UDFSINTSTS (Interrupt Status Register) UDFSINTENB(Interrupt Enable Register) UDFSMWTOUT(Master Write Timeout Register) UDFSC2STSET(UDC2 Setting Register) UDFSMSTSET(DMAC Setting Register) UDFSDMACRDREQ(DMAC Read Request Register) UDFSDMACRDVL(DMAC Read Value Register) UDFSUDC2RDREQ(UDC2 Read Request Register) UDFSUDC2RDVL(UDC2 Read Value Register) UDFSARBTSET(Arbiter Setting Register) UDFSMWSADR(Master Write Start Address Register) UDFSMWEADR(Master Write End Address Register) UDFSMWCADR(Master Write Current Address Register) UDFSMWAHBADR(Master Write AHB Address Register) UDFSMRSADR(Master Read Start Address Register) UDFSMREADR(Master Read End Address Register) UDFSMRCADR(Master Read Current Address Register) UDFSMRAHBADR(Master Read AHB Address Register) UDFSPWCTL(Power Detect Control Register) UDFSMSTSTS(Master Status Register) UDFSTOUTCNT(Timeout Count Register) UDC2 Register..............................................................................................................................................................367 14.4.2.1 14.4.2.2 14.4.2.3 14.4.2.4 14.4.2.5 14.4.2.6 14.4.2.7 14.4.2.8 14.4.2.9 14.4.2.10 14.4.2.11 14.4.2.12 14.4.2.13 14.4.2.14 viii Functions and Features Configuration Clock Domain UDC2 Registers How to access the UDC2 register UDFS2ADR(Address-State register) UDFS2FRM(Frame register) UDFS2CMD(Command register) UDFS2BRQ(bRequest-bmRequest Type register) UDFS2WVL(wValue register) UDFS2WIDX(wIndex register) UDFS2WLGTH(wLength register) UDFS2INT(INT register) UDFS2INTEP(INT_EP register) UDFS2INTEPMSK(INT_EP_MASK register) UDFS2INTRX0(INT_RX_DATA0 register) UDFS2INTNAK(INT_NAK register) 14.4.2.15 14.4.2.16 14.4.2.17 14.4.2.18 14.4.2.19 14.4.2.20 14.4.2.21 14.4.2.22 14.4.2.23 14.5 UDFS2INTNAKMSK(INT_NAK_MASK register) UDFS2EP0MSZ(EP0_MaxPacketSize register) UDFS2EP0STS(EP0_Status register) UDFS2EP0DSZ(EP0_Datasize register) UDFS2EP0FIFO(EP0_FIFO register) UDFS2EPxMSZ(EPx_MaxPacketSizeRegister) UDFS2EPxSTS(EPx_Status register) UDFS2EPxDSZ(EPx_Datasize register) UDFS2EPxFIFO(EPx_FIFO register) Description of UDC2AB operation.....................................................................................397 14.5.1 14.5.2 Reset...............................................................................................................................................................................397 Interrupt Signals............................................................................................................................................................398 14.5.2.1 14.5.2.2 14.5.3 14.5.4 Operation Sequence.......................................................................................................................................................400 Master Transfer Operation............................................................................................................................................402 14.5.4.1 14.5.4.2 14.5.5 Connection Diagram of Power Management Control Signal Sequence of USB Bus Power (VBUS) Connection/Disconnection USB Reset......................................................................................................................................................................407 Suspend / Resume.........................................................................................................................................................408 14.5.7.1 14.5.7.2 14.5.7.3 14.5.7.4 14.6 14.7 Master Read transfer Master Write transfer USB Power Management Control.................................................................................................................................406 14.5.5.1 14.5.5.2 14.5.6 14.5.7 INTUSB Interrupt Signal INTUSBWKUP Interrupt Shift to the suspended state Resuming from suspended state (resuming from the USB host) Resuming from the suspend state (disconnect) Remote wakeup from the suspended state USB Device Response.........................................................................................................415 Flow of Control in Transfer of EPs....................................................................................417 14.7.1 EP0.................................................................................................................................................................................417 14.7.1.1 14.7.1.2 14.7.1.3 14.7.1.4 14.7.1.5 14.7.2 14.8 Control-RD transfer Control-WR transfer (without DATA-Stage) Control-WR transfer (with DATA-Stage) Example of using the INT_STATUS_NAK flag Processing when standard request EPs other than EP0........................................................................................................................................................431 Suspend/Resume State.........................................................................................................432 14.8.1 14.8.2 Shift to the suspended state...........................................................................................................................................432 Resuming from suspended state....................................................................................................................................432 14.8.2.1 14.8.2.2 14.9 Resuming by an output from the host Resuming by way remote wakeup from UDC2 USB-Spec2.0 Device Controller Appendix........................................................................433 14.9.1 Appendix A System Power Management.....................................................................................................................433 14.9.1.1 14.9.1.2 14.9.1.3 14.9.1.4 14.9.2 Appendix B About Setting an Odd Number of Bytes as MaxPacketSize...................................................................439 14.9.2.1 14.9.3 Connect / Disconnect Operations Reset Operation Suspend Operation Resume Operation Setting an odd number in the UDFS2EPxMSZ Appendix C Isochronous Translator.............................................................................................................................442 14.9.3.1 14.9.3.2 Accessing an EP using Isochronous transfer Restrictions on command usage to EP when using Isochronous transfer 15. Serial Channel (SIO/UART) 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 15.4.7 Overview............................................................................................................................443 Difference in the Specifications of SIO Modules...............................................................443 Configuration.......................................................................................................................444 Registers Description...........................................................................................................445 Registers List in Each Channel.....................................................................................................................................445 SCxEN (Enable Register)..............................................................................................................................................446 SCxBUF (Buffer Register)............................................................................................................................................447 SCxCR (Control Register)............................................................................................................................................448 SCxMOD0 (Mode Control Register 0).........................................................................................................................449 SCxMOD1 (Mode Control Register 1).........................................................................................................................450 SCxMOD2 (Mode Control Register 2).........................................................................................................................451 ix 15.4.8 SCxBRCR (Baud Rate Generator Control Register), SCxBRADD (Baud Rate Generator Control Register 2).......453 15.4.9 SCxFCNF (FIFO Configuration Register)....................................................................................................................455 15.4.10 SCxRFC (RX FIFO Configuration Register).............................................................................................................456 15.4.11 SCxTFC (TX FIFO Configuration Register) (Note2)................................................................................................457 15.4.12 SCxRST (RX FIFO Status Register)..........................................................................................................................458 15.4.13 SCxTST (TX FIFO Status Register)...........................................................................................................................459 15.4.14 SCxDMA (DMA request enable register)..................................................................................................................460 15.5 15.6 Operation in Each Mode.....................................................................................................461 Data Format.........................................................................................................................462 15.6.1 15.6.2 Data Format List............................................................................................................................................................462 Parity Control................................................................................................................................................................463 15.6.2.1 15.6.2.2 15.6.3 15.7 Transmission Receiving Data STOP Bit Length...........................................................................................................................................................463 Clock Control......................................................................................................................464 15.7.1 15.7.2 Prescaler.........................................................................................................................................................................464 Serial Clock Generation Circuit....................................................................................................................................468 15.7.2.1 15.7.2.2 15.8 Baud Rate Generator Clock Selection Circuit Transmit/Receive Buffer and FIFO....................................................................................472 15.8.1 15.8.2 15.8.3 Configuration.................................................................................................................................................................472 Transmit/Receive Buffer...............................................................................................................................................472 FIFO...............................................................................................................................................................................473 15.9 Status Flag...........................................................................................................................473 15.10 Error Flag...........................................................................................................................473 15.10.1 15.10.2 15.10.3 15.11 15.11.1 15.11.2 OERR Flag..................................................................................................................................................................474 PERR Flag...................................................................................................................................................................474 FERR Flag...................................................................................................................................................................474 Receive..............................................................................................................................475 Receive Counter..........................................................................................................................................................475 Receive Control Unit...................................................................................................................................................475 15.11.2.1 15.11.2.2 15.11.3 Receive Operation.......................................................................................................................................................475 15.11.3.1 15.11.3.2 15.11.3.3 15.11.3.4 15.11.3.5 15.11.3.6 15.12 15.12.1 15.12.2 Transmission Counter..................................................................................................................................................479 Transmission Control..................................................................................................................................................479 15.14.1 RX Interrupts...............................................................................................................................................................484 15.17.1 UART Mode IO Interface Mode Software Reset...................................................................................................................486 DMA request.....................................................................................................................486 Operation in Each Mode...................................................................................................487 Mode 0 (I/O interface mode)......................................................................................................................................487 15.17.1.1 x Single Buffer / Double Buffer FIFO Error Generation..........................................................................................................................................................486 15.14.3.1 15.14.3.2 15.15 15.16 15.17 Single Buffer / Double Buffer FIFO TX interrupts................................................................................................................................................................485 15.14.2.1 15.14.2.2 15.14.3 Operation of Transmission Buffer Transmit FIFO Operation I/O interface Mode/Transmission by SCLK Output Under-run error Handshake function...........................................................................................................483 Interrupt/Error Generation Timing....................................................................................484 15.14.1.1 15.14.1.2 15.14.2 I/O Interface Mode UART Mode Transmit Operation......................................................................................................................................................479 15.12.3.1 15.12.3.2 15.12.3.3 15.12.3.4 15.13 15.14 Receive Buffer Receive FIFO Operation I/O interface mode with SCLK output Read Received Data Wake-up Function Overrun Error Transmission......................................................................................................................479 15.12.2.1 15.12.2.2 15.12.3 I/O interface mode UART Mode Transmitting Data 15.17.1.2 15.17.1.3 15.17.2 15.17.3 15.17.4 Receive Transmit and Receive (Full-duplex) Mode 1 (7-bit UART mode).......................................................................................................................................498 Mode 2 (8-bit UART mode).......................................................................................................................................498 Mode 3 (9-bit UART mode).......................................................................................................................................499 15.17.4.1 15.17.4.2 Wake up function Protocol 16. Asynchronous Serial Channel (UART) 16.1 16.2 16.3 Overview............................................................................................................................501 Configuration.......................................................................................................................503 Registers Description...........................................................................................................504 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 16.3.9 16.3.10 16.3.11 16.3.12 16.3.13 16.3.14 16.3.15 16.3.16 16.4 Registers List ................................................................................................................................................................504 UARTDR (Data Register).............................................................................................................................................505 UARTRSR (Receive status Register)...........................................................................................................................506 UARTECR (Error clear register)..................................................................................................................................507 UARTFR (UART Flag register)...................................................................................................................................508 UARTILPR(UART IrDA low-power counter Register)..............................................................................................510 UARTIBDR (UART integer baud rate Register).........................................................................................................511 UARTFBDR(UART Fractional baud rate Register)....................................................................................................512 UARTLCR_H (UART Line Control Register)............................................................................................................513 UARTCR (UART Control register)............................................................................................................................515 UARTIFLS (UART interrupt FIFO level select register ).........................................................................................517 UARTIMSC (UART Interrupt mask set/clear Register) ...........................................................................................518 UARTRIS (UART Raw interrupt status Register).....................................................................................................520 UARTMIS (UART Masked interrupt status Register)...............................................................................................521 UARTICR (UART Interrupt clear register)................................................................................................................522 UARTDMACR (UART DMA control register).........................................................................................................523 Operation Description.........................................................................................................524 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.4.7 16.4.8 16.4.9 16.4.10 16.4.11 Baud rate generator.......................................................................................................................................................524 Transmit FIFO...............................................................................................................................................................524 Receive FIFO.................................................................................................................................................................524 Transmit logic................................................................................................................................................................524 Receive logic.................................................................................................................................................................524 Interrupt generation logic..............................................................................................................................................524 Interrupt timing..............................................................................................................................................................524 UART interrupt block...................................................................................................................................................525 DMA interface...............................................................................................................................................................525 IrDA circuit description...............................................................................................................................................525 Hardware flow control.................................................................................................................................................526 17. Synchronous Serial Port (SSP) 17.1 17.2 17.3 Overview..............................................................................................................................529 Block Diagram.....................................................................................................................530 Register................................................................................................................................531 17.3.1 17.3.2 17.3.3 17.3.4 17.3.5 17.3.6 17.3.7 17.3.8 17.3.9 17.3.10 17.3.11 17.4 17.4.1 17.4.2 Register List...................................................................................................................................................................531 SSPxCR0(Control register 0)........................................................................................................................................532 SSPxCR1(Control register1).........................................................................................................................................533 SSPxDR(Data register)..................................................................................................................................................534 SSPxSR(Status register)................................................................................................................................................535 SSPxCPSR (Clock prescale register)............................................................................................................................536 SSPxIMSC (Interrupt enable/disable register)..............................................................................................................537 SSPxRIS (Pre-enable interrupt status register).............................................................................................................538 SSPxMIS (Post-enable interrupt status register)..........................................................................................................539 SSPxICR (Interrupt clear register)..............................................................................................................................540 SSPxDMACR (DMA control register).......................................................................................................................540 Overview of SSP.................................................................................................................541 Clock prescaler..............................................................................................................................................................541 Transmit FIFO...............................................................................................................................................................541 xi 17.4.3 17.4.4 17.4.5 17.5 Receive FIFO.................................................................................................................................................................541 Interrupt generation logic..............................................................................................................................................542 DMA interface...............................................................................................................................................................544 SSP operation......................................................................................................................545 17.5.1 17.5.2 17.5.3 17.6 Initial setting for SSP....................................................................................................................................................545 Enabling SSP.................................................................................................................................................................545 Clock ratios....................................................................................................................................................................545 Frame Format......................................................................................................................546 17.6.1 17.6.2 17.6.3 SSI frame format...........................................................................................................................................................547 SPI frame format...........................................................................................................................................................548 Microwire frame format................................................................................................................................................550 18. Serial Bus Interface (I2C/SIO) 18.1 18.2 Configuration.......................................................................................................................554 Register................................................................................................................................555 18.2.1 18.3 18.4 Registers for each channel............................................................................................................................................555 I2C Bus Mode Data Format................................................................................................556 Control Registers in the I2C Bus Mode..............................................................................557 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.4.6 18.4.7 18.5 SBIxCR0(Control register 0)........................................................................................................................................557 SBIxCR1(Control register 1)........................................................................................................................................558 SBIxCR2(Control register 2)........................................................................................................................................560 SBIxSR (Status Register)..............................................................................................................................................561 SBIxBR0(Serial bus interface baud rate register 0).....................................................................................................562 SBIxDBR (Serial bus interface data buffer register)....................................................................................................562 SBIxI2CAR (I2Cbus address register)..........................................................................................................................563 Control in the I2C Bus Mode..............................................................................................564 18.5.1 Serial Clock...................................................................................................................................................................564 18.5.1.1 18.5.1.2 18.5.2 18.5.3 18.5.4 18.5.5 18.5.6 18.5.7 18.5.8 18.5.9 18.5.10 18.5.11 18.5.12 18.5.13 18.5.14 18.5.15 18.5.16 18.6 Setting the Acknowledgement Mode............................................................................................................................565 Setting the Number of Bits per Transfer......................................................................................................................565 Slave Addressing and Address Recognition Mode......................................................................................................565 Operating mode.............................................................................................................................................................565 Configuring the SBI as a Transmitter or a Receiver....................................................................................................566 Configuring the SBI as a Master or a Slave.................................................................................................................566 Generating Start and Stop Conditions..........................................................................................................................566 Interrupt Service Request and Release.........................................................................................................................567 Arbitration Lost Detection Monitor............................................................................................................................567 Slave Address Match Detection Monitor....................................................................................................................569 General-call Detection Monitor...................................................................................................................................569 Last Received Bit Monitor..........................................................................................................................................569 Data Buffer Register (SBIxDBR)...............................................................................................................................569 Baud Rate Register (SBIxBR0)..................................................................................................................................570 Software Reset.............................................................................................................................................................570 Data Transfer Procedure in the I2C Bus ModeI2C............................................................571 18.6.1 18.6.2 Device Initialization......................................................................................................................................................571 Generating the Start Condition and a Slave Address...................................................................................................571 18.6.2.1 18.6.2.2 18.6.3 18.6.4 18.6.5 18.7 18.7.1 18.7.2 18.7.3 18.7.4 18.7.5 18.7.6 Master mode Slave mode Transferring a Data Word.............................................................................................................................................573 18.6.3.1 18.6.3.2 xii Clock source Clock Synchronization Master mode ( = "1") Slave mode ( = "0") Generating the Stop Condition......................................................................................................................................578 Restart Procedure...........................................................................................................................................................578 Control register of SIO mode..............................................................................................580 SBIxCR0(control register 0).........................................................................................................................................580 SBIxCR1(Control register 1)........................................................................................................................................581 SBIxDBR (Data buffer register)...................................................................................................................................582 SBIxCR2(Control register 2)........................................................................................................................................583 SBIxSR (Status Register)..............................................................................................................................................584 SBIxBR0 (Baud rate register 0)....................................................................................................................................585 18.8 Control in SIO mode...........................................................................................................586 18.8.1 Serial Clock...................................................................................................................................................................586 18.8.1.1 18.8.1.2 18.8.2 Clock source Shift Edge Transfer Modes..............................................................................................................................................................588 18.8.2.1 18.8.2.2 18.8.2.3 18.8.2.4 8-bit 8-bit 8-bit Data transmit mode receive mode transmit/receive mode retention time of the last bit at the end of transmission 19. Analog/Digital Converter (ADC) 19.1 19.2 19.3 Outline.................................................................................................................................593 Configuration.......................................................................................................................594 Registers..............................................................................................................................595 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.3.9 19.3.10 19.3.11 19.3.12 19.3.13 19.3.14 19.3.15 19.3.16 19.4 Register list....................................................................................................................................................................595 ADCLK (Conversion Clock Setting Register).............................................................................................................596 ADMOD0 (Mode Control Register 0) .........................................................................................................................598 ADMOD1 (Mode Control Register 1)..........................................................................................................................599 ADMOD2 (Mode Control Register 2) .........................................................................................................................600 ADMOD3 (Mode Control Register 3) .........................................................................................................................601 ADMOD4 (Mode Control Register 4) .........................................................................................................................602 ADMOD5 (Mode Control Register 5)..........................................................................................................................603 ADMOD6 (Mode Control Register 6)..........................................................................................................................604 ADMOD7 (Mode Control Register7).........................................................................................................................605 ADCMPCR0 (Monitor Control Register 0)................................................................................................................606 ADCMPCR1 (AD Monitor Control Register 1).........................................................................................................607 ADCMP0 (AD Conversion Result Comparison Register 0)......................................................................................608 ADCMP1 (AD Conversion Result Comparison Register 1)......................................................................................609 ADREG00 to ADREG11 (Normal Conversion Result Register 00 to 11)................................................................610 ADREGSP (Highest-priority Conversion Result Register)........................................................................................611 Description of Operations...................................................................................................612 19.4.1 19.4.2 Analog Reference Voltage............................................................................................................................................612 AD Conversion Mode...................................................................................................................................................612 19.4.2.1 19.4.2.2 19.4.3 19.4.4 19.4.5 Normal AD Conversion Highest-priority AD conversion AD Monitor Function....................................................................................................................................................613 Selecting the Input Channel..........................................................................................................................................614 AD Conversion Details.................................................................................................................................................615 19.4.5.1 19.4.5.2 19.4.5.3 19.4.5.4 19.4.5.5 19.4.5.6 19.4.5.7 19.4.5.8 Starting AD Conversion AD Conversion Highest-priority AD conversion requests during normal AD conversion Stopping Repeat Conversion Mode Reactivating normal AD conversion Conversion completion Interrupt generation timings and AD conversion result storage register The way of stopping ADC in the low power consumption mode 20. Flash Memory Operation 20.1 Flash Memory......................................................................................................................623 20.1.1 20.1.2 20.2 Features..........................................................................................................................................................................623 Block Diagram of the Flash Memory Section..............................................................................................................625 Operation Mode...................................................................................................................626 20.2.1 20.2.2 Reset Operation.............................................................................................................................................................627 User Boot Mode (Single chip mode)............................................................................................................................628 20.2.2.1 20.2.2.2 20.2.3 Single Boot Mode..........................................................................................................................................................636 20.2.3.1 20.2.4 20.2.5 20.2.6 (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1-B) Method 2: Transferring a Programming Routine from an External Host (2-A) Using the Program in the On-Chip Boot ROM Configuration for Single Boot Mode............................................................................................................................639 Memory Map.................................................................................................................................................................640 Interface specification....................................................................................................................................................641 xiii 20.2.7 20.2.8 20.2.9 Data Transfer Format....................................................................................................................................................643 Restrictions on internal memories.................................................................................................................................643 Transfer Format for Single Boot Mode commands......................................................................................................643 20.2.9.1 20.2.9.2 20.2.10 RAM Transfer Chip Erase and Protect Bit Erase Operation of Boot Program.........................................................................................................................................646 20.2.10.1 20.2.10.2 20.2.10.3 20.2.10.4 20.2.10.5 20.2.10.6 20.2.11 20.2.12 General Boot Program Flowchart...............................................................................................................................657 USB Boot ...................................................................................................................................................................659 20.2.12.1 20.2.12.2 20.2.13 20.3 RAM Transfer Command Chip and Protection Bit Erase Command Acknowledge Responses Determination of a Serial Operation Mode Password Checksum Calculation Boot Sequence USB Boot Command Descriptor.....................................................................................................................................................................661 On-board Programming of Flash Memory (Rewrite/Erase)...............................................664 20.3.1 Flash Memory................................................................................................................................................................664 20.3.1.1 20.3.1.2 20.3.1.3 20.3.1.4 20.3.1.5 20.3.1.6 20.3.1.7 20.3.1.8 Block Configuration Basic operation Reset (Hardware reset) Commands Flash control/ status register List of Command Sequences Address bit configuration for bus write cycles Flowchart 21. ROM protection 21.1 21.2 21.2.1 21.2.2 21.3 21.3.1 21.3.2 21.4 21.4.1 21.4.2 Outline.................................................................................................................................679 Features................................................................................................................................679 Write/ erase-protection function....................................................................................................................................679 Security function............................................................................................................................................................679 Register................................................................................................................................680 FCFLCS (Flash control register)...................................................................................................................................681 FCSECBIT(Security bit register)..................................................................................................................................682 Writing and erasing.............................................................................................................683 Protection bits................................................................................................................................................................683 Security bit.....................................................................................................................................................................683 22. Port Section Equivalent Circuit Schematic 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 PA0 to 7,PB0 to 7...............................................................................................................685 PC0 to 2, PD0 to 7, PE0 to 7, PF1 to 7, PG0 to 4, PH0 to 4, PI0 to 7.............................685 PJ0 to 7, PK0 to 3...............................................................................................................686 PF0.......................................................................................................................................686 PG5......................................................................................................................................687 X1,X2...................................................................................................................................687 RESET,NMI........................................................................................................................687 BSC......................................................................................................................................688 MODE..................................................................................................................................688 FTEST3..............................................................................................................................688 AVREFH,AVREFL...........................................................................................................688 23. Electrical Characteristics xiv 23.1 23.2 23.3 23.4 23.5 23.6 Absolute Maximum Ratings................................................................................................689 DC Electrical Characteristics (1/3).....................................................................................690 DC Electrical Characteristics (2/3).....................................................................................691 DC Electrical Characteristics (3/3).....................................................................................692 12-bit ADC Electrical Characteristics.................................................................................693 AC Electrical Characteristics..............................................................................................694 23.6.1 23.6.2 AC measurement condition...........................................................................................................................................694 Serial Channel (SIO/UART).........................................................................................................................................694 23.6.2.1 23.6.3 I/O Interface mode Serial Bus Interface (I2C/SIO)......................................................................................................................................697 23.6.3.1 23.6.3.2 23.6.4 I2C Mode Clock-Synchronous 8-Bit SIO mode Synchronous serial Interface (SSP)...............................................................................................................................700 23.6.4.1 23.6.4.2 23.6.4.3 23.6.5 AC measurement conditions SSP SPI mode (Master) SSP SPI mode (Slave) 16-bit timer / event counter...........................................................................................................................................704 23.6.5.1 23.6.5.2 23.6.6 23.6.7 23.6.8 23.6.9 23.6.10 23.6.11 Event Counter Capture External Interrupt...........................................................................................................................................................704 NMI................................................................................................................................................................................705 SCOUT Pin AC Characteristic.....................................................................................................................................705 ADTRG Trigger Input Pin AC Characteristic..............................................................................................................706 USB Timing.................................................................................................................................................................706 External bus interface AC Characteristic....................................................................................................................707 23.6.11.1 23.6.11.2 23.6.12 Debug Communication................................................................................................................................................716 23.6.12.1 23.6.12.2 23.6.13 23.6.14 23.6.15 23.6.16 23.7 Separate Bus mode Multiplex Bus mode SWD Interface JTAG Interface ETM Trace...................................................................................................................................................................717 On chip oscillator........................................................................................................................................................717 External clock input.....................................................................................................................................................717 Flash Memory Characteristics...................................................................................................................................718 Recommended Oscillation Circuit......................................................................................719 23.7.1 23.7.2 Ceramic oscillator..........................................................................................................................................................719 Crystal oscillator............................................................................................................................................................719 23.7.2.1 23.8 23.8.1 Precautions for designing printed circuit board Handling Precaution............................................................................................................720 Power-on sequence........................................................................................................................................................720 24. Package Dimensions xv xvi TMPM366FDXBG/FYXBG/FWXBG TMPM366FDXBG/FYXBG/FWXBG The TMPM366FDXBG/FYXBG/FWXBG is a 32-bit RISC microprocessor series with an ARM Cortex™-M3 microprocessor core. Product Name ROM RAM (FLASH) TMPM366FDXBG 512 Kbyte 64 Kbyte TMPM366FYXBG 256 Kbyte 48 Kbyte TMPM366FWXBG 128 Kbyte 32 Kbyte Package P-TFBGA109-0909-0.65-002 Features of the TMPM366FDXBG/FYXBG/FWXBG are as follows: 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb® -2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ New 32-bit Thumb instructions for improved performance ・ New Thumb mixed 16-/32-bit instruction set can produce faster, more efficient code. b. Both high performance and low power consumption have been achieved. [High performance] ・ A 32-bit multiplication (32×32=32 bit) can be executed with one clock. ・ Division takes between 2 and 12 cycles depending on dividend and devisor [Low power consumption] ・ Optimized design using a low power consumption library ・ Standby function that stops the operation of the micro controller core c. High-speed interrupt response suitable for real-time control ・ An interruptible long instruction. ・ Stack push automatically handled by hardware. 2. On chip program memory and data memory ・ On chip SRAM : 64 Kbyte / 48 Kbyte / 32 Kbyte ・ On chip Flash ROM : 512 Kbyte / 256 Kbyte / 128 Kbyte 3. External bus interface (EBIF) ・ Up to 16Mbytes access area (Program / Data) ・ External data bus (Separate / Multiplex): 8 /16bit bus width ・ Chip select / Wait controller: 2 channels 4. DMA controller (DMAC) : 2 units 4 channels Page 1 2013/6/11 1.1 Features TMPM366FDXBG/FYXBG/FWXBG Transfer can support on chip Memory / Peripheral function / External memory 5. 16-bit timer / event counter (TMRB) : 10 channels ・ 16-bit interval timer mode ・ 16-bit event counter mode ・ 16-bit PPG output (can start 4-channels synchronously) ・ Input capture function 6. Watchdog timer (WDT): 1 channel Watchdog timer generates a reset or a non-maskable interrupt (NMI) 7. Asynchronous serial channel (UART) : 1 channel Supports UART with flow control / supports IrDA1.0 mode 8. Serial channel (SIO/UART): 2 channels Either UART mode or I/O interface mode can be selected (4byte FIFO equipped) 9. Serial bus interface (I2C/SIO): 2 channels Either I2C bus mode or clock-synchronous 8-bit SIO mode can be selected. 10. Synchronous serial port (SSP): 3 channel ・ Communication protocol that includes SPI: 3 types (SPI/SSI/Microwire) ・ Baud rate: Master mode: 6Mbps (max.), Slave mode: 4.0Mbps (max.) 11. USB Device controller : 1channel ・ USB support ・ Supports full communication speed (12Mbps) (dose not support Low Speed). ・ Supports 8 endpoints. End -point 0 : Control 64 bytes × 1-FIFO End -point 1 : Bulk ( Device → Host : IN transfer ) 64 bytes × 2-FIFO End -point 2 : Bulk ( Host → Device : OUT transfer ) 64 bytes × 2-FIFO End -point 3 : Bulk ( Device → Host : IN transfer ) 64 bytes × 2-FIFO End -point 4 : Bulk ( Host → Device : OUT transfer ) 64 bytes × 2-FIFO End -point 5 : Bulk ( Device → Host : IN transfer ) 64 bytes × 2-FIFO End -point 6 : Bulk ( Host → Device : OUT transfer ) 64 bytes × 2-FIFO End -point 7 : Interrupt ( Device → Host : IN transfer ) 64 bytes × 2-FIFO ・ From End-point 1 to 7 can be support 4 transfer modes. 12. 12-bit AD converter (ADC): 12channels ・ Start up with 16-bit timer / Start up with an external trigger input ・ Fixed channel / Channel scan mode ・ Single / repeat mode ・ AD monitoring 2channels ・ Conversion time 1μs (@fsys = 40MHz), 1.67μs (@fsys = 48MHz) 2013/6/11 Page 2 TMPM366FDXBG/FYXBG/FWXBG 13. Interrupt source ・ Internal 50 factors: The order of precedence can be set over 7 levels (except the watchdog timer interrupt). ・ External 10 factors: The order of precedence can be set over 7 levels. 14. Non-maskable interrupt (NMI) Non-maskable interrupt (NMI) is generated by a watchdog timer or a NMI pin. 15. Input/ output ports (PORT): 74 pins I/O pin: 73 pins (One 5V tolerant pin included) Output pin: 1 pin 16. Low power consumption mode IDLE, STOP1, STOP2 17. Clock generator (CG) ・ On chip PLL (6 times or 8 times selectable) ・ Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4, 1/8 or 1/16. 18. Endian Little endian can be supported. 19. Debug interface JTAG / SWD / SWV / TRACE (DATA 4bit) 20. JTAG interface Boundary scan 21. Maximum operating frequency: 48 MHz 22. Operating voltage range 2.7 V to 3.6 V 3.0 V to 3.45 V (when USB is used) 23. Temperature range ・ -40 to 85 degrees (except during Flash writing/ erasing) ・ 0 to 70 degrees (during Flash writing/ erasing) 24. Package P-TFBGA109-0909-0.65-002 (9mm × 9mm, 0.65mm pitch) Page 3 2013/6/11 1.2 Block Diagram 1.2 TMPM366FDXBG/FYXBG/FWXBG Block Diagram Cortex-M3 CPU I/F FLASH I/F RAM I/F BOOTROM I-Code Debug System NVIC AHB-Bus-Matrix D-Code DMAC USB-Device (1ch) Bus Bridge Bus Bridge CG 12-bit ADC (12ch) WDT UART (1ch) APB-Bus I/O-Bus TMRB (10ch) SIO/UART (2ch) EBIF SSP (3ch) I2C/SIO (2ch) PORT A to K Figure 1-1 TMPM366FDXBG/FYXBG/FWXBGBlock Diagram 2013/6/11 Page 4 TMPM366FDXBG/FYXBG/FWXBG 1.3 Pin Layout (Top view) Figure 1-2 shows the pin layout of TMPM366FDXBG/FYXBG/FWXBG. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 D4 㸫 㸫 㸫 㸫 㸫 D10 D11 D12 E1 E2 E3 㸫 㸫 㸫 㸫 㸫 㸫 E10 E11 E12 F1 F2 F3 㸫 㸫 㸫 㸫 㸫 㸫 F10 F11 F12 G1 G2 G3 㸫 㸫 㸫 㸫 㸫 㸫 G10 G11 G12 H1 H2 H3 㸫 㸫 㸫 㸫 㸫 㸫 H10 H11 H12 J1 J2 J3 㸫 㸫 㸫 㸫 㸫 㸫 J10 J11 J12 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L5 L6 L7 L8 L9 L10 L11 L12 M5 M6 M7 M8 M9 M10 M11 M12 M1 M2 L4 M3 M4 Figure 1-2 Pin Layout (BGA109) Page 5 2013/6/11 1.4 Pin names and Functions 1.4 TMPM366FDXBG/FYXBG/FWXBG Pin names and Functions Table 1-1 and Table 1-2 sort the input and output pins of the TMPM366FDXBG/FYXBG/FWXBG by pin or port. 1.4.1 Sorted by Pin Table 1-1 Pin Names and Functions Sorted by Pin (1/7) Type Pin No. Function A1 Function A2 Pin Name Input/ Output Function PK3 I/O I/O port AIN11 I Analog input TB6IN1 I Inputting 16-bit timer / event counter capture trigger PJ7 I/O I/O port AIN07 I Analog input INT9 I External interrupt pin TB0IN1 I Inputting 16-bit timer / event counter capture trigger PJ3 I/O I/O port AIN03 I Analog input PJ0 I/O I/O port AIN00 I Analog input Function A3 Function A4 PS A5 RVDD3 − Power supply pin for internal regulator PS A6 RVSS − GND pin for internal regulator PS A7 DVSSA − GND pin PS A8 DVDD3A − Power supply pin Clock A9 X1 I Connected to a high-speed oscillator or input external clock. PS A10 DVSSC − GND pin Clock A11 X2 O Connected to a high-speed oscillator. PS A12 DVSSC − GND pin PS B1 AVDD3 I PK2 I/O I/O port Function B2 AIN10 I Analog input TB6IN0 I Inputting 16-bit timer / event counter capture trigger PJ4 I/O I/O port AIN04 I Analog input PJ1 I/O I/O port AIN01 I Analog input AVSS I PE7 I/O I/O port INT4 I External interrupt pin A11 O Address bus PE5 I/O I/O port SCL1/SI1 I/O Clock in I2C mode / Data in SIO mode A13 O Address bus Function B3 Function B4 PS B5 Function B6 Function 2013/6/11 B7 Power supply pin for AD converters (note) AVDD3 must be connected to power supply even if A/D converters are not used. GND pin for AD converters (note) AVSS must be connected to GND even if the A/D converters are not used. Page 6 TMPM366FDXBG/FYXBG/FWXBG Table 1-1 Pin Names and Functions Sorted by Pin (2/7) Input/ Output Type Pin No. PS B8 DVDD3A − Function B9 NMI I PS B10 DVSSC − Control B11 MODE I Function B12 RESET I PS C1 AVREFH I PK1 I/O I/O port AIN09 I Analog input INT3 I External interrupt pin TB1IN1 I Inputting 16-bit timer / event counter capture trigger PJ5 I/O I/O port AIN05 I Analog input PJ2 I/O I/O port AIN02 I Analog input AVSS I PE6 I/O I/O port SCK1 I/O Clock in SIO mode A12 O Address bus PE4 I/O I/O port SDA1/SO1 I/O Data in I2C mode / Data in SIO mode A14 O Address bus PD0 I/O I/O port A16 O Address bus TB7OUT O 16-bit timer / event counter output PD1 I/O I/O port A17 O Address bus TB8OUT O 16-bit timer / event counter output PD2 I/O I/O port A18 O Address bus TB9OUT O 16-bit timer / event counter output PE2 I/O I/O port SCLK0 I/O Serial channel clock pin TB2OUT O 16-bit timer / event counter output CTS0 I Serial channel handshake input pin A22 O Address bus Function C2 Function C3 Function C4 PS C5 Function C6 Function Function Function/ Debug Function Function C7 C8 C9 C10 C11 Pin Name Function Power supply pin Non-maskable interrupt (note) With a noise filter (about 30ns (typical value)) GND pin Mode pin (note) MODE pin must be connected to GND. Reset input pin (note) With a pull-up and a noise filter (about 30ns (typical value)) Power supply pin for AD converters (note) AVREFH must be connected to power supply even if A/D converters are not used. GND pin for AD converters (note) AVSS must be connected to GND even if the A/D converters are not used. Page 7 2013/6/11 1.4 Pin names and Functions TMPM366FDXBG/FYXBG/FWXBG Table 1-1 Pin Names and Functions Sorted by Pin (3/7) Type Function PS Function Function Pin No. C12 D1 D2 D3 PS D4 Function D10 Function Function D11 D12 Pin Name Input/ Output Function PE3 I/O I/O port INT5 I External interrupt pin A15 O Address bus TB3OUT O 16-bit timer / event counter output A23 O Address bus AVSS I PK0 I/O I/O port AIN08 I Analog input INT2 I External interrupt pin TB1IN0 I Inputting 16-bit timer / event counter capture trigger PJ6 I/O I/O port AIN06 I Analog input TB0IN0 I Inputting 16-bit timer / event counter capture trigger AVSS I PD3 I/O I/O port A19 O Address bus ADTRG I ADC trigger input PE0 I/O I/O port TXD0 O Serial channel sending serial data A20 O Address bus PE1 I/O GND pin RXD0 I Serial channel receiving serial data A21 O Address bus GND pin for AD converters (note) AVSS must be connected to GND even if the A/D converters are not used. GND pin for AD converters (note) AVSS must be connected to GND even if the A/D converters are not used. Power supply pin for AD converters PS E1 AVREFL I PS E2 AVSS I Control E3 BSC I Boundary scan control pin Function E10 PD4 I/O I/O port SP0DO O SSP DO output PS E11 DVDD3C − Power supply pin for USB PS E12 DVDD3C − Power supply pin for USB PS F1 DVDD3A − Power supply pin PS F2 DVSSA − GND pin PI7 I/O I/O port TRST I Debug pin PD5 I/O I/O port SP0DI I SSP DI input DVSS3C − GND pin for USB Function/ Debug F3 Function F10 PS F11 2013/6/11 (note) AVREFL must be connected to GND even if A/D converters are not used. GND pin for AD converters (note) AVSS must be connected to GND even if the A/D converters are not used. Page 8 TMPM366FDXBG/FYXBG/FWXBG Table 1-1 Pin Names and Functions Sorted by Pin (4/7) Type Pin No. Function F12 Function/ Debug Function/ Debug Function/ Debug G1 G2 G3 Pin Name Input/ Output Function D+ Ι/Ο USB pin (D+) PI2 I/O I/O port TRACECLK O Debug pin PI6 I/O I/O port TDI I Debug pin PI5 I/O I/O port TDO/SWV O Debug pin PD6 I/O I/O port SP0CLK I/O SSP clock input/ output Function G10 PS G11 DVSS3C − GND pin for USB Function G12 D− I/O USB pin (D-) I/O I/O port O Debug pin I/O I/O port O Debug pin PI4 I/O I/O port TMS/SWDIO I/O Debug pin PD7 I/O I/O port SP0FSS I/O SSP FSS input/ output SCOUT O System clock output Function/ Debug Function/ Debug Function/ Debug Function PI0 H1 TRACEDATA1 PI1 H2 H3 H10 TRACEDATA0 PS H11 DVSSA − GND pin PS H12 DVDD3A − Power supply pin I/O I/O port O Debug pin I/O I/O port O Debug pin PI3 I/O I/O port TCK/SWCLK I Debug pin PB7 I/O I/O port D15/AD15 I/O Data bus/Address data bus SP2FSS I/O SSP FSS input/ output A7 O Address bus PB6 I/O I/O port D14/AD14 I/O Data bus/Address data bus SP2CLK I/O SSP clock input/ output A6 O Address bus Function/ Debug Function/ Debug Function Debug Function Function PH0 J1 TRACEDATA2 PH1 J2 J3 J10 J11 TRACEDATA3 Page 9 2013/6/11 1.4 Pin names and Functions TMPM366FDXBG/FYXBG/FWXBG Table 1-1 Pin Names and Functions Sorted by Pin (5/7) Type Function Function Function Function Function Function Function Function Pin No. J12 K1 K2 K3 K4 K5 K6 K7 Function K8 Function K9 Function K10 Function Function 2013/6/11 K11 K12 Pin Name Input/ Output Function PB5 I/O I/O port D13/AD13 I/O Data bus/Address bus SP2DI I SSP DI input A5 O Address bus PH4 I/O I/O port A8 O Address bus INT8 I External interrupt pin DTR2 O Output modem controlling DTR (Data Terminal Ready). PH3 I/O I/O port A9 O Address bus TB5OUT O 16-bit timer / event counter output DSR2 I Modem status signal DSR (Data Set Ready). PH2 I/O I/O port A10 O Address bus TB4OUT O 16-bit timer / event counter output DCD2 I Modem status signal DCD (Data Carrier Detect). PG5 I/O I/O port (5V tolerant input) (note) INT1 I External interrupt pin USBPON I USB connection detection pin (VBUS Detect) PC2 I/O I/O port SCLK1 I/O Serial channel clock pin A0 O Address bus TB0OUT O 16-bit timer / event counter output CTS1 I Serial channel handshake input pin PF2 I/O I/O port WR O Write strobe signal PF5 I/O I/O port CS1 O Chip select output INT7 I External interrupt pin TB5IN1 I Inputting 16-bit timer / event counter capture trigger PF7 I/O I/O port ALE O Address latch enable PA1 I/O I/O port D1/AD1 I/O Data bus/Address data bus PA4 I/O I/O port D4/AD4 I/O Data bus/Address data bus PB2 I/O I/O port D10/AD10 I/O Data bus/Address data bus SP1CLK I/O SSP clock input/ output A2 O Address bus PB4 I/O I/O port D12/AD12 I/O Data bus/Address data bus SP2DO O SSP DO output A4 O Address bus Page 10 TMPM366FDXBG/FYXBG/FWXBG Table 1-1 Pin Names and Functions Sorted by Pin (6/7) Type Function Function Function Function Pin No. L1 L2 L3 L4 Function L5 Function L6 Function L7 Function L8 Function L9 Function L10 Function Function Control L11 L12 M1 Pin Name Input/ Output Function PG2 I/O I/O port SCK0 I/O Clock in SIO mode A5 O Address bus TB3IN1 I Inputting 16-bit timer / event counter capture trigger CTS2 I Output modem control line CTS (Clear To Send) PG3 I/O I/O port INT0 I External interrupt pin A6 O Address bus TB4IN0 I Inputting 16-bit timer / event counter capture trigger RIN2 I Modem status signal RI (Ring Indicator) PG4 I/O I/O port A7 O Address bus TB4IN1 I Inputting 16-bit timer / event counter capture trigger RTS2 O Output modem control line RTS (Request To Send). PC0 I/O I/O port TXD1 O Serial channel sending serial data A2 O Address bus TB2IN0 I Inputting 16-bit timer / event counter capture trigger PF1 I/O I/O port RD O Read strobe signal PF3 I/O I/O port BELL O Byte enable signal as an external 8-bit memory access PF6 I/O I/O port CS0 O Chip select output PA0 I/O I/O port D0/AD0 I/O Data bus/Address data bus PA2 I/O I/O port D2/AD2 I/O Data bus/Address data bus PA5 I/O I/O port D5/AD5 I/O Data bus/Address data bus PB0 I/O I/O port D8/AD8 I/O Data bus/Address data bus SP1DO O SSP DO output A0 O Address bus PB3 I/O I/O port D11/AD11 I/O Data bus/Address data bus SP1FSS I/O SSP FSS input/ output A3 O Address bus FTEST3 − TEST pin (note) TEST pin must be left OPEN. Page 11 2013/6/11 1.4 Pin names and Functions TMPM366FDXBG/FYXBG/FWXBG Table 1-1 Pin Names and Functions Sorted by Pin (7/7) Type Function Function Function Function/ Control Function Pin No. M2 M3 M4 M5 M6 Pin Name Input/ Output Function PG1 I/O I/O port SCL0/SI0 I/O Clock in I2C mode/Data in SIO mode A4 O Address bus TB3IN0 I Inputting 16-bit timer / event counter capture trigger RXD2 I UART receive data. IRIN I Data input pin for IrDA1.0. PG0 I/O I/O port SDA0/SO0 I/O Data in I2C mode/Data in SIO mode A3 O Address bus TXD2 O UART transmission data. IROUT O Data output pin for IrDA1.0. PC1 I/O I/O port RXD1 I Serial channel receiving serial data A1 O Address bus TB2IN1 I Inputting 16-bit timer / event counter capture trigger PF0 O BOOT I TB6OUT O PF4 I/O I/O port BELH O Byte enable signal as an external 8-bit memory access INT6 I External interrupt pin TB5IN0 I Inputting 16-bit timer / event counter capture trigger Output port Setting a boot mode TMPM366FDXBG/FYXBG/FWXBG goes into single boot mode by sampling "Low" at the rising edge of a RESET pin. 16-bit timer / event counter output PS M7 DVSSA − GND pin PS M8 DVDD3A − Power supply pin Function M9 PA3 I/O I/O port D3/AD3 I/O Data bus/Address data bus Function M1 0 PA6 I/O I/O port D6/AD6 I/O Data bus/Address data bus Function M1 1 PA7 I/O I/O port D7/AD7 I/O Data bus/Address data bus PB1 I/O I/O port Function M1 2 D9/AD9 I/O Data bus/Address data bus SP1DI I SSP DI input A1 O Address bus Note:Only when input is enabled, this pin tolerates 5V input. Note that this pin can not be pulled up over the power supply voltage when using as open-drain output. 2013/6/11 Page 12 TMPM366FDXBG/FYXBG/FWXBG 1.4.2 Sorted by Port Table 1-2 Pin Names and Functions Sorted by Port (1/7) PORT Type Pin No. PORT A Function L8 PORT A Function K9 PORT A Function L9 PORT A Function M9 PORT A Function K10 PORT A Function L10 PORT A Function M10 PORT A Function M11 PORT B PORT B PORT B PORT B PORT B PORT B Function Function Function Function Function Function L11 M12 K11 L12 K12 J12 Pin Name Input/ Output Function PA0 I/O I/O port D0/AD0 I/O Data bus/Address data bus PA1 I/O I/O port D1/AD1 I/O Data bus/Address data bus PA2 I/O I/O port D2/AD2 I/O Data bus/Address data bus PA3 I/O I/O port D3/AD3 I/O Data bus/Address data bus PA4 I/O I/O port D4/AD4 I/O Data bus/Address data bus PA5 I/O I/O port D5/AD5 I/O Data bus/Address data bus PA6 I/O I/O port D6/AD6 I/O Data bus/Address data bus PA7 I/O I/O port D7/AD7 I/O Data bus/Address data bus PB0 I/O I/O port D8/AD8 I/O Data bus/Address data bus SP1DO O SSP DO output A0 O Address bus PB1 I/O I/O port D9/AD9 I/O Data bus/Address data bus SP1DI I SSP DI input A1 O Address bus PB2 I/O I/O port D10/AD10 I/O Data bus/Address data bus SP1CLK I/O SSP clock input/ output A2 O Address bus PB3 I/O I/O port D11/AD11 I/O Data bus/Address data bus SP1FSS I/O SSP FSS input/ output A3 O Address bus PB4 I/O I/O port D12/AD12 I/O Data bus/Address data bus SP2DO O SSP DO output A4 O Address bus PB5 I/O I/O port D13/AD13 I/O Data bus/Address bus SP2DI I SSP DI input A5 O Address bus Page 13 2013/6/11 1.4 Pin names and Functions TMPM366FDXBG/FYXBG/FWXBG Table 1-2 Pin Names and Functions Sorted by Port (2/7) PORT PORT B PORT B PORT C PORT C PORT C PORT D PORT D PORT D PORT D Type Function Function Function Function Function Function Function Function Function Pin No. J11 J10 L4 M4 K5 C8 C9 C10 D10 PORT D Function E10 PORT D Function F10 PORT D Function G10 PORT D Function H10 2013/6/11 Pin Name Input/ Output Function PB6 I/O I/O port D14/AD14 I/O Data bus/Address data bus SP2CLK I/O SSP clock input/ output A6 O Address bus PB7 I/O I/O port D15/AD15 I/O Data bus/Address data bus SP2FSS I/O SSP FSS input/ output A7 O Address bus PC0 I/O I/O port TXD1 O Serial channel sending serial data A2 O Address bus TB2IN0 I Inputting 16-bit timer / event counter capture trigger PC1 I/O I/O port RXD1 I Serial channel receiving serial data A1 O Address bus TB2IN1 I Inputting 16-bit timer / event counter capture trigger PC2 I/O I/O port SCLK1 I/O Serial channel clock pin A0 O Address bus TB0OUT O 16-bit timer / event counter output CTS1 I Serial channel handshake input pin PD0 I/O I/O port A16 O Address bus TB7OUT O 16-bit timer / event counter output PD1 I/O I/O port A17 O Address bus TB8OUT O 16-bit timer / event counter output PD2 I/O I/O port A18 O Address bus TB9OUT O 16-bit timer / event counter output PD3 I/O I/O port A19 O Address bus ADTRG I ADC trigger input PD4 I/O I/O port SP0DO O SSP DO output PD5 I/O I/O port SP0DI I SSP DI input PD6 I/O I/O port SP0CLK I/O SSP clock input/ output PD7 I/O I/O port SP0FSS I/O SSP FSS input/ output SCOUT O System clock output Page 14 TMPM366FDXBG/FYXBG/FWXBG Table 1-2 Pin Names and Functions Sorted by Port (3/7) PORT Type Pin No. PORT E Function D11 PORT E PORT E PORT E PORT E PORT E PORT E PORT E PORT F Function Function Function Function Function Function Function Function/ Control D12 C11 C12 C7 B7 C6 B6 M5 Pin Name Input/ Output Function PE0 I/O I/O port TXD0 O Serial channel sending serial data A20 O Address bus PE1 I/O GND pin RXD0 I Serial channel receiving serial data A21 O Address bus PE2 I/O I/O port SCLK0 I/O Serial channel clock pin TB2OUT O 16-bit timer / event counter output CTS0 I Serial channel handshake input pin A22 O Address bus PE3 I/O I/O port INT5 I External interrupt pin A15 O Address bus TB3OUT O 16-bit timer / event counter output A23 O Address bus PE4 I/O I/O port SDA1/SO1 I/O Data in I2C mode/Data in SIO mode A14 O Address bus PE5 I/O I/O port SCL1/SI1 I/O Clock in I2C mode/Data in SIO mode A13 O Address bus PE6 I/O I/O port SCK1 I/O Clock in SIO mode A12 O Address bus PE7 I/O I/O port INT4 I External interrupt pin A11 O Address bus PF0 I/O I/O port TB6OUT O 16-bit timer / event counter output BOOT I Setting a boot mode TMPM366FDXBG/FYXBG/FWXBG goes into single boot mode by sampling "Low" at the rising edge of a RESET pin. PORT F Function L5 PORT F Function K6 PORT F Function L6 PORT F Function M6 PF1 I/O I/O port RD O Read strobe signal PF2 I/O I/O port WR O Write strobe signal PF3 I/O I/O port BELL O Byte enable signal as an external 8-bit memory access PF4 I/O I/O port BELH O Byte enable signal as an external 8-bit memory access INT6 I External interrupt pin TB5IN0 I Inputting 16-bit timer / event counter capture trigger Page 15 2013/6/11 1.4 Pin names and Functions TMPM366FDXBG/FYXBG/FWXBG Table 1-2 Pin Names and Functions Sorted by Port (4/7) PORT PORT F Type Function Pin No. K7 PORT F Function L7 PORT F Function K8 PORT G PORT G PORT G PORT G PORT G PORT G PORT H PORT H PORT H 2013/6/11 Function Function Function Function Function Function Function/ Debug Function/ Debug Function M3 M2 L1 L2 L3 K4 Pin Name I/O I/O port CS1 O Chip select output INT7 I External interrupt pin TB5IN1 I Inputting 16-bit timer / event counter capture trigger PF6 I/O I/O port CS0 O Chip select output PF7 I/O I/O port ALE O Address latch enable (output disable for noise-reduction can be selectalbe) PG0 I/O I/O port SDA0/SO0 I/O Data in I2C mode/Data in SIO mode A3 O Address bus TXD2 O UART transmission data. IROUT O Data output pin for IrDA1.0. PG1 I/O I/O port SCL0/SI0 I/O Clock in I2C mode/Data in SIO mode A4 O Address bus TB3IN0 I Inputting 16-bit timer / event counter capture trigger RXD2 I UART receive data. IRIN I Data input pin for IrDA1.0. PG2 I/O I/O port SCK0 I/O Clock in SIO mode A5 O Address bus TB3IN1 I Inputting 16-bit timer / event counter capture trigger CTS2 I Output modem control line CTS (Clear To Send) PG3 I/O I/O port INT0 I External interrupt pin A6 O Address bus TB4IN0 I Inputting 16-bit timer / event counter capture trigger RIN2 I Modem status signal RI (Ring Indicator) PG4 I/O I/O port A7 O Address bus TB4IN1 I Inputting 16-bit timer / event counter capture trigger RTS2 O Output modem control line RTS (Request To Send). PG5 I/O I/O port (5V tolerant input) (note) INT1 I External interrupt pin USBPON I USB connection detection pin (VBUS Detect) I/O I/O port O Debug pin I/O I/O port O Debug pin PH2 I/O I/O port A10 O Address bus TB4OUT O 16-bit timer / event counter output DCD2 I Modem status signal DCD (Data Carrier Detect). TRACEDATA2 PH1 J2 K3 Function PF5 PH0 J1 Input/ Output TRACEDATA3 Page 16 TMPM366FDXBG/FYXBG/FWXBG Table 1-2 Pin Names and Functions Sorted by Port (5/7) PORT PORT H PORT H PORT I PORT I PORT I PORT I PORT I PORT I PORT I PORT I Type Function Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Function/ Debug Pin No. K2 K1 G1 J3 H3 G3 G2 F3 Function A4 PORT J Function B4 PORT J Function C4 PORT J Function A3 PORT J Function B3 PORT J Function C3 PORT J Function D3 Function A2 Function I/O I/O port A9 O Address bus TB5OUT O 16-bit timer / event counter output DSR2 I Modem status signal DSR (Data Set Ready). PH4 I/O I/O port A8 O Address bus INT8 I External interrupt pin DTR2 O Output modem controlling DTR (Data Terminal Ready). I/O I/O port O Debug pin I/O I/O port O Debug pin PI2 I/O I/O port TRACECLK O Debug pin PI3 I/O I/O port TCK/SWCLK I Debug pin PI4 I/O I/O port TMS/SWDIO I/O Debug pin PI5 I/O I/O port TDO/SWV O Debug pin PI6 I/O I/O port TDI I Debug pin PI7 I/O I/O port TRST I Debug pin PJ0 I/O I/O port AIN00 I Analog input PJ1 I/O I/O port AIN01 I Analog input PJ2 I/O I/O port AIN02 I Analog input PJ3 I/O I/O port AIN03 I Analog input PJ4 I/O I/O port AIN04 I Analog input PJ5 I/O I/O port AIN05 I Analog input PJ6 I/O I/O port AIN06 I Analog input TB0IN0 I Inputting 16-bit timer / event counter capture trigger PJ7 I/O I/O port AIN07 I Analog input INT9 I External interrupt pin TB0IN1 I Inputting 16-bit timer / event counter capture trigger TRACEDATA1 PI1 H2 Input/ Output PH3 PI0 H1 PORT J PORT J Pin Name TRACEDATA0 Page 17 2013/6/11 1.4 Pin names and Functions TMPM366FDXBG/FYXBG/FWXBG Table 1-2 Pin Names and Functions Sorted by Port (6/7) PORT PORT K PORT K PORT K PORT K Type Function Function Function Function Pin No. D2 C2 B2 A1 Pin Name Input/ Output Function PK0 I/O I/O port AIN08 I Analog input INT2 I External interrupt pin TB1IN0 I Inputting 16-bit timer / event counter capture trigger PK1 I/O I/O port AIN09 I Analog input INT3 I External interrupt pin TB1IN1 I Inputting 16-bit timer / event counter capture trigger PK2 I/O I/O port AIN10 I Analog input TB6IN0 I Inputting 16-bit timer / event counter capture trigger PK3 I/O I/O port AIN11 I Analog input TB6IN1 I Inputting 16-bit timer / event counter capture trigger - Function F12 D− I/O USB DP(D+) pin - Function G12 D+ I/O USB DM(D-) pin - Control B12 RESET I - Function B9 NMI I - Control B11 MODE I - Control M1 FTEST3 − - Control E3 BSC I Boundary scan control pin - Clock A9 X1 I Connected to a high-speed oscillator or input external clock. - Clock A11 X2 O Connected to a high-speed oscillator. - PS F1 DVDD3A − Power supply pin - PS M8 DVDD3A − Power supply pin - PS H12 DVDD3A − Power supply pin - PS A8 DVDD3A − Power supply pin - PS B8 DVDD3A − Power supply pin - PS F2 DVSSA − GND pin - PS M7 DVSSA − GND pin - PS H11 DVSSA − GND pin - PS A7 DVSSA − GND pin 2013/6/11 Reset input pin (note) With a pull-up and a noise filter (about 30ns (typical value)) Non-maskable interrupt (note) With a noise filter (about 30ns (typical value)) Mode pin (note) MODE pin must be connected to GND. TEST pin (note) TEST pin must be left OPEN. Page 18 TMPM366FDXBG/FYXBG/FWXBG Table 1-2 Pin Names and Functions Sorted by Port (7/7) Input/ Output PORT Type Pin No. - PS A5 RVDD3 − Power supply pin for internal regulator - PS A6 RVSS − GND pin for internal regulator - PS A10 DVSSC − GND pin - PS E12 DVDD3C − Power supply pin for USB - PS G11 DVSS3C − GND pin for USB - PS C1 AVREFH I - PS E1 AVREFL I - PS B1 AVDD3 I - PS D1 AVSS I - PS A12 DVSSC − - PS B5 AVSS I - PS B10 DVSSC − - PS C5 AVSS I - PS D4 AVSS I - PS E2 AVSS I - PS E11 DVDD3C − Power supply pin for USB - PS F11 DVSS3C − GND pin for USB Pin Name Function Power supply pin for AD converters. (note) AVREFH must be connected to power supply even if A/D converters are not used. Power supply pin for AD converters. (note) AVREFL must be connected to GND even if A/D converters are not used. Power supply pin for AD converters. (note) AVDD3 must be connected to power supply even if A/D converters are not used. GND pin for AD converters. (note) AVSS must be connected to GND even if the A/D converters are not used. GND pin GND pin for AD converters. (note) AVSS must be connected to GND even if the A/D converters are not used. GND pin GND pin for AD converters. (note) AVSS must be connected to GND even if the A/D converters are not used. GND pin for AD converters. (note) AVSS must be connected to GND even if the A/D converters are not used. GND pin for AD converters. (note) AVSS must be connected to GND even if the A/D converters are not used. Note:Only when input is enabled, this pin tolerates 5V input. Note that this pin can not be pulled up over the power supply voltage when using as open-drain output. Page 19 2013/6/11 1.5 Pin Numbers and Power Supply Pins 1.5 TMPM366FDXBG/FYXBG/FWXBG Pin Numbers and Power Supply Pins Table 1-3 Pin Numbers and Power Supplies Power supply Voltage range DVDD3A 2.7 to 3.6V Pin name A8,B8,F1,H12, M8 PA,PB,PC,PD,PE,PF,PG, PH, PI, X1, X2, FTEST3, RESET, NMI, MODE, BSC AVDD3 (When USB is used : B1 PJ, PK RVDD3 3.0 to 3.45 V) A5 − E11,E12 D+,D− DVDD3C 2013/6/11 Pin No. Page 20 TMPM366FDXBG/FYXBG/FWXBG 2. Processor Core The TX03 series has a high-performance 32-bit processor core (the ARM Cortex-M3 processor core). For information on the operations of this processor core, please refer to the "Cortex-M3 Technical Reference Manual" issued by ARM Limited.This chapter describes the functions unique to the TX03 series that are not explained in that document. 2.1 Information on the processor core The following table shows the revision of the processor core in the TMPM366FDXBG/FYXBG/FWXBG. Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M series processors" in the following URL: http://infocenter.arm.com/help/index.jsp 2.2 Product Name Core Revision TMPM366FDXBG/ FYXBG/FWXBG r2p0 Configurable Options The Cortex-M3 core has optional blocks. The optional blocks of the revision r2p0 are ETM™, MPU and WIC. The following table shows the configurable options in the TMPM366FDXBG/FYXBG/FWXBG. Implementation Configurable Options Two literal comparators FPB Six instruction comparators DWT Four comparators ITM Present MPU Absent ETM Present AHB-AP Present AHB Trace Macrocell Interface Absent TPIU Present WIC Absent Debug Port JTAG / Serial wire Page 21 2013/6/11 2. 2.3 Processor Core Exceptions/ Interruptions 2.3 TMPM366FDXBG/FYXBG/FWXBG Exceptions/ Interruptions Exceptions and interruptions are described in the following section. 2.3.1 Number of Interrupt Inputs The number of interrupt inputs can optionally be defined from 1 to 240 in the Cortex-M3 core. TMPM366FDXBG/FYXBG/FWXBG has 60 interrupt inputs. The number of interrupt inputs is reflected in bit of NVIC register. In this product, if read bit, 0x00 is read out. 2.3.2 Number of Priority Level Interrupt Bits The Cortex-M3 core can optionally configure the number of priority level interrupt bits from 3 bits to 8 bits. TMPM366FDXBG/FYXBG/FWXBG has 3 priority level interrupt bits. The number of priority level interrupt bits is used for assigning a priority level in the interrupt priority registers and system handler priority registers. 2.3.3 SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. For the detail of SysTick exception, refer to the section of "SysTick" in the exception and the register of SysTick in the NVIC register. 2.3.4 SYSRESETREQ The Cortex-M3 core outputs SYSRESETREQ signal when bit of Application Interrupt and Reset Control Register are set. TMPM366FDXBG/FYXBG/FWXBG provides the same operation when SYSRESETREQ signal are output. 2.3.5 LOCKUP When irreparable exception generates, the Cortex-M3 core outputs LOCKUP signal to show a serious error included in software. TMPM366FDXBG/FYXBG/FWXBG does not use this signal. To return from LOCKUP status, it is necessary to use non-maskable interruput (NMI) or reset. 2.3.6 Auxiliary Fault Status register The Cortex-M3 core provides auxiliary fault status registers to supply additional system fault information to software. However, TMPM366FDXBG/FYXBG/FWXBG is not defined this function. If auxiliary fault status register is read, always "0x0000_0000" is read out. 2013/6/11 Page 22 TMPM366FDXBG/FYXBG/FWXBG 2.4 Events The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV instruction execution. If an event is input, the core returns from low-power consumption mode caused by WFE instruction. TMPM366FDXBG/FYXBG/FWXBG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 Power Management The Cortex-M3 core provides power management system which uses SLEEPING signal and SLEEPDEEP signal. SLEEPDEEP signals are output when bit of System Control Register is set. These signals are output in the following circumstances: -Wait-For-Interrupt (WFI) instruction execution -Wait-For-Event (WFE) instruction execution -the timing when interrupt-service-routine (ISR) exit in case that bit of System Control Register is set. TMPM366FDXBG/FYXBG/FWXBG does not use SLEEPDEEP signal so that bit must not be set. And also event signal is not used so that please do not use WFE instruction. For detail of power management, refer to the Chapter "Clock/Mode control." 2.6 Exclusive access In Cortex-M3 core, the DCode bus system supports exclusive access. However TMPM366FDXBG/FYXBG/ FWXBG does not use this function. Page 23 2013/6/11 2. 2.6 Processor Core Exclusive access 2013/6/11 TMPM366FDXBG/FYXBG/FWXBG Page 24 TMPM366FDXBG/FYXBG/FWXBG 3. Debug Interface 3.1 Specification Overview TMPM366FDXBG/FYXBG/FWXBG contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell™(ETM) unit for instruction trace output.Trace data is output to the dedicated pins(TRACEDATA[3:0], SWV) for the debugging via the on-chip Trace Port Interface Unit (TPIU). For details about SWJ-DP, ETM and TPIU, refer to "Cortex-M3 Technical Reference Manual" . 3.2 SWJ-DP SWJ-DP supports the Serial Wire Debug Port (SWCLK, SWDIO) and the JTAG Debug Port (TDI, TDO, TMS, TCK, TRST). 3.3 ETM ETM supports four data signal pins (TRACEDATA[3:0]), one clock signal pin (TRACECLK) and trace output from Serial Wire Viewer (SWV). Page 25 2013/6/11 3. Debug Interface 3.4 Pin Functions 3.4 TMPM366FDXBG/FYXBG/FWXBG Pin Functions The debug interface pins can also be used as general-purpose ports. The PI3 and PI4 pins are shared between the JTAG debug port function and the Serial Wire Debug Port function. The PI5 pin is shared between the JTAG debug port function and the SWV trace output function. Table 3-1 SWJ-DP,ETM Debug Functions Generalpurpose SWJ-DP Pin Name JTAG Debug Function SW Debug Function Port Name I/O Explanation I/O Explanation TMS / SWDIO PI4 Input JTAG Test Mode Selection I/O Serial Wire Data Input/Output TCK / SWCLK PI3 Input JTAG Test Check Input Serial Wire Clock TDO / SWV PI5 Output JTAG Test Data Output (Output) (Note) (Serial Wire Viewer Output) TDI PI6 Input JTAG Test Data Input - - JTAG Test RESET - - TRST PI7 Input TRACECLK PI2 Output TRACE Clock Output TRACEDATA0 PI1 Output TRACE DATA Output0 TRACEDATA1 PI0 Output TRACE DATA Output1 TRACEDATA2 PH0 Output TRACE DATA Output2 TRACEDATA3 PH1 Output TRACE DATA Output3 Note:When SWV function is enabled. After reset, PI3, PI4 and , PI5, PI6 and PI7 pins are configured as debug port function pins. The functions of other debug interface pins need to be programmed as required. When using a low power consumption mode, take note of the following points. Note:If PI4 and PI5 are configured as TMS/SWDIO and TDO/SWV, output continues to be enabled even in STOP1 mode regardless of the setting of the CGSTBYCR bit. Table 3-2 summarizes the debug interface pin and related port settings after reset. Table 3-2 Debug Interface Pins and Related Port Settings after Reset Port Name (Bit Name) Value of Related port settings after reset Debug Function Function Input Output Pull-up Pull-down (PxFR) (PxIE) (PxCR) (PxPUP) (PxPDN) − PI4 TMS/SWDIO 1 1 1 1 PI3 TCK/SWCLK 1 1 0 − 1 PI5 TDO/SWV 1 0 1 0 − PI6 TDI 1 1 0 1 − PI7 TRST 1 1 0 1 − PI2 TRACECLK 0 0 0 0 − PI1 TRACEDATA0 0 0 0 0 − PI0 TRACEDATA1 0 0 0 0 − PH0 TRACEDATA2 0 0 0 0 − PH1 TRACEDATA3 0 0 0 0 − − : Don’t care 2013/6/11 Page 26 TMPM366FDXBG/FYXBG/FWXBG 3.5 Peripheral Functions in Halt Mode When the Cortex-M3 core enters in the halt mode, the watchdog-timer (WDT) automatically stops. Other peripheral functions continue to operate. 3.6 Connection with a Debug Tool 3.6.1 About connection with debug tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are connected with external pull-up or pull-down, please pay attention to input level. Note 1: Ensure that to mesure the power-consumption with debug tool connected in STOP1/STOP2 mode is prohibitted. Note 2: Ensure that not to matain STOP2 mode for a long time with debug tool connected. 3.6.2 Important points of using debug interface pins used as general-purpose ports When setting a debugging interface terminal to a general-purpose port by a user's program after reset release,after that the control from a debugging tool is impossible. Please note that it is necessary to prepare for the structure which changes the general-purpose port to the debugging interface function by some kind of methods to connect a debugging tool again.. Table 3-3 Example Table of using debug interface pins Debug interface pins TDO / TCK / TMS / TRACE TRACE SWV SWCLK SWDIO DATA[3:0] CLK ο ο ο ο × × ο ο ο ο × × TRST TDI JTAG+SW (After reset) ο JTAG+SW (without TRST) × JTAG+TRACE ο ο ο ο ο ο ο SW × × × ο ο × × SW+SWV × × ο ο ο × × Debugging function disabled × × × × × × × ο : Enabled × : Disabled (Usable as general-purpose port) Page 27 2013/6/11 3. 3.6 Debug Interface Connection with a Debug Tool 2013/6/11 TMPM366FDXBG/FYXBG/FWXBG Page 28 TMPM366FDXBG/FYXBG/FWXBG 4. JTAG Interface 4.1 Overview The TMPM366FDXBG/FYXBG/FWXBG provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) specifications and uses the industry-standard JTAG protocol (IEEE Standard 1149.1・ 1990 ). This chapter describes the JTAG interface, with the descriptions of boundary scan and the pins and signals used by the interface. 1. JTAG standard version IEEE Standard 1149.1・1990 (Includes IEEE Standard 1149.1a・1993) 2. JTAG instructions Standard instructions (BYPASS, SAMPLE/PRELOAD, EXTEST) HIGHZ instruction CLAMP instruction However, the SAMPLE/RELOAD instruction doesn't function because internal circuit reset starts as for TMPM366FDXBG/FYXBG/FWXBG while JTAG is operating. 3. IDCODE Not available 4. Pins a. b. c. d. e. f. g. excluded from boundary scan register (BSR) Oscillator circuit pins (X1, X2) DAC pin (DA0, DA1) JTAG control pins (BSC) Power supply/GND pins (including reference supply pin for ADC) TEST pins (FTEST3) Function pins (RESET) Control pins (MODE, ) Note:As for PF0 pin is always pull-up, the pin is output high-level while in HIGHZ instruction. Note:Please note the input level to the analog input pins. Page 29 2013/6/11 4. 4.2 JTAG Interface Signal Summary and Connection Example 4.2 TMPM366FDXBG/FYXBG/FWXBG Signal Summary and Connection Example The JTAG interface signals are listed below. - TDI JTAG serial data input - TDO JTAG serial data output - TMS JTAG test mode select - TCK JTAG serial clock input - TRST JTAG test reset input - BSC ICE/JTAG test select input (compatible with the Enable signal) 0: ICE, 1: JTAG The TMPM366FDXBG/FYXBG/FWXBG supports debugging by connecting the JTAG interface with a JTAGcompliant development tool. For information about debugging, refer to the specification of the development tool used. TDI TDO JTAG TOOL TMS TCK BSC TRST Figure 4-1 Example of connection with a JTAG development tool Operation mode Mode Setting Pin (BSC) Set this pin to 0 except for Boundary Scan Mode. 0 The TMPM366FDXBG/FYXBG/FWXBG operates as regular Debug Mode. Note: Debugging is not available if the internal BOOT is running. 1 2013/6/11 The TMPM366FDXBG/FYXBG/FWXBG operates in Boundary Scan Mode. Page 30 TMPM366FDXBG/FYXBG/FWXBG 4.3 Outline With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided component mounting on printed-circuit boards (PCBs), and set-in recesses, in-circuit tests that depend upon physical contact like the connection of the internal board and chip has become more and more difficult to use. The more ICs have become complex, the larger and more difficult the test program became. As one of the solutions, boundary-scan circuits started to be developed. A boundary-scan circuit is a series of shift register cells placed between the pins and the internal circuitry of the IC to which the said pins are connected. Normally, these boundary-scan cells are bypassed; when the IC enters test mode, however, the scan cells can be directed by the test program to pass data along the shift register path and perform various diagnostic tests. To accomplish this, the tests use the five signals, TCK, TMS, TDI, TDO and TRST. The JTAG boundary-scan mechanism (hereinafter referred to as JTAG mechanism in the chapter) allows testing of the connections between the processor, the printed circuit board to which it is attached, and the other components on the circuit board. The JTAG mechanism cannot test the processor alone. 4.4 JTAG Controller and Registers The processor contains the following JTAG controller and registers. ・ ・ ・ ・ ・ Instruction register Boundary scan register Bypass register Device identification register Test Access Port (TAP) controller JTAG basically operates to monitor the TMS input signal with the TAP controller state machine. When the monitoring starts, the TAP controller determines the test functionality to be implemented. This includes both loading the JTAG instruction register (IR) and beginning a serial data scan through a data register (DR), as shown in Table 4-1. As the data is scanned, the state of the TMS pin signals each new data word and indicates the end of the data stream. The data register is selected according to the contents of the instruction register. Page 31 2013/6/11 4. 4.5 JTAG Interface Instruction Register 4.5 TMPM366FDXBG/FYXBG/FWXBG Instruction Register The JTAG instruction register includes four shift register-based cells. This register is used to select the test to be performed and/or the test data register to be accessed. As listed in Table 4-1, this instruction codes select either the boundary scan register or the bypass register. Table 4-1 JTAG Instruction Register Bit Configuration Instruction code Instruction Selected data register 0000 EXTEST Boundary scan register 0001 SAMPLE/PRELOAD Boundary scan register 0100 to 1110 Reserved Reserved 0010 HIGHZ Bypass register 0011 CLAMP Bypass register 1111 BYPASS Bypass register (MSB to LSB) Figure 4-2 shows the format of the instruction register. 3 2 MSB 1 0 LSB Figure 4-2 Instruction register The instruction code is shifted out to the instruction register from the LSB. Bypass Register LSB MSB TDI TDO Figure 4-3 Instruction Register Shift Direction The bypass register is 1 bit wide. When the TAP controller is in the Shift-DR (bypass) state, the data on the TDI pin is shifted into the bypass register, and the bypass register output shifts to the data out on the TDO output pin. In essence, the bypass register is an alternative route which allows bypassing of board-level devices in the serial boundary-scan chain, which are not required for a specific test. The logical location of the bypass register in the boundary-scan chain is shown in Figure 4-4. Use of the bypass register speeds up access to the boundary scan register in the IC that remains active in the board-level test data path. 2013/6/11 Page 32 TMPM366FDXBG/FYXBG/FWXBG TDI Bypass Register User’s Board Input to user’s board Output from user’s board TDO TDO TDI TDI TDO TDO TDI TDI TDO : IC package Boundary scan register pad cell Figure 4-4 Bypass Register Operation 4.6 Boundary Scan Register The boundary scan register provides all the inputs and outputs of the TMPM366FDXBG/FYXBG/FWXBG processor except some analog outputs and control signals. The pins of the TMPM366FDXBG/FYXBG/FWXBG allow any pattern to be driven by scanning the data into the boundary scan register in the Shift-DR state. Incoming data to the processor is examined by enabling the boundary scan register and shifting the data when the BSR is in the Capture-DR state. The boundary scan register is a single, 231-bit-wide, shift register-based path containing cells connected to the input and output pads on the TMPM366FDXBG/FYXBG/FWXBG. The TDI input is loaded to the LSB of the boundary scan register. The MSB of the boundary scan register is shifted out on the TDO output. Page 33 2013/6/11 4. 4.7 JTAG Interface Test Access Port (TAP) 4.7 TMPM366FDXBG/FYXBG/FWXBG Test Access Port (TAP) The Test Access Port (TAP) consists of the five signal pins: TRST, TDI, TDO, TMS and TCK. These pins control a test by communicating the serial test data and instructions. As Figure 4-5 shows, data is serially scanned into one of the three registers (instruction register, bypass register or boundary scan register) on the TDI pin, or it is scanned out from one of these three registers on the TDO pin. The TMS input controls the state transitions of the main TAP controller state machine. The TCK input is a special test clock that allows serial JTAG data to be shifted synchronously, independent of any chip-specific or system clocks. TCK TMS and TDI are sampled on the rising edge of TCK. TDO is sampled on the falling edge of TCK. Data is scanned out serially. Data is scanned in serially. 3 0 3 0 Instruction register Instruction register 0 0 Bypass register 115 Bypass register TDI pin 0 TMS pin Boundary scan register 115 TDO pin 0 Boundary scan register Figure 4-5 JTAG Test Access Port Data on the TDI and TMS pins are sampled on the rising edge of the TCK input clock signal. Data on the TDO pin changes on the falling edge of the TCK clock signal. 4.8 TAP Controller The processor incorporates the 16-state TAP controller stipulated in the IEEE JTAG specification. 4.9 Resetting the TAP Controller The TAP controller state machine can be put into the Reset state by the following method. Assertion of the TRST signal input (low) resets the TAP controller. After the processor reset state is released, keep the TMS input signal asserted through five consecutive rising edges of TCK input. Keeping TMS asserted maintains the Reset state. 2013/6/11 Page 34 TMPM366FDXBG/FYXBG/FWXBG 4.10 State Transitions of the TAP Controller The state transition diagram of the TAP controller is shown in Figure 4-6. Each arrow between states is labeled with a 1 or 0, indicating the logic value of TMS that must be set up before the rising edge of TCK to cause the transition. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR-Scan 1 Select-IR-Scan 0 0 Capture-DR Capture-IR 0 0 0 Shift-DR 0 Shift-IR 1 1 1 Exit 1 -DR 1 Exit 1 -IR 0 0 0 Pause-DR 0 Pause-IR 1 1 Exit 2 -DR Exit 2 -IR 1 1 Update-DR 1 1 Update-IR 0 1 0 Figure 4-6 TAP Controller State Transition Diagram The following paragraphs describe each of the controller states. The left column in Figure 4-6 is the data column, and the right column is the instruction column. The data column and instruction column reference the data register (DR) and the instruction register (IR), respectively. ・ Test-Logic-Reset When the TAP controller is in the Reset state, the device identification register is selected by default. The MSB of the boundary scan register is cleared to 0 which disables the outputs. The TAP controller remains in this state while TMS is high. If TMS is held low while the TAP controller is in this state, then the controller moves to the Run-Test/Idle state. ・ Run-Test/Idle In the Run-Test/Idle state, the IC is put in test mode only when certain instructions such as a built-in self test (BIST) instruction are present. For instructions that do not cause any activities in this state, all test data registers selected by the current instruction retain their previous states. The TAP controller remains in this state while TMS is held low. When TMS is held high, the controller moves to the Select-DR-Scan state. ・ Select-DR-Scan This is a temporary controller state. Here, the IC does not execute any specific functions. If TMS is held low when the TAP controller is in this state, the controller moves to the Capture-DR state. If TMS is held high, the controller moves to the Select-IR-Scan state. ・ Select-IR-Scan This is a temporary controller state. Here, the IC does not execute any specific functions. If TMS is held low when the TAP controller is in this state, the controller moves to the Capture-IR state. IF TMS is held high, the controller returns to the Test-Logic-Reset state. Page 35 2013/6/11 4. JTAG Interface 4.10 State Transitions of the TAP Controller TMPM366FDXBG/FYXBG/FWXBG ・ Capture-DR In this state, if the test data register selected by the current instruction has parallel inputs, then data is parallel-loaded into the shift portion of the data register. If the test data register does not have parallel inputs, or if data needs not be loaded into the selected data register, then the data register retains its previous state. If TMS is held low when the TAP controller is in this state, the controller moves to the Shift-DR state. If TMS is held high, the controller moves to the Exit 1-DR state. ・ Shift-DR In this controller state, the test data register connected between TDI and TDO shifts data out serially. When the TAP controller is in this state, then it remains in the Shift-DR state if TMS is held low, or moves to the Exit 1-DR state if TMS is held high. ・ Exit 1-DR This is a temporary controller state. If TMS is held low when the TAP controller is in this state, the controller moves to the Pause-DR state. If TMS is held high, the controller moves to the Update-DR state. ・ Pause-DR This state allows the shifting of the data register selected by the instruction register to be temporarily suspended. Both the instruction register and the data register retain their current states. When the TAP controller is in this state, then it remains in the Pause-DR state if TMS is held low, or moves to the Exit 2-DR state if TMS is held high. ・ Exit 2-DR This is a temporary controller state. When the TAP controller is in this state, it returns to the Shift-DR state if TMS is held low, or moves on to the Update-DR state if TMS is held high. ・ Update-DR In this state, data is latched, on the rising edge of TCK, onto the parallel outputs of the data registers from the shift register path. The data held at the parallel output does not change while data is shifted in the associated shift register path. When the TAP controller is in this state, it moves to either the Run-Test/Idle state if TMS is held low, or the Select-DR-Scan state if TMS is held high. ・ Capture-IR In this state, data is parallel-loaded into the instruction register. The data to be loaded is 0y0001. The Capture-IR state is used for testing the instruction register. Faults in the instruction register, if any, may be detected by shifting out the loaded data. When the TAP controller is in this state, it moves to either the Shift-IR state if TMS is held low, or the Exit 1-IR state if TMS is high. ・ Shift-IR In this state, the instruction register is connected between TDI and TDO and shifts the captured data toward its serial output on the rising edge of TCK. When the TAP controller is in this state, it remains in the Shift-IR state if TMS is low, or moves to the Exit 1-IR state if TMS is high. ・ Exit 1-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Pause-IR state if TMS is held low, or the Update-IR state if TMS is held high. 2013/6/11 Page 36 TMPM366FDXBG/FYXBG/FWXBG ・ Pause-IR This state allows the shifting of the instruction register to be temporarily suspended. Both the instruction register and the data register retain their current states. When the TAP controller is in this state, it remains in the Pause-IR state if TMS is held low, or moves to the Exit 2-IR state if TMS is held high. ・ Exit 2-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Shift-IR state if TMS is held low, or the Update-IR state if TMS is held high. ・ Update-IR This state allows the instruction previously shifted into the instruction register to be output in parallel on the rising edge of TCK. Then it becomes the current instruction, setting a new operational mode. When the TAP controller is in this state, it moves to either the Run-Test/Idle state if TMS is low, or the Select-DR-Scan state if TMS is high. Page 37 2013/6/11 4. JTAG Interface 4.11 Boundary Scan Order 4.11 TMPM366FDXBG/FYXBG/FWXBG Boundary Scan Order The below table shows the boundary scan order with respect to the processor signals. TDI → 1 (PK3)→ 2(PK2)→ − →69(PI1)→70(PI2)→TDO Table 4-2 JTAG Scan Order of the TMPM366FDXBG/FYXBG/FWXBG Processor Pins No. Pin Name No. Pin Name No. Pin Name No. Pin Name TDI 2013/6/11 1 PK3 21 PE0 41 PA4 61 PG4 2 PK2 22 PD0 42 PA3 62 PG5 3 PK1 23 PD1 43 PA2 63 PH4 4 PK0 24 PD2 44 PA1 64 PH3 5 PJ7 25 PD3 45 PA0 65 PH2 6 PJ6 26 PD4 46 PF7 66 PH1 7 PJ5 27 PD5 47 PF6 67 PH0 8 PJ4 28 PD6 48 PF5 68 PI0 9 PJ3 29 PD7 49 PF4 69 PI1 10 PJ2 30 PB7 50 PF3 70 PI2 11 PJ1 31 PB6 51 PF2 12 PJ0 32 PB5 52 PF1 13 PE7 33 PB4 53 PF0 14 PE6 34 PB3 54 PC2 15 PE5 35 PB2 55 PC1 16 PE4 36 PB1 56 PC0 17 NMI 37 PB0 57 PG0 18 PE3 38 PA7 58 PG1 19 PE2 39 PA6 59 PG2 20 PE1 40 PA5 60 PG3 Page 38 TDO TMPM366FDXBG/FYXBG/FWXBG 4.12 Instructions Supported by the JTAG Controller Cells This section describes the instructions supported by the JTAG controller cells of the TMPM366FDXBG/FYXBG/ FWXBG. 1. EXTEST instruction The EXTEST instruction is used for external interconnect tests. The EXTEST instruction permits BSR cells at output pins to shift out test patterns in the Update-DR state and those at input pins to capture test results in the Capture-DR state. Typically, before EXTEST is executed, the initialization pattern is shifted into the boundary scan register using the SAMPLE/PRELOAD instruction. If the boundary scan register is not reset, indeterminate data will be transferred in the Update-DR state and bus conflicts between ICs may occur. Figure 4-7 shows data flow when the EXTEST instruction is selected. Boundary scan path Input Core logic TDI Output TDO Figure 4-7 Test Data Flow when the EXTEST Instruction is Selected The following steps describe the basic test procedure of the external interconnect test. 1. Reset the TAP controller to the Test-Logic-Reset state. 2. Load the instruction register with the SAMPLE/PRELOAD instruction. This causes the boundary scan register to be connected between TDI and TDO. 3. Reset the boundary scan register by shifting certain data in. 4. Load the test pattern into the boundary scan register. 5. Load the instruction register with the EXTEST instruction. 6. Capture the data applied to the input pin into the boundary scan register. 7. Shift out the captured data while simultaneously shifting the next test pattern in. 8. Send out the test pattern in the boundary scan register at the output on the output pin. Repeat steps 6 to 8 for each test pattern. 2. SAMPLE/PRELOAD instruction This instruction targets the boundary scan register between TDI and TDO. As its name implies, the SAMPLE/PRELOAD instruction provides two functions. SAMPLE allows the input and output pads of an IC to be monitored. While it does so, it does not disconnect the system logic from the IC pins. SAMPLE is executed in the Capture-DR state. It is mainly used to capture the values of the IC's I/O pins on the rising edge of TCK during normal operation. Figure 4-8 shows the flow of data for the SAMPLE phase of the SAMPLE/PRELOAD instruction. Page 39 2013/6/11 4. JTAG Interface 4.12 Instructions Supported by the JTAG Controller Cells TMPM366FDXBG/FYXBG/FWXBG Boundary scan path Input Output Core logic TDI TDO Figure 4-8 Test Data Flow while the SAMPLE is Selected PRELOAD allows the boundary scan register to be reset before any other instruction is selected. For example, prior to selection of the EXTEST instruction, PRELOAD is used to load reset data into the boundary scan register. PRELOAD permits data shifting of the boundary scan register without interfering with the normal operation of the system logic. Figure 4-9 shows the data flow for the PRELOAD phase of the SAMPLE/PRELOAD instruction. Boundary scan path Input Output Core logic TDI TDO Figure 4-9 Test Data Flow while PRELOAD is Selected 3. BYPASS instruction This instruction targets the bypass register between JTDI and JTDO. The bypass register provides the shortest serial path that bypasses the IC (between JTDI and JTDO) when the test does not require control or monitoring of the IC. The BYPASS instruction does not cause interference in the normal operation of the on-chip system logic. Figure 4-10 shows the data flow through the bypass register when the BYPASS instruction is selected. Bypass register TDI TDO 1 bit Figure 4-10 Test Data Flow when the BYPASS Instruction is Selected 4. CLAMP instruction The CLAMP instruction outputs the value that boundary scan register is programmed according to the PRELOAD instruction, and execute Bypass operation. The CLAMP instruction selects the bypass register between TDI and TDO. 2013/6/11 Page 40 TMPM366FDXBG/FYXBG/FWXBG 5. HIGHZ instruction The HIGHZ instruction disables the output of the internal logical circuits. When the HIGHZ instruction is executed, it places the 3-state output pins in the high-impedance state. The HIGHZ instruction also selects the bypass register between TDI and TDO. ・ Notes This section describes the cautions of the JTAG boundary-scan operations specific to the processor. 1. As for a PF0 pin is always pull-up, whenever HIGHZ is ordered, High is output. 2. Please note the input level to the analog input pins. 3. The JTAG circuit can be released from the reset state by either of the following two methods: Assert TRST, initialize the JTAG circuit, and then deassertion TRST. Supply the TCK signal for 5 or more clock pulses to TCK while pulling the TMS pin High. Page 41 2013/6/11 4. JTAG Interface 4.12 Instructions Supported by the JTAG Controller Cells 2013/6/11 TMPM366FDXBG/FYXBG/FWXBG Page 42 TMPM366FDXBG/FYXBG/FWXBG 5. Memory Map 5.1 Memory map The memory maps for theTMPM366FDXBG/FYXBG/FWXBG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. The special function register (SFR) indicates I/O ports and control registers for the peripheral function. The SRAM and SFR regions are all included in the bit-band region. The CPU register region is the processor core's internal register region. For more information on each region, see the "Cortex-M3 Technical Reference Manual". Note that access to regions indicated as "Fault" causes a memory fault if memory faults are enabled or a hard fault if memory faults are disabled. Do not access the vendor-specific region. Page 43 2013/6/11 5. 5.1 Memory Map Memory map 5.1.1 TMPM366FDXBG/FYXBG/FWXBG Memory map of the TMPM366FD Figure 5-1shows the memory map of the TMPM366FD. [))))B)))) Vendor-Specific [(B [()B)))) CPU Register Region [(B [')))B)))) Fault [))B)))) External bus area [B Fault [))B)))) SFR [B Fault [B)))) Main RAM (62K) [B [B)) Backup RAM (2K) [B Fault [B)))) Internal ROM (512K) [B Figure 5-1 Memory Map (TMPM366FD) 2013/6/11 Page 44 TMPM366FDXBG/FYXBG/FWXBG 5.1.2 Memory map of the TMPM366FY Figure 5-2shows the memory map of the TMPM366FY. [))))B)))) Vendor-Specific [(B [()B)))) CPU Register Region [(B [')))B)))) Fault [))B)))) External bus area [B Fault [))B)))) SFR [B Fault [B%))) Main RAM (46K) [B [B)) Backup RAM (2K) [B Fault [B)))) Internal ROM (256K) [B Figure 5-2 Memory Map (TMPM366FY) Page 45 2013/6/11 5. 5.1 Memory Map Memory map 5.1.3 TMPM366FDXBG/FYXBG/FWXBG Memory map of the TMPM366FW Figure 5-3shows the memory map of the TMPM366FW. [))))B)))) Vendor-Specific [(B [()B)))) CPU Register Region [(B [')))B)))) Fault [))B)))) External bus area [B Fault [))B)))) SFR [B Fault [B))) Main RAM (30K) [B [B)) Backup RAM (2K) [B Fault [B)))) Internal ROM (128K) [B Figure 5-3 Memory Map (TMPM366FW) 2013/6/11 Page 46 TMPM366FDXBG/FYXBG/FWXBG 5.2 SFR area detail This section contains the list of addresses in the SFR area (0x4000_0000 through 0x41FF_FFFF) assigned to peripheral function. Access to the Reserved areas in the Table 5-1, the address not specified and the Reserved area in each chapter are prohibited. As for the SFR area, the areas not specified in each chapter is read an undefined value. Writing this area is ignored. Table 5-1 SFR area detail Start Address End Address Peripheral Reserved 0x4000_0028 0x4000_0000 0x4000_3FFF DMAC(2 units, 4ch) - 0x4000_002C - 0x4000_102C 0x4000_0034 0x4000_1028 0x4000_1034 0x4000_4000 0x4000_7FFF Reserved 0x4000_8000 0x4000_9FFF USB Device (1ch) 0x4000_A000 0x4003_FFFF Reserved 0x4004_0000 0x4004_7FFF SSP (3ch) 0x4004_8000 0x4004_BFFF UART (1ch) 0x4004_C000 0x4004_FFFF Reserved 0x4005_0000 0x4005_3FFF ADC(12ch) 0x4005_0064 - 0x4005_0073 0x4005_0F00 - 0x4005_0F8B 0x4004_0230 - 0x4004_023F 0x4005_4000 0x4005_BFFF Reserved 0x4005_C000 0x4005_CFFF EBIF 0x4005_D000 0x400B_FFFF Reserved 0x400C_0000 0x400C_1FFF PORT 0x400C_2000 0x400C_3FFF Reserved 0x400C_4000 0x400C_5FFF TMRB (10ch) 0x400C_6000 0x400D_FFFF Reserved 0x400E_0000 0x400E_0FFF I2C/SIO (2ch) 0x400E_0800 - 0x400E_0FFF 0x400E_1000 0x400E_1FFF SIO/UART (2ch) 0x400E_1134 - 0x400E_1137 0x400E_2000 0x400F_0FFF Reserved 0x400F_1000 0x400F_1FFF Reserved 0x400F_2000 0x400F_2FFF WDT 0x400F_2100 - 0x400F_2FFF 0x400F_3000 0x400F_3FFF CG 0x400F_3100 - 0x400F_3FFF 0x400F_4000 0x41FF_EFFF Reserved 0x41FF_F000 - 0x41FF_F007 0x41FF_F000 0x41FF_F03F FLASH 0x41FF_F014 - 0x41FF_F017 0x41FF_F024 - 0x41FF_F02B 0x41FF_F040 0x41FF_FFFF Reserved Page 47 2013/6/11 5. 5.2 Memory Map SFR area detail 2013/6/11 TMPM366FDXBG/FYXBG/FWXBG Page 48 TMPM366FDXBG/FYXBG/FWXBG 6. Reset The TMPM366FDXBG/FYXBG/FWXBG has four reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from , refer to "Cortex-M3 Technical Reference Manual". 6.1 Initial state 6.1.1 State before input reset The internal circuits, register settings and pin status of the TMPM366FDXBG/FYXBG/FWXBG are undefined right after the power-on. The state continues until the RESET pin receives low level input after all the power supply voltage (DVDD3A, RVDD3, AVDD3 and DVDD3C) is applied. 6.2 Cold reset The power-on sequence must include the time for the internal regulator to be stable and the reset time. In the TMPM366FDXBG/FYXBG/FWXBG, the internal regulator requires at least 1ms to be stable. At cold reset, the external reset pin must be kept "Low" for a duration of time sufficiently long enough for the internal regulator to be stable. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400 μs. Figure 6-1 shows the power-on sequence. DVDD3A, DVDD3C, RVDD3, AVDD3 2.7 V 0V 1 ms RESET Internal Oscillation 400Ǵs Internal reset 1.4 ms Figure 6-1 Cold Reset Sequence Note 1: Turn on the power while the RESET pin is fixed to "Low". Release the RESET pin while all the power supplies are stabilized within operating voltage (DVDD3A/DVDD3B/RVDD3/AVDD3) and after an elapse of 1ms or more from while all the power supplies are stabilized within operating voltage. Note 2: The above sequence is applied as well when restoring power. Page 49 2013/6/11 6. 6.3 Reset Warm reset TMPM366FDXBG/FYXBG/FWXBG 6.3 Warm reset 6.3.1 Reset period As a precondition, ensure that the power supply voltage is within the operating range and the internal highfrequency oscillator is providing stable oscillation. To reset the TMPM366FDXBG/FYXBG/FWXBG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. And When the RESET signal input at "Low" level while in STOP2 mode, the RESET signal is fixed to "Low" more than 500μs as internal regulator stability time. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400 μs. 6.4 After reset A warm reset initializes the majority of the Cortex-M3 processor core's system control registers and internal function registers. The processor core's system debug components (FPB, DWT, ITM) register, the clock generator's CGRSTFLG register and the FCSECBIT register are initialized by following factors. And FCSECBIT register is initialized by STOP2 mode released. After reset, the PLL multiplication circuit is inactive and must be enabled in the CGPLLSEL register if needed. When the reset exception handling is completed, the program branches to the reset interrupt service routine. Note:The reset operation may alter the internal RAM state. The factor of register initialization Register Factors CGRSTFLG Cold reset External Reset FCSECBIT Cold reset STOP2 mode released FPB, DWT, ITM Cold reset STOP2 mode released (Note Note:When a debug tool is connecting, these registers are not initialized. 2013/6/11 Page 50 TMPM366FDXBG/FYXBG/FWXBG 7. Watchdog Timer(WDT) The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or other disturbances and remedying them to return the CPU to normal operation. If the watchdog timer detects a runaway, it generates a INTWDT interrupt or reset. Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI). Also, the watchdog timer notifies of the detecting malfunction to the external peripheral devices from the watchdog timer pin (WDTOUT) by outputting "Low". Note:This product does not have the watchdog timer out pin (WDTOUT). Configuration Figure 7-1shows the block diagram of the watchdog timer. WDMOD RESET pin To internal reset Watchdog timer out control WDTOUT Watchdog timer interrupt INTWDT fsys 225/fsys 223/fsys 221/fsys 217/fsys 219/fsys Selector WDMOD 215/fsys 7.1 Q Binary counter R S Reset Internal reset Write “0x4E” Write “0xB1” WDMOD Watch dog timer Control Register WDCR Internal data bus Figure 7-1 Block Diagram of the Watchdog Timer Page 51 2013/6/11 7. 7.2 Watchdog Timer(WDT) Register TMPM366FDXBG/FYXBG/FWXBG 7.2 Register The followings are the watchdog timer control registers and addresses. Base Address = 0x400F_2000 Register name Address(Base+) Watchdog Timer Mode Register Watchdog Timer Control Register 7.2.1 WDMOD 0x0000 WDCR 0x0004 WDMOD(Watchdog Timer Mode Register) bit symbol After reset 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - I2WDT RESCR - 0 0 0 1 0 bit symbol WDTE After reset 1 Bit Bit Symbol WDTP 0 0 Type Function 31-8 − R Read as 0. 7 WDTE R/W Enable/Disable control 0:Disable 1:Enable 6-4 WDTP[2:0] R/W Selects WDT detection time(Refer toTable 7-1) 000: 215/fsys 100: 223/fsys 001: 217/fsys 101: 225/fsys 010: 219/fsys 110:Setting prohibited. 011: 221/fsys 111:Setting prohibited. 3 − R Read as 0. 2 I2WDT R/W Operation when IDLE mode 0: Stop 1:In operation 1 RESCR R/W Operation after detecting malfunction 0: INTWDT interrupt request generates. (Note) 1: Reset 0 − R/W Write 0. Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI). 2013/6/11 Page 52 TMPM366FDXBG/FYXBG/FWXBG Table 7-1 Detection time of watchdog timer (fc = 48MHz) WDMOD Clock gear value CGSYSCR 000 001 010 011 100 101 000 (fc) 0.68 ms 2.73 ms 10.92 ms 43.69 ms 174.76 ms 699.05 ms 100 (fc/2) 1.37 ms 5.46 ms 21.85 ms 87.38 ms 349.53 ms 1.40 s 101 (fc/4) 2.73 ms 10.92 ms 43.69 ms 174.76 ms 699.05 ms 2.80 s 110 (fc/8) 5.46 ms 21.85 ms 87.38 ms 349.53 ms 1.40 s 5.59 s 111 (fc/16) 10.92 ms 43.69 ms 174.76 ms 699.05 ms 2.80 s 11.18 s Page 53 2013/6/11 7. 7.2 Watchdog Timer(WDT) Register TMPM366FDXBG/FYXBG/FWXBG 7.2.2 WDCR (Watchdog Timer Control Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - - - bit symbol WDCR After reset Bit - Bit Symbol - - - Type Function 31-8 − R Read as 0. 7-0 WDCR W Disable/Clear code 0xB1:Disable code 0x4E: Clear code Others:Reserved 2013/6/11 Page 54 TMPM366FDXBG/FYXBG/FWXBG 7.3 Operations 7.3.1 Basic Operation The Watchdog timer is consists of the binary counters that work using the system clock (fsys) as an input. Detecting time can be selected between 215, 217, 219 , 221, 223 and 225 by the WDMOD. The detecting time as specified is elapsed, the watchdog timer interrupt (INTWDT) generates, and the watchdog timer out pin (WDTOUT) output "Low". To detect malfunctions (runaways) of the CPU caused by noise or other disturbances, the binary counter of the watchdog timer should be cleared by software instruction before INTWDT interrupt generates. If the binary counter is not cleared, the non-maskable interrupt generates by INTWDT. Thus CPU detects malfunction (runway), malfunction countermeasure program is performed to return to the normal operation. Additionally, it is possible to resolve the problem of a malfunction (runaway) of the CPU by connecting the watchdog timer out pin to reset pins of peripheral devices. Note:This product does not include a watchdog timer out pin (WDTOUT). 7.3.2 Operation Mode and Status The watchdog timer begins operation immediately after a reset is cleared. If not using the watchdog timer, it should be disabled. The watchdog timer cannot be used as the high-speed frequency clock is stopped. Before transition to below modes, the watchdog timer should be disabled.In IDLE mode, its operation depends on the WDMOD setting. - STOP1 mode STOP2 mode Also, the binary counter is automatically stopped during debug mode. Page 55 2013/6/11 7. 7.4 Watchdog Timer(WDT) Operation when malfunction (runaway) is detected 7.4 TMPM366FDXBG/FYXBG/FWXBG Operation when malfunction (runaway) is detected 7.4.1 INTWDT interrupt generation In the Figure 7-2 shows the case that INTWDT interrupt generates (WDMOD="0"). When an overflow of the binary counter occurs, INTWDT interrupt generates. It is a factor of non-maskable interrupt (NMI). Thus CPU detects non-maskable interrupt and performs the countermeasure program. The factor of non-maskable interrupt is the plural. CGNMIFLG identifies the factor of non-maskable interrupts. In the case of INTWDT interrupt, CGNMIFLG is set. When INTWDT interrupt generates, simultaneously the watchdog timer out (WDTOUT) output "Low". WDTOUT becomes "High" by the watchdog timer clearing that is writing clear code 0x4E to the WDCR register. Note:This product does not have the watchdog timer output pin(WDTOUT). WDT counter n Overflow 0 INTWDT Write of a clear code WDT clear WDTOUT Figure 7-2 INTWDT interrupt generation 2013/6/11 Page 56 TMPM366FDXBG/FYXBG/FWXBG 7.4.2 Internal reset generation Figure 7-3 shows the internal reset generation (WDMOD="1"). MCU is reset by the overflow of the binary counter. In this case, reset status continues for 32 states. A clock is initialized so that input clock (fsys) is the same as a internal high-speed frequency clock (fosc). This means fsys = fosc. Overflow WDT counter n INTWDT Internal reset WDTOUT 32-state Figure 7-3 Internal reset generation Page 57 2013/6/11 7. 7.5 Watchdog Timer(WDT) Control register 7.5 TMPM366FDXBG/FYXBG/FWXBG Control register The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. 7.5.1 Watchdog Timer Mode Register (WDMOD) 1. Specifying the detection time of the watchdog timer . Set the watchdog timer detecting time to WDMOD. After reset, it is initialized to WDMOD = "000". 2. Enabling/disabling the watchdog timer . When resetting, WDMOD is initialized to "1" and the watchdog timer is enabled. To disable the watchdog timer to protect from the error writing by the malfunction, first bit is set to "0", and then the disable code (0xB1) must be written to WDCR register. To change the status of the watchdog timer from "disable" to "enable," set the bit to "1". 3. Watchdog timer out reset connection This register specifies whether WDTOUT is used for internal reset or interrupt. After reset, WDMOD is initialized to "1", the internal reset is generated by the overflow of binary counter. 7.5.2 Watchdog Timer Control Register(WDCR) This is a register for disabling the watchdog timer function and controlling the clearing function of the binary counter. 2013/6/11 Page 58 TMPM366FDXBG/FYXBG/FWXBG 7.5.3 Setting example 7.5.3.1 Disabling control By writing the disable code (0xB1) to this WDCR register after setting WDMOD to "0," the watchdog timer can be disabled and the binary counter can be cleared. 7.5.3.2 7 6 5 4 3 2 1 0 WDMOD ← 0 − − − − − − − Set to "0". WDCR ← 1 0 1 1 0 0 0 1 Writes the disable code (0xB1). Enabling control Set WDMOD to "1". WDMOD 7.5.3.3 ← 7 6 5 4 3 2 1 0 1 − − − − − − − Set to "1". Watchdog timer clearing control Writing the clear code (0x4E) to the WDCR register clears the binary counter and it restarts counting. WDCR 7.5.3.4 ← 7 6 5 4 3 2 1 0 0 1 0 0 1 1 1 0 Writes the clear code (0x4E). Detection time of watchdog timer In the case that 221/fsys is used, set "011" to WDMOD. WDMOD ← 7 6 5 4 3 2 1 0 1 0 1 1 − − − − Page 59 2013/6/11 7. 7.5 Watchdog Timer(WDT) Control register 2013/6/11 TMPM366FDXBG/FYXBG/FWXBG Page 60 TMPM366FDXBG/FYXBG/FWXBG 8. Clock/Mode control 8.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL clock multiplication circuit and oscillator. There is also the low power consumption mode which can reduce power consumption by mode transitions. This chapter describes how to control clock operating modes and mode transitions. The clock/mode control block has the following functions: ・ ・ ・ ・ Controls the system clock Controls the prescaler clock Controls the PLL multiplication circuit Controls the warm-up timer In addition to NORMAL mode, the TMPM366FDXBG/FYXBG/FWXBG can operate in three types of low power mode to reduce power consumption according to its usage conditions. Page 61 2013/6/11 8. 8.2 Clock/Mode control Registers 8.2 TMPM366FDXBG/FYXBG/FWXBG Registers 8.2.1 Register List The following table shows the CG-related registers and addresses. Base Address = 0x400F_3000 Register name Address(Base+) System control register CGSYSCR 0x0000 Oscillation control register CGOSCCR 0x0004 Standby control register CGSTBYCR 0x0008 PLL selection register CGPLLSEL 0x000C Reserved - 0x0010 Reserved - 0x0014 CGUSBCTL 0x0038 CGPROTECT 0x003C USB clock control register Protect register Note:Access to the "Reserved" area is prohibited. 2013/6/11 Page 62 TMPM366FDXBG/FYXBG/FWXBG 8.2.2 CGSYSCR (System control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 - - - FCSTOP - - bit symbol After reset 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 bit symbol - - - FPSEL - After reset 0 0 0 0 0 0 2 7 6 5 4 3 bit symbol - - - - - After reset 0 0 0 0 0 Bit 16 SCOSEL Bit Symbol Type PRCK 0 0 1 0 GEAR 0 0 0 Function 31-21 − R Read as 0. 20 FCSTOP R/W ADC clock 0: Active 1: Stop Enables to stop providing ADC clock. ADC clock is provided after reset. Confirming that ADC is stopped or finished in advance is required when setting "1"(stop). 19-18 − R Read as 0. 17-16 SCOSEL[1:0] R/W SCOUT out 00: Reserved 01: fsys/2 10: fsys 11: φT0 Enables to output the specified clock from SCOUT pin. 15-14 − R Read as 0. 13 − R/W Write "0" 12 FPSEL − fperiph 0: fgear 1: fc Specifies the source clock to fperiph. Selecting fc fixes fperiph regardless of the clock gear mode. 11 − R Read as 0. 10-8 PRCK[2:0] R/W Prescaler clock 000: fperiph 100: fperiph/16 001: fperiph/2 101: fperiph/32 010: fperiph/4 110: Reserved 011: fperiph/8 111: Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as 0. 2-0 GEAR[2:0] R/W High-speed clock gear (fc) gear 000: fc 100: fc/2 001: Reserved 101: fc/4 010: Reserved 110: fc/8 011: Reserved 111: fc/16 Page 63 2013/6/11 8. 8.2 Clock/Mode control Registers TMPM366FDXBG/FYXBG/FWXBG 8.2.3 CGOSCCR (Oscillation control register) 31 30 29 28 1 0 0 0 23 22 21 20 bit symbol 27 26 25 24 0 0 0 0 WUODR After reset bit symbol WUODR After reset 19 18 17 16 HWUPSEL EHOSCSEL OSCSEL XEN2 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 bit symbol - - - - - - - XEN1 After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - PLLON WUEF WUEON After reset 0 0 1 1 0 0 0 0 Bit 31-20 Bit Symbol WUODR[11:0] Type R/W Function Warm-up counter setup value. Setup the 16-bit timer for warm-up timer of upper 12-bits counter value. 19 HWUPSEL R/W High-speed warm-up clock. 0: internal (IHOSC) 1: external (feosc) Selects the source clock for warm-up counter. The selected clock is counted by warm-up counter. 18 EHOSCSEL R/W External oscillator. 0: input external clock (EHCLKIN) 1: external oscillator (EHOSC) 17 OSCSEL R/W High-speed oscillator (Note2) 0: internal high-speed oscillator (IHOSC) 1: external high-speed oscillator (feosc) 16 XEN2 R/W Internal high-speed oscillator operation 0: Stop 1: Oscillation 15-12 − R/W Write "0". 11-10 − R Read as 0. 9 − R/W Write "0". 8 XEN1 R/W External high-speed oscillator operation 0: Stop 1: Oscillation 7-3 − R/W Write "00110" 2 PLLON R/W PLL (multiplying circuit) operation 0: Stop 1: Oscillation 1 WUEF R Operation of warm-up timer (WUP) for oscillator 0: WUP finish 1: WUP active Enables to monitor the status of the warm-up timer. 0 WUEON W Operation of warm-up timer (WUP) for oscillator 0: don’t care 1: WUP start Enables to start the warm-up timer. Read as 0. Note 1: Refer to Section "8.3.4 Warm-up function" about the Warm-up setup. Note 2: When selecting external oscillator ( input external clock), select after setting . (Do not select simultaneously) 2013/6/11 Page 64 TMPM366FDXBG/FYXBG/FWXBG Note 3: After setting CGOSCCR=1, operate Warm-up operation and then set CGPLLSEL=1. Note 4: Returning from the STOP1/STOP2 mode, related bits , , , , of the register CGOSCCR and CGPLLSEL are initialized because of internal high-speed oscillator starts up. Note 5: When using internal high-speed oscillator (IHOSC) as system clock, do not use PLL multiplying. Note 6: When using internal high-speed oscillator (IHOSC), do not use it as system clock which high accuracy assurance is required. Page 65 2013/6/11 8. 8.2 Clock/Mode control Registers TMPM366FDXBG/FYXBG/FWXBG 8.2.4 CGSTBYCR (Standby control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - PTKEEP DRVE bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 2 1 0 7 6 5 4 3 bit symbol - - - - - After reset 0 0 0 0 0 Bit Bit Symbol Type STBY 0 1 Function 31-20 − R Read as 0. 19-18 − R/W Write "0" after reset. 17 PTKEEP R/W Keeps IO control signal in STOP2 mode 0: Control by port 1: Keep status when setting 0->1 ( must be set before entering STOP2 mode) 16 DRVE R/W Pin status in STOP1 mode. 0: Inactive in STOP1 mode 1: Active in STOP1 mode 15-3 − R Read as 0. 2-0 STBY[2:0] R/W Low power consumption mode 000: Reserved 001: STOP1 010: Reserved 011: IDLE 100: Reserved 101: STOP2 110: Reserved 111: Reserved Note 1: The reserved value is not set. 2013/6/11 Page 66 1 TMPM366FDXBG/FYXBG/FWXBG 8.2.5 CGPLLSEL (PLL Selection Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 bit symbol PLLSET After reset bit symbol PLLSET After reset Bit 0 Bit Symbol 0 0 0 Type 0 PLLSEL 0 0 0 0 Function 31-16 − R Read as 0. 15-1 PLLSET[14:0] R/W PLL multiplying value (Do not use except below) 0x381E: 8 multiplying 0x3816: 6 multiplying 0 PLLSEL R/W Use of PLL 0: fosc 1: fPLL / 2 (PLL use) Specifies use or disuse of the clock multiplied by the PLL. "fosc (internal high-speed oscillator)" is automatically set after reset.Resetting is required when using the PLL. Note 1: Select PLL multiplying value which is shown in Table 8-1. Note 2: Select PLL multiplying value when CGOSCCR=0 (PLL stop). Note 3: Returning from the STOP1/STOP2 mode, related bits , CGOSCCR, , , , and are initialized because of internal high-speed oscillator starts up. Note 4: When using internal high-speed oscillator (IHOSC) as system clock, do not use PLL multiplying. Page 67 2013/6/11 8. 8.2 Clock/Mode control Registers TMPM366FDXBG/FYXBG/FWXBG 8.2.6 CGUSBCTL (USB clock control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - USBCLKSEL USBCLKEN- After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - - After reset 0 0 1 1 0 0 0 0 Bit Bit Symbol Type Function 31-10 − R Read as 0. 9 USBCLKSEL R/W USB Source clock selection 0 : PLL clock 1 : External input clcok Selects source clock to USB device block. 8 USBCLKEN R/W USB Souce clock control 0: Clock disable 1: Clock enable 7-1 0 − R Read as 0 R/W Write as Zero Note 1: When is modified, it should be doing in source clock disable. Note 2: and 4/fsys Figure 18-16 Maximum Transfer Frequency of External Clock Input 2013/6/11 Page 586 TMPM366FDXBG/FYXBG/FWXBG 18.8.1.2 Shift Edge Leading-edge shift is used in transmission. Trailing-edge shift is used in reception. - Leading-edge shift Data is shifted at the leading edge of the serial clock (or the falling edge of the SCKx pin input/output). - Trailing-edge shift Data is shifted at the trailing edge of the serial clock (or the rising edge of the SCKx pin input/output). SCKx pin SOx pin Shift register bit 0 bit 1 bit 2 bit 3 bit 4 76543210 *7654321 **765432 ***76543 ****7654 bit 5 bit 6 bit 7 *****765 ******76 *******7 bit 5 bit 6 bit 7 (a) Leading-edge SCKx pin SIx pin Shift register bit 0 ******** bit 1 0******* bit 2 10****** bit 3 210***** bit 4 3210**** 43210*** 543210** 6543210* 76543210 (b) Trailing-edge Figure 18-17 Shift Edge Page 587 2013/6/11 18. 18.8 Serial Bus Interface (I2C/SIO) Control in SIO mode 18.8.2 TMPM366FDXBG/FYXBG/FWXBG Transfer Modes The transmit mode, the receive mode or the transmit/receive mode can be selected by programming SBIxCR1. 18.8.2.1 8-bit transmit mode Set the control register to the transmit mode and write the transmit data to SBIxDBR. After writing the transmit data, writing "1" to SBIxCR1 starts the transmission. The transmit data is moved from SBIxDBR to a shift register and output to the SO pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the transmit data is transferred to the shift register, SBIxDBR becomes empty, and the INTSBIx (buffer-empty) interrupt is generated, requesting the next transmit data. In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if next data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared when SBIxDBR is loaded with the next transmit data. In the external clock mode, SBIxDBR must be loaded with data before the next data shift operation is started. Therefore, the data transfer rate varies depending on the maximum latency between when the interrupt request is generated and when SBIxDBR is loaded with data in the interrupt service program. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting SBIxSR to "1" to the falling edge of SCK. Transmission can be terminated by clearing to "0" or setting to "1" in the INTSBIx interrupt service program. If is cleared, remaining data is output before transmission ends. The program checks SBIxSR to determine whether transmission has come to an end. is cleared to "0" at the end of transmission. If is set to "1", the transmission is aborted immediately and is cleared to "0". When in the external clock mode, must be cleared to "0" before next data shifting. If does not be cleared to "0" before next data shifting, SBI output dummy data and stopped. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 0 0 0 X X X Selects the transmit mode. SBIxDBR ← X X X X X X X X Writes the transmit data. SBIxCR1 ← 1 0 0 0 0 X X X Starts transmission. X X X X X X X Writes the transmit data. INTSBIx interrupt SBIxDBR 2013/6/11 ← X Page 588 TMPM366FDXBG/FYXBG/FWXBG is cleared SCKx pin(output) SOx pin a0 * a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 b6 b7 INTSBIx interrupt request SBIxDBR a b (a) Internal clock :ULWHWKHWUDQVPLWGDWD is cleared. SCKx pin(input) SOx pin a0 * a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 INTSBIx interrupt request SBIxDBR a b (b)External clock :ULWHWKHWUDQVPLWGDWD Figure 18-18 Transmit Mode Example: Example of programming (external clock) to terminate transmission by 7 6 5 4 3 2 1 0 if SBIxSR ≠ 0 Recognizes the completion of the transmission. Then Recognizes "1" is set to the SCK pin by monitoring the port. if SCK ≠ 1 Then SBIxCR1 ← 0 0 0 0 0 1 1 1 Page 589 Completes the transmission by setting = 0. 2013/6/11 18. 18.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM366FDXBG/FYXBG/FWXBG 18.8.2.2 8-bit receive mode Set the control register to the receive mode. Then writing "1" to SBIxCR1 enables reception.Data is taken into the shift register from the SI pin, with the least-significant bit (LSB) first, in synchronization with the serial clock. Once the shift register is loaded with the 8-bit data, it transfers the received data to SBIxDBR and the INTSBIx (buffer-full) interrupt request is generated to request reading the received data. The interrupt service program then reads the received data from SBIxDBR. In the internal clock mode, the serial clock will be stopped and automatically be in the wait state until the received data is read from SBIxDBR. In the external clock mode, shift operations are executed in synchronization with the external clock. The maximum data transfer rate varies, depending on the maximum latency between generating the interrupt request and reading the received data Reception can be terminated by clearing to "0" or setting to "1" in the INTSBIx interrupt service program. If is cleared, reception continues until all the bits of received data are written to SBIxDBR. The program checks SBIxSR to determine whether reception has come to an end. is cleared to "0" at the end of reception. After confirming the completion of the reception, last received data is read. If is set to "1", the reception is aborted immediately and is cleared to "0". (The received data becomes invalid, and there is no need to read it out.) Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 1 1 0 X X X Selects the receive mode. SBIxCR1 ← 1 0 1 1 0 X X X Starts reception. INTSBIx interrupt Reg. 2013/6/11 ← SBIxDBR Reads the received data. Page 590 TMPM366FDXBG/FYXBG/FWXBG Clear SCKx pin(output) SIx pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSBIx interrupt request SBIxDBR a b Read receive data Read receive data Figure 18-19 Receive Mode (Example: Internal Clock) 18.8.2.3 8-bit transmit/receive mode Set the control register to the transfer/receive mode. Then writing the transmit data to SBIxDBR and setting SBIxCR1 to "1" enables transmission and reception.The transmit data is output through the SOx pin at the falling of the serial clock, and the received data is taken in through the SI pin at the rising of the serial clock, with the least-significant bit (LSB) first. Once the shift register is loaded with the 8bit data, it transfers the received data to SBIxDBR and the INTSBIx interrupt request is generated.The interrupt service program reads the received data from the data buffer register and writes the next transmit data. Because SBIxDBR is shared between transmit and receive operations, the received data must be read before the next transmit data is written. In the internal clock operation, the serial clock will be automatically in the wait state until the received data is read and the next transmit data is written. In the external clock mode, shift operations are executed in synchronization with the external serial clock. Therefore, the received data must be read and the next transmit data must be written before the next shift operation is started.The maximum data transfer rate for the external clock operation varies depending on the maximum latency between when the interrupt request is generated and when the transmit data is written. At the beginning of transmission, the same value as in the last bit of the previously transmitted data is output in a period from setting to "1" to the falling edge of SCK. Transmission and reception can be terminated by clearing to "0" or setting SBIxCR1 to "1" in the INTSBIx interrupt service program. If is cleared, transmission and reception continue until the received data is fully transferred to SBIxDBR. The program checks SBIxSR to determine whether transmission and reception have come to an end. is cleared to "0" at the end of transmission and reception.If is set to "1", the transmission and reception is aborted immediately and is cleared to "0". Note:The contents of SBIxDBR will not be retained after the transfer mode is changed. The ongoing transmission and reception must be completed by clearing to "0" and the last received data must be read before the transfer mode is changed. Page 591 2013/6/11 18. 18.8 Serial Bus Interface (I2C/SIO) Control in SIO mode TMPM366FDXBG/FYXBG/FWXBG is cleard. SCKx pin(output) SOx pin * SIx pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 c2 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 d6 d7 INTSBIx interrupt request SBIxDBR c a Write the transmitted data(a) Read the received data(c) b Write the transmitted data(b) d Read the received data(d) Figure 18-20 Transmit/Receive Mode (Example: Internal Clock) 7 6 5 4 3 2 1 0 SBIxCR1 ← 0 1 1 0 0 X X X Selects the transmit mode. SBIxDBR ← X X X X X X X X Writes the transmit data. SBIxCR1 ← 1 0 1 0 0 X X X Starts reception/transmission. INTSBIx interrupt Reg. ← SBIxDBR SBIxDBR ← X 18.8.2.4 X Reads the received data. X X X X X X Writes the transmit data. Data retention time of the last bit at the end of transmission Under the condition SBIxCR1= "0", the last bit of the transmitted data retains the data of SCK rising edge as shown below. Transmit mode and transmit/receive mode are the same. SCKx pin SOx pin bit 6 Bit 7 of end of transmitted word tSODH = Min. 4/fsys [s] Figure 18-21 Data retention time of the last bit at the end of transmission 2013/6/11 Page 592 TMPM366FDXBG/FYXBG/FWXBG 19. Analog/Digital Converter (ADC) 19.1 Outline TMPM366FDXBG/FYXBG/FWXBG contains a 12-bit, sequential-conversion analog/digital converter (ADC) with 12 analog input channnels. These 12 analog input channels (pins AIN00 through AIN11) are also used as input/output ports. The 12-bit AD converter has the following features: ・ Starting normal AD conversion and highest-priority AD conversion Software activation Activation with the 16-bit timer (TMRB) Hardware activation with an external trigger input (ADTRG pin) ・ AD conversion Fixed-channel singlel conversion mode Channel scan single conversion mode Fixed-channel repeat conversion mode Channnel scan repeat conversion mode ・ Highest-priority AD conversion ・ Normal AD conversion completion interrupt and highest-priority AD conversion completion interrupt ・ Normal AD conversion and highest-priority AD conversion have the following status flags. A flag indicating the AD conversion result data is valid, , and a flag indicating theAD conversion result data is overwritten, Normal AD conversion completion flag and highest-priority AD conversion completion flag Normal AD conversion busy flag and highest-priority AD conversion busy flag ・ AD Monitor Function ・ ・ ・ ・ When the AD monitor function is enabled, an interrupt is generated if any comparison result is matched. AD conversion clock can be contorolled from 1/fc to 1/16fc. When AD conversion is completed, two types of DMA requests are supported. Standby mode is supported. Output switching monitor function This is the function that monitors output switching operation of general input-output ports, which is also used as analog input channels (pins AIN00 througe AIN11), during AD conversion. This monitor function is used to suggest the possibility that output switching operation during AD conversion affects conversion accuracy. Page 593 2013/6/11 2013/6/11 fc SCANAREA Multiplexer Page 594 1/1 1/2 1/4 1/8 Busy Sample hold ADCLK DA Converter Comparator   ADMOD0 ADMOD1 Interrupt Interval AD conversion comparision register ADCMP0,1 AD conversion result register ADREGSP AD conversion result register ADREG00- 11 Internal data bus AD conversion end interrupt ADCMPCR0,1 AD monitor function interrupt AD monitor function control Highest priority AD conversion end interrupt Start AD start control Highest priority AD conversion control circuit Scan Repeat ADMOD3 ADMOD7 ADMOD6 DMAREQ DMACLR INTAD INTADHP INTADM0, 1 INTCAP40 INTCAP50 Configuration AVREFL (AVSS) End Normal AD conversion control circuit End AVREFH ADMOD5 ADS VREF ADMOD4 HPADS AIN 11 Channel select control circuit ADMOD2 19.2 AIN00 ADTRG ADCLK 19.2 Internal data bus 19. Analog/Digital Converter (ADC) TMPM366FDXBG/FYXBG/FWXBG Configuration Figure 19-1 shows the block diagram of the AD converter. Comparision register Busy Figure 19-1 AD Converter Block Diagram TMPM366FDXBG/FYXBG/FWXBG 19.3 Registers 19.3.1 Register list The control registers and addresses of the AD converter are as follows. The AD converter is controlled by the AD mode control registers (ADMOD0 through ADMOD7). The result of AD conversion is stored in 12 AD conversion result registers, ADREG00 through ADREG11. The highest-priority conversion result is stored in the register ADREGSP. Base Address = 0x4005_0000 Register name Address(Base+) Conversion Clock Setting Register ADCLK 0x0000 Mode Control Register 0 ADMOD0 0x0004 Mode Control Register 1 ADMOD1 0x0008 Mode Control Register 2 ADMOD2 0x000C Mode Control Register 3 ADMOD3 0x0010 Mode Control Register 4 ADMOD4 0x0014 Mode Control Register 5 ADMOD5 0x0018 Mode Control Register 6 ADMOD6 0x001C Mode Control Register 7 ADMOD7 0x0020 Monitor Function Control Register 0 ADCMPCR0 0x0024 Monitor Function Control Register 1 ADCMPCR1 0x0028 ADCMP0 0x002C Conversion Result Comparison Register 1 ADCMP1 0x0030 Conversion Result Register 0 ADREG00 0x0034 Conversion Result Register 1 ADREG01 0x0038 Conversion Result Register 2 ADREG02 0x003C Conversion Result Register 3 ADREG03 0x0040 Conversion Result Register 4 ADREG04 0x0044 Conversion Result Register 5 ADREG05 0x0048 Conversion Result Register 6 ADREG06 0x004C Conversion Result Register 7 ADREG07 0x0050 Conversion Result Register 8 ADREG08 0x0054 Conversion Result Register 9 ADREG09 0x0058 Conversion Result Register 10 ADREG10 0x005C Conversion Result Register 11 Conversion Result Comparison Register 0 ADREG11 0x0060 Reserved - 0x0064 Reserved - 0x0068 Reserved - 0x006C Reserved - 0x0070 Conversion Result Register SP ADREGSP 0x0074 Reserved - 0x0F00 Reserved - 0x0F04 Reserved - 0x0F08 Note:Access to the "Reserved" area is prohibited. Page 595 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.2 ADCLK (Conversion Clock Setting Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol After reset Bit ADSH 0 Bit Symbol 0 0 0 Type 0 ADCLK 0 0 0 Function 31-8 − R Read as 0. 7-4 ADSH[3:0] R/W Select the AD sample hold time. 0000: 10 × 0001: 20 × 0010: 30 × 0011: 40 × 0100: 80 × 0101 to 1111: Reserved 3 − R Read as 0. 2-0 ADCLK[2:0] R/W Select the AD prescaler clock. 000: fc 001: fc/2 010: fc/4 011: fc/8 100 to 111: Reserved Note 1: Specify ADCLK in range 4MHz ≤ ADCLK ≤ 40MHz. For example, when fosc = 12MHz and PLL = 8 multiplying, fc comes to 48MHz. In such case, set ADCLK to a value other than "000". Note 2: Do not change the setting of except when AD convertsion is suspended and ADMOD1="0". fc ÷1 ÷2 ÷4 ÷8 ADCLK Figure 19-2 AD conversion clock (ADCLK) A clock count required for conversion is 40 clocks at the minimum. Examples of sample hold time and conversion time as shown as below. 2013/6/11 Page 596 TMPM366FDXBG/FYXBG/FWXBG Setting 000 (fc) 001 (fc/2) 010 (fc/4) 011 (fc/8) Conversion time fc=32MHz fc=40MHz fc=48MHz conversion clock × 10 1.25 μs 1.00 μs − conversion clock × 20 1.56 μs 1.25 μs − conversion clock × 30 1.88 μs 1.50 μs − conversion clock × 40 2.19 μs 1.75 μs − conversion clock × 80 3.44 μs 2.75 μs − conversion clock × 10 2.50 μs 2.00 μs 1.67 μs conversion clock × 20 3.13 μs 2.50 μs 2.08 μs conversion clock × 30 3.75 μs 3.00 μs 2.50 μs conversion clock × 40 4.38 μs 3.50 μs 2.92 μs conversion clock × 80 6.88 μs 5.50 μs 4.58 μs conversion clock × 10 5.00 μs 4.00 μs 3.33 μs conversion clock × 20 6.25 μs 5.00 μs 4.17 μs conversion clock × 30 7.50 μs 6.00 μs 5.00 μs conversion clock × 40 8.75 μs 7.00 μs 5.83 μs conversion clock × 80 − − 9.17 μs conversion clock × 10 10.0 μs 8.00 μs 6.67 μs conversion clock × 20 − 10.0 μs 8.33 μs conversion clock × 30 − − 10.00 μs conversion clock × 40 − − − conversion clock × 80 − − − Note 1: Do not change the setting of the AD conversion clock during AD conversion. Note 2: Setting the element indicated by "−" in the above table is prohibited. Specify ADCLK setting in the 1μs to 10μs range. Page 597 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.3 ADMOD0 (Mode Control Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - HPADS ADS After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-2 − R Read as 0. 1 HPADS W Activate highest-priority AD conversion 0: Don't care 1: Start conversion "0" is always read. 0 ADS W Activate normal (software) AD conversion (Note 3) 0: Don't care 1: Start conversion "0" is always read. Note 1: In use ADC, write "1" to ADMOD1 first, and then start AD conversion or external trigger by setting ADMOD0 or . Note 2: When both highest-priority AD conversion and normal AD conversion (software) are enabled and they are selected as ADTRG (external trigger input), highest-priority AD conversion is activated as a priority and normal AD conversion is not activated. 2013/6/11 Page 598 TMPM366FDXBG/FYXBG/FWXBG 19.3.4 ADMOD1 (Mode Control Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol VREFON I2AD RCUT - HPADHWS HPADHWE ADHWS ADHWE After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-8 − R Read as 0. 7 VREFON R/W VREF application control (Note1 and Note2) 0: OFF 1: ON 6 I2AD R/W Specify operation mode in IDLE mode 0: Stop 1: Operation 5 RCUT R/W Control AVREFH-AVREFL current 0: Apply the current only in conversion. 1: Apply the current at any time except in RESET 4 − R Read as 0. 3 HPADHWS R/W Select hardware activation source of highest-priority AD conversion 0: External trigger 1: Interrupt of INTCAP40 2 HPADHWE R/W Activate highest-priority AD conversion triggered by hardware factors 0: Disable 1: Enable 1 ADHWS R/W Select hardware activation source of normal AD conversion (Note 3) 0: External trigger 1: Interrupt of INTCAP50 0 ADHWE R/W Activate normal AD conversion triggered by hardware factors 0: Disable 1: Enable Note 1: In use AD conversion, write "1" to the ADMOD bit, wait for 3μs during which time the internal reference voltage should stabilize, and then start AD conversion or external trigger by setting ADMOD0 or to "1". Note 2: Set to "0" to go into standby mode upon completion of AD conversion. Note 3: The external trigger cannot be used for H/W activation of normal AD conversion when it is used for H/W activation of highest-priority AD conversion. Note 4: If it is necessary to reduce a power current with IDLE or STOP mode and if either case shown below is applicable, you must first suspend the AD converter and then execute the instruction to put into standby mode. 1. In the case of putting into IDLE mode with ADMOD1 = "0". 2. In the case of putting into STOP mode. Page 599 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.5 ADMOD2 (Mode Control Register 2) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 bit symbol HPADCH After reset Bit 0 0 Bit Symbol ADCH 0 0 Type 0 0 Function 31-8 − R Read as 0. 7-4 HPADCH[3:0] R/W Select analog input channels in highest-priority AD conversion. (See Table 19-1.) (prohibit "1100 to 1111") 3-0 ADCH[3:0] R/W Select analog input channels in normal AD conversion. (See Table 19-1.) (prohibit "1100 to 1111") Table 19-1 Selection of input channels in normal AD conversion or highest-priority AD conversion Analog input channels 2013/6/11 Analog input channels in highest-priority AD conversion 0000 AIN00 0000 AIN00 0001 AIN01 0001 AIN01 0010 AIN02 0010 AIN02 0011 AIN03 0011 AIN03 0100 AIN04 0100 AIN04 0101 AIN05 0101 AIN05 0110 AIN06 0110 AIN06 0111 AIN07 0111 AIN07 1000 AIN08 1000 AIN08 1001 AIN09 1001 AIN09 1010 AIN10 1010 AIN10 1011 AIN11 1011 AIN11 Page 600 in normal AD conversion TMPM366FDXBG/FYXBG/FWXBG 19.3.6 ADMOD3 (Mode Control Register 3) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 - - REPEAT SCAN 0 0 0 0 bit symbol - After reset 0 Bit Bit Symbol ITM 0 0 0 Type Function 31-7 − R Read as 0. 6-4 ITM[2:0] R/W Specify interrupt in fixed channel repeat conversion mode. See Table 19-2. 3-2 − R Read as 0. 1 REPEAT R/W Specify repeat mode 0 : Single conversion mode 1 : Repeat conversion mode 0 SCAN R/W Specify scan mode 0 : Fixed channel mode 1 : Channel scan mode Table 19-2 AD conversion interrupt specification in fixed channel repeat conversion mode Fixed channel repeat conversion mode = "0", = "1" 000 Generate in interrupt once every single conversion. 001 Generate interrupt once every 2 conversions. 010 Generate interrupt once every 3 conversions. 011 Generate interrupt once every 4 conversions. 100 Generate interrupt once every 5 conversions. 101 Generate interrupt once every 6 conversions. 110 Generate interrupt once every 7 conversions. 111 Generate interrupt once every 8 conversions. Note 1: is valid only when it’s specified in the fixed channel repeat mode, ="1" and = "0". Note 2: When repeat conversion is aborted during repeat conversion (in =1, fixed channel mode or channel scan mode), is "0" cleared. In such case, do not change the setting except bit. Page 601 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.7 ADMOD4 (Mode Control Register 4) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 bit symbol After reset Bit SCANAREA 0 Bit Symbol 0 SCANSTA 0 0 0 Type 0 Function 31-8 − R Read as 0. 7-4 SCANAREA [3:0] R/W Range of channel scan (prohibit "1100 to 1111") 3-0 SCANSTA[3:0] R/W Select the start channel to be scanned. (prohibit "1100" to "1111") To specify channel scan single mode, set ADMOD3 to "1" and to "0". And, to specify channel scan repeat mode, set ADMOD3 to "1" and to "1". At first, select the start channel to be scanned. Then select the number of channels to be scanned, starting on the specified start channel. For example, when ADMOD4 is set to "0001"(AIN01) and is set to "0010" (3ch scan), three channels from AIN01 to AIN03 are scanned. The following shows the range of assignable value to in relation to setting of . Table 19-3 The range of assignable channel scan value The start channel to be scanned The range of assignable channel scan value 0000 AIN00 0000 to 1011 (1ch to 12ch) 0001 AIN01 0000 to 1010 (1ch to 11ch) 0010 AIN02 0000 to 1001 (1ch to 10ch) 0011 AIN03 0000 to 1000 (1ch to 9ch) 0100 AIN04 0000 to 0111 (1ch to 8ch) 0101 AIN05 0000 to 0110 (1ch to 7ch) 0110 AIN06 0000 to 0101 (1ch to 6ch) 0111 AIN07 0000 to 0100 (1ch to 5ch) 1000 AIN08 0000 to 0011 (1ch to 4ch) 1001 AIN09 0000 to 0010 (1ch to 3ch) 1010 AIN10 0000 to 0001 (1ch to 2ch) 1011 AIN11 0000 (1ch) Note:In case of a setting other than listed above, AD conversion is not activated even if ADMOD0 register is set to activate AD conversion. 2013/6/11 Page 602 TMPM366FDXBG/FYXBG/FWXBG 19.3.8 ADMOD5 (Mode Control Register 5) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - HPEOCF HPADBF EOCF ADBF After reset 0 0 0 0 0 0 0 0 Bit Bit Symbol Type Function 31-4 − R Read as 0. 3 HPEOCF R Highest-priority AD conversion completion flag (Note1) 0: Before or during conversion 1: Completion 2 HPADBF R Highest-priority AD conversion BUSY flag 0: During conversion halts 1: During conversion 1 EOCF R Normal AD conversion completion flag (Note1) 0: Before or during conversion 1: Completion 0 ADBF R Normal AD conversion BUSY flag 0: During conversion halts 1: During conversion Note 1: This flag is "0" cleared by reading the ADMOD5 register. Note 2: If it is necessary to reduce a power current with IDLE or STOP mode and if either case shown below is applicable, you must first stop the AD converter and then execute the instruction to put into standby mode. 1. In the case of putting into IDLE mode with ADMOD1 = "0". 2. In the case of putting into STOP1/STOP2 mode. Page 603 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.9 ADMOD6 (Mode Control Register 6) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 1 7 6 5 4 3 2 bit symbol - - - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type 0 ADRST 0 0 Function 31-2 − R Read as 0. 1-0 ADRST[1:0] W Overwriting 10 with 01 allows ADC to be software reset. Note 1: When DMA transmission is executed by using AD conversion completion interrupt, software reset ADMOD6 first, and then operate DMAC(DMA request standby state) and configure (activate) the ADC. Note 2: Initialization takes 3μs in case of the software reset. 2013/6/11 Page 604 TMPM366FDXBG/FYXBG/FWXBG 19.3.10 ADMOD7 (Mode Control Register7) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - After reset 0 0 0 0 0 0 Bit Bit Symbol Type INTADHP DMA 0 INTADDMA 0 Function 31-4 − R Read as 0. 3-2 − R/W Always write "0". 1 INTADHPDMA R/W Specify Highest-priority AD conversion DMA activation factor. 0 : Disable 1 : Enable 0 INTADDMA RW Specify normal AD conversion DMA activation factor. 0 : Disable 1 : Enable Page 605 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.11 ADCMPCR0 (Monitor Control Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 1 0 0 0 bit symbol - - - - After reset 0 0 0 0 0 0 7 6 5 4 3 2 bit symbol CMP0EN - - ADBIG0 After reset 0 0 0 0 Bit Bit Symbol Type CMPCNT0 AINS0 0 0 Function 31-12 − R Read as "0". 11-8 CMPCNT0[3:0] R/W Number of comparison until the judgment is confirmed. An interrupt is generated when the number of the counts is achieved. 7 CMP0EN R/W 0000 : 1 time count 0110 : 7 times count 1100 : 13 times count 0001 : 2 times count 0111 : 8 times count 1101 : 14 times count 0010 : 3 times count 1000 : 9 times count 1110 : 15 times count 0011 : 4 times count 1001 : 10 times count 1111 : 16 times count 0100 : 5 times count 1010 : 11 times count 0101 : 6 times count 1011 : 12 times count AD monitor function 0 0: Disable 1: Enable Setting the condition ="0" (disabled) clears the number of counts. 6-5 − R Read as "0". 4 ADBIG0 R/W Set the determination for small and large. 0: Larger than comparison register 1: Smaller than comparison register Every time when the AD conversion set to is completed, compare the size of conversion results. If the result matches the settings of , the counter is incremented. 3-0 AINS0[3:0] R/W Set analog inputs as a target for comparison. 0000 : AIN00 0101 : AIN05 1010 : AIN10 0001 : AIN01 0110 : AIN06 1011 : AIN11 0010 : AIN02 0111 : AIN07 0011 : AIN03 1000 : AIN08 0100 : AIN04 1001 : AIN09 Prohibit "1100" to "1111". Note:AD monitor function is used the fixed repeat mode and the scan repeat mode. 2013/6/11 Page 606 TMPM366FDXBG/FYXBG/FWXBG 19.3.12 ADCMPCR1 (AD Monitor Control Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 1 0 0 0 bit symbol - - - - After reset 0 0 0 0 0 0 7 6 5 4 3 2 bit symbol CMP1EN - - ADBIG1 After reset 0 0 0 0 Bit Bit Symbol Type CMPCNT1 AINS1 0 0 Function 31-12 − R Read as 0. 11-8 CMPCNT1[3:0] R/W Number of comparison until the judgment is confirmed. An interrupt is generated when the number of the counts is achieved. 7 CMP1EN R/W 0000 : 1 time count 0110 : 7 times count 1100 : 13 times count 0001 : 2 times count 0111 : 8 times count 1101 : 14 times count 0010 : 3 times count 1000 : 9 times count 1110 : 15 times count 0011 : 4 times count 1001 : 10 times count 1111 : 16 times count 0100 : 5 times count 1010 : 11 times count 0101 : 6 times count 1011 : 12 times count AD monitor function 1 0: Disable 1: Enable Setting the condition ="0" (disabled) clears the number of counts. 6-5 − R Read as 0. 4 ADBIG1 R/W Set the determination for small and large. 0: Larger than comparison register 1: Smaller than comparison register Every time when the AD conversion set to is completed, compare the size of conversion results. If the result matches the settings of , the counter is incremented. 3-0 AINS1[3:0] R/W Set analog inputs as a target for comparison. 0000 : AIN00 0101 : AIN05 1010 : AIN10 0001 : AIN01 0110 : AIN06 1011 : AIN11 0010 : AIN02 0111 : AIN07 0011 : AIN03 1000 : AIN08 0100 : AIN04 1001 : AIN09 Prohibit "1100" to "1111". Note:AD monitor function is used the fixed repeat mode and the scan repeat mode. Page 607 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.13 ADCMP0 (AD Conversion Result Comparison Register 0) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 3 2 1 0 0 0 0 0 bit symbol - - - - After reset 0 0 0 0 7 6 5 4 bit symbol After reset Bit AD0CMP AD0CMP 0 Bit Symbol 0 0 0 Type Function 31-12 − R Read as 0. 11-0 AD0CMP[11:0] W Sets a value to be compared with the value of the conversion result register Note:To write values into this register, the AD monitor function 0 must be disabled (ADCMPCR0 ="0"). 2013/6/11 Page 608 TMPM366FDXBG/FYXBG/FWXBG 19.3.14 ADCMP1 (AD Conversion Result Comparison Register 1) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 3 2 1 0 0 0 0 0 bit symbol - - - - After reset 0 0 0 0 7 6 5 4 bit symbol After reset Bit AD1CMP AD1CMP 0 Bit Symbol 0 0 0 Type Function 31-12 − R Read as 0. 11-0 AD1CMP[11:0] W Sets a value to be compared with the value of the conversion result register Note:To write values into this register, the AD monitor function 1 must be disabled (ADCMPCR1 ="0"). Page 609 2013/6/11 19. 19.3 Analog/Digital Converter (ADC) Registers TMPM366FDXBG/FYXBG/FWXBG 19.3.15 ADREG00 to ADREG11 (Normal Conversion Result Register 00 to 11) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - ADPOSWF ADOVRF ADRF After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 bit symbol ADR After reset Bit ADR 0 Bit Symbol 0 0 0 Type Function 31-15 − R Read as 0. 14 ADPOSWF R The output switching flag of AIN port. 0: Without switching 1: With switching When PxDATA register of general input-output port which is also used as AIN changes during AD conversion, the port output switching flag, , is set to "1". In this case, when PxCR register corresponding to the changed bit is "1", there is a possibility that the output switching during AD conversion affects conversion accuracy. This bit is "0" cleared when registers, ADREG00 through ADREG11, are read. 13 ADOVRF R Overrun flag 0: Not generated. 1: Generated. If the conversion result is overwritten before reading , this bit is set to "1". This bit is "0" cleared when registers, ADREG00 through ADREG11, are read. 12 ADRF R AD conversion result storage flag 0: Conversion result is not stored 1: Conversion result is stored. If the conversion result is stored, this bit is set to "1". This bit is "0" cleared when the conversion result of register, ADREG00 through ADREG11, are read. 11-0 ADR[11:0] R AD conversion result Conversion result is stored. For information about the correlation between the conversion channel and the conversion result register, refer to Table 19-5, chapter 19.4.5.7. Note:Do not do the output switching during AD conversion, when other analog / input-output ports are used as output port. 2013/6/11 Page 610 TMPM366FDXBG/FYXBG/FWXBG 19.3.16 ADREGSP (Highest-priority Conversion Result Register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ADOVRFSP ADRFSP ADPO bit symbol - After reset 0 0 0 0 7 6 5 4 SWFSP bit symbol 0 0 0 0 3 2 1 0 0 0 0 0 ADRSP After reset Bit ADRSP 0 Bit Symbol 0 0 0 Type Function 31-15 − R Read as 0. 14 ADPOSWFSP R The output switching flag of AIN port. 0: Without switching 1: With switching When PxDATA register of general input-output port which is also used as AIN changes during AD conversion, the port output switching flag, , is set to "1". In this case, when PxCR register corresponding to the changed bit is "1", there is a possibility that the output switching during AD conversion affects conversion accuracy. This bit is "0" cleared when registers, ADREGx is read. 13 ADOVRFSP R Overrun flag 0: Not generated 1: Generated If the highest-priority AD conversion result is overwritten before reading , "1" is set. This bit is "0" cleared when ADREGSP register is read. 12 ADRFSP R Highest-priority AD conversion result storage flag 0: Conversion result is not stored. 1: Conversion result is stored. If the highest-priority conversion result is stored, this bit is set to "1". This bit is "0" cleared when ADREGSP conversion result is read. 11-0 ADRSP[11:0] R Highest-priority AD conversion result Highest-priority conversion result is stored. Note:Do not do the output switching during AD conversion, when other analog / input-output ports are used as output port. Page 611 2013/6/11 19. 19.4 Analog/Digital Converter (ADC) Description of Operations 19.4 TMPM366FDXBG/FYXBG/FWXBG Description of Operations 19.4.1 Analog Reference Voltage The "High" level of the analog reference voltage shall be applied to the AVRFEH pin, and the "Low" shall be applied to the AVREFL pin. To start AD conversion, make sure that you first write "1" to the bit, wait for 3 μs during which time the internal reference voltage should stabilize, and then write "1" to the ADMOD0 bit. 19.4.2 AD Conversion Mode Two types of AD conversion are supported: normal AD conversion and highest-priority AD conversion. 19.4.2.1 Normal AD Conversion For normal AD conversion, the following four operation modes are supported and the operation mode is selected with the ADMOD3. ・ ・ ・ ・ (1) Fixed channel single conversion mode Channel scan single conversion mode Fixed channel repeat conversion mode Channel scan repeat conversion mode Fixed channel single conversion mode If ADMOD3 is set to "00", "AD conversion is performed in the fixed channel single conversion mode. In this mode, AD conversion is performed once for one channel selected by ADMOD2 . After AD conversion is completed, ADMOD5 is set to "1", ADMOD5 is cleared to "0", and the AD conversion completion interrupt request (INTAD) is generated. is cleared to "0" upon read. (2) Channel scan single conversion mode If ADMOD3 is set to "01," AD conversion is performed in the channel scan single conversion mode. In this mode, AD conversion is performed once for the scan channel area selected by ADMOD4 from the start channel selected by ADMOD4 . After AD scan conversion is completed, ADMOD5 is set to "1", ADMOD5 is cleared to "0", and the conversion completion interrupt request (INTAD) is generated. is cleared to "0" upon read. (3) Fixed channel repeat conversion mode If ADMOD3 is set to "10", AD conversion is performed in fixed channel repeat conversation mode. In this mode, AD conversion is performed repeatedly for one channel selected by ADMOD2 . After AD conversion is completed, ADMOD5 is set to "1". ADMOD5 is not cleared to "0". It remains at "1". The timing with which the conversion completion interrupt re- 2013/6/11 Page 612 TMPM366FDXBG/FYXBG/FWXBG quest (INTAD) is generated can be selected by setting ADMOD3 to an appropriate setting. is set with the same timing as this interrupt INTAD is generated. is cleared to "0" upon read. (4) Channel scan repeat conversion mode If ADMOD3 is set to "11", AD conversion is performed in the channel scan repeat conversion mode. In this mode, AD conversion is performed repeatedly for the scan channel area selected by ADMOD4 from the start channel selected by ADMOD4 . Each time one AD scan conversion is completed, ADMOD5 is set to "1", and the conversion completion interrupt request (INTAD) is generated. ADMOD5 is not cleared to "0" and remains at "1". is cleared to "0" upon read. 19.4.2.2 Highest-priority AD conversion By interrupting ongoing normal AD conversion, highest-priority AD conversion can be performed. The fixed-channel single conversion is automatically selected, irrespective of the ADMOD3 setting. When conditions to start operation are met, a conversion is performed just once for a channel selected by ADMOD2. When conversion is completed, the highest-priority AD conversion completion interrupt (INTADHP) is generated, and ADMOD5 showing the completion of AD conversion is set to "1". returns to "0". flag is cleared to "0" upon read. Highest-priority AD conversion activated while highest-priority AD conversion is under way is ignored. 19.4.3 AD Monitor Function This is a function for setting the channel fixed repeat mode and the scan repeat mode. Setting "1" to both ADCMPCR0 and ADCMPCR1 enables the AD monitor function. The monitor function can also be enabled for both registers at the same time. Here is an example, taking the ADCMPCR0. Configure the following settings: analog input as a target for comparison to the of the ADCMPCR0 register, large/small determination to the and the number of counts in determination to the . Once AD conversion starts, every time when one single conversion completes, large/small determination is performed. If the result of the conversion matches the settings stored in the , increment the judgment counter. AD monitor function interrupts (INTADM0) are generated when conditions set to the pile up and reach the counting number set to the . The counter values are held even the condition is different from that is set to the . If values of the conversion result storage register set to the ADCMPCR0 are the same as the values of a register as a comparison target, the count is not incremented. AD monitor function interrupt (INTADM0) is not generated. This comparison is performed every time when a result is stored to the conversion result storage register, and an interrupt (INTADM0) occurs when a condition matches. Since the storage register used as AD monitor function is not usually read using software, registers correspond to overrun flags, from ADREG00 to 14, and conversion result storage flags, from ADREG00 to 14, are always set to "1". Thus, do not use those flags of the conversion result storage register when you use the AD monitor function. Example : Set AIN00 input as fixed channel repeat conversion. Compare values of the AD conversion result comparison register (0x0888). Page 613 2013/6/11 19. 19.4 Analog/Digital Converter (ADC) Description of Operations TMPM366FDXBG/FYXBG/FWXBG ・ ADMOD3=0x0002： fixed channel repeat conversion Note: AD conversion completion interrupt (INTAD) is disabled. ・ ADCMPCR0 =0x02A0： target channel for comparison: AIN00, large/small determination: larger than the comparison register, AD monitor function: enabled, counting number of large/small determination: three counts. ・ ADCMP0=0x0888: AD conversion result comparison register (comparison value 0x0888） Conversion result 0x0FFF Interrupt is generated. ADCMPCRx =0x0888 The counter is kept. The counter is incremented. The counter is kept. The counter is incremented. The counter is incremented. The counter is incremented. The counter is incremented. The counter is incremented. 0x0 1st counter: 0 2nd counter: 1 3rd counter: 1 4th counter: 2 5th counter: 3 6th counter: 4 7th counter: 5 8th counter: 6 Number of conversion Counter value Figure 19-3 AD monitor function (Fixed channel repeat) 19.4.4 Selecting the Input Channel After reset, ADMOD3 is initialized to "00" and ADMOD2 is initialized to "0000". The channels to be converted are selected according to the operation mode of the AD converter as shown below. 1. Normal AD conversion mode ・ If the analog input channel is used in a fixed state (ADMOD3 = "0") One channel is selected from analog input pins AIN00 through AIN11 by setting ADMOD2 to an appropriate setting ・ If the analog input channel is used in a scan state (ADMOD3 = "1") The channel to be started can be specified by setting ADMOD4 . And, the number of channels to be scanned can be specified by setting ADMOD4 . 2. Highest-priority AD conversion mode One channel is selected from analog input pins from AIN00 through AIN11 by setting ADMOD2 to an appropriate setting. If highest-priority AD conversion has been activated during normal AD conversion, ongoing normal AD conversion is suspended, and restarts normal AD conversion after highest-priority AD conversion is completed. 2013/6/11 Page 614 TMPM366FDXBG/FYXBG/FWXBG 19.4.5 AD Conversion Details 19.4.5.1 Starting AD Conversion Two types of A/D conversion are supported: normal AD conversion and top-priority AD conversion. Normal AD conversion is activated by setting ADMOD0 to "1". Highest-priority AD conversion is activated by setting ADMOD0 to "1". Four operation modes are made available to normal AD conversion. In performing normal AD conversion, one of these operation modes must be selected by setting ADMOD3 to an appropriate setting. For highest-priority AD conversion, only one operation mode can be used: fixed channel single conversion mode. Normal AD conversion can be activated using the H/W activation source selected by ADMOD1, and highest-priority AD conversion can be activated using the HW activation source selected by ADMOD1. If bits of and are "0", normal and highestpriority AD conversions are activated in response to the input of a falling edge through the ADTRG pin. If these bits are "1", normal AD conversion is activated in response to INTCAP50 generated by the 16bit timer channel 5, and highest-priority AD conversion is activated in response to INTCAP40 generated by the 16-bit timer channel 4. To permit H/W activation, set ADMOD1 to "1" for normal AD conversion and set ADMOD1 to "1" for highest-priority AD conversion. Software activation is still valid even after H/W activation has been permitted. Note:When an external trigger is used for the HW activation source of a highest-priority AD conversion, an external trigger cannot be set for activating normal AD conversion H/W start. 19.4.5.2 AD Conversion When normal AD conversion starts, the AD conversion Busy flag (ADMOD5 ) showing that AD conversion is under way is set to "1". When highest-priority AD conversion starts, the highest-priority AD conversion Busy flag (ADMOD5 ) showing that AD conversion is under way is set to "1". At that time, the value of the Busy flag ADMOD5 for normal AD conversion before the start of highest-priority AD conversion is retained. The value of the conversion completion flag ADMOD5 for normal AD conversion before the start of highest-priority AD conversion is retained. Note:Normal AD conversion must not be activated when highest-priority AD conversion is under way. If activated when highest-priority AD conversion is under way, the highest-priority AD conversion completion flag cannot be set, and the flag for previous normal A/D conversion cannot be cleared. Page 615 2013/6/11 19. 19.4 Analog/Digital Converter (ADC) Description of Operations 19.4.5.3 TMPM366FDXBG/FYXBG/FWXBG Highest-priority AD conversion requests during normal AD conversion If highest-priority AD conversion has been activated during normal AD conversion, ongoing normal AD conversion is suspended, and restarts normal AD conversion after highest-priority AD conversion is completed. If ADMOD0 is set to "1" during normal AD conversion, ongoing normal AD conversion is suspended, and the highest-priority AD conversion starts; specifically, AD conversion (fixed-channel single conversion) is executed for a channel designated by ADMOD2. After the result of this highestpriority AD conversion is stored in the storage register ADREGSP, normal AD conversion is resumed. If H/W activation of highest-priority AD conversion is authorized during normal AD conversion, ongoing AD conversion is discontinued when requirements for activation using a H/W activation resource are met, and highest-priority AD conversion (fixed-channel single conversion) starts for a channel designated by ADMOD2. After the result of this highest-priority AD conversion is stored in the storage register ADREGSP, normal AD conversion is resumed. For example, if channel repeat conversion is activated for channels AIN00 through AIN03 and if is set to "1" during AIN02 conversion, AIN02 conversion is suspended, and conversion is performed for a channel designated by (AIN11 in the case shown below). After the result of conversion is stored in ADREGSP, channel repeat conversion is resumed, starting from AIN02. Highest-priority AD has been activated Conversion Ch 19.4.5.4 Ch0 Ch1 Ch2 Ch11 Ch2 Ch3 Ch0 Stopping Repeat Conversion Mode To stop the AD conversion operation in the repeat conversion mode (fixed-channel repeat conversion mode or channel scan conversion mode), write "0" to ADMOD3. When ongoing AD conversion is completed, the repeat conversion mode terminates, and ADMOD5 is set to "0". 2013/6/11 Page 616 TMPM366FDXBG/FYXBG/FWXBG 19.4.5.5 Reactivating normal AD conversion If ADMOD0 is set to "1" during normal AD conversion, normal AD conversion is reactivated. Ongoing normal AD conversion is suspended at the time that it is reactivated. At that time, the normal AD conversion Busy flag ADMOD5 , the normal AD conversion completion flag ADMOD5 and the storage result flag ADREGm , are cleared to "0". (m=00-11) If H/W activation of normal AD conversion is authorized during normal AD conversion, ongoing AD conversion is discontinued when requirements for activation using a H/W activation resource are met. Ongoing normal AD conversion is suspended at the time that it is reactivated. At that time, the normal AD conversion Busy flag ADMOD5 , the normal AD conversion completion flag ADMOD5 and the storage result flag ADREGm , are cleared to "0". (m=00-11) 19.4.5.6 Conversion completion (1) Normal AD conversion completion When normal AD conversion is completed, the AD conversion completion interrupt (INTAD) is generated. The result of AD conversion is stored in the storage register, and two registers change: the register ADMOD5 which indicates the completion of AD conversion and the register ADMOD5. The timing that interrupt request is generated and the timing that conversion result register changes vary according to a mode selected. In mode other than fixed-channel repeat conversion mode, conversion results are stored in AD conversion result registers (ADREG00 through ADREG11) corresponding to a channel. In fixed-channel repeat conversion mode, the conversion results are sequentially stored in storage registers ADREG00 through ADREG11. However, if interrupt setting on is set to be generated each time one AD conversion is completed, the conversion result is stored only in ADREG00. If interrupt setting on is set to be generated each time 8 AD conversions are completed, the conversion results are sequentially stored in ADREG00 through ADREG07. Interrupt requests, flag changes and conversion result registers in each mode are as shown below. ・ Fixed-channel single conversion mode After AD conversion is completed, ADMOD5 is set to "1", ADMOD5 is cleared to "0", and the interrupt request INTAD is generated. Conversion results are stored a conversion result register correspond to a channel. ・ Channel scan single conversion mode After the channel scan conversion is completed, ADMOD5 is set to "1", ADMOD5 is cleared to "0", and the interrupt request INTAD is generated. Conversion results are stored a conversion result register correspond to a channel. ・ Fixed-channel repeat conversion mode ADMOD5 is not cleared to "0". It remains at "1". The timing with which the interrupt request INTAD is generated can be selected by setting ADMOD3 to an appropriate setting. ADMOD5 is set with the same timing as this interrupt INTAD is generated. a. One conversion With ADMOD2 set to "0000" (AIN00) and ADMOD3 set to "000", an interrupt request is generated each time one AD conversion is completed. In this case, the conversion results are always stored in the storage register ADREG00. After the conversion result is stored, is set to "1". b. 8 conversions Page 617 2013/6/11 19. 19.4 Analog/Digital Converter (ADC) Description of Operations TMPM366FDXBG/FYXBG/FWXBG With ADMOD2 set to "1011" (AIN11) and ADMOD3 set to "111", an interrupt request is generated each time 8 AD conversions are completed. In this case, the conversion results are sequentially stored in the storage register ADREG00 through ADREG07. After the conversion result is stored in ADREG07, is set to "1", and the storage of subsequent conversion results starts from ADREG00. ・ Channel scan repeat conversion mode Each time one AD conversion is completed, ADMOD5 is set to "1" and an interrupt request INTAD is generated. ADMOD5 is not cleared to "0". It remains at "1". If ADMOD4 is set to "0001" (AIN01) and ADMOD4 is set to "1110" (11Ch scan), each time one AD conversion is completed, ADMOD5 is set to "1" and an interrupt request INTAD is generated. ADMOD5 is not cleared to "0" and remains at "1". AD conversion results are stored in a AD conversion result register corresponding to a channel. (2) Highest-priority AD conversion completion After the highest-priority AD conversion is completed, the highest-priority AD conversion completion interrupt (INTADHP) is generated, and ADMOD5 which indicates the completion of highest-priority AD conversion is set to "1". AD conversion results are stored in the AD conversion result register ADREGSP. (3) Data polling To confirm the completion of AD conversion without using interrupts, data polling can be used. When AD conversion is completed, ADMOD5 is set to "1". To confirm the completion of AD conversion and to obtain the results, poll this bit. AD conversion result storage register must be read by word access. If = “0”, = “1” and = “0”, a correct conversion result has been obtained. (4) DMA request After the normal AD conversion completion interrupt (INTAD) or the highest-priority AD conversion completion interrupt (INTADHP) is generated , DMA request is issued. DMA request after any interrupt is generated can be set to "disable" or "enable" by setting ADMOD7 register to an appropriate setting. A DMA request is issued in 2 system clocks (fsys) after AD conversion completion interrupt (INTAD or INTADHP) is generated. 2013/6/11 Page 618 TMPM366FDXBG/FYXBG/FWXBG 19.4.5.7 Interrupt generation timings and AD conversion result storage register Table 19-4 shows a relation in the following three items: AD conversion modes, interrupt generation timings and flag operations. Table 19-5 shows a relation between analog channel inputs and AD conversion result registers. Table 19-4 Relations in conversion modes, interrupt generation timings and flag operations ADMOD3 Conversion mode ADMOD5 Interrupt generation timing / (After the (After the set timing interrupt is generated) interrupt is generated) (See note) Fixed-channel single conversion Fixed-channel repeat conversion 0 1 0 Channel scan single conversion Channel scan repeat conversion Highest-priority conversion 0 − After generation is completed. After generation is completed. 0 − 000 Each time one conversion is completed. After one conversion is completed. 1 − 001 Each time 2 conversion is completed. After 2 conversions are completed. 1 − 010 Each time 3 conversion is completed. After 3 conversions are completed. 1 − 011 Each time 4 conversion is completed. After 4 conversions are completed. 1 − 100 Each time 5 conversion is completed. After 5 conversions are completed. 1 − 101 Each time 6 conversion is completed. After 6 conversions are completed. 1 − 110 Each time 7 conversion is completed. After 7 conversions are completed. 1 − 111 Each time 8 conversion is completed. After 8 conversions are completed. 1 − After scan conversion is completed. 0 − 0 Normal conversion 1 − After scan conversion is completed. 1 1 − After one scan conversion is completed. After one scan conversion is completed. 1 − − − − After generation is completed. Conversion completion − 0 Note 1: ADMOD5 and are cleared upon read. Note 2: In repeat mode, ADMOD5 is not cleared to "0" even if any interrupt is generated. To suspend the repeat operation, ADMOD5 is cleared to "0" after ADMOD3 is written "0" and AD conversion is completed. Page 619 2013/6/11 19. 19.4 Analog/Digital Converter (ADC) Description of Operations TMPM366FDXBG/FYXBG/FWXBG Table 19-5 Relations between analog channel inputs and AD conversion result registers Fixed-channel Fixed-channel single mode repeat mode Channel Storage register Storage register AIN00 ADREG00 000 Interrupt by each time AD/C ADREG00 AIN01 ADREG01 001 Interrupt by each time 2 AD/C ADREG00 to ADREG01 AIN02 ADREG02 010 Interrupt by each time 3 AD/C ADREG00 to ADREG02 AIN03 ADREG03 011 Interrupt by each time 4 AD/C ADREG00 to ADREG03 AIN04 ADREG04 100 Interrupt by each time 5 AD/C ADREG00 to ADREG04 AIN05 ADREG05 101 Interrupt by each time 6 AD/C ADREG00 to ADREG05 AIN06 ADREG06 110 Interrupt by each time 7 AD/C ADREG00 to ADREG06 AIN07 ADREG07 111 Interrupt by each time 8 AD/C ADREG00 to ADREG07 AIN08 ADREG08 AIN09 ADREG09 AIN10 ADREG10 AIN11 ADREG11 ADMOD3 Channel scan single mode / repeat mode ADMOD4 ADMOD4 (Starts channel) (Scan channel range) AIN00 12 channels ADREG00 to ADRE11 AIN01 11 channels ADREG01 to ADRE11 AIN02 10 channels ADREG02 to ADRE11 AIN03 9 channels ADREG03 to ADRE11 AIN04 8 channels ADREG04 to ADRE11 AIN05 7 channels ADREG05 to ADRE11 AIN06 6 channels ADREG06 to ADRE11 AIN07 5 channels ADREG07 to ADRE11 AIN08 4 channels ADREG08 to ADRE11 AIN09 3channels ADREG09 to ADRE11 AIN10 2 channels ADREG10 to ADRE11 AIN11 1 channels ADREG11 to ADRE11 Storage register Note:When the range of channel scan is set to out of the assignable value in channel scan mode, the AD conversion can not be activated even if ADMOD0 is set to activate AD conversion. 2013/6/11 Page 620 TMPM366FDXBG/FYXBG/FWXBG Notes on designing for AD converter inputs An output impedance of the external signal source which is connected with AIN pin is equal or less than REXAIN shown below formula. - Calculating formula of allowable value of output impedance of the external signal source The maxmum value of an output impedance connected with AIN pin : REXAIN < Tscyc ÷ (ADCLK × CADC × ln (214)) − RAIN MCU information Symbol Min Typ Max Unit ADC clock frequency ADCLK 4 - 40 MHz Total AIN input capacity in MCU CADC - - 12.2 pF AIN resistance in MCU RAIN - - 1 kΩ Cycle number in the sample hold period Tscyc 10 - 80 Cycle REXAIN maximum value list ( ADCLK = 40MHz ) Tcsyc REXAIN Unit 10 1.1 kΩ 20 3.2 kΩ 30 5.3 kΩ 40 7.5 kΩ 80 15.9 kΩ < Addition of stabilizing capacity > If high-speed AD conversion is required and the sample hold period cannot meet the conditions of calculating formula of allowable values of output impedance of external signal source, add stabilizing capacity to the AIN pin. The additional capacity depends on external circuitd. Although the capacity depended on the external circuit is different from the each board set, add the capacity from about 0.1μF to 1μF, appropriate amount for your circuit board. Set the capacity to be added next to the AIN pin. < Adjustment of sample hold period> Generally, by setting the sample hold period long, you can make the input voltage of the comparator in the ADC circuit as same as the input voltage of the AIN pin can reduce the error of an AD conversion. Although, in case that the sample hold period is too long, the error of an AD conversion may be increased because the voltage held in sample hold circuit is changed. Because the suitable sample hold period is depended on the each board set, please decided the suitable sample hold period on your board set. Cautions for use AD converter The result value of AD conversion may vary depending on the fluctuation of the supply voltage, or may be affected by noise. When using analog input pins and ports alternately, do not read and write ports during conversion because the conversion accuracy may be reduced. Also the conversion accuracy may be reduced if the output ports current fluctuate during AD conversion. Please take counteractive measures with the program such as averaging the AD conversion results. Page 621 2013/6/11 19. 19.4 Analog/Digital Converter (ADC) Description of Operations 19.4.5.8 TMPM366FDXBG/FYXBG/FWXBG The way of stopping ADC in the low power consumption mode When ADC is stopped in the low power consumption mode, it is stopped by the following order. 1. ADC is stopped in the state of ADMOD1="1". 2. ADCLK is set to "010" (ADCLK=fc/4) or "100" (ADCLK=fc/8). 3. Make ADC initialize by a software reset (ADMOD6="10" → "01"). 4. The CPU enters in the low power consumption mode. 2013/6/11 Page 622 TMPM366FDXBG/FYXBG/FWXBG 20. Flash Memory Operation This section describes the hardware configuration and operation of the flash memory. 20.1 Flash Memory 20.1.1 Features 1. Memory capacity The TMPM366FDXBG/FYXBG/FWXBG devices contain flash memory. The memory sizes and configurations of each device are shown in the table below. Independent write access to each block is available. When the CPU is to access the internal flash memory, 32-bit data bus width is used. 2. Write/erase time Writing is executed per page. The TMPM366FDXBG/FYXBG/FWXBG contain 128 words. Page writing requires 1.25ms (typical) regardless of number of words. A block erase requires 0.1 sec. (typical). The following table shows write and erase time per chip. Note: Product Name Memory Size TMPM366FDFG 512 KB Block Configuration 128 KB 64 KB 32 KB 16 KB Number of Words Write Time Erase Time 3 1 2 − 128 1.28 sec 0.4 sec The above values are theoretical values not including data transfer time. The write time per chip depends on the write method to be used by the user. 3. Programming method There are two types of the onboard programming mode for the user to program (rewrite) the device while it is mounted on the user's board: ・ The onboard programming mode a. User boot mode The user's original rewriting method can be supported. b. Single boot mode The rewriting method to use serial data transfer (Toshiba's unique method) can be supported. 4. Rewriting method The flash memory included in this device is generally compliant with the applicable JEDEC standards except for some specific functions. Therefore, if the user is currently using an external flash mem- Page 623 2013/6/11 20. 20.1 Flash Memory Operation Flash Memory TMPM366FDXBG/FYXBG/FWXBG ory device, it is easy to implement the functions into this device. Furthermore, the user is not required to build his/her own programs to realize complicated write and erase functions because such functions are automatically performed using the circuits already built-in the flash memory chip. JEDEC compliant functions Modified, added, or deleted functions ・ Automatic programming ・ Automatic chip erase Block protect (only software protection is supported) ・ Automatic block erase Erase resume - suspend function ・ Data polling/toggle bit 5. Protect/ Security Function This device is also implemented with a read-protect function to inhibit reading flash memory data from any external writer device. On the other hand, rewrite protection is available only through command-based software programming; any hardware setting method to apply +12VDC is not supported. See the chapter "ROM protection" for details of ROM protection and security function. Note: 2013/6/11 If a password is set to 0xFF (erased data), it is difficult to protect data securely due to an easy-toguess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. Page 624 TMPM366FDXBG/FYXBG/FWXBG 20.1.2 Block Diagram of the Flash Memory Section Internal address bus Internal data bus Internal control bus ROM controller Control Address Data Flash memory Control circuit (includes automatic sequence control) Data latch Column decoder/sense amplifier Row decoder Command register Address latch Flash memory cell Erase block decoder Figure 20-1 Block Diagram of the Flash Memory Section Page 625 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode 20.2 TMPM366FDXBG/FYXBG/FWXBG Operation Mode This device has three operation modes including the mode not to use the internal flash memory. Table 20-1 Operation Modes Operation mode Operation details Single chip mode After reset is cleared, it starts up from the internal flash memory. Normal mode In this operation mode, two different modes, i.e., the mode to execute user application programs and the mode to rewrite the flash memory onboard the user’s card, are defined. The former is referred to as "normal mode" and the latter "user boot mode. User boot mode The user can uniquely configure the system to switch between these two modes. For example, the user can freely design the system such that the normal mode is selected when the port "A0" is set to "1" and the user boot mode is selected when it is set to "0." The user should prepare a routine as part of the application program to make the decision on the selection of the modes. Single boot mode After reset is cleared, it starts up from the internal Boot ROM (Mask ROM). In the Boot ROM, an algorithm to enable flash memory rewriting on the user’s set through the serial port of this device is programmed. By connecting to an external host computer through the serial port, the internal flash memory can be programmed by transferring data in accordance with predefined protocols. Among the flash memory operation modes listed in the above table, the User Boot mode and the Single Boot mode are the programmable modes. These two modes, the User Boot mode and the Single Boot mode, are referred to as "Onboard Programming" modes where onboard rewriting of internal flash memory can be made on the user's card. Either the Single Chip or Single Boot operation mode can be selected by externally setting the level of the BOOT (PF0) pin while the device is in reset status. Table 20-2 Operation Mode Setting Operation mode Pin RESET BOOT (PF0) Single chip mode 0→1 1 Single boot mode 0→1 0 Reset state Single chip mode Single boot mode Normal mode User boot mode Onboard programming mode User to set the switch method Figure 20-2 Mode Transition Diagram 2013/6/11 Page 626 TMPM366FDXBG/FYXBG/FWXBG 20.2.1 Reset Operation To reset the device, ensure that the power supply voltage is within the operating voltage range, that the internal oscillator has been stabilized, and that the RESET input is held at "0" for a minimum duration of 12 system clocks (0.3 μs with 40MHz operation; the "1/1" clock gear mode is applied after reset). Note 1: Regarding cold-reset of devices with internal flash memory; for devices with internal flash memory, it is necessary to apply "0" to the RESET inputs upon power on for a minimum duration of 1.4 milli-seconds regardless of the operating frequency. Note 2: While flash automatic programming or deletion is in progress, at least 0.5 microseconds of reset period is required regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. Page 627 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode 20.2.2 TMPM366FDXBG/FYXBG/FWXBG User Boot Mode (Single chip mode) User Boot mode is to use flash memory programming routine defined by users. It is used when the data transfer buses for flash memory program code on the old application and for serial I/O are different. It operates at the single chip mode; therefore, a switch from normal mode in which user application is activated at the single chip mode to User Boot Mode for programming flash is required. Specifically, add a mode judgment routine to a reset program in the old application. The condition to switch the modes needs to be set by using the I/O of TMPM366FDXBG/FYXBG/ FWXBG in conformity with the user’s system setup condition. Also, flash memory programming routine that the user uniquely makes up needs to be set in the new application. This routine is used for programming after being switched to User Boot Mode. The execution of the programming routine must take place while it is stored in the area other than the flash memory since the data in the internal flash memory cannot be read out during delete/ writing mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. Be sure not to cause any exceptions including a non-maskable while User Boot Mode. (1-A) and (1-B) are the examples of programming with routines in the internal flash memory and in the external memory. For a detailed description of the erase and program sequence, refer to "20.3 On-board Programming of Flash Memory (Rewrite/Erase)". 20.2.2.1 (1-A) Method 1: Storing a Programming Routine in the Flash Memory (1) Step-1 Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMPM366FDXBG/FYXBG/FWXBG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Programming routine: Code to download new program code from a host controller and re-program the flash memory (c) Copy routine: Code to copy the data described in (b) from the TMPM366FDXBG/FYXBG/FWXBG flash memory to either the TMPM366FDXBG/FYXBG/FWXBG on-chip RAM or external memory device. (Host) New Application Program Code TMPM366FDXBG/FYXBG/FWXBG (I/O) Flash memory Old Application Program Code [Reset Procedure] (a) Mode Judgment Routine (b) Programming Routine RAM (c) Copy routine 2013/6/11 Page 628 TMPM366FDXBG/FYXBG/FWXBG (2) Step-2 After RESET is released, the reset procedure determines whether to put the TMPM366FDXBG/ FYXBG/FWXBG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be disabled while in User Boot mode.) (Host) TMPM366FDXBG/FYXBG/FWXBG New Application Program Code (I/O) 0 → 1 RESET Flash memory Old Application Program Code Conditions for entering User Boot mode (defined by the user) [Reset Procedure] (a) Mode Judgment Routine (b) Programming routine RAM (c) Copy routine (3) Step-3 Once transition to User Boot mode is occurred, execute the copy routine (c) to copy the flash programming routine (b) to the TMPM366FDXBG/FYXBG/FWXBG on-chip RAM. (Host) TMPM366FDXBG/FYXBG/FWXBG New Application Program Code (I/O) Flash memory Old Application Program Code [Reset procedure] (b) Programming routine (a) Mode judgment routine (b) Programming routine (c) Copy routine RAM Page 629 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG (4) Step-4 Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. (Host) TMPM366FDXBG/FYXBG/FWXBG New Application Program Code (I/O) Flash memory (Erasd) [Reset procedure] (b) Programming routine (a) Mode judgment routine (b) Programming routine (c) Copy routine (5) RAM Step-5 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user’s program area must be set. (Host) TMPM366FDXBG/FYXBG/FWXBG (I/O) Flash memory New Application Program Code [Reset procedure] (b) Programming࣮ routine (a) Mode judgment routine (b) Programming routine (c) Copy routine 2013/6/11 RAM Page 630 New Application Program Code TMPM366FDXBG/FYXBG/FWXBG (6) Step-6 Set RESET to "0" to reset the TMPM366FDXBG/FYXBG/FWXBG. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. (Host) TMPM366FDXBG/FYXBG/FWXBG (I/O) 0 → 1 RESET Flash memory New application program code Set to normal mode [Reset procedure] (a) Mode judgment routine (b) Programming routine (c) Copy routine RAM Page 631 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode 20.2.2.2 TMPM366FDXBG/FYXBG/FWXBG (1-B) Method 2: Transferring a Programming Routine from an External Host (1) Step-1 Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMPM366FDXBG/FYXBG/FWXBG on a printed circuit board, write the following program routines into an arbitrary flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Transfer routine: Code to download new program code from a host controller Also, prepare a programming routine shown below on the host controller: (c) Programming routine: Code to download new program code from an external host controller and re-program the flash memory (Host) New application program code (c) Programming routine TMPM366FDXBG/FYXBG/FWXBG (I/O) Flash memory Old application program code [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine 2013/6/11 Page 632 TMPM366FDXBG/FYXBG/FWXBG (2) Step-2 After RESET is released, the reset procedure determines whether to put the TMPM366FDXBG/ FYXBG/FWXBG flash memory in User Boot mode. If mode switching conditions are met, the flash memory enters User Boot mode. (All interrupts including NMI must be disabled while in User Boot mode). New application program code (Host) (c) Programming routine TMPM366FDXBG/FYXBG/FWXBG (I/O) 0 → 1 RESET Flash memory Old application program code Conditions for entering User Boot mode (defined by the user) [Reset procedure] (a) Mode judgment routine (b) Transfer routine (3) RAM Step-3 Once User Boot mode is entered, execute the transfer routine (b) to download the flash programming routine (c) from the host controller to the TMPM366FDXBG/FYXBG/FWXBG on-chip RAM. New application Program code (Host) (c) Programming routine TMPM366FDXBG/FYXBG/FWXBG (I/O) Flash memory Old application program code (c) Programming routine [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine Page 633 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG (4) Step-4 Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. (Host) New application program code (c) Programming routine TMPM366FDXBG/FYXBG/FWXBG (I/O) Flash memory (Erasd) (c) Programming routine [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine (5) Step-5 Continue executing the flash programming routine to download new program code from the host controller and program it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user program area must be set. (Host) New application program code (c) Programming routine TMPM366FDXBG/FYXBG/FWXBG (I/O) Flash memory New application Program code (c) Programming routine [Reset procedure] (a) Mode judgment routine RAM (b) Transfer routine 2013/6/11 Page 634 TMPM366FDXBG/FYXBG/FWXBG (6) Step-6 Set RESET to "0" low to reset the TMPM366FDXBG/FYXBG/FWXBG. Upon reset, the on-chip flash memory is put in Normal mode. After RESET is released, the CPU will start executing the new application program code. (Host) TMPM366FDXBG/FYXBG/FWXBG (I/O) 0 → 1 RESET Flash memory New application program code Set to normal mode [Reset procedure] (a) Mode judgment routine (b) Transfer routine RAM Page 635 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode 20.2.3 TMPM366FDXBG/FYXBG/FWXBG Single Boot Mode In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMPM366FDXBG/FYXBG/FWXBG on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it. Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the TMPM366FDXBG/FYXBG/FWXBG is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMPM366FDXBG/FYXBG/FWXBG on-chip RAM. Then, the flash memory is re-programmed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO0 and the host must follow the protocol described later. To secure the contents of the flash memory, the validity of the application’s password is verified before a programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a programming routine itself is aborted. As in the case of User Boot mode, all interrupts including the non-maskable interrupt (NMI) must be disabled in Single Boot mode while the flash memory is being erased or programmed. In Single Boot mode, the boot-ROM programs are executed in Normal mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental corruption during subsequent Single-Chip (Normal mode) operations. 20.2.3.1 (2-A) Using the Program in the On-Chip Boot ROM (1) Step-1 The flash block containing the older version of the program code need not be erased before executing the programming routine. Since a programming routine and programming data are transferred via the SIO (SIO0), the SIO0 must be connected to a host controller. Prepare a programming routine (a) on the host controller. (Host) New application program code (a) Programming routine TMPM366FDXBG/FYXBG/FWXBG Boot ROM (I/O) SIO0 Flash memory Old application program code (or erased state) 2013/6/11 RAM Page 636 TMPM366FDXBG/FYXBG/FWXBG (2) Step-2 Set the RESET pin to "1" to cancel the reset of the TMPM366FDXBG/FYXBG/FWXBG when the BOOT pin has already been set to "0". After reset, CPU reboots from the on-chip boot ROM. The 12-byte password transferred from the host controller via SIO0 is first compared to the contents of the special flash memory locations. (If the flash block has already been erased, the password is 0xFF). (Host) New application program code (a) Programming routine TMPM366FDXBG/FYXBG/FWXBG Boot ROM (I/O) 0 → 1 RESET SIO0 Flash memory 0 BOOT Old application program code (or erased state) (3) RAM Step-3 If the password was correct, the boot program downloads, via the SIO0, the programming routine (a) from the host controller into the on-chip RAM of the TMPM366FDXBG/FYXBG/FWXBG. The programming routine must be stored in the range from 0x2000_0800 to the end address of RAM. (Host) New application program code (a) Programming routine TMPM366FDXBG/FYXBG/FWXBG Boot ROM (I/O) SIO0 Flash memory Old application Program code (or erased state) (a) Programming routine RAM Page 637 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG (4) Step-4 The CPU jumps to the programming routine (a) in the on-chip RAM to erase the flash block containing the old application program code. The Block Erase or Chip Erase command may be used. (Host) New application Program code (a) Programming routine TMPM366FDXBG/FYXBG/FWXBG Boot ROM (I/O) SIO0 Flash memory (a) Programming routine Erased RAM (5) Step-5 Next, the programming routine (a) downloads new application program code from the host controller and programs it into the erased flash block. When the programming is completed, the writing or erase protection of that flash block in the user’s program area must be set. In the example below, new program code comes from the same host controller via the same SIO0 channel as for the programming routine. However, once the programming routine has begun to execute, it is free to change the transfer path and the source of the transfer. Create board hardware and a programming routine to suit your particular needs. (Host) New application Program code (a) Programming routine TMPM366FDXBG/FYXBG/FWXBG Boot ROM (I/O) SIO0 Flash memory New application program code (a) Programming routine RAM 2013/6/11 Page 638 TMPM366FDXBG/FYXBG/FWXBG (6) Step-6 When programming of the flash memory is complete, power off the board and disconnect the cable leading from the host to the target board. Turn on the power again so that the TMPM366FDXBG/ FYXBG/FWXBG re-boots in Single-Chip (Normal) mode to execute the new program. (Host) TMPM366FDXBG/FYXBG/FWXBG (I/O) Boot ROM 0 → 1 RESET SIO0 Flash memory Set to Single-Chip Normal) mode (BOOT=1) New application program code RAM 20.2.4 Configuration for Single Boot Mode To execute the on-board programming, boot the TMPM366FDXBG/FYXBG/FWXBG with Single Boot mode following the configuration shown below. BOOT(PF0) = 0 RESET = 0 → 1 Set the RESET input to "0", and set the each BOOT (PF0) pins to values shown above, and then release RESET (high). Page 639 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode 20.2.5 TMPM366FDXBG/FYXBG/FWXBG Memory Map Figure 20-3 shows a comparison of the memory maps in Normal and Single Boot modes. In Single Boot mode, the internal flash memory is mapped to 0x3F80_0000 and later addresses, and the Internal boot ROM (Mask ROM) is mapped to 0x0000_0000 through 0x0000_0FFF. The internal flash memory and RAM addresses of each device are shown below. Product Name Flash Size RAM Size TMPM366FDXBG/ FYXBG/FWXBG 512 KB 32 KB Flash Address RAM Address (Single Chip/ Single Boot Mode) 0x0000_0000 to 0x0007_FFFF 0x2000_0000 to 0x2000_7FFF 0x3F80_0000 to 0x3F87_FFFF Single Boot Mode Single Chip Mode 0xFFFF_FFFF 0xFFFF_FFFF Internal I/O 0x41FF_FFFF Internal I/O 0x4000_0000 0x4000_0000 Internal Flash ROM Internal RAM (64KB) 0x2000_FFFF Internal Flash ROM 0x0007_FFFF (512 KB) 0x41FF_FFFF 0x2000_0000 0x3F87_FFFF (512 KB) 0x3F80_0000 Internal RAM (64 KB) 0x2000_FFFF 0x2000_0000 Internal BOOT ROM 0x0000_2FFF (12KB) 0x0000_0000 0x0000_0000 Figure 20-3 Memory Maps for TMPM366FDXBG/FYXBG/FWXBG 2013/6/11 Page 640 TMPM366FDXBG/FYXBG/FWXBG 20.2.6 Interface specification In Single Boot mode, an SIO channel is used for communications with a programming controller. The same configuration is applied to a communication format on a programming controller to execute the onboard programming. Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. In USB Boot mode, a USB port is used for communication with a programing controll .The same configuration is applied to a communication format on a programming controller to execute the on-board programming. The communication formats are shown below. ・ UART communication Communication channel : SIO channel 0 Serial transfer mode : UART (asynchronous), half -duplex, LSB first Data length : 8 bit Parity bits : None STOP bits : 1 bit Baud rate : Arbitrary baud rate ・ I/O interface mode Communication channel : SIO channel 0 Serial transfer mode : I/O interface mode, full -duplex, LSB first Synchronization clock (SCLK0) : Input mode Handshaking signal : PE4 configured as an output mode Baud rate : Arbitrary baud rate USB Boot mode ・ Communication port : D+/DFull-Speed communication only Transfer mode : Control /Bulk USB clock : 48MHz( 12/16MHz Crystal with PLL / External Input) Page 641 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG Table 20-3 Required Pin Connections Interface Pins UART I/O Interface Mode MODE Connect with Pull-down resistance FTEST3 fixed to open USB ο PE3 × × Mode-setting pin Reset pin Communication pins ο : used 2013/6/11 (="L":Internal clock ,="H":External Clock) PE5 ο (="L" input) ο (="L" input) ο (="H" input) PG5 × × ο (for Vbus detection) BOOT (PF0) ο ο ο X1 - - ο(12/16/48MHz) RESET ο ο ο TXD0 (PE0) ο ο × RXD0 (PE1) ο ο × SCLK0 (PE2) × ο (Input mode) × PE4 × ο (Output mode) ο (Output mode) D+ × × ο D- × × ο ×: unused Page 642 TMPM366FDXBG/FYXBG/FWXBG 20.2.7 Data Transfer Format Table 20-4 and Table 20-6 to Table 20-7 illustrate the operation commands and data transfer formats at each operation mode. In conjunction with this section, refer to "20.2.10 Operation of Boot Program". Table 20-4 Single Boot Mode Commands 20.2.8 Code Command 0x10 RAM transfer 0x40 Chip and protection bit erase Restrictions on internal memories Single Boot Mode places restrictions on the internal RAM and ROM as shown in Table 20-5. Table 20-5 Restrictions in Single Boot Mode Memory Internal RAM Details A program contained in the BOOT ROM uses the area, through 0x2000_0000 to 0x2000_07FF as a work area. Store the RAM transfer program from 0x2000_0800 through the end address of RAM. Internal ROM The following addresses are assigned for storing software ID information and passwords. Storing program in these addresses is not recommendable. TMPM366FDXBG/FYXBG/FWXBG: 0x3F87_FFF0 to 0x3F87_FFFF 20.2.9 Transfer Format for Single Boot Mode commands The following tables shows the transfer format for each Single Boot Mode command. Use this section in conjunction with Chapter "20.2.10 Operation of Boot Program". Page 643 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG 20.2.9.1 RAM Transfer Table 20-6 Transfer Format for the RAM Transfer Command Data Transferred from the Controller Byte Boot ROM 1 byte to the TMPM366FDXBG/FYXBG/FWXBG Serial operation mode and baud rate For UART mode : 0x86 Baud rate Desired baud rate (Note 1) Data Transferred from the TMPM366FDXBG/ FYXBG/FWXBG to the Controller − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode -Normal acknowledge : 0x86 (The boot program aborts if the baud rate can not be set correctly.) ・For I/O Interface mode -Normal acknowledge :0x30 3 byte Command code (0x10) − 4 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 5 byte to 16 byte Password sequence (12 bytes) − 0x3F87_FFF4 to 0x3F87_FFFF 17 byte Check SUM value for bytes 5 - 16 − 18 byte − ACK for the checksum byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 19 byte RAM storage start address 31 to 24 − 20 byte RAM storage start address 23 to 16 − 21 byte RAM storage start address 15 to 8 − 22 byte RAM storage start address 7 to 0 − 23 byte RAM storage byte count 15 to 8 − 24 byte RAM storage byte count 7 to 0 − 25 byte Check SUM value for bytes 19 to 24 − 26 byte − ACK for the checksum byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 27 byte to m byte RAM storage data − m + 1 byte Checksum value for bytes 27 to m − m + 2 byte − ACK for the checksum byte (Note 2) -Normal acknowledge : 0x10 -Negative acknowledge : 0xX1 -Communication error : 0xX8 RAM m + 3 byte − Jump to RAM storage start address Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Note 3: The 19th to 25th bytes must be within the RAM address range from 0x2000_0800 through the end address of RAM. 2013/6/11 Page 644 TMPM366FDXBG/FYXBG/FWXBG 20.2.9.2 Chip Erase and Protect Bit Erase Table 20-7 Transfer Format for the Chip and Protection Bit Erase Command Data Transferred from the Controller Byte Boot ROM 1 byte to the TMPM366FDXBG/FYXBG/FWXBG Baud rate Serial operation mode and baud rate Desired baud For UART mode : 0x86 rate (Note 1) Data Transferred from the TMPM366FDXBG/ FYXBG/FWXBG to the Controller − For I/O Interface mode : 0x30 2 byte − ACK for the serial operation mode byte ・For UART mode -Normal acknowledge : 0x86 ・For I/O Interface mode -Normal acknowledge : 0x30 (The boot program aborts if the baud rate can not be set correctly.) 3 byte Command code (0x40) − 4 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x40 -Negative acknowledge : 0xX1 -Communication error : 0xX8 5 byte to 16 byte Password sequence (12 bytes) − 0x3F87_FFF4 to 0x3F87_FFFF 17 byte Check SUM value for bytes 5 - 16 − 18 byte − ACK for the checksum byte (Note 2) -Normal acknowledge : 0x40 -Negative acknowledge : 0xX1 -Communication error : 0xX8 19 byte Erase command code (0x54) − 20 byte − ACK for the command code byte (Note 2) -Normal acknowledge : 0x54 -Negative acknowledge : 0xX1 -Communication error : 0xX8 21 byte − ACK for the chip erase command code byte -Normal acknowledge : 0x4F -Negative acknowledge : 0x4C 22 byte (Wait for the next command code.) − Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second bytes must be 1/16 of the desired baud rate. Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowledge does not occur. Page 645 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG 20.2.10 Operation of Boot Program When Single Boot mode is selected, the boot program is automatically executed on startup. The boot program offers these four commands, of which the details are provided on the following subsections. 1. RAM Transfer command The RAM Transfer command stores program code transferred from a host controller to the onchip RAM and executes the program once the transfer is successfully completed. The user program RAM space can be assigned to the range from 0x2000_0800 to the end address of RAM, whereas the boot program area (0x2000_0000 ~ 0x2000_07FF) is unavailable. The user program starts at the assigned RAM address. The RAM Transfer command can be used to download a flash programming routine of your own; this provides the ability to control on-board programming of the flash memory in a unique manner. The programming routine must utilize the flash memory command sequences described in Section 20.3. Before initiating a transfer, the RAM Transfer command verifies a password sequence coming from the controller against that stored in the flash memory. Note: If a password is set to 0xFF (erased data), it is difficult to protect data securely due to an easy-toguess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. 2. Chip and Protection Bit Erase command This command erases the entire area of the flash memory automatically without verifying a password. All the blocks in the memory cell and their protection conditions are erased even when any of the blocks are prohibited from writing and erasing. When the command is completed, the FCSECBIT bit is set to "1". This command serves to recover boot programming operation when a user forgets the password. Therefore password verification is not executed. 2013/6/11 Page 646 TMPM366FDXBG/FYXBG/FWXBG 20.2.10.1 RAM Transfer Command See Table 20-6 for the transfer format of this command. 1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed description of how the serial operation mode is determined, see "20.2.10.4 Determination of a Serial Operation Mode" described later. If it is determined as UART mode, the boot program then checks if the SIO0 is programmable to the baud rate at which the 1st byte was transferred. During the first-byte interval, the RXE bit in the SC0MOD register is cleared. ・ To communicate in UART mode Send, from the controller to the target board, 0x86 in UART data format at the desired baud rate. If the serial operation mode is determined as UART, then the boot program checks if the SIO0 can be programmed to the baud rate at which the first byte was transferred. If that baud rate is not possible, the boot program aborts, disabling any subsequent communications. ・ To communicate in I/O Interface mode Send, from the controller to the target board, 0x30 in I/O Interface data format at 1/16 of the desired baud rate. Also send the 2nd byte at the same baud rate. Then send all subsequent bytes at a rate equal to the desired baud rate. In I/O Interface mode, the CPU sees the serial receive pin as if it were a general input port in monitoring its logic transitions. If the baud rate of the incoming data is high or the chip’s operating frequency is high, the CPU may not be able to keep up with the speed of logic transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. When the serial operation mode is determined as I/O Interface mode, the SIO0 is configured for SCLK Input mode. Beginning with the third byte, the controller must ensure that its AC timing restrictions are satisfied at the selected baud rate. In the case of I/O Interface mode, the boot program does not check the receive error flag; thus there is no such thing as error acknowledge (bit 3, 0xX8). 2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. The boot program echoes back the first byte: 0x86 for UART mode and 0x30 for I/O Interface mode. ・ UART mode If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the boot program programs the SC0BRCR and sends back 0x86 to the controller as an acknowledge. If the SIO0 is not programmable at that baud rate, the boot program simply aborts with no error indication. Following the 1st byte, the controller should allow for a time-out period of five seconds. If it does not receive 0x86 within the allowed time-out period, the controller should give up the communication. The boot program sets the RXE bit in the SC0MOD0 register to enable reception ("1") before loading the SIO transmit buffer with 0x86. ・ I/O Interface mode The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O Interface mode (clocked by the rising edge of SCLK0), writes 0x30 to the SC0BUF. Then, the SIO0 waits for the SCLK0 signal to come from the controller. Following the transmission of the 1st byte, the controller should send the SCLK clock to the target board after a certain idle time (several microseconds). This must be done at 1/16 the desire baud rate. If the 2nd byte, which is from the target board to the controller, is 0x30, then the controller should take it as a go-ahead. The controller must then deliver the 3rd byte to the target board at a rate equal to the desired baud rate. The boot program sets the RXE bit in the SC0MOD register to enable reception before loading the SIO transmit buffer with 0x30. Page 647 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG 3. The 3rd byte transmitted from the controller to the target board is a command. The code for the RAM Transfer command is 0x10. 4. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. When the SIO0 is configured for I/O Interface mode, the boot program does not check for a receive error. If the 3rd byte is equal to any of the command codes listed in Table 20-4, the boot program echoes it back to the controller. When the RAM Transfer command was received, the boot program echoes back a value of 0x10 and then branches to the RAM Transfer routine. Once this branch is taken, password verification is done. Password verification is detailed in a later section "Password". If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 5. The 5th to 16th bytes transmitted from the controller to the target board, are a 12-byte password. Each byte is compared to the contents of following addresses in the flash memory. The verification is started with the 5th byte and the smallest address in the designated area. If the password verification fails, the RAM Transfer routine sets the password error flag. Product name Area TMPM366FDXBG/ FYXBG/FWXBG 0x3F87_FFF4 to 0x3F87_FFFF 6. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in a later section "Checksum Calculation". 7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th bytes. If there was a receive error, the boot program sends back 0x18 (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 5th to 16th bytes must result in 0x00 (with the carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. Finally, the RAM Transfer routine examines the result of the password verification. The following two cases are treated as a password error. In these cases, the RAM Transfer routine sends back 0x11 (bit 0) to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ・ Irrespective of the result of the password comparison, all the 12 bytes of a password in the flash memory are the same value other than 0xFF. ・ Not the entire password bytes transmitted from the controller matched those contained in the flash memory. 2013/6/11 Page 648 TMPM366FDXBG/FYXBG/FWXBG When all the above verification has been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 8. The 19th to 22nd bytes, transmitted from the controller the target board, indicate the start address of the RAM region where subsequent data (e.g., a flash programming routine) should be stored. The 19th byte corresponds to bits 31.24 of the address and the 22nd byte corresponds to bits 7.0 of the address. The start address of the stored RAM must be even address. 9. The 23rd and 24th bytes, transmitted from the controller to the target board, indicate the number of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte corresponds to bits 15.8 of the number of bytes to be transferred, and the 24th byte corresponds to bits 7.0 of the number of bytes. 10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add all these bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in a later section "Checksum Calculation". 11. The 26th byte, transmitted from the target board to the controller, is an acknowledge response to the 19th to 25th bytes of data. First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer routine sends back 0x18 and returns to the command wait state (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 19th to 25th bytes must result in 0x00 (with the carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer routine sends back 0x11 to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. ・ The RAM storage start address must be within the range of 0x2000_0800 to the end address of RAM. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 12. The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMPM366FDXBG/FYXBG/FWXBG. Storage begins at the address specified by the 19th. 22nd bytes and continues for the number of bytes specified by the 23rd.24th bytes. 13. The (m+1) th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes together, drop the carries and take the two’s complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in details in a later section "Checksum Calculation". 14. The (m+2) th byte is a acknowledge response to the 27th to (m+1) th bytes. First, the RAM Transfer routine checks for a receive error in the 27th to (m+1) th bytes. If there was a receive error, the RAM Transfer routine sends back 0x18 (bit 3) and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the previously issued command (i.e., 1). When the SIO0 is configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error. Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the series of the 27th to (m+1) th bytes must result in 0x00 (with the carry dropped). If it is not 0x00, one or more bytes of data has been corrupted. In case of a checksum error, Page 649 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG the RAM Transfer routine sends back 0x11 (bit 0) to the controller and returns to the command wait state (i.e., the 3rd byte) again. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (0x10) to the controller. 15. If the (m+2) th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes after a normal acknowledge response (0x10) is transfered. 20.2.10.2 Chip and Protection Bit Erase Command See Table 20-7 for the transfer format of this command. 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. 2. From the Controller to the TMPM366FDXBG/FYXBG/FWXBG The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 0x40. 3. From the TMPM366FDXBG/FYXBG/FWXBG to the Controller The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. If the 3rd byte is equal to any of the command codes listed in Table 20-4, the boot program echoes it back to the controller. When the Show Flash Memory Sum command was received, the boot program echoes back a value of 0x40. If the 3rd byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 4. From the Controller to the TMPM366FDXBG/FYXBG/FWXBG The 5th byte, transmitted from the target board to the controller, is the Chip Erase Enable command code (0x54). 5. From the TMPM366FDXBG/FYXBG/FWXBG to the Controller The 6th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the command wait state again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. If the 5th byte is equal to any of the command codes to enable erasing, the boot program echoes it back to the controller. When the Chip and Protection Erase command was received, the boot program echoes back a value of 0x54 and then branches to the Chip Erase routine. If the 5th byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it waits for a command (the third byte) again. In this case, the upper four bits of the acknowledge response are undefined - they hold the same values as the upper four bits of the previously issued command. 2013/6/11 Page 650 TMPM366FDXBG/FYXBG/FWXBG 6. From the TMPM366FDXBG/FYXBG/FWXBG to the Controller The 7th byte indicates whether the Chip Erase command is normally completed or not. At normal completion, completion code (0x4F) is sent. When an error was detected, error code (0x4C) is sent. 7. The 9th byte is the next command code. Page 651 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG 20.2.10.3 Acknowledge Responses The boot program represents processing states with specific codes. Table 20-8 to Table 20-11 show the values of possible acknowledge responses to the received data. The upper four bits of the acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1 and bit 2 are always "0". Receive error checking is not done in I/O Interface mode. Table 20-8 ACK Response to the Serial Operation Mode Byte Return Value Meaning 0x86 The SIO can be configured to operate in UART mode. (See Note) 0x30 The SIO can be configured to operate in I/O Interface mode. Note:If the serial operation mode is determined as UART, the boot program checks if the SIO can be programmed to the baud rate at which the operation mode byte was transferred. If that baud rate is not possible, the boot program aborts, without sending back any response. Table 20-9 ACK Response to the Command Byte Return Value 0xX8 (See Note) 0xX1 (See Note) Meaning A receive error occurred while getting a command code. An undefined command code was received. (Reception was completed normally.) 0x10 The RAM Transfer command was received. 0x40 The Chip Erase command was received. Note:The upper four bits of the ACK response are the same as those of the previous command code. Table 20-10 ACK Response to the Checksum Byte Meaning Return Value 0xX8 (See Note) 0xX1 (See Note) 0xX0 (See Note) A receive error occurred. A checksum or password error occurred. The checksum was correct. Note:The upper four bits of the ACK response are the same as those of the operation command code. It is 1 (X ; RAM transfer command data [7:4] ) when password error occurs. Table 20-11 ACK Response to Chip and Protection Bit Erase Byte Return Value 2013/6/11 Meaning 0x54 The Erase enabling command was received. 0x4F The Erase command was completed. 0x4C The Erase command was abnormally completed. Page 652 TMPM366FDXBG/FYXBG/FWXBG 20.2.10.4 Determination of a Serial Operation Mode The first byte from the controller determines the serial operation mode. To use UART mode for communications between the controller and the target board, the controller must first send a value of 0x86 at a desired baud rate to the target board. To use I/O Interface mode, the controller must send a value of 0x30 at 1/16 the desired baud rate. Figure 20-4 shows the waveforms for the first byte. Start Point A bit 0 bit 1 Point B bit 2 bit 3 Point C bit 4 bit 5 bit 6 bit 7 Point D Stop UART (0x86) tAB bit 0 Point A bit 1 tCD bit 2 bit 3 bit 4 Point B bit 5 bit 6 Point C bit 7 Point D I/O Interface (0x30) tCD tAB Figure 20-4 Serial Operation Mode Byte After RESET is released, the boot program monitors the first serial byte from the controller, with the SIO reception disabled, and calculates the intervals of tAB, tAC and tAD. Figure 20-5 shows a flowchart describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot program captures timer counts each time a logic transition occurs in the first serial byte. Consequently,the calculated tAB, tAC and tAD intervals are bound to have slight errors. If the transfer goes at a high baud rate, the CPU might not be able to keep up with the speed of logic transitions at the serial receive pin. In particular, I/O Interface mode is more prone to this problem since its baud rate is generally much higher than that for UART mode. To avoid such a situation, the controller should send the first serial byte at 1/16 the desired baud rate. The flowchart in Figure 20-5 shows how the boot program distinguishes between UART and I/O Interface modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is determined as UART mode. If the length of tAB is greater than the length of tCD, the serial operation mode is determined as I/O Interface mode. Bear in mind that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. This becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. To prevent this problem, reset UART mode within the programming routine. For example, the serial operation mode may be determined to be I/O Interface mode when the intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should allow for a time-out period within which it expects to receive an echo-back (0x86) from the target board. The controller should give up the communication if it fails to get that echo-back within the allowed time. When I/O Interface mode is utilized, once the first serial byte has been transmitted, the controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowledge response is not 0x30, the controller should give up further communications. When the intended mode is I/O interface mode, the first byte does not have to be 0x30 as long as tAB is greater than tCD as shown above. 0x91, 0xA1 or 0xB1 can be sent as the first byte code to determine the falling edges of Point A and Point C and the rising edges of Point B and Point D. If tAB is greater than tCD and SIO is selected by the resolution of the operation mode determination, the second byte code is 0x30 even though the transmitted code on the first byte is not 0x30 (The first byte code to determine I/O interface mode is described as 0x30). Page 653 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG Start Initialize TMRB0 Prescaler is on.(source clock:φT0) Point A High-to-low transition on serial receive pin? YES TMRB0 starts counting up Point B Low-to-high transition on serial receive pin? YES Software-capture and save timer value (tAB) Point C High-to-low transition on serial receive pin? YES Software-capture and save timer value (tAC) Point D Low-to-high transition on serial receive pin? YES Software-capture and save timer value (tAD) 16-bit Timer 0 stops counting YES WAC Ӎ tAD? Make backup copy of tAD value Done Stop operation (infinite loop waiting for RESET) Figure 20-5 Serial Operation Mode Byte Reception Flowchart 2013/6/11 Page 654 TMPM366FDXBG/FYXBG/FWXBG Start tCD ← tAD  tAC YES WAB > tCD? UART mode I/O interface mode Figure 20-6 Serial Operation Mode Determination Flowchart 20.2.10.5 Password The RAM Transfer command (0x10) causes the boot program to perform password verification. Following an echo-back of the command code, the boot program verifies the contents of the 12-byte password area within the flash memory. The following table shows the password area of each product. Product name Area TMPM366FDXBG/ FYXBG/FWXBG 0x3F87_FFF4 to 0x3F87_FFFF Note:If a password is set to 0xFF (erased data area), it is difficult to protect data securely due to an easy-to-guess password. Even if Single Boot mode is not used, it is recommended to set a unique value as a password. If all these address locations contain the same bytes of data other than 0xFF, a password area error occurs as shown in Figure 20-7. In this case, the boot program returns an error acknowledge (0x11) in response to the checksum byte (the 17th byte), regardless of whether the password sequence sent from the controller is all 0xFFs. The password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. All of the 12 bytes must match to pass the password verification. Otherwise, a password error occurs, which causes the boot program to reply an error acknowledge in response to the checksum byte (the 17th byte). The password verification is performed even if the security function is enabled. Start Are all bytes the same? YES Are all bytes equal to FFH? YES Password area error Password area is normal. Figure 20-7 Password Area Verification Flowchart Page 655 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG 20.2.10.6 Checksum Calculation The checksum byte for a series of bytes of data is calculated by adding the bytes together, dropping the carries, and taking the two’s complement of the total sum. The Show Flash Memory Sum command and the Show Product Information command perform the checksum calculation. The controller must perform the same checksum operation in transmitting checksum bytes. Example) Assume the Show Flash Memory Sum command provides the upper and lower bytes of the sum as 0xE5 and 0xF6. To calculate the checksum for a series of 0xE5 and 0xF6: Add the bytes together 0xE5 + 0xF6 = 0x1DB Take the two’s complement of the sum, and that is the checksum byte. 0 − 0xDB = 0x25 2013/6/11 Page 656 TMPM366FDXBG/FYXBG/FWXBG 20.2.11 General Boot Program Flowchart Figure 20-8 shows an overall flowchart of the boot program. Page 657 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG Single Boot program starts Initialize Set SIO operation mode  SIO operation mode? UART  Baud rate setting ? I/O interface Cannot be set Can be set Set I/O interface mode Set UART mode and baud rate ACK data← received data (0x30) ACK data← received data (0x86) (Send 0x30) Normal response (Send 0x86) Normal response Stop operation Prepare to get a command ACK data← ACK data & 0xF0 Receive routine Set a command  Yes Receive error ? ACK data ← ACK data 0x08 Transmission routine (Send 0xX8:receive error No normally   RAM transfer? Chip erase? YES (0x10) Command error YES (0x40) ACK data ← Received data (0x10) ACK data ← Received data (0x40) Transmission routine (Send 0x10: normal response) Transmission routine (Send 0x40: normal response) RAM transfer processing Chip erase processing ACK data ← Received data (0xX1) Transmission routine (Send 0xX1: Command error)  Processed normally? Yes normally Jump to RAM Figure 20-8 Overall Boot Program Flowchart 2013/6/11 Page 658 TMPM366FDXBG/FYXBG/FWXBG 20.2.12 USB Boot 20.2.12.1 Boot Sequence USB BOOT Sequence is shown as following table. Table 20-12 USB Boot Sequence USB BOOT Protocol TMPM366FDXBG/FYXBG/ FWXBG PC Start USB BOOT Protocol → ← Send Password → Confirm Password → ← Send Boot Information → Confirm Boot Information → ← Plane Data → Send Sum Data → Confirm Sum Data → ← Response Response Response Response Flash Erase Protocol Start Flash Erase Protocol → ← Send Password → Confirm Password → ← Run Flash Erase Response → ← Confirm Flash Erase Response Response → ← Response Page 659 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG 20.2.12.2 USB Boot Command USB Boot Command is shown as following table. Table 20-13 Boot Command List Start USB Boot Protocol Send Password Confirm Password Send Boot Information Confirm Boot Information bmRequestType 1byte Vendor Class in out in out in bRequest 1byte Command 0x18 0x20 0x28 0x30 0x38 wValue 2byte 0x0000 - - - - - wIndex 2byte Sequence ID any data Same as Start Protocol Same as Start Protocol Same as Start Protocol Same as Start Protocol wLength 2byte Data Length 1 12 1 6 1 Data Stage 0 to 64 byte 0x28:OK RAM Address 0x39:NG 0x18: OK 0x19: NG Password[0] Passwoed[1] RAM Address Password[2] RAM Address Password[3] RAM Address Password[4] Transfer Size Password[5] Transfer Size Password[6] Password[7] Password[8] Password[9] Password[10] Password[11] 2013/6/11 0x29:NG Page 660 0x38:OK TMPM366FDXBG/FYXBG/FWXBG Send Sum Data Confirm Sum Data Start Flash Erase Protocol Run Flash Erase Confirm Flash Erase bmRequestType 1byte Vendor Class out in in in in bRequest 1byte Command 0x40 0x48 0x58 0x68 0x78 wValue 2byte 0x0000 - - - - - wIndex 2byte Sequence ID Same as Start Protocol Same as Start Protocol any data Same as Start Protocol Same as Start Protocol wLength 2byte Data Length 1 1 1 1 1 Data Stage 0 - 64 byte 20.2.13 Sum Data 0x48: OK 0x58:OK 0x68: OK 0x78:OK 0x49: NG 0x59:NG 0x69: NG 0x79:NG Descriptor Descriptor in USB Boot Mode is shown as following table. Table 20-14 Device Descriptor Offset Filed value 0 bLentgth 0x12 18 bytes 1 bDescripotType 0x01 Device descriptor 0x00 USB version 2.0 2 3 bcdUSB Description 0x02 4 bDeviceClass 0x00 Device class (Not used) 5 bDeviceSubClass 0x00 Sub command (Not used) 6 bDeviceProtocol 0x00 Protocol (Not used) 7 bMaxPacketSize0 0x40 EP0 Maximum packet size 64 bytes 0x30 Vender ID 8 9 10 11 12 13 idVendor idProduct bcdDevice 0x09 0x69 Product ID 0x65 0x00 Device version 0x01 14 iManufacture 0x00 String descriptor index shown as manufacturer 15 iProduct 0x00 String descriptor index shown as manufacturer 16 iSerialNumber 0x00 String descriptor index shown as manufacturer 17 bNumConfigurations 0x01 The number of configuration 1 Page 661 2013/6/11 20. 20.2 Flash Memory Operation Operation Mode TMPM366FDXBG/FYXBG/FWXBG Table 20-15 Configuration Descriptor Offset Filed value 0 bLentgth 0x09 9 bytes 1 bDescripotType 0x02 Configuration descripor 0x20 The length which is added with configuration and end point (32 bytes) 2 bTotal Lenght 3 Description 0x00 4 bNumInterfaces 0x01 The number of interface 1 5 bConfigurationValue 0x01 The number of configuration 1 6 iConfiguration 0x00 7 bmAttributes 0x80 Bus power 8 MaxPower 0x31 Maximum power consumption (49mA) String descriptor index shown this configuration name (Not used) Table 20-16 Interface Descriptor Offset Filed value Description 0 bLentgth 0x09 9 bytes 1 bDescripotType 0x04 Interface descriptor 2 bInterdfaceNumber 0x00 The number of interface 1 3 bAlternateSetting 0x00 The number of alternate setting 0 4 bNumEndpoints 0x02 Two end point 5 bInterfaceClass 0xFF 6 bInterfaceSubClass 0x00 7 bInterfaceProtocol 0x50 8 iInterface 0x00 Bulk only protocol String descriptor index shown this interface name (Not used) Table 20-17 Bulk-In Endpoint Descriptor Offset Filed value 0 bLentgth 0x07 7 bytes 1 bDescripotType 0x05 End point descriptor 2 bEndpointAddress 0x81 End point 1 is used as input 3 bmAttributes 0x02 Bulk transfer 4 5 6 2013/6/11 wMaxPacketSize bInterval Description 0x40 0x00 0x00 (Ignore because of bulk transfer) Page 662 TMPM366FDXBG/FYXBG/FWXBG Table 20-18 Bulk-Out Endpoint Descriptor Offset Filed value 0 bLentgth 0x07 7 bytes 1 bDescripotType 0x05 End point descriptor 2 bEndpointAddress 0x02 End point 2 is used as output 3 bmAttributes 0x02 Bulk transfer 0x40 Payload 64 bytes 4 5 6 wMaxPacketSize bInterval Description 0x00 0x00 (Ignore because of bulk transfer) Page 663 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) 20.3 TMPM366FDXBG/FYXBG/FWXBG On-board Programming of Flash Memory (Rewrite/Erase) In on-board programming, the CPU is to execute software commands for rewriting or erasing the flash memory. The rewrite/erase control program should be prepared by the user beforehand. Because the flash memory content cannot be read while it is being written or erased, it is necessary to run the rewrite/erase program from the internal RAM after shifting to the user boot mode. 20.3.1 Flash Memory Except for some functions, writing and erasing flash memory data are in accordance with the standard JEDEC commands. In writing or erasing, use 32-bit data transfer command of the CPU to enter commands to the flash memory. Once the command is entered, the actual write or erase operation is automatically performed internally. Table 20-19 Flash Memory Functions Major functions 20.3.1.1 Description Automatic page program Writes data automatically per page. Automatic chip erase Erases the entire area of the flash memory automatically. Automatic block erase Erases a selected block automatically. Protect function The write or erase operation can be individually inhibited for each block. Block Configuration User Boot Mode 0x0007_FFFF 0x0006_0000 0x0004_0000 0x0002_0000 Single Boot Mode Page Configuration 0x3F87_FFFF 128K bytes (BLOCK0) 128 ZRUGV™256 128K bytes (BLOCK1) 128 ZRUGV™256 128K bytes (BLOCK2) 128 ZRUGV™256 64K bytes (BLOCK3) 128 ZRUGV™128 32K bytes (BLOCK5) 128 ZRUGV™64 32K bytes (BLOCK4) 128 ZRUGV™64 0x3F86_0000 0x3F84_0000 0x3F82_0000 0x0001_0000 0x3F81_0000 0x0000_8000 0x3F80_8000 0x0000_0000 0x3F80_0000 Figure 20-9 Block Configuration of Flash Memory 2013/6/11 Page 664 TMPM366FDXBG/FYXBG/FWXBG 20.3.1.2 Basic operation This flash memory device has the following two operation modes: ・ The mode to read memory data (Read mode) ・ The mode to automatically erase or rewrite memory data (Automatic operation) Transition to the automatic mode is made by executing a command sequence while it is in the memory read mode. In the automatic operation mode, flash memory data cannot be read and any commands stored in the flash memory cannot be executed. In the automatic operation mode, any interrupt or exception generation cannot set the device to the read mode except when a hardware reset is generated. During automatic operation, be sure not to cause any exceptions other than reset and debug exceptions while a debug port is connected. Any exception generation cannot set the device to the read mode except when a hardware reset is generated. (1) Read When data is to be read, the flash memory must be set to the read mode. The flash memory will be set to the read mode immediately after power is applied, when CPU reset is removed, or when an automatic operation is normally terminated. In order to return to the read mode from other modes or after an automatic operation has been abnormally terminated, either the Read/reset command (a software command to be described later) or a hardware reset is used. The device must also be in the read mode when any command written on the flash memory is to be executed. ・ Read/reset command and Read command (software reset) When a command that has not been completely written has to be canceled, the Read/reset command must be used. The Read command is used to return to the read mode after executing 32-bit data transfer command to write the data "0x0000_00F0" to an arbitrary address of the flash memory. ・ With the Read/reset command, the device is returned to the read mode after completing the third bus write cycle. (2) Command write This flash memory uses the command control method. Commands are executed by executing a command sequence to the flash memory. The flash memory executes automatic operation commands according to the address and data combinations applied (refer to Command Sequence). If it is desired to cancel a command write operation already in progress or when any incorrect command sequence has been entered, the Read/reset command is to be executed. Then, the flash memory will terminate the command execution and return to the read. While commands are generally comprised of several bus cycles, the operation to apply 32-bit data transmit command to the flash memory is called "bus write cycle." The bus write cycles are to be in a specific sequential order and the flash memory will perform an automatic operation when the sequence of the bus write cycle data and address of a command write operation is in accordance with a predefined specific sequence. If any bus write cycle does not follow a predefined command write sequence, the flash memory will terminate the command execution and return to the read mode. Note 1: Command sequences are executed from outside the flash memory area. Note 2: Each bus write cycle must be sequentially executed by 32-bit data transmit command. While a command sequence is being executed, access to the flash memory is prohibited. Also, don't generate any interrupt (except debug exceptions when a debug port is connected).If such an operation is made, it can result in an unexpected read access to the flash memory and the command sequencer may not be able to correctly recognize the command. While it could cause an abnormal termination of the command sequence, it is also possible that the written command is incorrectly recognized. Note 3: For the command sequencer to recognize a command, the device must be in the read mode prior to executing the command. Be sure to check before the first bus write cycle Page 665 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM366FDXBG/FYXBG/FWXBG that FCFLCS is set to "1." It is recommended to subsequently execute a Read command. Note 4: Upon issuing a command, if any address or data is incorrectly written, be sure to perform a software reset to return to the read mode again. 20.3.1.3 Reset (Hardware reset) A hardware reset is used to cancel the operational mode set by the command write operation when forcibly termination during automatic programming/ erasing or abnormal termination during automatic operation. The flash memory has a reset input as the memory block and it is connected to the CPU reset signal. Therefore, when the RESET input pin of this device is set to VIL or when the CPU is reset due to any overflow of the watch dog timer, the flash memory will return to the read mode terminating any automatic operation that may be in progress. It should also be noted that applying a hardware reset during an automatic operation can result in incorrect rewriting of data. In such a case, be sure to perform the rewriting again. Refer to Section "20.2.1 Reset Operation" for CPU reset operations. After a given reset input, the CPU will read the reset vector data from the flash memory and starts operation after the reset is removed. 20.3.1.4 Commands (1) Automatic Page Programming Writing to a flash memory device is to make "1" data cells to "0" data cells. Any "0" data cell cannot be changed to a "1" data cell. For making "0" data cells to "1" data cells, it is necessary to perform an erase operation. The automatic page programming function of this device writes data of each page. The TMPM366FDXBG/FYXBG/FWXBG contain 128 words in a page. A 128 word block is defined by a same [31:9] address and it starts from the address [8:0] = 0x00 and ends at the address [8:0] = 0x1FF. This programming unit is hereafter referred to as a "page". Writing to data cells is automatically performed by an internal sequencer and no external control by the CPU is required. The state of automatic page programming (whether it is in writing operation or not) can be checked by FCFLCS [0] . Also, any new command sequence is not accepted while it is in the automatic page programming mode. If it is desired to interrupt the automatic page programming, use the hardware reset function. If the operation is stopped by a hardware reset operation, it is necessary to once erase the page and then perform the automatic page programming again because writing to the page has not been normally terminated. The automatic page programming operation is allowed only once for a page already erased. No programming can be performed twice or more times irrespective of the data cell value whether it is "1" or "0." Note that rewriting to a page that has been once written requires execution of the automatic block erase or automatic chip erase command before executing the automatic page programming command again. Note that an attempt to rewrite a page two or more times without erasing the content can cause damages to the device. No automatic verify operation is performed internally to the device. So, be sure to read the data programmed to confirm that it has been correctly written. The automatic page programming operation starts when the third bus write cycle of the command cycle is completed. On and after the fifth bus write cycle, data will be written sequentially starting from the next address of the address specified in the fourth bus write cycle (in the fourth bus write cycle, the page top address will be command written) (32 bits of data is input at a time). Be sure to use the 32-bit data transfer command in writing commands on and after the fourth bus cycle. In this, any 32-bit data transfer commands shall not be placed across word boundary. On and after the 2013/6/11 Page 666 TMPM366FDXBG/FYXBG/FWXBG fifth bus write cycle, data is command written to the same page area. Even if it is desired to write the page only partially, it is required to perform the automatic page programming for the entire page. In this case, the address input for the fourth bus write cycle shall be set to the top address of the page. Be sure to perform command write operation with the input data set to "1" for the data cells not to be set to "0." For example, if the top address of a page is not to be written, set the input data of the fourth bus write cycle to 0xFFFFFFFF to command write the data. Once the third bus cycle is executed, the automatic page programming is in operation. This condition can be checked by monitoring FCFLCS. Any new command sequence is not accepted while it is in automatic page programming mode. If it is desired to stop operation, use the hardware reset function. Be careful in doing so because data cannot be written normally if the operation is interrupted. When a single page has been command written normally terminating the automatic page writing process, FCFLCS is set to "1" and it returns to the read mode. When multiple pages are to be written, it is necessary to execute the page programming command for each page because the number of pages to be written by a single execution of the automatic page program command is limited to only one page. It is not allowed for automatic page programming to process input data across pages. Data cannot be written to a protected block. When automatic programming is finished, it automatically returns to the read mode. This condition can be checked by monitoring FCFLCS . If automatic programming has failed, the flash memory is locked in the mode and will not return to the read mode. For returning to the read mode, it is necessary to execute hardware reset to reset the flash memory or the device. In this case, while writing to the address has failed, it is recommended not to use the device or not to use the block that includes the failed address. Note:Software reset becomes ineffective in bus write cycles on and after the fourth bus write cycle of the automatic page programming command. (2) Automatic chip erase The automatic chip erase operation starts when the sixth bus write cycle of the command cycle is completed. This condition can be checked by monitoring FCFLCS . While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. Any new command sequence is not accepted while it is in an automatic chip erase operation. If it is desired to stop operation, use the hardware reset function. If the operation is forced to stop, it is necessary to perform the automatic chip erase operation again because the data erasing operation has not been normally terminated. Also, any protected blocks cannot be erased. If all the blocks are protected, the automatic chip erase operation will not be performed and it returns to the read mode after completing the sixth bus read cycle of the command sequence. When an automatic chip erase operation is normally terminated, it automatically returns to the read mode. If an automatic chip erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. For returning to the read mode, it is necessary to execute hardware reset to reset the device. In this case, the failed block cannot be detected. It is recommended not to use the device anymore or to identify the failed block by using the block erase function for not to use the identified block anymore. Page 667 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) (3) TMPM366FDXBG/FYXBG/FWXBG Automatic block erase (for each block) The automatic block erase operation starts when the sixth bus write cycle of the command cycle is completed. This status of the automatic block erase operation can be checked by monitoring FCFLCS . While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that data has been correctly erased. Any new command sequence is not accepted while it is in an automatic block erase operation. If it is desired to stop operation, use the hardware reset function. In this case, it is necessary to perform the automatic block erase operation again because the data erasing operation has not been normally terminated. Also, any protected blocks cannot be erased. If an automatic block erase operation has failed, the flash memory is locked in the mode and will not return to the read mode. In this case, execute hardware reset to reset the device. (4) Automatic programming of protection bits (for each block) This device is implemented with protection bits. This protection can be set for each block. See Table 20-24 for table of protection bit addresses. This device assigns 1 bit to 1 block as a protection bit. The applicable protection bit is specified by PBA in the seventh bus write cycle. By automatically programming the protection bits, write and/or erase functions can be inhibited (for protection) individually for each block. The protection status of each block can be checked by FCFLCS to be described later. This status of the automatic programming operation to set protection bits can be checked by monitoring FCFLCS . Any new command sequence is not accepted while automatic programming is in progress to program the protection bits. If it is desired to stop the programming operation, use the hardware reset function. In this case, it is necessary to perform the programming operation again because the protection bits may not have been correctly programmed. If all the protection bits have been programmed, all FCFLCS are set to "1" indicating that it is in the protected state. This disables subsequent writing and erasing of all blocks. Note:Software reset is ineffective in the seventh bus write cycle of the automatic protection bit programming command. FCFLCS turns to "0" after entering the seventh bus write cycle. (5) Automatic erasing of protection bits Different results will be obtained when the automatic protection bit erase command is executed depending on the status of the protection bits and the security bits. It depends on the status of FCFLCS whether all are set to "1" or not if FCSECBIT is 0x1. Be sure to check the value of FCFLCS before executing the automatic protection bit erase command. See the chapter "ROM protection" for details. ・ When all the FCFLCS are set to "1" (all the protection bits are programmed): When the automatic protection bit erase command is command written, the flash memory is automatically initialized within the device. When the seventh bus write cycle is completed,the entire area of the flash memory data cells is erased and then the protection bits are erased. This operation can be checked by monitoring FCFLCS . If the automatic operation to erase protection bits is normally terminated, FCFLCS will be set to "0x00000001".While no automatic verify operation is performed internally to the device, be sure to read the data to confirm that it has been correctly erased. For returning to the read mode while the automatic operation after the seventh bus cycle is in progress, it is necessary to use the hardware reset to reset the device. If this is done, it is necessary to check the status of protection bits by FCFLCS after retuning to the read mode and perform either the automatic protection bit erase, automatic chip erase, or automatic block erase operation, as appropriate. ・ When FCFLCS include "0" (not all the protection bits are programmed): 2013/6/11 Page 668 TMPM366FDXBG/FYXBG/FWXBG If the automatic protection bit is cleared to "0", the protection condition is canceled. With this device, protection bits can be programmed to an individual block and performed bit-erase operation in the four bits unit as shown in Table 20-25. The target bits are specified in the seventh bus write cycle.The protection status of each block can be checked by FCFLCS to be described later. This status of the programming operation for automatic protection bits can be checked by monitoring FCFLCS . When the automatic operation to erase protection bits is normally terminated, the protection bits of FCFLCS selected for erasure are set to "0". In any case, any new command sequence is not accepted while it is in an automatic operation to erase protection bits. If it is desired to stop the operation, use the hardware reset function. When the automatic operation to erase protection bits is normally terminated, it returns to the read mode. Note:The FCFLCS bit is "0" while in automatic operation and it turns to "1" when the automatic operation is terminated. Page 669 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) 20.3.1.5 TMPM366FDXBG/FYXBG/FWXBG Flash control/ status register Base Address = 0x41FF_F000 Register name Address(Base+) Reserved - Security bit register Reserved Flash control register Reserved Note:Access to the "Reserved" areas is prohibited. 2013/6/11 Page 670 0x0000 to 0x000F FCSECBIT 0x0010 - 0x0014 to 0x001F FCFLCS 0x0020 - 0x0024 to 0x0FFF TMPM366FDXBG/FYXBG/FWXBG (1) bit symbol After reset FCSECBIT (Security bit register) 31 30 29 28 27 26 25 24 - - - - - - - - 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 8 15 14 13 12 11 10 9 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - SECBIT After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 SECBIT R/W Security bits 0:disabled 1:enabled Note:This register is initialized by cold reset or releasing STOP2 mode of standby mode. Page 671 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) (2) TMPM366FDXBG/FYXBG/FWXBG FCFLCS (Flash control register) 31 30 29 28 27 26 25 24 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 bit symbol - - BLPRO5 BLPRO4 BLPRO3 BLPRO2 BLPRO1 BLPRO0 After reset 0 0 (Note2) (Note2) (Note2) (Note2) (Note2) (Note2) 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RDY/BSY After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-22 − R Read as 0. 21-16 BLPRO5 to BLPRO0 R Protection for Block5 to 0 0: disabled 1: enabled Protection status bits Each of the protection bits represents the protection status of the corresponding block. When a bit is set to "1," it indicates that the block corresponding to the bit is protected. When the block is protected, data cannot be written to it. 15-1 − R Read as 0. 0 RDY/BSY R Ready/Busy (Note 1) 0: automatic operating 1:automatic operation terminated Ready/Busy flag bit The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a function bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and outputs "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0" output. By applying a hardware reset, it returns to "1." Note 1: This command must be issued in the ready state. Issuing the command in the busy state may disable both correct command transmission and further command input. To exit from the condition, execute system reset. System reset requires at least 0.5 μs regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. Note 2: The value varies depending on protection applied. 2013/6/11 Page 672 TMPM366FDXBG/FYXBG/FWXBG 20.3.1.6 List of Command Sequences Table 20-20 shows the addresses and the data of each command of flash memory. Bus cycles are "bus write cycles" except for the second bus cycle of the Read command and the fourth bus cycle of the Read/reset command. Bus write cycles are executed by 32-bit (word) data transfer commands. (In the following table, only lower 8 bits data are shown.) See Table 20-21 for the detail of the address bit configuration. Use a value of "Addr." in the Table 20-20 for the address [15:8] of the normal command in the Table 20-21. Note:Always set "0" to the address bits [1:0] in the entire bus cycle. Table 20-20 Flash Memory Access from the Internal CPU Command sequence Read Read/Reset Automatic page programming Automatic chip erase First bus cycle Second bus cycle Third bus cycle Fourth bus cycle Fifth bus cycle Sixth bus cycle Seventh bus cycle Addr. Addr. Addr. Addr. Addr. Addr. Addr. Data Data Data Data Data Data Data 0xXX − − − − − − 0xF0 − − − − − − 0x54XX 0xAAXX 0x54XX RA − − − 0xAA 0x55 0xF0 RD − − − 0x54XX 0xAAXX 0x54XX PA PA PA PA 0xAA 0x55 0xA0 PD0 PD1 PD2 PD3 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX − 0xAA 0x55 0x80 0xAA 0x55 0x10 − 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX BA − 0xAA 0x55 0x80 0xAA 0x55 0x30 − Automatic protection bit programming 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA 0xAA 0x55 0x9A 0xAA 0x55 0x9A 0x9A Automatic protection bit erase 0x54XX 0xAAXX 0x54XX 0x54XX 0xAAXX 0x54XX PBA 0xAA 0x55 0x6A 0xAA 0x55 0x6A 0x6A Automatic block erase Supplementary explanation ・ RA: Read address ・ RD: Read data ・ PA: Program page address PD: Program data (32 bit data) After the fourth bus cycle, enter data in the order of the address for a page. ・ BA: Block address ・ PBA: Protection bit address Page 673 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) 20.3.1.7 TMPM366FDXBG/FYXBG/FWXBG Address bit configuration for bus write cycles Table 20-21 is used in conjunction with Table 20-20 "Flash Memory Access from the Internal CPU." Address setting can be performed according to the normal bus write cycle address configuration from the first bus cycle. "0" is recommended" in the Table 20-21 Address Bit Configuration for Bus Write Cycles can be changed as necessary. Table 20-21 Address Bit Configuration for Bus Write Cycles Address Addr [31:19] Addr [18] Addr [17] Addr [16] Addr [15] Addr [14] Addr [13:11] Addr [10] Addr [9] Addr Addr [8] [7:0] Table 20-22 Normal bus write cycle address configuration Normal commands Addr[1:0]="0" (fixed) Flash area "0" is recommended. Others:0 Command (recommended) BA: Block address (Set the sixth bus write cycle address for block erase operation) Block erase Block selection Addr[1:0]="0" (fixed) , Others:0 (recommended) (Table 20-23) PA: Program page address (Set the fourth bus write cycle address for page programming operation) Automatic page programming Addr[1:0]="0" (fixed) Page address Others:0 (recommended) PBA: Protection bit address (Set the seventh bus write cycle address for protection bit programming Protection bit programming Flash area Protection bit selection Fixed to "0". (Table 20-24) Protection bit selection (Table 20-24) Addr[1:0]="0" (fixed) Others:0 (recommended) PBA: Protection bit address (Set the seventh bus erase cycle address for protection bit erasure) Protection bit erase Flash area Protection bit selection Fixed to "0". (Table 20-25) 2013/6/11 Protection bit selection (Table 20-25) Page 674 Addr[1:0]="0" (fixed) Others:0 (recommended) TMPM366FDXBG/FYXBG/FWXBG As block address, specify any address in the block to be erased. Table 20-23 Block Address Table Block Address (User boot mode) Address (Single boot mode) Size (Kbyte) 4 0x0000_0000 ~ 0x0000_7FFF 0x3F80_0000 ~ 0x3F80_7FFF 32 5 0x0000_8000 ~ 0x0000_FFFF 0x3F80_8000 ~ 0x3F80_FFFF 32 3 0x0001_0000 ~ 0x0001_FFFF 0x3F81_0000 ~ 0x3F81_FFFF 64 2 0x0002_0000 ~ 0x0003_FFFF 0x3F82_0000 ~ 0x3F83_FFFF 128 1 0x0004_0000 ~ 0x0005_FFFF 0x3F84_0000 ~ 0x3F85_FFFF 128 0 0x0006_0000 ~ 0x0007_FFFF 0x3F86_8000 ~ 0x3F87_FFFF 128 Note:As for the addresses from the first to the fifth bus cycles, specify the upper addresses of the blocks to be erased. Table 20-24 Protection Bit Programming Address Table The seventh bus write cycle address Block Protection bit Address [18] Address [17] Block0 0 0 0 0 Block1 0 0 0 1 Block2 0 0 1 0 Block3 0 0 1 1 Block4 0 1 0 0 Block5 0 1 0 1 Page 675 Address [16:11] Fixed to "0". Address [10] Address [9] Address [8] "0" is recommended. 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM366FDXBG/FYXBG/FWXBG Table 20-25 Protection Bit Erase Address Table Block The seventh bus write cycle address [18:17] Protection bit Address[18] Address[17] Block0 to 3 0 0 Block4 to 5 0 1 Note:The protection bit erase command cannot erase by individual block. 2013/6/11 Page 676 TMPM366FDXBG/FYXBG/FWXBG 20.3.1.8 Flowchart Start Automatic page programming command sequence (see the flowchart shown below) Address = Address + 0x200 (set by a page) NO The address of the last page? YES Automatic page programming Automatic Page Programming Command Sequence (Address/ Command) 0x54xx/0xAA 0xAAxx/0x55 0x54xx/0xA0 Programming address (page address)/ Programming data (32 bit data) Figure 20-10 Automatic Programming Note:Command sequence is executed by 0x54xx or 0x55xx. Page 677 2013/6/11 20. 20.3 Flash Memory Operation On-board Programming of Flash Memory (Rewrite/Erase) TMPM366FDXBG/FYXBG/FWXBG Start Automatic chip erase command sequence (see the flowchart shown below) Automatic chip erase completed Automatic chip erase command sequence (address/ command) Automatic block erase command sequence (address/ command) 0x54xx/0xAA 0x54xx/0xAA 0xAAxx/0x55 0xAAxx/0x55 0x54xx/0x80 0x54xx/0x80 0x54xx/0xAA 0x54xx/0xAA 0xAAxx/0x55 0xAAxx/0x55 0x54xx/0x10 Block address/0x30 Figure 20-11 Automatic Erase Note:Command sequence is executed by 0x54xx or 0x55xx. 2013/6/11 Page 678 TMPM366FDXBG/FYXBG/FWXBG 21. ROM protection 21.1 Outline The TMPM366FDXBG/FYXBG/FWXBG offers two kinds of ROM protection/ security functions. One is a write/ erase-protection function for the internal flash ROM data. The other is a security function that restricts internal flash ROM data readout and debugging. 21.2 Features 21.2.1 Write/ erase-protection function The write/ erase-protection function enables the internal flash to prohibit the writing and erasing operation for each block. To activate the function, write "1" to the corresponding bits to a block to protect. Writing "0" to the bits cancels the protection. The protection settings of the bits can be monitored by the FCFLCS bit. See the chapter "Flash" for programming details. 21.2.2 Security function The security function restricts flash ROM data readout and debugging. This function is available under the conditions shown below. 1. The FCSECBIT bit is set to"1". 2. All the protection bits (the FCFLCS bits) used for the write/erase-protection function are set to "1". Note:The FCSECBIT bit is set to "1" at a power-on reset right after power-on. Table 21-1 shows details of the restrictions by the security function. Table 21-1 Restrictions by the security function Item Details 1) ROM data readout Data can be read from CPU. 2) Debug port Communication of JTAG/SW and trace are prohibited Writing a command to the flash memory is prohibited. 3) Command for flash memory An attempt to erase the contents in the bits used for the write/ erase-protection erases all the protection bits. Page 679 2013/6/11 21. 21.3 ROM protection Register 21.3 TMPM366FDXBG/FYXBG/FWXBG Register Base Address = 0x41FF_F000 Register name Address(Base+) Reserved Security bit register Flash control register Reserved Note:Access to the "Reserved" area is prohibited. 2013/6/11 Page 680 - 0x0000,0x0004 FCSECBIT 0x0010 FCFLCS 0x0020 - 0x0024,0x0028 TMPM366FDXBG/FYXBG/FWXBG 21.3.1 FCFLCS (Flash control register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - BLPRO5 BLPRO4 BLPRO3 BLPRO2 BLPRO1 BLPRO0 0 0 (Note2) (Note2) (Note2) (Note2) (Note2) (Note2) 15 14 13 12 11 10 9 8 bit symbol After reset bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - RDY/BSY After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-22 − R Read as 0. 21-16 BLPRO5 to BLPRO0 R Protection for Block5 to 0 0: disabled 1: enabled Protection status bits Each of the protection bits represents the protection status of the corresponding block. When a bit is set to "1," it indicates that the block corresponding to the bit is protected. When the block is protected, data cannot be written to it. 15-1 − R Read as 0. 0 RDY/BSY R Ready/Busy (Note 1) 0: Auto operating 1:Auto operation terminated Ready/Busy flag bit The RDY/BSY output is provided as a means to monitor the status of automatic operation. This bit is a function bit for the CPU to monitor the function. When the flash memory is in automatic operation, it outputs "0" to indicate that it is busy. When the automatic operation is terminated, it returns to the ready state and outputs "1" to accept the next command. If the automatic operation has failed, this bit maintains the "0" output. By applying a hardware reset, it returns to "1." Note 1: This command must be issued in the ready state. Issuing the command in the busy state may disable both correct command transmission and further command input. To exit from the condition, execute system reset. System reset requires at least 0.5 ms regardless of the system clock frequency. In this condition, it takes approx. 2 ms to enable reading after reset. Note 2: The value varies depending on protection applied. Page 681 2013/6/11 21. 21.3 ROM protection Register TMPM366FDXBG/FYXBG/FWXBG 21.3.2 FCSECBIT(Security bit register) 31 30 29 28 27 26 25 24 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 - - - - - - - - bit symbol After reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 bit symbol - - - - - - - - After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit symbol - - - - - - - SECBIT After reset 0 0 0 0 0 0 0 1 Bit Bit Symbol Type Function 31-1 − R Read as 0. 0 SECBIT R/W Security bit 0: Disabled 1: Enabled Note:This register is initialized by cold reset and releasing STOP2 mode of the standby mode. 2013/6/11 Page 682 TMPM366FDXBG/FYXBG/FWXBG 21.4 Writing and erasing Writing and erasing protection bits are available with a single chip mode, single boot mode and writer mode. 21.4.1 Protection bits Writing to the protection bits is done on block-by-block basis. When the settings for all the blocks are "1", erasing must be done after setting the FCSECBIT bit to "0". Setting "1" at that situation erases all the protection bits. To write and erase the protection bits, command sequence is used. See the capter "Flash" for details 21.4.2 Security bit The FCSECBIT bit that activates security function is set to "1" at a power-on reset right after power-on. The bit is rewritten by the following procedure. 1. Write the code 0xa74a9d23 to FCSECBIT register. 2. Write data within 16 clocks from the above.1. Note:The above procedure is enabled only when using 32-bit data transfer command. Page 683 2013/6/11 21. 21.4 ROM protection Writing and erasing 2013/6/11 TMPM366FDXBG/FYXBG/FWXBG Page 684 TMPM366FDXBG/FYXBG/FWXBG 22. Port Section Equivalent Circuit Schematic Basically, the gate symbols written are the same as those used for the standard CMOS logic IC [74HCXX] series. The input protection resistance ranges from several tens of Ω to several hundreds of Ω. Feedback resistor and Damping resistor are shown with a typical value. 22.1 PA0 to 7,PB0 to 7 Output Data P-ch Open-drain Enable N-ch Output Enable I/O port Input Data Programmable Pull-up Resistor Input Enable Pull-up Enable Pull-down Enable Programmable Pull-down Resistor 22.2 PC0 to 2, PD0 to 7, PE0 to 7, PF1 to 7, PG0 to 4, PH0 to 4, PI0 to 7 Output Data P-ch Open-drain Enable N-ch Output Enable I/O port Input Data Schmitt Programmable Pull-up Resistor Input Enable Pull-up Enable Pull-down Enable Programmable Pull-down Resistor Page 685 2013/6/11 22. 22.3 Port Section Equivalent Circuit Schematic PJ0 to 7, PK0 to 3 22.3 TMPM366FDXBG/FYXBG/FWXBG PJ0 to 7, PK0 to 3 Input AIN Output Data P-ch Open-drain Enable N-ch Output Enable I/O port Input Data Schmitt Programmable Pull-up Resistor Input Enable Pull-up Enable Pull-down Enable Programmable Pull-down Resistor 22.4 PF0 Output Data P-ch Open-drain Enable N-ch Output Enable I/O port BOOT Schmitt Input Enable Programmable Pull-up Resistor Pull-up Enable Pull-down Enable Programmable Pull-down Resistor 2013/6/11 Page 686 TMPM366FDXBG/FYXBG/FWXBG 22.5 PG5 Output Data P-ch Open-drain Enable N-ch Output Enable I/O port Input Data Schmitt Programmable Pull-up Resistor Input Enable Pull-up Enable Pull-down Enable Programmable Pull-down Resistor Note:Only when input is enabled, this pin tolerates 5V input. 22.6 X1,X2 Clock Oscillator Circuit 500kΩ (typ.) 1kΩ (typ.) X2 High-frequency Oscillation Enable X1 22.7 RESET,NMI Pull-up Resistor Reset Input Port Schmitt Page 687 2013/6/11 22. 22.8 Port Section Equivalent Circuit Schematic BSC 22.8 TMPM366FDXBG/FYXBG/FWXBG BSC BSC Input Port Schmitt Pull-down Resistor 22.9 MODE MODE Input Port Schmitt (Note)MODE pin is fixed to GND. 22.10 FTEST3 FTEST3 Open (Note)FTEST3 pin is fixed to Open. 22.11 AVREFH,AVREFL ADC AVDD3 AVREFH AVSS String Resistor AVDD3 AVREFL AVSS 2013/6/11 Page 688 TMPM366FDXBG/FYXBG/FWXBG 23. Electrical Characteristics 23.1 Absolute Maximum Ratings Parameter Symbol Rating DVDD3A −0.3 to 3.9 DVDD3C −0.3 to 3.9 AVDD3 −0.3 to 3.9 RVDD3 −0.3 to 3.9 Except below pins VIN1 −0.3 to VDD + 0.3 PG5 VIN2 −0.3 to 5.5 Low-level Per pin IOL 5 output current Total ΣIOL 50 High-level Per pin IOH −5 output current Total ΣIOH -50 Supply voltage Input voltage Power consumption (Ta = 85 °C) Soldering temperature(10 s) Storage temperature Operating Temperature Except during Flash W/E Unit V V mA PD 600 mW TSOLDER 260 °C TSTG −40 to 125 °C TOPR During Flash W/E −40 to 85 °C 0 to 70 Note:Absolute maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no Absolute maximum rating value is exceeded with respect to current, voltage, power consumption, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning. Page 689 2013/6/11 23. 23.2 Electrical Characteristics DC Electrical Characteristics (1/3) 23.2 TMPM366FDXBG/FYXBG/FWXBG DC Electrical Characteristics (1/3) Ta = −40 to 85 °C Parameter DVDD3A DVDD3C Supply voltage AVDD3 RVDD3 DVSSA = DVSSB = AVSS = RVSS = DVSSC = 0V Symbol DVDD3A DVDD3C AVDD3 RVDD3 Min. Typ. (Note 1) Max. Unit without USB 2.7 − 3.6 V with USB 3.0 − 3.45 V −0.3 − fOSC = 8 to 16 MHz fsys = 1 to 48 MHz (Note 2) PA, PB, PC, PD, PE, PF Low-level input voltage Condition PG, PH, PI, PJ, PK, RESET, NMI, MODE, BSC VIL1 X1 VIL4 2.7 V ≤ DVDD3A ≤ 3.6 V (Include 5V tolerant input pin) 2.7 V ≤ RVDD3 ≤ 3.6 V 0.2 DVDD3A V 0.2 RVDD3 PA, PB, PC, PD, PE, PF High-level input voltage PG4 to 0, PH, PI, PJ, PK, RESET, NMI, MODE, BSC VIL1 PG5 VIL3 X1 VIL2 2.7 V ≤ RVDD3 ≤ 3.6 V VOL IOL = 2 mA, 2.7 V ≤ DVDD3A ≤ 3.6 V − − 0.4 VOH IOH = −2 mA, 2.7 V ≤ DVDD3A ≤ 3.6 V 2.4 − DVDD3A 2.4 − DVDD3A − 0.02 ±5 − 0.05 ±10 150 Low-level output voltage High-level PA, PB, PC, PD, PE, PF output PG4 to 0, PH, PI, PJ, PK voltage PG5 2.7 V ≤ DVDD3A ≤ 3.6 V 0.8 DVDD3A DVDD3A+0.3 − V 5.5 0.8 RVDD3 0.0 ≤ VIN ≤ DVDD3A RVDD3 + 0.3 V V Input leakage current ILI1 Output leakage current ILO Pull-up resister at Reset RRST 2.7 V ≤ DVDD3A ≤ 3.6 V − 50 Hysteresis voltage VTH1 2.7 V ≤ DVDD3A ≤ 3.6 V 0.3 0.6 − V Programmable pull-up/pull-down resistor PKH 2.7 V ≤ DVDD3A ≤ 3.6 V − 50 150 kΩ Pin capacitance (Except power supply pins) CIO fc = 1 MHz − − 10 pF 0.0 ≤ VIN ≤ AVDD3 μA 0.2 ≤ VIN ≤ DVDD3A − 0.2 0.2 ≤ VIN ≤ AVDD3 − 0.2 kΩ Note 1: Ta = 25 ×C, DVDD3A = DVDD3C = RVDD3 = AVDD3 = 3.3 V, unless otherwise noted. Note 2: The same voltage must be supplied to DVDD3A, AVDD3, and RVDD3. Note 3: Ensure that all power suply source, including DVDD3C, is power-off and then power-on again when DVDD3A, RVDD3 and AVDD3 falls below 2.7V which is minimum operation voltage. 2013/6/11 Page 690 TMPM366FDXBG/FYXBG/FWXBG 23.3 DC Electrical Characteristics (2/3) DVDD3A = DVDD3C = RVDD3 = AVDD3 = 2.7 V to 3.6 V DVSSA = DVSS3C = RVSS = AVSS, Ta = −40 to 85 °C Parameter Symbol Condition Min. Typ. Max. − − 2 − − 2 Unit Per pin IOL1 2.7 V ≤ DVDD3A ≤ 3.6 V Except PG5 Per pin IOL2 2.7 V ≤ DVDD3A ≤ 3.6 V PG5 Low-level output current ΣIOL3 Per group, Port A − − 10 ΣIOL4 Per group, Port B − − 10 ΣIOL5 Per group, Port C − − 10 ΣIOL6 Per group, Port D − − 10 ΣIOL7 Per group, Port E − − 10 ΣIOL8 Per group, Port F − − 10 ΣIOL9 Per group, PortG − − 20 ΣIOL10 Per group, Port H − − 10 ΣIOL11 Per group, Port I − − 10 ΣIOL12 Per group, Port J − − 10 ΣIOL13 Per group, Port K − − 10 Total, all Port − − 35 − − -2 − − -2 ΣIOL mA mA Per pin IOH1 2.7 V ≤ DVDD3A ≤ 3.6 V Except PG5 Per pin IOH2 2.7 V ≤ DVDD3A ≤ 3.6 V PG5 High-level output current ΣIOH3 Per group, Port A − − -10 ΣIOH4 Per group, Port B − − -10 ΣIOH5 Per group, Port C − − -10 ΣIOH6 Per group, Port D − − -10 ΣIOH7 Per group, Port E − − -10 ΣIOH8 Per group, Port F − − -10 ΣIOH9 Per group, Port G − − -10 ΣIOH10 Per group, Port H − − -10 ΣIOH11 Per group, Port I − − -10 ΣIOH12 Per group, Port J − − -10 ΣIOH13 Per group, Port K − − -10 Total, all Port − − -35 ΣIOH mA mA Note:The same voltage must be supplied to DVDD3A, AVDD3, and RVDD3. Page 691 2013/6/11 23. 23.4 Electrical Characteristics DC Electrical Characteristics (3/3) 23.4 TMPM366FDXBG/FYXBG/FWXBG DC Electrical Characteristics (3/3) DVDD3A = DVDD3C = AVDD3 = RVDD3 = 2.7 V to 3.6 V, Ta = −40 to 85 °C Min. Typ. (Note1) Max. − 36 50 fsys = 48 MHz − 34 46 USB disabled − 21 25 STOP1 − − 80 1200 STOP2 − − 3.5 50 Parameter Symbol fsys = 48 MHz NORMAL (Note2) Gear 1/1 USB enabled NORMALGear 1/1 IDLE (Note3) Condition IDD Note 1: Ta = 25 °C, DVDD3A = DVDD3C = AVDD3 = RVDD3 = 3.3 V, unless otherwise noted. Note 2: IDD NORMAL: Measurement condition Operation program : The dhrystone ver. 2.1 operated in FLASH Operation peripheral : 16-bit timer / event counter, ADC, serial channel, serial bus interface, asynchronous serial channel, USB Device controller (EP1, 3, 5 and 7 operated) Note 3: IDD IDLE: Measurement condition Operation peripheral : All peripheral stopped The currents flow through DVDD3A, DVDD3C, AVDD3 and RVDD3 are included. 2013/6/11 Page 692 Unit mA μA TMPM366FDXBG/FYXBG/FWXBG 23.5 12-bit ADC Electrical Characteristics DVDD3A = DVDD3C = AVDD3 = RVDD3 = AVREFH = 2.7 V to 3.6 V AVSS = DVSSA = DVSSC = RVSS = AVREFL = 0 Ta = −40 to 85 °C Parameter Analog reference voltage(+) Symbol Condition Min. Typ. Max Unit AVREFH − 2.7 3.3 3.6 V Analog input voltage VAIN − AVSS − VREFH V Power supply current of analog reference voltage − 1.5 2.0 mA IREF − 0.02 0.1 μA − 4 6 − 2 6 AD conversion Non-AD DVSSA = DVSSC = AVSS conversion INL error DNL error Offset error AIN resistance ≤ 600 Ω − AIN load capacitance ≥ 0.1 μF − 3 6 Full-scale error − 3 6 INL error − 3 6 − 2 6 − 4 6 − 2 6 1.0 − 10 Conversion time ≥ 1.0 μs LSB DNL error Offset error AIN resistance ≤ 600 Ω − AIN load capacitance ≥ 33 pF Conversion time ≥ 1.66 μs Full-scale error Conversion time Tconv − μs Note 1: 1LSB = (AVREFH − AVSS)/4096 [V] Note 2: Peripheral functions are disable. Page 693 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6 TMPM366FDXBG/FYXBG/FWXBG AC Electrical Characteristics 23.6.1 AC measurement condition The AC characteristics data of this chapter is measured under the following conditions unless otherwise noted ・ Output levels: High = 0.8 × DVDD3A, 0.8 × DVDD3C ・ Output levels: Low = 0.2 × DVDD3A, 0.2 × DVDD3C ・ Input levels: Refer to low-level input voltage and high-level input voltage in "DC Electrical Characteristics". ・ Load capacity: CL = 30pF 23.6.2 Serial Channel (SIO/UART) 23.6.2.1 I/O Interface mode In the table below, the letter x represents the SIO operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. (1) SCLK input mode [Data input] Parameter Symbol Equation 40 MHz 48 MHz Min. Max Min. Max Min. Max SCLK Clock High width (input) tSCH 4x − 100 − 83.3 − SCLK Clock Low width (input) tSCL 4x − 100 − 83.3 − SCLK cycle tSCY tSCH + tSCL − 200 − 166.6 − tSRD 30 − 30.0 − 30.0 − tHSR x + 30 − 55.0 − 50.8 − Min. Max. Min. Max. Min. Unit ns Valid Data input → SCLK rise or fall(Note1) SCLK rise or fall(Note1) → Input Data hold [Data output] Parameter Symbol Equation 40 MHz SCLK Clock High width (input) tSCH 4x − SCLK Clock Low width (input) tSCL 4x − SCLK cycle tSCY tSCH + tSCL − tOSS tSCY/2 − 3x− 45 − tOHS tSCY/2 − Output Data → SCLK rise or fall (Note 1) SCLK rise or fall (Note1) → Output Data hold 120 (Note3) 120 (Note3) 240 0.00 (Note2) 120 48 MHz − − − − − 107.5 (Note3) 107.5 (Note3) 215 0.00 (Note2) 107.5 Max. Unit − − − ns − − Note 1: SCLK rise/fall : SCLK rise mode uses the rise timing of SCLK. SCLK fall mode uses the fall timing of SCLK. Note 2: Use the frequency of SCLK in a range where the calculation value keeps positive. 2013/6/11 Page 694 TMPM366FDXBG/FYXBG/FWXBG Note 3: The value indicates a minimum value that enables tOSS to be zero or more. Page 695 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics (2) TMPM366FDXBG/FYXBG/FWXBG SCLK output mode Parameter Equation Symbol 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. tSCY 4x − 100 − 83.3 − Output Data → SCLK rise tOSS tSCY/2 − 30 − 20 − 11.7 − SCLK rise → Output hold Data hold tOHS tSCY/2 − 30 − 20 − 11.7 − Valid Data Input → SCLK rise tSRD 45 − 45 − 45 − SCLK rise → Input Data hold tHSR 0 − 0 − 0 − SCLK cycle (programmable) tSCY SCLK (Output Mode/ Input High Mode) tSCH tSCL SCLK (Input Low Mode) tOSS OUTPUT DATA TxD INPUT DATA RxD 2013/6/11 tOHS 0 1 tSRD 2 3 tHSR 0 VALID 1 2 VALID VALID Page 696 3 VALID Unit ns TMPM366FDXBG/FYXBG/FWXBG 23.6.3 Serial Bus Interface (I2C/SIO) 23.6.3.1 I2C Mode In the table below, the letter x represents the I2C operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. n denotes the value of n programmed into the SCK (SCL output frequency select) field in the SBIxCR. Parameter Symbol Equation Standard Mode Fast Mode Unit Min. Max. Min. Max. Min. Max. tSCL 0 − 0 100 0 400 kHz Hold time for START condition tHD; STA − − 4.0 − 0.6 − μs SCL Low width (Input) (Note 1) tLOW − − 4.7 − 1.3 − μs SCL High width (Input) (Note 2) tHIGH − − 4.0 − 0.6 − μs Setup time for a repeated START condition tSU; STA (Note5) − 4.7 − 0.6 − μs Data hold time (Input) (Note 3, 4) tHD; DAT − − 0.0 − 0.0 − μs Data setup time tSU; DAT − − 250 − 100 − ns Setup time for a STOP condition tSU; STO − − 4.0 − 0.6 − μs tBUF (Note5) − 4.7 − 1.3 − μs SCL clock frequency Bus free time between stop condition and start condition Note 1: SCL clock Low width (output) = (2n - 1 + 58)/x Note 2: SCL clock High width (output) = (2n - 1 + 14)/x On I2C-bus specification, Maximum Speed of Standard Mode is 100kHz, Fast mode is 400khz. Internal SCL Frequency setting should comply with Note1 & Note2 shown above. Note 3: The output data hold time is equal to 4x of internal SCL. Note 4: The Philips I2C-bus specification states that a device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. However, this SBI does not satisfy this requirement. Also, the output buffer for SCL does not incorporate slope control of the falling edges; therefore, the equipment manufacturer should design so that the input data hold time shown in the table is satisfied, including tr/tf of the SCL and SDA lines. Note 5: Software -dependent Note 6: The Philips I2C-bus specification instructs that if the power supply to a Fast-mode device is switched off, the SDA and SCL I/O pins must be floating so that they don't obstruct the bus lines. However, this SBI does not satisfy this requirement. tSCL tf tLOW tr tHIGH SCL tHD;STA tSU;DAT tHD;DAT tSU;STA tSU;STO tBUF SDA S Sr P S: Start condition Sr: Repeated start condition P: Stop condition Page 697 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.3.2 TMPM366FDXBG/FYXBG/FWXBG Clock-Synchronous 8-Bit SIO mode In the table below, the letter x represents the I2C operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. (1) SCK Input Mode (The electrical specifications below are for an SCK signal with a 50% duty cycle.) [Data input] Parameter Symbol Equation 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. SCK Clock High width (input) tSCH 4x − 100 − 83.3 − SCK Clock Low width (input) tSCL 4x − 100 − 83.3 − SCK cycle tSCY tSCH + tSCL − 200 − 166 − Valid Data input → SCK rise tSRD 30 − x − 5 − 9 − SCK rise → Input Data hold tHSR 2x + 30 − 80 − 71.7 − Min. Max. Min. Max. Min. Unit ns [Data output] Parameter Symbol Equation 40 MHz SCK Clock High width (input) tSCH 4x − SCK Clock Low width (input) tSCL 4x − SCK cycle tSCY tSCH + tSCL − Output Data → SCK rise tOSS tSCY/2 − 3x − 45 − SCK rise → Output Data hold tOHS tSCY/2 + x − 120 48 MHz − (Note2) 120 − (Note2) 240 − 0 − (Note1) 145 − Max. 108 Unit − (Note2) 108 − (Note2) 215 − 0 ns − (Note1) 128 − Note 1: Use the frequency of SCK in a range where the calculation value keeps positive. Note 2: The value indicates a minimum value that enables tOSS to be zero or more. (2) SCK Output Mode (The electrical specifications below are for an SCK signal with a 50% duty cycle.) Parameter Symbol Equation 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. SCK cycle (programmable) tSCY 16x − 400 − 333 − Output Data → SCK rise tOSS tSCY/2 − 20 − 180 − 147 − SCK rise → Output Data hold tOHS tSCY/2 − 20 − 180 − 147 − Valid Data input → SCK rise tSRD x + 45 − 70 − 65.8 − SCK rise → Input Data hold tHSR 0 − 0 − 0 − Note 1: SCK cycle after automatic wait becomes 14x. Note 2: tOSS after automatic wait may be tSCY/2-x-20. 2013/6/11 Page 698 Unit ns TMPM366FDXBG/FYXBG/FWXBG tSCY tSCH tSCL SCK tOSS OUTPUT DATA SO INPUT DATA SI tOHS 0 1 tSRD 2 3 tHSR 1 2 VALID VALID 0 VALID Page 699 3 VALID 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.4 TMPM366FDXBG/FYXBG/FWXBG Synchronous serial Interface (SSP) 23.6.4.1 AC measurement conditions The letter "T" used in the equations in the table represents the period of internal bus frequency (fsys). ・ Output levels: High = 0.7 × DVDD3A, Low = 0.3 × DVDD3A ・ Input levels: High = 0.9 × DVDD3A, Low = 0.1 × DVDD3A Note:The "Equation" column in the table shows the specifications under the conditions DVDD3A = 2.7V to 3.6V. Parameter Equation Symbol Min. Max. (m)T SPCLK Period (Master) Tm However more than 50ns − SPCLK Period (Slave) Ts (n)T − SPCLK rise up time tr − SPCLK fall down time tf − Master mode: SPCLK low level pulse width tWLM Master mode: SPCLK high level pulse width Slave mode: SPCLK low level pulse width Slave mode: SPCLK high level pulse width Master mode: SPCLK rise/fall → output data valid Master mode: SPCLK rise/fall → output data hold fsys=40MHz fsys=48MHz (m=4, n=12) (m=4, n=12) 100 83.3 (10MHz) (12MHz) 300 250 (3.3MHz) (4MHz) 15 15 15 15 15 15 (m)T/2 - 15 − 35 26.7 tWHM (m)T/2 - 15 − 35 26.7 tWLS (n)T/2 - 15 − 135 110 tWHS (n)T/2 - 15 − 135 110 tODSM − 15 15 15 tODHM (m)T/2 - 13 − 35 28.7 tIDSM 30 − 30 30 tIDHM 5 − 5 5 tOFSM (m)T - 15 (m)T + 15 85 Å` 115 68.3 Å` 98.3 tODSS − (3T) + 35 110 97.5 (n)T/2 + (2T) − 200 166.7 tIDSS 10 − 10 10 tIDHS (3T) + 10 − 85 72.5 tOFSS (n)T + 5 − 305 255 ns Master mode: SPCLK rise/fall → input data valid delay time Master mode: SPCLK rise/fall → input data hold Master mode: SPFSS valid → SPCLK rise/fall Slave mode: SPCLK rise/fall → output data valid delay time tODHS Slave mode: SPCLK rise/fall → output data hold Slave mode: SPCLK rise/fall → input data valid delay time Slave mode: SPCLK rise/fall → input data hold Slave mode: SPFSS valid → SPCLK rise/fall (Note1) Note:Baud rate clock is set under below condition Master Mode m=(×(1+))= fsys /fSPCLK is set only even number. 65024≥ m ≥8 Slave mode n=(×(1+))= fsys /fSPCLK 2013/6/11 Unit 65024≥ n≥12 Page 700 TMPM366FDXBG/FYXBG/FWXBG 23.6.4.2 SSP SPI mode (Master) ・ fsys / 8 ≥ fSPCLK ≥ fsys / 65024 (1) Master SSPxCR0=0 (Data is latched on the first edge.) Tm tOFSM SPCLK output (Master) (SSPxCR0=0) tf tWH Internal clock state tWL tr SPCLK output (Master) (SSPxCR0=1) Internal clock state tODSM tODSM tODHM SPDO output tIDSM tIDHM SPDI input SPFSS output Page 701 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics (2) TMPM366FDXBG/FYXBG/FWXBG Master SSPxCR0=1 (Data is latched on the second edge.) Tm tOFSM tf tWH SPCLK output (Master) tWL (SSPxCR0=1) tr SPCLK output (Master) (SSPxCR0=0) tODSM tODHM SPDO output tIDSM tIDHM SPDI input SPFSS output 23.6.4.3 SSP SPI mode (Slave) ・ fsys / 12 ≥ fSPCLK ≥ fsys / 65024 (1) Slave SSPxCR0=0 (Data is latched on the first edge.) Ts tOFSS tf tWH SPCLK input tWL (SSPxCR0=0) tr SPCLK input (SSPxCR0=1) tIDSS tIDHS SPDI input tODSS SPDO output SPFSS input 2013/6/11 Page 702 tODHS TMPM366FDXBG/FYXBG/FWXBG (2) Slave SSPCR0=1 (Data is latched on the second edge.) Ts tOFSS tf tWH SPCLK input tWL (SSPxCR0=1) tr SPCLK input (SSPxCR0=0) tIDSS tIDHS SPDI input tODSS tODHS SPDO output SPFSS input Page 703 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.5 TMPM366FDXBG/FYXBG/FWXBG 16-bit timer / event counter 23.6.5.1 Event Counter In the table below, the letter x represents the 16-bit timer / event counter operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. Parameter Symbol Equation 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. Unit Clock Low pulse width tVCKL 2x + 100 − 150 − 142 − ns Clock High pulse width tVCKH 2x + 100 − 150 − 142 − ns 23.6.5.2 Capture In the table below, the letter x represents the 16-bit timer / event counter operation clock cycle time which is identical to the fsys cycle time. It varies depending on the programming of the clock gear function. Parameter Symbol Equation 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. Unit Low pulse width tCPL 2x + 100 − 150 − 142 − ns High pulse width tCPH 2x + 100 − 150 − 142 − ns 23.6.6 External Interrupt In the table below, the letter x represents the fsys cycle time. 1. Except STOP1 and STOP2 release interrupts Parameter Symbol Equation 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. INT0 to 9 low level pulse width tINTAL x + 100 − 125 − 121 − ns INT0 to 9 high level pulse width tINTAH x + 100 − 125 − 121 − ns 2. STOP1 release interrupts Parameter Symbol Min. Max. Unit INT0 to 9 low level pulse width tINTBL 100 − ns INT0 to 9 high level pulse width tINTBH 100 − ns Symbol Min. Max. Unit tINTCH 500 − μs 3. STOP2 release interrupts Parameter INT0 to 9 high level pulse width 2013/6/11 Unit Page 704 TMPM366FDXBG/FYXBG/FWXBG 23.6.7 NMI 1. Except STOP1 and STOP2 release interrupts Parameter NIM low level pulse width Symbol Min. Max. Unit tINTCL 100 − ns Symbol Min. Max. Unit tINTBL 100 − ns Symbol Min. Max. Unit tINTCL 500 − μs 2. STOP1 release interrupts Parameter NMI low level pulse width 3. STOP2 release interrupts Parameter NMI low level pulse width 23.6.8 SCOUT Pin AC Characteristic Parameter Symbol Equation 40 MHz 48 MHz Min. Max. Min. Max. Min. Max. Unit High pulse width tSCH 0.5T − 5 − 7.5 − 5.4 − ns Low pulse width tSCL 0.5T − 5 − 7.5 − 5.4 − ns Note:In the above table, the letter T represents the cycle time of the SCOUT output clock. tSCH tSCL SCOUT Page 705 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.9 TMPM366FDXBG/FYXBG/FWXBG ADTRG Trigger Input Pin AC Characteristic In the table below, the letter x represents fsys cycle time. It varies depending on the programming of the clock gear function. Equation Symbol Parameter 40MHz Min. Max. Min. 48MHz Max. Min. Low level pulse width Tadl 2 x + 20 − 70 − 62 − High level pulse interval Tadh 2 x + 20 − 70 − 62 − 23.6.10 USB Timing DVDD3A = DVCC3C = RVDD = 3.0 to 3.45V fsys = 48MHz Symbol Min. Max. D+,D− rise time tR 4 20 D+,D− withdraw time tF 4 20 VCRS 1.3 2.0 Parameter Data Line crossover voltage & & VCRS 90% Page 706 V 10% tF Unit ns 90% 10% tR 2013/6/11 Max. Unit ns TMPM366FDXBG/FYXBG/FWXBG 23.6.11 External bus interface AC Characteristic 23.6.11.1 Separate Bus mode Conditional variable : RWS = 1, TW = 2, RWH = 1 and CSH =1 ・ ・ ・ ・ RWS : Number of setup cycle insertion before RD, WR asserted (TW = 0, 1, 2 or 4) TW : Number of internal wait insertion (TW = 0 to 15) RWH : Number of RD, WR recovery cycle insertion (RWH = 0 to 6 or 8) CSH : Number of CSn recovery cycle insertion (CSH = 0, 1, 2 or 4) DVDD3A = DVDD3C = AVDD3 = RVDD3 = 2.7 V to 3.6 V Parameter Symbol Equation 40MHz 48MHz Min. Max. Min. Max. Min. Max. System clock period (x) tSYS x - 25 − 20.8 − External bus clock (EXBCLK) tCYC x - 25 − 20.8 − A[23:0] valid → RD, WR asserted tAC x (1+RWS)−10 - 40 − 31.7 − tCAR x (1+RWH+CSH)−10 - 65 − 52.5 − A[23:0] valid → D[15:0] data input tAD - x (2+RWS+TW)−40 − 85 − 64.2 RD asserted → D[15:0] data input tRD - x (1+TW)−30 − 45 − 32.5 RD Low-level pulse width tRR x (1+TW)−12 - 63 − 50.5 − RD, WR negated → A[23:0] hold RD negated → D[15:0] hold tHR 0 - 0 − 0 − RD negated → A[23:0] output tRAE x (1+RWH+CSH)−15 - 60 − 47.5 − WR Low-level pulse width tWW x (1+TW)−15 - 60 − 47.5 − D[15:0] valid → WR negated tDW x (1+TW)−15 - 60 − 47.5 − WR negated → D[15:0] hold tWD x (1+RWH)−7 - 43 − 34.7 − Page 707 Unit ns 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics (1) TMPM366FDXBG/FYXBG/FWXBG Read cycle timing ( minimum bus cycle ) (Neither Cycle expander, RD setup, Internal wait, CS recovery nor RD recovery function are used.) 3CLK / 1BUS cycle tCYC EXBCLK CSn A[23:0] Address Address tAD Hi-Z D[15:0] tAC Hi-Z Data tRD tRR RD BELL BELH (2) Read cycle timing ( 1 bus cycle per 6 clock ) (RD setup, Internal wait, CS recovery and RD recovery function are set to 1 cycle though Cycle expander function is not used.) 6CLK / 1BUS cycle RD recovery period RD setup period Internal wait period CS recovery period EXBCLK CSn A[23:0] D[15:0] Address Address tHR tAD Hi-Z tAC Hi-Z Data tCAR tRD tRAE RD tRR BELL BELH 2013/6/11 Page 708 TMPM366FDXBG/FYXBG/FWXBG (3) Write cycle timing ( minimum bus cycle ) (Neither Cycle expander, WR setup, Internal wait, CS recovery nor WR recovery function are used.) 3CLK / 1BUS cycle tCYC EXBCLK CSn A[23:0] Address Address tDW Hi-Z D[15:0] tWD Hi-Z Data Data tAC tWW WR BELL BELH (4) Write cycle timing ( 1 bus cycle per 6 clock ) (WR setup, Internal wait, CS recovery and WR recovery function are set to 1 cycle though Cycle expander function is not used.) 6CLK / 1BUS cycle WR recovery period WR setup period Internal wait period CS recovery period EXBCLK CSn A[23:0] D[15:0] WR Address Address tDW Hi-Z tWD Hi-Z Data tAC tCAR tRAE tWW BELL BELH Page 709 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.11.2 TMPM366FDXBG/FYXBG/FWXBG Multiplex Bus mode Conditional variable : ALE = 1, RWS = 1, TW = 2, RWH = 1 and CSH =1 ・ ・ ・ ・ ・ ALE : Number of ALE cycle insertion (ALE = 0, 1, 2 or 4) RWS : Number of setup cycle insertion before RD, WR asserted (TW = 0, 1, 2 or 4) TW : Number of internal wait insertion (TW = 0 to 15) RWH : Number of RD, WR recovery cycle insertion (RWH = 0 to 6 or 8) CSH : Number of CSn recovery cycle insertion (CSH = 0, 1, 2 or 4) DVDD3A = DVDD3C = AVDD3 = RVDD3 = 2.7 V to 3.6 V Parameter Symbol Equation 40MHz 48MHz Min. Max. Min. Max. Min. Max. System clock period (x) tSYS x − 25 − 20.8 − External bus clock (EXBCLK) tCYC x − 25 − 20.8 − A[23:0] valid → ALE negated tAL x (1+ALE)-26 − 24 − 15.7 − ALE negated → A[23:0] hold tLA x (1+RWS)-7 − 43 − 34.7 − ALE high pulse width tLL x (1+ALE)-15 − 35 − 26.7 − ALE negated → RD or WR asserted tLC x (1+RWS)-7 − 43 − 34.7 − RD or WR negated → ALE asserted tCL x (1+RWH+CSH)-20 − 55 − 42.5 − x(2+ALE+RWS)-19 − 81 − 64.3 − x (1+RWH+CSH)-15 − 60 − 60 − − x (3+ALE+RWS+TW)-35 − 140 − 111 A[15:0] valid → RD or WR asserted tACL A[23:16] valid → RD or WR asserted tACH RD or WR negated → A[31:16] hold tCAR A[15:0] valid → D[15:0] input tADL A[23:16] valid → D[15:0] input tADH RD asserted → D[15:0] input tRD − x (1+TW)-30 − 45 − 32.5 RD low pulse width tRR x (1+TW)-12 − 63 − 50.5 − RD negated → D[15:0] hold tHR 0 − 0 − 0 − RD negated → A[23:0] output tRAE x (1+RWH+CSH)-15 − 60 − 47.5 − WR low pulse width tWW x (1+TW)-15 − 60 − 47.5 − D[15:0] valid → WR negated tDW x (1+TW)-20 − 55 − 42.5 − WR negated → D[15:0] hold tWD x (1+RWH)-7 − 43 − 34.7 − 2013/6/11 Page 710 Unit ns TMPM366FDXBG/FYXBG/FWXBG (1) Read cycle timing ( minimum bus cycle ) (Neither Cycle expander, ALE wait, RD setup, Internal wait, CS recovery nor RD recovery function are used.) 4CLK / 1BUS cycle tCYC EXBCLK CSn tLL tCL ALE tLA tAL A[23:16] Address Address tHR tADH /tADL AD[15:0] Hi-Z Address tRD tLC Data Hi-Z Address tCAR tRAE tRR RD BELL BELH Page 711 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics (2) TMPM366FDXBG/FYXBG/FWXBG Read cycle timing ( 1 bus cycle per 8 clock ) (ALE wait, RD setup, Internal wait, CS recovery and RD recovery function are set to 1 cycle though Cycle expander function is not used.) 8CLK / 1BUS cycle Internal wait period ALE wait period CS recovery period RD recovery period RD setup period EXBCLK CSn tLL tCL ALE tAL A[23:16] tLA Address Address tADH /tADL AD[15:0] tHR Hi-Z Address tLC RD tRD tRR BELL BELH 2013/6/11 Page 712 Data Hi-Z tCAR tRAE TMPM366FDXBG/FYXBG/FWXBG (3) Read cycle timing ( 1 bus cycle per 9 clock ) (ALE wait, RD setup, Internal wait, CS recovery and RD recovery function are set to 1 cycle though Cycle expander function is set double.) 9CLK / 1BUS cycle ALE wait period (1 cycle x 2) Internal wait period (1 cycle x 2) RD recovery period (1 cycle x 2) CS recovery period (1 cycle x 2) EXBCLK CSn ALE A[23:16] Address AD[15:0] Address Address Hi-Z Data RD BELL BELH Page 713 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics (4) TMPM366FDXBG/FYXBG/FWXBG Write cycle timing ( minimum bus cycle ) (Neither Cycle expander, ALE wait, WR setup, Internal wait, CS recovery nor WR recovery function are used.) 4CLK / 1BUS cycle tCYC EXBCLK CSn tLL tCL ALE tLA tAL A[23:16] Address Address tACH /tACL AD[15:0] tDW Address Data Address tCAR tLC tWW WR BELL BELH 2013/6/11 tWD Page 714 TMPM366FDXBG/FYXBG/FWXBG (5) Write cycle timing ( 1 bus cycle per 8 clock ) (ALE wait, WR setup, Internal wait, CS recovery and WR recovery function are set to 1 cycle though Cycle expander function is not used.) 8CLK / 1BUS cycle Internal wait period ALE wait period CS recovery period WR recovery period WR setup period EXBCLK CSn tLL tCL ALE tAL A[23:16] tLA Address Address tACH /tACL AD[15:0] tDW Hi-Z Data Address tCAR tLC WR tWD tWW BELL BELH Page 715 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.12 TMPM366FDXBG/FYXBG/FWXBG Debug Communication 23.6.12.1 SWD Interface Symbol Min. Max. CLK cycle Tdck 100 − CLK rise →Output data hold Td1 4 − CLK fall → Output data hold Td2 − 30 Input data valid ←CLK rise Tds 20 − CLK rise → Input data hold Tdh 15 − Symbol Min. Max. CLK cycle Tdck 100 − CLK rise →Output data hold Td3 4 − CLK fall → Output data hold Td4 − 50 Input data valid ←CLK rise Tds 20 − CLK rise → Input data hold Tdh 15 − Parameter 23.6.12.2 ns JTAG Interface Parameter Tdck CLK INPUT (SWCLK) (TCK) Td2 Td1 OUTPUT DATA (SWDIO) Td4 Td3 OUTPUT DATA (TDO) INPUT DATA (SWDIO) (TMS/TDI) Tds 2013/6/11 Unit Tdh Page 716 Unit ns TMPM366FDXBG/FYXBG/FWXBG 23.6.13 ETM Trace Symbol Min. Max. Unit ttclk 50 − ns TRACEDATA valid ← TRACECLK rise tsetupr 2 − ns TRACECLK rise → TRACEDATA hold tholdr 1 − ns TRACEDATA valid ← TRACECLK fall tsetupf 2 − ns TRACECLK fall → TRACEDATA hold tholdf 1 − ns Parameter TRACECLK cycle ttclk TRACECLK tsetupf TRACEDATA 0 to 3 23.6.14 tholdf 0 tsetupr tholdr 1 2 3 On chip oscillator Parameter Symbol Oscillating frequency IHOSC Condition Min. Typ. Max. Ta = -40 to 85°C 8 10 12 Ta =0 to 65°C 8.5 10 11.5 Unit MHz Note:The on-chip-oscillator can not be used as system clock (fsys) which is required oscillation accuracy. 23.6.15 External clock input Parameter External clock frequency External clock duty Symbol Min. Typ. Max. Unit tehcin 8 − 48 MHz − 45 − 55 % External clock input rise time trehc − − 10 ns External clock input fall time tfehc − − 10 ns tehcin EHCLKIN trehc tfehc Page 717 2013/6/11 23. 23.6 Electrical Characteristics AC Electrical Characteristics 23.6.16 TMPM366FDXBG/FYXBG/FWXBG Flash Memory Characteristics Parameter Guarantee on Flash-Mmory Rewriting 2013/6/11 condition DVDD3A = DVDD3C = AVDD3 = RVDD3 = 2.7 V to 3.6 V, Ta = 0 to 70 °c Page 718 Min. Typ. Max. unit - - 100 times TMPM366FDXBG/FYXBG/FWXBG 23.7 Recommended Oscillation Circuit X1 X2 Figure 23-1 High-frequency oscillation connection Note:To obtain a stable oscillation, load capacity and the position of the oscillator must be configured properly. Since these factors are strongly affected by substratepatterns, please evaluate oscillation stability using the substrate you use. The TX03 has been evaluated by the oscillator vender below. Please refer this information when selecting external parts 23.7.1 Ceramic oscillator The TX03 recommends the high-frequency oscillator by Murata Manufacturing Co., Ltd. Please refer to the following URL for details. http://www.murata.co.jp 23.7.2 Crystal oscillator The TX03 recommends the high-frequency oscillator by KYOCERA Crystal Device Corporation. Please refer to the following URL for details http://www.kinseki.co.jp 23.7.2.1 Precautions for designing printed circuit board Be sure to design printed circuit board patterns that connect a crystal unit with other oscillation elements so that the lenghts of such patterns become shortest possible to prevent deterioration of characteristics due to stray capacitances and wiring inductance. For multi-layer circuit boards, it is importtant not to wire the ground and other signal patterns right beneath the oscillation circuit. For more information ,please refer to the URL of the oscillator vendor. Page 719 2013/6/11 23. 23.8 Electrical Characteristics Handling Precaution 23.8 TMPM366FDXBG/FYXBG/FWXBG Handling Precaution 23.8.1 Power-on sequence The power-on sequence must include the time for the internal regulator, internal flash memory and internal oscillator to be stable and the reset. In the TX03, the internal circuit automatically insert the time for the internal regulator which requires the time at least 1 ms and after this, internal reset operation requires 4096 cycles on internal oscillation, therefore, A little bit of time differences occur until CPU start operate. And there are multiple independent Power supply, however please operate the power-on procedure simultaneously. The time required to achieve stable oscillation varies with system. At cold reset, the external reset pin must be kept "Low" for a duration of time sufficiently long enough for the internal regulator and oscillator to be stable. Figure 23-2 shows the power-on sequence. DVDD3A, DVDD3C, RVDD3, AVDD3 2.7 V 0V Internal Oscillator (IHOSC) 1 ms Internal reset period RESET 4096 cycles Internal reset signal 1.4 ms Figure 23-2 Power-on sequence 2013/6/11 Page 720 TMPM366FDXBG/FYXBG/FWXBG 24. Package Dimensions Type: P-TFBGA109-0909-0.65-002 Unit:mm 9.0 9.0 A 0.2 S S 0.32±0.05 0.15 1.2MAX B x4 0.325 0.325 M L K J H G F E D C B A 0.925 0.65 0.65 0.12 S 1 2 3 4 5 6 7 8 9 10 11 12 0.925 Φ0.43±0.05 Page 721 0.15 0.08 S AB S 2013/6/11 24. Package Dimensions TMPM366FDXBG/FYXBG/FWXBG 2013/6/11 Page 722 RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "Product") without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. • PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative. • Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. • Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. • The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. • ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. • Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. • Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.