TMPN3120FE5MG

TMPN3120FE5MG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TMPN3120FE5MG Neuron® Chip for Distributed Intelligent Control Networks (LONW ORKS®) The TMPN3120FE5MG features extra single-chip memory in the form of a 3 Kbyte EEPROM, a 4 Kbyte SRAM, and a 16 Kbyte ROM. Neuron Chips have all the built-in communications and control functions ® required to implement LONWORKS nodes. These nodes may then be easily integrated into highly reliable distributed intelligent control networks. The typical functions for this chip are described below. Features Main features of the 20 MHz Neuron Chip (compared with the TMPN3120E1M) • Increased communication speed The maximum transmission speed has been increased twofold: 1.25 Mbps → 2.5 Mbps (This value applies to Single-Ended Mode only.) Weight: 1.1 g (typ.) • Shortened response time The amount of time required from I/O input to I/O output has been greatly reduced. Maximum speed 7 ms → 3 to 4 ms • Increased I/O object speed The execution time for all objects has been halved. Example) Serial I/O 9600 bps Parallel I/O 1.2 µs/byte 1 2005-10-24 TMPN3120FE5MG I/O functions • Eleven programmable I/O pins • Two programmable 16-bit timers and counters built in • More than thirty different types of I/O functions to handle a wide range of input and output • ROM firmware image containing preprogrammed I/O drivers, greatly simplifying application programs Network functions • High-impedance communication port • Two CPUs for communication protocol processing built in The communications and application CPUs execute in parallel. • Equipped with a built-in LonTalk protocol supporting all seven levels of the ISO OSI reference model • The ROM firmware image contains a complete network operating system, greatly simplifying application programs. • Built-in twisted-pair wire transceiver with improved common-mode and drive current capabilities • Equipped with communications modes and communication speeds to support various types of external transceivers • Communication port transceiver modes and logical addresses are stored within the EEPROM. Can be amended via the network. Other functions • Application programs are also stored within the EEPROM. Can be updated by downloading over the network. • Built-in watchdog timer • Each chip has a unique ID number. Effective during the logical installation of networks • Low electrical consumption mode supported through a sleep mode • Built-in selectable reset time Prolongs the power-on reset time for at least 50 ms and keeps the operation stable during this time. time for reset after power on, however, can be set to 3-clock delay mode by programming. The reset • High-impedance communication port (CP0 to CP3) The communication port pins (CP0 to CP3) attain high impedance. This eliminates the need for an external relay. • Built-in low-voltage detection circuit Prevents incorrect operations and writing errors in the EEPROM during drops in power voltage. An external LVD must be used to assert reset at a power supply voltage below 4.5 V if the Neuron Chip is operated at 20 MHz. • Built-in programmable LVD (low-voltage detection) circuit An external LVD input pin (LVDin) is used to assert reset at a given voltage. • Firmware version 10 • The package is SOP32-P-525-1.27 (lead-free type). 2 2005-10-24 TMPN3120FE5MG Timing for the main I/O objects during 20 MHz Neuron Chip operations I/O Model Parallel Bitshift Magcard Magtrack1 Neurowire master Neurowire slave Serial Touch Frequency output 2.4 µs/byte 10 MHz Timing 1.2 µs/byte 20 MHz Timing 1, 10 or 15 kbps Up to 8334 bps Up to 7246 bps 1, 10 or 20 kbps Up to 18 kbps 600, 1200, 2400 or 4800 bps Supported Resolution: 0.4 to 51.2 µs Max range: 26.21 to 3355 ms Resolution: 0.2 to 25.6 µs Max range: 13.1 to 1678 ms 2, 20 or 30 kbps Up to 16668 bps Up to 14492 bps 2, 20 or 40 kbps Up to 36 kbps 1200, 2400, 4800 or 9600 bps Not supported Resolution: 0.2 to 25.6 µs Max range: 13.1 to 1678 ms Resolution: 0.1 to 12.8 µs Max range: 6.55 to 839 ms Other timer/counter The specifications for the main timers during 20 MHz operations are as follows: Watchdog timer Millisecond timers Second timers Delay ( ) function Get_tick_count ( ) function 420 ms 1 to 32000 ms 1 to 65000 s 1 to 32767 counts 409.6 µs per count 3 2005-10-24 TMPN3120FE5MG Block Diagram Network communications port • Application I/O • General-purpose I/O • Parallel I/O • Serial I/O • Two timer/counters Etc. Clock and control 50 ms delay Low-voltage detector reset circuit 3-clock delay circuit Mode select Item CPU RAM ROM EEPROM 16-bit timer/counter External memory interface Package TMPN3120FE5MG 8-bit CPU × 3 4,096 bytes 16,384 bytes 3,072 bytes 2 channels Not available 32-pin SOP 4 2005-10-24 TMPN3120FE5MG Pin Connections TMPN3120FE5MG Note: All NC pins should be open. Pin Functions Pin No. 15 14 1 Pin Name CLK1 CLK2 ~RESET I/O Input Output I/O (built-in pull-up) I/O 8 ~SERVICE (built-in configurable pull-up) I/O I/O 3, 30 to 28 IO4 to IO7 (built-in configurable pull-up) I/O Input Input Input I/O Service pin. Indicator output during operation. Large current sink capacity (20 mA). General I/O port. General I/O port. One of IO4 to IO7 can be specified as the No.1 timer/counter input. Output signals can be output to IO0. IO4 can be used as the No.2 timer/counter input with IO1 as output. General I/O port. Can be used for serial communication with other devices. Power input (5.0 V typ.) Power input (0 V GND) Input pin for programmable LVD (normally connected to VDD) Bidirectional port for communications. Supports several communications protocols through specifying of mode. Pin Function Oscillator connection, or external clock input Oscillator connection. Leave open when the external clock is input to CLK1. Reset pin (active low) 7 to 4 IO0 to IO3 27, 26, 24 11, 12, 18, 25, 32 9, 10, 13, 16, 23, 31 2 19, 20, 17, 21, 22 IO8 to IO10 VDD VSS LVDin CP0 to CP4 *: ● The ~SERVICE and IO4 to IO7 terminals are programmable pull-ups. ● All VDD terminals must be externally connected. ● All VSS terminals must be externally connected. 5 2005-10-24 TMPN3120FE5MG Maximum Ratings (VSS = 0 V, VSS typ.) Item Power supply voltage Input voltage Input voltage CP0 to CP3 Drain current Source current Power dissipation Storage temperature Symbol VDD VIN (1) VIN (2) IDD ISS PD Tstg Rating −0.3 to 7.0 −0.3 to VDD + 0.3 V −0.5 to VDD + 1.3 V VIN (2) ≤ 7.3 (Note 1) 200 300 800 −65 to 150 Unit V V V mA mA mW °C Note 1: VIN (2) should not exceed 7.3 V. Operating Conditions Item Operating voltage Input voltage (TTL) Symbol VDD VIH VIL VIH VIL VIH VIL fosc Topr Min 4.5 2.0 VSS VDD − 0.8 V VSS ― −0.1 0.625 −40 Typ. 5.0 ― ― ― ― ― ― ― ― Max 5.5 VDD 0.8 VDD 0.8 VDD + 1.0 V ― 20 85 Unit V V V V V V MHz °C Input voltage (CMOS) Input voltage CP0 to CP3 (differential mode) Operating frequency Operating temperature 6 2005-10-24 TMPN3120FE5MG Electrical Characteristics DC characteristic (VDD = 5.0 V ± 10%, VSS = 0 V, Ta = −40 to 85°C) (The above operating conditions apply unless otherwise stated.) Item LOW level input voltage (1) LOW level input voltage (2) HIGH level input voltage (1) HIGH level input voltage (2) LOW output voltage (1) LOW output voltage (2) LOW output voltage (3) HIGH output voltage (1) HIGH output voltage (2) HIGH output voltage (3) HIGH output voltage (4) Input current Pull-up current Low-voltage detection level Symbol VIL (1) VIL (2) VIH (1) VIH (2) VOL (1) VOL (2) VOL (3) VOH (1) VOH (2) VOH (3) VOH (4) IIN IPU (Note 3) VLVD Pins IO0 to IO10 CP0, CP3, CP4, ~SERVICE ~RESET IO0 to IO10 CP0, CP3, CP4, ~SERVICE ~RESET IO0 to IO3 ~SERVICE, ~RESET CP2, CP3 Others (Note 1) IO0 to IO3 ~SERVICE CP2, CP3 Others (Note 1) (Note 2) IO4 to IO7 ~SERVICE, ~RESET VDD Test Condition ― ― ― ― IOL = 20 mA IOL = 10 mA IOL = 40 mA IOL = 1.4 mA IOH = −1.4 mA IOH = −1.4 mA IOH = −40 mA IOH = −1.4 mA VIN = VSS to VDD VIN = 0 V ― Min 0 0 2.0 VDD − 0.7 V 0 0 0 0 VDD − 0.4 V VDD − 0.4 V VDD − 1.0 V VDD − 0.4 V −10 −30 3.8 Max 0.8 VDD × 0.3 VDD VDD 0.8 0.4 1.0 0.4 VDD VDD VDD VDD 10 −300 4.5 Unit V V V V V V V V V V V µA µA V Note 1: Output voltage characteristics exclude the CLK2 pin. Note 2: Excludes pull-up input pins. Note 3: The IO4 to IO7 and ~SERVICE pins have programmable pull-ups. ~RESET has a fixed pull-up. Item 20 MHz clock 10 MHz clock Operating mode current consumption 5 MHz clock 2.5 MHz clock 1.25 MHz clock 0.625 MHz clock Sleep mode current consumption IDD (SLP) IDD (OP) Symbol Typ. 34 16 8.5 4.5 2.3 1.3 16 Max 55 30 15 8 5 3 100 µA mA Unit Note: Test conditions for current dissipation: VDD = 5 V; all output = with no load; all input = 0.2 V or below or VDD − 0.2 V; programmable pull-up = off; crystal oscillator clock input; differential receiver disabled. The current value (typ.) is a typical value when Ta = 25°C. The current value (max) applies to the rated temperature range at VDD = 5.5 V. 200 µA (typ.) to 600 µA (max) is added to the current of the differential receiver when the receiver is enabled. The differential receiver is enabled by either of the following conditions: ● W hen the Neuron Chip is in Run mode and the communication ports are in Differential mode. ● W hen the Neuron Chip is in Sleep mode, the communication ports are in Differential mode, and the Comm Port Wakeup is not masked. 7 2005-10-24 TMPN3120FE5MG Echelon, Neuron, LON, LonTalk, NodeBuilder, LONW ORKS, 3150 and 3120 are trademarks of Echelon Corporation (“Echelon”) registered in the United States and other countries. The Neuron Chip is manufactured by Toshiba under license from Echelon. A licensing agreement between the customer and Echelon must be concluded before purchase of any of the Neuron Chip products. The Neuron Chip itself does not include the I C object function. You need the “I C Library” supplied by Echelon. 2 2 The Neuron Chip and the I C Library neither convey nor imply a right under any I C patent rights of Philips Electronics N.V. (“Philips”) to make, use or sell any product employing such patent rights. Please refer all questions 2 regarding I C patents and licenses to Philips at the following: Mr. Gert-Jan Hesselmann Corporate Intellectual Property Philips International B.V. Prof. Holstlaan 6 Building WAH 1-100 P.O. Box 220 5600 AE, Eindhoven, The Netherlands Phone : +31 40 274 32 61 Fax : +31 40 274 34 89 E-mail : Gert.Jan.Hesselmann@philips.com 2 2 8 2005-10-24 TMPN3120FE5MG Package Dimensions Weight : 1.1g (typ.) Lead-free type 9 2005-10-24 TMPN3120FE5MG About solderability, following conditions were confirmed Solderability (1) Use of Sn-63Pb solder Bath ⋅ solder bath temperature = 230°C ⋅ dipping time = 5 seconds ⋅ the number of times = once ⋅ use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath ⋅ solder bath temperature = 245°C ⋅ dipping time = 5 seconds ⋅ the number of times = once ⋅ use of R-type flux 10 2005-10-24