TMPR4938XBG-300

64-Bit TX System RISC TX49 Family TMPR4938 Rev. 2.0 R4000/R4400/R5000 are a trademark of MIPS Technologies, Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. 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These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer’s own risk. The products described in this document may include products subject to the foreign exchange and foreign trade laws. The products described in this document contain components made in the United States and subject to export control of the U.S. authorities. Diversion contrary to the U.S. law is prohibited. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. © 2005 TOSHIBA CORPORATION All Rights Reserved Preface Thank you for new or continued patronage of TOSHIBA semiconductor products. This is the 2005 edition of the user’s manual for the TMPR4938 64-bit RISC microprocessor. This databook is written so as to be accessible to engineers who may be designing a TOSHIBA microprocessor into their products for the first time. No prior knowledge of this device is assumed. What we offer here is basic information about the microprocessor, a discussion of the application fields in which the microprocessor is utilized, and an overview of design methods. On the other hand, the more experienced designer will find complete technical specifications for this product. Toshiba continually updates its technical information. Your comments and suggestions concerning this and other Toshiba documents are sincerely appreciated and may be utilized in subsequent editions. For updating of the data in this manual, or for additional information about the product appearing in it, please contact your nearest Toshiba office or authorized Toshiba dealer. March 2005 Table of Contents Table of Contents Handling Precautions TMPR4938 1. Overview and Features ........................................................................................................................................... 1-1 1.1 Overview........................................................................................................................................................ 1-1 1.2 Features .......................................................................................................................................................... 1-1 1.2.1 Features of the TX49/H3 core.............................................................................................................. 1-2 1.2.2 Features of TX4938 peripheral functions ............................................................................................ 1-2 2. Configuration.......................................................................................................................................................... 2-1 2.1 TX4938 block diagram .................................................................................................................................. 2-1 3. Signals ............................................................................................................................................................. 3-1 3.1 Pin Signal Description ................................................................................................................................... 3-1 3.1.1 Signals Common to SDRAM and External Bus Interfaces.................................................................. 3-1 3.1.2 SDRAM Interface Signals ................................................................................................................... 3-2 3.1.3 External Interface Signals.................................................................................................................... 3-3 3.1.4 DMA Interface Signals ........................................................................................................................ 3-4 3.1.5 PCI Interface Signals ........................................................................................................................... 3-4 3.1.6 Serial I/O Interface Signals.................................................................................................................. 3-6 3.1.7 Timer Interface Signals........................................................................................................................ 3-6 3.1.8 Parallel I/O Interface Signals ............................................................................................................... 3-6 3.1.9 AC-link Interface Signals .................................................................................................................... 3-7 3.1.10 Interrupt Signals................................................................................................................................... 3-7 3.1.11 SPI Interface Signals............................................................................................................................ 3-7 3.1.12 ISA/ATA Interface Signals................................................................................................................... 3-8 3.1.13 ETHER Interface Signals (Channel 0)................................................................................................. 3-8 3.1.14 ETHER Interface Signals (Channel 1)................................................................................................. 3-9 3.1.15 NAND Flash Memory Interface Signals............................................................................................ 3-10 3.1.16 Extended EJTAG Interface Signals.................................................................................................... 3-10 3.1.17 Clock Signals ..................................................................................................................................... 3-11 3.1.18 Initialization Signal............................................................................................................................ 3-11 3.1.19 Test Signals........................................................................................................................................ 3-11 3.1.20 Power Supply Pins ............................................................................................................................. 3-12 3.2 3.3 Boot Configuration ...................................................................................................................................... 3-13 Pin multiplex................................................................................................................................................ 3-17 4. Address Mapping.................................................................................................................................................... 4-1 4.1 TX4938 Physical Address Map...................................................................................................................... 4-1 4.2 Register Map.................................................................................................................................................. 4-2 4.2.1 Addressing ........................................................................................................................................... 4-2 4.2.2 Ways to Access to Internal Registers ................................................................................................... 4-2 4.2.3 Register Map........................................................................................................................................ 4-3 5. Configuration Registers .......................................................................................................................................... 5-1 5.1 Detailed Description ...................................................................................................................................... 5-1 5.1.1 Detecting G-Bus Timeout .................................................................................................................... 5-1 5.2 Registers......................................................................................................................................................... 5-2 5.2.1 Chip Configuration Register (CCFG) 0xE000..................................................................................... 5-3 5.2.2 Chip Revision ID Register (REVID) 0xE008...................................................................................... 5-6 5.2.3 Pin Configuration Register (PCFG) 0xE010 ....................................................................................... 5-7 5.2.4 Timeout Error Access Address Register (TOEA) 0xE018 ................................................................ 5-10 5.2.5 Clock Control Register (CLKCTR) 0xE020...................................................................................... 5-11 5.2.6 G-Bus Arbiter Control Register (GARBC) 0xE030........................................................................... 5-14 5.2.7 Register Address Mapping Register (RAMP) 0xE048 ...................................................................... 5-15 i Table of Contents 5.2.8 6. Clocks Jump Address Register (JMPADR) 0xE058 ...................................................................................... 5-16 ............................................................................................................................................................. 6-1 6.1 TX4938 Clock Signals ................................................................................................................................... 6-1 6.2 Power-Down Mode ........................................................................................................................................ 6-5 6.2.1 Halt Mode and Doze Mode.................................................................................................................. 6-5 6.2.2 Power Reduction for Peripheral Modules............................................................................................ 6-5 6.3 Power-On Sequence ....................................................................................................................................... 6-6 7. External Bus Controller .......................................................................................................................................... 7-1 7.1 Features .......................................................................................................................................................... 7-1 7.2 Block Diagram ............................................................................................................................................... 7-2 7.3 Detailed Explanation...................................................................................................................................... 7-3 7.3.1 External Bus Control Register ............................................................................................................. 7-3 7.3.2 Global/Boot-up Options....................................................................................................................... 7-4 7.3.3 Address Mapping................................................................................................................................. 7-5 7.3.4 External Address Output...................................................................................................................... 7-6 7.3.5 Data Bus Size....................................................................................................................................... 7-7 7.3.6 Access Mode........................................................................................................................................ 7-9 7.3.7 Access Timing ................................................................................................................................... 7-13 7.3.8 Clock Options .................................................................................................................................... 7-19 7.3.9 ISA /ATA Mode ................................................................................................................................. 7-20 7.4 Register ........................................................................................................................................................ 7-24 7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7)...... 7-25 7.5 Timing Diagrams ......................................................................................................................................... 7-28 7.5.1 ACE* Signal ...................................................................................................................................... 7-29 7.5.2 Normal mode access (Single, 32-bit Bus).......................................................................................... 7-31 7.5.3 Normal mode access (Burst, 32-bit Bus) ........................................................................................... 7-35 7.5.4 Normal Mode Access (Single, 16-bit bus) ......................................................................................... 7-37 7.5.5 Normal Mode Access (Burst, 16-bit Bus).......................................................................................... 7-41 7.5.6 Normal Mode Access (Single, 8-bit Bus) .......................................................................................... 7-43 7.5.7 Normal Mode Access (Burst, 8-bit Bus)............................................................................................ 7-46 7.5.8 Page Mode Access (Burst, 32-bit Bus) .............................................................................................. 7-48 7.5.9 External ACK Mode Access (32-bit Bus) .......................................................................................... 7-50 7.5.10 READY Mode Access (32-bit Bus) ................................................................................................... 7-56 7.5.11 ISA IO Space Access ......................................................................................................................... 7-58 7.5.12 ATA/PIO Transfer Mode Access........................................................................................................ 7-60 7.6 Flash ROM, SRAM Usage Example ........................................................................................................... 7-62 8. DMA Controller...................................................................................................................................................... 8-1 8.1 Features .......................................................................................................................................................... 8-1 8.2 Block Diagram ............................................................................................................................................... 8-2 8.3 Detailed Explanation...................................................................................................................................... 8-4 8.3.1 Transfer Mode...................................................................................................................................... 8-4 8.3.2 On-chip Registers ................................................................................................................................ 8-5 8.3.3 External I/O DMA Transfer Mode ....................................................................................................... 8-5 8.3.4 Internal I/O DMA Transfer Mode ........................................................................................................ 8-8 8.3.5 Memory-Memory Copy Mode............................................................................................................. 8-9 8.3.6 Memory Fill Transfer Mode ................................................................................................................ 8-9 8.3.7 Single Address Transfer ....................................................................................................................... 8-9 8.3.8 Dual Address Transfer ....................................................................................................................... 8-12 8.3.9 DMA Transfer.................................................................................................................................... 8-17 8.3.10 Chain DMA Transfer ......................................................................................................................... 8-18 8.3.11 D ynamic Chain Operation ................................................................................................................. 8-20 8.3.12 Interrupts............................................................................................................................................ 8-21 8.3.13 Transfer Stall Detection Function ...................................................................................................... 8-21 8.3.14 Arbitration Among DMA Channels ................................................................................................... 8-22 ii Table of Contents 8.3.15 Restrictions in Access to PCI Bus...................................................................................................... 8-22 8.4 DMA Controller Registers ........................................................................................................................... 8-23 8.4.1 DMA Master Control Register (DM0MCR, DM1MCR)................................................................... 8-25 8.4.2 DMA Channel Control Register (DM0CCRn, DM1CCRn) .............................................................. 8-27 8.4.3 DMA Channel Status Register (DM0CSRn, DM1CSRn)) ................................................................ 8-31 8.4.4 DMA Source Address Register (DM0SARn, DM1SARn) ................................................................ 8-33 8.4.5 DMA Destination Address Register (DM0DARn, DM1DARn)........................................................ 8-34 8.4.6 DMA Chain Address Register (DM0CHARn, DM1CHARn) ........................................................... 8-35 8.4.7 DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)............................................. 8-36 8.4.8 DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) .................................... 8-37 8.4.9 DMA Count Register (DM0CNTRn, DM1CNTRn).......................................................................... 8-38 8.4.10 DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) ........................................................ 8-39 8.5 Timing Diagrams ......................................................................................................................................... 8-40 8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM) ................................................. 8-40 8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-41 8.5.3 Single Address Single Transfer from I/O to Memory (32-bit SRAM)............................................... 8-42 8.5.4 Single Address Burst Transfer from Memory to I/O (32-bit ROM) .................................................. 8-43 8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM) ................................................ 8-44 8.5.6 Single Address Single Transfer from Memory to I/O (16-bit ROM) ................................................. 8-46 8.5.7 Single Address Single Transfer from I/O to Memory (16-bit SRAM)............................................... 8-47 8.5.8 Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) .............................. 8-48 8.5.9 Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) ............................ 8-49 8.5.10 Single Address Single Transfer from Memory to I/O (64-bit SRAM)............................................... 8-50 8.5.11 Single Address Single Transfer from I/O to Memory (64-bit SDRAM) ............................................ 8-51 8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE* Signal is Set to Output ...................................................................................... 8-52 8.5.13 Single Address Single Transfer from Memory to I/O (32-bit SDRAM) ............................................ 8-53 8.5.14 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) ............................................ 8-54 8.5.15 External I/O Device – SRAM Dual Address Transfer ....................................................................... 8-55 8.5.16 External I/O Device – SDRAM Dual Address Transfer .................................................................... 8-57 8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer................................................. 8-59 9. SDRAM Controller................................................................................................................................................. 9-1 9.1 9.2 Characteristics................................................................................................................................................ 9-1 Block Diagram ............................................................................................................................................... 9-2 9.3 Detailed Explanation...................................................................................................................................... 9-3 9.3.1 Supported SDRAM configurations...................................................................................................... 9-3 9.3.2 Address Mapping................................................................................................................................. 9-4 9.3.3 Initialization of SDRAM ..................................................................................................................... 9-9 9.3.4 Initialization of Memory Data, ECC/Parity ....................................................................................... 9-10 9.3.5 Low Power Consumption Function ................................................................................................... 9-11 9.3.6 Bus Errors .......................................................................................................................................... 9-12 9.3.7 Memory Read and Memory Write ..................................................................................................... 9-12 9.3.8 Slow Write Burst................................................................................................................................ 9-12 9.3.9 Clock Feedback ................................................................................................................................. 9-12 9.3.10 ECC ................................................................................................................................................... 9-13 9.4 Registers....................................................................................................................................................... 9-17 9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1) 0x8010 (ch. 2) 0x8018 (ch. 3)........................................................................................................... 9-18 9.4.2 SDRAM Timing Register (SDCTR) 0x8040 ..................................................................................... 9-20 9.4.3 SDRAM Command Register (SDCCMD) 0x8058 ............................................................................ 9-22 9.4.4 ECC Control Register (ECCCR) 0xA000.......................................................................................... 9-23 9.4.5 ECC Status Register (ECCSR) 0xA008............................................................................................. 9-25 9.5 Timing Diagrams ......................................................................................................................................... 9-26 9.5.1 Single Read (64-bit Bus).................................................................................................................... 9-26 9.5.2 Single Write (64-bit Bus) ................................................................................................................... 9-28 9.5.3 Burst Read (64-bit Bus) ..................................................................................................................... 9-30 9.5.4 Burst Write (64-bit Bus) .................................................................................................................... 9-31 iii Table of Contents 9.5.5 9.5.6 9.5.7 9.5.8 9.6 Burst Write (64-bit Bus, Slow Write Burst) ....................................................................................... 9-32 Single Read (32-bit Bus).................................................................................................................... 9-33 Single Write (32-bit Bus) ................................................................................................................... 9-35 Low Power Consumption and Power Down Mode ........................................................................... 9-37 SDRAM Usage Example ............................................................................................................................. 9-42 10. PCI Controller....................................................................................................................................................... 10-1 10.1 Features ........................................................................................................................................................ 10-1 10.1.1 Overall ............................................................................................................................................... 10-1 10.1.2 Initiator Function ............................................................................................................................... 10-1 10.1.3 Target Function .................................................................................................................................. 10-2 10.1.4 PCI Arbiter......................................................................................................................................... 10-2 10.1.5 PDMAC (PCI DMA Controller)........................................................................................................ 10-2 10.2 Block Diagram ............................................................................................................................................. 10-3 10.3 Detailed Explanation.................................................................................................................................... 10-4 10.3.1 Terminology Explanation .................................................................................................................. 10-4 10.3.2 On-chip Register ................................................................................................................................ 10-4 10.3.3 Supported PCI Bus Commands ......................................................................................................... 10-6 10.3.4 Initiator Access (G-Bus → PCI Bus Address Conversion) ................................................................ 10-8 10.3.5 Target Access (PCI Bus → G-Bus Address Conversion)................................................................. 10-10 10.3.6 Post Write Function ......................................................................................................................... 10-12 10.3.7 Endian Switching Function.............................................................................................................. 10-12 10.3.8 66 MHz Operation Mode................................................................................................................. 10-13 10.3.9 Power Management ......................................................................................................................... 10-14 10.3.10 PDMAC (PCI DMA Controller)...................................................................................................... 10-15 10.3.11 Error Detection, Interrupt Reporting................................................................................................ 10-18 10.3.12 PCI Bus Arbiter................................................................................................................................ 10-20 10.3.13 PCI Boot .......................................................................................................................................... 10-22 10.3.14 Set Configuration Space .................................................................................................................. 10-23 10.3.15 PCI Clock ........................................................................................................................................ 10-23 10.4 PCI Controller Control Register................................................................................................................. 10-24 10.4.1 ID Register (PCIID) 0xD000 ........................................................................................................... 10-26 10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004.................................................................. 10-27 10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008............................................................... 10-30 10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C......................................................................... 10-31 10.4.5 P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0xD010 ................ 10-32 10.4.6 P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0xD014 ................ 10-33 10.4.7 P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0xD018 ................ 10-33 10.4.8 P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0xD01C ................ 10-34 10.4.9 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD020......................... 10-34 10.4.10 P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD024 ...................................... 10-35 10.4.11 Subsystem ID Register (PCISID) 0xD02C...................................................................................... 10-36 10.4.12 Capabilities Pointer Register (PCICAPPTR) 0xD034..................................................................... 10-37 10.4.13 PCI Configuration 2 Register (PCICFG2) 0xD03C......................................................................... 10-38 10.4.14 G2P Timeout Count Register (G2PTOCNT) 0xD040 .................................................................... 10-39 10.4.15 G2P Status Register (G2PSTATUS) 0xD080................................................................................... 10-40 10.4.16 G2P Interrupt Mask Register (G2PMASK) 0xD084 ....................................................................... 10-41 10.4.17 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088.................................................... 10-42 10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C.............................................................. 10-43 10.4.19 P2G Configuration Register (P2GCFG) 0xD090 ............................................................................ 10-44 10.4.20 P2G Status Register (P2GSTATUS) 0xD094 .................................................................................. 10-46 10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098 ....................................................................... 10-47 10.4.22 P2G Current Command Register (P2GCCMD) 0xD09C ................................................................ 10-48 10.4.23 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100 ........................................... 10-49 10.4.24 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 ................................................... 10-51 10.4.25 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 ............................................................... 10-52 10.4.26 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) 0xD10C ............................................. 10-53 10.4.27 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 ................................................... 10-54 iv Table of Contents 10.4.28 10.4.29 10.4.30 10.4.31 10.4.32 10.4.33 10.4.34 10.4.35 10.4.36 10.4.37 10.4.38 10.4.39 10.4.40 10.4.41 10.4.42 10.4.43 10.4.44 10.4.45 10.4.46 10.4.47 10.4.48 10.4.49 10.4.50 10.4.51 10.4.52 10.4.53 10.4.54 10.4.55 10.4.56 10.4.57 10.4.58 10.4.59 10.4.60 10.4.61 10.4.62 10.4.63 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 ............................................. 10-55 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 ................................................ 10-56 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C ............................................. 10-57 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120 ..................... 10-59 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128 ..................... 10-60 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0xD130 ..................... 10-61 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0xD138.................................. 10-62 G2P Memory Space 0 Address Mask Register (G2PM0MASK) 0xD140................................. 10-63 G2P Memory Space 1 Address Mask Register (G2PM1MASK) 0xD144................................. 10-64 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 0xD148................................. 10-65 G2P I/O Space Address Mask Register (G2PIOMASK) 0xD14C ............................................. 10-66 G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 0xD150 .......................... 10-67 G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 0xD158 .......................... 10-68 G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 0xD160 .......................... 10-69 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0xD168....................................... 10-70 PCI Controller Configuration Register (PCICCFG) 0xD170 .................................................... 10-71 PCI Controller Status Register (PCICSTATUS) 0xD174 ................................................................ 10-74 PCI Controller Interrupt Mask Register (PCICMASK) 0xD178 ............................................... 10-76 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0xD180 ..................... 10-77 P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0xD188 ..................... 10-78 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0xD190 ..................... 10-79 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198.................................. 10-80 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0 .............................................. 10-81 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4 ................................................... 10-82 G2P Interrupt Acknowledge Data Register (G2PINTACK) 0xD1C8 ........................................ 10-83 G2P Special Cycle Data Register (G2PSPC) 0xD1CC.................................................................... 10-84 Configuration Data 0 Register (PCICDATA0) 0xD1D0.................................................................. 10-85 Configuration Data 1 Register (PCICDATA1) 0xD1D4.................................................................. 10-86 Configuration Data 2 Register (PCICDATA2) 0xD1D8.................................................................. 10-87 Configuration Data 3 Register (PCICDATA3) 0xD1DC ................................................................. 10-88 PDMAC Chain Address Register (PDMCA) 0xD200 .................................................................... 10-89 PDMAC G-Bus Address Register (PDMGA) 0xD208.................................................................... 10-90 PDMAC PCI Bus Address Register (PDMPA) 0xD210 .................................................................. 10-91 PDMAC Count Register (PDMCTR) 0xD218 ................................................................................ 10-92 PDMAC Configuration Register (PDMCFG) 0xD220.................................................................... 10-93 PDMAC Status Register (PDMSTATUS) 0xD228 ........................................................................ 10-95 10.5 PCI Configuration Space Register ............................................................................................................. 10-98 10.5.1 Capability ID Register (Cap_ID) 0xDC .......................................................................................... 10-99 10.5.2 Next Item Pointer Register (Next_Item_Ptr) 0xDD...................................................................... 10-100 10.5.3 Power Management Capability Register (PMC) 0xDE ................................................................. 10-101 10.5.4 Power Management Control/Status Register (PMCSR) 0xE0 ................................................. 10-102 11. Serial I/O Port ....................................................................................................................................................... 11-1 11.1 Features ........................................................................................................................................................ 11-1 11.2 Block Diagram ............................................................................................................................................. 11-2 11.3 Detailed Explanation.................................................................................................................................... 11-3 11.3.1 Overview ........................................................................................................................................... 11-3 11.3.2 Data Format ....................................................................................................................................... 11-3 11.3.3 Serial Clock Generator....................................................................................................................... 11-5 11.3.4 Data Reception................................................................................................................................... 11-7 11.3.5 Data Transmission ............................................................................................................................. 11-7 11.3.6 DMA Transfer.................................................................................................................................... 11-7 11.3.7 Flow Control...................................................................................................................................... 11-8 11.3.8 Reception Data Status........................................................................................................................ 11-8 11.3.9 Reception Time Out ........................................................................................................................... 11-9 11.3.10 Software Reset ................................................................................................................................... 11-9 11.3.11 Error Detection/Interrupt Signaling ..................................................................................................11-10 11.3.12 Multi-Controller System ...................................................................................................................11-11 11.4 Registers......................................................................................................................................................11-12 v Table of Contents 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.4.9 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0) Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) ..........................................................................11-13 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0) DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1)........................................................11-15 DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0) DMA/Interrupt Status Register 1 (SIDISR1) 0xF408 (Ch. 1) ..........................................................11-17 Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0) Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1) .......................................11-19 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0) FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1) .........................................................................11-20 Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0) Flow Control Register 1 (SIFLCR1) 0xF414 (Ch. 1) .......................................................................11-21 Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch. 0) Baud Rate Control Register 1 (SIBGR1) 0xF418 (Ch. 1) ................................................................11-22 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1) ...................................................................11-23 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1).....................................................................11-24 12. Timer/Counter....................................................................................................................................................... 12-1 12.1 12.2 Features ........................................................................................................................................................ 12-1 Block Diagram ............................................................................................................................................. 12-2 12.3 Detailed Explanation.................................................................................................................................... 12-3 12.3.1 Overview ........................................................................................................................................... 12-3 12.3.2 Counter Clock.................................................................................................................................... 12-3 12.3.3 Counter .............................................................................................................................................. 12-4 12.3.4 Interval Timer Mode .......................................................................................................................... 12-4 12.3.5 Pulse Generator Mode ....................................................................................................................... 12-6 12.3.6 Watchdog Timer Mode ...................................................................................................................... 12-7 12.4 Registers....................................................................................................................................................... 12-9 12.4.1 Timer Control Register n (TMTCRn) TMTCR0 0xF000 TMTCR1 0xF100 TMTCR2 0xF200... 12-10 12.4.2 Timer Interrupt Status Register n (TMTISRn) TMTISR0 0xF004 TMTISR1 0xF104 TMTISR2 0xF204 ............................................................................................................................12-11 12.4.3 Compare Register An (TMCPRAn) TMCPRA0 0xF008 TMCPRA1 0xF108 TMCPRA2 0xF208.......................................................................................................................... 12-12 12.4.4 Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C TMCPRB1 0xF10C .............................. 12-13 12.4.5 Interval Timer Mode Register n (TMITMRn) TMITMR0 0xF010 TMITMR1 0xF110 TMITMR2 0xF210 .......................................................................................................................... 12-14 12.4.6 Divide Register n (TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 .. 12-15 12.4.7 Pulse Generator Mode Register n (TMPGMRn) TMPGMR0 0xF000 TMPGMR1 0xF130 ........ 12-16 12.4.8 Watchdog Timer Mode Register n (TMWTMRn) TMWTMR2 0xF240 ....................................... 12-17 12.4.9 Timer Read Register n (TMTRRn) 0xF0F0 TMTRR0 0xF0F0 TMTRR1 0xF1F0 TMTRR2 0xF2F0 ............................................................................................................................ 12-18 13. Parallel I/O Port .................................................................................................................................................... 13-1 13.1 13.2 Characteristics.............................................................................................................................................. 13-1 Block Diagram ............................................................................................................................................. 13-1 13.3 Detailed Description .................................................................................................................................... 13-2 13.3.1 Selecting PIO Pins ............................................................................................................................. 13-2 13.3.2 General-purpose Parallel Port ............................................................................................................ 13-2 13.4 Registers....................................................................................................................................................... 13-2 13.4.1 PIO Output Data Register (PIODO) 0xF500 ..................................................................................... 13-3 13.4.2 PIO Input Data Register (PIODI) 0xF504 ......................................................................................... 13-3 13.4.3 PIO Direction Control Register (PIODIR) 0xF508 ........................................................................... 13-4 13.4.4 PIO Open Drain Control Register (XPIOOD) 0xF50C ..................................................................... 13-4 14. AC-link Controller................................................................................................................................................ 14-1 14.1 Features ........................................................................................................................................................ 14-1 vi Table of Contents 14.2 Configuration ............................................................................................................................................... 14-2 14.3 Functional Description................................................................................................................................. 14-3 14.3.1 CODEC Connection .......................................................................................................................... 14-3 14.3.2 Boot Configuration ............................................................................................................................ 14-4 14.3.3 Usage Flow ........................................................................................................................................ 14-5 14.3.4 AC-link Start Up................................................................................................................................ 14-7 14.3.5 CODEC Register Access ................................................................................................................... 14-8 14.3.6 Sample-data Transmission and Reception ......................................................................................... 14-9 14.3.7 GPIO Operation ............................................................................................................................... 14-14 14.3.8 Interrupt ........................................................................................................................................... 14-15 14.3.9 AC-link Low-power Mode .............................................................................................................. 14-15 14.4 Registers..................................................................................................................................................... 14-16 14.4.1 ACLC Control Enable Register 0xF700 ......................................................................................... 14-17 14.4.2 ACLC Control Disable Register 0xF704 ........................................................................................ 14-20 14.4.3 ACLC CODEC Register Access Register 0xF708 .......................................................................... 14-22 14.4.4 ACLC Interrupt Status Register 0xF710......................................................................................... 14-23 14.4.5 ACLC Interrupt Masked Status Register 0xF714 ............................................................................ 14-25 14.4.6 ACLC Interrupt Enable Register 0xF718 ........................................................................................ 14-25 14.4.7 ACLC Interrupt Disable Register 0xF71C....................................................................................... 14-25 14.4.8 ACLC Semaphore Register 0xF720 .............................................................................................. 14-26 14.4.9 ACLC GPI Data Register 0xF740 ................................................................................................. 14-27 14.4.10 ACLC GPO Data Register 0xF744................................................................................................ 14-28 14.4.11 ACLC Slot Enable Register 0xF748.............................................................................................. 14-29 14.4.12 ACLC Slot Disable Register 0xF74C ............................................................................................ 14-31 14.4.13 ACLC FIFO Status Register 0xF750 ............................................................................................. 14-32 14.4.14 ACLC DMA Request Status Register 0xF780................................................................................ 14-34 14.4.15 ACLC DMA Channel Selection Register 0xF784 ........................................................................... 14-35 14.4.16 ACLC Audio PCM Output Data Register 0xF7A0.......................................................................... 14-36 14.4.17 ACLC Center Data Register 0xF7A8 ............................................................................................ 14-37 14.4.18 ACLC Audio PCM Input Data Register 0xF7B0............................................................................ 14-38 14.4.19 ACLC Modem Input Data Register 0xF7BC.................................................................................. 14-39 14.4.20 ACLC Revision ID Register 0xF7FC ............................................................................................ 14-40 15. Interrupt Controller ............................................................................................................................................... 15-1 15.1 Characteristics.............................................................................................................................................. 15-1 15.2 Block Diagram ............................................................................................................................................. 15-2 15.3 Detailed Explanation.................................................................................................................................... 15-4 15.3.1 Interrupt sources ................................................................................................................................ 15-4 15.3.2 Interrupt request detection ................................................................................................................. 15-5 15.3.3 Interrupt level assigning..................................................................................................................... 15-5 15.3.4 Interrupt priority assigning ................................................................................................................ 15-6 15.3.5 Interrupt notification .......................................................................................................................... 15-7 15.3.6 Clearing interrupt requests................................................................................................................. 15-7 15.3.7 Interrupt requests ............................................................................................................................... 15-8 15.4 Registers..................................................................................................................................................... 15-10 15.4.1 Interrupt Detection Enable Register (IRDEN) 0xF600.....................................................................15-11 15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604 .................................................................. 15-12 15.4.3 Interrupt Detection Mode Register 1 (IRDM1) 0xF608 .................................................................. 15-14 15.4.4 Interrupt Level Register 0 (IRLVL0) 0xF610 .................................................................................. 15-17 15.4.5 Interrupt Level Register (IRLVL1) 0xF614 ..................................................................................... 15-19 15.4.6 Interrupt Level Register 2 (IRLVL2) 0xF618 .................................................................................. 15-21 15.4.7 Interrupt Level Register 3 (IRLVL3) 0xF61C ................................................................................. 15-22 15.4.8 Interrupt Level Register 4 (IRLVL4) 0xF620 .................................................................................. 15-24 15.4.9 Interrupt Level Register 5 (IRLVL5) 0xF624 ................................................................................ 15-26 15.4.10 Interrupt Level Register 6 (IRLVL6) 0xF628 .................................................................................. 15-28 15.4.11 Interrupt Level Register 7 (IRLVL7) 0xF62C ................................................................................. 15-30 15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640............................................................................ 15-32 15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660 ............................................................. 15-33 vii Table of Contents 15.4.14 15.4.15 15.4.16 15.4.17 15.4.18 15.4.19 15.4.20 15.4.21 16.1 16.2 Interrupt Pending Register (IRPND) 0xF680 .................................................................................. 15-34 Interrupt Current Status Register (IRCS) 0xF6A0........................................................................... 15-37 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 ................................................................... 15-39 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 ................................................................... 15-40 Interrupt Request Polarity Control Register (IRPOL) 0xF518 ........................................................ 15-41 Interrupt Request Control Register (IRRCNT) 0xF51C .................................................................. 15-42 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520 .................................. 15-43 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524 ................................ 15-44 16. Ethernet Controller ............................................................................................................................................... 16-1 Features ........................................................................................................................................................ 16-1 Block diagram.............................................................................................................................................. 16-1 16.3 Detailed explanation .................................................................................................................................... 16-2 16.3.1 Accessing the Ethernet Controller ..................................................................................................... 16-2 16.3.2 Data structure..................................................................................................................................... 16-4 16.3.3 System control model ........................................................................................................................ 16-5 16.3.4 Functional overview .......................................................................................................................... 16-6 16.3.5 DMA function block ........................................................................................................................ 16-10 16.3.6 MAC function blocks .......................................................................................................................16-11 16.3.7 Memory configuration ..................................................................................................................... 16-13 16.3.8 MAC operation ................................................................................................................................ 16-20 16.3.9 DMA operation ................................................................................................................................ 16-32 16.4 Registers..................................................................................................................................................... 16-37 16.4.1 Overview ......................................................................................................................................... 16-37 16.4.2 PCI Configuration Register group ................................................................................................... 16-42 16.4.3 DMA Control, Status Register group ............................................................................................... 16-54 16.4.4 Flow Control Register group ........................................................................................................... 16-68 16.4.5 MAC Control, Status Register group ............................................................................................... 16-70 17. SPI (Serial Peripheral Interface) Module (SPI) .................................................................................................... 17-1 17.1 17.2 Characteristics.............................................................................................................................................. 17-1 Block diagram.............................................................................................................................................. 17-2 17.3 Operational description ................................................................................................................................ 17-3 17.3.1 Operation modes................................................................................................................................ 17-3 17.3.2 Transmitter/Receiver.......................................................................................................................... 17-3 17.3.3 Baud Rate Generator.......................................................................................................................... 17-4 17.3.4 Transfer format .................................................................................................................................. 17-5 17.3.5 Interframe Delay Time Counter ......................................................................................................... 17-6 17.3.6 Buffer configuration .......................................................................................................................... 17-7 17.3.7 SPI system errors ............................................................................................................................... 17-7 17.3.8 Interrupts............................................................................................................................................ 17-7 17.4 Registers....................................................................................................................................................... 17-8 17.4.1 SPI Master Control Register (SPMCR) 0xF800 ................................................................................ 17-8 17.4.2 SPI Control Register 0 (SPCR0) 0xF804.......................................................................................... 17-9 17.4.3 SPI Control Register 1 (SPCR1) 0xF808..........................................................................................17-11 17.4.4 SPI Interframe Delay Time Counter (SPFS) 0xF80C ...................................................................... 17-12 17.4.5 SPI Status Register (SPSR) 0xF814................................................................................................ 17-13 17.4.6 SPI Data Register (SPDR) 0xF818 ................................................................................................. 17-14 18. NAND Flash Memory IPL ................................................................................................................................... 18-1 18.1 Features ........................................................................................................................................................ 18-1 18.2 Block Diagram ............................................................................................................................................. 18-2 18.2.1 System Block Diagram ...................................................................................................................... 18-2 18.2.2 Function Block Diagram.................................................................................................................... 18-2 18.3 Detailed Explanation.................................................................................................................................... 18-3 18.3.1 NAND IPL Operation Conditions...................................................................................................... 18-3 18.3.2 NAND IPL Operation ........................................................................................................................ 18-4 18.3.3 NAND Flash Memory IPL Address Map........................................................................................... 18-8 viii Table of Contents 18.3.4 18.3.5 18.3.6 19.1 19.2 NAND Flash Memory IPL Control Information...............................................................................18-11 Data configuration of NAND Flash Memory .................................................................................. 18-17 NAND Flash Memory IPL Error Handling ..................................................................................... 18-26 19. On-Chip SRAM .................................................................................................................................................... 19-1 Characteristics.............................................................................................................................................. 19-1 Block diagram.............................................................................................................................................. 19-1 19.3 Detailed explanation .................................................................................................................................... 19-2 19.3.1 Base address ...................................................................................................................................... 19-2 19.3.2 Access cycle count............................................................................................................................. 19-2 19.4 Register ........................................................................................................................................................ 19-3 19.4.1 On-chip SRAM Control Register (SRAMCR : 0x6000) ................................................................... 19-3 20. NAND Flash Memory Controller ......................................................................................................................... 20-1 20.1 20.2 Features ........................................................................................................................................................ 20-1 Block diagram.............................................................................................................................................. 20-1 20.3 Detailed operation ........................................................................................................................................ 20-2 20.3.1 Accessing NAND flash memory ....................................................................................................... 20-2 20.3.2 ECC control ....................................................................................................................................... 20-5 20.4 Registers....................................................................................................................................................... 20-6 20.4.1 NAND Flash Memory Data Transfer Register (NDFDTR) 0x5000 .................................................. 20-6 20.4.2 NAND Flash Memory Mode Control Register (NDFMCR) 0x5008................................................. 20-7 20.4.3 NAND Flash Memory Status Register (NDFSR) 0x5010 ................................................................. 20-8 20.4.4 NAND Flash Memory Interrupt Status Register (NDFISR) 0x5018 ................................................. 20-9 20.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR) 0x5020 .............................................. 20-10 20.4.6 NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0x5028 .........................................20-11 20.4.7 NAND Flash Memory Reset Register (NDFRSTR) 0x5030 ........................................................... 20-12 20.5 Timing diagram.......................................................................................................................................... 20-13 20.5.1 Command cycles and address cycles ............................................................................................... 20-13 20.5.2 Data read cycles............................................................................................................................... 20-14 20.5.3 Data write cycles.............................................................................................................................. 20-15 20.6 NAND flash memory connection example ................................................................................................ 20-16 21. Extended EJTAG Interface ................................................................................................................................... 21-1 21.1 Extended EJTAG Interface .......................................................................................................................... 21-1 21.2 JTAG Boundary Scan Test .......................................................................................................................... 21-2 21.2.1 JTAG Controller and Register ........................................................................................................... 21-2 21.2.2 Instruction Register............................................................................................................................ 21-3 21.2.3 Boundary Scan Register..................................................................................................................... 21-3 21.2.4 Device ID Register ............................................................................................................................ 21-6 21.3 Initializing the Extended EJTAG Interface .................................................................................................. 21-7 22. Electrical Characteristics ...................................................................................................................................... 22-1 22.1 Absolute maximum rating (*1) .................................................................................................................... 22-1 22.2 Recommended operating conditions ............................................................................................................ 22-1 22.3 DC characteristics ........................................................................................................................................ 22-2 22.3.1 DC characteristics of pins other than PCI Interface pins ................................................................... 22-2 22.3.2 DC characteristics of PCI Interface pins............................................................................................ 22-3 22.4 PLL power.................................................................................................................................................... 22-4 22.4.1 PLL power connection example ........................................................................................................ 22-4 22.5 AC characteristics ........................................................................................................................................ 22-5 22.5.1 MASTERCLK AC characteristics ..................................................................................................... 22-5 22.5.2 Power on AC characteristics .............................................................................................................. 22-5 22.5.3 SDRAM Interface AC characteristics................................................................................................ 22-6 22.5.4 External Bus Interface AC characteristics ......................................................................................... 22-8 22.5.5 PCI Interface AC characteristics (66 MHz) ....................................................................................... 22-9 22.5.6 PCI Interface AC characteristics (33 MHz) ....................................................................................... 22-9 ix Table of Contents 22.5.7 22.5.8 22.5.9 22.5.10 22.5.11 22.5.12 22.5.13 22.5.14 22.5.15 22.5.16 23.1 23.2 24.1 24.2 24.3 24.4 24.5 24.6 PCI EEPROM Interface AC characteristics......................................................................................22-11 DMA Interface AC characteristics ....................................................................................................22-11 Interrupt Interface AC characteristics .............................................................................................. 22-12 SIO Interface AC characteristics...................................................................................................... 22-13 Timer Interface AC characteristics .................................................................................................. 22-13 PIO Interface AC characteristics...................................................................................................... 22-14 AC-link Interface AC characteristics ............................................................................................... 22-14 NAND Flash Memory Interface AC characteristics ........................................................................ 22-15 SPI AC characteristics ..................................................................................................................... 22-16 Ethernet Interface (MII) AC characteristics..................................................................................... 22-17 23. Pinout and Package Information........................................................................................................................... 23-1 Pinout Diagram ............................................................................................................................................ 23-1 Package Dimensions .................................................................................................................................... 23-9 Notes on TX49/H3 Core .............................................................................................................................. 24-1 Notes on External Bus Controller ................................................................................................................ 24-3 Notes on DMA Controller............................................................................................................................ 24-3 Note on PCI Controller ................................................................................................................................ 24-6 Notes on Serial I/O Port ............................................................................................................................. 24-10 Notes on Ether Controller ...........................................................................................................................24-11 24. Notes on Use of TMPR4938................................................................................................................................. 24-1 25. Parts Number when Ordering ............................................................................................................................... 25-1 Appendix A A.1 A.2 A.3 A.4 A.5 TX49/H3 Core Supplement ................................................................................................................ A-1 Processor ID.................................................................................................................................................. A-1 Interrupts....................................................................................................................................................... A-1 Bus Snoop ..................................................................................................................................................... A-1 Halt/Doze mode ............................................................................................................................................ A-1 Memory access order .................................................................................................................................... A-1 TMPR4938 Revision History............................................................................................................................................1 x Handling Precautions 1 Using Toshiba Semiconductors Safely 1. Using Toshiba Semiconductors Safely TOSHIBA are continually working to improve the quality and the reliability of their products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 1-1 1 Using Toshiba Semiconductors Safely 1-2 2 Safety Precautions 2. Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions. [Explanation of labels] Indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions. Indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury. [Explanation of graphic symbol] Graphic symbol Meaning Indicates that caution is required (laser beam is dangerous to eyes). 2-1 2 Safety Precautions 2.1 General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury. Do not insert devices in the wrong orientation. Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode and resulting in injury. When power to a device is on, do not touch the device’s heat sink. Heat sinks become hot, so you may burn your hand. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to the pins of the device under test before powering it on. Otherwise, you may receive an electric shock causing injury. Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it. Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock. Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. 2-2 2 Safety Precautions 2.2 2.2.1 Precautions Specific to Each Product Group Optical semiconductor devices W hen a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and in the worst case may cause blindness. If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate type of laser protective glasses as stipulated by IEC standard IEC825-1. Ensure that the current flowing in an LED device does not exceed the device’s maximum rated current. This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up, scattering resin fragments and causing injury. When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the photocoupler. If you detect a leakage current of more than 100 µA, use the testing equipment to shut off the photocoupler’s supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into flames, resulting in fire or injury. When incorporating a visible semiconductor laser into a design, use the device’s internal photodetector or a separate photodetector to stabilize the laser’s radiant power so as to ensure that laser beams exceeding the laser’s rated radiant power cannot be emitted. If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the excessively powerful laser beams may cause injury. 2.2.2 Power devices Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly discharged all remaining electrical charge. Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious injury. When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to the device under test before powering it on. When you have finished, discharge any electrical charge remaining in the device. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. 2-3 2 Safety Precautions Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or explode, resulting in fire or injury. Use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs. If the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device to catch fire or explode, resulting in fire or injury. When designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device catching fire or exploding. Flying shrapnel can cause injury. When conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the device. Otherwise you may sustain injury caused by the device catching fire or exploding. Make sure that all metal casings in your design are grounded to earth. Even in modules where a device’s electrodes and metal casing are insulated, capacitance in the module may cause the electrostatic potential in the casing to rise. Dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it. When designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the device’s forward and reverse losses into account. The leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is used in an extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur. This may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user. A design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate while electricity is conducted to control circuits, so that the main circuit will become inactive. Malfunction of the device may cause serious accidents or injuries. W hen conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has cooled properly before handling it. Devices become hot when they are operated. Even after the power has been turned off, the device will retain residual heat which may cause a burn to anyone touching it. 2.2.3 Bipolar ICs (for use in automobiles) If your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to prevent negative current from flowing in. The load current generated by powering the device on and off may cause it to function erratically or to break down, which could in turn cause injury. Ensure that the power supply to any device which incorporates protective functions is stable. If the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly. If protective functions fail, the device may break down causing injury to the user. 2-4 3 General Safety Precautions and Usage Considerations 3. General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 3.1.1 From Incoming to Shipping Electrostatic discharge (ESD) When handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-MΩ protective resistor. Please follow the precautions described below; this is particularly important for devices which are marked “Be careful of static.”. (1) Work environment • When humidity in the working environment decreases, the human body and other insulators can easily become charged with static electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking. • Be sure that all equipment, jigs and tools in the working area are grounded to earth. • Place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is protected against static electricity and is grounded to earth. The surface resistivity should be 104 to 108 Ω/sq and the resistance between surface and ground, 7.5 × 105 to 108 Ω • Cover the workbench surface also with a conductive mat (with a surface resistivity of 104 to 108 Ω/sq, for a resistance between surface and ground of 7.5 × 105 to 108 Ω) . The purpose of this is to disperse static electricity on the surface (through resistive components) and ground it to earth. Workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly. • Pay attention to the following points when using automatic equipment in your workplace: (a) When picking up ICs with a vacuum unit, use a conductive rubber fitting on the end of the pick-up wand to protect against electrostatic charge. (b) Minimize friction on IC package surfaces. If some rubbing is unavoidable due to the device’s mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. Also, consider the use of an ionizer. (c) In sections which come into contact with device lead terminals, use a material which dissipates static electricity. (d) Ensure that no statically charged bodies (such as work clothes or the human body) touch the devices. 3-1 3 General Safety Precautions and Usage Considerations (e) Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not touch devices. (g) In processes in which packages may retain an electrostatic charge, use an ionizer to neutralize the ions. • Make sure that CRT displays in the working area are protected against static charge, for example by a VDT filter. As much as possible, avoid turning displays on and off. Doing so can cause electrostatic induction in devices. • Keep track of charged potential in the working area by taking periodic measurements. • Ensure that work chairs are protected by an anti-static textile cover and are grounded to the floor surface by a grounding chain. (Suggested resistance between the seat surface and grounding chain is 7.5 × 105 to 1012Ω.) • Install anti-static mats on storage shelf surfaces. (Suggested surface resistivity is 104 to 108 Ω/sq; suggested resistance between surface and ground is 7.5 × 105 to 108 Ω.) • For transport and temporary storage of devices, use containers (boxes, jigs or bags) that are made of anti-static materials or materials which dissipate electrostatic charge. • Make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain. • In any location where the level of static electricity is to be closely controlled, the ground resistance level should be Class 3 or above. Use different ground wires for all items of equipment which may come into physical contact with devices. (2) Operating environment • Operators must wear anti-static clothing and conductive shoes (or a leg or heel strap). • Operators must wear a wrist strap grounded to earth via a resistor of about 1 MΩ. • Soldering irons must be grounded from iron tip to earth, and must be used only at low voltages (6 V to 24 V). • If the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in particular avoid metallic tweezers. If a charged device touches a low-resistance tool, rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 104 to 108 Ω). • Do not place devices or their containers near sources of strong electrical fields (such as above a CRT). 3-2 3 General Safety Precautions and Usage Considerations • When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another. • Ensure, if possible, that any articles (such as clipboards) which are brought to any location where the level of static electricity must be closely controlled are constructed of anti-static materials. • In cases where the human body comes into direct contact with a device, be sure to wear anti-static finger covers or gloves (suggested resistance value: 108 Ω or less). • Equipment safety covers installed near devices should have resistance ratings of 109 Ω or less. • If a wrist strap cannot be used for some reason, and there is a possibility of imparting friction to devices, use an ionizer. • The transport film used in TCP products is manufactured from materials in which static charges tend to build up. When using these products, install an ionizer to prevent the film from being charged with static electricity. Also, ensure that no static electricity will be applied to the product’s copper foils by taking measures to prevent static occuring in the peripheral equipment. 3.1.2 Vibration, impact and stress Handle devices and packaging materials with care. To avoid damage to devices, do not toss or drop packages. Ensure that devices are not subjected to mechanical vibration or shock during transportation. Ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends. Vibration Plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. However, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. Therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully. If a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. In products such as CCDs which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate. Furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. In analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above. 3-3 3 General Safety Precautions and Usage Considerations 3.2 3.2.1 Storage General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. • The storage area temperature should be kept within a temperature range of 5°C to 35°C, and relative humidity should be maintained at between 45% and 75%. Humidity: Temperature: • Do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions. • Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. As a result, the solderability of the leads will be degraded. • When repacking devices, use anti-static containers. • Do not allow external forces or loads to be applied to devices while they are in storage. • If devices have been stored for more than two years, their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used. 3.2.2 Moisture-proof packing Moisture-proof packing should be handled with care. The handling procedure specified for each packing type should be followed scrupulously. If the proper procedures are not followed, the quality and reliability of devices may be degraded. This section describes general precautions for handling moisture-proof packing. Since the details may differ from device to device, refer also to the relevant individual datasheets or databook. (1) General precautions Follow the instructions printed on the device cartons regarding transportation and storage. • Do not drop or toss device packing. The laminated aluminum material in it can be rendered ineffective by rough handling. • The storage area temperature should be kept within a temperature range of 5°C to 30°C, and relative humidity should be maintained at 90% (max). Use devices within 12 months of the date marked on the package seal. 3-4 3 General Safety Precautions and Usage Considerations • If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. Please refer to the table below. After the pack has been opened, use the devices in a 5°C to 30°C. 60% RH environment and within the effective usage period listed on the moisture-proof package. If the effective usage period has expired, or if the packing has been stored in a highhumidity environment, bake the devices at high temperature. Packing Tray Tube Tape Moisture removal If the packing bears the “Heatproof” marking or indicates the maximum temperature which it can withstand, bake at 125°C for 20 hours. (Some devices require a different procedure.) Transfer devices to trays bearing the “Heatproof” marking or indicating the temperature which they can withstand, or to aluminum tubes before baking at 125°C for 20 hours. Deviced packed on tape cannot be baked and must be used within the effective usage period after unpacking, as specified on the packing. • When baking devices, protect the devices from static electricity. • Moisture indicators can detect the approximate humidity level at a standard temperature of 25°C. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators. HUMIDITY INDICATOR 60% 50% 30% DANGER IF PINK CHANGE DESICCANT 40% HUMIDITY INDICATOR 40 DANGER IF PINK 20% 30 10% READ AT LAVENDER BETWEEN PINK & BLUE (a) 6-point indicator 20 READ AT LAVENDER BETWEEN PINK & BLUE (b) 3-point indicator Figure 1 Humidity indicator 3-5 3 General Safety Precautions and Usage Considerations 3.3 Design Care must be exercised in the design of electronic equipment to achieve the desired reliability. It is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. A device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures. If the voltage or current on any pin exceeds the absolute maximum rating, the device’s internal circuitry can become degraded. In the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down. If storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed. 3.3.2 Recommended operating conditions The recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. If greater reliability is required, derate the device’s absolute maximum ratings for voltage, current, power and temperature before using it. 3.3.3 Derating When incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. Since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design. 3.3.4 Unused pins If unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. Similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the IC may malfunction or break down. Since the details regarding the handling of unused pins differ from device to device and from pin to pin, please follow the instructions given in the relevant individual datasheets or databook. 3-6 3 General Safety Precautions and Usage Considerations CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow. Therefore, ensure that the unused input pins of a device are connected to the power supply (Vcc) pin or ground (GND) pin of the same device. For details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook. 3.3.5 Latch-up Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to ground. This happens when a parasitic PN-PN junction (thyristor structure) internal to the CMOS chip is turned on, causing a large current of the order of several hundred mA or more to flow between Vcc and GND, eventually causing the device to break down. Latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. Once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between Vcc (Vdd) and GND (Vss). This causes the device to heat up and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the following precautions: (1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to fall below GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly. (2) Do not allow any abnormal noise signals to be applied to the device. (3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss). (4) Do not connect output pins to one another. 3.3.6 Input/Output protection Wired-AND configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND (Vss). Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. Therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously. 3.3.7 Load capacitance Some devices display increased delay times if the load capacitance is large. Also, large charging and discharging currents will flow in the device, causing noise. Furthermore, since outputs are shorted for a relatively long time, wiring can become fused. Consult the technical information for the device being used to determine the recommended load capacitance. 3-7 3 General Safety Precautions and Usage Considerations 3.3.8 Thermal design The failure rate of semiconductor devices is greatly increased as operating temperatures increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. Therefore, to achieve optimum reliability, observe the following precautions concerning thermal design: (1) Keep the ambient temperature (Ta) as low as possible. (2) If the device’s dynamic power dissipation is relatively large, select the most appropriate circuit board material, and consider the use of heat sinks or of forced air cooling. Such measures will help lower the thermal resistance of the package. (3) Derate the device’s absolute maximum ratings to minimize thermal stress from power dissipation. θja = θjc + θca θja = (Tj–Ta) / P θjc = (Tj–Tc) / P θca = (Tc–Ta) / P in which θja = thermal resistance between junction and surrounding air (°C/W) θjc = thermal resistance between junction and package surface, or internal thermal resistance (°C/W) θca = thermal resistance between package surface and surrounding air, or external thermal resistance (°C/W) Tj = junction temperature or chip temperature (°C) Tc = package surface temperature or case temperature (°C) Ta = ambient temperature (°C) P = power dissipation (W) Ta θca Tc θjc Tj Figure 2 Thermal resistance of package 3.3.9 Interfacing When connecting inputs and outputs between devices, make sure input voltage (VIL/VIH) and output voltage (VOL/VOH) levels are matched. Otherwise, the devices may malfunction. When connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and poweroff sequences can result in device breakdown. For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor. 3-8 3 General Safety Precautions and Usage Considerations 3.3.10 Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 Ω to 100 Ω.) For this reason, the impedance of power supply lines with respect to high frequencies must be kept low. This can be accomplished by using thick and short wiring for the Vcc (Vdd) and GND (Vss) lines and by installing decoupling capacitors (of approximately 0.01 µF to 1 µF capacitance) as high-frequency filters between Vcc (Vdd) and GND (Vss) at strategic locations on the printed circuit board. For low-frequency filtering, it is a good idea to install a 10- to 100-µF capacitor on the printed circuit board (one capacitor will suffice). If the capacitance is excessively large, however, (e.g. several thousand µF) latch-up can be a problem. Be sure to choose an appropriate capacitance value. An important point about wiring is that, in the case of high-speed logic ICs, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. Reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device’s safety margins with respect to noise. To prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (L) and capacitance (C) in the wiring. Extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. In practice, there must be a trade-off between these two factors. 3.3.11 External noise Printed circuit boards with long I/O or signal pattern lines are vulnerable to induced noise or surges from outside sources. Consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. To protect against noise, lower the impedance of the pattern line or insert a noisecanceling circuit. Protective measures must also be taken against surges. For details of the appropriate protective measures for a particular device, consult the relevant databook. Input/Output Signals 3.3.12 Electromagnetic interference Widespread use of electrical and electronic equipment in recent years has brought with it radio and TV reception problems due to electromagnetic interference. To use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products. Electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. Different measurement methods and corrective measures are used to assess and counteract each specific type of noise. Difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. For this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. Yet it is possible during system design to incorporate some measures for the prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. These include installing shields and noise filters, and increasing the thickness of the power supply wiring patterns on the printed circuit board. One effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed. 3-9 3 General Safety Precautions and Usage Considerations 3.3.13 Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be taken into account. (1) Inappropriate voltages or currents applied to a device’s input pins may cause it to operate erratically. Some devices contain pull-up or pull-down resistors. When designing your system, remember to take the effect of this on the voltage and current levels into account. (2) The output pins on a device have a predetermined external circuit drive capability. If this drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits. 3.3.14 Safety standards Each country has safety standards which must be observed. These safety standards include requirements for quality assurance systems and design of device insulation. Such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards. 3.3.15 Other precautions (1) When designing a system, be sure to incorporate fail-safe and other appropriate measures according to the intended purpose of your system. Also, be sure to debug your system under actual board-mounted conditions. (2) If a plastic-package device is placed in a strong electric field, surface leakage may occur due to the chargeup phenomenon, resulting in device malfunction. In such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield. (3) With some microcomputers and MOS memory devices, caution is required when powering on or resetting the device. To ensure that your design does not violate device specifications, consult the relevant databook for each constituent device. (4) Ensure that no conductive material or object (such as a metal pin) can drop onto and short the leads of a device mounted on a printed circuit board. 3.4 3.4.1 Inspection, Testing and Evaluation Grounding Ground all measuring instruments, jigs, tools and soldering irons to earth. Electrical leakage may cause a device to break down or may result in electric shock. 3-10 3 General Safety Precautions and Usage Considerations 3.4.2 Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user. When conducting any kind of evaluation, inspection or testing using AC power with a peak voltage of 42.4 V or DC power exceeding 60 V, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury. (1) Apply voltage to the test jig only after inserting the device securely into it. When applying or removing power, observe the relevant precautions, if any. (2) Make sure that the voltage applied to the device is off before removing the device from the test jig. Otherwise, the device may undergo performance degradation or be destroyed. (3) Make sure that no surge voltages from the measuring equipment are applied to the device. (4) The chips housed in tape carrier packages (TCPs) are bare chips and are therefore exposed. During inspection take care not to crack the chip or cause any flaws in it. Electrical contact may also cause a chip to become faulty. Therefore make sure that nothing comes into electrical contact with the chip. 3.5 Mounting There are essentially two main types of semiconductor device package: lead insertion and surface mount. During mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. With surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. This section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. Note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. Therefore, please consult the relevant technical datasheet and databook. 3.5.1 Lead forming Always wear protective glasses when cutting the leads of a device with clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes. Do not touch the tips of device leads. Because some types of device have leads with pointed tips, you may prick your finger. Semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. If undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. This is attributable primarily to differences between the stress on the device’s external leads and the stress on the internal leads. If the relative difference is great enough, the device’s internal leads, adhesive properties or sealant can be damaged. Observe these precautions during the lead-forming process (this does not apply to surface-mount devices): (1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. 3-11 3 General Safety Precautions and Usage Considerations (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For the minimum clearance specification between a device and a printed circuit board, refer to the relevant device’s datasheet and databook. If necessary, achieve the required clearance by forming the device’s leads appropriately. Do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. These spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device. (4) Observe the following precautions when forming the leads of a device prior to mounting. • Use a tool or jig to secure the lead at its base (where the lead meets the device package) while bending so as to avoid mechanical stress to the device. Also avoid bending or stretching device leads repeatedly. • Be careful not to damage the lead during lead forming. • Follow any other precautions described in the individual datasheets and databooks for each device and package type. 3.5.2 Socket mounting (1) When socket mounting devices on a printed circuit board, use sockets which match the inserted device’s package. (2) Use sockets whose contacts have the appropriate contact pressure. If the contact pressure is insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket. (3) When soldering sockets to the printed circuit board, use sockets whose construction prevents flux from penetrating into the contacts or which allows flux to be completely cleaned off. (4) Make sure the coating agent applied to the printed circuit board for moisture-proofing purposes does not stick to the socket contacts. (5) If the device leads are severely bent by a socket as it is inserted or removed and you wish to repair the leads so as to continue using the device, make sure that this lead correction is only performed once. Do not use devices whose leads have been corrected more than once. (6) If the printed circuit board with the devices mounted on it will be subjected to vibration from external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another. 3-12 3 General Safety Precautions and Usage Considerations 3.5.3 Soldering temperature profile The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used. (1) Using medium infrared ray reflow • Heating top and bottom with long or medium infrared rays is recommended (see Figure 3). Medium infrared ray heater (reflow) Product flow Long infrared ray heater (preheating) Figure 3 Heating top and bottom with long or medium infrared rays • Complete the infrared ray reflow process for 30 to 50 seconds at a package surface temperature of between 230°C and 260°C. • Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow. (°C) 260 Package surface temperature 230 190 180 60-120 s 30-50 s Time (s) Figure 4 Sample temperature profile (Pb free) for infrared or hot air reflow (2) Using hot air reflow • Complete hot air reflow for 30 to 50 seconds at a package surface temperature of between 230°C and 260°C. • For an example of a recommended temperature profile, refer to Figure 4 above. 3.5.4 Flux cleaning and ultrasonic cleaning (1) When cleaning circuit boards to remove flux, make sure that no residual reactive ions such as Na or Cl remain. Note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance. (2) Washing devices with water will not cause any problems. However, make sure that no reactive ions such as sodium and chlorine are left as a residue. Also, be sure to dry devices sufficiently after washing. 3-13 3 General Safety Precautions and Usage Considerations (3) Do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. Doing so can rub off the markings. (4) The dip cleaning, shower cleaning and steam cleaning processes all involve the chemical action of a solvent. Use only recommended solvents for these cleaning methods. When immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50°C or below, and that the circuit board is removed from the bath within one minute. (5) Ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a leadless chip carrier (LCC), pin grid array (PGA) or charge-coupled device (CCD), because the bonding wires can become disconnected due to resonance during the cleaning process. Even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. The following ultrasonic cleaning conditions are recommended: Frequency: 27 kHz ∼ 29 kHz Ultrasonic output power: 300 W or less (0.25 W/cm2 or less) Cleaning time: 30 seconds or less Suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device. 3.5.5 No cleaning If analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. Similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause between-lead leakage or migration. Therefore, Toshiba recommends that these devices be cleaned. However, if the flux used contains only a small amount of halogen (0.05W% or less), the devices may be used without cleaning without any problems. No cleaning is recommended for TX4938. 3.5.6 Mounting tape carrier packages (TCPs) (1) When tape carrier packages (TCPs) are mounted, measures must be taken to prevent electrostatic breakdown of the devices. (2) If devices are being picked up from tape, or outer lead bonding (OLB) mounting is being carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards. (3) The base film, which is made of polyimide, is hard and thin. Be careful not to cut or scratch your hands or any objects while handling the tape. (4) When punching tape, try not to scatter broken pieces of tape too much. (5) Treat the extra film, reels and spacers left after punching as industrial waste, taking care not to destroy or pollute the environment. (6) Chips housed in tape carrier packages (TCPs) are bare chips and therefore have their reverse side exposed. To ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand. 3-14 3 General Safety Precautions and Usage Considerations 3.5.7 Mounting chips Devices delivered in chip form tend to degrade or break under external forces much more easily than plasticpackaged devices. Therefore, caution is required when handling this type of device. (1) Mount devices in a properly prepared environment so that chip surfaces will not be exposed to polluted ambient air or other polluted substances. (2) When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). (3) Make sure that PCBs (or any other kind of circuit board) on which chips are being mounted do not have any chemical residues on them (such as the chemicals which were used for etching the PCBs). (4) When mounting chips on a board, use the method of assembly that is most suitable for maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used. * For details of devices in chip form, refer to the relevant device’s individual datasheets. 3.5.8 Circuit board coating When devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. However, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device. 3.5.9 Heat sinks (1) When attaching a heat sink to a device, be careful not to apply excessive force to the device in the process. (2) When attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). Finally, fully tighten all the screws up to the specified torque. (3) Drill holes for screws in the heat sink exactly as specified. Smooth the surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device. (4) A coating of silicone compound can be applied between the heat sink and the device to improve heat conductivity. Be sure to apply the coating thinly and evenly; do not use too much. Also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate. (5) If the device is housed in a plastic package, use caution when selecting the type of silicone compound to be applied between the heat sink and the device. With some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone. (6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you may sustain a burn. 3-15 3 General Safety Precautions and Usage Considerations 3.5.10 Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch devices. 3.5.11 Repeated device mounting and usage Do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability. (1) Devices which have been removed from the board after soldering (2) Devices which have been inserted in the wrong orientation or which have had reverse current applied (3) Devices which have undergone lead forming more than once 3.6 3.6.1 Protecting Devices in the Field Temperature Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. It is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. Note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected. 3.6.2 Humidity Resin-molded devices are sometimes improperly sealed. When these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. Furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under high-humidity conditions. In systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. The application of a moisture-proof treatment to the device surface should be considered in this case. On the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. Unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%). 3.6.3 Corrosive gases Corrosive gases can cause chemical reactions in devices, degrading device characteristics. For example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device’s leads. The resulting chemical reaction between leads forms foreign particles which can cause electrical leakage. 3.6.4 Radioactive and cosmic rays Most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. Devices used in aerospace equipment or in radioactive environments must therefore be shielded. 3-16 3 General Safety Precautions and Usage Considerations 3.6.5 Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures have been reported in LSIs mounted near malfunctioning deflection yokes in TV sets. In such cases the device’s installation location must be changed or the device must be shielded against the electrical or magnetic field. Shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment. 3.6.6 Interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the internal chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. This problem is not limited to optical semiconductors and EPROMs. All types of device can be affected by light. 3.6.7 Dust and oil Just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device’s electrical characteristics. To avoid this problem, do not use devices in dusty or oily environments. This is especially important for optical devices because dust and oil can affect a device’s optical characteristics as well as its physical integrity and the electrical performance factors mentioned above. 3.6.8 Fire Semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. When this happens, some devices may generate poisonous gases. Devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials. 3.7 Disposal of Devices and Packing Materials When discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination. 3-17 3 General Safety Precautions and Usage Considerations 3-18 4 Precautions and Usage Considerations 4. Precautions and Usage Considerations This section describes matters specific to each product group which need to be taken into consideration when using devices. If the same item is described in Sections 3 and 4, the description in Section 4 takes precedence. 4.1 4.1.1 Microcontrollers Design (1) Using resonators which are not specifically recommended for use Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application. (2) Undefined functions In some microcontrollers certain instruction code values do not constitute valid processor instructions. Also, it is possible that the values of bits in registers will become undefined. Take care in your applications not to use invalid instructions or to let register bit values become undefined. 4-1 4 Precautions and Usage Considerations 4-2 TMPR4938 2005-3 Rev 2.0 Conventions in this Manual Conventions in this Manual Value Conventions • • Hexadecimal values are expressed as in the following example. (This value is expressed as 42 in the decimal system.) KB (kilobyte) = 1,024 Bytes, MB (megabyte) = 1,024 × 1,024 = 1,048,576 Bytes, GB (gigabyte) = 1,024 × 1,024 × 1,024 = 1,073,741,824 Bytes Data Conventions • • • • Byte: 8 bits Half-word: 2 consecutive Bytes (16 bits) Word: 4 consecutive Bytes (32 bits) Double-word: 8 consecutive Bytes (64 bits) Signal Conventions • • An asterisk (“*”) is added to the end of signal names to indicate Low Active signals. (Example: RESET*) “Assert” means to move a signal to its Active level. “Deassert” means to move a signal to its Inactive level. Register Conventions • Bit operation is expressed as follows. Set: Put a bit in the “1” position. Clear: Put a bit in the “0” position. Properties of each bit in a register are expressed as follows. R: Read only. The software cannot change the bit value. W: Write only. The value that is read is undefined. R/W: Read/Write is possible. W1C Write 1 Clear. This corresponding bit is cleared when “1” is written to this bit. “0” is invalid if written. R/W1C: Read/Write 1 Clear. These bits can be read from and written to. The corresponding bit is cleared when “1” is written to this bit. “0” is invalid if written. R/W0C: Read/Write 0 Clear. These bits can be read from and written to. The corresponding bit is cleared when “0” is written to this bit. “1” is invalid if written. R/W1S Read/Write 1 Set. These bits can be read from and written to. The corresponding bit is set when “1” is written to this bit. “0” is invalid if written. RS/WC Read Set/Write Clear. These bits can be read from and written to. The bits is set when read, and a write of an arbitrary value to the bit clears it. R/L: Property unique to the PCI Controller. This bit can be read. The value of this bit can only be changed by the method described in “10.3.14: Set Configuration Space”. Registers and the register bit/field name are expressed as “.”. Example: CCFG.TOE The above example indicates Time Out Bus Error Enable (TOE), a bit field of bit 14 in the Chip Configuration Register (CCFG). • • i Conventions in this Manual Handling reserved regions Operation is undefined when a register defined in this document as a reserved region (Reserved) is accessed. If there is a bit or field that was defined as Reserved in a register, write the expressed default value or the specified value (“0” if no particular value is expressed) to these bits. Also, do not use any value read from this bit/field. Diagnostic function Any function described as a “diagnostic function” is used to facilitate operation evaluations. The operation of such functions is not guaranteed. References 64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture (http://www.semicon.toshiba.co.jp/eng/index.html) MIPS RISC Architecture, Gerry Kane and Joe Heinrich (ISBN 0-13-590472-2) See MIPS Run, Dominic Sweetman (ISBN 1-55860-410-3) MIPS Publications (http://www.mips.com/publications/) PCI Local Bus Specification Revision 2.2 (http://www.pcisig.com/) PCI Bus Power Management Interface Specification Revision 1.1 Audio CODEC ‘97 (AC ‘97) Revision 2.1 (http://developer.intel.com/ial/scalableplatforms/audio/) – SmartMedia™ Physical Format Specifications Web-Online Version 1.00 – SMIL (SmartMedia™ Interface Library) Software Edition Version 1.00 (http://www.ssfdc.or.jp/english/business/) ii Chapter 1 Overview and Features 1. 1.1 Overview and Features Overview The TMPR4938 (TX4938) is a standard microcontroller that belongs to the 64-bit TX System RISC TX49 family. The TX4938 uses the TX49/H3 core as its CPU. The TX49/H3 core is a 64-bit RISC core that Toshiba developed based on the MIPS III architecture of MIPS Technologies, Inc. (MIPS). For details of the TX49/H3 core such as instruction sets, see “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture”. In addition to the TX49/H3 core, the TX4938 uses as microcontrollers for embedded applications an External Bus Controller, DMA Controllers, SDRAM Controller, PCI Controller, Ethernet Controller and NAND Flash Memory Controller (enables booting from NAND flash memory). The TX4938 also has peripheral circuits such as a synchronous serial interface, on-chip SRAM, a serial I/O port, a timer/counter, a parallel I/O port, an AC-link Controller and an Interrupt Controller. By having an on-chip a data bus with a maximum width of 64 bits and an SDRAM Controller with a memory clock frequency of 133 MHz, the TX4938 realizes low memory access latency and high memory bandwidth. This allows the TX4938 to show its capacity as a high-performance CPU core. 1.2 Features • TX49/H3 core Maximum Operating Frequency: 300 MHz (TMPR4938XBG-300), 333 MHz (TMPR4938XBG-333) On-chip IEEE754-compliant single/double precision floating point unit (FPU) function External Bus Controller (8 channels) Supports the ISA/ATA interface DMA (Direct Memory Access) Controllers (8 channels) SDRAM Controller (4 channels) 64-bit Data Bus Memory Clock Frequency: 133 MHz (For relationship between CPU clock and memory clock, see Section 6.1) Supports ECC/Parity PCI Controller Complies with PCI Local Bus Specification Revision 2.2 PCI Bus Clock Frequency: 66 MHz/33 MHz Ethernet Controller (2 channels) NAND Flash Memory Controller (bootable) Serial Peripheral Interface (SPI) On-chip SRAM (2 K-byte) Serial I/O Port (2 channels) Timer/Counter (3 channels) Parallel I/O Port (Maximum 16 bits) AC-link Controller Interrupt Controller Selectable Little Endian mode or Big Endian mode • • • • • • • • • • • • • • • 1-1 Chapter 1 Overview and Features • • • Low Power Consumption Supports internal 1.5 V, IO block 3.3 V operation, and low power consumption mode (Halt) Supports IEEE1149.1 (JTAG): Debugging Support Unit (EJTAG) Package: 484-pin PBGA (with 64pin thermal ball) 1.2.1 Features of the TX49/H3 core The TX49/H3 core is a high-performance, low power consumption 64-bit RISC CPU core that Toshiba developed. • • • • • 64-bit operation 32 64-bit integer general-purpose registers 64 GB physical address space Optimized 5-stage pipeline Instruction Set Upwards compatible MIPS III ISA Added 3-operand multiply instruction, MAC (multiply accumulate) instruction, and PREF (prefetch) instruction Supports 32 KB Instruction cache, 32 KB Data cache, 4-way set associative, and the lock function MMU (Memory Management Unit) 48 double entry (odd/even) joint TLB On-chip IEEE754-compatible single-precision and double-precision FPU 4-stage write buffer mounted Debugging Support Unit: EJTAG • • • • • 1.2.2 Features of TX4938 peripheral functions (1) External Bus Controller (EBUSC) The External Bus Controller generates the signals necessary to control external memory and external I/O devices. • • • • • • Has 8-channel Chip Select signal, can control up to 8 external devices Supports access of ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, Flash ROM, and I/O devices Can set data bus width to 32 bits, 16 bits, or 8 bits for each channel System clock for External Bus Controller (SYSCLK) frequency is up to 133 MHz (For relationship between CPU clock and this system clock, see Section 6.1) Can select full speed, 1/2 speed, 1/3 speed , or 1/4 speed for each channel Can set timing for each channel Can set up and set the Hold interval of the Address, Chip Enable, Write Enable, and Output Enable signals Supports access of devices with a 32-bit wide data bus in memory sizes from 1 MB to 1 GB. Supports access of devices with a 16-bit wide data bus in memory sizes from 1 MB to 512 MB. Supports access of devices with an 8-bit wide data bus in memory sizes from 1 MB to 256 MB. Supports the ISA/ATA interface • • 1-2 Chapter 1 Overview and Features (2) Direct Memory Access Controllers (DMAC) The TX4938 has two DMA Controllers for invoking DMA transfer with memory and I/O devices. Each DMA Controller has 4 built-in DMA Channels. • • • • • • • Can set internal/external DMA requests Supports as internal DMA requests DMA with the on-chip Serial I/O Controller or AC-link Controller Supports as external I/O DMA transfer modes using external DMA requests Single Address transfer (Fly-by DMA) and Dual Address transfer Supports transfer between external devices with a data bus width of 32 bits, 16 bits or 8 bits and memory Supports memory-memory copy mode that has no address boundary constraints Can perform Burst transfer of up to 8 double words in a single read or write operation Supports the Memory Fill mode that writes double-word data to the memory region Supports Chain DMA transfer (3) SDRAM Controller (SDRAMC) The SDRAM Controller generates the control signals required for the SDRAM interface. By having 4 on-chip channels and supporting a variety of memory configurations, the SDRAM Controller can support memory sizes of up to 4 GB (1 GB/channel). • • • • • • • • • Memory clock (SDCLK) frequencies from 50 MHz to 133 MHz (For relationship between CPU clock and memory clock, see Section 6.1) 4 sets of independent memory channels Supports 2-bank or 4-bank 16 MB, 64 MB, 128 MB, 256 MB, or 512 MB SDRAM Can used Registered DIMM Supports ECC or parity generation/check functions Can select either 32-bit or 64-bit data bus width for each channel Can set SDRAM timing for each channel Supports TX49/H3 core critical word first access Low power consumption mode: can select Self-refresh or Pre-charge power down (4) PCI Controller (PCIC) The TX4938 has an on-chip PCI Controller that is compliant with PCI Local Bus Specification Revision 2.2. • • • • • • • PCI Local Bus Specification Revision 2.2 compliant 32-bit PCI interface with maximum PCI Bus clock frequency of 66 MHz Supports both the Target and Initiator functions Can change the address mapping between the internal bus and PCI Bus Has an on-chip PCI Bus arbiter and can connect up to 4 External Bus Masters Has a function mounted for booting the TX4938 from memory on the PCI Bus Has an on-chip 1-channel PCI Controller-dedicated DMA Controller (PDMAC) 1-3 Chapter 1 Overview and Features (5) Serial I/O port (SIO) The TX4938 has an on-chip 2-channel asynchronous serial I/O interface (full duplex UART) • • • Full duplex UART × 2 channels On-chip baud rate generator FIFO Transmission: on-chip 8-bit × 8-stage FIFO Reception: on-chip 13-bit × 16-stage (data: 8 bits; status: 5 bits) FIFO Supports DMA transfer • (6) Timer/Counter control (TMR) The TX4938 has an on-chip 3-channel timer/counter • • • • • 32-bit setup counter × 3 channels Supports 3 modes: Interval Timer mode, Pulse Generator mode, Watchdog Timer mode Timer output pins: 2 pins Count clock input pin: 1 pin Watchdog external reset pin: 1 pin (7) Parallel I/O port (PIO) The TX4938 has a 16-bit parallel I/O port (8 bits of which are shared with CB[7:0]) • Can set I/O direction and port type (totem pole output/open drain output) during output for each bit (8) AC-link Controller (ACLC) The TX4938 on-chip AC-link Controller can connect and manipulate audio and/or modem CODECs described in “Audio CODEC ’97 Revision 2.1”. • • • • • • Supports up to 2 CODECs Supports 16-bit PCM stereo channel recording and playback Supports 16-bit surround, center, LFE channel playback Supports variable rate audio recording and playback Supports Line 1 for modem CODEC and GPIO slot Supports AC-link low-power mode, Wake Up, and Warm Reset Supports sample data input/output by DMA transfer (9) Interrupt Controller (IRC) The Interrupt Controller built into the TX4938 receives interrupt requests and external interrupts from the TX4938 on-chip peripheral circuits and issues interrupt requests to the TX49/H3 core. This controller has a 16-bit flag register that generates interrupt requests to an external device or the TX49/H3 core. • • Supports 19 types of internal interrupts from the on-chip peripheral circuits and 6 external interrupt signal inputs Sets 8 priority levels for each interrupt input 1-4 Chapter 1 Overview and Features • • Can select either the Edge or Level interrupt detection mode for each external interrupt Has a built-in 16-bit read/write register as a flag register for interrupt requests. Can request interrupts to an external device or to the TX49/H3 core (IRC interrupt) (10) Ethernet Controller • • • • 2-channel on-chip Ethernet interface Supports transfer rates of 100 Mbps or 10 Mbps Supports MAC layers, employs the standard interface MII between physical layers and MAC layers On-chip DMA (11) NAND Flash Memory Controller • • • Controls the NAND Flash Memory Interface by the register settings On-chip ECC (Error Correction Code) calculation circuit On-chip mask ROM, is bootable from NAND Flash Memory (12) Serial Peripheral Interface (SPI) • • • • Full duplex, synchronous serial data transfer (I/O data, clock signals) Can specify 8-bit or 16-bit data length Programmable SPI baud rate Supports only Masters (13) On-chip SRAM • On-chip 2 KB SRAM (14) Extended EJTAGInterface The TX4938's Extended EJTAG (Extended Enhanced Joint Test Action Group) interface provides two functions: IEEE1149.1-compliant JTAG boundary scan testing and real-time debugging using the Debugging Support Unit (DSU) built into the TX49/H3 core. • • IEEE 1149.1 JTAG Boundary Scan Can use execution control (invoke, break, step, register/memory access) or PC tracing as realtime debugging function that uses a dedicated emulation probe 1-5 Chapter 1 Overview and Features 1-6 Chapter 2 Configuration 2. 2.1 Configuration TX4938 block diagram Figure 2.1.1 is an internal block diagram of the TX4938. TX49/H3 Core I-Cache D-Cache FPU HALTDOZE TEST[4:0]* W BU G-Bus I/F DSU CPU core TDI TCK TDO TMS TRST* DCLK PCST[8:0] TPC[3:1] RESET* CB[7:0] SDCLK[3:0] SDCLKIN RAS* CAS* DQM[7:0] SDCS[3:0]* WE* CKE DATA[63:0] ADDR[19:0] ACK*/READY SYSCLK IOR*, IOW * CS*[1;0] ND_CLE, ND_ALE, ND_CE*, ND_RE*, ND_WE*, ND_RB* SWE* OE* CE[7:0] * ACE* BWE[3:0] * BUSSPRT* DMAREQ[3:0] DMAACK[3:0] DMADONE* E0TXD[3:0] (O) E0RXD[3:0] (I) E0RXER (I), E0RXCLK (I) E0MDC (O) E0RXDV (I) E0TXER (O) E0TXCLK (I) E0MDIO (I/O) E0TXEN (O) E0CRS (I) E0COL(I) E1TXD[3:0] (O) E1RXD[3:0] (I) E1RXER (I), E1RXCLK (I) E1MDC (O) E1RXDV (I) E1TXER (O) E1TXCLK (I) E1MDIO (I/O) E1TXEN (O) E1CRS (I) .E1COL(I) NMI* INT[5:0] INTOUT PIO[15:0] CTS[1:0]* RTS[1:0]* RXD[1:0] TXD[1:0] SCLK TEST ECC BYPASSPLL* CGRESET* MASTERCLK PCIAD[31:0] C_BE[3:0] PAR FRAME* IRDY* TRDY* STOP* ID_SEL DEVSEL* REQ[3:0]* GNT[3:0]* PERR* SERR* LOCK* M66EN PME* EEPROM_DO EEPROM_DI EEPROM_CS EEPROM_SK PCICLK[5:0] PCICLKIN ACRESET* SYNC SDOUT SDIN[1:0] BITCLK SPIIN SPIOUT SPICLK WDRST* TIMER[1] TCLK TIMER[0] PLL CG SDRAMC (4 channels) G-Bus SRAM (2kbx1) Mask ROM EBIF PCIC NDFMC EBUSC (8 channels) PDMAC DMAC0 (4 channels) DMAC1 (4 channels) PCIC1 ACLC IMB ETHER C0 Internal PCI bus ETHER C1 SPI TMR2 TMR1 TMR0 IM Bus IRC PIO SIO (2ch.) Figure 2.1.1 TX4938 Block Diagram 2-1 Chapter 2 Configuration The TX4938 has the following blocks. (1) TX49/H3 Core: Consists of a CPU, System Control Coprocessor (CP0), Instruction cache, Data cache, Floating-point Unit (FPU), write buffer (WBU), Debugging Support Unit (DSU), and a G-Bus I/F. • • • • FPU: An IEEE754-compliant single-precision or double-precision floating-point unit. Is allocated as one coprocessor unit (CP1). I-Cache: Instruction cache memory. 32 KB, 4-way set associative. D-Cache: Data cache memory. 32 KB, 4-way set associative. You can select as a write policy Write Back, Write Through No Write Allocate, or Write Through Write Allocate. DSU: Debugging Support Unit. This is an on-chip debugging module. External Bus Controller. Controls 8-channel ROM, SRAM, I/O. Direct Memory Access Controller. Has 4 channels. Can transfer internal I/O device, external I/O device, mutual memory data. Direct Memory Access Controller. Has 4 channels. Can transfer internal I/O device, mutual memory data. SDRAM Controller. Controls 4-channel SDRAM. Supports 64-bit data bus, 133 MHz operation, ECC/parity. PCI Controller. Complies with PCI Local Bus Specification Revision 2.2. Supports 66 MHz operation. Has an on-chip dedicated DMA Controller (PDMAC). Serial I/O. This is a 2-channel asynchronous serial I/F. Timer/counter. This is a 3-channel timer/counter. Parallel I/O. Has an 8-bit dedicated port and an 8-bit shared port. AC-link Controller. Is compliant to Audio CODEC '97 Revision 2.1 (AC'97). Interrupt Controller. External Bus Interface. Connects 20-bit External Address Bus or 64-bit External Data Bus to SDRAMC or EBUSC. Clock Generator. Has a built-in PLL and provides a clock to each TX4938 block. TX4938 internal bus. This is a 64-bit, high-speed internal bus that is directly connected to the TX49/H3 core. TX4938 internal bus. This is a 32-bit, slow-speed internal bus that is connected to the GBus via IMB. G-Bus - IM-Bus Bridge NAND Flash Memory Controller 2 KB on-chip SRAM Channel 0 of the Ethernet Controller. The system side is the PCI Bus Interface. Channel 1 of the Ethernet Controller. The system side is the PCI Bus Interface. PCI Bus/G-Bus bridge for connecting ETHERC0 and ETHERC1 to the G-Bus. Serial Peripheral Interface. Supports Master operation. This is the internal diagnostic module. (2) EBUSC: (3) DMAC0: (4) DMAC1: (5) SDRAMC: (6) PCIC: (7) SIO: (8) TMR: (9) PIO: (10) ACLC: (11) IRC: (12) EBIF: (13) CG: (14) G-Bus: (15) IM-Bus: (16) MB: (17) NDFMC: (19) SRAM: (20) ETHERC0: (21) ETHERC1: (22) PCIC1: (23) SPI: (24) TEST (18) Mask ROM: Mask ROM that boots from NAND Flash memory 2-2 Chapter 3 Signals 3. 3.1 Signals Pin Signal Description In the following tables, asterisks at the end of signal names indicate active-low signals. In the Type column, PU indicates that the pin is equipped with an internal pull-up resister and PD indicates that the pin is equipped with an internal pull-down resister. OD indicates an open-drain pin. The Initial State column shows the state of the signal when the RESET* signal is asserted and immediately after it is deasserted. Those signals which are selected by a configuration signal upon a reset have the state selected by the configuration signal even when the reset signal is asserted. 3.1.1 Signals Common to SDRAM and External Bus Interfaces Table 3.1.1 Signals Common to SDRAM and External Bus Interfaces Signal Name ADDR[19:0] Type Description Initial State Input Input/output Address PU Address signals. For SDRAM, ADDR[19:5] are used (refer to Sections “9.3.2.2” and “9.3.2.3 Address Signal Mapping”). When the external bus controller uses these pins, the meaning of each bit varies with the data bus width (refer to Section “7.3.5 Data Bus Size”). The ADDR signals are also used as boot configuration signals (input) during a reset. For details of configuration signals, refer to Section “3.2 Boot Configuration”. The ADDR signals are input signals only when the RESET* signal is asserted and become output signals after the RESET* signal is deasserted. Input/output PU Input Data 64-bit data bus. The DATA[15:0] signals are also used as boot configuration signals (input) during a reset. For details of configuration signals, refer to Section “3.2 Boot Configuration”. Bus Separate Controls the connection and separation of devices controlled by the external bus controller to or from a high-speed device, such as SDRAM (refer to Section “7.6 Flash ROM, SRAM Usage Example”). H: Separate devices other than SDRAM from the data bus. L: Connect devices other than SDRAM to the data bus. Separation and connection are performed using external bidirectional bus buffers (such as the 74xx245). High DATA[63:0] BUSSPRT* Output 3-1 Chapter 3 Signals 3.1.2 SDRAM Interface Signals Table 3.1.2 SDRAM Interface Signals Signal Name SDCLK[3:0] Type Output Description SDRAM Controller Clock Clock signals used by SDRAM. The clock frequency is the same as the G-Bus clock (GBUSCLK) frequency. When these clock signals are not used, the pins can be set to H using the SDCLK Enable field of the configuration register (CCFG.SDCLKEN[3:0]). Initial State All High SDCLKIN Input/output SDRAM Feedback Clock input Feedback clock signal for SDRAM controller input signals. Setting the SDCLKINEN bit of the pin configuration register causes the TX4938 to feed back signals internally, making SDCLKIN an output signal. Output Output Output Output Output Output Clock Enable CKE signal for SDRAM. Synchronous Memory Device Chip Select Chip select signals for SDRAM. Row Address Strobe RAS signal for SDRAM. Column Address Strobe CAS signal for SDRAM. Write Enable WR signal for SDRAM. Data Mask During a write cycle, the DQM signals function as a data mask. During a read cycle, they control the SDRAM output buffers. The bits correspond to the following data bus signals: DQM[7]:DATA[63:54], DQM[6]:DATA[53:48] DQM[5]:DATA[47:40], DQM[4]:DATA[39:32] DQM[3]:DATA[31:24], DQM[2]:DATA[23:16] DQM[1]:DATA[15:8], DQM[0]:DATA[7:0] Connect any one of the DQM[3:0] to SDRAM which connects CB. Input CKE SDCS[3:0]* RAS* CAS* W E* DQM[7:0] High All High High High High All High CB[7:0] Input/output ECC/Parity Check Bit PU ECC/parity check bit signals. The bits correspond to the following data bus signals: CB[7]:DATA[63:54], CB[6]:DATA[53:48] CB[5]:DATA[47:40], CB[4]:DATA[39:32] CB[3]:DATA[31:24], CB[2]:DATA[23:16] CB[1]:DATA[15:8], CB[0]:DATA[7:0] CB[7:0] share pins with other function signals (refer to Section “3.3 Pin multiplex”). Input 3-2 Chapter 3 Signals 3.1.3 External Interface Signals Table 3.1.3 External Interface Signals Signal Name SYSCLK Type Output Description Initial State High System Clock Clock for external I/O devices. Outputs a clock in full speed mode (at the same frequency as the G-Bus clock (GBUSCLK) frequency), half speed mode (at one half the GBUSCLK frequency), third speed mode (at one third the GBUSCLK frequency), or quarter speed mode (at one quarter the GBUSCLK frequency). The boot configuration signals on the ADDR[14:13] pins select which speed mode will be used. When this clock signal is not used, the pin can be set to H using the SYSCLK Enable bit of the configuration register (CCFG.SYSCLKEN). Address Clock Enable Latch enable signal for the high-order address bits of ADDR. Chip Enable Chip select signals for ROM, SRAM, and I/O devices (refer to Section “3.3 Pin multiplex”). Output Enable Output enable signal for ROM, SRAM, and I/O devices. Write Enable Write enable signal for SRAM and I/O devices. Byte Enable/Byte Write Enable BE[3:0]* indicate a valid data position on the data bus DATA[31:0] during read and write bus operation. In 16-bit bus mode, only BE[1:0]* are used. In 8-bit bus mode, only BE[0]* is used. BWE[3:0]* indicate a valid data position on the data bus DATA[31:0] during write bus operation. In 16-bit bus mode, only BWE[1:0]* are used. In 8-bit bus mode, only BWE[0]* is used. The following shows the correspondence between BE[3:0]*/BWE[3:0]* and the data bus signals. BE[3]*/BWE[3]*: DATA[31:24] BE[2]*/BWE[2]*: DATA[23:16] BE[1]*/BWE[1]*: DATA[15:8] BE[0]*/BWE[0]*: DATA[7:0] The boot configuration signal on the DATA[5] pin and the EBCCRn.BC bit of the external bus controller determine whether the signals are used as BE[3:0]* or BWE[3:0]*. Data Acknowledge/Ready Flow control signal (refer to Section “7.3.6 Access Modes”). High All High ACE* CE[7:0]* Output Output OE * SWE* BWE[3:0]* /BE[3:0]* Output Output Output High High All High ACK*/ READY Input/output PU High 3-3 Chapter 3 Signals 3.1.4 DMA Interface Signals Table 3.1.4 DMA Interface Signals Signal Name DMAREQ[3:0] Type Input PU Description Input DMA Request DMA transfer request signals from an external I/O device. The DMAREQ[3:1] signal shares the pin with the other function signal (refer to Section “3.3 Pin multiplex”). Initial State DMAACK[3:0] Output All High DMA Acknowledge DMA transfer acknowledge signals to an external I/O device. The DMAACK[3:1] signal shares the other function signal (refer to Section “3.3 Pin multiplex”). Input DMADONE* Input/output DMA Done DMADONE* is either used as an output signal that reports the termination of PU DMA transfer or as an input signal that causes DMA transfer to terminate. 3.1.5 PCI Interface Signals Table 3.1.5 PCI Interface Signals (1/2) Signal Name PCICLK[5:0] Type Output Description PCI Clock PCI bus clock signals. When these clock signals are not used, the pins can be set to H using the PCICLK Enable field of the pin configuration register (PCFG.PCICLKEN[5:0]). PCI Feedback Clock PCI feedback clock input. Initial State All High PCICLKIN PCIAD[31:0] C_BE[3:0] PAR FRAME* IRDY* TRDY* STOP* LOCK* Input Input Input Input Input Input Input Input Input Input Input/output PCI Address and Data Multiplexed address and data bus. Input/output Command and Byte Enable Command and byte enable signals. Input/output Parity Even parity signal for PCIAD[31:0] and C_BE[3:0]*. Input/output Cycle Frame Indicates that bus operation is in progress. Input/output Initiator Ready Indicates that the initiator is ready to complete data transfer. Input/output Target Ready Indicates that the target is ready to complete data transfer. Input/output Stop The target sends this signal to the initiator to request termination of data transfer. Input Lock Indicates that the PCI bus master is locking (exclusively accessing) a specified memory target on the PCI bus. Initialization Device Select Chip select signal used for configuration access. This pin is not used in host mode. When the PCI Controller is configured in host mode, this pin must be pulled down. ID_SEL Input Input DEVSEL* Input/output Device Select The target asserts this signal in response to access from the initiator. Input 3-4 Chapter 3 Signals Table 3.1.5 PCI Interface Signals (2/2) Signal Name REQ[3:2]* Type Input Description Initial State Input Request Signals used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, REQ[3:2]* are PCI bus request input signals. In external arbiter mode, REQ[3:2]* are not used. Because the pins are still placed in the input state, they must be pulled up externally. Selected by DATA[2] H: Input L: Hi-Z REQ[1]* /INTOUT Input/output/ Request OD Signal used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, this signal is a PCI bus request input signal. In external arbiter mode, this signal is an external interrupt output signal (INTOUT). Refer to Section “15.3.7 Interrupt Requests”. Input/output Request Signal used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, this signal is a PCI bus request input signal. In external arbiter mode, this signal is a PCI bus request output signal. Input/output Grant Indicates that bus mastership has been granted to the PCI bus master. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal arbiter mode, all of GNT[3:0]* are PCI bus grant output signals. In external arbiter mode, GNT[0]* is a PCI bus grant input signal. Because GNT[3:1]* also become input signals, they must be pulled up externally. Input/output Data Parity Error Indicates a data parity error in a bus cycle other than special cycles. Input/OD REQ[0]* Selected by DATA[2] H: Input L: High Selected by DATA[2] H: All High L: Input GNT[3:0]* PERR* SERR* Input Input System Error Indicates an address parity error, a data parity error in a special cycle, or a fatal error. In host mode, SERR* is an input signal. In satellite mode, SERR* is an open-drain output signal. The mode is determined by the boot configuration signal on the ADDR[19] pin. Selected by ADDR[19] H: Low L: Input M66EN Input/output PCI Bus 66 MHz Clock Enable 1: Enable 66 MHz operating mode. 0: Disable 66 MHz operating mode. This pin is configured as input in satellite mode and as output in host mode. The mode is selected through the logic level of the ADDR[19] pin at boot time. This pin must be pulled down when the PCI Controller is configured in satellite mode and when the 66-MHz operating mode is disabled. Input/OD Power Management Event PME* indicates the power management mode. In host mode, PME* is an input signal. In satellite mode, PME* is an open-drain output signal. The mode is determined by the boot configuration signal on the ADDR[19] pin. EEPROM Data In Data input from serial EEPROM for initially setting the PCI configuration. EEPROM Data Out Data output to serial EEPROM for initially setting the PCI configuration. EEPROM Chip Select Chip select for serial EEPROM for initially setting the PCI configuration. EEPROM Serial Clock Clock for serial EEPROM for initially setting the PCI configuration. PME* Selected by ADDR[19] H: Input L: Hi-Z Input Low Low Low EEPROM_DI EEPROM_DO EEPROM_CS EEPROM_SK Input PU Output Output Output Note: The PCI bus specification specifies that the following pins require pullups: FRAME*, IRDY*, TRDY*, STOP*, LOCK*, DEVSEL*, PERR*, SERR* and PME*. If these pins are unused, pullups must be provided externally to the TX4938. 3-5 Chapter 3 Signals 3.1.6 Serial I/O Interface Signals Table 3.1.6 Serial I/O Interface Signals Signal Name CTS [1:0]* Type Input PU Output Description SIO Clear to Send CTS* signals. CTS[1]* share pins with other function signals (refer to Section “3.3 Pin multiplex”). SIO Request to Send RTS* signals. RTS[1]* share pins with other function signals (refer to Section “3.3 Pin multiplex”). SIO Receive Data Serial data input signals. RXD[1] share pins with other function signals (refer to Section “3.3 Pin multiplex”). SIO Transmit Data Serial data output signals. TXD[1] share pins with other function signals (refer to Section “3.3 Pin multiplex”). External Serial Clock SIO clock input signal. SIO0 and SIO1 share this signal. Initial State Input RTS [1:0]* All Low RXD[1:0] Input PU 3-state Output Input PU Input TXD[1:0] All High SCLK Input 3.1.7 Timer Interface Signals Table 3.1.7 Timer Interface Signals Signal Name TIMER[1:0] TCLK W DRST* Type Output Input PU OD output Timer Output Timer output signals. Description Initial State All High Input Hi-Z External Timer Clock Timer input clock signal. TMR0, TMR1, and TMR2 share this signal. Watchdog Reset Watchdog reset output signal. 3.1.8 Parallel I/O Interface Signals Table 3.1.8 Parallel I/O Interface Signals Signal Name PIO[15:8] Type Description Initial State Input Input/output PIO Ports[15:8] PU Parallel I/O signals. PIO[15:8] share pins with other function signals (refer to Section “3.3 Pin multiplex”). Input/output PIO Ports[7:0] PU Parallel I/O signals. PIO[7:0] share pins with other function signals (refer to Section “3.3 Pin multiplex”). PIO[7:0] Input 3-6 Chapter 3 Signals 3.1.9 AC-link Interface Signals Table 3.1.9 AC-link Interface Signals Signal Name ACRESET* SYNC SDOUT Type Output Output Output PU Input Description AC '97 Master H/W Reset ACRESET* share pins with other function signals (refer to Section “3.3 Pin multiplex”). 48 kHz Fixed Rate Sample Sync SYNC share pins with other function signals (refer to Section “3.3 Pin multiplex”). Serial, Time Division Multiplexed, AC '97 Output Stream SDOUT shares share pins with other function signals (refer to Section “3.3 Pin multiplex”). Serial, Time Division Multiplexed, AC ‘97 Input Stream SDIN[1] share pins with other function signals (refer to Section “3.3 Pin multiplex”). When this pin is used as SDIN[1], pull down by the resister on the board. (Regarding the value of register, please ask the Engineering Department in Toshiba). Serial, Time Division Multiplexed, AC '97 Input Stream SDIN[0] share pins with other function signals (refer to Section “3.3 Pin multiplex”). When this pin is used as SDIN[0], pull down by the resister on the board. (Regarding the value of register, please ask the Engineering Department in Toshiba). 12.288 MHz Serial Data Clock BITCLK share pins with other function signals (refer to Section “3.3 Pin multiplex”). When this pin is used as BITCLK, pull down by the resister on the board. (Regarding the value of register, please ask the Engineering Department in Toshiba). Initial State Low Low Low SDIN[1] Input SDIN[0] Input PU Input BITCLK Input PU Input 3.1.10 Interrupt Signals Table 3.1.10 Interrupt Signals Signal Name NMI* INT[5:0] Type Input PU Input PU Non-Maskable Interrupt Non-maskable interrupt signal. Description Initial State Input Input External Interrupt Requests External interrupt request signals. INT[4:3] share pins with other function signals (refer to Section “3.3 Pin multiplex”). 3.1.11 SPI Interface Signals Table 3.1.11 SPI Interface Signals Signal Name SPICLK Type Input PU Description SPI Clock This pin is used for a data clock to or from an SPI slave device. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Initial State Input SPIOUT Output High SPI Data Output This signal contains data to be shifted to an SPI slave device. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. SPI Data Inputxternal Interrupt Requests This signal contains data to be shifted from an SPI slave device. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Input SPIIN Input PU 3-7 Chapter 3 Signals 3.1.12 ISA/ATA Interface Signals Table 3.1.12 SPI Interface Signals Signal Name IOR* Type Output PU Output Description IO read This is IO read signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. IO write This is IO write signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. ATA chip select This is ATA chip select signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Initial State Input IOW * High CS[1:0]* Output PU Input 3.1.13 ETHER Interface Signals (Channel 0) Table 3.1.13 ETHER Interface Signals (Channel 0) Signal Name E0COL Type Input Description Collision detection signal This is collision detection signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Transmit clock This is IO write signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Transmit data This is the transmitting data signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Initial State Input E0TXCLK Input PU Output PU Output PU Output PU Input PU Input PU Input PU Input PU Input E0TXD[3:0] Low E0TXEN Low Transmit Enable This is the transmitting enable signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Transmit Error indicator This is the transmitting error signal. These signals are common with the other funxtions (refer to Section “3.3 Pin multiplex”). Low E0TXER E0CRS Input Carrier sense signal This is the carrier sense signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Input Receive clock This is the receive clock signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Receive data This is the receive data signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Receive data valid signal This is the receive data valid signal. These signals are common with the other functions(refer to Section “3.3 Pin multiplex”). Use the configuration setting during bootup. Receive Error indicator input This is the receive error indicator signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during bootup. Management data clock output This is the management data clock signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during bootup. Input E0RXCLK E0RXD[3:0] E0RXDV Input E0RXER Input PU Input E0MDC Output Low E0MDIO Input/output Management data bi-directional signal This is the management data bi-directional signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Input 3-8 Chapter 3 Signals 3.1.14 ETHER Interface Signals (Channel 1) Table 3.1.14 ETHER Interface Signals (Channel 1) Signal Name E1COL Type Input Description Collision detection signal This is collision detection signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Transmit clock This is IO write signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Transmit data This is the transmitting data signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Initial State Input E1TXCLK Input Input E1TXD[3:0] Output Low E1TXEN Output Low Transmit Enable This is the transmitting enable signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Transmit Error indicator This is the transmitting error signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Low E1TXER Output E1CRS Input Input Carrier sense signal This is the carrier sense signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Input Receive clock This is the receive clock signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Receive data This is the receive data signal. These signals are common with the other functions(refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Receive data valid signal This is the receive data valid signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Receive Error indicator input This is the receive error indicator signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during bootup. Management data clock output This is the management data clock signal. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during bootup. Input E1RXCLK Input E1RXD[3:0] Input E1RXDV Input PU Input Input E1RXER Input E1MDC Output Low E1MDIO Input/output Management data bi-directional signal This is the management data bi-directional signal. These signals are common with the PU other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Input 3-9 Chapter 3 Signals 3.1.15 NAND Flash Memory Interface Signals Table 3.1.15 NAND Flash Memory Interface Signals Signal Name ND_ALE Type Output PU Output Description NAND Flash Address Latch Enable ALE signal for NAND flash memory. These signals are common with the other functions (refer to Section “3.3 Pin Multiplex”). Use the configuration setting during boot-up. NAND Flash Command Latch Enable CLE signal for NAND flash memory. These signals are common with the other functions (refer to Section “3.3 Pin Multiplex”). Use the configuration setting during boot-up. NAND Flash Chip Enable CE signal for NAND flash memory. Refer to Section “3.3 Pin multiplex” NAND Flash Read Enable RE signal for NAND flash memory. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. NADND Flash Write Enable WE signal for NAND flash memory. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. NAND Flash Ready/Busy Ready/Busy signal for NAND flash memory. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during bootup. Initial State Input ND_CLE High ND_CE* ND_RE* Output Output PU Output High Input ND_WE* High ND_RB* Input PU Input 3.1.16 Extended EJTAG Interface Signals Table 3.1.16 Extended EJTAG Interface Signals (1/2) Signal Name TCK Type Input PU Input PU Description JTAG Test Clock Input Clock input signal for JTAG. TCK is used to execute JTAG instructions and input/output data. Initial State Input TDI/DINT* Input JTAG Test Data Input/Debug Interrupt When PC trace mode is not selected, this signal is a JTAG data input signal. It is used to input serial data to JTAG data/instruction registers. When PC trace mode is selected, this signal is an interrupt input signal used to cancel PC trace mode for the debug unit. JTAG Test Data Output/PC Trace Output When PC trace mode is not selected, this signal is a JTAG data output signal. Data is output by means of serial scan. When PC trace mode is selected, this signal outputs the value of the non-continuous program counter in sync with the debug clock (DCLK). PC Trace Output TPC[3:1] output the value of the noncontiguous program counter in sync with DCLK. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. JTAG Test Mode Select Input TMS mainly controls state transition in the TAP controller state machine. Test Reset Input Asynchronous reset input for the TAP controller and debug support unit (DSU). TRST* pin must be pulled down (ex. 10 kΩ). When this signal is deasserted, G-Bus timeout detection is disabled (refer to Section “5.1.1 Detecting G-Bus Timeout”). High TDO/TPC[0] Output TPC[3:1] Output All High TMS TRST* Input PU Input Input Input 3-10 Chapter 3 Signals Table 3.1.16 Extended EJTAG Interface Signals (2/2) Signal Name DCLK Type Output Description Debug Clock Clock output signal for the real-time debugging system. When PC trace mode is selected, the TPC[3:1] and PCST signals are output synchronously. This clock is the TX49/H3 core operating clock (CPUCLK) divided by 3. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. PC Trace Status Information Outputs PC trace status and other information. These signals are common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. Initial State Low PCST[8:0] Output All Low 3.1.17 Clock Signals Table 3.1.17 Clock Signals Signal Name MASTERCLK Type Input Description Master Clock Input pin for the TX4938 operating clock. A crystal resonator cannot be connected to this pin because the pin does not contain an oscillator. Halt/Doze State Output This signal is asserted (High output) when the TX4938 enters Halt or Doze mode. Bypass PLL This pin must be fixed to High. CG Reset CGRESET* initializes the CG. Initial State Input HALTDOZE BYPASSPLL* CGRESET* Output Input Input Low Input Input 3.1.18 Initialization Signal Table 3.1.18 Initialization Signal Signal Name RESET* Type Input Reset Reset signal. Description Initial State Input 3.1.19 Test Signals Table 3.1.19 Test Signals Signal Name TEST[4:0]* Type Input PU Description Test Mode Setting Test pins. These pins must be left open or fixed to High. TEST[1]* may be used when debugging the system. Toshiba recommends that your board design enable the pin to be driven low after the TX4938 is mounted on the PC board. Contact Toshiba technical staff for more information on the TEST[1]* functions. Initial State Input 3-11 Chapter 3 Signals 3.1.20 Power Supply Pins Table 3.1.20 Power Supply Pins Signal Name PLL1VDD_A, PLL2VDD_A PLL1VSS_A, PLL2VSS_A VccInt VccIO Vss Type ⎯ Description PLL Power Pins PLL analog power supply pins. PLL1VDD_A = 1.5 V. PLL2VDD_A = 1.5 V. PLL Ground Pins PLL analog ground pins. PLL1VSS_A = 0 V. PLL2VSS_A = 0 V. Internal Power Pins Digital power supply pins for internal logic. VccInt = 1.5 V. I/O Power Pins Digital power supply pins for input/output pins. VccIO = 3.3 V. Ground Pins Digital ground pins. Vss = 0 V. Initial State ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3-12 Chapter 3 Signals 3.2 Boot Configuration The ADDR[19:0] and DATA[15:0] signals can also function as configuration signals for initially setting various functions upon booting the system. The states of the configuration signals immediately after the RESET* or CGRESET* signal is deasserted are read as initial values for the TX4938 internal registers. A High signal level sets a value of 1 and a Low signal level sets a value of 0. All configuration signals are provided with internal pull-up resistors. To drive a signal Low, pull down the corresponding pin on the board using an approx. 4.7 kΩ resistor. Driving a signal High does not require a pull-down resistor. Any signals defined as Reserved should not be pulled down. Table 3.2.1 lists the functions that can be set using configuration signals. Table 3.2.2 and Table 3.2.3 describe each configuration signal. Table 3.2.1 Functions that Can be Set Using Configuration Signals Peripheral Function PCI controller Functions that Can be Set PCI controller operating mode (satellite or host) Division ratio of PCICLK[5:0] to CPUCLK PCI bus arbiter selection (internal or external) Division ratio of SYSCLK to GBUSCLK Boot device selection Division ratio of the external bus controller clock upon booting BE[3:0]*/BWE[3:0]* function selection upon booting Handling of the ACK signal upon booting (internal or external) Data bus width for the boot device Configuration Signal ADDR[19] ADDR[11:10] DATA[2] ADDR[14:13] ADDR[8:6] DATA[5] DATA[4] DATA[1:0] ADDR[16] ADDR[3:0] ADDR[18], ADDR[9] DATA[6], DATA[3] ADDR[12] DATA[15:8] DATA[7] External bus controller Ethernet controller Clock Operation frequency for System interface signal (Internal PCI bus) Division ratio of CPUCLK to MASTERCLK Shared pin function setting Others Endian setting Board information setting Controlling built-in timer interrupts of the TX49/H3 core 3-13 Chapter 3 Signals Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (1/2) Signal ADDR[19] Description PCI Controller Mode Select Specifies the operating mode of the TX4938 PCI controller. L = Satellite H = Host Select Shared I/O Pins Specifies the function of the PIO[15:8]/CB[7:0] shared pins. L = PIO[15:8] H = CB[7:0] Reserved Used for testing. This signal will not be set to 0 upon booting. Select internal PCI1 clock Frequency (PCIDMD) Specifies the operating mode of the TX4938 internal PCI controller for Ethernet Controller. L = PCI1CLK = GBUSCLK frequency/2 H = PCI1CLK = GBUSCLK frequency/4 Reserved Used for testing. This signal will not be set to 0 upon booting. Select SYSCLK Frequency Specifies the division ratio of the SYSCLK frequency to the G-Bus clock (GBUSCLK) frequency. LL = 4 (SYSCLK frequency = GBUSCLK frequency/4) LH = 3 (SYSCLK frequency = GBUSCLK frequency/3) HL = 2 (SYSCLK frequency = GBUSCLK frequency/2) HH = 1 (SYSCLK frequency = GBUSCLK frequency) TX4938 Endian Mode Specifies the TX4938 endian mode. L = Little endian H = Big endian Corresponding Register Bit CCFG. PCIMODE Configuration Determined at RESET* deassert edge ADDR[18] PCFG. SEL1 RESET* deassert edge ADDR[17] ADDR[16] ⎯ CCFG. PCI1DMD ⎯ CGRESET* deassert edge ADDR[15] ADDR[14:13] ⎯ CCFG. SYSSP ⎯ CGRESET* deassert edge ADDR[12] CCFG. ENDIAN RESET* deassert edge ADDR[11:10] Select PCI Clock Frequency CCFG. PCIDIVMODE CGRESET* deassert edge Specifies the division ratio of the PCI bus clock (PCICLK[5:0]) to the TX49/H3 core clock (CPUCLK). Initial value of CCFG[12] is 0. LL = 8 (PCICLK frequency = CPUCLK frequency/8) LH = 9 (PCICLK frequency = CPUCLK frequency/9) HL = 10 (PCICLK frequency = CPUCLK frequency/10) HH = 11 (PCICLK frequency = CPUCLK frequency/11) PIO[4:2]/ACLC/DMAREQ[2]/DMAACK[2] Select Specifies whether PIO[4:2]/DMAREQ[2]/DMAACK[2] signals are used as PIO or AC-link interface signals. L = PIO H = AC-link interface Select Boot Memory and Device Clock Frequency Specifies the clock division ratio for external bus controller channel 0 upon booting (refer to Section “7.3.8 Clock Options”). HHH = Device connected to channel 0 of the external bus controller (Clock division rate = 1/1) HHL = Device connected to channel 0 of the external bus controller (Clock division rate = 1/2) HLH = Device connected to channel 0 of the external bus controller (Clock division rate = 1/3) HLL = Device connected to channel 0 of the external bus controller (Clock division rate = 1/4) LHH =PCI boot LHL = NAND Flash memory boot (NAND IPL) LLH and LLL = Reserved PCFG.SEL2 RESET* deassert edge ADDR[9] ADDR[8:6] ADDR[8]: EBCCR0.ME ADDR[7:6] EBCCR0.SP RESET* deassert edge 3-14 Chapter 3 Signals Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (2/2) Signal ADDR[5] Description Select SDRAM device Select initial setting derivability of SDRAM interface signals L = 8mA H = 16mA ADDR[19:0], CKE, RAS*, CAS*, WE*, SDCS[3:0], SDCLK[3:0], SDCLKIN Initial Setting of Boot Select initial setting derivability of SDRAM interface signals L = 8mA H = 16mA DATA[63:0], CB[7:0], DQM[7:0] CPUCLK Clock Speed Setting Specifies the value by which MASTERCLK input signal is multiplied to produce the TX49/H3 core clock (CPUCLK). The values of ADDR[1:0] are also reflected in the EC field of the TX49/H3 core Config register. ADDR[3:0] : DIVMODE[3:0] HHHH:0100 CPUCLK frequency = 2 x MASTERCLK frequency HHHL:1111 CPUCLK frequency = 2.5 x MASTERCLK frequency HHLH:0101 CPUCLK frequency = 3 x MASTERCLK frequency HHLL:0110 CPUCLK frequency = 4 x MASTERCLK frequency LHHH:1101 CPUCLK frequency = 4.5 x MASTERCLK frequency LHHL: reserved LHLH: reserved LHLL: reserved HLHH:0000 CPUCLK frequency = 8 x MASTERCLK frequency HLHL:1011 CPUCLK frequency = 10 x MASTERCLK frequency HLLH:0001 CPUCLK frequency = 12 x MASTERCLK frequency HLLL:0010 CPUCLK frequency = 16 x MASTERCLK frequency LLHH:1001 CPUCLK frequency = 18 x MASTERCLK frequency LLHL: reserved LLLH: reserved LLLL: reserved Corresponding Register Bit PCFG[53:40] Configuration Determined at RESET* deassert edge ADDR[4] PCFG[56:54] RESET* deassert edge ADDR[3:0] CCFG.DIVMODE CGRESET* deassert edge 3-15 Chapter 3 Signals Table 3.2.3 Boot Configuration Specified with the DATA[22:0] Signals Signal DATA[22:16] DATA[15:8] Reserved Description Corresponding Register Bit ⎯ Configuration Determined at ⎯ RESET* deassert edge CCFG.BCFG Boot Configuration Reads the board information and accordingly sets the boot configuration field (BCFG) of the chip configuration register (CCFG). TX49/H3 Internal Timer Interrupt Disable Specifies whether timer interrupts within the TX49/H2 core are enabled. H = Enable timer interrupts within the TX49/H3 core. L = Disable timer interrupts within the TX49/H3 core. L = ETHER1 usable H = ETHER1 unusable Specifies the function of the BE[3:0]*/BWE[3:0]* pins upon booting. L = BE[3:0]* (Byte Enable) H = BWE[3:0]* (Byte Write Enable) Boot ACK* Input Specifies the access mode for external bus controller channel 0. L = External ACK mode H = Normal mode L = ETHER0 usable H = ETHER0 unusable PCI Arbiter Select Selects a PCI bus arbiter. L = External PCI bus arbiter. H = Built-in PCI bus arbiter. Boot ROM Bus Width Specifies the data bus width when booting from a memory device connected to the external bus controller. LL = Reserved LH = 32 bits HL = 16 bits HH = 8 bits CCFG.TINTDIS DATA[7] RESET* deassert edge DATA[6] DATA[5] PCFG.ETH1_SEL EBCCR0.BC RESET* deassert edge RESET* deassert edge DATA[4] EBCCR0.WT[0] RESET* deassert edge DATA[3] DATA[2] PCFG.ETH0_SEL CCFG.PCIARB RESET* deassert edge RESET* deassert edge DATA[1:0] EBCCR0.BSZ RESET* deassert edge 3-16 Chapter 3 Signals 3.3 Pin multiplex The TX4938 has some multiplexed pins. Each pin is used for different functions depending on the settings of the PCFG[61:58] control register and ADDR[18]/[9], DATA[6]/[3] boot configuration signal. Table 3.3.1 shows how to set the function for each pin. Table 3.3.1 Pin multiplex (1/2) Signal, PCFG ADDR[18] ADDR[9] DATA[6] DATA[3] PCFG[61] PCFG[60] PCFG[59] PCFG[58] CE[7] CE[6] CE[5] CE[4] CE[3] CB[7] CB[6] CB[5] CB[4] CB[3] CB[2] CB[1] CB[0] CB[7] CB[6] CB[5] CB[4] CB[3] CB[2] CB[1] CB[0] PIO[15] PIO[14] PIO[13] PIO[12] PIO[11] PIO[10] PIO[9] PIO[8] E0TXD[3] E0TXD[2] E0RXD[3] E0RXD[2] E0TXD[1] E0TXD[0] E0RXD[1] E0RXD[0] IOR* IOW * ACRESET E0TXCLK * SYNC E0MDIO SPIN SPIOUT IOR* IOW * ND_RE* ND_WE* Function on pin-multiplex ECC H * * H * * * * PIO[15:8] L * * H * * * * ACLC * H * H * * * * ETHER0 ETHER1 ATA/ISA H L * L * * * * * * L * * * * * E1COL E1CRS E1TXER * * * * 1 * * 0 ISA * * * * 0 1 * 0 SPI * * * * * * 1 * NDFMC * * * * 0 0 * 1 Setting of Boot config. signal and PCFG (Note1) (Note2) ND_CE* ND_CLE Function of Each signal (Note3) (Note4) DMAREQ[3] DMAACK[3] DMAREQ[2] DMAACK[2] DMAREQ[1] DMAACK[1] DMAREQ[0] DMAACK[0] PIO[7] PIO[6] PIO[5] PIO[4] PIO[3] PIO[2] SDOUT SDIN[0] BITCLK E0TXEN E0CRS CS[1]* CS[0]* ND_RB * ND_AL E 3-17 Chapter 3 Signals Table 3.3.1 Pin multiplex (2/2) Signal, PCFG PIO[1] PIO[0] INT[5] INT[4] INT[3] INT[2] INT[1] INT[0] CTS[1]* RTS[1]* RXD[1] TXD[1] CTS[0]* E0RXCLK E0MDC E0RXDV E0TXER E0RXER E1RXDV Function on pin-multiplex ECC PIO[15:8] ACLC ETHER0 ETHER1 E1MDIO SPICLK ATA ISA SPI NDFMC Function of Each signal (Note3) (Note4) RTS[0]* RXD[0] TXD[0] SDIN[1] DCLK PCST[8] PCST[7] PCST[6] PCST[5] PCST[4] PCST[3] PCST[2] PCST[1] PCST[0] TPC[3] TPC[2] TPC[1] SDIN[1] E0COL E1TXD[3] E1TXD[2] E1TXD[1] E1TXD[0] E1RXD[3] E1RXD[2] E1RXD[1] E1RXD[0] E1RXCLK E1TXCLK E1RXER E1MDC E1TXEN Note 1: * shows that there is no relationship to the configuration of the corresponding function. Note 2: One of ECC, PIO[15:8] and ETHERC0 can be selected (can't use simultaneously). One of ACLC and ETHERC0 can be selected (can't use simultaneously). One of ATA and NDFMC can be selected (can't use simultaneously). One of ISA and NDFMC can be selected (can't use simultaneously). (Operation is not guaranteed when these functions that cannot be used simultaneously are set up) Note 3: It shows that these terminals are multiplexed under each function. Note 4: Blank shows that the terminal isn't multiplexed with the function. For example, when only two pieces, ATA and SPI are selected, functions other than DMAREQ[3], DMAREQ[1], DMAACK[3], DMAACK[1], PIO[0] can be used. 3-18 Chapter 4 Address Mapping 4. Address Mapping This chapter explains the physical address map of TX4938. Please refer to "64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture" about the details of mapping to a physical address from the virtual address of TX49/H3 core. 4.1 TX4938 Physical Address Map TX4938 supports up to 64G (236) bytes of physical address. Following resources are to be allocated in the physical address of the TX4938. • • • • TX4938 Internal registers (refer to “4.2 Register Map”) SDRAM (refer to “9.3.2 Address Mapping”) External Devices such as ROM, I/O Devices (refer to “7.3.3 Address Mapping”) PCI Bus (refer to “10.3.4 Initiator Access”) Each resource is to be allocated in any physical addresses by the register setup. Refer to the explanation of each controller for the details of the mapping. At initialization, only the internal registers and the memory space which stores the TX49/H3 core reset vectors are allocated shown as Figure 4.1.1. Usually ROM connected to the external bus controller channel 0 is used for the memory device that stores the reset vectors. TX4938 also supports using the memories on PCI bus as the memory device stores the reset vectors. Refer to “10.3.13 PCI Boot” for detail about this. 0xF_FFFF_FFFF 0xF_FF1F_FFFF TX4938 Internal Register 0xF_FF1F_0000 64 K Bytes 0x0_1FFF_FFFF External Bus Controller Channel 0 0x0_1FC0_0000 4 M Bytes 0x0_0000_0000 Figure 4.1.1 Physical Address Map at Initializing System It is possible to access a resource of TX4938 as a PCI target device through PCI bus. About how to allocate resources of TX4938 to the PCI bus address space, refer to “10.3.5 Target Access”. 4-1 Chapter 4 Address Mapping 4.2 Register Map Addressing TX4938 internal registers are to be accessed through 64 K bytes address space that is based on physical address 0xF_FF1F_0000 or pointed address by RAMP register (refer to 5.2.7). Figure 4.2.1 shows how to generate internal register address. Physical address 1 and physical address 2 shown Figure 4.2.1 access the same register. In TX49/H3 Core, the physical address form 0xF_FF00_0000 to 0xF_FF3F_FFFF are uncached mapped to the virtual address form 0xFF00_0000 to 0xFF3F_FFFF (32 bit mode) /form 0xFFFF_FFFF_FF00_0000 to 0xFFFF_FFFF_FF3F_FFFF (64 bit mode). This space includes the region form 0xF_FF1F_0000 allocated TX4938 internal registers at initialization. Base Address (0xF_FF1F_0000) + Offset Address = Physical Address 1 4.2.1 Base Address Register (RAMP) + Offset Address = Physical Address 2 Figure 4.2.1 Generating Physical Address for a Internal Register 4.2.2 Ways to Access to Internal Registers 3 ways to access to the internal registers of TX4938 are supported. First is 32-bit register access. Second is 64-bit register access. Last is PCI configuration register access in PCI satellite mode. 32-bit register supports 32-bit size access only. Another size access without 32-bit size is undefined. 64-bit register supports both 64-bit size access and two times 32-bit size access. In each Endian mode, 32-bit size access is performed shown as Table 4.2.1. When the build-in PCI controller works in the satellite mode (refer to “10.3.1 Terminology Explanation”), PCI configuration registers are to be accessed through PCI bus in configuration cycles. It is possible to access to the arbitrary size of PCI configuration register as always Little Endian space regardless the system setup. Table 4.2.1 32-bit Size Access to 64-bit Register Address 0x*_****_***0 0x*_****_***8 0x*_****_***4 0x*_****_***C Big Endian (Bit which are accessed) [63........32] [31........0] ######## Little Endian (Bit which are accessed) [63........32] [31........0] ######## [63........32] [31........0] ######## [63........32] [31........0] ######## (######## means 32 bits data (upper 32 bits or lower 32 bits) which are accessed.) 4-2 Chapter 4 Address Mapping 4.2.3 Register Map Please refer to “10.5 PCI Configuration Space Register” about PCI configuration register. Table 4.2.2 Register Map Offset Address 0x0000 to 0x4FFF 0x5000 to 0x5FFF 0x6000 to 0x67FF 0x6800 to 0x6FFF 0x7000 to 0x7FFF Peripheral Controller Reserved NDFMC SRAMC Reserved PCIC1 Detail ⎯ Refer to “20.4” Refer to “21.4” ⎯ Refer to “16” (For ETHERC0 and ETHERC1) Refer to “9.4” Refer to “7.4” Refer to “9.4” Refer to “8.4” Refer to “8.4” Refer to “10.4” Refer to “5.2” Refer to “12.4” Refer to “12.4” Refer to “12.4” Refer to “11.4” Refer to “11.4” Refer to “13.4” Refer to “15.4” Refer to “14.4” Refer to “17.4” 0x8000 to 0x8FFF 0x9000 to 0x9FFF 0xA000 to 0xAFFF 0xB000 to 0xB7FF 0xB800 to 0xBFFF 0xD000 to 0xDFFF 0xE000 to 0xEFFF 0xF000 to 0xF0FF 0xF100 to 0xF1FF 0xF200 to 0xF2FF 0xF300 to 0xF3FF 0xF400 to 0xF4FF 0xF500 to 0xF50F 0xF510 to 0xF6FF 0xF700 to 0xF7FF 0xF800 to 0xF8FF 0xF900 to 0xFFFF SDRAMC EBUSC ECC DMAC0 DMAC1 PCIC CONFIG TMR0 TMR1 TMR2 SIO0 SIO1 PIO IRC ACLC SPIC Reserved 4-3 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (1/12) Offset Address 0x5000 0x5008 0x5010 0x5018 0x5020 0x5028 0x5030 SRAM Controller (SRAMC) 0x6000 64 SRAMCR Internal SRAM Control Register Register Size (bit) Register Symbol 64 64 64 64 64 64 64 NDFDTR NDFMCR NDFSR NDFISR NDFIMR NDFSPR NDFRSTR Register Name NAND Flash Memory Data Transfer Register NAND Flash Memory Mode Control Register NAND Flash Memory Status Register NAND Flash Memory Interrupt Status Register NAND Flash Memory Interrupt Mask Register NAND Flash Memory Strobe Pulse Width Register NAND Flash Memory Reset Register NAND Flash Memory Controller (NDFMC) 4-4 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (2/12) Offset Address 0x7000 0x7004 0x7008 0x700C 0x7010 0x7014 0x7018 0x701C 0x7020 0x7024 0x702C 0x7034 0x703C 0x7040 0x7080 0x7084 0x7088 0x708C 0x7090 0x7094 0x7098 0x709C 0x7100 0x7104 0x7108 0x710C 0x7110 0x7114 0x7118 0x711C Register Size (bit) Register Symbol 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 PCIID PCISTATUS PCICCREV PCICFG1 P2GM0PLBASE P2GM0PUBASE P2GM1PLBASE P2GM1PUBASE P2GM2PBASE P2GIOPBASE PCISID PCICAPPTR PCICFG2 G2PTOCNT G2PSTATUS G2PMASK PCISSTATUS PCIMASK P2GCFG P2GSTATUS P2GMASK P2GCCMD PBAREQPORT PBACFG PBASTATUS PBAMASK PBABM PBACREQ PBACGNT PBACSTATE Register Name ID Register (Device ID, Vender ID) PCI Status Command Register (Status, Command) Class Code Revision ID Register (Class Code, Revision ID) PCI Configuration 1 Register (BIST, Header Type, Latency Timer, Cache Line Size) P2G Memory Space 0 PCI Lower Base Address Register (Base Address 0 Lower) P2G Memory Space 0 PCI Upper Base Address Register (Base Address 0 Upper) P2G Memory Space 1 PCI Lower Base Address Register (Base Address 1 Lower) P2G Memory Space 1 PCI Upper Base Address Register (Base Address 1 Upper) P2G Memory Space 2 PCI Base Address Register (Base Address 2) P2G I/O Space PCI Base Address Register (Base Address 3) Subsystem ID Register (Subsystem ID, Subsystem Vender ID) Capability Pointer Register (Capability Register) PCI Configuration 2 Register (Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line) G2P Timeout Count Register (Retry Timeout Value, TRDY Timeout Value) G2P Status Register G2P Interrupt Mask Register Satellite Mode PCI Status Register (Status, PMCSR) PCI Status Interrupt Mask Register P2G Configuration Register P2G Status Register P2G Interrupt Mask Register P2G Current Command Register PCI Bus Arbiter Request port Register PCI Bus Arbiter Configuration Register PCI Bus Arbiter Status Register PCI Bus Arbiter Interrupt Mask Register PCI Bus Arbiter Broken Master Register PCI Bus Arbiter Current Request Register PCI Bus Arbiter Current Grant Register PCI Bus Arbiter Current State Register PCI Controller for ETHERC (PCIC1) 4-5 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (3/12) Offset Address 0x7120 0x7128 0x7130 0x7138 0x7140 0x7144 0x7148 0x714C 0x7150 0x7158 0x7160 0x7168 0x7170 0x7174 0x7178 0x7180 0x7188 0x7190 0x7198 0x71A0 0x71A4 0x71C8 0x71CC Register Size (bit) Register Symbol 64 64 64 64 32 32 32 32 64 64 64 64 32 32 32 64 64 64 64 32 32 32 32 G2PM0GBASE G2PM1GBASE G2PM2GBASE G2PIOGBASE G2PM0MASK G2PM1MASK G2PM2MASK G2PIOMASK G2PM0PBASE G2PM1PBASE G2PM2PBASE G2PIOPBASE PCICCFG PCICSTATUS PCICMASK P2GM0GBASE P2GM1GBASE P2GM2GBASE P2GIOGBASE G2PCFGADRS G2PCFGDATA G2PINTACK G2PSPC Register Name G2P Memory Space 0 G-bus Base Address Register G2P Memory Space 1 G-bus Base Address Register G2P Memory Space 2 G-bus Base Address Register G2P I/O Space G-bus Base Address Register G2P Memory Space 0 Address Mask Register G2P Memory Space 1 Address Mask Register G2P Memory Space 2 Address Mask Register G2P I/O Space Address Mask Register G2P Memory Space 0 PCI Base Address Register G2P Memory Space 1 PCI Base Address Register G2P Memory Space 2 PCI Base Address Register G2P I/O Space PCI Base Address Register PCI Controller Configuration Register PCI Controller Status Register PCI Controller Interrupt Mask Register P2G Memory Space 0 G-bus Base Address Register P2G Memory Space 1 G-bus Base Address Register P2G Memory Space 2 G-bus Base Address Register P2G I/O Space G-bus Base Address Register G2P Configuration Address Register G2P Interrupt Acknowledge Data Register G2P Interrupt Acknowledge Data Register G2P Special Cycle Data Register PCI Controller for ETHERC (PCIC1) 4-6 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (4/12) Offset Address 0x8000 0x8008 0x8010 0x8018 0x8040 0x8058 0x9000 0x9008 0x9010 0x9018 0x9020 0x9028 0x9030 0x9038 0xA000 0xA008 External Bus Controller (EBUSC) 64 64 64 64 64 64 64 64 64 64 EBCCR0 EBCCR1 EBCCR2 EBCCR3 EBCCR4 EBCCR5 EBCCR6 EBCCR7 ECCCR ECCSR EBUS Channel Control Register 0 EBUS Channel Control Register 1 EBUS Channel Control Register 2 EBUS Channel Control Register 3 EBUS Channel Control Register 4 EBUS Channel Control Register 5 EBUS Channel Control Register 6 EBUS Channel Control Register 7 ECC Control Register ECC Status Register Register Size (bit) Register Symbol 64 64 64 64 64 64 SDCCR0 SDCCR1 SDCCR2 SDCCR3 SDCTR SDCCMD Register Name SDRAM Channel Control Register 0 SDRAM Channel Control Register 1 SDRAM Channel Control Register 2 SDRAM Channel Control Register 3 SDRAM Timing Register SDRAM Command Register SDRAM Controller (SDRAMC) SDRAM Error Check Correction (ECC) 4-7 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (5/12) Offset Address 0xB000 0xB008 0xB010 0xB018 0xB020 0xB028 0xB030 0xB038 0xB040 0xB048 0xB050 0xB058 0xB060 0xB068 0xB070 0xB078 0xB080 0xB088 0xB090 0xB098 0xB0A0 0xB0A8 0xB0B0 0xB0B8 0xB0C0 0xB0C8 0xB0D0 0xB0D8 0xB0E0 0xB0E8 0xB0F0 0xB0F8 0xB148 0xB150 Register Size (bit) Register Symbol 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 DM0CHAR0 DM0SAR0 DM0DAR0 DM0CNTR0 DM0SAIR0 DM0DAIR0 DM0CCR0 DM0CSR0 DM0CHAR1 DM0SAR1 DM0DAR1 DM0CNTR1 DM0SAIR1 DM0DAIR1 DM0CCR1 DM0CSR1 DM0CHAR2 DM0SAR2 DM0DAR2 DM0CNTR2 DM0SAIR2 DM0DAIR2 DM0CCR2 DM0CSR2 DM0CHAR3 DM0SAR3 DM0DAR3 DM0CNTR3 DM0SAIR3 DM0DAIR3 DM0CCR3 DM0CSR3 DM0MFDR DM0MCR Register Name DMAC0 Chain Address Register 0 DMAC0 Source Address Register 0 DMAC0 Destination Address Register 0 DMAC0 Count Register 0 DMAC0 Source Address Increment Register 0 DMAC0 Destination Address Increment Register 0 DMAC0 Channel Control Register 0 DMAC0 Channel Status Register 0 DMAC0 Chain Address Register 1 DMAC0 Source Address Register 1 DMAC0 Destination Address Register 1 DMAC0 Count Register 1 DMAC0 Source Address Increment Register 1 DMAC0 Destination Address Increment Register 1 DMAC0 Channel Control Register 1 DMAC0 Channel Status Register 1 DMAC0 Chain Address Register 2 DMAC0 Source Address Register 2 DMAC0 Destination Address Register 2 DMAC0 Count Register 2 DMAC0 Source Address Increment Register 2 DMAC0 Destination Address Increment Register 2 DMAC0 Channel Control Register 2 DMAC0 Channel Status Register 2 DMAC0 Chain Address Register 3 DMAC0 Source Address Register 3 DMAC0 Destination Address Register 3 DMAC0 Count Register 3 DMAC0 Source Address Increment Register 3 DMAC0 Destination Address Increment Register 3 DMAC0 Channel Control Register 3 DMAC0 Channel Status Register 3 DMAC0 Memory Fill Data Register DMAC0 Master Control Register DMA Controller (DMAC0) 4-8 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (6/12) Offset Address 0xB800 0xB808 0xB810 0xB818 0xB820 0xB828 0xB830 0xB838 0xB840 0xB848 0xB850 0xB858 0xB860 0xB868 0xB870 0xB878 0xB880 0xB888 0xB890 0xB898 0xB8A0 0xB8A8 0xB8B0 0xB8B8 0xB8C0 0xB8C8 0xB8D0 0xB8D8 0xB8E0 0xB8E8 0xB8F0 0xB8F8 0xB948 0xB950 Register Size (bit) Register Symbol 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 DM1CHAR0 DM1SAR0 DM1DAR0 DM1CNTR0 DM1SAIR0 DM1DAIR0 DM1CCR0 DM1CSR0 DM1CHAR1 DM1SAR1 DM1DAR1 DM1CNTR1 DM1SAIR1 DM1DAIR1 DM1CCR1 DM1CSR1 DM1CHAR2 DM1SAR2 DM1DAR2 DM1CNTR2 DM1SAIR2 DM1DAIR2 DM1CCR2 DM1CSR2 DM1CHAR3 DM1SAR3 DM1DAR3 DM1CNTR3 DM1SAIR3 DM1DAIR3 DM1CCR3 DM1CSR3 DM1MFDR DM1MCR Register Name DMAC1 Chain Address Register 0 DMAC1 Source Address Register 0 DMAC1 Destination Address Register 0 DMAC1 Count Register 0 DMAC1 Source Address Increment Register 0 DMAC1 Destination Address Increment Register 0 DMAC1 Channel Control Register 0 DMAC1 Channel Status Register 0 DMAC1 Chain Address Register 1 DMAC1 Source Address Register 1 DMAC1 Destination Address Register 1 DMAC1 Count Register 1 DMAC1 Source Address Increment Register 1 DMAC1 Destination Address Increment Register 1 DMAC1 Channel Control Register 1 DMAC1 Channel Status Register 1 DMAC1 Chain Address Register 2 DMAC1 Source Address Register 2 DMAC1 Destination Address Register 2 DMAC1 Count Register 2 DMAC1 Source Address Increment Register 2 DMAC1 Destination Address Increment Register 2 DMAC1 Channel Control Register 2 DMAC1 Channel Status Register 2 DMAC1 Chain Address Register 3 DMAC1 Source Address Register 3 DMAC1 Destination Address Register 3 DMAC1 Count Register 3 DMAC1 Source Address Increment Register 3 DMAC1 Destination Address Increment Register 3 DMAC1 Channel Control Register 3 DMAC1 Channel Status Register 3 DMAC1 Memory Fill Data Register DMAC1 Master Control Register DMA Controller (DMAC1) 4-9 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (7/12) Offset Address PCI Controller (PCIC) 0xD000 0xD004 0xD008 0xD00C 0xD010 0xD014 0xD018 0xD01C 0xD020 0xD024 0xD02C 0xD034 0xD03C 0xD040 0xD080 0xD084 0xD088 0xD08c 0xD090 0xD094 0xD098 0xD09C 0xD100 0xD104 0xD108 0xD10C 0xD110 0xD114 0xD118 0xD11C 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 PCIID PCISTATUS PCICCREV PCICFG1 P2GM0PLBASE P2GM0PUBASE P2GM1PLBASE P2GM1PUBASE P2GM2PBASE P2GIOPBASE PCISID PCICAPPTR PCICFG2 G2PTOCNT G2PSTATUS G2PMASK PCISSTATUS PCIMASK P2GCFG P2GSTATUS P2GMASK P2GCCMD PBAREQPORT PBACFG PBASTATUS PBAMASK PBABM PBACREQ PBACGNT PBACSTATE ID Register (Device ID, Vendor ID) PCI Status, Command Register (Status, Command) Class Code, Revision ID Register (Class Code, Revision ID) PCI Configuration 1 Register (BIST, Header Type, Latency Timer, Cache Line Size) P2G Memory Space 0 PCI Lower Base Address Register (Base Address 0 Lower) P2G Memory Space 0 PCI Upper Base Address Register (Base Address 0 Upper) P2G Memory Space 1 PCI Lower Base Address Register (Base Address 1 Lower) P2G Memory Space 1 PCI Upper Base Address Register (Base Address 1 Upper) P2G Memory Space 2 PCI Base Address Register (Base Address 2) P2G I/O Space PCI Base Address Register (Base Address 3) Subsystem ID Register (Subsystem ID, Subsystem Vendor ID) Capabilities Pointer Register (Capabilities Pointer) PCI Configuration 2 Register (Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line) G2P Timeout Count register (Retry Timeout Value, TRDY Timeout Value) G2P Status Register G2P Interrupt Mask Register Satellite Mode PCI Status Register (Status, PMCSR) PCI Status Interrupt Mask Register P2G Configuration Register P2G Status Register P2G Interrupt Mask Register P2G Current Command Register PCI Bus Arbiter Request Port Register PCI Bus Arbiter Configuration Register PCI Bus Arbiter Status Register PCI Bus Arbiter Interrupt Mask Register PCI Bus Arbiter Broken Master Register PCI Bus Arbiter Current Request Register (for a diagnosis) PCI Bus Arbiter Current Grant Register (for a diagnosis) PCI Bus Arbiter Current Status Register (for a diagnosis) Register Size (bit) Register Symbol Register Name 4-10 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (8/12) Offset Address 0xD120 0xD128 0xD130 0xD138 0xD140 0xD144 0xD148 0xD14C 0xD150 0xD158 0xD160 0xD168 0xD170 0xD174 0xD178 0xD180 0xD188 0xD190 0xD198 0xD1A0 0xD1A4 0xD1C8 0xD1CC 0xD1D0 0xD1D4 0xD1D8 0xD1DC 0xD200 0xD208 0xD210 0xD218 0xD220 0xD228 Register Size (bit) Register Symbol 64 64 64 64 32 32 32 32 64 64 64 64 32 32 32 64 64 64 64 32 32 32 32 32 32 32 32 64 64 64 64 64 64 G2PM0GBASE G2PM1GBASE G2PM2GBASE G2PIOGBASE G2PM0MASK G2PM1MASK G2PM2MASK G2PIOMASK G2PM0PBASE G2PM1PBASE G2PM2PBASE G2PIOPBASE PCICCFG PCICSTATUS PCICMASK P2GM0GBASE P2GM1GBASE P2GM2GBASE P2GIOGBASE G2PCFGADRS G2PCFGDATA G2PINTACK G2PSPC PCICDATA0 PCICDATA1 PCICDATA2 PCICDATA3 PDMCA PDMGA PDMPA PDMCTR PDMCFG PDMSTATUS Register Name G2P Memory Space 0 G-Bus Base Address Register G2P Memory Space 1 G-Bus Base Address Register G2P Memory Space 2 G-Bus Base Address Register G2P I/O Space G-Bus Base Address Register G2P Memory Space 0 Address Mask Register G2P Memory Space 1 Address Mask Register G2P Memory Space 2 Address Mask Register G2P I/O Space Address Mask Register G2P Memory Space 0 PCI Base Address Register G2P Memory Space 1 PCI Base Address Register G2P Memory Space 2 PCI Base Address Register G2P I/O Space PCI Base Address Register PCI Controller Configuration Register PCI Controller Status Register PCI Controller Interrupt Mask register P2G Memory Space 0 G-Bus Base Address Register P2G Memory Space 1 G-Bus Base Address Register P2G Memory Space 2 G-Bus Base Address Register P2G I/O Space 0 G-Bus Base Address Register G2P Configuration Address Register G2P Configuration Data Register G2P Interrupt Acknowledge Register G2P Special Cycle Data Register PCI Configuration Data 0 Register PCI Configuration Data 1 Register PCI Configuration Data 2 Register PCI Configuration Data 3 Register PDMAC Chain Address Register PDMAC G-Bus Address Register PDMAC PCI Bus Address Register PDMAC Count Register PDMAC Configuration Register PDMAC Status Register 4-11 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (9/12) Offset Address Configuration 0xE000 0xE008 0xE010 0xE018 0xE020 0xE030 0xE048 0xE050 Timer (Channel 0) 0xF000 0xF004 0xF008 0xF00C 0xF010 0xF020 0xF030 0xF0F0 Timer (Channel 1) 0xF100 0xF104 0xF108 0xF10C 0xF110 0xF120 0xF130 0xF1F0 Timer (Channel 2) 0xF200 0xF204 0xF208 0xF210 0xF220 0xF240 0xF2F0 32 32 32 32 32 32 32 TMTCR2 TMTISR2 TMCPRA2 TMITMR2 TMCCDR2 TMWTMR2 TMTRR2 Timer Control Register 2 Timer Interrupt Status Register 2 Compare Register A 2 Interval Timer Mode Register 2 Divider Register 2 Watch Dog Timer Register 2 Timer Read Register 2 32 32 32 32 32 32 32 32 TMTCR1 TMTISR1 TMCPRA1 TMCPRB1 TMITMR1 TMCCDR1 TMPGMR1 TMTRR1 Timer Control Register 1 Timer Interrupt Status Register 1 Compare Address Register A 1 Compare Address Register B 1 Interval Timer Mode Register 1 Divider Register 1 Plus Generator Mode Register 1 Timer Read Register 1 32 32 32 32 32 32 32 32 TMTCR0 TMTISR0 TMCPRA0 TMCPRB0 TMITMR0 TMCCDR0 TMPGMR0 TMTRR0 Timer Control Register 0 Timer Interrupt Status Register 0 Compare Address Register A 0 Compare Address Register B 0 Interval Timer Mode Register 0 Divider Register 0 Plus Generator Mode Register 0 Timer Read Register 0 64 64 64 64 64 64 64 64 CCFG REVID PCFG TOEA CLKCTR GARBC RAMP Chip Configuration Register Chip Revision ID Register Pin Configuration Register Timeout Error Access Address Register Clock Control Register G-Bus Arbiter Control Register Register Address Mapping Register Reserved Register Size (bit) Register Symbol Register Name 4-12 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (10/12) Offset Address Serial I/O (Channel 0) 0xF300 0xF304 0xF308 0xF30C 0xF310 0xF314 0xF318 0xF31C 0xF320 Serial I/O (Channel 1) 0xF400 0xF404 0xF408 0xF40C 0xF410 0xF414 0xF418 0xF41C 0xF420 Parallel I/O (PIO) 0xF500 0xF504 0xF508 0xF50C 32 32 32 32 PIODO PIODI PIODIR PIOOD Output Data Register Input Data Register Direction Control Register Open Drain Control Register 32 32 32 32 32 32 32 32 32 SILCR1 SIDICR1 SIDISR1 SISCISR1 SIFCR1 SIFLCR1 SIBGR1 SITFIFO1 SIRFIFO1 Line Control Register 1 DMA/Interrupt Control Register 1 DMA/ Interrupt Status Register 1 Status Change Interrupt Status Register 1 FIFO Control Register 1 Flow Control Register 1 Baud Rate Control Register 1 Transmitter FIFO Register 1 Receiver FIFO Register 1 32 32 32 32 32 32 32 32 32 SILCR0 SIDICR0 SIDISR0 SISCISR0 SIFCR0 SIFLCR0 SIBGR0 SITFIFO0 SIRFIFO0 Line Control Register 0 DMA/Interrupt Control Register 0 DMA/ Interrupt Status Register 0 Status Change Interrupt Status Register 0 FIFO Control Register 0 Flow Control Register 0 Baud Rate Control Register 0 Transmitter FIFO Register 0 Receiver FIFO Register 0 Register Size (bit) Register Symbol Register Name 4-13 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (11/12) Offset Address 0xF510 0xF514 0xF518 0xF51C 0xF520 0xF524 0xF600 0xF604 0xF608 0xF610 0xF614 0xF618 0xF61C 0xF620 0xF624 0xF628 0xF62C 0xF640 0xF660 0xF680 0xF6A0 Register Size (bit) Register Symbol 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 IRFLAG0 IRFLAG1 IRPOL IRRCNT IRMASKINT IRMASKEXT IRDEN IRDM0 IRDM1 IRLVL0 IRLVL1 IRLVL2 IRLVL3 IRLVL4 IRLVL5 IRLVL6 IRLVL7 IRMSK IREDC IRPND IRCS Register Name Interrupt Request Flag 0 Register Interrupt Request Flag 1 Register Interrupt Request Polarity Control Register Interrupt Request Control Register Internal Interrupt Mask Register External Interrupt Mask Register Interrupt Detection Enable Register Interrupt Detection Mode Register 0 Interrupt Detection Mode Register 1 Interrupt Level Register 0 Interrupt Level Register 1 Interrupt Level Register 2 Interrupt Level Register 3 Interrupt Level Register 4 Interrupt Level Register 5 Interrupt Level Register 6 Interrupt Level Register 7 Interrupt Mask Level Register Interrupt Edge Detection Clear Register Interrupt Pending Register Interrupt Current Status Register Interrupt Controller (IRC) 4-14 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (12/12) Offset Address 0xF700 0xF704 0xF708 0xF710 0xF714 0xF718 0xF71C 0xF720 0xF740 0xF744 0xF748 0xF74C 0xF750 0xF780 0xF784 0xF7A0 0xF7A4 0xF7A8 0xF7AC 0xF7B0 0xF7B8 0xF7BC 0xF7FC Serial Peripheral Interface (SPI) 0xF800 0xF804 0xF808 0xF80C 0xF810 0xF814 0xF818 0xF81C 32 32 32 32 32 32 32 32 SPMCR SPCR0 SPCR1 SPFS SPSR SPDR SPI Master Control Register SPI Control Register 0 SPI Control Register 1 SPI Inter Frame Space Register Reserved SPI Status Register SPI Data Register Reserved Register Size (bit) Register Symbol 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCTLEN ACCTLDIS ACREGACC ACINTSTS ACINTMSTS ACINTEN ACINTDIS ACSEMAPH ACGPIDAT ACGPODAT ACSLTEN ACSLTDIS ACFIFOSTS ACDMASTS ACDMASEL ACAUDODAT ACSURRDAT ACCENTDAT ACLFEDAT ACAUDIDAT ACMODODAT ACMODIDAT ACREVID Register Name ACLC Control Enable Register ACLC Control Disable Register ACLC CODEC Register Access Register ACLC Interrupt Status Register ACLC Interrupt Masked Status Register ACLC Interrupt Enable Register ACLC Interrupt Disable Register ACLC Semaphore Register ACLC GPI Data Register ACLC GPO Data Register ACLC Slot Enable Register ACLC Slot Disable Register ACLC FIFO Status Register ACLC DMA Request Status Register ACLC DMA Channel Selection Register ACLC Audio PCM Output Data Register ACLC Surround Data Register ACLC Center Data register ACLC LFE Data Register ACLC Audio PCM Input Data Register ACLC Modem Output Data Register ACLC Modem Input Data Register ACLC Revision ID Register AC-link Controller (ACLC) 4-15 Chapter 4 Address Mapping 4-16 Chapter 5 Configuration Registers 5. 5.1 Configuration Registers Detailed Description The configuration registers set up and control the basic functionality of the entire TX4938. Refer to Section 5.2 for details of each configuration register. Also refer to sections mentioned in the description about each bit field. 5.1.1 Detecting G-Bus Timeout The G-bus is an internal bus of the TX4938. Access to each address on the G-Bus is completed upon a bus response from the accessed address. If an attempt is made to access an undefined physical address or if a hardware failure occurs, no bus response is made. If a bus response does not occur, the bus access will not be completed, leading to a system halt. To solve this problem, the TX4938 is provided with a G-Bus timeout detection function. This function forcibly stops bus access if no bus response occurs within the specified time. Setting the G-Bus Timeout Error Detection bit (CCFG.TOE) of the chip configuration register enables the G-Bus timeout detection function. If a bus response does not occur within the G-Bus clock (GBUSCLK) cycle specified in the G-Bus Timeout Time field (CCFG.GTOT), the G-Bus timeout detection function makes an error response to force the bus access to end. The accessed address is stored to the timeout error access address register (TOEA). If a timeout error is detected while the TX49/H3 core, as the bus master, is gaining write access to the G-Bus, the Write-Access Bus Error bit (CCFG.BEOW) is set. Enabling interrupt No. 1 in the interrupt controller makes it possible to post an interrupt to the TX49/H3 core. If a timeout error is detected while the TX49/H3 core is gaining read access to the bus, a bus error exception occurs in the TX49/H3 core. If a timeout error is detected while another G-Bus master (the PCI controller or DMA controller) is accessing the G-Bus, an error bit in that controller is set, which can be used to post an interrupt. Refer to the descriptions of each controller for details. If the TRST* signal is deasserted, it is assumed that an EJTAG probe is connected, so the G-Bus timeout detection feature is disabled. 5-1 Chapter 5 Configuration Registers 5.2 Registers Table 5.2.1 lists the configuration registers. Table 5.2.1 Configuration Register Mapping Offset Address 0xE000 0xE008 0xE010 0xE018 0xE020 0xE030 0xE048 0xE058 Size in Bits 64 64 64 64 64 64 64 64 Register Symbol CCFG REVID PCFG TOEA CLKCTR GARBC RAMP JMPADR Register Name Chip Configuration Register Chip Revision ID Register Pin Configuration Register Timeout Error Access Address Register Clock Control Register G-Bus Arbiter Control Register Register Address Mapping Register Jump Address Register Any address not defined in this table is reserved for future use. 5-2 Chapter 5 Configuration Registers 5.2.1 Chip Configuration Register (CCFG) 0xE000 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. 63 Reserved : Type : Initial value 47 Reserved 42 41 W DRST 48 40 WDREXEN 39 BCFG R DATA[15:8] 23 22 PCIMODE 32 R/W1C R/W 0 0 31 Reserved 27 26 25 24 21 PCI1-66 : Type : Initial value 17 16 BEOW R/W1C : Type 0 : Initial value 1 0 ACEHOLD 20 DIVMODE R ADDR[3:0] 3 Reserved 2 GTOT R/W 11 TINTDIS PCI66 R ~DATA[7] R/W 0 7 R ADDR[19] R/W 0 5 15 WR R/W 0 14 13 12 10 9 8 6 TOE PCIARB PCIDIVMODE R/W 0 Reserved PCI1DMD SYSSP R ADDR[14:13] ENDIAN ARMODE R/W R R/W 0 DATA[2] ADDR[11:10] R/W ADDR[16] R ADDR[12] R/W 0 R/W : Type 1 : Initial value Bit 63:42 41 Mnemonic ⎯ WDRST Field Name Reserved Watchdog Reset Status Description ⎯ Initial Value Read/Write ⎯ ⎯ R/W1C 0 Watch Dog Reset Status (Initial Value 0, RW1C) Indicates that a watchdog reset has occurred (refer to Section 12.3.6). Initialized when CGRESET* is asserted. 0 = No watchdog reset has occurred. 1 = A watchdog reset has occurred 0 Watch Dog Reset External Enable (Initial Value 0, R/W) Specifies whether to assert the WDRST* signal at a watchdog reset (refer to Section 12.3.6). Initialized when CGRESET* is asserted. 0 = Do not assert the WDRST* signal. 1 = Assert the WDRST* signal. 40 WDREXEN Watchdog Reset External Output R/W 39:32 BCFG Boot Configuration Set to 1 at a reset if the corresponding DATA[15:8] signal is high. Set to 0 at a reset if the corresponding DATA[15:8] signal is low. ⎯ DATA[15:8] R 31:27 26:25 ⎯ GTOT Reserved G-Bus Timeout Time ⎯ R/W ⎯ Specifies the number of G-Bus clock (GBUSCLK) cycles after 11 which a bus timeout error will occur on the internal bus (GBus) of the TX4938. 11 = 4096 GBUSCLK 10 = 2048 GBUSCLK 01 = 1024 GBUSCLK 00 = 512 GBUSCLK Indicates a value for indicating whether to enable the TX49/H3 internal timer interrupt (refer to Section 15.3.5). H: 0: The TX49/H3 internal timer interrupt is enabled. L: 1: The TX49/H3 internal timer interrupt is disabled. ~DATA[7] 24 TINTDIS Disable TX49/H3 Core Timer Interrupt R Figure 5.2.1 Chip Configuration Register (1/3) 5-3 Chapter 5 Configuration Registers Bit 23 Mnemonic Field Name PCI66 PCI 66MHz Mode Description Initial Value Read/Write R/W Used to inform the device connected to the PCI bus that a 66 0 MHz operation is to be performed. This bit is valid only when the PCI controller of the TX4938 is in host mode. (Refer to Section 10.3.8.) 0 = Do not perform a 66 MHz operation. 1 = Perform a 66 MHz operation. Indicates information about the operation mode of the TX4938 PCI controller. (Refer to Section 10.3.1.) L: 0: Satellite mode H: 1: Host mode Used to inform the ETHERC0 and ETHERC1 connected to the PCI1 bus that a 66 MHz operation is to be performed. 0 = Do not perform a 66 MHz operation (1/4 GBUSCLK). 1 = Perform a 66 MHz operation (1/2 GBUSCLK). ADDR[19] 22 PCIMODE PCI Operation Mode PCI1 66MHz Mode R 21 PCI1-66 0 R/W 20:17 DIVMODE CPUCLK Frequency Multiplication Factor Indicates information about the frequency multiplication factor of ADDR[3:0] the TX49/H3 core clock (CPUCLK) to the MASTERCLK. This field is set with a result of encoding an initial input value at ADDR[3:0]. The PLL incorporated in the TX4938 multiplies the MASTERCLK and supplies the resulting frequency to the TX49/H3 core. The value set in DIVMODE[3:0] is reflected in the EC field of the TX49/H3 core Config register. ADDR[3:0]:DIVMODE[3:0] HHHH: 0100: CPUCLK freq. = 2 × MASTERCLK freq. HHHL: 1111: CPUCLK freq. = 2.5 × MASTERCLK freq. HHLH: 0101: CPUCLK freq. = 3 × MASTERCLK freq. HHLL: 0110: CPUCLK freq. = 4 × MASTERCLK freq. LHHH: 1101: CPUCLK freq. = 4.5 x MASTERCLK freq. LHHL: ---- : Reserved LHLH: ---- : Reserved LHLL: ---- : Reserved HLHH: 0000: CPUCLK freq. = 8 × MASTERCLK freq. HLHL: 1011: CPUCLK freq. = 10 × MASTERCLK freq. HLLH: 0001: CPUCLK freq. = 12 × MASTERCLK freq. HLLL: 0010: CPUCLK freq. = 16 × MASTERCLK freq. LLHH: 1001: CPUCLK freq. = 18 × MASTERCLK freq. LLHL: ---- : Reserved LLLH: ---- : Reserved LLLL: ---- : Reserved R 16 BEOW Write-Access Indicates that a timeout error has occurred in the internal bus (G- 0 Bus Error Bus) during a write bus transaction of the TX49/H3 core. This bit corresponds to interrupt No. 1 in the interrupt controller. 0 = No error has occurred. 1 = An error has occurred. Watchdog Timer Mode Specifies how information will be reported in watchdog timer mode (refer to Section 12.3.6). 0 = Generate an NMI exception. 1 = Generate a watchdog reset. 0 R/W1C 15 WR R/W 14 TOE G-Bus Timeout Error Detection PCI Arbiter Selection Specifies whether to detect and report a bus timeout error in the 0 internal bus (G-Bus) of the TX4938. 0 = Do not detect or report a bus timeout error. 1 = Detect and report a bus timeout error. Indicates the PCI bus arbiter selection setting (refer to Section 10.3.12). L: 0 = External PCI bus arbiter H: 1 = Built-in PCI bus arbiter DATA[2] R/W 13 PCIARB R Figure 5.2.1 Chip Configuration Register (2/3) 5-4 Chapter 5 Configuration Registers Bit 12:10 Mnemonic Field Name Description Specifies the frequency division ratio of the PCI bus clock output (PCICLK[5:0]) frequency to the clock frequency (CPUCLK) of the TX49/H3 core. 001: PCICLK frequency = CPUCLK frequency ÷ 4 011: PCICLK frequency = CPUCLK frequency ÷ 4.5 101: PCICLK frequency = CPUCLK frequency ÷ 5 111: PCICLK frequency = CPUCLK frequency ÷ 5.5 000: PCICLK frequency = CPUCLK frequency ÷ 8 010: PCICLK frequency = CPUCLK frequency ÷ 9 100: PCICLK frequency = CPUCLK frequency ÷ 10 110: PCICLK frequency = CPUCLK frequency ÷ 11 ⎯ Internal PCI1CLK Frequency Division Ration L 0: PCI1CLK frequency = GBUSCLK frequency ÷ 2 H 1: PCI1CLK frequency = GBUSCLK frequency ÷ 4 Indicates the frequency division ratio of the SYSCLK frequency to the G-Bus clock frequency (GBUSCLK). LL: 00: SYSCLK frequency = GBUSCLK frequency ÷ 4 LH: 01: SYSCLK frequency = GBUSCLK frequency ÷ 3 HL: 10: SYSCLK frequency = GBUSCLK frequency ÷ 2 HH: 11: SYSCLK frequency = GBUSCLK frequency ⎯ Indicates the TX4938 endian mode setting. L: 0 = Little endian mode H: 1 = Big endian mode Selects an ACK*/READY signal operation mode for the external bus controller (refer to Section 7.3.6). 0 = ACK*/READY dynamic mode 1 = ACK*/READY static mode Specifies the hold time of an address relative to the external bus controller ACE* signal (refer to Section 7.3.4). 0 = Switch the address at the same time when the ACE* signal is deasserted. 1 = Switch the address one clock cycle after the ACE* signal is deasserted. Initial Value Read/Write ADDR[11:10] R/W ,0 PCIDIVMODE PCICLK Frequency Division Ratio 9 8 ⎯ PCI1DMD Reserved PCI1CLK Frequency Division Ratio SYSCLK frequency division ratio ⎯ ADDR[16] R ⎯ 7:6 SYSSP ADDR[14:13] R 5:3 2 ⎯ ENDIAN Reserved Endian ⎯ ADDR[12] R ⎯ 1 ARMODE ACK*/READY Mode 0 R/W 0 ACEHOLD ACE Hold 1 R/W Figure 5.2.1 Chip Configuration Register (3/3) 5-5 Chapter 5 Configuration Registers 5.2.2 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 PCODE R 0x4938 15 MJERREV R 0x0 12 11 MINEREV R 0x0 8 7 MJREV R 0x1 4 3 MINREV R 0x0 : Type : Initial value 0 : Type : Initial value 16 32 Chip Revision ID Register (REVID) 0xE008 48 Bit 63:32 31:16 15:12 11:8 7:4 3:0 Mnemonic ⎯ PCODE MJERREV MINEREV MJREV MINREV Field Name Reserved Product Code Major Extra Code Major Extra Code Major Revision Code Minor Revision Code Description ⎯ Indicates the product number. It is a fixed value. Indicates the major extra code. Indicates the minor extra code. Indicates the major revision of the product. Contact Toshiba technical staff for the latest information. Indicates the minor revision of the product. Contact Toshiba technical staff for the latest information. Initial Value Read/Write ⎯ 0x4938 0x0 0x0 0x1 0x0 R R R R R ⎯ Figure 5.2.2 Chip Revision ID Register 5-6 Chapter 5 Configuration Registers 5.2.3 Pin Configuration Register (PCFG) 0xE010 For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated. 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 ETH0_SEL ETH1_SEL ATA_SEL ISA_SEL SPI_SEL NDF_SEL Reserved DRVDATA DRVCB DRVDQM DRVADDR DRVCKE DRVRAS DRVCAS DRVWE DRVCS[3] ~ ~ DATA[3] DATA[6] R R R/W 0 45 R/W 0 44 R/W 0 R/W 0 41 R/W R/W R/W R/W R/W R/W R/W R/W ADDR[4] ADDR[4] ADDR[4] ADDR[5] ADDR[5] ADDR[5] ADDR[5] ADDR[5] ADDR[5] R/W : Type : Initial value 32 47 DRVCS[2:0] R/W ADDR[5] 31 30 40 DRVCKIN 39 Reserved 33 DRVCK[3:0] R/W ADDR[5] 29 28 27 SYSCLKEN BYPASSPLL R/W ADDR[5] R BYPASSPLL* : Type : Initial value 26 SDCLKEN[3:0] R/W 1111 10 9 SEL2 R 8 SEL1 R 23 22 SDCLKINEN 21 PCICLKEN[5:0] R/W 111111 16 Reserved SDCLKDLY R/W 00 R/W 1 R/W 0 7 DMASEL3 R/W 00 DMASEL2 R/W 00 : Type : Initial value 0 15 Reserved DMASEL1 R/W 00 DMASEL0 R/W 00 : Type : Initial value ADDR[9] ADDR[18] Bit 63 Mnemonic ETH0_SEL Field Name Description Initial Value Read/Write ~DATA[3] R Status of shared ETHERC0 Shared-pin status pin Indicates the status of shared pin. L : 1 : ETHERC0 selected H : 0 : ETHERC0 not selected Status of shared ETHERC1 Shared-pin status pin Indicates the status of shared pin. L : 1 : ETHERC1 selected H : 0 : ETHERC1 not selected Setting of shared pin ATA/ISA Shared-pin setting Specifies the status of shared pin. 1 : ATA/ISA selected 0 : ATA/ISA not selected ISA Shared-pin setting Specifies the status of shared pin. 1 : ISA selected 0 : ISA not selected SPI Shared-pin setting Specifies the status of shared pin. 1 : SPI selected 0 : SPI not selected 62 ETH1_SEL ~DATA[6] R 61 ATA_SEL 0 R/W 60 ISA_SEL Setting of shared pin 0 R/W 59 SPI_SEL Setting of shared pin 0 R/W 58 NDF_SEL Setting of shared pin 0 NDFMC Shared-pin setting Specifies the status of shared pin. When use NAND Flash IPL function, the initial value of this bit indicates 1 after booting. 1 : NDFMC selected 0 : NDFMC not selected ⎯ ⎯ R/W 57 ⎯ Reserved ⎯ Figure 5.2.3 Pin Configuration Register (1/3) 5-7 Chapter 5 Configuration Registers Bit 56 Mnemonic DRVDATA Field Name DATA Signal Control CB Signal Control Description Specifies the driving capability of the DATA[63:0] signals. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the CB[7:0]* signals. L : 0 = 8 mA H : 1 = 16 mA Note: CB[7:0]* share pins with PIO[15:8], E0TXD[3:0], E0RXD[3:0]. The driving capability of these pins are below. CB[7:0], E0TXD[3:0], E0RXD[3:0]: 8 mA or 16 mA PIO[15:8]: 8 mA only Initial Value Read/Write ADDR[4] R/W 55 DRVCB ADDR[4] R/W 54 DRVDQM DQM Signal Control ADDR Signal Control CKE Signal Control RAS Signal Control CAS Signal Control WE Signal Control SDRAM CS Signal Control Specifies the driving capability of the DQM[7:0]* signals. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the ADDR[19:0] signals. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the CKE signal. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the RAS* signal. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the CAS* signal. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the WE* signal. L : 0 = 8 mA H : 1 = 16 mA Specifies the driving capability of the SDCS[3:0]* signals. L : 0 = 8 mA H : 1 = 16 mA ADDR[4] R/W 53 DRVADDR ADDR[5] R/W 52 DRVCKE ADDR[5] R/W 51 DRVRAS ADDR[5] R/W 50 DRVCAS ADDR[5] R/W 49 DRVWE ADDR[5] R/W 48:45 DRVCS[3:0] ADDR[5] R/W 44:41 DRVCK[3:0] SDRAM SDCLK Specifies the driving capability of the SDCLK[3:0] signals. Signal Control L : 0 = 8 mA H : 1 = 16 mA SDRAM SDCLKIN Signal Control Reserved Bypass PLL Specifies the driving capability of the SDCLKIN signal. L : 0 = 8 mA H : 1 = 16 mA ⎯ Indicates information about whether a PLL for a circuit other than the PCI controller is on or off. L: 0 = The PLL is off. H: 1 = The PLL is on. ⎯ ADDR[5] R/W 40 DRVCKIN ADDR[5] R/W 39:33 32 ⎯ BYPASS PLL ⎯ BYPASSPLL* R ⎯ 31:30 29:28 ⎯ SDCLKDLY Reserved ⎯ 00 R/W ⎯ SDCLK Specifies the feedback delay for the SDCLK. This function is Feedback Delay for diagnosis purposes. Usually, set the bits to 00. 00 = Delay 1 (minimum delay) 10 = Delay 2 01 = Delay 3 11 = Delay 4 (maximum delay) SYSCLK Enable Specifies whether to output the SYSCLK. 1 = Clock output 0=H 27 SYSCLKEN 1 R/W Figure 5.2.3 Pin Configuration Register (2/3) 5-8 Chapter 5 Configuration Registers Bit Mnemonic Field Name Description Individually specifies whether to output each of SDCLK[3:0]. 1 = Clock output 0=H Bit 26 = SDCLK[3] Bit 25 = SDCLK[2] Bit 24 = SDCLK[1] Bit 23 = SDCLK[0] Specifies how SDCLK[3:0] should be fed back. This function is for diagnosis purposes. Usually, set this bit to 0. 0 = Use the SDCLKIN signal as a feedback clock. 1 = Perform feedback within the TX4938 (the SDCLKIN becomes an output signal). Initial Value Read/Write 1111 R/W 26:23 SDCLKEN [3:0] SDCLK Enable 22 SDCLKINEN SDCLKIN Enable 0 R/W 21:16 PCICLKEN [5:0] PCICLK Enable Individually specifies whether to output each of PCICLK[5:0]. 1 = Clock output 0=H Bit 21 = PCICLK[5] Bit 20 = PCICLK[4] Bit 19 = PCICLK[3] Bit 18 = PCICLK[2] Bit 17 = PCICLK[1] Bit 16 = PCICLK[0] 15:10 9 ⎯ SEL2 Reserved Shared-Pin Status 2 ⎯ 111111 R/W ⎯ R ⎯ DMAREQ[2], DMAACK[2], and PIO[4:2] share pins with the ADDR[9] AC-link interface signals. Indicates which function the shared pins are set to. L: 0 = The shared pins are set to DMAREQ[2], DMAACK[2], and PIO[4:2]. H: 1 = The shared pins are set to the AC-link interface signals. Indicates which function, PIO[15:8] or CB[7:0], the shared pins ADDR[18] are set to. L: 0 = The shared pins are set to PIO[15:8]. H: 1 = The shared pins are set to CB[7:0]. ⎯ Selects a DMA request used by DMA controller 0 channel 3. 0: DMAREQ[3] (external) 1: SIO channel 0 transmission (internal) Selects a DMA request used by DMA controller 0 channel 2. 0: DMAREQ[2] (external) 1: SIO channel 0 reception (internal) Selects a DMA request used by DMA controller 0 channel 1. 00: DMAREQ[1] (external) 01: SIO channel 1 transmission (internal) Selects a DMA request used by DMA controller 0 channel 0. 00: DMAREQ[0] (external) 01: SIO channel 1 reception (internal) 0 ⎯ 8 SEL1 Shared-Pin Status 1 R 7:4 3 ⎯ DMASEL3 Reserved DMA Request Select 3 DMA Request Select 2 DMA Request Select 1 DMA Request Select 0 ⎯ R/W 2 DMASEL2 0 R/W 1 DMASEL1 0 R/W 1:0 DMASEL0 0 R/W Figure 5.2.3 Pin Configuration Register (3/3) 5-9 Chapter 5 Configuration Registers 5.2.4 63 Reserved : Type : Initial value 47 Reserved 36 35 TOEA[35:32] R 0 31 TOEA[31:16] R 0 15 TOEA[15:0] R 0 : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 Timeout Error Access Address Register (TOEA) 0xE018 48 Bit 63:36 35:0 Mnemonic ⎯ TOEA Field Name Reserved Timeout Error Access Address Description ⎯ Holds the G-Bus address for the G-Bus cycle in which the latest G-Bus timeout error was detected. Initial Value Read/Write ⎯ 0x0_0000_00 R 00 ⎯ Figure 5.2.4 Timeout Error Access Address Register 5-10 Chapter 5 Configuration Registers 5.2.5 Clock Control Register (CLKCTR) 0xE020 Bit 32 and bits 15-0 are reset bits for the on-chip peripheral modules. To bring on-chip peripheral modules out of the reset state, the corresponding bits must be cleared by software. Before clearing them, wait at least 128 CPU clock cycles after they are set. 63 Reserved 50 49 0 48 NDFCKD R/W R/W : Type : Initial value 32 NDFRST 47 Reserved 34 33 0 R/W 0 R/W : Type 0 : Initial value 16 31 ETH1CKD ETH0CKD 26 25 24 23 22 21 1 20 19 18 17 SPICKD SRAMCKD PCI1CKD DMA1CKD ACLCKD PIOCKD DMACKD PCICCKD TM0CKD TM1CKD TM2CKD SIO0CKD SIO1CKD R/W 0 15 ETH1RST R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 1 5 1 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W : Type 0 : Initial value 0 ETH0RST SPIRST SRAMRST PCI1RST DMA1RST ACLRST PIORST DMA0RST PCICRST TM0RST TM1RST TM2RST SIO0RST SIO1RST R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W : Type 0 : Initial value Bit 63:50 49 48 Mnemonic ⎯ ⎯ NDFCKD Field Name Reserved ⎯ NDFMC Clock Disable Reserved ⎯ NDFMC Reset Always set this bit to 0. Always set this bit to 0. Description ⎯ Initial Value Read/Write ⎯ 0 0 R/W R/W ⎯ Controls clock pulses for the NAND Flash Memory controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. ⎯ 47:34 33 32 ⎯ ⎯ NDFRST ⎯ 0 0 R/W R/W ⎯ Resets the NAND Flash Memory controller. 0 = Normal state 1 = Reset Controls clock pulses for the ETHERC1 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the ETHERC0 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the SPI controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the internal SRAM controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for PCI controller 1. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the DMA controller 1. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 31 ETH1CKD ETHERC1 Clock Disable ETHERC0 Clock Disable SPIC Clock Disable SRAMC Clock Disable PCIC1 Clock Disable DMAC1 Clock Disable 0 R/W 30 ETH0CKD 0 R/W 29 SPICKD 0 R/W 28 SRAMCKD 0 R/W 27 PCIC1CKD 0 R/W 26 DMA1CKD 0 R/W Figure 5.2.5 Clock Control Register (1/3) 5-11 Chapter 5 Configuration Registers Bit 25 Mnemonic ACLCKD Field Name ACLC Clock Disable PIO Clock Disable DMAC0 Clock Disable PCIC Clock Disable ⎯ Timer 0 Clock Disable Timer 1 Clock Disable Timer 2 Clock Disable SIO0 Clock Disable SIO1 Clock Disable ETHERC1 Reset ETHERC0 Reset SPI Reset Description Controls clock pulses for the AC-link controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the parallel IO controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the DMA controller 0. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the PCI controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Always set this bit to 1. Controls clock pulses for the TMR0 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the TMR1 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the TMR2 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the SIO0 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Controls clock pulses for the SIO1 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. Resets the ETHER controller 1. 0 = Normal state 1 = Reset Resets the ETHER controller 0. 0 = Normal state 1 = Reset Resets the SPI controller. 0 = Normal state 1 = Reset Resets the internal SRAM controller. 0 = Normal state 1 = Reset Resets the PCI controller 1. 0 = Normal state 1 = Reset Resets the DMAC controller 1. 0 = Normal state 1 = Reset Resets the AC-link controller. 0 = Normal state 1 = Reset Note: Reset the AC-link controller when it is not asserting the interrupt and DMA request. Resets the parallel IO controller. 0 = Normal state 1 = Reset Initial Value Read/Write 0 R/W 24 PIOCKD 0 R/W 23 DMA0CKD 0 R/W 22 PCICKD 0 R/W 21 20 ⎯ TM0CKD 1 0 R/W R/W 19 TM1CKD 0 R/W 18 TM2CKD 0 R/W 17 SIO0CKD 0 R/W 16 SIO1CKD 0 R/W 15 ETHC1RST 0 R/W 14 ETHC0RST 0 R/W 13 SPIRST 0 R/W 12 SRAMRST SRAMC Reset 0 R/W 11 PCIC1RST PCIC1 Reset 1 R/W 10 DMA1RST DMAC1 Reset 0 R/W 9 ACLRST ACLC Reset 0 R/W 8 PIORST PIO Reset 0 R/W Figure 5.2.5 Clock Control Register (2/3) 5-12 Chapter 5 Configuration Registers Bit 7 Mnemonic DMARST Field Name DMAC Reset Description Resets the DMA controller. 0 = Normal state 1 = Reset Resets the PCI controller. 0 = Normal state 1 = Reset Always set this bit to 1. Resets the TMR0 controller. 0 = Normal state 1 = Reset Resets the TMR1 controller. 0 = Normal state 1 = Reset Resets the TMR2 controller. 0 = Normal state 1 = Reset Resets the SIO0 controller. 0 = Normal state 1 = Reset Resets the SIO1 controller. 0 = Normal state 1 = Reset Initial Value Read/Write 0 R/W 6 PCICRST PCIC Reset 0 R/W 5 4 ⎯ TM0RST ⎯ TMR0 Reset 1 0 R/W R/W 3 TM1RST TMR1 Reset 0 R/W 2 TM2RST TMR2 Reset 0 R/W 1 SIO0RST SIO0 Reset 0 R/W 0 SIO1RST SIO1 Reset 0 R/W Figure 5.2.5 Clock Control Register (3/3) 5-13 Chapter 5 Configuration Registers 5.2.6 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 ARBMD G-Bus Arbiter Control Register (GARBC) 0xE030 48 32 30 Reserved 16 R/W 1 15 Reserved : Type : Initial value 14 PRIORITY R/W 000_001_010_011_100 : Type : Initial value 0 Bit 63:32 31 Mnemonic ⎯ ARBMD Field Name Reserved Arbitration Mode Description ⎯ Initial Value Read/Write ⎯ R/W ⎯ 1 Specifies how to prioritize G-Bus arbitration. 0 = Fixed priority. The G-Bus arbitration priority conforms to the content of the PRIORITY field (bits [14:0]). 1 = Round-robin (in a round-robin fashion, PCIC0 > PDMAC > DMAC0 > DMAC1 > PCIC1) Note: Before accessing the PCI by DMAC, specify round-robin as the priority mode. If fixed-priority mode is selected, a dead lock is likely to occur in PCI bus access. ⎯ Specifies the priority when ARBMD (bit [16]) specifies fixedpriority mode. [14:12] = Bus master with the highest priority [11:9] = Bus master with the second highest priority [8:6] = Bus master with the third highest priority [5:3] = Bus master with the fourth highest priority [2:0] = Bus master with the fifth highest priority 000 = PCI controller 001 = PDMAC 010 = DMAC0 011 = DMAC1 100 = PCI controller 1 A priority of PCIC > PDMAC > DMAC0 > DMAC1 > PCIC1 is initially set up. ⎯ 000_001_01 0_011_100 30:15 14:0 ⎯ PRIORITY Reserved Arbitration Priority ⎯ R/W Figure 5.2.6 G-Bus Arbiter Control Register 5-14 Chapter 5 Configuration Registers 5.2.7 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 Reserved 20 19 RAMP[35:32] R/W 0xF 15 RAMP[31:16] R/W 0xFF1F : Type : Initial value 0 : Type : Initial value 16 32 Register Address Mapping Register (RAMP) 0xE048 48 Bit 63:20 19:0 Mnemonic ⎯ RAMP[35:16] Field Name Reserved Register Address Mapping Description ⎯ Initial Value Read/Write ⎯ R/W ⎯ This is a base address register for the TX4938 built-in 0xF_FF1F registers. It holds the high-order 20 bits of a register address. The default built-in register base address is 0xF_FF1F_0000. Even after the content of the base address register is changed, the default value can be used to reference the built-in registers. (Refer to "4.2 Register Mapp".) Figure 5.2.7 Register Address Mapping Register 5-15 Chapter 5 Configuration Registers 5.2.8 63 JMPADR[63:48] R/W 0xFFFF 47 JMPADR[47:32] R/W 0xFFFF 31 JMPADR[31:16] R/W 0xBFC0 15 JMPADR[15:0] R/W 0x0000 : Type : Initial value 20 19 RAMP[35:32] R/W 0xF 0 : Type : Initial value 16 : Type : Initial value 32 : Type : Initial value Jump Address Register (JMPADR) 0xE058 48 Bit 63:0 Mnemonic Field Name Description Initial Value Read/Write R/W JMPADR[63:0] Jump Address Register When NAND-IPL loads a user boot program to RAM from a 0xFFFF_FFFF NAND flash memory, the address of the loading place is set _BFC0_0000 as this register. It is used in case NAND-IPL controls an interrupt vector table henceforth. This register is a register used on a program of NAND-IPL, and a user must not operate it directly. At the time of operating it cannot be guaranteed of operation. Please Refer to “Chapter 18 NAND Flash Memory IPL” for Details. Figure 5.2.8 Jump Address Register 5-16 Chapter 6 Clocks 6. 6.1 Clocks TX4938 Clock Signals Figure 6.1.1 shows the configuration of TX4938 blocks and clock signals. Table 6.1.1 describes each clock signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is 266 MHz. Table 6.1.3 shows the relationship among different clock signals when the CPU clock frequency is 300 MHz. Table 6.1.4 shows the relationship among different clock signals when the CPU clock frequency is 333 MHz. PCICLKIN PLL2 ×1 PCICLKO SYSCLK 1/4 1/4.5 1/5 1/5.5 1/8 1/9 1/10 1/11 ADDR[11:10] (CCFG. PCIDIVMODE CPUCLK PCICLK[5:0] PCI device External device TCK DCLK CG EJTAG/DSU TX49/H3 core SDCLK[3:0] Data input latch SDRAMC EBUSC DMAC NDFMC ADDR[16] 1/2 SRAMC PCIC 1/1 1/2 1/3 1/4 ADDR[14:13] SDRAM SDCLKIN PLL1 ×2 ×2.5 ×3 ×4 x4.5 CLKGATE ADDR[3][1:0] MASTERCLK Oscillato ×4 ×1 ADDR[2] DMACKD NDFCKD SRAMCKD PCICKD PCIC1CKD ETH1CKD ETH0CKD PIOCKD TM2CKD TM1CKD TM0CKD SIO1CKD SIO0CKD ACLCKD SPICKD CLKCTR 1/2 GBUSCLK 1/4 IMBUSCLK PCIC1 ETHERC1 ETHERC0 IRC PIO TMR2 TMR1 TMR0 SIO1 SIO0 ACLC SPI E1TXCL E1RXCL E0TXCL E0RXCL CLKGATE TCLK SCLK BITCLK SPICLK TX4938 Figure 6.1.1 TX4938 Block and Clock Configuration 6-1 Chapter 6 Clocks Table 6.1.1 TX4938 Clock Signals (1/2) Clock Input/Output Description Master input clock for the TX4938. The TX4938 internal clock generator multiplies or divides MASTERCLK to generate internal clock pulses. ADDR[3:0] Related Related Registers Configuration Signals (Refer to Chapters 5 and 10.) (Refer to Section 3.2.) ⎯ ⎯ MASTERCLK Input CPUCLK Internal signal Clock supplied to the TX49/H3 core. PLL1 in the TX4938 generates CPUCLK by multiplying MASTERCLK. Boot configuration signals ADDR[3:0] can set the frequency ratio of CPUCLK to MASTERCLK. ADDR[3:0] HHHH = 2 times MASTERCLK HHHL = 2.5 times MASTERCLK HHLH = 3 times MASTERCLK HHLL = 4 times MASTERCLK LHHH = 4.5 times MASTERCLK HLHH = 8 times MASTERCLK HLHL = 10 times MASTERCLK HLLH = 12 times MASTERCLK HLLL = 16 times MASTERCLK LLHH = 18 times MASTERCLK Internal signal Clock supplied to peripheral blocks on the G-Bus. PLL1 in the TX4938 generates GBUSCLK by multiplying MASTERCLK. Boot configuration signal ADDR[2] can set the multiplier value. ADDR[2] L = 4 times MASTERCLK H = 1 times MASTERCLK Internal signal Clock supplied to peripheral modules on the IMBus. The frequency of IMBUSCLK is half that of GBUSCLK. Output CCFG.DIVMODE[3:0] GBUSCLK ADDR[2] CCFG.DIVMODE[2] IMBUSCLK ⎯ ⎯ SYSCLK System clock output from the TX4938. Used by ADDR[14:13] the devices connected to the external bus controller (EBUSC). Boot configuration signals ADDR[14:13] can set the frequency ratio of SYSCLK to GBUSCLK. ADDR[14:13] LL: GBUSCLK divided by 4 LH: GBUSCLK divided by 3 HL: GBUSCLK divided by 2 HH: GBUSCLK divided by 1 The SYSCLKEN bit of the PCFG register can disable the output of SYSCLK. Note: To use SYSCLK to access external devices, the SYSCLK rate must match the EBUSC channel operating rate. For details, refer to Section 7.3.8. Clock supplied to SDRAM. The frequency of SDCLK[3:0] is the same as that of GBUSCLK. The SDCLKEN[3:0] field of the PCFG register can disable the output of SDCLK[3:0] on a per bit basis. Reference clock used to latch input data signals from SDRAM. The clock output from SDCLK should be connected to SDCLKIN via a feedback line outside the TX4938. ⎯ CCFG.SYSSP PCFG.SYSCLKEN SDCLK[3:0] Output PCFG.DRVCK[3:0] PCFG.SDCLKEN[3:0] SDCLKIN Input/output ⎯ PCFG.DRVCKIN (PCFG.SDCLKDLY) (PCFG.SDCLKINEN) 6-2 Chapter 6 Clocks Table 6.1.1 TX4938 Clock Signals (2/2) Clock PCICLK[5:0] Input/Output Output Description Related Related Registers Configuration Signals (Refer to Chapters 5 (Refer to Section and 10.) 3.2.) CCFG.PCIDIVMODE PCFG.PCICLKEN[5:0] ADDR[11:10] Clock supplied to devices on the PCI bus. The PCICLKEN bit of the PCFG register can disable the output of PCICLK. The frequency depends on boot configuration signals ADDR[11:10] or the PCIDIVMODE field of the CCFG register. Initial Value of PCIDIVMODE[0] is 0. CCFG_PCIDIVMODE[2:0] =001: CPUCLK divided by 4 =011: CPUCLK divided by 4.5 =101: CPUCLK divided by 5 =111: CPUCLK divided by 5.5 =000: CPUCLK divided by 8 =010: CPUCLK divided by 9 =100: CPUCLK divided by 10 =110: CPUCLK divided by 11 Note: PCICLK[5:0] can supply clock pulses at 66 or 33 MHz when the CPUCLK frequency is set to 300. The setting is: 011, 010 PCICLKIN Input PCI bus clock. The built-in PCI controller of the TX4938 operates with this clock. Note: To achieve an accurate phase match with the external clock, PCICLK[5:0] or the PCI clock output from another PCI device must be supplied to PCICLKIN. ⎯ ⎯ PCICLKO Internal signal Clock supplied to the PCI controller. PCICLKO is generated by PLL2 based on PCICLKIN. PCICLKO has the same frequency and phase as those of PCICLKIN (input pin). Clock for serial EEPROM used to initially set the PIC configuration. Input clock for SIO. SCLK is shared by SIO0 and SIO1. Input clock for timers. TCLK is shared by TMR0, TMR1, and TMR2. Input clock for the AC-link controller. The pin is shared with the PIO[2] signal. Input clock for JTAG. Clock output for the real-time debugging system. Transmit clock Receive clock This clock is used for a data clock to or from an SPI slave device. ADDR[9] ⎯ ⎯ EEPROM_SK Output SCLK TCLK BITCLK TCK DCLK E0TXCLK, E1TXCLK E0RXCLK, E1RXCLK SPICLK PCI1CLK Input Input Input Input Output Input Input Output ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADDR[16] Internal signal Clock supplied to the PCI controller connected ETHER0 and ETHER1. This clock is generated by dividing GBUSCLK. Divide mode is specified by ADDR[16] and CCFG. CCFG.PCI1DMD 6-3 Chapter 6 Clocks Table 6.1.2 Relationship Among Different Clock Frequencies (for TMPR4938XBG-300, CPUCLK = 266 MHz) Master Clock (Input) and Boot Configured Settings Boot MASTERCLK (MHz) Internal Clock External Clock (Output) SYSCLK (MHz) PCICLK[5:0] (MHz) † CCFG Settings PCIDIVMODE[2:0] LLH (1/4) LHH (1/4.5) HLH (1/5) HHH (1/5.5) LLL (1/8) LHL (1/9) HLL (1/10) HHL (1/11) Configured Setting ADDR[3:0] CPUCLK (MHz) GBUSCLK (MHz) IMBUSCLK (MHz) SDCLK [3:0] (MHz) Boot Configured Settings PCIDIVMODE[2:0] HH (1/1) HL (1/2) LH (1/3) LL (1/4) 133 33.3 106.4 26.6 88.7 22.2 66.5 16.6 59.1 14.8 HHHH (×2.0) HLHH (×8.0) HHHL (×2.5) HLHL (×10.0) HHLH (×3.0) HLLH (×12.0) HHLL (×4.0) HLLL (×16.0) LHHH (×4.5) LLHH (×18.0) 133 106.4 266 88.7 66.5 59.1 66 53 44 33.2 29.6 133 106.4 88.7 66.5 59.1 133 106.4 88.7 66.5 59.1 66 53 44.3 33.3 35.5 26.6 59.1 53.2 48.4 33.3 29.6 26.6 24.2 44.3 29.6 22.2 66.5 33.3 22.2 16.6 29.6 19.7 14.8 † The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10]. Table 6.1.3 Relationship Among Different Clock Frequencies (for TMPR4938XBG-300, CPUCLK = 300 MHz) Master Clock (Input) and Boot Configured Settings Boot MASTERCLK (MHz) Internal Clock External Clock (Output) SYSCLK (MHz) PCICLK[5:0] (MHz) † CCFG Settings PCIDIVMODE[2:0] LLH (1/4) LHH (1/4.5) HLH (1/5) HHH (1/5.5) LLL (1/8) LHL (1/9) HLL (1/10) HHL (1/11) Configured Setting ADDR[3:0] CPUCLK (MHz) GBUSCLK (MHz) IMBUSCLK (MHz) SDCLK [3:0] (MHz) Boot Configured Settings PCIDIVMODE[2:0] HH (1/1) HL (1/2) LH (1/3) LL (1/4) 120 30 100 25 75 18 66 16 HHHH(x2.0) HLHH(x8.0) HHHL (x2.5) HLHL (x10.0) HHLH (x3.0) HLLH (x12.0) HHLL (x4.0) HLLL (x16.0) LHHH(x4.5) LLHH (x18.0) 120 300 100 75 66 60 50 37 33 120 100 75 66 120 100 75 66 60 50 37 33 40 33 25 22 30 25 - - - - - - - - 75 18 16 66 60 54 37 33 30 27 † The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10]. 6-4 Chapter 6 Clocks Table 6.1.4 Relationship Among Different Clock Frequencies (for TMPR4938XBG-333, CPUCLK = 333 MHz) Master Clock (Input) and Boot Configured Settings Boot MASTERCLK (MHz) Internal Clock External Clock (Output) SYSCLK (MHz) PCICLK[5:0] (MHz) † CCFG Settings PCIDIVMODE[2:0] LLH (1/4) LHH (1/4.5) HLH (1/5) HHH (1/5.5) LLL (1/8) LHL (1/9) HLL (1/10) HHL (1/11) Configured Setting ADDR[3:0] CPUCLK (MHz) GBUSCLK (MHz) IMBUSCLK (MHz) SDCLK [3:0] (MHz) Boot Configured Settings PCIDIVMODE[2:0] HH (1/1) HL (1/2) LH (1/3) LL (1/4) 133 33 111 27 83 20 74 18 HHHH(x2.0) HLHH(x8.0) HHHL (x2.5) HLHL (x10.0) HHLH (x3.0) HLLH (x12.0) HHLL (x4.0) HLLL (x16.0) LHHH(x4.5) LLHH (x18.0) 133 333 111 83 74 66 55 41 37 133 111 83 74 133 111 83 74 66 55 41 37 44 37 27 24 33 27 - - - - - - - - 83 20 18 74 66 60 41 38 33 30 † The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10]. 6.2 Power-Down Mode Halt Mode and Doze Mode The WAIT instruction causes the TX49/H3 core to enter either of the two low-power modes: Halt and Doze. The TX49/H3 can exit from Halt or Doze mode upon an interrupt exception. Ensure, therefore, that the TX49/H3 does not enter Halt or Doze mode when all interrupts are masked in the interrupt controller. The HALT bit of the TX49/H3 core Config register is used to select Halt or Doze mode. As the TX4938 does not use the snoop function of the TX49/H3 core, the bit should be set to select Halt mode, which achieves greater power reduction than Doze mode. 6.2.1 6.2.2 Power Reduction for Peripheral Modules When the system does not use the DMA controller, PCI controller, serial I/O controller, timers/counters, parallel I/O controller, or AC-link controller, it can stop the input clock for that module to reduce power dissipation. The clock control register (CLKCTR) is used to control whether to turn each clock on or off. The module should be reset before its clock can be turned on or off. This reset is performed using the reset bit for the specific module, provided in the clock control register. The reset also initializes the registers of the module, thus requiring subsequent setup of necessary register values and other configurations. Refer to Section 5.2.5, "Clock Control Register" for detail of the clock control register (CLKCTR). 6-5 Chapter 6 Clocks 6.3 Power-On Sequence Vdd MASTERCLK RESET* CGRESET* PLL settling time PLL1 output CPUCLK GBUSCLK PCICLK PCICLKIN (when PCICLK is fed back) PLL settling time PLL2 output PCICLKO (clock for TX4938 PCI controller) Figure 6.3.1 Power-On Sequence 6-6 Chapter 7 External Bus Controller 7. 7.1 External Bus Controller Features The External Bus Controller is used for accessing ROM, SRAM memory, and I/O peripherals. The features of this bus are described below. (1) 8 independent channels (2) Supports access to ROM (mask ROM, page mode ROM, EPROM, EEPROM), SRAM, flash memory, and I/O peripherals. (3) Selectable data bus width of 8-bit, 16-bit, 32-bit for each channel (4) Selectable full-speed, 1/2 speed, 1/3 speed, 1/4 speed for each channel (5) Programmable timing for each channel. Programmable setup and hold time of address, chip enable, write enable, and output enable signals. (6) Supports memory sizes from 1 MB to 1 GB for devices with a 32-bit data bus. Supports memory sizes from 1 MB to 512 MB for devices with a 16-bit data bus. Supports memory sizes from 1 MB to 256 MB for devices with an 8-bit data bus. (7) Supports special DMAC Burst access (address decrement/fixed). (8) Supports critical word first access of the TX49/H3 core. (9) Supports page mode memory. Supports 4-, 8-, and 16-page size. (10) Supports the External Acknowledge Signal (ACK*) and External Ready Signal modes. (11) Channel 0 can be used as Boot memory. Boot settings can be made from the following selections: • • • • Data bus width: 8-bit, 16-bit, 32-bit ACK* output or ACK* input BWE pin (byte enable or byte Write enable) Boot channel clock frequency (12) Supports the ISA I/O area access. (13) Supports ATA PIO mode. 7-1 Chapter 7 External Bus Controller 7.2 Block Diagram G-Bus External Bus Controller (EBUSC) G-Bus I/F Channel Control Register CH0 Address Decoder CE*[7:0] Timing Control OE* SWE* BWE*[3:0]/BE*[3:0] ACK*/READY ACE* Channel Control Register CH7 Address Decoder EBIF CONTROL ADDR[19:0] EBIF DATA[31:0] BUSSPRT* IOR* IOW * CS[1:0]* ACEHOLD Boot Options Register Address Decoder Host I/F Timing Control CCFG.SYSSP CG SYSCLK Figure 7.2.1 Block Diagram of External Bus Controller 7-2 Chapter 7 External Bus Controller 7.3 Detailed Explanation External Bus Control Register The External Bus Controller (EBUSC) has eight channels. This register contains one Channel Control Register (EBCCRn) for each channel, and all settings can be made independently for each channel. Either Word or Double-word access is possible for a Control Register. However, be sure to make any Enable settings to EBCCRn.ME last when using Word access and dividing register settings into two accesses. If EBCCRn.ME is enabled before setting the base address, then unintended memory access may result. 7.3.1 7-3 Chapter 7 External Bus Controller 7.3.2 Global/Boot-up Options In addition to the settings made separately for each channel, the Channel Control Registers can also use global options that make settings common to all channels. External Bus Controller Channel 0 can be used as a Boot memory channel. Channel 0 is set by the external pins (Boot pins) during reset. These settings are summarized below in Table 7.3.1. (Please refer to “3.2 Boot Configuration” and “5.2.1 Chip Configuration Register” for more information.) Table 7.3.1 Global/Boot-up Options Pin Name ⎯ Set Register CCFG.ARMODE Explanation Selects the operation mode of the ACK*/READY signal. 0 = ACK*/READY Dynamic mode (Default) 1 = ACK*/READY Static mode Sets the address hold time relative to the ACE* signal. 0: Address changes simultaneous to deassertion of the ACE* signal. 1: Address changes 1 clock cycle after deassertion of the ACE* signal. (Default) Specifies the division ratio of the SYSCLK output relative to the internal bus clock (GBUSCLK). 00: 1/4 speed (1/4 the GBUSCLK frequency) 01: 1/3 speed (1/3 the GBUSCLK frequency) 10: 1/2 speed (1/2 the GBUSCLK frequency) 11: Full speed (same frequency as the GBUSCLK frequency) Specifies whether to enable or disable Channel 0. 0: Disable this channel as a Boot channel. 1: Enable this channel as a Boot channel. Specifies the operation speed of Channel 0. 00: 1/4 Speed mode 01: 1/3 Speed mode 10: 1/2 Speed mode 11: Full Speed mode When accessing Channel 0, specifies whether to use the BWE[3:0] signal as a Byte Enable signal (BE[3:0]) or to use it as a Byte Write Enable signal (BWE[3:0]). 0: Byte Enable mode 1: Byte Write Enable mode Specifies the Channel 0 access mode. 0: Normal mode (DATA[4] = H) 1: External ACK mode (DATA[4] = L) Specifies the memory bus width of Channel 0. 00: Reserved 01: 32-bit width 10: 16-bit width 11: 8-bit width ⎯ CCFG.ACEHOLD ADDR[14:13] CCFG.SYSSP ADDR[8] EBCCR0.ME ADDR[7:6] EBCCR0.SP DATA[5] EBCCR0.BC DATA[4] EBCCR0.WT[0] DATA[1:0] EBCCR0.BSZ 7-4 Chapter 7 External Bus Controller 7.3.3 Address Mapping Each of the eight channels can use the Base Address field (EBCCRn.BA[35:20]) and the Channel Size field (EBCCRn.CS[3:0]) of the External Bus Channel Control Register to map to any physical address. A channel is selected when the following equation becomes True. paddr[35:20] & !Mask[35:20] == BA[35:20] & !Mask[35:20] In the above equation, paddr represents the accessed physical address, Mask[35:20] represents the address mask value selected from Table 7.3.2 from the Channel Size field value, the ampersand (&) represents the AND operation, and the exclamation mark (!) represents the Logical NOT for each bit. Operation is indeterminate when either multiple channels are selected simultaneously, or a channel is selected simultaneously with the SDRAM Controller or PCI Controller. Table 7.3.2 Address Mask CS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Channel Size 1 MB 2 MB 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB 256 MB 512 MB 1 GB Reserved Reserved Reserved Reserved Reserved Address Mask[35:20] 0000_0000_0000_0000 0000_0000_0000_0001 0000_0000_0000_0011 0000_0000_0000_0111 0000_0000_0000_1111 0000_0000_0001_1111 0000_0000_0011_1111 0000_0000_0111_1111 0000_0000_1111_1111 0000_0001_1111_1111 0000_0011_1111_1111 Reserved Reserved Reserved Reserved Reserved 7-5 Chapter 7 External Bus Controller 7.3.4 External Address Output The maximum memory space size for each channel is 1 GB (230B). Addresses are output by dividing the 20-bit ADDR[19:0] signal into two parts: the upper address and the lower address. The address bit output to each bit of the ADDR[19:0] signal changes according to the setting of the channel data bus width. (See “7.3.5 Data Bus Size” for more information.) It is possible for an external device to latch the upper eight address bits using the ACE* signal. Either the ACE* signal itself can be used as a Latch Enable signal or the upper address can be latched at the rise of SYSCLK when the ACE* signal is being asserted. The ADDR signal output is held for one clock cycle after the ACE* signal rise when the CCFG.ACEHOLD bit is set (default). (See Figure 7.5.1.) The ADDR signal output is not held when the CCFG.ACEHOLD bit is cleared. This hold time setting is applied globally to all channels. The ACE* signal of the upper address is always asserted at the first external bus access cycle after Reset. In all subsequent external bus access cycles, the bit mapping of the upper address output to ADDR[19:12] is compared to the bit mapping of the upper address output to ADDR[19:12] previously. The upper address is output and the ACE* signal is asserted only if the compared results do not match. As indicated below in Table 7.3.3, in the case of channel sizes that do not use the upper address latched by the ACE* signal, with the exception of the first cycle after reset, the upper address is not output and the ACE* signal is not asserted. Table 7.3.3 Relationship Between the Upper Address Output and the Channel Size (CS) CS Bus Width 32 bits 16 bits 8 bits ⎯ ⎯ ⎯ 1 MB ⎯ ⎯ √ 2 MB ⎯ √ √ 4 MB 8 MB or more √ √ √ √: The upper address output changes when the upper address changes. ⎯: The upper address output does not change (with the exception of the first cycle after reset.) 7-6 Chapter 7 External Bus Controller 7.3.5 Data Bus Size The External Bus Controller supports devices with a data bus width of 8 bits, 16 bits, and 32 bits. The data bus width is selected using the BSZ field of the Channel Control Register (EBCCRn). The address bits output to each bit of the ADDR[19:0] signal change according to the mode. When access of a size larger than the data bus width is performed, the dynamic bus sizing function is used to execute multiple bus access cycles in order from the lower address. 7.3.5.1 32-bit Bus Width Mode DATA[31:0] becomes valid. Bits [21:2] of the physical address are output to ADDR[19:0]. The internal address bits [29:22], which are the upper address, are multiplexed to external ADDR[19:12]. The maximum memory size is 1 GB. Table 7.3.4 Address Output Bit Correspondence in the 32-bit Mode ADDR Bit Upper Address Lower Address 19 18 17 16 15 14 13 12 11 10 9 29 28 21 20 27 19 26 18 25 24 17 16 23 22 15 14 13 12 8 7 9 6 8 5 7 4 6 3 5 2 4 1 3 0 2 11 10 When a Single cycle that accesses 1-Byte/1 half-word/1-word data is executed, 32-bit access is executed only once on the external bus. 32-bit access is executed twice when performing 1double-word access. When a Burst cycle is executed, two 32-bit cycles are executed for each Burst access when the Bus cycle tries to request a byte combination other than double-word data. 7.3.5.2 16-bit Bus Width Mode DATA[15:0] becomes valid. Bits [20:1] of the physical address are output to ADDR[19:0]. The internal address bits [28:21], which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the address is shifted up one bit relative to the 32-bit bus mode when output. As a result, the maximum memory size of the 16-bit bus mode is 512 MB. Table 7.3.5 Address Output Bit Correspondence in the 16-bit Mode ADDR Bit Upper Address Lower Address 19 18 17 16 15 14 13 12 11 10 9 28 27 26 20 19 18 25 17 24 16 23 15 22 14 21 13 12 11 10 8 9 7 8 6 7 5 6 4 5 3 4 2 3 1 2 0 1 When a Single cycle that accesses 1-Byte or 1 half-word data is executed, 16-bit access is executed only once on the external bus. 16-bit access is executed twice when performing 1-word access. 16-bit access is executed four times when performing 1-double-word access. When a Burst cycle is executed, four 16-bit cycles are executed for each Burst access when the Bus cycle tries to request a byte combination other than double-word data. 7-7 Chapter 7 External Bus Controller 7.3.5.3 8-bit Bus Width Mode DATA[7:0] becomes valid. Bits [19:0] of the physical address are output to ADDR[19:0]. The internal address bits [27:20], which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the address is shifted up two bits or more relative to the 32-bit bus mode when output. As a result, the maximum memory size of the 8-bit bus mode is 256 MB. Table 7.3.6 Address Output Bit Correspondence in the 8-bit Mode ADDR Bit Upper Address Lower Address 19 18 17 16 15 14 13 12 11 10 9 27 26 19 18 25 17 24 16 23 22 15 14 21 20 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 When a Single cycle that accesses 1-Byte data is executed, 8-bit access is executed only once on the external bus. 8-bit access is executed twice when performing 1-half-word access. 8-bit access is executed four times when performing 1-word access. 8-bit access is executed eight times when performing 1-double-word access. When a Burst cycle is executed, eight 8-bit cycles are executed for each Burst access when the Bus cycle tries to request a byte combination other than doubleword data. 7-8 Chapter 7 External Bus Controller 7.3.6 Access Mode The following four modes are available as controller access modes. These modes can be set separately for each channel. • • • • Normal mode Page mode External ACK mode Ready mode Depending on the combination of modes in each channel, either of two modes in which the ACK*/Ready signal operates differently (ACK*/Ready Dynamic mode, ACK*/Ready Static mode) is selected by the ACK*/Ready Mode bit (CCFG.ARMODE) of the Chip Configuration Register. The mode selected is applied globally to all channels. (1) ACK*/READY Dynamic mode (CCFG.ARMODE = 0) This mode is selected in the initial state. The ACK*/Ready signal automatically switches to either input or output according to the setting of each channel. When in the Normal mode or the Page mode, the ACK*/Ready signal is an output signal, and the internally generated ACK* signal is output. When in the External ACK* or Ready mode, the ACK*/Ready signal becomes an input signal. The ACK*/Ready signal outputs High if there is no access to the External Bus Controller. However, this signal may output Low during access to SDRAM. Please refer to the timing diagrams (Figure 7.5.23 and Figure 7.5.24) and be careful to avoid conflicts when switching from output to input. (2) ACK*/Ready Static mode (CCFG.ARMODE = 0) The internally generated ACK* signal is not output when in either the Normal mode or Page mode. Therefore, the ACK*/Ready signal will not become an output in any channel. Access using Burst transfer by the internal bus (G-Bus) is supported when in a mode other than the Ready mode. However, the Ready mode is not supported. Table 7.3.7 Operation Mode PM RDY 0 1 !0 0 1 0 ACK*/Ready Static Mode !0 0 1 0 1 PWT:WT ! 3f 3f ⎯ ⎯ ⎯ ! 3f 3f ⎯ ⎯ ⎯ Mode Normal External ACK* READY Page Reserved Normal External ACK* READY Page Reserved ACK*/READY Pin State Output Input Input Output ⎯ Hi-Z Input Input Hi-Z ⎯ Access End Timing State Internally Generated ACK* ACK* Input Ready Input Internally Generated ACK* ⎯ Internally Generated ACK* ACK* Input Ready Input Internally Generated ACK* ⎯ G-Bus Burst Access √ √ ⎯ √ ⎯ √ √ ⎯ √ ⎯ 0 ACK*/Ready Dynamic Mode 7-9 Chapter 7 External Bus Controller 7.3.6.1 Normal Mode When in this mode, the ACK*/Ready signal becomes an ACK* output when it is in the ACK*/Ready Dynamic mode. The ACK*/Ready signal becomes High-Z when it is in the ACK*/Ready Static mode. Wait cycles are inserted according to the EBCCRn.PWT and EBCCRn.WT value at the access cycle. The Wait cycle count is 0 – 0x3e (becomes the external ACK mode when set to EBCCRn.PWT: WT = 0x3f). SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Output) EBCCRn.PWT:WT=3 expresses indeterminate values EBCCRn.SHWT=0 Figure 7.3.1 Normal Mode 7.3.6.2 External ACK Mode When in this mode, the ACK*/READY pin becomes ACK* input, and the cycle is ended by the ACK* signal from an external device. ACK* input is internally synchronized. Refer to Section “7.3.7.4 ACK* Input Timing” for more information regarding timing. SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY(Input) represents indeterminate values. EBCCRn.SHWT=0 Figure 7.3.2 External ACK Mode 7-10 Chapter 7 External Bus Controller 7.3.6.3 Ready Mode When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by Ready input from an external device. Ready input is internally synchronized. See Section “7.3.7.5 Ready Input Timing” for more information regarding the operation timing. When the Wait cycle count specified by EBCCREBCCRn.PWT:WT elapses, a check is performed to see whether the Ready signal was asserted. Since EBCCRn.WT[0] is used to indicate the ACK*/ Ready Static/Dynamic mode, it is not used for setting the Wait cycle count. Therefore, the Wait cycle count that can be set by the Ready mode is 0, 2, 4, 6, …, 62. When the number of wait cycles is 0, READY check is started in 1 cycle after asserting the CE* signal. When the number of wait cycles is other than zero, after waiting only for the specified number of cycles, READY check is started. The Ready mode does not support Burst access by the internal bus. SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Start Ready Check Figure 7.3.3 Ready Mode 7-11 Chapter 7 External Bus Controller 7.3.6.4 Page Mode When in this mode, the ACK*/Ready pin becomes ACK* output when it is in the Dynamic mode. When it is in the ACK*/Ready Static mode, the ACK*/Ready signal becomes HiZ. Wait cycles are inserted into the access cycle according to the values of EBCCRn.PWT and EBCCRn.WT. The Single access protocol in Page mode is identical to that of Normal mode, except the number of wait cycles inserted. The Wait cycle count in the first access cycle of Single access or Burst access is determined by the EBCCRn.WT value. The Wait cycle count can be set from 0 to 15. The Wait cycle count of subsequent Burst cycles is determined by the EBCCRn.PWT value. The Wait cycle count can be set from 0 to 3. SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Output) EBCCRn.WT=2 EBCCRn.PWT=1 EBCCRn.PWT=1 EBCCRn.PWT=1 Figure 7.3.4 Page Mode (Burst Access) 7-12 Chapter 7 External Bus Controller 7.3.7 Access Timing SHWT Option The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel Control Register is a value other than “0.” This option inserts Setup cycles and Hold cycles between signals as follows. Setup cycle: CE* from ADDR, OE* from CE*, BWE* from CE*, SWE* from CE*. Hold cycle: ADDR from CE*, CE* from OE*, CE* from BWE*, CE* from SWE* This option is used for I/O devices that are generally slow. All Setup cycles and Hold cycles will be identical, so each cycle cannot be set individually. The SHWT mode cannot be used by the Page mode. The SHWT mode can be used by all other modes, but there is one restriction: the internal bus cannot use Burst access. The hold cycles of DATA relative to SWE* and BWE* are fixed at one clock cycle, regardless of the settings of the SHWT option. When the SHWT option is disabled, the setup cycles of SEW* and BWE* relative to CE*, and the hold cycles of OE*, SEW* and BWE* relative to CE* are one clock cycle. 7.3.7.1 SYSCLK CE*/BE* ADDR [19:0] OE* SWE*/BWE* DATA [31:0] ACK*/READY (Output) EBCCRn.PWT:WT=0 EBCCRn.SHWT=0 Figure 7.3.5 SWHT Disable (Normal Mode, Single Read/Write Cycle) 7-13 Chapter 7 External Bus Controller SYSCLK CE*/BE* ADDR [19:0] OE* SWE*/BWE* DATA [31:0] ACK*/READY (Output) EBCCRn.PWT:WT=0 EBCCRn.SHWT=1 Figure 7.3.6 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle) 7.3.7.2 ACK*/READY Input/Output Switching Timing When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When in the ACK*/Ready Dynamic mode, the ACK*/Ready signal is an input signal when in the External ACK mode or the Ready mode, but is an output signal in all other modes. During External ACK mode or Ready mode access, the ACK* signal becomes High-Z at the cycle where the CE* signal is asserted. At the end of the access cycle, the ACK* signal is output (driven) again one clock cycle after the CE* signal is deasserted (see Figure 7.3.3 and Figure 7.5.23). 7-14 Chapter 7 External Bus Controller 7.3.7.3 ACK* Output Timing (Normal Mode, Page Mode) When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK* signal becomes an output signal and is asserted for one clock cycle to send notification to the external device of the data Read and data Write timing. During the Read cycle, the data is latched at the rise of the next clock cycle after when the ACK* signal is asserted. (See Figure 7.3.7 ACK* Output Timing (Single Read Cycle)). During the Write cycle, SWE*/BWE* is deasserted at the next clock cycle after when the ACK* signal is deasserted, and the data is held for one more clock cycle after that. (See Figure 7.3.8 ACK* Output Timing (Single Write Cycle)). SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Output) 1 clock Data is latched EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Figure 7.3.7 ACK* Output Timing (Single Read Cycle) SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Output) 2 clocks EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Figure 7.3.8 ACK* Output Timing (Single Write Cycle) 7-15 Chapter 7 External Bus Controller 7.3.7.4 ACK* Input Timing (External ACK Mode) The ACK* signal becomes an input signal when in the external ACK mode. During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is acknowledged (Figure 7.3.9 ACK* Input Timing (Single Read Cycle)). During a Write cycle, assertion of the ACK* signal is acknowledged, SWE*/BWE* is deasserted three clock cycles later, then data is held for one clock cycle after that (Figure 7.3.10 ACK* Input Timing (Single Write Cycle). The ACK* input signal is internally synchronized. Due to internal State Machine restrictions, ACK* cannot be acknowledged consecutively on consecutive clock cycles. External devices can assert ACK* across multiple clock cycles under the following conditions. • • During Single access, the ACK* signal can be asserted before the end of the cycle during which CE* is dasserted. During Burst access, it is possible to assert the ACK* signal for up to three clock cycles during Reads and for up to five clock cycles during Writes. If the ACK* signal is asserted for a period longer than this, it will be acknowledged as the next valid ACK* signal. SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) 2 clocks Acknowledge ACK* Latch Data EBCCRn.SHWT=0 Figure 7.3.9 ACK* Input Timing (Single Read Cycle) SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Input) 4 clocks 3 clocks Acknowledge ACK* EBCCRn.SHWT=0 Figure 7.3.10 ACK* Input Timing (Single Write Cycle) 7-16 Chapter 7 External Bus Controller SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) 2 clocks Acknowledge ACK* Latch Data 2 clocks Acknowledge ACK* Latch Data EBCCRn.SHWT=0 Figure 7.3.11 ACK* Input Timing (Burst Read Cycle) SYSCLK CE* ADDR [19:0] 3 clocks SWE*/BWE* DATA [31:0] ACK*/READY (Input) 4 clocks 4 clocks 3 clocks Acknowledge ACK* Acknowledge ACK* EBCCRn.SHWT=0 Figure 7.3.12 ACK* Input Timing (Burst Write Cycle) 7-17 Chapter 7 External Bus Controller 7.3.7.5 Ready Input Timing The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input timing is the same as the ACK* input timing explained in 7.3.7.4 ACK* Input Timing (External ACK Mode) with the two following exceptions. • • Ready must be a High Active signal. When in the Ready mode, the Wait cycle count specified by EBCCRn.PWT:WT must be inserted in order to delay the Ready signal check (see 7.3.6.3 Ready Mode). SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) 2 clocks Acknowledge Ready Latch Data EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) 2 clocks Start Ready Check Acknowledge Ready Latch Data EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Figure 7.3.13 Ready Input Timing (Read Cycle) 7-18 Chapter 7 External Bus Controller SYSCLK CE* ADDR [19:0] 3 clocks SWE*/BWE* DATA [31:0] ACK*/READY (Input) 4 clocks Acknowledge Ready EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Input) 4 clocks 3 clocks Start Ready Check Acknowledge Ready EBCCRn.PWT:WT=2 EBCCRn.SHWT=0 Figure 7.3.14 Ready Input Timing (Write Cycle) 7.3.8 Clock Options External devices connected to the external bus can use the SYSCLK signal as the clock. The SYSCLK signal clock frequency can be set to one of the following divisions of the internal bus clock (GBUSCLK): 1/1, 1/2, 1/3, 1/4. The ADDR[14:13] signal is used to set this frequency during reset, and the setting is reflected in the SYSCLK Division Ratio field (CCFG.SYSSP) of the Chip Configuration Register. The operation reference clock frequency can be set to one of the following divisions of the internal bus clock (GBUSCLK) for each channel independent of the SYSCLK signal clock frequency: 1/1, 1/2, 1/3, 1/4. The external signal of the External Bus Controller operates synchronous to this operation clock. The Bus Speed field (EBCCRn.SP) of the External Bus Channel Control Register sets this frequency. Please set the same value as CCFG.SYSSP to EBCCRn.SP when the external device uses the SYSCLK signal. If these two values do not match, then the channel, the operation reference clock, and the SYSCLK signal will no longer be synchronous and will not operate properly. 7-19 Chapter 7 External Bus Controller 7.3.9 ISA /ATA Mode TMPR4938 supports ISA I/O space access and ATA PIO transfer mode. Since the pins used in ISA/ATA mode are multiplexed pins, select ISA/ATA before use of these pins. Since the signal of CE* is not used in this mode, when ETHER1 is chosen, this mode can be used by channels 5, 6 and 7. (Refer to “5.2.3 Pin Configuration Register”.) 7.3.9.1 Address space In the channel set to EBCCRn.ISA=01, 64 kbyte from the start address of the channel is used for the ISA I/O space. (Refer to Figure 7.3.15). When access to the ISA I/O space is performed, IOR* and IOW* control signals are valid, and OE*, SWE* and CE* are invalid. Other control signals are usable, that is the same as the case other than the ISA/ATA mode. In the channel set to EBCCRn.ISA=11, 64 kbyte from the start address of the channel is used for ISA I/O space, and successive 128 kbyte is used for ATA space (64 kbyte each for CS[0]* and CS[1]*). (Refer to Figure 7.3.15). When access to the ATA space is performed, the IOR*, IOW* and CS* control signals are valid, and OE*, SWE* and CE* are invalid. Other control signals are usable, that is the same as the case other than the ISA/ATA mode. In general, the space from address off set 0x30000 (0x10000 in the ISA mode) to the channel end address becomes the channel space. Access to this space is the same as the case other than the ISA/ATA mode. (OE*, SWE* and CE* control signals are valid, and IOR*, IOW* and CS* are invalid). Channel End Address Normal Channel Space 0x30000 ATA CS[1]* Space (64Kbyte) 0x20000 CS[1]* Register Area ATA CS[0]* Space (64Kbyte) CS[0]* Register Area 0x10000 ISA Space (64Kbyte) 0x00000 Offset Address W hen EBCCRn.ISA is set to 01, the ATA CS[0]* and CS[1]* spaces become the normal channel space. See Table 7.3.8 for the mapping of the ATA CS[1]* and CS[0]* register areas. Channel Start Address Figure 7.3.15 Physical Address Mapping of the ISA/ATA Spaces 7-20 Chapter 7 External Bus Controller 7.3.9.2 Usage Considerations To use ISA and ATA modules in READY, their ICCHRDY or IORDY pin should be connected to the ACK*/READY pin of the TX4938. The SHWT option allows users to adjust the setup and hold timing of IOR* and IOW* relative to ADDR. When the READY mode and SHWT option are used, the internal bus burst accesses are prohibited. Although the ISA and ATA signals are 5-volt signals, the TX4938 is not 5-volt-tolerant. For voltage-level conversion, bus switches such as BUSSW and LCX245 must be inserted between ISA busses according to the modules used. 7.3.9.3 Usage Examples (1) 8-bit ISA module Following is a programming example to use an 8-bit ISA module: • • • • • ISA mode (EBCCRn.ISA=01) 8-bit bus (EBCCRn.BSZ=11) READY mode (EBCCRn.RDY=1, EBCCRn.PM=00) Channel enable (EBCCRn.ME=1) ISA select (PCFG.ISA_SEL=1) Program the number of wait cycles, the SHWT option and the bus speed according to the ISA module used. Figure 7.3.16 shows an example of connecting an 8-bit ISA module to the TX4938. TX4938 ADDR[15:0] DATA[7:0] IOR* IOW * ACK*/READY 16 8 ISA-Module SA[15:0] SD[7:0] IOR* IOW * IOCHRDY AEN Figure 7.3.16 An Example of Connecting an 8-Bit ISA Module 7-21 Chapter 7 External Bus Controller (2) 16-bit ISA module Following is a programming example to use a 16-bit ISA module: • • • • • ISA mode (EBCCRn.ISA=01) 16-bit bus (EBCCRn.BSZ=10) READY mode (EBCCRn.RDY=1, EBCCRn.PM=00) Channel enable (EBCCRn.ME=1) ISA select (PCFG.ISA_SEL=1) Program the number of wait cycles, the SHWT option and the bus speed according to the ISA module used. Figure 7.3.17 shows an example of connecting a 16-bit ISA module to the TX4938. TX4938 ADDR[15:0] DATA[15:0] IOR* IOW * ACK*/READY 16 16 ISA-Module SA[15:0] SD[15:0] IOR* IOW * IOCHRDY AEN Figure 7.3.17 An Example of Connecting an 16-Bit ISA Module With the EBUSC configured for a 16-bit bus, bits [16:1] of physical addresses are driven out from ADDR[15:0]. Thus, the address pins must be connected, as shown in Figure 7.3.17. To access halfwords in the ISA module with even addresses (*0, *2, *4, *6, …), the TX4938 must provide physical addresses with two low-order bits cleared (*0, *4, *8, *C, …). Therefore, the accessible ISA address space is limited to a maximum of 32 kbytes between 0x0000 and 0x7fff. For byte accesses, the valid byte lane in the data bus differs, depending on whether the TX4938 is configured for big-endian or little-endian byte ordering. Software is responsible for address conversion for a specific endianness, as shown in Table 7.3.8. 7-22 Chapter 7 External Bus Controller (3) ATA Following is a programming example to use an ATA module: • • • • • ISA/ATA mode (EBCCRn=11) 16-bit bus (EBCCRn=10) READY mode (EBCCRnRDY=1, EBCCRN.PM=00) Channel enable (EBCCRn.ME=1) ISA/ATA pin select mode (PCFG.ISA_SEL=1, PCFG.ATA_SEL=1) Program the number of wait cycles, the SHWT option and the bus speed according to the ISA module used. Figure 7.3.18 shows an example of connecting a 16-bit ISA module to the TX4938. TX4938 ADDR[15:0] DATA[15:0] IOR* IOW * ACK*/READY 16 16 ISA-Module SA[15:0] SD[15:0] IOR* IOW * IOCHRDY AEN Figure 7.3.18 An Example of Connecting an ATA Module Since the ATA has a 16-bit data bus, the same considerations apply to the ATA module as for the 16-bit ISA module. With the EBUSC configured for a 16-bit bus, bits [3:1] of physical addresses are driven out from ADDR[2:0]. Table 7.3.8 shows the relationships in offset addresses between the ATA and the TX4938. For byte accesses, the valid byte lane in the data bus differs, depending on whether the TX4938 is configured for big-endian or little-endian byte ordering. To access 8-bit registers in the ATA address space, address conversion is required, as shown in Table 7.3.8. Table 7.3.8 Relationships Between the ATA Addresses and Physical Addresses ATA Address Offset CS[0]* Space 0x1F0 0x1F1 0x1F2 0x1F3 0x1F4 0x1F5 0x1F6 0x1F7 CS[1]* Space 0x3F6 ATA Register Mnemonic DTR (16bit) ERR/FTR (8bit) SCR (8bit) SNR (8bit) CLR (8bit) CHR (8bit) DHR (8bit) STR/CMR (8bit) ASR/DCR (8bit) TX4938 Physical Address Offset 16-Bit Access 0x103E0 - 8-Bit Access Little-Endian 0x103E2 0x103E4 0x103E6 0x103E8 0x103EA 0x103EC 0x103EE 0x207EC Big-Endian 0x103E3 0x103E5 0x103E7 0x103E9 0x103EB 0x103ED 0x103EF 0x207ED 7-23 Chapter 7 External Bus Controller 7.4 Register Table 7.4.1 External Bus Controller (EBUSC) Registers Offset Address 0x9000 0x9008 0x9010 0x9018 0x9020 0x9028 0x9030 0x9038 Bit Width Register Symbol 64 64 64 64 64 64 64 64 EBCCR0 EBCCR1 EBCCR2 EBCCR3 EBCCR4 EBCCR5 EBCCR6 EBCCR7 Register Name E-Bus Channel Control Register 0 E-Bus Channel Control Register 1 E-Bus Channel Control Register 2 E-Bus Channel Control Register 3 E-Bus Channel Control Register 4 E-Bus Channel Control Register 5 E-Bus Channel Control Register 6 E-Bus Channel Control Register 7 7-24 Chapter 7 External Bus Controller 7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7) Channel 0 can be used as Boot memory. Therefore, the default is set by the Boot signal (see 7.3.2 Global/Boot-up Options). Channels 1 - 7 have the same register configuration as Channel 0, but they have different defaults than Channel 0. When the EBCCRn is programmed using a sequence of 32-bit store instructions, the base address in the high-order 32-bit portion of the register must be written first, followed by the Master Enable bit in the low-order 32-bit portion. 63 BA[35:20] R/W 0x01FC/0x0000 47 Reserved : Type : Initial value 31 Reserved 0 15 WT R/W 111(~D[4])/0000 0 0 12 11 CS R/W 1/0 0 8 7 BC R/W D[5]/0 23 ISA R/W 0 6 RDY R/W 0 22 21 BSZ R/W D[1:0]/00 5 SP R/W A[7:6]/00 4 0 3 ME R/W A[8]/0 0 20 19 PM R/W 0 2 SHWT R/W 0 0 : Type : Initial value 18 17 PWT R/W 11/00 0 : Type : Initial value 16 32 :Type : Initial value 48 Only in the case of Channel 0 are fields with different defaults in the “Channel 0/Other channel” state. D[ ] represents the corresponding Data[ ] signal value when the RESET* signal is deasserted. A[ ] represents the corresponding ADDR[ ] signal value when the RESET* signal is deasserted. Bit 63:48 Mnemonic BA[35:20] Field Name Base Address Description External Bus Control Base Address (Default: 0x01FC/0x0000) A physical address is used to specify the base address. The upper 16 bits [35:20] of the physical address are compared to the value of this field. ISA/ATA Mode (Default: 00) Specifies the ISA I/O mode and ATA PIO mode. 00: ISA/ATA Mode disable 10: Reserved 01: ISA Mode enable 11: ATA Mode enable External Bus Control Bus Size (Default: DATA[1:0]/00) Specifies the memory bus width. 00: Reserved 10: 16-bit width 01: 32-bit width 11: 8-bit width Note: DATA[1:0] is set to Channel 0 as the default. Read/Write R/W 47:24 23:22 ISA Reserved ISA/ATA Mode R/W ⎯ 21:20 BSZ Bus Width R/W Figure 7.4.1 External Bus Channel Control Register (1/3) 7-25 Chapter 7 External Bus Controller Bit 19:18 Mnemonic PM Field Name Page Mode Page Size Description External Bus Control Page Mode Page Size (Default: 00) Specifies the Page mode (Page mode memory support) use and page size. 00: Normal mode 01: 4-page mode 10: 8-page mode 11: 16-page mode External Bus Control Page Mode Wait Time (Default: 11 / 00) Specifies the wait cycle count during Burst access when in the Page mode. 00: 0 wait cycles 10: 2 wait cycles 01: 1 wait cycle 11: 3 wait cycles Specifies a wait cycle count from 0 to 62 that matches WT when in the Normal mode or Ready mode. (See the WT item.) External Bus Control Normal Mode Wait Time (Default: 111 (~DATA[4])/0000) Specifies the wait cycle count in the first cycle of a Single Cycle or Burst access. Specifies the following wait cycle count when in the Page mode. 0000: 0 wait cycles 0100: 4 wait cycles 1000: 8 wait cycles 1100: 12 wait cycles 0001: 1 wait cycle 0101: 5 wait cycles 1001: 9 wait cycles 1101: 13 wait cycles 0010: 2 wait cycles 0110: 6 wait cycles 1010: 10 wait cycles 1110: 14 wait cycles 0011: 3 wait cycles 0111: 7 wait cycles 1011: 11 wait cycles 1111: 15 wait cycles Specifies a wait cycle count from 0 to 62 that matches PWT when in a mode other than the Page mode. PWT[1:0]: WT[3:0] 000000: 0 wait cycles 010000: 16 wait cycles 110000: 48 wait cycles 000001: 1 wait cycle 010001: 17 wait cycles 110001: 49 wait cycles : : : 001110: 14 wait cycles 011110: 30 wait cycles 111110: 62 wait cycles 001111: 15 wait cycles 011111: 31 wait cycles 111111: External ACK mode Note 1: Value that is the reverse of DATA[4] is set to the LSB of Channel 0 as the default. Note 2: If PWT:WT is set to 0x3f when PM = 00 and RDY = 0, the external bus enters the ACK* Input mode (External ACK mode) without the wait cycle count for the ACK* output being the maximum value. Note 3: WT[0] is used to select Dynamic/Static ACK*/Ready mode when in the Ready mode. Therefore, the Wait cycle count is an even number. Note 4: The WT wait cycle count should be equal to or greater than the PWT Wait cycle count when in the Page mode. Read/Write R/W 17:16 PWT Page Mode Wait time R/W 15:12 WT Normal Mode Wait Time R/W 11:8 CS Channel Size External Bus Control Channel Size (Default: 0010/0000) Specifies the channel memory size. 0000: 1 MB 0101: 32 MB *1010: 1 GB 0001: 2 MB 0110: 64 MB 1011-1111: Reserved 0010: 4 MB 0111: 128 MB 0011: 8 MB 1000: 256 MB 0100: 16 MB 1001: 512 MB * The channel memory size can be set up to 512 MB when the memory bus width is 16 bits, or up to 256 MB when the memory bus width is 8 bits. No size larger than this can be set. R/W Figure 7.4.1 External Bus Channel Control Register (2/3) 7-26 Chapter 7 External Bus Controller Bit 7 Mnemonic BC Field Name Byte Control Description External Bus Byte Control (Default: DATA[5]/0) Specifies whether to use the BWE*[3:0] signal as an asserted Byte Write Enable signal (BWE*[3:0]) only during a Write cycle, or to use it as an asserted Byte Enable signal (BE*[3:0]) that is asserted during both Read and Write cycles. 0: Byte Enable (BE *[3:0]) 1: Byte Write Enable (BWE*[3:0]) Note: DATA[5] is set to Channel 0 as the default. External Bus Control Ready Input Mode (Default: 0) Specifies whether to use the Ready mode. 0: Disable the Ready mode. 1: Enable the Ready mode. Note: The Ready mode cannot be used when the Page mode is selected. External Bus Control Bus Speed (Default: ADDR[7:6] / 00) Specifies the External Bus speed. 00: 1/4 speed (1/4 of the GBUSCLK frequency) 01: 1/3 speed (1/3 of the GBUSCLK frequency) 10: 1/2 speed (1/2 of the GBUSCLK frequency) 11: Full speed (same frequency as GBUSCLK) Note: ADDR[7:6] is set to Channel 0 as the default. External Bus Control Master Enable (Default: ADDR[8] / 0) Enables a channel. 0: Disable channel 1: Enable channel Note: ADDR[8] is set to Channel 0 as the default. External Bus Control Setup/Hold Wait Time (Default: 000) Specifies the wait count when switching between the Address and Chip Enable signal, or the Chip Enable Signal and Write Enable/Output Enable signal. * 000: Disable 100: 4 wait cycles 001: 1wait cycle 101: 5 wait cycles 010: 2 wait cycles 110: 6 wait cycles 011: 3 wait cycles 111: 7 wait cycles * Set this bit field to “0” when using it in the Page mode or when performing Burst access. Read/Write R/W 6 RDY Ready Input Mode R/W 5:4 SP Bus Speed R/W 3 ME Master Enable R/W 2:0 SHWT Set Up/Hold Wait Time R/W Figure 7.4.1 External Bus Channel Control Register (3/3) 7-27 Chapter 7 External Bus Controller 7.5 Timing Diagrams Please take the following points into account when referring to the timing diagrams. (1) The clock frequency of the SYSCLK signal can be set to one of the following divisions of the internal bus clock (GBUSCLK): 1/1, 1/2, 1/3, or 1/4. Also, the operating reference clock frequency can be set to one of the following divisions of the internal bus clock (GBUSCLK) for each channel: 1/1, 1/2, 1/3, or 1/4. (See 7.3.8.) The timing diagrams indicate the SYSCLK signal clock frequency and channel operating reference clock frequency as being equivalent. (2) Both the BWE* signal and BE* signal are indicated in all timing diagrams. The setting of the Channel Control Register (EBCCRn) determines whether the BWE* pin will function as BWE* or BE*. (3) All Burst cycles in the timing diagrams illustrate examples in which the address increases by increments of 1 starting from 0. However, cases where the CWF (Critical Word First) function of the TX49 core was used or the decrement burst function performed by the DMA Controller was used are exceptions. (4) The timing diagrams display each clock cycle currently being accessed using the symbols described in the following table. SWn PWn ASn CSn AHn CHn ESn ACEn Sn Normal Wait Cycles Page Wait Cycles Set-up Time from SHWT Address Validation to CE Fall Set-up Time from SHWT CE Fall to OE/SWE Fall Hold Time from SHWT CE Rise to Address Change Hold Time from SHWT OE/SWE Rise to CE Rise Synch Cycles of the External Input Signal Address Clock Enable Cycles Other Cycles (5) Shaded areas ( ) in the diagrams are undefined values. 7-28 Chapter 7 External Bus Controller 7.5.1 ACE* Signal S3 0 ACE2 S1 S2 ACE1 f S2 S3 ACE1 ACE2 S1 f f f OE*/BUSSPRT* DATA[31:0] CE* ACE* SWE* BWE* BE* 0 f f 0 f Figure 7.5.1 ACE* Signal (CCFG.ACEHOLD=1, PWT: WT=0, SHWT=0, Normal) ADDR[19:0] SYSCLK 7-29 ACK* Chapter 7 External Bus Controller S3 0 ACE1 S1 S2 f S2 S3 ACE1 S1 f SYSCLK f f OE*/BUSSPRT* DATA[31:0] CE* ACE* SWE* BWE* BE* 0 f f 0 f Figure 7.5.2 ACE* Signal (CCFG.ACEHOLD=0, PWT: WT=0, SHWT=0, Normal) ADDR[19:0] 7-30 ACK* Chapter 7 External Bus Controller 7.5.2 Normal mode access (Single, 32-bit Bus) S3 f S2 S1 1 0 f S3 0 S1 S2 f SYSCLK f OE*/BUSSPRT* DATA[31:0] CE* ACE* SWE* BWE* BE* 0 0 f 0 f Figure 7.5.3 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) ADDR[19:0] 7-31 ACK* Chapter 7 External Bus Controller S1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE* DATA[31:0] ACK* f 0 0 S2 S1 S2 S3 1 f f 0 f Figure 7.5.4 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-32 Chapter 7 External Bus Controller S2 S3 0 S1 SW1 f f BE* f 0 f ACE* OE*/BUSSPRT* ADDR[19:0] SYSCLK Figure 7.5.5 1-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) 7-33 DATA[31:0] SWE* BWE* ACK* CE* Chapter 7 External Bus Controller S2 S3 S1 SW1 f f OE*/BUSSPRT* DATA[31:0] CE* ACE* SWE* BWE* BE* 0 f Figure 7.5.6 1-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) ADDR[19:0] SYSCLK 7-34 ACK* Chapter 7 External Bus Controller 7.5.3 Normal mode access (Burst, 32-bit Bus) S2 S3 3 S1 SW1 S2 S3 2 S1 SW1 0 f 0 BE f f 0 0 DATA[31:0] ACE* OE*/BUSSPRT* SWE* BWE* f S2 S3 S2 S3 S1 SW1 S1 SW1 SYSCLK CE* ADDR[19:0] 0 1 f 0 f f Figure 7.5.7 4-word Burst Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-35 ACK* Chapter 7 External Bus Controller S1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE DATA[31:0] ACK* f SW1 S2 S1 SW1 S2 S1 SW1 S2 S1 SW1 S2 S3 0 1 2 3 f 0 f Figure 7.5.8 4-word Burst Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) 7-36 Chapter 7 External Bus Controller 7.5.4 Normal Mode Access (Single, 16-bit bus) f S2 S3 c 3 f S2 S3 2 c f S2 S3 c 1 f S2 S3 0 c f S1 S1 S1 f S1 CE* ACE* OE*/BUSSPRT* SWE* BWE* BE* f c f c f c f c Figure 7.5.9 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) ADDR [19:0] 7-37 DATA [15:0] SYSCLK ACK* Chapter 7 External Bus Controller S2 S3 S1 3 S2 S1 2 f S2 S1 1 f S2 0 S1 ACE* OE*/BUSSPRT* BE* f c f c f c f c f SWE* SYSCLK ADDR [19:0] BWE* Figure 7.5.10 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-38 DATA [15:0] ACK* CE* Chapter 7 External Bus Controller S3 f S1 S2 f f DATA[15:0] ACE* c c f OE*/BUSSPRT* SWE* BWE* Figure 7.5.11 Half-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) ADDR[19:0] SYSCLK 7-39 ACK* CE* BE* Chapter 7 External Bus Controller S3 S2 S1 f BE* f c f ACE* OE*/BUSSPRT* ADDR[19:0] SYSCLK Figure 7.5.12 Half-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) 7-40 DATA[15:0] SWE* BWE* ACK* CE* Chapter 7 External Bus Controller 7.5.5 Normal Mode Access (Burst, 16-bit Bus) S2 S3 S2 S1 S2 S1 S2 S1 S1 4 5 6 7 S2 S2 S1 S2 S1 S2 S1 S1 0 1 2 3 f f OE*/BUSSPRT* DATA[15:0] ACE* SWE* BWE* c f ADDR[19:0] Figure 7.5.13 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) SYSCLK 7-41 ACK* CE* BE S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 SYSCLK CE* 0 1 2 3 4 5 6 7 ADDR [19:0] ACE* OE*/BUSSPRT* Figure 7.5.14 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) c c f c f c f c f c f c f c f 7-42 SWE* c f f BWE* f BE* f DATA [15:0] Chapter 7 External Bus Controller ACK* Chapter 7 External Bus Controller 7.5.6 Normal Mode Access (Single, 8-bit Bus) f S2 S3 e 7 f S2 S3 e 6 e 5 4 e e 3 f S2 S3 e 2 e 1 0 e f f S2 S3 S1 f S2 S3 S1 S1 f S2 S3 S1 f S2 S3 S1 f S2 S3 S1 S1 S1 f CE* ACE* OE*/BUSSPRT* SWE* BWE* BE* f e f e f e f e f e f e f e f e SYSCLK Figure 7.5.15 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) ADDR [19:0] 7-43 DATA [7:0] ACK* S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S3 SYSCLK CE* 0 1 4 2 3 5 6 7 ADDR [19:0] ACE* Figure 7.5.16 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) f e f f e f e e f e f e f f e f 7-44 OE*/BUSSPRT* SWE* BWE* BE* f e f DATA [7:0] Chapter 7 External Bus Controller ACK* Chapter 7 External Bus Controller S1 SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE* DATA [7:0] ACK* f f SW1 S2 S3 e e f f Figure 7.5.17 1-byte Single Write (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) S1 SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE* DATA [7:0] ACK* f SW1 S2 S3 f e f Figure 7.5.18 1-byte Single Read (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) 7-45 7.5.7 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 SYSCLK CE* 0 1 2 3 4 5 6 7 8 9 a b c d e f ADDR [19:0] ACE* Normal Mode Access (Burst, 8-bit Bus) OE*/BUSSPRT* Figure 7.5.19 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) e e f e f e f e f e f e f e f e f e f e f e f e f e e f e f e 7-46 SWE* f e f f BWE* f BE* f DATA [7:0] Chapter 7 External Bus Controller ACK* S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S1 S2 S3 SYSCLK CE* ADDR[19:0] 0 8 9 1 2 3 4 5 6 7 ACE* OE*/BUSSPRT* SWE* BWE* f e BE DATA[8:0] ACK* f e f a b c d e f Figure 7.5.20 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) 7-47 Chapter 7 External Bus Controller Chapter 7 External Bus Controller 7.5.8 Page Mode Access (Burst, 32-bit Bus) f S3 7 S1 S2 S3 S2 6 S1 S3 S2 5 S1 S2 S3 4 S1 SW1 S3 f S2 3 S1 S3 S2 2 S1 S3 S2 1 S1 S2 S3 0 S1 SW1 f 0 f 0 f 0 f 0 0 f 0 f 0 f 0 f ACE* CE* SWE* BWE* BE* f c OE*/BUSSPRT* Figure 7.5.21 8-word Burst Write (WT=1, PWT=0, SHWT=0, 4-page, 32-bit Bus) ADDR [19:0] 7-48 DATA [31:0] SYSCLK ACK* Chapter 7 External Bus Controller S3 S2 S2 S1 PW1 3 PW1 PW1 S2 S1 SW1 SW2 S2 S1 S1 0 1 2 SYSCLK f OE*/BUSSPRT* DATA[31:0] CE* ACE* SWE* BWE* BE* 0 f f Figure 7.5.22 4-word Burst Read (WT=2, PWT=1, SHWT=0, 4-page, 32-bit Bus) ADDR[19:0] 7-49 ACK* Chapter 7 External Bus Controller 7.5.9 External ACK Mode Access (32-bit Bus) S1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE* DATA[31:0] ACK* f f 0 0 f f ES1 ES2 ES3 S2 S3 Note 1: The TX4938 sets the ACK* signal to High Impedance in the S1 State. Note 2: External devices drive the ACK* signal to Low (assert the signal) by the ES1 State. Note 3: External devices drive the ACK* signal to High (deassert the signal) in the ES2 State. If an external device is late in asserting ACK*, then the Wait State is inserted for the amount of time the external device is late. If a certain condition is met, it is okay for the ACK* signal to be driven to Low for 1 clock cycle or more. See 7.3.7.4 ACK* Input Timing (External ACK Mode) for more information. Figure 7.5.23 1-word Single Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus) S1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE* DATA[31:0] ACK* f ES1 ES2 S2 S3 f 0 f Figure 7.5.24 1-word Single Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus) 7-50 S1 ES1 ES2 ES3 S2 S3 S1 ES1 ES2 ES3 S2 S3 S1 ES1 ES2 ES3 S2 S3 S1 ES1 ES2 ES3 S2 S3 SYSCLK CE* 0 1 2 3 ADDR [19:0] ACE* OE*/BUSSPRT* Figure 7.5.25 4-word Burst Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus) 0 f 0 f 0 0 f 0 7-51 SWE* f f BWE* f BE* f DATA [31:0] Chapter 7 External Bus Controller ACK* Chapter 7 External Bus Controller ES2 S2 S3 ES2 S2 S1 ES1 S1 ES1 2 3 ES2 S2 ES2 S2 S1 ES1 S1 ES1 0 1 BE f OE*/BUSSPRT* DATA[31:0] CE* ACE* SWE* BWE* 0 f f Figure 7.5.26 4-word Burst Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus) ADDR[19:0] SYSCLK 7-52 ACK* AS1 AS2 CS1 CS2 SW1 ES1 ES2 ES3 S2 CH1 AH1 AH2 AS1 AS2 CS1 CS2 SW1 ES1 ES2 ES3 CH2 S2 CH1 CH AH1 AH2 SYSCLK CE* 0 1 ADDR [19:0] ACE* OE*/BUSSPRT* Figure 7.5.27 Double-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) f 0 f 0 f 0 0 f 7-53 SWE* BWE* BE* f f DATA [31:0] ACK* Chapter 7 External Bus Controller Note: The TX4938 drives the ACK* signal when in the AH2, AS1, or AS2 State. AS1 AS2 CS1 CS2 S1 ES1 ES2 S2 CH2 CH2 AH1 AH2 AS1 AS2 CS1 CS2 S1 ES1 ES2 S2 CH1 CH2 AH1 AH2 SYSCLK CE* 0 1 ADDR [19:0] ACE* OE*/BUSSPRT* Figure 7.5.28 Double-word Single Read (0 Wait, SHWT=2, External ACK*, 32-bit Bus) f f 0 f 0 7-54 SWE* BWE* BE* f DATA [31:0] ACK* Chapter 7 External Bus Controller Note: The TX4938 drives the ACK* signal when in the AH2, AS1, or AS2 State. Chapter 7 External Bus Controller AS1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE DATA[31:0] ACK* f AS2 CS1 CS2 SW1 ES1 ES2 ES3 S2 CH1 CH2 AH1 AH2 f 0 0 f f Figure 7.5.29 1-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) AS1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE DATA[31:0] ACK* f AS2 CS1 CS2 S1 ES1 ES2 S2 CH1 CH2 AH1 AH2 f 0 f Figure 7.5.30 1-word Single Read (0 Wait, SHWT=2, External ACK*, 32-bit Bus) 7-55 Chapter 7 External Bus Controller 7.5.10 READY Mode Access (32-bit Bus) AH1 ES2 ES3 S2 CH1 0 f f BE* f 0 AS1 CS1 SW1 ES1 f ACE* OE*/BUSSPRT* ADDR[19:0] SYSCLK Figure 7.5.31 1-word Single Write (PWT: WT=2, SHWT=1, READY, 32-bit Bus) 7-56 DATA[31:0] SWE* BWE* ACK* CE* Chapter 7 External Bus Controller ES2 S2 CH1 AH1 AS1 CS1 S1 ES1 f SYSCLK ADDR[19:0] ACE* OE*/BUSSPRT* BE* f 0 f Figure 7.5.32 1-word Single Read (PWT: WT=2, SHWT=1, READY, 32-bit Bus) 7-57 DATA[31:0] SWE* BWE* ACK* CE* Chapter 7 External Bus Controller 7.5.11 ISA IO Space Access AH2 ES2 ES3 S2 CH1 CH2 AH1 0 AS1 AS CS1 CS SW1 ES1 f f OE*/BUSSPRT* DATA[31:0] SWE* BWE[3:0]* BE* e f ADDR[19:0] ACE* ACK* CE* CS[0]* Figure 7.5.33 1-byte Write Access for the ISA IO Space (READY, SHWT=2, 8-bit Bus) SYSCLK 7-58 CS[1]* IOR* IOW * AS1 SYSCLK CE* ADDR[19:0] ACE* BUSSPRT* OE* SWE* BWE[3:0]* BE* DATA[31:0] ACK* f e f f 0 AS CS1 CS S1 ES1 ES2 S2 CH1 AH1 ES3 CH2 AH2 Figure 7.5.34 1-byte Read Access for the ISA IO Space (READY, SHWT=2, 8-bit Bus) 7-59 IOR* IOW * CS[0]* CS[1]* Chapter 7 External Bus Controller Chapter 7 External Bus Controller 7.5.12 ATA/PIO Transfer Mode Access AH2 ES2 ES3 S2 CH1 CH2 AH1 8000 f AS1 AS‚ CS1 CS‚ SW1 ES1 f OE*/BUSSPRT* DATA[31:0] SWE* BWE[3:0]* BE* c f ADDR[19:0] ACE* ACK* CE* CS[0]* Figure 7.5.35 1-half-word Write Access for the ATA/PIO Space (CS0) (READY, SHWT=2, 16-bit Bus) SYSCLK 7-60 CS[1]* IOR* IOW * AS1 SYSCLK CE* ADDR[19:0] 10000 ACE* BUSSPRT* OE* SWE* BWE[3:0]* BE[3:0]* DATA[31:0] ACK* f c f f AS CS1 CS S1 ES1 ES2 S2 CH1 AH1 ES3 CH2 AH2 Figure 7.5.36 1-half-word Read Access for the ATA/PIO Space (CS1) (READY, SHWT=2, 16-bit Bus) 7-61 IOR* IOW * CS[0]* CS[1]* Chapter 7 External Bus Controller Chapter 7 External Bus Controller 7.6 Flash ROM, SRAM Usage Example Figure 7.6.1 illustrates example Flash ROM connections, and Figure 7.6.2 illustrates example SRAM connections. Also, Figure 7.6.3 illustrates example connections with the SDRAM and the bus separated. Since connecting multiple memory devices such as SDRAM and ROM onto a single bus increases the load, 100 MHz class high-speed SDRAM access may not be performed normally. As a corrective measure, there is a way of reducing the bus load by connecting a device other than SDRAM via a buffer. If such a method is employed, directional control becomes necessary since the data becomes bidirectional. The TX4938 prepares the BUSSPRT* signal for performing data directional control (see Figure 7.6.3). BUSSPRT* is asserted when the External Bus Controller channel is active and a Read operation is being performed. TX4938 Flash ROM (x16 bits) ADDR[19:0] ADDR[12] ACE* ADDR[19:0] (ADDR[20]) A[19:0] A20 A[19:0] A20 CE*[0] SWE* OE* CE* W E* OE* CE* W E* OE* D[15:0] DATA[31:0] D[31:16] D[15:0] D[15:0] Figure 7.6.1 Flash ROM (x16 Bits) Connection Example (32-bit Data Bus) TX4938 BWE*[3:0] SRAM (x16 Bits) BWE*[3] UB ADDR[19:0] BWE*[2] LB BWE*[1] UB BWE*[0] LB ADDR[19:0] A[19:0] A[19:0] CE*[1] SWE* OE* CS* W E* OE * CS* W E* OE * D[15:0] DATA[31:0] D[31:16] D[15:0] D[15:0] Figure 7.6.2 SRAM (x16 Bits) Connection Example (32-bit Data Bus) 7-62 Chapter 7 External Bus Controller TX4938 DQM[7:0] SDRAM (x16 Bits) DQM[7] DQM[6] DQM[5] DQM[4] DQM[3] DQM[2] DQM[1] DQM[0] UDQM LDQM ADDR[19:0] ADDR[17:5] A[12:0] ADDR[19] BS0 ADDR[18] BS1 CS* RAS* CAS* W E* CLK CKE DQ[15:0] UDQM LDQM A[12:0] BS0 BS1 CS* RAS* CAS* W E* CLK CKE DQ[15:0] UDQM LDQM A[12:0] BS0 BS1 CS* RAS* CAS* W E* CLK CKE DQ[15:0] UDQM LDQM A[12:0] BS0 BS1 CS* RAS* CAS* W E* CLK CKE DQ[15:0] D[15:0] SDCS*[0] RAS* CAS* WE* SDCLKIN SDCLK[0] CKE DATA[63:0] D[63:48] D[47:32] D[31:16] Flash ROM (x16 Bits) CE*[0] SWE* OE* BUSSPRT* ADDR[19:0] ADDR[12] ACE* (ADDR[20]) A[19:0] A20 A[19:0] A20 CE* W E* OE * CE* W E* OE * D[15:0] D[31:16] D[15:0] D[15:0] Figure 7.6.3 Connection Example with SDRAM and the Bus Separated 7-63 Chapter 7 External Bus Controller 7-64 Chapter 8 DMA Controller 8. 8.1 DMA Controller Features The TX4938 contains two four-channel DMA Controller (DMAC0, DMAC1) that executes DMA (Direct Memory Access) with memory and I/O devices. The DMA Controller has the following characteristics. • Has four on-chip DMA channels • • • • • • • Supports Memory-Memory Copy modes that do not have address boundary limitations. Burst transfer of up to eight double words is possible for each Read or Write operation. Supports Memory Fill mode that writes double-word data to the specified memory region Supports Chained DMA Transfer On-chip signed 24-bit address count up registers for both the source address and destination address On-chip 26-bit Byte Count Register for each channel One of two methods can be selected for determining access priority among multiple channels: Round Robin or Fixed Priority Big Endian or Little Endian mode can be set separately for each channel • Supports external I/O devices with 8-, 16-, and 32-bit Data Bus widths and transfer between memory devices. • • Supports single address transfer (Fly-by DMA) and dual address transfer when in the external I/O DMA Transfer Mode that is operated by external request signals Supports DMA on-chip Serial I/O Controllers • Supports DMA on-chip AC-Link Controllers 8-1 Chapter 8 DMA Controller 8.2 Block Diagram DMAC0 DMA Control 0 Block G-Bus DM0MCR DM0MFDR DMA0 DM0CHAR0 Channel 0 DM0SAR0 DM0DAR0 DM0CNTR0 DM0SAIR0 DM0DAIR0 DM0CCR0 DM0CSR0 DMA0 DM0CHAR1 Channel 1 DM0SAR1 DM0DAR1 DM0CNTR1 DM0SAIR1 DM0DAIR1 DM0CCR1 DM0CSR1 DMA0 DM0CHAR2 Channel 2 DM0SAR2 DM0DAR2 DM0CNTR2 DM0SAIR2 DM0DAIR2 DM0CCR2 DM0CSR2 DMA0 DM0CHAR3 Channel 3 DM0SAR3 DM0DAR3 DM0CNTR3 DM0SAIR3 DM0DAIR3 DM0CCR3 DM0CSR3 Multiplexer DREQ0 DACK0 DMAREQ[0] DMAACK[0] External Pins Internal I/O (Receive SIO ch1) PCFG.DMASEL0 DMAREQ[1] External Pins Internal I/O (Transfer SIO ch1) Multiplexer G-Bus I/F DREQ1 DMCK1 DMAACK[1] FIFO (8 Double Words) PCFG.DMASEL1 DMAREQ[2] Multiplexer DMAACK[2] External Pins Internal I/O (Receiver SIO ch0) PCFG.DMASEL2 DREQ3 DMCK3 DMAREQ[3] Multiplexer DMAACK[3] External Pins Internal I/O (Transfer SIO ch0) DREQ2 DACK2 DMA Channel Arbiter PCFG.DMASEL3 DMADONE* External Pins Figure 8.2.1 DMA0 Controller Block Diagram 8-2 Chapter 8 DMA Controller DMAC0 DMA Control 1 Block G-Bus DM1MCR DM1MFDR DMA1 DM1CHAR0 Channel 0 DM1SAR0 DM1DAR0 DM1CNTR0 DM1SAIR0 DM1DAIR0 DM1CCR0 DM1CSR0 DMA1 DM1CHAR1 Channel 1 DM1SAR1 DM1DAR1 DM1CNTR1 DM1SAIR1 DM1DAIR1 DM1CCR1 DM1CSR1 DMA1 DM1CHAR2 Channel 2 DM1SAR2 DM1DAR2 DM1CNTR2 DM1SAIR2 DM1DAIR2 DM1CCR2 DM1CSR2 DMA1 DM1CHAR3 Channel 3 DM1SAR3 DM1DAR3 DM1CNTR3 DM1SAIR3 DM1DAIR3 DM1CCR3 DM1CSR3 DREQ0 DACK0 Internal I/O (ACLC ch0) G-Bus I/F DREQ1 DMCK1 Internal I/O (ACLC ch1) FIFO (8 Double Words) DREQ2 DACK2 Internal I/O (ACLC ch2) DMA Channel Arbiter DREQ3 DMCK3 Internal I/O (ACLC ch3) Figure 8.2.2 DMA1 Controller Block Diagram 8-3 Chapter 8 DMA Controller 8.3 Detailed Explanation Transfer Mode The DMA Controller (DMAC0, DMAC1) supports five transfer mode types (refer to Table 8.3.1 below). The setting of the External Request bit (DMCCRn.EXTRQ) of the DMA Channel Control Register selects whether transfer with an I/O device is a DMA transfer. • I/O DMA Transfer Mode (DMCCRn.EXTRQ = “1”) Perform DMA transfer with either an external device connected to the External Bus Controller or an on-chip I/O device (ACLC or SIO). Memory Transfer Mode (DMCCRn.EXTRQ = “0”) Either copies data between memory devices or fills data in memory. Table 8.3.1 DMA Controller Transfer Modes 8.3.1 • DMA Controller DMAC0 Transfer Mode External I/O (Single Address) External I/O (Dual Address) Internal I/O (SIO) Memory-Memory Copy Fill Memory DMCCRn EXTREQ 1 1 1 0 0 1 0 0 PCFG DMASEL 0 0 1 ⎯ ⎯ ⎯ ⎯ ⎯ DMCCRn SNGAD 1 0 0 0 1 0 0 1 DMSAR √ √ √ √ √ √ √ √ DMDAR ⎯ √ √ √ ⎯ √ √ ⎯ Ref. 8.3.3 8.3.7 8.3.3 8.3.8 8.3.4 8.3.8 8.3.4 8.3.8 8.3.6 8.3.7 8.3.4 8.3.8 8.3.4 8.3.8 8.3.6 8.3.7 DMAC1 Internal I/O (ACLC) Memory-Memory Copy Fill Memory 8-4 Chapter 8 DMA Controller 8.3.2 On-chip Registers The DMA Controller has two shared registers that are shared by four channels. Section 8.4 explains each register in detail. • Shared Registers DMMCR: DMA Master Control Register DMMFDR: DMA Memory Fill Data Register DMA Channel Register DMCHARn: DMA Chained Address Register DMSARn: DMA Source Address Register DMDARn: DMA Destination Address Register DMCNTRn: DMA Count Register DMSAIRn: DMA Source Address Increment Register DMDAIRn: DMA Destination Address Increment Register DMCCRn: DMA Channel Control Register DMCSRn: DMA Channel Status Register • 8.3.3 External I/O DMA Transfer Mode The External I/O DMA Transfer Mode performs DMA transfer with external I/O devices that are connected to the External Bus Controller. 8.3.3.1 External Interface External I/O devices signal DMA requests to the DMA Controller by asserting the DMA Transfer Request Signal (DMAREQ[n]). On the other hand, the DMA Controller accesses external I/O devices by asserting the DMA Transfer Acknowledge Signal (DMAACK[n]). The DMA Transfer Request signal (DMAREQ[n]) can use the Request Polarity bit (REQPOL) of the DMA Channel Control Register (DMCCRn) to select the signal polarity for each channel, and can use the Edge Request bit (EGREQ) to select either edge detection or level detection for each channel. The DMA Transfer Acknowledge signal (DMAACK[n]) can also use the Acknowledge Polarity bit (ACKPOL) to select the polarity. Please assert/deassert the DMAREQ[n] signal as follows below. • When level detection is set (DMCCRn.EGREQ = 0) The DMAREQ[n] signal must be continuously asserted until one SYSCLK cycle after the DMAACK[n] signal is asserted. Also, the DMAREQ[n] signal must be deasserted before the CE*/CS* signal is deasserted. If this signal is asserted too soon, DMA transfer will not be performed. If this signal is asserted or deasserted too late, unexpected DMA transfer may result. During Dual Address transfer, we recommend detecting assertion of the CE* signal for the external I/O device that is currently asserting DMAACK[n], then deasserting DMAREQ[n]. 8-5 Chapter 8 DMA Controller • When edge detection is set (DMCCRn.EGREQ = 1) Please set up assertion of the DMAREQ[n] signal so the DMAREQ[n] signal is asserted after the DMAACK[n] signal corresponding to a previously asserted DMAREQ[n] signal is deasserted. The DMAREQ[n] signal will not be detected even if it is asserted before DMAACK[n] is deasserted. Figure 8.3.1 is a timing diagram that shows the timing of external DMA access. In this timing diagram, both the DMAREQ[n] signal and the DMAACK[n] signal are set to Low active (DMCCRn.REQPL = 0, DMCCRn.ACKPOL = 0). The DMAACK[n] and DMADONE[n] signals, which are DMA control signals, are synchronized to SDCLK. When these signals are used by an external I/O device that is synchronous to SYSCLK, it is necessary to take clock skew into account. The DMAACK[n] signal is asserted either at the SYSCLK cycle, the same as with assertion of the CE*/CS* signal, or before that. In addition, it is deasserted after the last ACK*/READY signal is deasserted. When the DMADONE* signal (refer to 8.3.3.4) is used as an output signal, it is asserted for at least one SYSCLK cycle while the DMAACK[n] signal is asserted either during the same SYSCLK cycle that the CE*/CS* signal is deasserted or during a subsequent SYSCLK cycle. When the DMADONE* signal is used as an input signal, it must be asserted for one SYSCLK cycle while the DMAACK[n] signal is being asserted. SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] ACK* 1 cycle DMAREQ[n] DMAACK[n] DMADONE* f 00000100 1c040 00040 Figure 8.3.1 External I/O DMA Transfer (Single Address, Level Request) 8-6 Chapter 8 DMA Controller 8.3.3.2 Dual Address Transfer If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices and to external memory is each performed continuously. Each access is the same as normal access except when the DMAACK[n] signal is asserted. Please refer to “8.3.8 Dual Address Transfer” for information regarding setting the register. 8.3.3.3 Single Address Transfer (Fly-by DMA) If the Single Address bit (DMCCRn.SNGAD) is set, either data reading from an external I/O device and data writing to external memory or data reading from external memory and data writing to an external I/O device is performed simultaneously. The following conditions must be met in order to perform Single Address transfer. • • The data bus widths of the external I/O device and external memory match Data can be input/output to/from the external I/O device and external memory during the same clock cycle The Transfer Direction bit (MEMIO) of the DMA Channel Control Register (DMCCRn) specifies the transfer direction. • From memory to an external I/O device (DMCCRn.MEMIO = “1”) External memory Read operation to an address specified by the DMA Source Address Register (DMSARn) is performed simultaneously to assertion of the DMAACK[n] signal. • Single Address transfer from memory to an external I/O device (DMCCRn.MEMIO = “0”) External memory Write operation to an address specified by the DMA Source Address Register (DMSARn) is performed simultaneously to assertion of the DMAACK[n] signal. At this time, the external I/O device drives the DATA signal instead of the TX4938. Special attention must be paid to the timing design when the bus clock frequency is high or when performing Burst transfer. Single Address transfer using Burst transfer with SDRAM is not recommended. 8.3.3.4 DMADONE* Signal The DMADONE* signal operates as either the DMA stop request input signal or the DMA done signalling output signal, or may operate as both of these signals depending on the setting of the DONE Control Field (DNCTRL) of the DMA Channel Control Register (DMCCRn). The DMADONE* signal is shared by four channels. The DMADONE* channel is valid for a channel when the DMAACK[n] signal for that channel is asserted. If the DMADONE* channel is set to be used as an output signal (DMCCRn.DNCTRL = 10/11), it will operate as follows depending on the setting of the Chain End bit (CHDN) of the DMA Channel Control Register (DMCCRn). When the Chain End bit (CHDN) is set, the DMADONE* signal is only asserted when the DMAACK[n] signal for the last DMA transfer in the Link List Command Chain is asserted. 8-7 Chapter 8 DMA Controller When the Chain End bit (CHDN) is cleared, the DMADONE* signal is asserted when the DMAACK[n] signal for the last data transfer in a DMA transfer specified by the current DMA Channel Register is asserted. Namely, if the Link List Command chain is used, there is one assertion at the end of each data transfer specified by each Descriptor. If the DMADONE* signal is set to be used as an input signal (DMCCRn.DNCTRL = 01/11), DMA transfer can be set to end normally when the external device asserts the DMADONE* signal when the DMAACK[n] signal of channel n is asserted. DMADONE* is asserted during DMAACK[n] is not asserted, then unexpected operation occurs. When DMA transfer is terminated by the DMADONE* assertion of the external device, the External DONE Assert bit (DMCSRn.EXTDN) of the DMA Channel Status Register is set regardless of the setting of the Chain End bit (CHDN) of the DMA Channel Control Register (DMCCRn). Operation is as follows depending on the setting of the Chain End bit (CHDN). When the Chain End bit (CHDN) is set, all DMA transfer for that chain is terminated. At this time, the Normal Chain End bit (NCHNC) and the Normal Transfer End bit (NTRNFC) of the DMA Channel Status Register are both set and the Transfer Active bit (DMCCRn.XFACT) of the DMA Channel Control Register is cleared. When the Chain End bit (CHDN) is cleared, only DMA transfer specified by the current DMA Channel Register ends normally, and only the Normal Transfer End bit (NTRNFC) is set. When the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn) is set, chain transfer is executed and DMA transfer continues. When the Chain Enable bit (CHNEN) is cleared, the Transfer Active bit (DMCCRn.XFACT) is cleared and the Normal Chain End bit (NCHNC) is set. Three clock cycles are required from external assertion of the DMADONE* signal to disabling of new DMA access. Operation will not stop even if the bus operation in progress is a Single transfer or a Burst transfer. For example, if the DMADONE* signal is asserted during Read operation of Dual Address transfer, the corresponding Write bus operation will also be executed. If the DMADONE* pin is set to become both input and output for channel n (DMCCRn.DNCTRL = “11”), the DMADONE* signal becomes an open drain signal when the channel becomes active. When used by this mode, the DMADONE* signal must be pulled up by an external source. When in this mode, the External DONE Assert bit (DMCSRn.EXTDN) is not only set when asserted by an external device, but is also set when asserted by the TX4938. 8.3.4 Internal I/O DMA Transfer Mode Performs DMA with the on-chip Serial I/O Controller and the AC-link Controller. Set the DMA Channel Control Register (DMCCRn) as follows. • • DMCCRn.EXTRQ = 1: I/O DMA Transfer mode DMCCRn.SNGAD = 0: Dual Address Transfer Refer to “8.3.8 Dual Address Transfer” and “11.3.6 DMA transfer (Serial I/O Controller)” or “14.3.6.4 DMA operation (AC-link Controller) for more information. 8-8 Chapter 8 DMA Controller 8.3.5 Memory-Memory Copy Mode It is possible to copy memory from any particular address to any other particular address when in the Memory-Memory Copy mode. Set the DMA Channel Control Register (DMCCRn) as follows. • • DMCCRn.EXTRQ = 0: Memory Transfer mode DMCCRn.SNGAD = 0: Dual Address mode Furthermore, when in the Memory-Memory Copy mode it is possible to set the interval for requesting ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control Register (DMCCRn). Refer to “8.3.8 Dual Address Transfer” for information regarding the setting of other registers. 8.3.6 Memory Fill Transfer Mode When in the Memory Fill Transfer mode, double word data set in the DMA Memory Fill Data Register (DMMFDR) is written to the data region specified by the DMA Source Address Register (DMSARn). This data can be used for initializing the memory, etc. Set the DMA Channel Control Register (DMCCRn) as follows. • • • DMCCRn.EXTRQ = 0: Memory transfer mode DMCCRn.SNGAD = 1: Single Address Transfer DMCCRn.MEMIO = 0: Transfer from I/O to memory In addition, when in the Memory Fill Transfer mode, it is possible to set the interval for requesting ownership of each bus using the Internal Request Delay field (INTRQD) of the DMA Channel Control Register (DMCCRn). Refer to “8.3.7 Single Address Transfer” for information regarding the setting of other registers. By using this function together with the memory Write function that writes to multiple SDRAM Controller memory channels simultaneously (refer to Section 9.3.4), it is possible to initialize memory even more efficiently. 8.3.7 Single Address Transfer This section explains register settings during Single Address transfer (DMCCRn.SNGAD = 1). This applies to the following DMA Transfer modes. • • External I/O (Single Address) Transfer Memory Fill Transfer 8-9 Chapter 8 DMA Controller 8.3.7.1 Channel Register Settings During Single Address Transfer Table 8.3.2 shows restrictions of the Channel Register settings during Single Address transfer. If these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit (CFERR) of the DMA Channel Status Register (DMCSRn) is set and DMA transfer is not performed. For Burst transfer, +8, 0, or –8 can be set to the DMA Source Address Increment Register (DMSAIRn). Setting 0 is only possible during transfer from memory to external I/O. A Configuration Error will result if the value “0” is set during transfer from external I/O to memory or during Memory Fill transfer. If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer setting size is 2 bytes or larger, then set the DMA Source Address Register (DMSARn) with 1 to 3 low-order bits complemented. • • • If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented. If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented. If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits complemented. Example: When the transfer address is 0x0_0001_0000, the DMA Source Address Register (DMSARn) is as follows below. • • DMSAIRn setting is “0” or greater: 0x0_0001_0000 DMSAIRn setting is a negative value: 0x0_0001_0007 During Single Address transfer, the DMA Destination Address Register (DMDARn) and DMA Destination Address Increment Register (DMDAIRn) settings are ignored. Table 8.3.2 Channel Register Setting Restrictions During Single Address Transfer Transfer Setting Size (DMCCRn.XFSZ) 1 Byte 2 Bytes 4 Bytes 8 Bytes 4 Double Words 8 Double Words 16 Double Words 32 Double Words 000 111 8/0/-8 000 DMSARn[2:0] DMSAIRn is “0” or greater *** **0 *00 000 DMSAIRn setting is a negative value *** **0 *00 111 DMSAIRn[2:0] *** **0 *00 000 DMCNTRn[2:0] *** **0 *00 000 8-10 Chapter 8 DMA Controller 8.3.7.2 Burst Transfer During Single Address Transfer According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst transfer that spans across 32-double word boundaries. Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size (DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that were specified by a Burst transfer. Therefore, the DMA Controller executes multiple Burst transactions of a transfer size smaller than the specified transfer size. This division method changes according to the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA Channel Control Register. Figure 8.3.2 shows the Single Address Burst transfer status when the lower 8 bits of the Transfer Start address are 0xA8 and the transfer setting size (DMCCRn.XFSZ) is set to 4 double words. Panel (a) of this figure shows the situation when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is “0”. In this case, first a three-double word transfer is performed up to the address aligned to the transfer setting size. Then, four-double word transfer specified by the transfer setting size is repeated. This setting is normally used. On the other hand, panel (b) shows when the Transfer Size Mode bit (DMCCRn.USEXFSWZ) is “1”. In this case, transfer is repeated according to the transfer setting size. Three-double word transfer and one-double word transfer is only performed consecutively without releasing bus ownership when transfer spans across a 32-double word boundary. 63 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 00 08 10 18 20 28 30 38 40 48 50 58 60 0 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 00 08 10 18 20 28 30 38 40 48 50 58 60 63 0 3 Double Words 4 Double Words 4 Double Words 4 Double Words 4 Double Words 32 Double Word Boundary (3 + 1) Double Words 4 Double Words 4 Double Words 4 Double Words 4 Double Words 4 Double Words 4 Double Words DMCCRn.XFER = 4 DMCCRn.XFER = 4 (a) DMCCRn.USEXFSZ = “0” (b) DMCCRn.USEXFSZ = “1” Figure 8.3.2 Non-aligned Single Address Burst Transfer 8-11 Chapter 8 DMA Controller 8.3.8 Dual Address Transfer This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This applies to the following DMA transfer modes. • • • 8.3.8.1 External I/O (Dual Address) transfer Internal I/O DMA transfer Memory-Memory Copy transfer Channel Register Settings During Dual Address Transfer Table 8.3.3 shows restrictions of the Channel Register settings during Dual Address transfer. If these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit (CFERR) of the DMA Channel Status Register (DMCSRn) is set, and DMA transfer is not performed. If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer setting size is 8 bytes or larger, then a value will be set in the DMA Source Address Register (DMSARn) that reflects as follows. If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the transfer size is 2 bytes or larger, set the DMA Source Address Register (DMSARn) as follows: • • • If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented. If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented. If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits complemented. Likewise, if the setting of the DMA Destination Address Increment Register (DMDAIRn) is negative and the transfer size is 2 bytes or larger, set the DMA Destination Address Register (DMDARn) as follows: • • • If the transfer size is 2 bytes, set the DMDARn with the low-order 1 bit complemented. If the transfer size is 4 bytes, set the DMDARn with the low-order 2 bits complemented. If the transfer size is 8 bytes or larger, set the DMDARn with the low-order 3 bits complemented. Example: When the transfer address is 0x0_0001_0000, the DMA Source Address Register (DMSARn) is as follows below. • • DMSAIRn setting is “0” or greater: 0x0_0001_0000 DMSAIRn setting is a negative value: 0x0_0001_0007 8-12 Chapter 8 DMA Controller Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer DMSARn[2:0] DMDARn[2:0] Transfer Setting DMDAIRn DMSAIRn DMCCRn DMDAIRn DMSAIRn Size setting is a DMSAIRn DMDAIRn DMCNTRn REVBYTE setting is a (DMCCRn.XFSZ) setting is 0 negative setting is 0 negative or greater or greater value value 1 Byte 2 Bytes 4 Bytes 8 Bytes, 4 / 8 Double Wods (DMMCR.FIFUM[n]=0) 4 / 8 Double Words (DMMCR.FIFUM[n]=1) 16 Double Words 32 Double Words *** **0 *00 000 000 *** ⎯ *** **0 *00 111 111 ⎯ *** *** **0 *00 000 000 *** ⎯ *** **1 *11 111 111 ⎯ *** *** **0 *00 000 8/0/-8 8 -8 *** **0 *00 000 8/-8 ‡ 8 -8 *** **0 *00 000 000 *** 0 0 0 0/1 0/1 0 0 Cannot be set (Configuration Error) Cannot be set (Configuration Error) : ‡: W hen DMSAIRn is set to 0, read access from source device is performed only one time per transmission specified by DMCCRn.XFSZ. For this reason, transfer can not be performed burst transfer to the I/O device which performs FIFO operation. 8, 0, or -8 can be specified when the Destination Burst Inhibit bit (DMCCRn.DBINH) is set. 8.3.8.2 Burst Transfer During Dual Address Transfer The DMA Controller has a 64-bit 8-stage FIFO on-chip that is connected to the internal bus (GBus) for Burst transfer during Dual Address transfer. Since this FIFO employs a shifter, it is possible to perform transfer of any address or data size. Burst transfer is only performed when 4 Double Words or 8 Double Words is set by the Transfer Setting Size field (DMCCRn.XFSZ) and the FIFO Use Enable bit (DMMCRn.FIFUM[n]) of the DMA Master Control Register is set. According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst transfer that spans across 32-double word boundaries. Consequently, if the address that starts DMA transfer is not a multiple of the transfer setting size (DMCCRn.XFSZ) (is not aligned), transfer cannot be performed by any of the transfer sizes that were specified by a Burst transfer. Therefore, it is necessary to divide the transfer into multiple Burst transactions of a transfer size smaller than the specified transfer size. This division method changes according to the seting of the Transfer Size Mode bit (DMCCRn.USEXFSZ) of the DMA Channel Control Register and whether or not the address offset relative to the Transfer Setting size (DMCCRn.XFSZ) is equivalent to the source address and destination address combined. Figure 8.3.3 shows Dual Address Burst transfer when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is set to “1”, the lower 8 bits of the Transfer Start address for the transfer source are set to 0xA8, the lower 8 bits of the Transfer Start address for the transfer destination are set to 0x38, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 Double Words. Transfer repeats according to the transfer setting size, regardless of the different address offsets. However, transfers that span across 32-double word boundaries are divided. Since data remains in the on-chip FIFO when in this mode, it becomes possible to share the on-chip FIFO among multiple DMA channels. 8-13 Chapter 8 DMA Controller Source Address 63 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 00 08 10 18 20 28 30 38 0 FIFO (8 Double Words) Destination Address 63 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 a0 a8 b0 b8 0 Figure 8.3.3 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 1) Figure 8.3.4 shows Dual Address Burst transfer when the Transfer Size Mode bit (DMCCRn.USEXFSZ) is set to “0”, the lower 8 bits of the Transfer Start address for the transfer source are set to 0xA8, the lower 8 bits of the Transfer Start address for the transfer destination are set to (a) 0x28/(b) 0x30, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 double words. Panel (a) of this figure shows when the address offset is equivalent. In this case, first transfer of three double words is performed up to the address that is aligned with the transfer setting size. Then, transfer of eight double words that is specified by the transfer setting size is repeated. On the other hand, panel (b) show when the address offset is not equivalent. In this case, first only data up to the address that is aligned with the transfer setting size is read to the on-chip FIFO. Then, data is written up to the address that is aligned with the transfer setting size as long as data remains in the on-chip FIFO. Efficiency decreases since the transfer size is divided. Also, since data may remain in the on-chip FIFO, Burst transfer of a Dual Address that uses the on-chip FIFO simultaneously with another channel cannot be performed. Using the Burst Inhibit bit makes it possible to mix Burst transfer with 8-Double-Word Single transfer. This in turn makes it possible to perform Burst access only for memory access during DMA transfer with external I/O devices that cannot perform Burst transfer. When the Source Burst Inhibit bit (DMCCRn.SBINH) is set, data read from the Source Address to the on-chip FIFO is divided into multiple 8-byte Single Read transfers, then transfer is executed. 8-14 Chapter 8 DMA Controller When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to the Destination Address is divided into multiple 8-byte Single Write transfers, then transfer is executed. When the Burst Inhibit bit is set, the TX4938 always performs an 8-byte Single transfer. For accesses to an external I/O device, a Single transfer is divided into multiple accesses, depending on its bus width. Thus, the address changes during a Single transfer. For more on this, see Section 7.3.5, "Data Bus Size." To continually access a fixed address in an external I/O device, program the trasnfer size (DMCCRn.XFSZ) to the bus width of the I/O device and perform Single transfers with the Burst Inhibit bit cleared. 8.3.8.3 Double Word Byte Swapping When the Reverse Byte bit (REVBYTE) of the DMA Channel Configuration Register (DMCCRn) is set, read double word data is written after byte swapping is performed. For example, if the read data is “0x01234567_90ABCDEF”, then the data “0xEFCDAB89_67452301” is written. The Reverse Byte bit can only be set when the REVBYTE column of Table 8.3.3 is set so “0/1” is indicated. 8-15 Chapter 8 DMA Controller Source Address 63 0 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 00 08 10 18 20 28 30 38 FIFO (8 Double Words) Destination Address 63 0 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 a0 a8 b0 b8 (a) Address offset is equivalent 63 a0 a8 b0 b8 c0 c8 d0 d8 e0 e8 f0 f8 00 08 10 18 20 28 30 38 40 48 50 58 60 0 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 a0 a8 b0 b8 c0 c8 d0 d8 e0 (b) Address offset differs 63 0 Figure 8.3.4 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 0) 8-16 Chapter 8 DMA Controller 8.3.9 DMA Transfer The sequence of DMA transfer that uses only the DMA Channel Register is as follows below. 1. Select DMA request signal When performing external I/O or internal I/O DMA, set the DMA Request Select field (PCFG.DMASEL) of the Pin Configuration Register. Set the Master Enable bit Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register. Set the Address Register and Count Register Set the five following register values. • • • • • 4. DMA Source Address Register (DMSARn) DMA Destination Address Register (DMDARn) DMA Count Register (DMCNTRn) DMA Source Address Increment Register (DMSAIRn) DMA Destination Address Increment Register (DMDAIRn) 2. 3. Set Chain Address Register Set “0” to the DMA Chain Address Register (DMCHARn). Clear the DMA Channel Status Register (DMCSRn) Clear when status from the previous DMA transfer remains. Set the DMA Channel Control Register (DMCCRn) Initiate DMA transfer DMA transfer is started by setting the Transfer Active bit (XFACT) of the DMA Channel Control Register. Signal completion When DMA data transfer ends normally, set the Normal Transfer Complete bit (NTRNFC) of the DMA Channel Status Register (DMCSRn). An interrupt is signalled if the Transfer Complete Interrupt Enable bit (INTENT) of the DMA Channel Control Register (DMCCRn) is set. If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of the DMA Channel Status Register and the transfer is interrupted. If the Error Interrupt Enable bit (INTENE) of the DMA Channel Control Register is set, then the interrupt is signaled. 5. 6. 7. 8. 8-17 Chapter 8 DMA Controller 8.3.10 Chain DMA Transfer Table 8.3.4 shows the data structure in memory that the DMA Command Descriptor has. When the Simple Chain bit (SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial four double words are used. DMSAIRn, DMDAIR, DMCCRn, and DMCSRn use the settings from when DMA started. In addition, all eight double words are used when the Simple Chain bit (SMPCHN) is cleared. Saving the start memory address of another DMA Command Descriptor in the Offset 0 Chain Address field makes it possible to construct a chain list of DMA Command Descriptors (Figure 8.3.5). Set “0” in the Chain Address field of the DMA Command Descriptor at the end of the chain list. When DMA transfer that is specified by one DMA Command Descriptor ends, the DMA Controller automatically reads the next DMA Command Descriptor indicated by the Chain Address Register (Chain transfer), then continues DMA transfer. Continuous DMA transfer that uses multiple Descriptors connected into such a chain-like structure is called Chain DMA transfer. Since the DMA Channel Status Register is also overwritten during Chain transfer when the DMA Simple Chain bit (SMPCHN) is cleared, be sure not to unnecessarily clear necessary bits. Placing DMA Command Descriptors at addresses that do not span across 32-double-word boundaries in memory is efficient since they are read by one G-Bus Burst Read operation. Table 8.3.4 DMA Command Descriptors Offset Address 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 Field Name Chain Address Source Address Destination Address Count Source Address Increment Destination Address Increment Channel Control Channel Status Transfer Destination Register DMA Chain Address Register (DMCHARn) DMA Source Address Register (DMSARn) DMA Destination Address Register (DMDARn) DMA Count Register (DMCNTRn) DMA Source Address Increment Register (DMSAIRn) DMA Destination Address Increment Register (DMDAIRn) DMA Channel Control Register (DMCCRn) DMA Channel Status Register (DMCSRn) 8-18 Chapter 8 DMA Controller “A” +08 +10 +18 +20 +28 +30 +38 “B” +08 +10 +18 +20 +28 +30 +38 “C” +08 +10 +18 +20 +28 +30 +38 “D” +08 +10 +18 +20 +28 +30 +38 “E” +08 +10 +18 +20 +28 +30 +38 Figure 8.3.5 DMA Command Descriptor Chain The sequence of Chain DMA transfer is as follows below. 1. Select DMA request signal When performing external I/O or internal I/O DMA, set the DMA Request Select field (PCFG.DMASEL) of the Pin Configuration Register. Set the Master Enable bit Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register. Structure of the DMA command Descriptor chain Construct the DMA Command Descriptor Chain in memory. Set the Count Register Set “0” to the DMA Count Register (DMCNTRn) . Sets the DMA Source Address Increment Register (DMSAIRn) and DMA destination Address Increment Register (MMDAIRn). Clear the DMA Channel Status Register (DMCSRn) Clear the status of the previous DMA transfer. Set the DMA Channel Control Register (DMCCRn). 2. 3. 4. 5. 6. 8-19 Chapter 8 DMA Controller 7. Initiate DMA transfer Setting the address of the DMA Command Descriptor at the beginning of the chain list in the DMA Chain Address Register (DMCHARn) automatically initiates DMA transfer. First, the value stored in each field of the DMA Command descriptor at the beginning of the Chain List is read to each corresponding DMA Channel register (Chain transfer), then DMA transfer is performed according to the read value. When a value other than “0” is stored in the DMA Chain Address Register (DMCHARn), data of the size stored in the DMA Count Register (DMCNTRn) is completely transferred, then the DMA Command Descriptor value of the memory address specified by the DMA Chain Address Register is read. In addition, if the Chain Address field value read the Descriptor 0, the DMA Chain Address Register value is not updated. All previous values (Data Command Descriptor Addresses with the value “0” in the Chain Address field when the values were read) are held. 0 Value judgement is performed when the lower 32 bits of the DMA Chain Address Register are rewritten. If the value is not “0” at this time, DMA transfer is automatically initiated. Therefore, please write to the upper 32 bits first when writing to the DMA Chain Address Register using 32bit Store instructions. 8. Signal completion Set the Normal Chain End bit (NCHNC) of the DMA Channel Status Register (DMCSRn) when DMA data transfer of all Descriptor Chains is complete. An interrupt is signalled if the Chain End Interrupt Enable bit (INTENC) of the DMA Channel Control Register (DMCCRn) is set at this time. In addition, the Normal Transfer End bit (NTRNFC) of the DMA Channel Status Register (DMCSRn) is set each time DMA data transfer specified by each DMA Command Descriptor ends normally. An interrupt is signalled if the Transfer End Interrupt Enable bit (INTENT) of the DMA Channel Control Register (DMCCRn) is set at this time. If an error is detected during DMA transfer, the error cause is recorded in the lower four bits of the DMA Channel Status register and transfer is interrupted. An interrupt is signalled if the Error Interrupt Enable bit (INTENE) of the DMA Channel Control Register is set. 8.3.11 Dynamic Chain Operation It is possible to add DMA Command Descriptor chains to the DMA Command Descriptor chain while Chain DMA transfer is in progress. This is performed according to the following procedure. 1. Construct the DMA Command Descriptor chain Construct the DMA Command Descriptor chain to be added to memory. Add a DMA Command Descriptor chain Substitute the address of the Command Descriptor at the beginning of the Descriptor Chain to be added into the Chain Address field of the Descriptor at the end of the DMA Command Descriptor chain that is currently performing DMA transfer. Check the Chain Enable bit Read the value of the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn). If that value is “0”, then write the Chain Address field value of the DMA Command Descriptor that is indicated by the address stored in the DMA Chain Address Register (DMCHARn). 2. 3. 8-20 Chapter 8 DMA Controller 8.3.12 Interrupts An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition, there are completion interrupts for when transfer ends normally and error interrupts for when transfer ends abnormally for each channel. When an interrupt occurs, then the bit that corresponds to either the Normal Interrupt Status field (DIS[3:0]) or the Error Interrupt Status field (EIS[3:0]) of the DMA Master Control Register (DMMCR) is set. Figure 8.3.6 shows the relationship between the Status bit and Interrupt Enable bit for each interrupt cause. Refer to the explanation for each Status bit for more information regarding each information cause. DMCCRn.INTENC DMCSRn.NCHNC DMCCRn.INTENT DMCSRn.NTRNFC DMMCR.DIS[n] Interrupt Controller (Interrupt No. 10 – 13) DMCSRn.STLXFER DMCCRn.INTENE DMMCR.EIS[n] DMCSRn.CFERR DMCSRn.CHERR DMCSRn.DESERR DMCSRn.SORERR DMCSRn.ABCHC Figure 8.3.6 DMA Controller Interrupt Signal 8.3.13 Transfer Stall Detection Function If the period from when a certain channel last performs internal bus access to when the next internal bus access is performed exceeds the Transfer Stall Detection Interval field (STLTIME) of the DMA Channel Control Register (DMCCRn), the Transfer Stall Detection bit (STLXFER) of the DMA Channel Status Register (DMCSRn) is set. An error interrupt is signalled if the Error Interrupt Enable bit (DMCCRn.INTENE) is set. In contrast to other error interrupts, DMA transfer is not stopped. Normal DMA transfer is executed if bus ownership can be obtained. Furthermore, clearing the Transfer Stall Detection field (STLXFER) resumes transfer stall detection as well. Setting the Transfer Stall Detection Interval field (STLTIME) to “000” disables the Transfer Stall Detection function. 8-21 Chapter 8 DMA Controller 8.3.14 Arbitration Among DMA Channels The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the round robin method and the fixed priority method. (See Figure 8.3.7.) The Round Robin Priority bit (RRPT) of the DMA Master Control Register (DMMCR) selects the priority method. • Fixed priority (DMMCR.RRPT = 0) As shown below, Channel 0 has the highest priority and Channel 3 has the lowest priority. CH0 > CH1 > CH2 > CH3 • Round Robin method (DMMCR.RRPT = 1) The last channel to perform DMA transfer has the lowest priority. • • • • After CH0 DMA transfer execution: CH1 > CH2 > CH3 > CH0 After CH1 DMA transfer execution: CH2 > CH3 > CH0 > CH1 After CH2 DMA transfer execution: CH3 > CH0 > CH1 > CH2 After CH3 DMA transfer execution: CH0 > CH1 > CH2 > CH3 Channel 0 Channel 1 Channel 2 Channel 3 a) Fixed Priority is selected Channel 0 Channel 3 Channel 2 b) Round Robin Priority is selected Channel 1 Figure 8.3.7 DMA Channel Arbitration 8.3.15 Restrictions in Access to PCI Bus The PCI Controller detects a bus error if the DMA Controller performs one of the following accesses to the PCI Bus. • • • • Burst transfer exceeding 8 double words (PCICSTATUS.TLB) Address Increment value –8 Burst transfer (PCICSTATUS.NIB) Address Increment Value 0 Burst transfer (PCICSTATUS.ZIB) Dual Address Burst transfer when the setting for DMSARn, DMDARn, or DMCNTRn is not a double word boundary (PCICSTATUS.IAA) In addition, Single Address transfers between an external I/O device and the PCI Bus are not supported. Data transfer is not performed, but no error is detected. 8-22 Chapter 8 DMA Controller 8.4 DMA Controller Registers Table 8.4.1 DMA Controller 0 Registers Offset Address 0xB000 0xB008 0xB010 0xB018 0xB020 0xB028 0xB030 0xB038 0xB040 0xB048 0xB050 0xB058 0xB060 0xB068 0xB070 0xB078 0xB080 0xB088 0xB090 0xB098 0xB0A0 0xB0A8 0xB0B0 0xB0B8 0xB0C0 0xB0C8 0xB0D0 0xB0D8 0xB0E0 0xB0E8 0xB0F0 0xB0F8 0xB148 0xB150 Bit Width 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Mnemonic DM0CHAR0 DM0SAR0 DM0DAR0 DM0CNTR0 DM0SAIR0 DM0DAIR0 DM0CCR0 DM0CSR0 DM0CHAR1 DM0SAR1 DM0DAR1 DM0CNTR1 DM0SAIR1 DM0DAIR1 DM0CCR1 DM0CSR1 DM0CHAR2 DM0SAR2 DM0DAR2 DM0CNTR2 DM0SAIR2 DM0DAIR2 DM0CCR2 DM0CSR2 DM0CHAR3 DM0SAR3 DM0DAR3 DM0CNTR3 DM0SAIR3 DM0DAIR3 DM0CCR3 DM0CSR3 DM0MFDR DM0MCR Register Name DMA Chain Address Register 0 DMA Source Address Register 0 DMA Destination Address Register 0 DMA Count Register 0 DMA Source Address Increment Register 0 DMA Destination Address Increment Register 0 DMA Channel Control Register 0 DMA Channel Status Register 0 DMA Chain Address Register 1 DMA Source Address Register 1 DMA Destination Address Register 1 DMA Count Register 1 DMA Source Address Increment Register 1 DMA Destination Address Increment Register 1 DMA Channel Control Register 1 DMA Channel Status Register 1 DMA Chain Address Register 2 DMA Source Address Register 2 DMA Destination Address Register 2 DMA Count Register 2 DMA Source Address Increment Register 2 DMA Destination Address Increment Register 2 DMA Channel Control Register 2 DMA Channel Status Register 2 DMA Chain Address Register 3 DMA Source Address Register 3 DMA Destination Address Register 3 DMA Count Register 3 DMA Source Address Increment Register 3 DMA Destination Address Increment Register 3 DMA Channel Control Register 3 DMA Channel Status Register 3 DMA Memory Fill Data Register DMA Master Control Register 8-23 Chapter 8 DMA Controller Table 8.4.2 DMA Controller 1 Registers Offset Address 0xB800 0xB808 0xB810 0xB818 0xB820 0xB828 0xB830 0xB838 0xB840 0xB848 0xB850 0xB858 0xB860 0xB868 0xB870 0xB878 0xB880 0xB888 0xB890 0xB898 0xB8A0 0xB8A8 0xB8B0 0xB8B8 0xB8C0 0xB8C8 0xB8D0 0xB8D8 0xB8E0 0xB8E8 0xB8F0 0xB8F8 0xB948 0xB950 Bit Width 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Mnemonic DM1CHAR0 DM1SAR0 DM1DAR0 DM1CNTR0 DM1SAIR0 DM1DAIR0 DM1CCR0 DM1CSR0 DM1CHAR1 DM1SAR1 DM1DAR1 DM1CNTR1 DM1SAIR1 DM1DAIR1 DM1CCR1 DM1CSR1 DM1CHAR2 DM1SAR2 DM1DAR2 DM1CNTR2 DM1SAIR2 DM1DAIR2 DM1CCR2 DM1CSR2 DM1CHAR3 DM1SAR3 DM1DAR3 DM1CNTR3 DM1SAIR3 DM1DAIR3 DM1CCR3 DM1CSR3 DM1MFDR DM1MCR Register Name DMA Chain Address Register 0 DMA Source Address Register 0 DMA Destination Address Register 0 DMA Count Register 0 DMA Source Address Increment Register 0 DMA Destination Address Increment Register 0 DMA Channel Control Register 0 DMA Channel Status Register 0 DMA Chain Address Register 1 DMA Source Address Register 1 DMA Destination Address Register 1 DMA Count Register 1 DMA Source Address Increment Register 1 DMA Destination Address Increment Register 1 DMA Channel Control Register 1 DMA Channel Status Register 1 DMA Chain Address Register 2 DMA Source Address Register 2 DMA Destination Address Register 2 DMA Count Register 2 DMA Source Address Increment Register 2 DMA Destination Address Increment Register 2 DMA Channel Control Register 2 DMA Channel Status Register 2 DMA Chain Address Register 3 DMA Source Address Register 3 DMA Destination Address Register 3 DMA Count Register 3 DMA Source Address Increment Register 3 DMA Destination Address Increment Register 3 DMA Channel Control Register 3 DMA Channel Status Register 3 DMA Memory Fill Data Register DMA Master Control Register 8-24 Chapter 8 DMA Controller 8.4.1 DMA Master Control Register (DM0MCR, DM1MCR) Offset address: DMAC0 0xB150, DMAC1 0xB950 This register controls the entire DMA Controller. 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 EIS[3:0] R 0000 15 14 FIFVC 13 FIFWP R 000 11 10 FIFRP R 000 28 27 DIS[3:0] R 0000 8 7 RSFIF R/W 0 6 FIFUM[3:0] R/W 0000 3 24 23 Reserved 21 20 FIFVC R 0000000 2 1 0 : Type : Initial value 16 32 48 Reserved RRPT MSTEN R/W 0 R/W 0 : Type : Initial value Bit 63:32 31:28 Mnemonic EIS[3:0] Field Name Reserved Error Interrupt Status Description Error Interrupt Status [3:0] (Default: 0x0) These four bits indicate the error interrupt status of each channel. EIS[n] corresponds to channel n. 1: There is an error interrupt in the corresponding channel. 0: There is no error interrupt in the corresponding channel. Done Interrupt Status [3:0] (Default: 0x0) These four bits indicate the transfer completion (transfer complete or chain ended) interrupt status of each channel. DIS[n] corresponds to channel n. 1: There is a transfer completion interrupt in the corresponding channel. 0: There is no transfer completion interrupt in the corresponding channel. FIFO Valid Entry Count (Default: 0000000) These read only bits indicate the byte count of data that were written to FIFO but not read out from the FIFO. FIFO Write Pointer (Default: 000) These read only bits indicate the next write position in FIFO. This is a diagnostic function. FIFO Read Pointer (Default: 000) These read only bits indicate the next read position in FIFO. This is a diagnostic function. Reset FIFO (Default: 0) This bit is used for resetting FIFO. When this bit is set to “1”, the FIFO read pointer, FIFO write pointer and FIFO valid entry count are initialized to “0”. If an error occurs during DMA transfer, use this bit when data remains in the FIFO (when the FIFO Valid entry Count Field is not “0”) to initialize the FIFO. Read/Write ⎯ R 27:24 DIS[3:0] Normal Completion Interrupt Status R 23:21 20:14 FIFVC Reserved FIFO Valid Entry Count FIFO Write Pointer FIFO Read Pointer Reset FIFO R ⎯ 13:11 FIFWP R 10:8 FIFRP R 7 RSFIF R/W Figure 8.4.1 DMA Master Control Register (1/2) 8-25 Chapter 8 DMA Controller Bit 6:3 Mnemonic FIFUM[3:0] Field Name FIFO Use Enable [3:0] Description FIFO Use Enable [3:0] (Default: 0x0) Each channel specifies whether to use 8-double word FIFO in Dual Address transfer. FIFUM[n] corresponds to channel n. Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. Round Robin Priority (Default: 0) Specifies the method for determining priority among channels. 1: Round Robin method. Priority of the last channel used is the lowest, and the next previous channel has the next lowest priority. Round robin is in the order Channel 0 > Channel 1 > Channel > Channel 3. 0: Fixed Priority. Priority is fixed in the order Channel 0 > Channel 1 > Channel 2 > Channel 3. Master Enable (Default: 0) This bit enables the DMA Controller. 1: Enable 0: Disable Note: If the entire DMA Controller is disabled, then all internal logic including the Bus Interface Logic and State Machine are reset. Read/Write R/W 2 1 RRPT Reserved Round Robin Priority R/W ⎯ 0 MSTEN Master Enable R/W Figure 8.4.1 DMA Master Control Register (2/2) 8-26 Chapter 8 DMA Controller 8.4.2 DMA Channel Control Register (DM0CCRn, DM1CCRn) Offset address: DMAC0 0xB030 (ch. 0) / 0xB070 (ch. 1) / 0xB0B0 (ch. 2) / 0xB0F0 (ch. 3) DMAC1 0xB830 (ch. 0) / 0xB870 (ch.1 ) / 0xB8B0 (ch. 2) / 0xB8F0 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 30 29 28 27 LE R/W ⎯ 11 26 25 24 23 22 21 20 19 18 17 16 EXTRQ 48 32 Reserved IMMCHN USEXFSZ DBINH SBINH CHRST RVBYTE ACKPOL REQPL EGREQ CHDN DNCTL R/W 00 2 1 R/W 0 15 13 R/W 0 12 R/W 0 10 R/W 0 9 R/W 1 8 R/W 0 7 R/W 0 6 R/W 0 5 SMPCHN R/W 0 4 R/W 0 R/W 0 0 : Type : Initial value STLTIME/INTRQD R/W 000 INTENE INTENC INTENT CHNEN XFACT Reserved XFSZ R/W 000 MEMIO SNGAD R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 : Type : Initial value Bit 63:32 29 28 Mnemonic IMMCHN USEXFSZ Field Name Reserved Immediate Chain Transfer Set Size Mode Immediate Chain (Default: 0) Always set this bit to “1”. Description Read/Write ⎯ R/W R/W Use Transfer Set Size (Default: 0) Selects the DMA channel operation mode during Burst DMA transfer. Refer to “8.3.7.2 Burst Transfer During Single Address Transfer” and “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. 1: The DMA Controller always transfers the amount of data set in DMCCRn.XFSZ for each bus operation. Since alignment to the boundary of the DMCCRn.XFSZ in the address is not forced when in this mode, transfers that exceed 32-double-word boundaries are divided into two operations. 0: The DMA Controller calculates the transfer size so the address set in DMSARn and DMDARn (only during Dual Address transfer) can be aligned to the boundary of the size set in DMCCRn.XFSZ, then transfers data according to that size. Note: In Dual Address Transfer mode, programming this bit to 1 is valid only when both the contents of the DMSARn and the DMDARn are on doubleword boundaries and the contents of the DMCNTRn is a multiple of eight bytes. Little Endian (Default: value that is the opposite of the G-Bus Endian (CCFG.ENDIAN) This bit sets the Endian of the channel. Please use the default value as is. 1: Channel operates in the Little Endian mode 0: Channel operates in the Big Endian mode 27 LE Little Endian R/W Figure 8.4.2 DMA Channel Control Register (1/4) 8-27 Chapter 8 DMA Controller Bit 26 Mnemonic DBINH Field Name Destination Burst Inhibit Description Destination Burst Inhibit (Default: 0) During Dual Address transfer, this bit sets whether to perform Burst transfer or Single transfer on a Write cycle to the address set from FIFO to DMDARn when Burst transfer is set by DMCCRn.XFSZ. Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. The settings of this bit have no effect during Single Address transfers. 1: Multiple Single transfers are executed. 0: Burst transfer is executed. Source Burst Inhibit (Default: 0) During Dual Address transfer, this bit sets whether to perform Burst transfer or Single transfer on a Read cycle to the FIFO from the address set to DMSARn when Burst transfer is set by DMCCRn.XFSZ. Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. The settings of this bit have no effect during Single Address transfers. 1: Multiple Single transfers are executed. 0: Burst transfer is executed. Channel Reset (Default: 1) This bit is used fo initializing channels. The DMCCRn.XFACT, DMCCRn.CHNEN, and DMCSRn bits are all cleared. In addition, all channel logic and interrupts from channels are cleared and bus ownership requests to the DMA Channel Arbiter are also reset. The software must clear this bit before operating a channel. 1: Reset channel 0: Enable channel Reverse Bytes (Default: 0) This bit specifies whether to reverse the byte order during a Dual Address transfer when the Transfer Setting Size field (DMCCRn.XFSZ) setting is 8 bytes or more. Refer to “8.3.8.3 Double Word Byte Swapping” for more information. 1: Reverses the byte order. 0: Does not reverse the byte order. Acknowledge Polarity (Default: 0) Specifies the polarity of the DMAACK[n] signal. 1: Asserts when the DMAACK[n] signal is High 0: Asserts when the DMAACK[n] signal is Low Request Polarity (Default: 0) Specifies the polarity of the DMAREQ[n] signal. 1: Asserts when the DMAREQ[n] signal is High. 0: Asserts when the DMAREQ[n] signal is Low. Edge Request (Default: 0) Specifies the method for detecting DMA requests by the DMAREQ[n] signal. 1: DMAREQ[n] signal is Edge Detect. 0: DMAREQ[n] signal is Level Detect. Chain Done (Default: 0) Selects control by the DMADONE* signal. See “8.3.3.4 DMA Controller” for more information. 1: Assertion of the DMADONE* signal controls the overall Chain DMA transfer. 0: Assertion of the DMADONE* signal controls DMA transfer according to the DMA Channel Register setting at that time. Done Control (Default: 00) Specifies the input/output mode of the DMADONE* signal. Refer to “8.3.3.4 DMADONE* Signal” for more information. 00: DMADONE* signal becomes the input signal, but input is ignored. 01: DMADONE* signal becomes the input signal. 10: DMADONE* signal becomes the output signal. 11: DMADONE* signal becomes the open drain input/output signal. Read/Write R/W 25 SBINH Source Burst Inhibit R/W 24 CHRST Channel Reset R/W 23 REVBYTE Reverse Byte R/W 22 ACKPOL Acknowledge Polarity R/W 21 REQPL Request Polarity R/W 20 EGREQ Edge Request R/W 19 CHDN Chain Complete R/W 18:17 DNCTL DONE Control R/W Figure 8.4.2 DMA Channel Control Register (2/4) 8-28 Chapter 8 DMA Controller Bit 16 Mnemonic EXTRQ Field Name External Request Description External Request (Default: 0) Sets the Request Transfer mode. 1: I/O DMA transfer mode This bit is used by the External I/O DMA Transfer mode and the Internal I/O DMA Transfer mode. A channel requests internal bus ownership when the I/O device asserts the DMA request signal. 0: Memory Transfer mode This bit is used by the Memory-Memory Copy Transfer mode and the Memory Fill Transfer mode. A channel requests internal bus ownership when the value of DMCSRn.WAITC becomes “0”. • W hen in the I/O DMA Transfer mode (DMCCRn.EXTRQ is “1”) Stalled Transfer Detect Time (Default: 000) Sets the detection interval for a lack of bus ownership. If this channel n releases bus ownership then the interval it does not have ownership exceeds the clock count set by this field, then DMCSRn.STLXFER is set to “1”. Refer to “8.3.13 Transfer Stall Detection Function” for more information. 000: Does not detect stalled transfers. 001: Sets 960 (15 × 64) clocks as the detection interval 010: Sets 4032 (63 × 64) clocks as the detection interval 011: Sets 16320 (255 × 64) clocks as the detection interval 100: Sets 65472 (1023 × 64) clocks as the detection interval 101: Sets 262080 (4095 × 64) clocks as the detection interval 110: Sets 1048512 (16383 × 64) clocks as the detection interval 111: Sets 4194240 (65535 × 64) clocks as the detection interval • W hen in the Memory Transfer mode (DMCCRn.EXTRQ is “0”) Internal Request Delay (Default: 000) Sets the delay time from when bus ownership is released to the next bus ownership request. Bus ownership is released, the set delay time elapses, then a bus ownership request is generated from the channel. 000: Always requests bus ownership when this channel is active. (Bus ownership is released after bus operation ends) 001: Set 16 clocks as the delay time 010: Set 32 clocks as the delay time 011: Set 64 clocks as the delay time 100: Set 128 clocks as the delay time 101: Set 256 clocks as the delay time 110: Set 512 clocks as the delay time 111: Set 1024 clocks as the delay time Read/Write R/W 15:13 STLTIME / INTRQD Transfer Stall Detection Interval/Internal Request Delay R/W 12 INTENE Error Interrupt Enable Interrupt Enable on Error (Default: 0) Enables interrupts when the Error End bit (DMCSRn.ABCHC) or the Transfer Stall Detection bit (DMCSRn.STLXFER) is set. 1: Generates interrupts. 0: Does not generate interrupts. Interrupt Enable on Chain Done (Default: 0) This bit enables interrupts when the Chain End bit (DMCSRn.NCHNC) is set. 1: Generate interrupts. 0: Do not generate interrupts. Interrupt Enable on Transfer Done (Default: 0) This bit enables interrupts when the Transfer End bit (DMCSRn.NTRNFC) is set. 1: Generate interrupts. 0: Do not generate interrupts. R/W 11 INTENC Chain End Interrupt Enable R/W 10 INTENT Transfer End Interrupt Enable R/W Figure 8.4.2 DMA Channel Control Register (3/4) 8-29 Chapter 8 DMA Controller Bit 9 Mnemonic CHNEN Field Name Chain Enable Description Chain Enable (Default: 0) This bit indicates whether Chain operation is being performed. Read Only. This bit is cleared when either the Master Enable bit (DMMCR.MSTEN) is cleared or the Channel Reset bit (DMCCRn.CHRST) is set. This bit is set if a value other than “0” is set when the CPU writes to the DMA Chain Address Register (DMCHARn) or when a Chain transfer writes DMA Command Descriptor. This bit is then cleared when “0” is set to the DMA Chain Address Register (DMCHARn). 1: If transfer completes due to the current DMA Channel Register setting, a DMA Command Descriptor is loaded in the DMA Channel Register from the specified DMA Chain Address Register (DMCHARn) address, then DMA transfer continues. 0: Further transfer does not start even if transfer completes due to the current DMA Channel Register setting. Transfer Active (Default: 0) DMA transfer is performed according to the DMA Channel Register setting when this bit is set. This bit is automatically set when a value other than “0” is set in the DMA Chain Address Register (DMCHARn). DMA transfer is then initiated. This bit is automatically cleared either when DMA transfer ends normally it is stopped due to an error. 1: Perform DMA transfer. 0: Do not perform DMA transfer. Simple Chain (Default: 0) This bit selects the DMA Channel Register that loads data from DMA Command Descriptors during Chain DMA transfer. 1: Data is only loaded to the four following DMA Channel Registers: the Chain Address Register (DMCHARn), the Source Address Register (DMSARn), the Destination Address Register (DMDARn), and the Count Register (DMCNTRn). 0: Data is loaded to all eight DMA Channel Registers. Transfer Set Size (Default: 000) These bits set the transfer data size of each bus operation in the internal bus. When the transfer set size is set to four double words or greater, the data size actually transferred during a single bus operation does not always match the transfer set size. Refer to “8.3.7.2 Burst Transfer During Single Address Transfer” and “8.3.8.2 Burst Transfer During Dual Address Transfer” for more information. 000: 1 byte 001: 2 byte 010: 4 byte 011: 8 bytes (1double word) 100: 4 double words 101: 8 double words 110: 16 double words (Single Address transfer only) 111: 32 double words (Single Address transfer only) Memory to I/O (Default: 0) This bit specifies the transfer direction during Single Address transfer (DMCCRn.SNGAD = 1). Clear this bit when in the Memory Fill Transfer mode. The setting of this bit is ignored when Dual Address transfer is set (DMCCRn.SNGAD = 0). 1: From memory to I/O 0: From I/O to memory Single Address (Default: 0) This bit specifies whether the transfer method is Single Address transfer or Dual Address transfer. 1: Single Address transfer 0: Dual Address transfer Read/Write R 8 XFACT Transfer Active R/W 7:6 5 SMPCHN Reserved Simple Chain R/W ⎯ 4:2 XFSZ Transfer Set Size R/W 1 MEMIO Memory to I/O R/W 0 SNGAD Single Address R/W Figure 8.4.2 DMA Channel Control Register (4/4) 8-30 Chapter 8 DMA Controller 8.4.3 DMA Channel Status Register (DM0CSRn, DM1CSRn)) Offset Address: DMAC0 0xB038 (ch. 0) / 0xB078 (ch. 1) / 0xB0B8 (ch. 2) / 0xB0F8 (ch. 3) DMAC1 0xB838 (ch. 0) / 0xB878 (ch. 1) / 0xB8B8 (ch. 2) / 0xB8F8 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 WAITC R 0x0000 15 Reserved 11 10 CHNEN 48 32 16 : Type : Initial value 6 5 4 3 2 1 0 9 STLXFER 8 7 XFACT ABCHC NCHNC NTRNFC EXTDN CFERR CHERR DESERR SORERR R 0 R/W1C 0 R 0 R 0 R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C : Type : Initial value 0 0 0 0 0 0 0 Bit 63:32 31:16 Mnemonic WAITC Field Name Reserved Wait Counter Description Wait Counter (Default: 0x0000) This is a diagnostic function. • I/O DMA transfer mode (DMCCRn.EXTRQ = “1”) This counter is decremented by 1 at each 64 G-Bus cycles. After channel n releases bus ownership, this counter sets the default (the value that is the detection interval clock cycle count set by the Transfer Stall Detection Interval field (DMCCRn.STLTIME) divided by 64). The Transfer Stall Detect bit (DMCSRn.STLXFER) is set when the interval during which bus ownership is not held reaches the set clock cycle. The counter is reset to the default and stops counting. Clearing the Transfer Stall Detect bit (DMCSRn.STLXFER) resumes the count and starts stall detection. • Memory transfer mode (DMCCRn.EXTRQ = “0”) This counter is decremented by 1 at each G-Bus cycle. After bus ownership is released, the counter is set to the delay clock cycle count set by the Internal Request Delay field (DMCCRn.INTRQD). When the counter reaches “0” the count stops and channel n requests bus ownership. Chain Enable (Default: 0) This value is a copy of the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn). Stalled Transfer Detect (Default: 0) This bit indicates whether the interval during which bus ownership is not held exceeds the value set by the Transfer Stall Detect Interval field (DMCCRn.STLTIME) after bus ownership is released when in the I/O DMA transfer mode. 1: Indicates that the interval during which bus ownership was not held exceeds the DMCCRn.STLTIME setting. 0: The interval during which bus ownership was not held did not exceed the setting since this bit was last cleared. Read/Write ⎯ R 15:11 10 CHNEN Reserved Chain Enable R ⎯ 9 STLXFER Transfer Stall Detect R/W1C Figure 8.4.3 DMA Channel Status Register (1/2) 8-31 Chapter 8 DMA Controller Bit 8 Mnemonic XFACT Field Name Transfer Active Description Transfer Active (Default: 0) This value is a copy of the Transfer Active bit (XFACT) of the DMA Channel Control Register (DMCCRn). Error Completion (Default: 0) This bit indicates whether an error occurred during DMA transfer. This bit indicates the logical sum of the four error bits (CFERR, CHERR, DESERR, SORERR) in DMCSRn[3:0]. 1: DMA transfer ends due to an error. 0: No error occurred since this bit was last cleared. Normal Chain Completion (Default: 0) When performing chain DMA transfer, This bit indicates whether all DMA data transfers in the DMA Descriptor chain are complete. 1: All DMA data transfers in the DMA Descriptor chain ended normally. Or, DMA transfer that did not use a DMA Descriptor chain ended normally. 0: DMA transfer has not ended normally since this bit was last cleared. Normal Transfer Completion (Default: 0) This bit indicates whether DMA transfer ended according to the current DMA Channel Register setting. 1: DMA transfer ended normally. 0: DMA transfer has not ended since this bit was last cleared. External Done Asserted (Default: 0) This bit indicates whether an external I/O device asserted the DMADONE* signal. When the DMADONE* signal is set to bidirectional, this bit is also set when the TX4938 asserts the DMADONE* signal. 1: DMADONE* signal was asserted. 0: DMADONE* signal was not asserted. Configuration Error (Default: 0) Indicates whether an illegal register setting was made. 1: There was a configuration error. 0: There was no configuration error. Chain Bus Error (Default: 0) This bit indicates whether a bus error occurred while reading a DMA Command Descriptor. 1: Bus error occurred. 0: No bus error occurred. Destination Bus Error (Default: 0) This bit indicates whether a bus error occurred during a destination bus Write operation (a Write to a set DMDARn address). 1: Bus error occurred. 0: No bus error occurred. Source Bus Error (Default: 0) This bit indicates whether a bus error occurred during either a source bus Read or Write operation (A Read or Write to a set DMSARn address). 1: Bus error occurred. 0: No bus error occurred. Read/Write R 7 ABCHC Error Complete R 6 NCHNC Chain Complete R/W1C 5 NTRNFC Transfer Complete R/W1C 4 EXTDN External DONE Asserted R/W1C 3 CFERR Configuration Error R/W1C 2 CHERR Chain Bus Error R/W1C 1 DESERR Destination Error R/W1C 0 SORERR Source Bus Error R/W1C Figure 8.4.3 DMA Channel Status Register (2/2) 8-32 Chapter 8 DMA Controller 8.4.4 DMA Source Address Register (DM0SARn, DM1SARn) Offset Address: DMAC0 0xB008 (ch. 0) / 0xB048 (ch. 1) / 0xB088 (ch. 2) / 0xB0C8 (ch. 3) DMAC1 0xB808 (ch. 0) / 0xB848 (ch. 1) / 0xB888 (ch. 2) / 0xB8C8 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved 36 35 SADDR[35:32] R/W ⎯ 31 SADDR[31:16] R/W ⎯ 15 SADDR[15:0] R/W ⎯ : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 48 Bits 63:36 35:0 Mnemonic ⎯ SADDR Field Name Reserved Source Address Description Source Address (Default: Undefined) This field sets the physical address of the transfer source during Dual Address transfer. This field sets the physical address of memory access during Single Address transfer. This field is used for either Memory-to-I/O or I/O-to-Memory transfers. Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. During Burst transfer, the value changes once for each bus operation only by the size that was transferred. During Single transfer, the value only changes by the value specified by the DMA Source Address Increment Register (DMSAIRn). Read/Write ⎯ R/W Figure 8.4.4 DMA Source Address Register 8-33 Chapter 8 DMA Controller 8.4.5 DMA Destination Address Register (DM0DARn, DM1DARn) Offset Address: DMAC0 0xB010 (ch. 0) / 0xB050 (ch. 1) / 0xB090 (ch. 2) / 0xB0D0 (ch. 3) DMAC1 0xB810 (ch. 0) / 0xB850 (ch. 1) / 0xB890 (ch. 2) / 0xB8D0 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved 36 35 DADDR[35:32] R/W ⎯ 31 DADDR[31:16] R/W ⎯ 15 DADDR[15:0] R/W ⎯ : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 48 Bit 63:36 35:0 Mnemonic DADDR Field Name Reserved Destination Address Description Destination Address (Default: undefined) This register sets the physical address of the transfer destination during Dual Address transfer. This register is ignored during Single Address transfer. Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. During Burst transfer, the value changes only by the size of data transferred during each single bus operation. During Single transfer, the value only changes by the value specified by the DMA Destination Address Increment Register (DMDAIRn). Read/Write ⎯ R/W Figure 8.4.5 DMA Destination Address Register 8-34 Chapter 8 DMA Controller 8.4.6 DMA Chain Address Register (DM0CHARn, DM1CHARn) Offset Address: DMAC0 0xB000 (ch. 0) / 0xB040 (ch. 1) / 0xB080 (ch. 2) / 0xB0C0 (ch. 3) DMAC1 0xB800 (ch. 0) / 0xB840 (ch. 1) / 0xB880 (ch. 2) / 0xB8C0 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved 36 35 CHADDR[35:32] R/W ⎯ 31 CHADDR[31:16] R/W ⎯ 15 CHADDR[15:3] R/W ⎯ 3 2 Reserved R/W : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 48 Bit 63:36 35:3 Mnemonic CHADDR Field Name Reserved Chain Address Description Chain Address (Default: undefined) When Chain DMA transfer is executed, this register sets the physical address of the next DMA Command Descriptor to be read. If DMA transfer according to the current Channel Register setting ends and the Chain Enable bit (DMCCRn.CHNEN) is set, then the DMA Command Descriptor is loaded in the Channel Register starting from the address indicated by this register. When a value other than “0” is set in this register, the Chain Enable bit (DMCCRn.CHNEN) and the Transfer Active bit (DMCCRn.XFACT) are set. When “0” is set in this register, only the Chain Enable bit (DMCCRn.CHNEN) is cleared. When the Chain Address field value reads a DMA Command Descriptor of 0, the value of this register is not updated and the value before that one (address of the Data Command Descriptor when the value of the Chain Address field being read was “0”) is held. Read/Write ⎯ R/W 2:0 Reserved R/W Figure 8.4.6 DMA Chain Address Register 8-35 Chapter 8 DMA Controller 8.4.7 DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn) Offset Address: DMAC0 0xB020 (ch. 0) / 0xB060 (ch. 1) / 0xB0A0 (ch. 2) / 0xB0E0 (ch. 3) DMAC1 0xB820 (ch. 0) / 0xB860 (ch. 1) / 0xB8A0 (ch. 2) / 0xB8E0 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 Reserved 24 23 SADINC[23:16] R/W ⎯ 15 SADINC[15:0] R/W ⎯ : Type : Initial value 0 : Type : Initial value 16 32 48 Bit 63:24 23:0 Mnemonic SADINC Field Name Reserved Source Address Increment Description Source Address Increment (Default: undefined) This field sets the increase/decrease value of the DMA Source Address Register (DMSARn). This value is a 24-bit two’s complement and indicates a byte count. Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. Read/Write ⎯ R/W Figure 8.4.7 DMA Source Address Increment Register 8-36 Chapter 8 DMA Controller 8.4.8 DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn) Offset Address: DMAC0 0xB028 (ch. 0) / 0xB068 (ch. 1) / 0xB0A8 (ch. 2) / 0xB0E8 (ch. 3) DMAC1 0xB828 (ch. 0) / 0xB868 (ch. 1) / 0xB8A8 (ch. 2) / 0xB8E8 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 Reserved 24 23 DADINC[23:16] R/W ⎯ 15 DADINC[15:0] R/W ⎯ : Type : Initial value 0 : Type : Initial value 16 32 48 Bit 63:24 23:0 Mnemonic DADINC Field Name Reserved Destination Address Increment Description Destination Address Increment (Default: undefined) This field sets the increase/decrease value of the DMA Destination Address Register (DMDARn). This value is a 24-bit two’s complement and indicates a byte count. Refer to “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. Read/Write ⎯ R/W Figure 8.4.8 DMA Destination Address Increment Register 8-37 Chapter 8 DMA Controller 8.4.9 DMA Count Register (DM0CNTRn, DM1CNTRn) Offset Address: DMAC0 0xB018 (ch. 0) / 0xB058 (ch. 1) / 0xB098 (ch. 2) / 0xB0D8 (ch. 3) DMAC1 0xB818 (ch. 0) / 0xB858 (ch. 1) / 0xB898 (ch. 2) / 0xB8D8 (ch. 3) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 Reserved 26 25 DMCNTR[25:0] R/W ⎯ 15 DMCNTR[15:0] R/W ⎯ : Type : Initial value 0 : Type : Initial value 16 32 48 Bit 63:26 25:0 Mnemonic DMCNTR Field Name Reserved Count Description Count Register (Default: undefined) This register sets the byte count that is transferred by the DMA Channel Register setting. The value is a 26-bit unsigned data that is decremented only by the size of the data transferred during a single bus operation. Refer to “8.3.7.1 Channel Register Settings During Single Address Transfer” and “8.3.8.1 Channel Register Settings During Dual Address Transfer” for more information. Read/Write ⎯ R/W Figure 8.4.9 DMA Count Register 8-38 Chapter 8 DMA Controller 8.4.10 63 MFD R/W ⎯ 47 MFD R/W ⎯ 31 MFD R/W ⎯ 15 MFD R/W ⎯ : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 : Type : Initial value DMA Memory Fiill Data Register (DM0MFDR, DM1MFDR) Offset Address: DMAC0 0xB148, DMAC1 0xB948 48 Bit 63:0 Mnemonic MFD Field Name Memory Fill Data Description Memory Fill Data (Default: undefined) This register, which stores double-word data written to memory when in the Memory Fill Transfer mode, is shared between all channels. Read/Write R/W Figure 8.4.10 DMA Memory Fill Data Register 8-39 Chapter 8 DMA Controller 8.5 Timing Diagrams This section contains timing diagrams for the external I/O DMA transfer mode. The DMAREQ[n] signals and DMAACK[n] signals in the timing diagrams are set to Low Active. 8.5.1 Single Address Single Transfer from Memory to I/O (32-bit ROM) SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* 1c040 00040 f 00000100 Figure 8.5.1 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit ROM) 8-40 Chapter 8 DMA Controller 8.5.2 Single Address Single Transfer from Memory to I/O (16-bit ROM) 00081 f 38080 00080 OE*/BUSSPRT* DATA [15:0] 0000 0100 DMAREQ[n] ADDR [19:0] DMAACK[n] CE* ACE* BWE* ACK* Figure 8.5.2 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 16-bit ROM) 8-41 DMADONE* SYSCLK SWE Chapter 8 DMA Controller 8.5.3 Single Address Single Transfer from I/O to Memory (32-bit SRAM) SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* f 00000100 0 f 1c040 00140 Figure 8.5.3 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SRAM) 8-42 Chapter 8 DMA Controller 8.5.4 Single Address Burst Transfer from Memory to I/O (32-bit ROM) 00043 00042 f 00041 CE* 1c040 00040 ACE* OE*/BUSSPRT* 00000100 fffffeff 00000108 fffffef7 ADDR [19:0] Figure 8.5.4 Single Address Burst Transfer from Memory to I/O (Burst Read of 4-word Data from 32-bit ROM) 8-43 DMADONE* DATA [31:0] SYSCLK SWE* BWE* ACK* DMAREQ[n] DMAACK[n] Chapter 8 DMA Controller 8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM) 00143 f f f f 00141 00140 0 OE*/BUSSPRT* SWE* BWE* f 00000100 ACE* ACK* CE* f fffffeff 0 00000108 00142 0 fffffef7 0 ADDR [19:0] Figure 8.5.5 Single Address Burst Transfer from I/O to Memory (Burst Write of 4-word Data from 32-bit SRAM) 8-44 DMADONE* DMAREQ[n] DMAACK[n] DATA [31:0] SYSCLK SYSCLK CE* 00680 00681 00682 00683 00684 00685 00686 00687 ADDR [19:0] 38080 ACE* OE*/BUSSPRT* SWE* f 00000900 fffff6ff 00000908 fffff6f7 0 f 0 f 0 f 0 f 0 00000910 f 0 fffff6ef f 0 00000918 f 0 fffff6e7 f Figure 8.5.6 Single Address Burst Transfer from I/O to Memory (Burst Write of 8-word Data to 32-bit SRAM) 8-45 BWE* DATA [31:0] ACK* DMAREQ[n] DMAACK[n] Chapter 8 DMA Controller DMADONE* Chapter 8 DMA Controller 8.5.6 Single Address Single Transfer from Memory to I/O (16-bit ROM) SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [15:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* f 0000 38080 00080 Figure 8.5.7 Single Address Single Transfer from Memory to I/O (Single Read from 16-bit ROM to 16-bit Data) 8-46 Chapter 8 DMA Controller 8.5.7 Single Address Single Transfer from I/O to Memory (16-bit SRAM) 00280 c f OE*/BUSSPRT* DATA [15:0] ACE* 0000 ADDR [19:0] f SYSCLK ACK* DMAREQ[n] SWE* BWE* CE* Figure 8.5.8 Single Address Single Transfer from I/O to Memory (Single Write of 16-bit Data to 16-bit SRAM) 8-47 DMADONE* DMAACK[n] Chapter 8 DMA Controller 8.5.8 Single Address Single Transfer from Memory to I/O (32-bit Half Speed ROM) 00041 SYSCLK 1c041 f OE*/BUSSPRT* ADDR [19:0] DATA [31:0] ACE* fffffeff ACK* SDCLK DMAREQ[n] CE* SWE* BWE* DMAACK[n] Figure 8.5.9 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit Half Speed ROM) 8-48 DMADONE* Chapter 8 DMA Controller 8.5.9 Single Address Single Transfer from I/O to Memory (32-bit Half Speed SRAM) 00140 0 f DATA [31:0] 00000100 SYSCLK 1c041 f OE*/BUSSPRT* DMAREQ[n] CE* ACE* SWE* BWE* ACK* DMAACK[n] Figure 8.5.10 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit Half Speed SRAM) ADDR [19:0] 8-49 DMADONE* SDCLK Chapter 8 DMA Controller 8.5.10 Single Address Single Transfer from Memory to I/O (64-bit SRAM) SDCLK CS* ADDR [19:5] RAS* CAS* WE* CKE* OE* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* ff 00 ff 0000 0040 Figure 8.5.11 Single Address Single Transfer from Memory to I/O (Single Read of 64-bit Data from 64-bit SDRAM) 8-50 Chapter 8 DMA Controller 8.5.11 Single Address Single Transfer from I/O to Memory (64-bit SDRAM) SDCLK CS* ADDR [19:5] RAS* CAS* WE* CKE* OE* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* ff 00 ff 0001 0040 Figure 8.5.12 Single Address Single Transfer from I/O to Memory (Single Write of 64-bit Data to 64-bit SDRAM) 8-51 Chapter 8 DMA Controller 8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE* Signal is Set to Output SDCLK CS* ADDR [19:5] RAS* CAS* WE* CKE* OE*/BUSSPRT* DQM [7:0] DATA [63:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* ff 00 ff 0000 0041 Figure 8.5.13 Single Address Single Transfer from Memory to I/O (Single Read of 64-bit Data from 64-bit SDRAM) 8-52 Chapter 8 DMA Controller 8.5.13 Single Address Single Transfer from Memory to I/O (32-bit SDRAM) ff 0000 0080 ff DATA [31:0] DQM [7:0] f0 00000100 0081 fffffeef DMAREQ[n] DMAACK[n] SDCLK OE*/BUSSPRT* Figure 8.5.14 Single Address Single Transfer from Memory to I/O (Single Read of 32-bit Data from 32-bit SDRAM) ADDR [19:5] 8-53 DMADONE* WE* RAS* CAS* CKE* ACK* CS* Chapter 8 DMA Controller 8.5.14 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) SDCLK CS* ADDR [19:5] RAS* CAS* WE* CKE* OE* DQM [7:0] DATA [31:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* ff f0 00000100 ff ff 0002 0080 0081 Figure 8.5.15 Single Address Single Transfer from I/O to Memory (Single Write of 32-bit Data to 32-bit SDRAM) 8-54 Chapter 8 DMA Controller 8.5.15 External I/O Device – SRAM Dual Address Transfer SYSCLK CE* (SRAM) CE* (I/O device) ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31 : 0] ACK* DMAREQ[n] DMAACK[n] DMADONE* f VXVXVXVXVXVXVXV f f f f f f f f Valid Valid Valid Valid Valid Valid Valid Valid Figure 8.5.16 Dual Address Transfer from External I/O Device to SRAM (8-word Burst Transfer to 32-bit Bus SRAM) 8-55 Chapter 8 DMA Controller SYSCLK CE* (SRAM) CE* (I/O device) ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* DATA [31:0] ACK* DMAREQ[n] DMAACK[n] DMADONE* V V f V V 0 Valid f 0 Valid f 0 Valid f 0 Valid f Figure 8.5.17 Dual Address Transfer from SRAM to External I/O Device (4-word Burst Transfer from 32-bit Bus SRAM) 8-56 Chapter 8 DMA Controller 8.5.16 External I/O Device – SDRAM Dual Address Transfer SDCLK/SYSCLK CS* CE* ADDR [19:0] RAS* CAS* WE* CKE OE*/BUSSPRT* DQM[7:0] DATA [31:0] ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* f V X V X ff V X V Valid f0 V V V ff Figure 8.5.18 Dual Address Transfer from External I/O Device to SDRAM (4-word Burst Transfer to 32-bit SDRAM) 8-57 Chapter 8 DMA Controller SDCLK/SYSCLK CS* CE* ADDR [19:0] RAS* CAS* WE* CKE OE*/BUSSPRT* DQM[7:0] DATA [31:0] ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* f f f f f f f f f ff f0 ff Valid Valid Valid Valid Valid Valid Valid Valid V Figure 8.5.19 Dual Address Transfer from SDRAM to External I/O Device (8-word Burst Transfer from 32-bit SDRAM) 8-58 Chapter 8 DMA Controller 8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer SDCLK/SYSCLK CS* CE* ADDR[19:0] RAS* CAS* WE* CKE OE*/ BUSSPRT* DQM[7:0] DATA[31:0] ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* f V V ff V V f0 Valid V V V ff Figure 8.5.20 Dual Address Transfer from External I/O Device (Non-Burst) to SDRAM (4-word Burst Transfer to 32-bit SDRAM: Set DMCCRn.SBINH to “1”) 8-59 Chapter 8 DMA Controller SDCLK/SYSCLK CS* CE* ADDR[19:0] RAS* CAS* WE* CKE OE*/BUSSPRT* DQM[7:0] DATA[31:0] ACK* ACE* SWE* BWE* DMAREQ[n] DMAACK[n] DMADONE* f 0 f 0 f 0 f 0 f ff f0 VVVV Valid ff Valid Valid Valid Figure 8.5.21 Dual Address Transfer from SDRAM to External I/O Device (4-word Burst Transfer from 32-bit SDRAM: Set DMCCRn.DBINH to “1”) 8-60 Chapter 9 SDRAM Controller 9. 9.1 SDRAM Controller Characteristics The SDRAM Controller (SDRAMC) generates the control signals required to interface with the SDRAM. There are a total of four channels, which can each be operated independently. The SDRAM Controller supports various bus configurations and a memory size of up to 2 GB. The SDRAM has the following characteristics. • • • • • • • Memory clock (SDCLK) frequency: 50 − 133 MHz (For relationship between CPU clock and memory clock, see Section 6.1) Four independent memory channels Can use registered DIMM Selectable data bus width for each channel: 64-bit/32-bit Supports critical word first access of the TX49/H3 core Supports DMAC special Burst access (address decrement/fix) Programmable SDRAM timing latency Can set timing to match the clock frequency used and the memory speed. Can realize a system with optimized memory performance. Can write to any byte during Single or Burst Write operation. This feature is controlled by the DQM signal. Can set the refresh cycle to be programmable. SDRAM refresh mode: both auto refresh and self refresh are possible. Low power consumption mode: can select between self refresh or pre-charge power down SDRAM Burst length: fixed to "2" SDRAM addressing mode: Fixed to the Sequential mode Supports systems with high fan-out Supports two selectable data read-back buses and supports the Slow Write Burst Mode in order to handle data buses with large load. In order to maintain timing consistency during Read operation, it is possible to select whether to use the feedback clock to latch data or to by-pass this latch path. Two clock cycles are used for each Write operation when in the Slow Write Burst Mode. Can use the ECC or parity generation/check functions. Can select EC (Error Check only), ECC (Error Check and Correct), or ECC + Scrub (write correction data back to memory) when using the ECC function. Can select Odd parity/Even parity when using the Parity function. • • • • • • • • • • 9-1 Chapter 9 SDRAM Controller 9.2 Block Diagram SDRAMC SDCS [3 : 0] * Channel 0 – 7 Control Register G-Bus I/F Signal Timing Register G-Bus Interface Control Control Circuit CKE WE* RAS* CAS* DQM [7 : 0] Command/Load Register Refresh Counter ECC Control Signal G-Bus I/FSignal ECC ECC Control Signal EBIF Control Signal ADDR [19 : 5] EBIF DATA [63 : 0] CB [7 : 0] G-Bus CG SDCLK[3:0] Figure 9.2.1 Block Diagram of SDRAMC 9-2 Chapter 9 SDRAM Controller 9.3 Detailed Explanation Supported SDRAM configurations This controller supports the SDRAM configurations listed below in Table 9.3.1. The MW field of the SDRAM Channel Control Register (SDCCRn) can be used to separately set the data bus width for each channel to either 64 bits or 32 bits. DATA[31:0] and DQM[3:0] are used when using a 32-bit data bus. DQM[7:4] output High. DATA[63:32] output an undefined value when DATA[31:0] become the output, but enter the High-Z state when DATA[31:0] are the input. When in the Big Endian Mode, first external access of the upper word (bits 63:32) of the internal data bus is performed, then external access of the lower word (bits 31:0) is performed. When in the Little Endian Mode, first external access of the lower word (bits 31:0) is performed, then external access of the upper word (bits 63:32) is performed. When using a 32-bit data bus, two external access will always be performed even when accessing less than 32 bits of data. The maximum memory capacity per channel when a 64-bit data bus is configured is 1 GBytes when using 16 512-Mbit SDRAMs with a 4-bit data bus. The total maximum memory capacity is 4 GBytes when totaling up the four channels. Table 9.3.1 Supported SDRAM Configurations SDRAM Configuration 1 M × 16 16 Mbit 2-bank 2M×8 4M×4 2 M × 32 2 M × 32 2-bank 64 Mbit 4 M × 16 4 M × 16 8M×8 16 M × 4 2 M × 32 4-bank 4 M × 16 8M×8 16 M × 4 4 M × 32 128 Mbit 4-bank 8 M × 16 16 M × 8 32 M × 4 16 M × 16 256 Mbit 4-bank 32 M × 8 64 M × 4 32 M × 16 512 Mbit 4-bank 64 M × 8 128 M × 4 9.3.1 Row Address (bit) 11 11 11 11 12 11 13 13 13 11 12 12 12 12 12 12 12 13 13 13 13 13 13 Column Address (bit) 8 9 10 9 8 10 8 9 10 8 8 9 10 8 9 10 11 9 10 11 10 11 12 Remarks See Note 1 See Note 1 See Note 1 See Note 1 See Note 1,2 See Note 2 See Note 1,2 Note1: The SDRAM Controller logic-wise does support these configurations, but please design carefully since the memory bus load will be large. Note2: This SDRAM configuration has 512 Mbytes of memory on a channel. If it is mapped to physical address space beginning with address 0, it overlaps the address space for the ROM wherein the bootstrap vectors reside. 9-3 Chapter 9 SDRAM Controller 9.3.2 Address Mapping Physical Address Mapping It is possible to map each of the four channels to an arbitrary physical address using the Base Address field (SDCCRn.BA[35:21]) of the SDRAM Channel Control Register and the Address Mask Field (SDCCRn.AM[35:21]). The channel that becomes True in the following equation is selected. paddr[35:21] & !AM[35:21] = BA[35:21] & !AM[35:21] In the above equation, "paddr" represents the accessed physical address, "&" represents the AND of each bit, and "!" represents the logical NOT of each bit. Operation is undefined when multiple channels are simultaneously selected, or when external bus controllers or PCI controllers are simultaneously selected. 9.3.2.1 9-4 Chapter 9 SDRAM Controller 9.3.2.2 Address Signal Mapping (64-bit Data Bus) Table 9.3.2 shows the address signal mapping when using a 64-bit data bus. B0 is used in the bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection in memory with a four-bank configuration. Bits with the description "L/H" output High when performing auto-precharging, or output Low when not performing auto-precharging. Table 9.3.2 Address Signal Mapping (64-bit Data Bus) (1/2) Row address width = 11 Column address width = 8 Address bit ADDR [19:5] Column Address Row Address 19 (B0) 22 22 18 (B1) 23 23 17 21 21 16 20 20 15 (AP) L/H 21 14 L/H 20 13 L/H 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 11 Column Address Width = 9 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 23 23 18 (B1) 23 23 17 23 23 16 23 23 15 (AP) L/H 21 14 23 20 13 22 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 11 Column Address Width = 10 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 24 24 18 (B1) 23 23 17 23 23 16 24 24 15 (AP) L/H 21 14 23 20 13 22 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 12 Column Address Width = 8 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 23 23 18 (B1) 24 24 17 23 23 16 22 22 15 (AP) L/H 21 14 24 20 13 23 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 12 Column Address Width = 9 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 24 24 18 (B1) 25 25 17 24 24 16 22 22 15 (AP) L/H 21 14 24 20 13 23 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 12 Column Address Width = 10 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 25 25 18 (B1) 26 26 17 25 25 16 22 22 15 (AP) L/H 21 14 24 20 13 23 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 9-5 Chapter 9 SDRAM Controller Table 9.3.2 Address Signal Mapping (64-bit Data Bus) (2/2) Row Address Width = 12 Column Address Width = 11 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 26 26 18 (B1) 27 27 17 26 26 16 25 22 15 (AP) L/H 21 14 24 20 13 23 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 13 Column Address Width = 8 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 24 24 18 (B1) 25 25 17 23 23 16 22 22 15 (AP) L/H 21 14 25 20 13 24 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address = 13 Column Address Width = 9 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 25 25 18 (B1) 26 26 17 23 23 16 22 22 15 (AP) L/H 21 14 25 20 13 24 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 13 Column Address Width = 10 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 26 26 18 (B1) 27 27 17 23 23 16 22 22 15 (AP) L/H 21 14 25 20 13 24 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 13 Column Address Width = 11 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 27 27 18 (B1) 28 28 17 23 23 16 26 22 15 (AP) L/H 21 14 25 20 13 24 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 Row Address Width = 13 Column Address Width = 12 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 28 28 18 (B1) 29 29 17 27 23 16 26 22 15 (AP) L/H 21 14 25 20 13 24 19 12 10 18 11 9 17 10 8 16 9 7 15 8 6 14 7 5 13 6 4 12 5 3 11 9-6 Chapter 9 SDRAM Controller 9.3.2.3 Address Signal Mapping (32-bit Data Bus) Table 9.3.3 shows the address signal mapping when using a 32-bit data bus. B0 is used in the bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection in memory with a four-bank configuration. Bits with the description "L/H" output High when performing auto-precharging, or output Low when not performing auto-precharging. Table 9.3.3 Address Signal Mapping (32-bit Data Bus) (1/2) Row Address Width = 11 Column Address Width = 8 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 21 21 18 (B1) 22 22 17 20 20 16 19 19 15 (AP) L/H 20 14 L/H 19 13 L/H 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 11 Column Address Width = 9 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 22 22 18 (B1) 22 22 17 22 22 16 22 22 15 (AP) L/H 20 14 22 19 13 21 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 11 Column Address Width = 10 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 23 23 18 (B1) 22 22 17 22 22 16 23 23 15 (AP) L/H 20 14 22 19 13 21 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 12 Column Address Width = 8 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 22 22 18 (B1) 23 23 17 22 22 16 21 21 15 (AP) L/H 20 14 23 19 13 22 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 12 Column Address Width = 9 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 23 23 18 (B1) 24 24 17 23 23 16 21 21 15 (AP) L/H 20 14 23 19 13 22 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 12 Column Address Width = 10 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 24 24 18 (B1) 25 25 17 24 24 16 21 21 15 (AP) L/H 20 14 23 19 13 22 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 9-7 Chapter 9 SDRAM Controller Table 9.3.3 Address Signal Mapping (32-bit Data Bus) (2/2) Row Address Width = 12 Column Address Width = 11 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 25 25 18 (B1) 26 26 17 25 25 16 24 21 15 (AP) L/H 20 14 23 19 13 22 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 13 Column Address Width = 8 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 23 23 18 (B1) 24 24 17 22 22 16 21 21 15 (AP) L/H 20 14 24 19 13 23 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 13 Column Address Width = 9 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 24 24 18 (B1) 25 25 17 22 22 16 21 21 15 (AP) L/H 20 14 24 19 13 23 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 13 Column Address Width = 10 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 25 25 18 (B1) 26 26 17 22 22 16 21 21 15 (AP) L/H 20 14 24 19 13 23 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 13 Column Address Width = 11 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 26 26 18 (B1) 27 27 17 22 22 16 25 21 15 (AP) L/H 20 14 24 19 13 23 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 Row Address Width = 13 Column Address Width = 12 Address Bit ADDR [19:5] Column Address Row Address 19 (B0) 29 29 18 (B1) 28 28 17 26 22 16 25 21 15 (AP) L/H 20 14 24 19 13 23 18 12 9 17 11 8 16 10 7 15 9 6 14 8 5 13 7 4 12 6 3 11 5 2 10 9-8 Chapter 9 SDRAM Controller 9.3.3 Initialization of SDRAM The TX4938 Command Register has functions for generating the cycles required for initializing SDRAM. Using software to set each register makes it possible to execute initial settings at a particular timing. 1 2 Set the SDRAM Channel Control Register (SDCCRn). Set the SDRAM Timing Register (SDCTR). This timing setting is applied to all channels, so please set it to the slowest memory device. Use the SDRAM Command Register (SDCCMD) to issue the Pre-charge All command. Issue the Set Mode Register command in the same manner. Set the refresh count required to initialize SDRAM to the refresh counter (SDCTR.RC)1 and set the refresh cycle (SDCTR.RP).2 3 Wait until the refresh counter returns to “0.” Set the refresh cycle (SDCTR.RP) to the proper value. 3 4 5 6 7 1 2 3 The number of refresh operations can be counted using the refresh counter. With this function, it is no longer necessary to assemble special timing groups in the software when counting refresh operations. Setting the refresh cycle to a small value makes it possible to expedite completion of the refresh cycle required for SDRAM initialization. As described above, please set normal values after the required number of refresh cycles have been generated. Refresh requests have priority over all other SDRAM Controller access requests. Please do not set the memory refresh cycle to an unnecessarily short value. 9-9 Chapter 9 SDRAM Controller 9.3.4 Initialization of Memory Data, ECC/Parity The SDRAMC has functions for simultaneously performing Memory Writes to multiple memory channels. These functions are effective when quickly initializing data memory or ECC/parity memory. Channels for which both the Channel Enable bit (SDCCRn.CE) and the Master Enable bit (SDCCRn.ME) of the SDRAM Channel Control Register are set become the Master channel. Also, channels for which both the Channel Enable bit (SDCCRn.CE) and the Slave Enable bit (SDCCRn.SE) are set become the Slave channel. See Table 9.3.4 Master/Slave Channel Settings for information regarding the Master/Slave channel settings. The slave channel is simultaneously written to when the Master channel is written to. Settings of the Master channel are used when in the ECC/Parity mode. Please set to the same value the SDRAM settings of all channels that are simultaneously written to. Using the DMA Controller and performing 32 double word Burst access is the most efficient way to access the Master channel. The DMAC has registers for setting memory initialization data. When the DMAC is launched by an internal request when in the Single address IO→Memory Transfer mode, the data set in this register are written to memory. See Chapter 8 "DMA Controller" for more information. Table 9.3.4 Master/Slave Channel Settings SDCCRn.CE SDCCRn.ME (Channel Enable) (Master Enable) 0 1 X 0 SDCCRn.SE (Slave Enable) X 0 Description Channel is disabled. Normal operation is performed. W hen a Write operation is executed by a channel where SDCCRn.ME=1, the Write operation is also executed by this channel. Normal operation is performed when this channel is Active. W hen a Write operation is executed by this channel, the Write operation is simultaneously executed by all channels where SDCCRn.SE=1. W hen a Write operation is executed by this channel, the Write operation is simultaneously executed by all channels where SDCCRn.SE=1. A Write operation is also simultaneously executed by this channel when the Write operation is executed by another channel where SDCCRn.ME=1. 1 0 1 1 1 0 1 1 1 9-10 Chapter 9 SDRAM Controller 9.3.5 Low Power Consumption Function Power Down Mode, Self-Refresh Mode SDRAM has two low power consumption modes called the Power Down mode and the SelfRefresh mode. Memory data is lost in the case of the Power Down mode since Memory Refresh is not performed, but the amount of power consumed is reduced the most. Memory data is not lost in the case of the Self-Refresh mode. SDRAM is set to the Power Down mode by using the SDRAM Command Register (SDCCMD) to issue the Power Down Mode command. Similarly, SDRAM is set to the Self-Refresh mode by issuing the Self-Refresh Mode command. The SDRAMC terminates internal refresh circuit operation after one of these commands has been issued. Issuing the Normal Mode command returns operation to normal. When the Power Down Auto Entry bit (SDCTR.PDAE) of the SDRAM Timing Register is set, SDRAM is automatically set to the Power Down mode when memory access is not being performed. The SDRAMC internal refresh circuit will continue operating, so there will be no loss of memory data. If either the Memory Access, Memory Refresh, or Memory command is executed while SDRAM is set to the Power Down mode or the Self-Refresh mode, then the Power Down mode and Self-Refresh mode will automatically terminate, and memory access will be performed. After returning from a low power consumption mode that was set by either the Power Down Mode command or the Self-Refresh Mode command, the next memory access starts after 10 SDCLK cycles pass. This latency sufficiently follows the stipulated time from Power Down to first access of the SDRAM. If setting the Power Down Auto Entry bit automatically causes memory access to be requested when set in the Power Down mode, then add 1 SDCLK cycle more of access latency than when not in the Power Down mode. 9.3.5.2 Advanced CKE Advanced CKE is a function that speeds up the CKE assertion and deassertion timing by 1 clock cycle. This function is set using the Address CKE bit (SDCTR.ACE) of the SDRAM Timing Register. Advanced CKE assumes that it will be used in a system where SDRAM data is saved even when the power to the TX4938 itself is cut. Since CKE On/Off becomes 1 cycle faster, it is possible to delay CKE by 1 clock cycle using external power consumption control logic. Please set the SDRAM to the Self-Refresh mode before using this function. When combining advanced CKE functionality with Power Down Auto Entry functionality and memory access is requested while in the Power Down mode, two more SDCLK cycles of latency are added than would be the case when not in the Power Down mode. 9.3.5.1 9-11 Chapter 9 SDRAM Controller 9.3.6 Bus Errors The SDRAMC detects bus errors in the following situations: • • Bus time-out occurs during Read or Write operation to the SDRAMC ECC 2-bit fault error or Parity error occurs during SDRAM Read operation If a bus error occurs when accessing the SDRAMC, then the SDRAMC will immediately assert the current operation. Then, the current SDRAM cycle will end, remaining SDRAMC operations will be aborted, a Pre-charge All command will be issued to SDRAM, then the SDRAMC will return to the Idle state. 9.3.7 Memory Read and Memory Write The RAS* signal, CAS* signal, WE*, signal, and ADDR[19:5] signal are set up 1 cycle before the SDCS* signal is asserted in the case of the Read command, Write command, Pre-charge command, or Mode Register Set command. The same set up time is observed even for active commands if the Active Command Ready bit (SDCTR.DA) of the SDRAM Timing Register is set. Figure 9.5.1 is a timing diagram of Single Read operation when the SDCTR.DA bit is cleared. Figure 9.5.2 is a timing diagram of Single Read operation when the SDCTR.DA bit is set. Burst or Single Read operation is terminated by the Pre-charge Active Bank command. Burst or Single Write operation is terminated by the Auto Pre-charge Command. 9.3.8 Slow Write Burst When the Slow Write Burst bit (SDCTR.SWB) of the SDRAM Timing Register is cleared, the data changes at each cycle during Burst Write operation (Figure 9.5.6). When the Slow Write Burst bit is set, the data will change every other cycle (Figure 9.5.7). When the Slow Write Burst bit is set, all Write accesses will operate as tRCD = 3tCK regardless of the setting of the RAS-CAS Delay bit (SDCTR.RCD) of the SDRAM Timing Register. The RAS-CAS Delay bit setting becomes valid when Slow Write Burst access is invalid. The setting of the Slow Burst bit does not have any effect on Read access. 9.3.9 Clock Feedback When performing Read access at fast rates like 100 MHz, there may be insufficient set up time if an attempt to directly latch Read data with the internal clock is made. With the TX4938, it is possible to latch data using SDRAM clock SDCLKIN that is input from outside the chip. Please connect SDCLKIN to one of the SDCLK[3:0] pins and the external source. 9-12 Chapter 9 SDRAM Controller 9.3.10 ECC Table 9.3.5 shows the supported ECC/Parity functions. The ECC/Parity mode can be set separately for each channel using the ECC/Parity Mode field (SDCCRn.ECC) of the SDRAM Channel Control Register. The ECC enable bit (ECCCR.ECCE) of the ECC Control Register must be set in order to use the ECC function. No error detection, logging, or notification will be performed if this bit is not set. Table 9.3.5 ECC/Parity Mode ECC Field 0x0 0x1 9.3.10.1 ECC/Parity Mode Mode Name NOP Mode EC Mode Description Disables the ECC/Parity function. EC (Error Check) enable Read: Performs only error checking. Correction is not performed. Write: Generates check code. ECC (Error Check and Correct) enable Read: Performs error checking and correction. Write: Generates check code. ECC + scrub enable Read: Performs error checking and correction. Corrected data is written back to memory if an error occurs. Write: Generates check code. Even parity enable Read: Performs error checking. Write: Generates even parity. Odd parity enable Read: Performs error checking. Write: Generates odd parity. Reserved Reserved 0x2 ECC Mode 0x3 ECC + Scrub Mode 0x4 Even Parity Mode 0x5 0x6 0x7 Odd Parity Mode — — • • • The ECC/Parity Mode changes dynamically according to each channel setting. Error checking is performed when writing data smaller than 64 bits when Memory Read access is being performed while in the EC Mode, ECC Mode, or ECC + scrub mode. Data correction is performed if the read data cause a single-bit error when in the ECC Mode or the ECC + scrub mode. Data is read unchanged when in any other mode regardless of whether or not an error occurs. 9-13 Chapter 9 SDRAM Controller 9.3.10.2 ECC Error Notification When either an ECC error or a parity error occurs, error data is written into one of the following fields, then error notification is performed as described below: • • • • Error Address Field (ERRAD) in the ECC Status Register (ECCSR) Error ECC/Parity Mode Field (ERRMODE) Error Memory Width Field (ERRMW) Error Syndrome Field (ERRS) The Multi-bit Error bit (ECCSR.MBERR) of the ECC Status Register is set and an interrupt is generated if either an ECC multi-bit error or parity error is detected during any Read/Write access while the Multi-bit Error Interrupt Enable bit (ECCCR.MEI) is set. The Single-bit Error bit (ECCSR.SBERR) of the ECC Status Register is set and an interrupt is generated if an ECC single-bit error is detected during any Read/Write access while the Single-bit Error Interrupt Enable bit (ECCCR.SEI) is set. Multi-bit errors are assigned a higher priority than single-bit errors. If a multi-bit error is detected while the Single-bit Error bit (ECCSR.SBERR) is set, then the Single-bit Error bit (ECCSR.SBERR) is cleared, error data is written for the multi-bit error, then error notification is performed. If a single-bit error is detected while the Multi-bit Error bit (ECCSR.MBERR) is set, the Single-bit Error bit (ECCSR.SBERR) is not set and not error data is written. However, the single-bit error is corrected according to the usual procedure. The following error notification will also be performed if either an ECC multi-bit error or parity error is detected while the Multi-bit Error Bus Error Enable Bit (ECCCR.MEB) of the ECC Control Register is set. During read access by the TX49 core, bus error notification is sent to the TX49 core and an exception is generated. A nonmaskable interrupt is generated during Read-Modify-Write memory Read access that is performed when writing from the TX49 core data that is smaller than 64 bits. Bus error notification is sent to the appropriate bus master during Read/Write access from another bus master. 9-14 Chapter 9 SDRAM Controller 9.3.10.3 Adding Read Latency for Each ECC/Parity Mode When using the ECC/parity function, memory access latency is added according to which ECC/parity mode is selected, whether errors will be generated or not, the error type to be generated, and whether or not to generate bus errors. Table 9.3.6 shows in cycles the memory Read access latency that will be added based on NOP mode operation under each condition. Table 9.3.6 Read Latency Added for Each ECC/Parity Mode ECC/Parity Mode NOP Mode Bus Error Notification (ECCCR.MEB) ⎯ Error Type/Operation ⎯ No error SBErr: Do not correct MBErr: Correct No error SBErr: Do not correct MBErr: Do not correct No error SBErr: Correct MBErr: Do not correct No error SBErr: Correct MBErr: Do not correct No error SBErr: Correct & scrub MBErr: Do not correct No error Added Read Latency (in cycles) 0 0 0 1 2 1 2 1 2 1 Max. 22 3 1 Max. 22 2 0 0 1 1 Disable EC Mode Enable Disable ECC Mode Enable Disable ECC + scrub Mode Enable SBErr: Correct & scrub MBErr: Do not correct No error MBErr: Do not correct No error MBErr: Do not correct Even Parity Mode Odd Parity Mode SBErr = Single-bit error MBErr = Multi-bit error Disable Enable 9-15 Chapter 9 SDRAM Controller 9.3.10.4 ECC Memory Access 8-bit check code is used whether the data bus width is 64 bits or 32 bits. For 32-bit data bus width, check code is generated for and the error check is performed on 64-bit data that consists of two 32-bit data at the double word boundary. CB[7:0] are used for check code reading and writing when in the 64-bit mode. CB[3:0] are used for check code reading and writing when in the 32-bit mode. An 8-bit check code is used for 64bit data. Similar to the data however, accesses to the memory are divided into half with 4 bits being accessed at a time. The upper 4 bits of the check code are accessed simultaneous to when the upper 32 bits of the data are written or read. Similarly, the lower 4 bits of the check code are accessed simultaneous to when the lower 32 bits of the data are written or read. All 64-bit data are always read and checked when set in the EC mode, ECC mode, or ECC + Scrub mode. Consequently, data at the double word boundary, including this data, is read and checked even when accessing data smaller than a double word (word access, byte access, etc.). Read-Modify-Write (RMW) is performed during a Write operation of less than a double word. First, 64 bits of data that include the address where the writing is performed is read. Then, check code is generated for new 64-bit data that has replaced the written data. Single-bit errors are corrected, but multi-bit errors are not. Therefore, if multi-bit errors are detected, no data are written back to memory. If data is being transferred between external I/O and memory during a DMAC single address transfer, check code will not be generated even if the ECC function has been enabled. 9.3.10.5 Diagnostic Mode Setting the Diagnostic Mode bit (ECCCR.DM) of the ECC Control Register makes it possible to use the Diagnostic Mode. When in this mode and writing to a channel for which the ECC function is enabled, the code that is set in the Diagnostic ECC field (ECCCR.DECC) is written in place of the code that was calculated from the Write data. 9-16 Chapter 9 SDRAM Controller 9.4 Registers Table 9.4.1 SDRAM Control Register Offset Address 0x8000 0x8008 0x8010 0x8018 0x8040 0x8058 Bit Width Register Symbol 64 64 64 64 64 64 SDCCR0 SDCCR1 SDCCR2 SDCCR3 SDCTR SDCCMD Register Name SDRAM Channel Control Register 0 SDRAM Channel Control Register 1 SDRAM Channel Control Register 2 SDRAM Channel Control Register 3 SDRAM Timing Register SDRAM Command Register Table 9.4.2 ECC Control Register Offset Address 0xA000 0xA008 Bit Width Register Symbol 64 64 ECCCR ECCSR Register Name ECC Control Register ECC Status Register 9-17 Chapter 9 SDRAM Controller 9.4.1 SDRAM Channel Control Register (SDCCRn) 0x8000 (ch. 0) 0x8008 (ch. 1) 0x8010 (ch. 2) 0x8018 (ch. 3) When the SDCCRn is programmed using a sequence of 32-bit store instructions, the base address and the address mask in the high-order 32-bit portion of the register must be written first, followed by the Channel Enable bit in the low-order 32-bit portion. 63 BA R/W 0x01FC/0x0000 47 AM R/W 0x0000 31 ECC 0 15 RD R/W 0 R/W 0 14 MT R/W 01) 0 13 Reserved 49 48 Reserved :Type :Initial value 33 32 Reserved :Type :Initial value 16 Reserved :Type :Initial value 29 28 12 ME R/W 0 11 SE R/W 0 10 CE R/W 01) 9 Reserved 8 BS R/W 0 7 Reserved 6 RS R/W 0001) 5 4 3 CS R/W 0001) 2 1 Reserved 0 MW R/W 1 :Type :Initial value Bit 63:49 Mnemonic BA[35:21] Field Name Base Address Description Base Address (Default: 0x01FC/0x0000) Specifies the base address. The upper 15 bits [35:21] of the physical address are compared to the value of this field. (Note) Only the default for Channel 0 differs. Channel 0: 0x01FC, Others: 0x0000 Reserved Address Mask (Default: 0x0000) Sets the valid bits for address comparison according to the base address. 0: Bits of the corresponding BA field are compared. 1: Bits of the corresponding BA field are not compared. Reserved ECC/Parity mode (Default: 000) Specifies the channel ECC/Parity type (refer to 9.3.10.1). 000: NOP Mode 001: EC Mode 010: ECC Mode 011: ECC + scrub Mode 100: Even Parity Mode 101: Odd Parity Mode 110: Reserved 110: Reserved Reserved Read/Write R/W 48 47:33 — AM[35:21] — Address Mask ⎯ R/W 32 31:29 — ECC — ECC/Parity Mode ⎯ R/W 28:16 — — ⎯ Figure 9.4.1 SDRAM Channel Control Register (1/2) 9-18 Chapter 9 SDRAM Controller Bit 15 Mnemonic RD Field Name Registered DIMM Description Registered DIMM (Default: 0) Specifies whether the SDRAM connected to the channel is Registered memory. 0: Disable Registered memory 1: Enable Registered memory Reserved Master Enable (Default: 0) Specifies during ECC initialization whether a channel will be made the Master channel. 0: Disable 1: Enable Slave Enable (Default: 0) Specifies during ECC initialization whether a channel will be made the Slave channel. 0: Disable 1: Enable Enable (Default: 0) Specifies whether to enable a channel. 0: Disable 1: Enable Reserved Number of Banks (Default: 0) Specifies the bank count. 0: 2 banks 1: 4 banks Reserved Row Size (Default: 00) Specifies the row size. 00: 2048 Rows (11 bits) 01: 4096 Rows (12 bits) 10: 8192 Rows (13 bits) 11: Reserved Column Size (Default: 000) Specifies the column size. 000: 256 words (8 bits) 001: 512 words (9 bits) 010: 1024 words (10 bits) 011: 2048 words (11 bits) 100: 4096 words (12 bits) 101-111: Reserved Reserved Memory Width (Default: 0) Specifies the bus width. 0: 64 bits 1: 32 bits Read/Write R/W 14:13 12 — ME — Master Enable ⎯ R/W 11 SE Slave Enable R/W 10 CE Channel Enable R/W 9 8 — BS — Bank Count ⎯ R/W 7 6:5 — RS — Row Size ⎯ R/W 4:2 CS Column Size R/W 1 0 — MW — Memory Width ⎯ R/W Figure 9.4.1 SDRAM Channel Control Register (2/2) 9-19 Chapter 9 SDRAM Controller 9.4.2 63 Reserved :Type :Initial value 47 Reserved 1 31 BC 1 15 DA R/W 1 R/W 0 14 SWB R/W 1 1 13 1 12 29 28 ACP R/W 1 11 RP R/W 0x30C :Type :Initial value 27 26 PT R/W 1 25 RCD R/W 1 24 ACE R/W 0 23 PDAE R/W 0 0 0 22 RC R/W 0 0 0 18 17 CASL R/W 1 34 33 DIA R/W 1 16 DRB R/W :Type 0 :Initial value 0 :Type :Initial value 32 SDRAM Timing Register (SDCTR) 0x8040 48 Reserved Bit 63:34 33:32 Mnemonic — DIA Field Name — Write Active Period Reserved Description Data In to Active(tDAL) (Default: 11) Specifies the period from the last Write data to the Active command. 00: Reserved 1 01: 4 tCK 10: 5 tCK 11: 6 tCK Bank Cycle Time (tRC) (Default: 101) 2 Specifies the bank cycle time. 000: 5 tCK 100: 9 tCK 001: 6 tCK 101: 10 tCK 010: 7 tCK 110: Reserved 011: 8 tCK 111: Reserved Active Command Period (tRAS) (Default: 11) Specifies the active command time. 00: 3 tCK 01: 4 tCK 10: 5 tCK 11: 6 tCK Precharge Time (tRP) (Default: 1) Specifies the precharge time. 0: 2 tCK 1: 3 tCK RAS to CAS Delay (tRCD) (Default: 1) Specifies the RAS - CAS delay. 0: 2 tCK 1: 3 tCK Read/Write ⎯ R/W 31:29 BC Bank Cycle Time R/W 28:27 ACP Active Command Time R/W 26 PT Precharge Time R/W 25 RCD RAS-CAS Delay R/W Figure 9.4.2 SDRAM Timing Register (1/2) 1 2 tCK = Clock cycle tRC is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is tRAS + tRP + 1tCK if tRAS + tRP < tRC in the case of (ii) (iii). 9-20 Chapter 9 SDRAM Controller Bit 24 Mnemonic ACE Field Name Advanced CKE Description Advanced CKE enable (Default: 0) Enabling this function makes the timing at which CKE changes one cycle earlier. 0: Disable 1: Enable Power Down Auto Entry Enable (Default: 0) Enabling this function makes CKE become “L” while the SDRAMC is in the Idle state. When refresh, memory access, or command execution is performed, CKE automatically becomes “H”, the requested operation is performed, then CKE returns to “L” when the operation is complete. 0: Disable 1: Enable Refresh Counter (Default: 000000) This counter is decremented at each refresh. If the refresh circuit is activated and a value other than “0” is loaded, this field becomes a down counter that stops at “0”. A value other than “0” must be reloaded to start the countdown again. This is used during memory initialization. CAS Latency (tCASL) (Default: 1) Specifies the CAS latency. 0: 2 tCK 1: 3 tCK Data Read Bypass (Default: 0) Selects the Data Read path used. 0: Data Read latches to the register using the feedback clock. 1: Data Read bypasses the feedback clock latch. Delay Activate (tDA) (Default: 1) Specifies the delay from the row address to the bank active command. Setting this bit to “1” sets up the row address two cycles before the active command is executed. 0: 0 tCK 1: 1 tCK Slow Write Burst (tSWB) (Default: 1) Specifies whether to perform Slow Write Burst. 0: Burst Write occurs at each 1 tCK 1: Burst Write occurs at each 2 tCK Reserved Refresh Period (Default: 0x30c) Specifies the clock cycle count that generates the refresh cycle. Refresh is only enabled when at least one SDRAM channel is enabled. Please program the Timing Register before an arbitrary channel is enabled. Default is 0x30C. A refresh cycle occurs for each 7.8 µs@100 MHz in this situation. Read/Write R/W 23 PDAE Power Down Auto Entry R/W 22:18 RC Refresh Counter R/W 17 CASL CAS Latency R/W 16 DRB Data Read Bypass R/W 15 DA Active Command Delay R/W 14 SWB Slow Write Burst R/W 13:12 11:0 — RP — Refresh Period ⎯ R/W Figure 9.4.2 SDRAM Timing Register (2/2) 1 2 tCK = Clock cycle tRC is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is tRAS + tRP + 1tCK if tRAS + tRP < tRC in the case of (ii) (iii). 9-21 Chapter 9 SDRAM Controller 9.4.3 63 Reserved :Type :Initial value 47 Reserved :Type :Initial value 31 MDLNO R 0x30 15 14 13 12 11 8 7 CCE R/W 0x0 4 24 23 VERNO R 0x10 3 CMD R/W 0x0 :Type :Initial value 0 :Type :Initial value 16 32 SDRAM Command Register (SDCCMD) 0x8058 48 Reserved Bit 63:32 31:24 Mnemonic — MDLNO Field Name — Model Number Reserved Description Model Number (Default: 0x30) Indicates the model number. The default value is 0x30 for the TX4938. This field is Read Only. Version Number (Default: 0x10) Indicates the version number. The default value is 0x10 for the TX4938. This field is Read Only. Reserved Command Channel Enable Setting one of these bits to “1” enables the command of the corresponding channel. This command is simultaneously executed on all channels that are enabled. bit 7: Channel 3 bit 6: Channel 2 bit 5: Channel 1 bit 4: Channel 0 Command Specifies a command that is performed on memory. 0x0: NOP command 0x1: Set Mode Register command Set SDRAM Mode Register from SDCTR value 0x2: Reserved 0x3: Precharge All command Precharge All SDRAM Banks 0x4: Self-Refresh Mode command Sets SDRAM to the Self-Refresh Mode 0x5: Power Down Mode Command Set SDRAM to the Power Down Mode 0x6: Normal Mode Command Cancel Self-Refresh/Power Down Mode 0x7-0xf: Reserved Read/Write ⎯ R 23:16 VERNO Version Number R 15:8 7:4 — CCE — Command Channel Enable ⎯ R/W 3:0 CMD Command R/W Figure 9.4.3 SDRAM Command Register 9-22 Chapter 9 SDRAM Controller 9.4.4 63 MDLNO 0x10 ECC Control Register (ECCCR) 56 55 0xA000 48 VERNO 0x10 :Type :Initial value 32 47 Reserved :Type :Initial value 31 DECC R/W 0 15 Reserved 0 0 0 0 11 0 10 MEB R/W 0 0 9 MEI R/W 0 0 8 SEI R/W 0 7 Reserved 1 24 23 Reserved 17 16 DM R/W :Type 0 :Initial value 0 ECCE R/W :Type 0 :Initial value Bit 63:56 Mnemonic MDLNO Field Name Model Number Description Model Number (Default: 0x10) Indicates the model number. The default value for the TX4938 is 0x10. This field is Read Only. Address Mask (Default: 0x10) Indicates the version number. The default value for the TX4938 is 0x10. This field is Read Only. Reserved Diagnostic ECC (Default: 0x00) The value set by this field is output from CB[7:0] as the check code when the DM bit is set to “Enable.” Reserved ECC Diagnostic Mode (Default: 0) Specifies whether to use the Diagnostic Mode. 0: Disable 1: Enable Reserved Multi-Bit Error Bus Error Enable (Default: 0) Specifies whether to generate a bus error when a multi-bit error occurs. When this function is enabled, an NMI is generated for RMW * errors occurring during a Write operation to the TX49/H3 core. Bus errors are generated for all other operations. 0: Disable 1: Enable Multi-Bit Error Interrupt Enable (Default: 0) Specifies whether to generate an interrupt during a multi-bit error. 0: Disable 1: Enable Read/Write R 55:48 VERNO Version Number R 47:32 31:24 — DECC — Diagnostic ECC ⎯ R/W 23:17 16 — DM — Diagnostic Mode ⎯ R/W 15:11 10 — MEB — Multi-Bit Error Bus Error Enable ⎯ R/W 9 MEI Multi-Bit Error Interrupt Enable R/W Figure 9.4.4 ECC Control Register (1/2) 9-23 Chapter 9 SDRAM Controller Bit 8 Mnemonic SEI Field Name Single-Bit Error Interrupt Enable Description Single-Bit Error Interrupt Enable (Default: 0) Specifies whether to generate an interrupt during a single-bit error. 0: Disable 1: Enable Reserved ECC Enable (Default: 0) Specifies whether to enable the ECC/Parity function. When disabled, the ECC function will not operate even if the ECC Parity Mode field (SDCCRn.ECC) selects the ECC/Parity Mode. 0: Disable 1: Enable Read/Write R/W 7:1 0 — ECCE — ECC Enable ⎯ R/W Figure 9.4.4 ECC Control Register (2/2) 9-24 Chapter 9 SDRAM Controller 9.4.5 63 ERRAD R — 47 ERRAD R — 31 ERRAD R — 15 ERRS R — — — — — — — — — — — — — — — 28 — 27 Reserved ECC Status Register (ECCSR) 0xA008 48 — — — — — — — — — — — — — — — 32 :Type :Initial value — 26 — — 24 — 23 — 22 — 21 ERRMW — 20 — — — — 16 :Type :Initial value ERRMODE R — — 8 Reserved — 7 — Reserved :Type :Initial value 2 1 0 R — Reserved MBERR SBERR R/W 0 R/W :Type 0 :Initial value Bit 63:28 Mnemonic ERRAD Field Name Error Address Description Error Address (Default: Unknown) A 36-bit physical address is set when an error occurs. This address is retained until either SBERR or MBERR is cleared. This field is Read Only. Reserved Error ECC Mode (Default: Unknown) The ECC/Parity Mode is set when an error occurs. This address is retained until either SBERR or MBERR is cleared. This field is Read Only. Reserved Error Memory Width (Default: Unknown) The memory data width is set when an error occurs. This address is retained until either SBERR or MBERR is cleared. This field is Read Only. 0: 64 bits 1: 32 bits Reserved Error Syndrome (Default: Unknown) The error syndrome for when errors occur is set. The syndrome is retained until either SBERR or MBERR is cleared. This field is Read Only. Reserved Multi-Bit Error (Default: 0) This bit is set to “1” when a multi-bit error occurs, or when a parity error occurs while in the Parity Mode. Once a multi-bit error occurs, until this bit is cleared, no status in the Status Register is updated even if new multi/single-bit errors occur. 0: No error 1: Generate error Single-Bit Error (Default: 0) This bit is set to “1” when a single-bit error occurs. Once a single-bit error occurs, until this bit is cleared, no status in the Status Register is updated even if new single-bit error occurs. If a multi-bit error occurs, status is updated regardless of whether a single-bit error has occurred or not. 0: No error 1: Generate error Read/Write R 27 26:24 — ERRMODE — Error ECC/Parity Mode — Error Memory Width ⎯ R 23:22 21 — ERRMW ⎯ R 20:16 15:8 — ERRS — Error Syndrome ⎯ R 7:2 1 — MBERR — Multi-Bit Error ⎯ R/W 0 SBERR Single-Bit Error R/W Figure 9.4.5 ECC Status Register 9-25 Chapter 9 SDRAM Controller 9.5 Timing Diagrams Please note the following when referring to the timing diagrams in this section: the shaded area each diagram expresses values that have yet to be determined. in 9.5.1 Single Read (64-bit Bus) SDCLK SDCS* ADDR [19:5] RAS* 7fff 0000 CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ff 00 ff ACK*/READY* Figure 9.5.1 Single Read (tRCD = 2, tCASL = 2, tDA = 0, 64-bit Bus) 9-26 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 7fff 0000 RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* ff 00 ff Figure 9.5.2 Single Read (tRCD = 3, tCASL = 3, tDA = 1, 64-bit Bus) 9-27 Chapter 9 SDRAM Controller 9.5.2 Single Write (64-bit Bus) SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* ff 00 ff Figure 9.5.3 Double-Word Single Write (tRCD = 2, tDA = 0, 64-bit Bus) 9-28 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ff f0 ff ACK*/READY* Figure 9.5.4 One-Word Single Write (tRCD = 3, tDA = 1, 64-bit Bus) 9-29 Chapter 9 SDRAM Controller 9.5.3 Burst Read (64-bit Bus) 0002 0004 0001 0000 RAS* SDCS* CAS* SDCLK WE* ff 00 ff Figure 9.5.5 Eight-Word Burst Read (tRCD = 2, tCASL = 2, tDA = 0, 64-bit Bus) 9-30 ACK*/READY CKE ADDR [19:5] DATA [63:0] CB [7:0] DQM [7:0] Chapter 9 SDRAM Controller 9.5.4 Burst Write (64-bit Bus) 0402 0000 0000 DQM [7:0] ff DATA [63:0] CB [7:0] WE* CKE 00 ff Figure 9.5.6 Eight-Word Burst Write (tRCD = 2, tDA = 0, 64-bit Bus) 9-31 ACK*/READY SDCLK SDCS* ADDR [19:5] RAS* CAS* Chapter 9 SDRAM Controller 9.5.5 Burst Write (64-bit Bus, Slow Write Burst) 04C3 00 ff 00C2 00C1 00C0 0000 SDCS* ff 00 ff 00 ff 00 ff 0 Figure 9.5.7 Eight-Word Burst Write (tRCD = 2, tDA = 0, 64-bit Bus, Slow Write Burst) 9-32 ACK*/READY* ADDR [19:5] DATA [63:0] CB [7:0] RAS* CAS* WE* DQM [7:0] SDCLK CKE Chapter 9 SDRAM Controller 9.5.6 Single Read (32-bit Bus) SDCLK SDCS* ADDR [19:5] RAS* 7fff 0000 CAS* WE* CKE DQM [7:0] DATA [31:0] CB [7:0] ff ff f0 ACK*/READY* Figure 9.5.8 Double-Word Single Read (tRCD = 2, tCASL = 2, tDA = 0, 32-bit Bus) 9-33 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 7fff 0000 RAS* CAS* WE* CKE DQM [7:0] DATA [31:0] CB [7:0] ff ff f0 ACK*/READY* Figure 9.5.9 One-Word Single Read (tRCD = 2, tCASL = 3, tDA = 0, 32-bit Bus) 9-34 Chapter 9 SDRAM Controller 9.5.7 Single Write (32-bit Bus) SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ff f0 ff ACK*/READY* Figure 9.5.10 Double-Word Single Write (tRCD = 2, tDA = 0, 32-bit Bus) 9-35 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] 0000 0400 RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ff f0 ff ACK*/READY* Figure 9.5.11 One-Word Single Write (tRCD = 3, tDA = 0, 32-bit Bus) 9-36 Chapter 9 SDRAM Controller 9.5.8 Low Power Consumption and Power Down Mode SDCLK SDCS* ADDR [19:5] RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* ff Figure 9.5.12 Transition to Low Power Consumption Mode (SDCTR.ACE = 0) 9-37 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ACK*/READY* ff Figure 9.5.13 Transition to Power Down Mode 9-38 Chapter 9 SDRAM Controller 0000 0006 ADDR [19:5] CKE DQM [7:0] ff DATA [63:0] CB [7:0] SDCS* RAS* CAS* WE* 00 ff Figure 9.5.14 Return From Low Power Consumption/Power Down Mode (SDCTR.PDAE = 0, SDCTR.ACE = 0) 9-39 ACK*/READY* SDCLK Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:5] RAS* 0000 0400 CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ff 00 ff ACK*/READY* Figure 9.5.15 Power Down Auto Entry (SDCTR.PDAE = 1, SDCTR.ACE = 0) 9-40 Chapter 9 SDRAM Controller SDCLK SDCS* ADDR [19:18] SDCSFCMD.BK ADDR [17:12] ADDR [12:5] SDCSFCMD.CMD RAS* CAS* WE* CKE DQM [7:0] DATA [63:0] CB [7:0] ff ACK*/READY Figure 9.5.16 LCR Command 9-41 Chapter 9 SDRAM Controller 9.6 SDRAM Usage Example Figure 9.6.1 illustrates an example SDRAM connection. Figure 9.6.2 illustrates an example SDRAM DIMM (168-pin) connection. TX4938 DQM [7:0] SDRAM (×16 bits) DQM [7] DQM [6] DQM [5] DQM [4] DQM [3] DQM [2] DQM [1] DQM [0] UDQM LDQM UDQM LDQM A [12:0] BS0 BS1 CS* RAS* CAS* W E* UDQM LDQM A [12:0] BS0 BS1 CS* RAS* CAS* W E* UDQM LDQM A [12:0] BS0 BS1 CS* RAS* CAS* W E* ADDR [19:5] ADDR [17:5] A [12:0] ADDR [19] BS0 ADDR [18] BS1 CS* RAS* CAS* W E* SDCS*[0] RAS* CAS* WE* SDCLKIN SDCLK [0] CKE CLK CKE DQ [15:0] D [63:48] CLK CKE DQ [15:0] D [47:32] CLK CKE DQ [15:0] D [31:16] CLK CKE DQ [15:0] D [15:0] DATA [63:0] Figure 9.6.1 SDRAM (×16 bits) Connection Example TX4938 ADDR[19:5] ADDR[16:5] A[11:0] ADDR[19] BA0 ADDR[18] BA1 DQMB[7:0] S0 S1 128MB unbuffer DIMM × 2 A[11:0] BA0 BA1 DQMB[7:0] S0 S1 DQM[7:0] SDCS[0]* SDCS[1]* RAS* CAS* WE* CKE SDCLKIN SDCLK[0] SDCLK[1] SDCLK[2] SDCLK[3] DATA[63:0] RAS* CAS* W E* CKE0 CKE1 CK0 CK1 RAS* CAS* W E* CKE0 CKE1 CK0 CK1 DQ[63:0] DQ[63:0] Figure 9.6.2 168-pin DIMM Connection Example 9-42 Chapter 10 PCI Controller 10. PCI Controller 10.1 Features The TX4938 PCI Controller functions as a bus bridge between the TX4938 External PCI and the internal bus (G-Bus). 10.1.1 Overall • • • • • • • • • • • • • Compliant to “PCI Local Bus Specification Revision 2.2” PCI Bus: 32-bit data bus; Internal Bus: 64-bit data bus Maximum PCI bus clock operating frequency: 66 MHz Dual address cycle support (40-bit PCI address space) Supports both the Initiator and Target functions Supports power management functions that are compliant to PCI Bus Power Management Interface Specifications Version 1.1. On-chip PCI Bus Arbiter, can connect to a maximum of four external bus masters 1-channel on-chip DMA Controller (PDMAC) dedicated to the PCI Controller Supports six PCI clock outputs The Internal Bus clock and PCI Bus clock are asynchronous and can be set independently Includes function for booting the TX4938 from memory on the PCI Bus Can set configuration data from serial ROM Mounted a retry function on the Internal Bus side also in order to avoid deadlock on the PCI Bus. 10.1.2 Initiator Function • • • • • • Single and Burst transfer from the Internal Bus to the PCI Bus Supports memory, I/O, configuration, special cycle, and interrupt acknowledge transactions. Address mapping between the Internal Bus and the PCI Bus can be modified Mounted 8-stage 64-bit data one FIFO each for Read and Write Post Write function enables quick termination of a maximum of four Write transactions by the GBus without waiting for completion on the PCI Bus. Endian switching function 10-1 Chapter 10 PCI Controller 10.1.3 Target Function • • • • • • • • • Single and Burst transfer from the PCI Bus to the Internal Bus Supports memory, I/O, and configuration cycles Supports high-speed back-to-back transactions on the PCI Bus Address mapping between the PCI Bus and the Internal bus can be modified Mounted 8-stage 64-bit data FIFO for Read Mounted 12-stage 64-bit data FIFO for Write Post Write function enables quick termination of a maximum of nine Write transactions by the PCI Bus without waiting for completion on the G-Bus. Read Burst length (pre-fetch data size) on the Internal Bus when reading a pre-fetchable space can be made programmable Endian switching function 10.1.4 PCI Arbiter • • • • • • Supports four external PCI bus masters Uses the Programmable Fairness algorithm (two levels with different priorities for four roundrobin request/grant pairs) Supports bus parking Bus master uses the Most Recently Used algorithm Unused slots and broken masters can be automatically disabled after Power On reset On-chip arbitration function can be disabled and external arbiter can be used 10.1.5 PDMAC (PCI DMA Controller) • • • • • • Direct Memory Access (DMA) Controller dedicated to 1-channel PCI Is possible to transfer data using minimal G-Bus bandwidth Data can be transferred bidirectionally between the G-Bus and the PCI Bus Specifying a physical address on the PCI Bus and an address on the G-Bus makes it possible to automatically transfer data between the PCI Bus and the G-Bus Supports the Chain DMA mode, in which a Descriptor containing chain-shaped addresses and a transfer size is automatically read from memory while DMA transfer continuous On-chip 4-stage 64-bit data buffer 10-2 Chapter 10 PCI Controller 10.2 Block Diagram TX49/H3 Core Memory Controller DMA Controller Arbiter G-Bus PCI Controller Retry G-Bus I/F Targ. cont. (PCI→G-Bus) 64-bit × 4 Mast. cont. (G-Bus→PCI) PDMAC (64-bit × 4) Config EBUSC Arb. Target Write 64-bit × 8 Target Read 64-bit × 8 Master Write 64-bit × 8 Master Read 64-bit × 8 Req. × 4 PCI Arbiter PCI Core TX4938 PCI Bus PCI Device PCI Device Figure 10.2.1 PCI Controller Block Diagram 10-3 Chapter 10 PCI Controller 10.3 Detailed Explanation 10.3.1 Terminology Explanation The following terms are used in this chapter. • Initiator Means the bus Master of the PCI Bus. The TX4938 operates as the initiator when it obtains the PCI Bus and issues PCI access. Target Means the bus Slave of the PCI Bus. The TX4938 operates as the target when an external PCI device on the PCI Bus executes PCI access to the TX4938. Host mode One PCI Host device exists for one PCI Bus. The PCI Host device uses a PCI configuration space to perform PCI configuration on other PCI devices on the PCI Bus. The TX4938 is set to the Host mode if the ADDR[19] signal is High when the RESET* signal is being deasserted. • Satellite mode A PCI device other than the PCI Host device accepts configuration from the PCI Host device. This state is referred to as the Satellite mode. The TX4938 is set to the Satellite mode if the ADDR[19] signal is Low when the RESET signal is being deasserted. • DWORD, QWORD DWORD expresses 32-bit words, and QWORD expresses 64-bit words. According to conventions observed regarding MIPS architecture, this manual uses the following expressions: Byte: 8-bit Half-word: 16-bit Word: 32-bit Double-word: 64-bit • • 10.3.2 On-chip Register The PCI Controller on-chip register contains the PCI Configuration Space Register and the PCI Controller Control Register. The registers that can be accessed vary according to whether the current mode is the Host mode or the Satellite mode. An external PCI Host device only accesses the PCI Configuration Space Register when in the Satellite mode. This register is defined in the PCI Bus Specifications. A PCI configuration cycle is used to access this register. This register cannot be accessed when in the Host mode. Section “10.5 PCI Configuration Space Register” explains each register in detail. The PCI Controller Control Register is only accessed by the TX49 core and cannot be accessed from the PCI Bus. 10-4 Chapter 10 PCI Controller Registers in the PCI Controller Control Register that include an offset address in the range from 0xD000 to 0xD07F can only be accessed when in the Host mode and cannot be accessed when in the Satellite mode. These registers correspond to PCI Configuration Space Registers that an external PCI Host device accesses when in the Satellite mode. Section “10.4 PCI Controller Control Register” explains each register in detail. Figure 10.3.1 illustrates the register map when in the Host mode. Figure 10.3.2 illustrates the register map when in the Satellite mode. 0xDFFF Reserved 0xD270 PCI Controller Control Register 0xFF 0x80 0xD000 G-Bus Address Space 0x00 PCI Bus Configuration Space Reserved Figure 10.3.1 Register Map in the Host Mode 0xDFFF Reserved 0xD270 PCI Controller Control Register 0xFF 0xD080 Reserved 0xD000 G-Bus Address Space 0x80 0x00 PCI Bus Configuration Space PCI Configuration Space Register Figure 10.3.2 Register Map in the Satellite Mode 10-5 Chapter 10 PCI Controller 10.3.3 Supported PCI Bus Commands Table 10.3.1 shows the PCI Bus commands that the PCI Controller supports. Table 10.3.1 Supported PCI Bus Commands C/BE Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PCI Command Interrupt Acknowledge Special Cycle I/O Read I/O Write (Reserved) (Reserved) Memory Read Memory Write (Reserved) (Reserved) Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate As Initiator † † √ √ ⎯ ⎯ √ √ ⎯ ⎯ † † √ √ √ √ As Target ⎯ ⎯ √ √ ⎯ ⎯ √ √ ⎯ ⎯ ‡ ‡ √ √ √ √ Note: Key: The byte enable signals are asserted as necessary during memory read and memory write cycles using I/O Read, I/O Write and Single Access commands. During burst memory reads, four byte enable signals are asserted. √ : Supported when in both the Host mode and the Satellite mode † : Supported only when in the Host mode ‡ : Supported only when in the Satellite mode — : Not supported • I/O Read, I/O Write, Memory Read, Memory Write This command executes Read/Write access to the address mapped on the G-Bus and PCI Bus. • Memory Read Multiple, Memory Read Line The Memory Read Multiple command is issued if all of the following conditions are met when the Initiator function is operating and Burst Read access is issued from the G-Bus to the PCI Bus. (1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI Configuration 1 Register. (2) The Read data word count is equal to or less than the value set in the Cache Line Size Field. Also, the Read Memory Line command is issued when all of the following conditions are met. (1) A value other than “0” is set to the Cache Line Size Field (PCICFG1.CLS) of the PCI Configuration 1 Register. (2) The Read data word count is equal to or less than the value set in the Cache Line Size Field. 10-6 Chapter 10 PCI Controller The Memory Read command is issued if these conditions are not met, namely, if “0” is set to the Cache Line Size field (PCICFG1.CLS) of the PCI Configuration 1 Register. In the case of the target, a normal G-Bus cycle is issued to the address mapped from the PCI Bus to the G-Bus. • Memory Write and Invalidate When the TX4938 operates as the initiator, the PCI Controller is sue the Memory Write and Invalidate command if all of the folllowing conditions are met when write access from the G-Bus to the PCI Bus occurs. (1) The Memory Write and Invalidate Enable bit (PCISTATUS.MWIEN) of the PCI Status Command Register is set. (2) A value other than “0” was set to the Cache Line Size field (PCICFG1.CLS) of the PCI Configuration 1 Register. (3) The word count of the Write data is equal to or larger than the value set in the Cache Line Size field. The Memory Write command is issued in these conditions are not met. When the TX4938 operates as the target, the Memory Write and Invalidate command is converted into G-Bus Write access. Note that the TX4938 does nto support the cache memory Snoop function. • Dual address cycle When the TX4938 operates as the initiator, the PCI Controller executes dual access cycles if the PCI Bus address exceeds 0x00_FFFF_FFFF. When the TX4938 operates as the target, normal G-Bus cycles are executed to the address mapped from the PCI Bus to the G-Bus. • Configuration Read, Configuration Write These commands only issue configuration cycles as the when in the Host mode. The corresponding configuration cycles are issued on the PCI Bus. This is done by either reading or writing from/to the G2P Configuration Data Register (G2PCFGDATA) after writing the configuration space address to the G2P Configuration Address Register. The TX4938 supports both “Type 0” and “Type 1” configuration transactions. On systems that have PCI card slots, the PCI Host device checks each PCI card slot during system initialization to see if PCI device exist, then set the Configuration Space Register of the devices that do exist. If a PCI Configuration Read operation is performed for devices that do not exist, then by default a Bus Error exception will be generated since there is no PCI Bus response. Clearing the Bus Error Response During Initiator Read bit (PCICFG.IRBER) of the PCI Controller Configuration Register makes it possible to execute a Read transaction without causing a Bus Error. All bits of the data read at this time will be set to “1”. 10-7 Chapter 10 PCI Controller Configuration cycles will be accepted as the target only when in the Satellite mode. After reset, Retry response to PCI Configuration access will continue until the software sets the Target Configuration Access Ready Bit (PCICFG.TCAR) of the PCI Controller Configuration Register. Please use the software to set this bit after the software initialization process ends and the software is ready to accept PCI configuration. • Interrupt Acknowledge This command issues interrupt acknowledge cycles as an initiator only when in the Host mode. Interrupt acknowledge cycles are executed on the PCI Bus when the G2P Interrupt Acknowledge Data Register (G2PINTACK) is read. The value returned by this Read becomes the interrupt acknowledge cycle data. The TX4938 does not support interrupt acknowledge cycles as the target. • Special Cycle This command issues specialy cycles as the initiator only when in the Host mode. This command issues special cycles on the PCI Bus when writing to the G2P Special Cycle Data Register (G2PSPC). The written value is output as the special cycle data. The TX4938 does not support special cycles as the target. 10.3.4 Initiator Access (G-Bus → PCI Bus Address Conversion) During PCI initiator access, the G-Bus address of the Burst transaction issued by the G-Bus that was converted into the PCI Bus address is used to issue a Burst transaction on the PCI Bus. 36-bit physical address (G-Bus addresses) are used on the G-Bus. Also, 40-bit PCI Bus addresses are used on the PCI Bus. Three memory access windows and one I/O access window can be set in the G-Bus space (Figure 10.3.3). The size of each window is variable. When Burst transactions are issued to these access windows on the G-Bus, then that G-Bus address is converted into a PCI Bus address that is used to issue a Burst transaction to the PCI Bus as the initiator. PCI memory access is issued when the access window is the memory access window. PCI I/O access is issued when the access window is the I/O access window. Dual access cycles are also issued to the PCI Bus when the PCI Bus address exceeds 0x00_FFFF_FFFF. 0xFF_FFFF_FFFF 0xFF_FFFF_FFFF 0xF_FFFF_FFFF 0x00_0000_0000 PCI I/O Space 0x0_0000_0000 G-Bus Space 0x00_0000_0000 PCI Memory Space Memory Access Window I/O Access Window Figure 10.3.3 Initiator Access Memory Window 10-8 Chapter 10 PCI Controller When expressed as a formula, conversion of a G-Bus address (GBusAddr[35:0]) into a PCI Bus Address (PCIAddr[39:0]) is as follows below. GBASE[35:8], PBASE[39:8], and AM[35:8] each represent the setting register of the corresponding access window indicated below in Table 10.3.2. The “&” symbol indicates a logical AND for each bit, “||” indicates a logical OR for each bit, “!” indicates logical NOT, and “|” indicates bit linking. If (GBusAddr[35:8] & ! AM[35:8] == GBASE[35:8] & ! AM[35:8]) then PCIAddr[39:0] = PBASE[39:36] | ((PBASE[35:8] & ! AM[35:8]) || (GBusAddr[35:8] & AM[35:8])) | GBusAddr[7:0]; Table 10.3.2 Initiator Access Space Address Mapping Register G-Bus Base Address GBASE[35:8] Memory Space 0 Memory Space 1 Memory Space 2 I/O Space G2PM0GBASE.BA[35:8] G2PM1GBASE.BA[35:8] G2PM2GBASE.BA[35:8] G2PIOGBASE.BA[35:8] PCI Bus Base Address PBASE[39:8] G2PM0PBASE.BA[39:8] G2PM1PBASE.BA[39:8] G2PM2PBASE.BA[39:8] G2PIOPBASE.BA[39:8] Address Mask AM[35:8] G2PM0MASK.AM[35:8] G2PM1MASK.AM[35:8] G2PM2MASK.AM[35:8] G2PIOMASK.AM[35:8] Figure 10.3.4 illustrates this address conversion. 35 GBusAddr Compare 35 GBASE 8 7 0x00 0 0 35 AM 8 7 0x00 0 000-----------00111-------------------- 39 PBASE 8 7 0x00 0 39 PCIAddr 0 Figure 10.3.4 Address Conversion For Initiator (G-Bus → PCI Bus Address Conversion) It is possible to set each space to valid/invalid or to perform Word Swap (see “10.3.7 Endian Switching Function). Table 10.3.3 shows the settings registers for these properties. When 64-bit access is made to the initiator memory space, two 32-bit Burst accesses are issued on the PCI Bus. 64-bit access to the I/O space is not supported. Also, operation is not guaranteed if resources in the PCI space were made cacheable and were then accessed when the Critical Word First function of the TX49/H3 core was enabled. 10-9 Chapter 10 PCI Controller Table 10.3.3 Initiator Access Space Properties Register Enable Memory Space 0 Memory Space 1 Memory Space 2 I/O Space BusMasterEnable & PCICCFG.G2PM0EN BusMasterEnable & PCICCFG.G2PM1EN BusMasterEnable & PCICCFG.G2PM2EN BusMasterEnable & PCICCFG.G2PIOEN Word Swap G2PM0GBASE.BSWAP G2PM1GBASE.BSWAP G2PM2GBASE.BSWAP G2PIOGBASE.BSWAP BusMasterEnable: Host mode: PCI State Command Register Bus Master Bit (PCISTATUS.BM) Satellite mode: Command Register Bus Master bit 10.3.5 Target Access (PCI Bus → G-Bus Address Conversion) During PCI target access, the PCI Bus address of the Bus transaction issued by the PCI Bus is converted into a G-Bus address and is used to issue a Bus transaction on the G-Bus. 40-bit PCI Bus addresses are used on the PCI Bus. Also, 36-bit physical addresses are used on the G-Bus. Three memory access windows and one I/O access window can be set in the PCI bus space (Figure 10.3.5). The size of each window is fixed. When Bus transactions to these access windows is issued on the PCI Bus, these Bus transactions are accepted as PCI target devices. The PCI Bus Address is converted into G-Bus addresses, then Bus transactions are issued to the G-Bus. The memory space window responds to the PCI memory space access command. The I/O space window responds to the PCI I/O space access command. Note: Byte swapping is always disabled when prefetch mode is disabled. When the G-Bus is configured for big-endian mode, the order of bits in a 32-bit word does not change during a PCI transfer. (The byte ordering changes.) 0xFF_FFFF_FFFF 0xFF_FFFF_FFFF 0xF_FFFF_FFFF 0x00_FFFF_FFFF 0x00_0000_0000 PCI I/O Space Memory Access Window I/O Access Window 0x0_0000_0000 G-Bus Space 0x00_FFFF_FFFF 0x00_0000_0000 PCI Memory Space Figure 10.3.5 Target Access Memory Window 10-10 Chapter 10 PCI Controller When expressed as a formula, conversion of a PCI Bus Address (PCIAddr[39:0]) into a G-Bus address (GBusAddr[35:0]) is as follows below. GBASE[35:8], and PBASE[39:8] each represent the setting register of the corresponding access window indicated below in Table 10.3.4. The “&” symbol indicates a logical AND for each bit, and “|” indicates bit linking. Memory space 0 If (PCIAddr[39:29] == P2GM0PUBASE.BA[39:32] | P2GM0PLBASE.BA[31:29] then GBusAddr[35:0] = P2GM0GBASE[35:29] | PCIAddr[28:0]; Memory space 1 If (PCIAddr[39:24] == P2GM1PUBASE.BA[39:32] | P2GM1PLBASE.BA[31:24] then GBusAddr[35:0] = P2GM1GBASE[35:24] | PCIAddr[23:0]; Memory space 2 If (PCIAddr[31:20] == P2GM2PBASE.BA[31:20]) then GBusAddr[35:0] = P2GM2GBASE[35:20] | PCIAddr[19:0]; I/O space If (PCIAddr[31:8] == P2GIOPBASE.BA[31:8]) then GBusAddr[35:0] = P2GIOGBASE[35:8] | PCIAddr[7:0]; Table 10.3.4 Target Access Space Address Mapping Register Space Size Memory Space 0 Memory Space 1 Memory Space 2 I/O Space 512 MB 16 MB 1 MB 256 B PCI Address 40-bit 40-bit 32-bit 32-bit PCI Bus Base Address PBASE P2GM0PUBASE.BA[39:32] | P2GM0PLBASE.BA[31:29] P2GM1PUBASE.BA[39:32] | P2GM1PLBASE.BA[31:24] P2GM2PBASE.BA[31:20] P2GIOPBASE.BA[31:8] G-Bus Base Address GBASE P2GM0GBASE.BA[35:29] P2GM1GBASE.BA[35:24] P2GM2GBASE.BA[35:20] P2GIOGBASE.BA[35:8] Figure 10.3.6 illustrates this address conversion. 39/32 PCIAddr n n−1 0 Compare 39/32 PBASE n n−1 0 35 GBASE n n−1 0 35 GBusAddr n = 29 n = 24 n = 20 n=8 n n−1 0 Memory Space 0 Memory Space 1 Memory Space 2 I/O Space Figure 10.3.6 Address Conversion for Target (PCI Bus (PCI Bus → G-Bus Address Conversion) 10-11 Chapter 10 PCI Controller It is possible to set each space to valid/invalid, pre-fetch Read to valid/invalid, or to perform Word Swap (see10.3.7). Table 10.3.5 shows the settings registers for these properties. When pre-fetch Reads are set to valid, data transfer is performed on the G-Bus according to the size set by the Target Pre-fetch Read Burst Length Field (P2GCFG.TPRBL) of the P2G Configuration Register during a PCI target Read transaction. This is performed using accesses to resources that will not be affected even if a pre-read such as memory is performed. Also, PCI Burst Reads to memory spaces that were set to I/O space and pre-fetch disable are not supported. Note: Always use PCI single reads. Don’t use burst reads. Table 10.3.5 Target Access Space Properties Register Enable Memory Space 0 Memory Space 1 Memory Space 2 I/O Space PCICCFG.TCAR & MemEnable & P2GM0GBASE.P2GM0EN PCICCFG.TCAR & MemEnable & P2GM1GBASE.P2GM1EN PCICCFG.TCAR & MemEnable & P2GM2GBASE.P2GM2EN PCICCFG.TCAR & IOEnable & P2GIOGBASE.P2GIOEN Pre-fetch (Initial State) P2GCFG.MEM0PD (valid) P2GCFG.MEM1PD (valid) P2GCFG.MEM2PD (invalid) Always invalid Word Swap P2GM0GBASE.BSWAP P2GM1GBASE.BSWAP P2GM2GBASE.BSWAP P2GIOGBASE.BSWAP MemEnable: Host mode: PCI State Command Register Memory Space bit (PCISTATUS.MEMSP) Satellite mode: Command Register Memory Space bit IOEnable: Host mode: PCI State Command Register I/O Space bit (PCISTATUS.IOSP) Satellite mode: Command Register I/O Space bit 10.3.6 Post Write Function The Post Write function improves system performance by completing the original bus Write transaction without waiting for the other bus to complete its transaction when the first bus issues a Write transaction. Initiator Write can Post Write a maximum of four Write transactions, and Target Write can Post Write a maximum of nine Write transactions. Due to compatibility issues with old PC software in the PCI specifications, performing Post Writes with Initiator Configuration Write and Target I/O Write is not recognized. However, the TX4938 PCI Controller can even perform Post Writes to these functions. In order to guarantee that these Writes are completed by the target device, please execute Reads to the device that performed the Write, then either refer to the read value (so the TX49/H3 core can support non-blocking load) or execute the SYNC instruction. 10.3.7 Endian Switching Function The TX4938 supports both the Little Endian mode and the Bit Endian mode. On the other hand, the PCI Bus is only defined in Little Endian logic. Therefore, when the TX4938 is in the Big Endian mode, either the software or the hardware must perform some kind of conversion when exchanging data larger than 2 B in size with the PCI Bus. The PCI Controller can specify the endian switching function that reverses the byte arrangement of the DWORD (32-bit) data for each access window. 10-12 Chapter 10 PCI Controller Initial state operation matches the correspondence between the address and byte data regardless of the endian mode (operation is address consistent). For example, if WORD (16-bit) data is written to address 0 of the PCI Bus when the TX4938 is in the Big Endian mode, the upper byte (address 0 in Big Endian) is written to PCI Bus address 0 and the lower byte (address 1 in Big Endian) is written to address 1 of the PCI Bus. For Little Endian PCI devices, this means that the byte order is reversed. When in the Big Endian mode and a particular access window Endian switching mechanism is validated, data is transferred so the byte order does not change in DWORD (32-bit) access to that access window. Endian switching during initiator access is specified by the Byte Swap bit (BSWAP) of the G-Bus Base Address Register (G2PMnGBASE, G2PIOGBASE) of the access window for each initiator access (see Table 10.3.3). Ending switching during target access is specified by the Byte Swap bit (BSWAP) of the G-Bus Base Address Register (P2GMnGBASE, P2GIOGBASE) of the access window for each target access (see Table 10.3.5). 10.3.8 66 MHz Operation Mode The TX4938 PCI Controller supports 66 MHz PCI. When in the Host mode, the procedure for setting the PCI Bus to the 66 MHz mode is as follows below. (1) Start the system with a PCI Bus Clock frequency of 33 MHz or less. (2) The TX4938 system initialization program checks the 66 MHz Capable bit (bit 5) of the configuration Space Register Status Register in all PCI devices. If the 66 MHz Capable bit of all devices is set, then change the PCI Bus Clock frequency according to the following procedure. (3) Assert the PCI Bus Reset signal. (The TX4938 does not have PCI Reset output, so it is necessary to use an external circuit to control the PCI Bus Reset signal.) (4) Set the Software Reset bit (PCICFG.SRST) of the PCI Controller Configuration Register. (5) Setting the PCI66 MHz Mode bit (CCFG.PCI66) of the Chip Configuration Register asserts the M66EN signal. (6) Modifying the setting of the PCICLK Division Ratio field (CCFG.PCIDIVMODE) of the Chip Configuration Register changes the PCI Clock frequency from 33 MHz to 66 MHz. (7) The software reset bit (PCICCFG.SRST) is cleared after the PLL stabilizes (about 10 ms). (8) Deassert the PCI Bus Reset signal. Each PCI device detects assertion of the M66EN signal if necessary and performs the process. When the TX4938 is in the Satellite mode, the M66EN signal becomes the input signal. It is possible to read this state from the 66 MHz Drive Status bit (P2GSTATUS.M66EN) of the P2G Status Register. 10-13 Chapter 10 PCI Controller PCI Reset is detected by either using the PCI Bus Reset Signal as the TX4938 overall reset signal or using the PCI Bus Reset Signal assertion detection device that the system provides. Then, the software reset the PCI Controller. The software uses a hardware reset (PCICCFG.HRST) of the PCI Controller Configuration Register to reset the PCI Controller. 10.3.9 Power Management The TX4938 PCI Controller supports power management functions that are compliant to PCI Bus Power Management Interface Specifications Version 1.1. The PCI Host device controls the system status by reporting the power management state to the PCI Satellite device. Also, the PCI Satellite device uses the PME* signal to report requests for changing the power management state or to report to the PCI Host device that a power management event has occurred. 10.3.9.1 Power Management State In the case of the PCI Bus Power Management Interface Specifications, four power management states are defined from State D0 to State D3. The TX4938 supports states D0 through D3. Figure 10.3.7 illustrates the power management state transition. After Power On Reset, or when transitioning from the D3HOT state to the D0 state, the power management state becomes uninitialized D0. If initialized by the system software at this point, the state transitions to D0 Active. If an external PCI Host device writes 11b (D3HOT) to the PowerState field of the Power Management Control Status Register (PMCSR) of the Configuration space when in the Satellite mode, then the Power Management State Change bit (P2GSTATUS.PMSC) of the P2G Status Register is set and transitions to the D3HOT state. It then becomes possible to report Power State Change interrupts. The PowerState field value can be read from the PowerState field (PCISSTATUS.PS) of the Satellite Mode PCI Status Register. The TX4938 uses the software to change the system status after a status change is detected. Power On Reset (RESET*) D0 Uninitialized Initialization by the System Software PCI RST* (RESET*) D3cold D0 Active Software Reset VCCCut-off Change PMCSR PowerState D3hot Figure 10.3.7 Transition of the Power Management States 10-14 Chapter 10 PCI Controller 10.3.9.2 PME* Signal (Satellite Mode) The following PMEs (Power Management Events) are reported when in the Satellite mode. • The PCI Host device sets the PME_En bit of the PMCSR Register in the TX4938 Configuration space. This makes it possible for the TX4938 to assert the PME* signal. Then, the PME_En Set bit (P2GSTATUS.PMEES) of the P2G Status Register is set. Furthermore, it also becomes possible to generate PME_En Set interrupts. The PME_En bit value can be read from the PME_En bit (PCISSTATUS.PMEEN) of the Satellite Mode PCI Status Register. • Writing “1” to the PME bit (P2GCFG.PME) of the P2G Configuration Register sets the PME_Status bit of the PMCSR Register, then asserts the PME* signal, which is the open drain signal. PME is then reported to the PCI Host device. The PCI Host device checks the PMCSR PME_Status bit of each PCI device, then specifies the PCI device that asserted the PME* signal. After the process corresponding to PME ends, the PCI Host device writes “1” to the TX4938 PME_Status bit that reported PME, thereby reporting the end of the process. As a result, the PME_Status bit of the PMCSR Register is cleared and the PME* signal is deasserted. Then, the PME Status Clear bit (P2GSTATUS.PMECLR) of the P2G Status Register is set. It is also possible to generate PME Status Clear interrupts. 10.3.9.3 PME* Signal* (Host Mode) The PME Detection bit (PCICSTATUS.PMED) of the PCI Controller Status Register is set when an external satellite device asserts the PME* signal while the TX4938 is in the Host mode. It is also possible to generate PME Detection interrupts at this time. • • 10.3.10 PDMAC (PCI DMA Controller) The PCI DMA Controller (PDMAC) is a one-channel PCI Director Memory Access (DMA) controller. Data can be transferred bidirectionally between the G-Bus and the PCI Bus. Note: The PDMAC can only access the SDRAMC on the G-Bus. It does not provide support for access to other controllers on the G-Bus. 10.3.10.1 DMA Transfer The following DMA transfer procedure does not use the Chain DMA mode. 1. Address Register and Count Register Setting Sets values for the three following registers. • • • 2. PDMAC G-Bus Address Register (PDMGA) PDMAC PCI Bus Address Register (PDMPA) PDMAC Count Register (PDMCTR) Chain Address Register Setting Sets “0” to the PDMAC Chain Address Register (PDMCA). 10-15 Chapter 10 PCI Controller 3. PDMAC Status Register (PDMSTATUS) Clearing Clears any remaining status from a previous DMA transfer. PDMAC Configuration register (PDMCFG) Setting Clears the Channel Reset bit (CHRST), and makes settings such as the data transfer direction (XFRDIRC), and the data transfer unit size (XFRSIZE). DMA Transfer Initiation Setting the Transfer Active bit (XFRACT) of the PDMAC Configuration Register initiates DMA transfer. Termination Report When the DMA data transfer terminates normally, the Normal Data Transfer Complete bit (NTCMP) of the PDMAC Status Register (PDMSTATUS) is set. An interrupt is then reported if the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) of the PDMAC Configuration Register is set. If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Configuration register is set. 10.3.10.2 Chain DMA DMA Command Descriptors are 4 QWORD (32-Byte) data structures indicated in Table 10.3.6 that are placed in memory. Storing the starting memory address of another DMA Command Descriptor in the Offset 0 Chain Address Field makes it possible to configure a chain list for the DMA command Descriptor. Set “0” in the Chain Address field of the DMA Command Descriptor at the end of the chain list. When the DMA transfer specified by one DMA Command Descriptor ends, the PDMAC reads the next DMA Command Descriptor that the Chain Address field automatically points to, then continues the DMA transfer. Such continuous DMA transfer that uses multiple descriptors in a chain format is referred to as the Chain DMA mode. When a DMA Command Descriptor is placed to an address that does not extend across a 32 QWORD boundary in memory, this transfer method is more efficient since data can be read by a single G-Bus Burst Read transaction. Table 10.3.6 DMA Command Descriptors Offset Address 0x00 0x08 0x10 0x18 4. 5. 6. Field Name Chain Address G-Bus Address PCI Bus Address Count Transfer Destination Register PDMAC Chain Address Register (PDMCA) PDMAC G-Bus Address Register (PDMGA) PDMAC PCI Bus Address Register (PDMPA) PDMAC Count Register (PDMCTR) 10-16 Chapter 10 PCI Controller The DMA transfer procedure is as follows when in the Chain DMA mode. 1. Count Register Setting Sets “0” to the PDMAC Count Register (PMDCTR). DMA Command Descriptor Chain Construction Constructs the DMA Command Descriptor Chain in memory. PDMAC Status Register (PDMSTATUS) Clearing Clears any remaining status from a previous DMA transfer. PDMAC Configuration Register (PDMCFG) Setting Clears the Channel Regster bit (CHRST) and makes settings such as the data transfer direction (XFRDIRC) and the data transfer unit size (XFRSIZE). DMA Transfer Initiation Setting the address of the DMA Command descriptor that is at the beginning of the Chain List in the PDMAC Chain Address Register (PDMCA) automatically initiates DMA transfer. First, the values stored in each field of the DMA Command Descriptor that is at the beginning of the Chain List are read to each corresponding PDMAC Register, then DMA transfer is performed according to the read values. If a value other than “0” is stored in the PDMAC Chain Address Register (PDMCA), data transfer of the size stored in the PDMAC Count Register is complete, then the DMA Command Descriptor value for the memory address specified by the PDMAC Chain Address Register is read. When the Chain Address field value reads a descriptor of “0”, the PDMAC Chain Address Register value is not updated and the previous value (address of the Data Command Descriptor at which the Chain Address field value is “0” when read) is held. 0 value judgement is performed when the lower 32 bits of the PDMAC Chain Address Register are rewritten. DMA transfer is automatically initiated if the value was not “0”. Therefore, please write to the upper 32 bits first when writing to the PDMAC Chain Address Register using a 32-bit Store instruction. 6. Termination Report When DMA data transfer of all descriptor chains terminates normally, the Normal Chain Complete bit (NCCMP) of the PDMAC Status Register is set. An interrupt is reported if the Chain Termination Interrupt Enable bit (MCCMPIE) of the PDMAC Configuration register (PDMCFG) is set. Also, the Normal Data Transfer Complete bit (NTCMP) of the DPMAC Status Register is set each time the DMA data transfer specified by a DMA Command Descriptor terminates normally. An interrupt is reported if the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) of the PDMAC Configuration Register (PDMCFG) is set. If an error is detected during DMA transfer, the error cause is recorded in the lower 5 bits of the PDMAC Status Register and the transfer is aborted. An interrupt is then reported if the Error Detection Interrupt Enable bit (ERRIE) of the PDMAC Configuration register is set. 2. 3. 4. 5. 10-17 Chapter 10 PCI Controller 10.3.10.3 Dynamic Chain Operation It is possible to dynamically add other DMA Command Descriptor Chains to a DMA Command Descriptor Chain that is currently being processed when executing DMA data transfer. This is done according to the following procedure. 1. DMA Command Descriptor Chain Construction Constructs a DMA Command Descriptor Chain in memory. Addition of DMA Command Descriptor Chains Substitutes the address of the command descriptor that is at the beginning of the descriptor chain to be added into the Descriptor Chain Address field at the end of the DMA Command Descriptor Chain that is currently performing DMA transfer. Chain Enable bit checking Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Configuration Register (PDMCFG). If the read value is “0”, then the Chain Address field value of the DMA Command Descriptor indicated by the address stored in the PDMAC Chain Address Register (PDMCA) is written to the PDMAC Chain Address Register (PDMCA) 2. 3. 10.3.10.4 Data Transfer Size The Transfer Size field (PDMCFG.XFERSIZE) of the PDMAC Configuration Register specifies the transfer size of each G-Bus transaction in a DMA transfer. The transfer size can be selected from one of the following: 1 DWORD, 1 QWORD, or 4 QWORD (Burst transfer). 1 QWORD or 4 QWORD can only be selected as the transfer size when the setting of the PDMAC G-Bus Address Register (PDMGA) and the PDMAC PCI Bus Address Register (PDMPA) is a 64-bit address boundary and the PDMAC Count Register (PDMCTR) setting is an 8-byte multiple. 1 DWORD must be selected as the transfer size in all other cases. 10.3.11 Error Detection, Interrupt Reporting The PCI Controller reports the four following types of interrupts to the Interrupt Controller (IRC). • • • • Normal Operation Interrupt PDMAC Interrupt Power Management Interrupt Error Detection Interrupt (Interrupt Number: 16, PCIC) (Interrupt Number: 15, PDMAC) (Interrupt Number: 23, PCIPME) (Interrupt Number: 22, PCIERR) When each cause is detected, an interrupt is reported if the corresponding Status bit is set, and the corresponding Interrupt Enable Bit is set. The following tables list the name of each interrupt cause, the Status bit, and the Interrupt Enable bit. Please refer to the explanation of each Status bit for more information regarding each interrupt cause. 10.3.11.1 Normal Operation Interrupt Name M66EN Signal Assert Detect Status Bit P2GSTATUS M66EN Interrupt Enable Bit P2GMASK M66ENIE 10-18 Chapter 10 PCI Controller 10.3.11.2 PDMAC Interrupts Name Normal Chain Termination Normal Data Transfer Termination Inter-Transfer Stall Time Reached Configuration Error PCI Fatal Error G-Bus Chain Error G-Bus Data Error PDMSTATUS Status Bit NCCMP NTCMP STLTRF CFGERR PCIERR CHNERR DATAERR Interrupt Enable Bit NCCMPIE NTCMPIE PDMCFG ERRIE 10.3.11.3 Power Management Interrupts Name PM Status Change Detect PME_En Set Detect PME Status Clear Detect PME Detect PCICSTATUS P2GSTATUS Status Bit PMSC PMEES PMECLR PME Interrupt Enable Bit PMSCIE P2GMASK PCICMASK PMEESIE PMECLRIE PMEIE 10.3.11.4 Error Detection Interrupts Name Parity Error Detect System Error Report Master Abort Receive Target Abort Receive Target Abort Report Master Data Parity Error TRDY Timeout Error Retry Timeout Error Broken Master Detect Long Burst Transfer Detect Negative Increase Burst Transfer Detect Zero Increase Burst Transfer Detect PERR* Detect SERR* Detect G-Bus Bus Error Detect PCICSTATUS G2PSTATUS PBASTATUS PCISTATUS / PCISSTATUS Status Bit DPE SSE RMA RTA STA MDPE IDTTOE IDRTOE BMD TLB NIB ZIB PERR SERR GBE Interrupt Enable Bit DPEIE SSEIE PCIMASK RMAIE RTAIE STAIE MDPEIE G2PMASK PBAMASK IDTTOEIE IDRTOEIE BMDIE TLBIE NIBIE PCICMASK ZIBIE PERRIE SERRIE GBEIE Note: In the initiator write cycle, access on the G-Bus has been finished before access on the PCI bus is finished (Post write). Therefore, when an error occurs on PCI bus, it is reported with an error detection interrupt, as shown above. In the initiator read cycle, when an error occurs on the PCI bus access, PCIC responds with a G-Bus error instead of returning read data to the G-Bus. Setting "0" to the IRBER bit of the PCICFG register suppresses output of a G-Bus error during initiator read. 10-19 Chapter 10 PCI Controller 10.3.12 PCI Bus Arbiter Configuration settings (DATA[2] signal) during boot up select whether to use the on-chip PCI Bus arbiter (Internal PCI Bus Arbiter mode) or to use the External PCI Bus arbiter (External PCI Bus Arbiter mode). When in the Internal PCI Bus Abiter mode, setting the PCI Bus Arbiter Enable bit (PBACFG.PBAEN) of the PCI Bus Arbiter Configuration Register starts operation. The on-chip PCI Bus arbiter can arbitrate eight sets of PCI Bus usage requests from the Bus Master. Five ports are used: one for the PCI Controller bus master and four for External Bus masters. The three remaining ports are reserved for future expanded features. 10.3.12.1 Request Signal, Grant Signal The four external Bus Masters are connected to the REQ[3:0] signal and the GNT[3:0]* signal. Also, when in the External PCI Bus Master mode, the REQ[0]* signal becomes the PCI Bus Request Output signal and the GNT[0]* signal becomes the Bus Usage Permission Input Signal. Furthermore, the REQ[1]* signal can be used as an interrupt output signal to the external devices (see 14.3.7 for more information). 10.3.12.2 Priority Control As illustrated below in Figure 10.3.8, a combination of two round-robin sequences is used as the arbitration algorithm that determines the priority of Internal PCI Bus arbiter bus requests. The round-robin with the lower priority (Level 2) consists of Masters W - Z, and the round-robin with the high priority (Level 1), consists of Master A - D and Level 2 Masters. The PCI Bus Arbiter Request Port Register (PBAREQPORT) specifies whether to allocate the PCI Controller and the four External Bus Masters to Masters A-D or W - Z. Level 1 (Prirority: High) Master B Master C Master A Level 2 Master D Level 2 (Priority: Low) Master W Master Z Master X Master Y Figure 10.3.8 PCI Bus Arbitration Priority 10-20 Chapter 10 PCI Controller The Bus Master priority is determined based on the Level 1 round-robin sequence. However, when Level 2 is used inside Level 1, the Level 2 Bus Master priority is determined based on the Level 2 round-robin sequence. All 8 Bus Masters cannot be used on the TX4938. However, the Bus Master priority would be as follows if we assume there is a hypothetical device that can use all 8 Bus Masters and all 8 Bus Masters (Masters A – D, W – Z) simultaneously requested the bus. A→B→C→D→W →A→ B→ C→ D → X →A→ B→ C→ D →Y →A→ B→ C→ D → Z → A (returns to the beginning) Since the priority can only transition in the order indicated by the above arrows (or the arrows in Figure 10.3.8, if we assume that the three Bus Masters A, B, and W exist, then Master B will obtain the bus first. If A and W then simultaneously request the bus, then PCI Bus ownership will transition in the order B → W → A. 10.3.12.3 Bus Parking The On-chip PCI Bus Arbiter supports bus parking. The last PCI Bus Master is made the Park Master when the Fix Park Master bit (FIXPM) of the PCI Bus Arbiter Configuration Register (PBACFG) is cleared (in the default state). When this bit is set, the Internal PCI Bus Arbiter Request A Port (Master A) becomes the Park Master. 10.3.12.4 Broken Master Detect The TX4938 On-chip PCI Bus Arbiter has a function for automatically detecting broken masters. If the PCI Bus Master requests and is granted the bus when the PCI Bus is in the Idle state, this master must assert the FRAME* signal within 16 PCI block cycles and start a transaction. The PCI Bus Arbiter recognizes any device that breaks this rule as a broken bus master and removes that device from the bus arbitration sequence. This detection function is enabled when the Broken Master Check Enable bit (BMCEN) of the PCI Bus Arbiter Configuration Register (PBACFG) is set. When a broken master is detected, the Broken Master Detection bit (PBSTATUS.BMD) of the PCI Bus Arbiter Status Register is set and the bit in the PCI Bus Arbiter Broken Master Register (PBABM) that corresponds to that master is set. Then it also becomes possible to report an interrupt. 10-21 Chapter 10 PCI Controller 10.3.12.5 Special Programming There may be some devices among PCI bus masters that operate differently from typical PCI devices. PCI devices with the following characteristics can be made usable by changing the programming of the PCI bus arbiter. 1. Bus masters that can not re-assert REQ unless GNT is once deasserted after deasserting REQ • • 2. Assign the bus master to a request port other than Port A through the PBAREQPORT register (at 0xD100). (Assign the TX4938 to Port A.) Enable the Fixed Parked Master (FIXPA) bit in the PBACFG register (at 0xD104). Bus masters that initiate a PCI transaction even when the deassertion of GNT has taken away their bus mastership before the start of the transaction • Assign the bus master to request port A, B, C or D through the PBAREQPORT register (at 0xD100). For example, a bus master with both of the above characteristics can be used by configuring the PCI bus arbiter as follows: Set the internal PCI bus arbiter to the fixed parked master. Assign the TX4938 to request port A. Assign the bus master to request port B. If this bus master is connected to REQ[3] and broken master checking is to be enabled, values to be written to the PBACFG and PBAREQPORT registers are as follows: PBACFG (at 0xD104): 0x0000000B PBAREQPORT (at 0xD100): 0x73546210 10.3.13 PCI Boot Setting the configuration during boot up (ADDR[8:6]) makes it possible to set the reset exception vector address of the TX49/H3 core to PCI Bus address 0x00_BFC0_0000. Two windows of the memory space from the G-Bus to the PCI Bus space are used when in the PCI Boot mode. The defaults of several registers are changed as indicated below. • • • • • • G-Bus base address (G2GBASE): Space size (G2PM2MASK): PCI Bus base address (G2PM2PBASE): Initiator Memory Space 2 Enable (PCICCFG.G2PM2EN): Bus Master bit (PCISTATUS.BM) [Only when in the Host mode] Target Configuration Access Ready (PCICSTAUTS.TCAR) [Only when in the Satellite mode] 0x0_1FC0_0000 4 MB 0x00_BFC0_0000 1 1 1 Also, the on-chip PCI Bus Arbiter cannot be used when the PCI Boot mode is being used while in the Satellite mode. 10-22 Chapter 10 PCI Controller 10.3.14 Set Configuration Space In Table 10.5.1, the values for the registers inside the PCI Configuration Space Register that have a gray background can be rewritten using one of the two following methods. 10.3.14.1 Set the Configuration Space Using EEPROM Load values during Reset by connecting standard 93C46/93C48 EEPROM to a dedicated port. The PCI Controller reads 16-bit half-word data for address 2n (n: 0, 1, 2, …, 31) of the PCI Configuration Space from EEPROM address (2n + 2 - 4(n mod 2)). Also, 16-bit data is read in order from the upper bits to the lower bits. The EEPROM values that correspond to the registers in Table 10.5.1 that have a white background are “don’t care”. 10.3.14.2 Set the Configuration Space Using Software Reset By using the following procedure, it is possible to use the software to set the configuration space without using EEPROM. (1) Set the value to be loaded in the Configuration Data 0 Register (PCICDATA0), the Configuration Data 1 Register (PCICDATA1), the Configuration Data 2 Register (PCICDATA2), and the Configuration Data 3 Register (PCICDATA3). (2) Set the Load Configuration Data Register bit (LCFG) of the PCI Controller Configuration Register (PCICCFG) and the Software Reset bit (SRST). (3) Clear the Software Reset bit (PCICCFG.SRST) at least four PCI Bus clock cycles later. This starts loading the data. After these processes are complete, please set the Target Configuration Access Ready bit (PCICCFG.TCAR) of the PCI Controller Configuration Register to be able to accept access to the PCI Configuration space. 10.3.15 PCI Clock The PCI bus signals are synchronized by the PCI clock applied to the PCICLKIN pin. Therefore, in PCI clock output mode, the PCI output clock must be connected to the PCICLKIN pin. 10-23 Chapter 10 PCI Controller 10.4 PCI Controller Control Register Table 10.4.1 lists the registers contained in the PCI Controller Control Register. Parentheses in the register names indicate the corresponding PCI Configuration Space Register. Table 10.4.1 PCI Controller Control Register (1/2) Section 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.4.10 10.4.11 10.4.12 10.4.13 10.4.14 10.4.15 10.4.16 10.4.17 10.4.18 10.4.19 10.4.20 10.4.21 10.4.22 10.4.23 10.4.24 10.4.25 10.4.26 10.4.27 10.4.28 10.4.29 10.4.30 10.4.31 10.4.32 10.4.33 10.4.34 10.4.35 10.4.36 10.4.37 10.4.38 10.4.39 10.4.40 Address 0xD000 0xD004 0xD008 0xD00C 0xD010 0xD014 0xD018 0xD01C 0xD020 0xD024 0xD02C 0xD034 0xD03C 0xD040 0xD080 0xD084 0xD088 0xD08C 0xD090 0xD094 0xD098 0xD09C 0xD100 0xD104 0xD108 0xD10C 0xD110 0xD114 0xD118 0xD11C 0xD120 0xD128 0xD130 0xD138 0xD140 0xD144 0xD148 0xD14C 0xD150 0xD158 Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 64 64 64 64 32 32 32 32 64 64 Mnemonic PCIID PCISTATUS PCICCREV PCICFG1 P2GM0PLBASE P2GM0PUBASE P2GM1PLBASE P2GM1PUBASE P2GM2PBASE P2GIOPBASE PCISID PCICAPPTR PCICFG2 G2PTOCNT G2PSTATUS G2PMASK PCISSTATUS PCIMASK P2GCFG P2GSTATUS P2GMASK P2GCCMD PBAREQPORT PBACFG PBASTATUS PBAMASK PBABM PBACREQ PBACGNT PBACSTATE G2PM0GBASE G2PM1GBASE G2PM2GBASE G2PIOGBASE G2PM0MASK G2PM1MASK G2PM2MASK G2PIOMASK G2PM0PBASE G2PM1PBASE Register Name ID Register (Device ID, Vendor ID) PCI Status, Command Register (Status, Command) Class Code, Revision ID Register (Class Code, Revision ID) PCI Configuration 1 Register (BIST, Header Type, Latency Timer, Cache Line Size) P2G Memory Space 0 PCI Lower Base Address Register (Base Address 0 Lower) P2G Memory Space 0 PCI Upper Base Address Register (Base Address 0 Upper) P2G Memory Space 1 PCI Lower Base Address Register (Base Address 1 Lower) P2G Memory Space 1 PCI Upper Base Address Register (Base Address 1 Upper) P2G Memory Space 2 PCI Base Address Register (Base Address 2) P2G I/O Space PCI Base Address Register (Base Address 3) Subsystem ID Register (Subsystem ID, Subsystem Vendor ID) Capabilities Pointer Register (Capabilities Pointer) PCI Configuration 2 Register (Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line) G2P Timeout Count Register (Retry Timeout Value, TRDY Timeout Value) G2P Status Register G2P Interrupt Mask Register Satellite Mode PCI Status Register (Status, PMCSR) PCI Status Interrupt Mask Register P2G Configuration Register P2G Status Register P2G Interrupt Mask Register P2G Current Command Register PCI Bus Arbiter Request Port Register PCI Bus Arbiter Configuration Register PCI Bus Arbiter Status Register PCI Bus Arbiter Interrupt Mask Register PCI Bus Arbiter Broken Master Register PCI Bus Arbiter Current Request Register (for diagnositics) PCI Bus Arbiter Current Grant Register (for diagnostics) PCI Bus Arbiter Currrent State Register (for diagnostics) G2P Memory Space 0 G-Bus Base Address Register G2P Memory Space 1 G-Bus Base Address Register G2P Memory Space 2 G-Bus Base Address Register G2P I/O Space G-Bus Base Address Register G2P Memory Space 0 Address Mask Register G2P Memory Space 1 Address Mask Register G2P Memory Space 2 Address Mask Register G2P I/O Space Address Mask Register G2P Memory Space 0 PCI Base Address Register G2P Memory Space 1 PCI Base Address Register 10-24 Chapter 10 PCI Controller Table 10.4.1 PCI Controller Control Register (2/2) Section 10.4.41 10.4.42 10.4.43 10.4.44 10.4.45 10.4.46 10.4.47 10.4.48 10.4.49 10.4.50 10.4.51 10.4.52 10.4.53 10.4.54 10.4.55 10.4.56 10.4.57 10.4.58 10.4.59 10.4.60 10.4.61 10.4.62 10.4.63 Address 0xD160 0xD168 0xD170 0xD174 0xD178 0xD180 0xD188 0xD190 0xD198 0xD1A0 0xD1A4 0xD1C8 0xD1CC 0xD1D0 0xD1D4 0xD1D8 0xD1DC 0xD200 0xD208 0xD210 0xD218 0xD220 0xD228 Size 64 64 32 32 32 64 64 64 64 32 32 32 32 32 32 32 32 64 64 64 64 64 64 Mnemonic G2PM2PBASE G2PIOPBASE PCICCFG PCICSTATUS PCICMASK P2GM0GBASE P2GM1GBASE P2GM2GBASE P2GIOGBASE G2PCFGADRS G2PCFGDATA G2PINTACK G2PSPC PCICDATA0 PCICDATA1 PCICDATA2 PCICDATA3 PDMCA PDMGA PDMPA PDMCTR PDMCFG PDMSTATUS Register Name G2P Memory Space 2 PCI Base Address Register G2P I/O Space PCI Base Address Register PCI Controller Configuration Register PCI Controller Status Register PCI Controller Interrupt Mask Register P2G Memory Space 0 G-Bus Base Address Register P2G Memory Space 1 G-Bus Base Address Register P2G Memory Space 2 G-Bus Base Address Register P2G I/O Space G-Bus Base Address Register G2P Configuration Address Register G2P Configuration Data Register G2P Interrupt Acknowldge Data Register G2P Special Cycle Data Register Configuration Data 0 Register Configuration Data 1 Register Configuration Data 2 Register Configuration Data 3 Register PDMAC Chain Address Register PDMAC G-Bus Address Register PDMAC PCI Bus Address Register PDMAC Count Register PDMAC Configuration Register PDMAC Status Register 10-25 Chapter 10 PCI Controller 10.4.1 ID Register (PCIID) 0xD000[HH5] The Device ID field corresponds to the Device ID Register in the PCI Configuration Space, and the Vendor ID field corresponds to the Vendor ID register of the PCI Configuration Space. This register cannot be access when in the Satellite mode. 31 DID R/L 0x0183 15 VID R/L 0x102F : Type : Initial value 0 : Type : Initial value 16 Bits 31:16 Mnemonic DID Field Name Device ID Description Read/Write R/L Device ID (Default: 0x0183) This register indicates the ID that is allocated to a device. The ID can be changed by loading data from a configuration EEPROM during initialization. Vendor ID (Default: 0x102F) This register indicates the device product that is allocated by PCI SIG. The product allocation can be changed by loading data from a configuration EEPROM during initialization. R/L 15:0 VID Vendor ID Figure 10.4.1 ID Registers 10-26 Chapter 10 PCI Controller 10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004 The upper 16 bits correspond to the Status Register in the PCI Configuration Space, and the lower 16 bits correspond to the Command Register in the PCI Configuration Space. This register cannot be accessed when in the Satellite mode. However, it is possible to read some values of the upper 16 bits from the Satellite Mode PCI Status Register (PCISSTATUS). 31 DPE 30 SSE 29 RMA 28 RTA 27 STA 26 DT R 01 10 Reserved 25 24 23 22 21 20 CL R 1 3 SC R 0 2 BM R/W 0/1 1 0 19 Reserved : Type : Initial value 16 MDPE FBBCP Reserved 66MCP R/W1C 0 R 1 R 1 R/W1C R/W1C R/W1C R/W1C R/W1C 0 0 0 0 0 15 9 8 7 6 5 4 FBBEN SEREN STPC PEREN VPS MWIEN R/W 0 R/W 0 R 0 R/W 0 R 0 R/W 0 MEMSP IOSP R/W 0 R/W : Type 0 : Initial value Bit 31 Mnemonic DPE Field Name Detected Parity Error Description Detected Parity Error (Default: 0) Indicates that a parity error was detected. A parity error is detected in the three following situtations: • Detected a data parity error as the Read command PCI initiator. • Detected a data parity error as the Write command PCI target. • Detected an address parity error. This bit is set regardless of the setting of the Parity Error Response bit (PCISTATUS.PEREN) of the PCI Status, Command Register. 1: Detected a parity error. 0: Did not detect a parity error. Read/Write R/W1C 30 SSE Signaled System Error Signaled System Error (Default: 0) Detects either an address parity error or a special cycle data parity error. This bit is set when the SERR* signal is asserted. 1: Asserted the SERR* signal 0: Did not assert the SERR* signal. Received Master Abort (Default: 0) This bit is set when a Master Abort aborts a PCI Bus Transaction when the PCI Controller operates as the PCI initiator (except for special cycles). 1: Transaction was aborted by a Master Abort. 0: Transaction was not aborted by a Master Abort. Received Target Abort (Default: 0) This bit is set when a Target Abort aborts a PCI Bus Transaction when the PCI Controller operates as the PCI initiator. 1: Transaction was aborted by a Target Abort. 0: Transaction was not aborted by a Target Abort. Signaled Target Abort (Default: 0) This bit is set when a Target Abort aborts a PCI Bus Transaction when the PCI Controller operates as the PCI target. 1: Bus transaction was aborted by a Target Abort. 0: Bus transaction was not aborted by a Target Abort. DEVSEL Timing (Fixed Value: 01) Three DEVSEL assert timings are defined in the PCI 2.2 Specifications: 00b = Fast; 01b = Medium; 10b = Slow; 11b = Reserved). With the exception of Read Configuration and Write Configuration, when the PCI Controller is the PCI target, the DEVSEL signal is asserted to a certain bus command and indicates the slowest speed for responding to the PCI Bus Master. R/W1C 29 RMA Received Master Abort R/W1C 28 RTA Received Target Abort R/W1C 27 STA Signaled Target Abort R/W1C 26:25 DT DEVSEL Timing R Figure 10.4.2 PCI Status, Command Register (1/3) 10-27 Chapter 10 PCI Controller Bit 24 Mnemonic MDPE Field Name Master Data Parity Error Description Master Data Parity Error (Default: 0) Indicates the a parity error occurred when the PCI Controller is the PCI initiator. This bit is not set when the PCI Controller is the target. This bit is set when all of the three following conditions are met. • It has been detected that the PERR* signal was set either directly or indirectly. • The PCI Controller is the Bus Master for a PCI Bus transaction during which an error occurred. • The Parity Error Response bit of the PCI Status Command Register (PCISTATUS.PEREN) has been set. Fast Back-to-Back Capable (Fixed Value: 1) Indicates whether target access of a fast back-to-back transaction can be accepted. Is fixed to “1”. 66 MHz Capable (Fixed Value: 1) Indicates the 66 MHz operation is possible. Is fixed to “1”. Capabilities List (Fixed Value: 1) Indicates that the capabilities list is being implemented. Is fixed to “1”. Fast Back-to-Back Enable (Default: 0) Indicates that issuing of fast back-to-back transactions has been enabled. 1: Enable 0: Disable SERR* Enable (Default: 0) Enables/Disables the SERR* signal. The SERR* signal reports that either a PCI Bus address parity error or a special cycle data parity error was detected. The SERR* signal is only asserted when the Parity Error Response bit is set and this bit is set. 1: Enable 0: Disable Stepping Control (Fixed Value: 0) Indicates that stepping control is not being supported. Parity Error Response (Default 0) Sets operation when a PCI address/data parity error is detected. A parity error response (either when the Parity Error Response bit (PCISTATUS.PEREN) of the PERR* Signal Assert or PCI Status, Command Register is set, or the SERR* signal is asserted) is performed only when this bit is set. When this bit is cleared, the PCI Controller ignores all parity errors and continues the transaction process as if the parity of that transaction was correct. 1: Parity error response is performed. 0: Parity error response is not performed. VGA Palette Snoop (Fixed Value: 0) Indicates that the VGA palette snoop function is not supported. Read/Write R/W1C 23 FBBCP Fast Back-toBack Capable Reserved R 22 21 20 19:10 9 FBBEN 66MCP CL ⎯ R R ⎯ R/W 66 MHz Capable Capabilities List Reserved Fast Back-toBack Enable 8 SEREN SERR* Enable R/W 7 6 STPC PEREN Stepping Control Parity Error Response R R/W 5 4 VPS MWIEN VGA Palette Snoop Memory Write and Invalidate Enable Special Cycles Bus Master R R/W Memory Write and Invalidate Enable (Default: 0) Controls whether to use the Memory Write and Invalidate command instead of the Memory Write command when the PCI Controller is the initiator. Special Cycles (Fixed Value: 0) Indicates that special cycles will not be accepted as PCI targets. Bus Master (Default: 0/1) The default is only “1” when in the PCI Boot mode and in the Host mode. 1: Operates as the Bus Master. 0: Does not operate as the Bus Master. R R/W 3 2 SC BM Figure 10.4.2 PCI Status, Command Register (2/3) 10-28 Chapter 10 PCI Controller Bit 1 Mnemonic MEMSP Field Name Memory Space Description Memory Space (Default: 0) 1: Respond to PCI memory access. 0: Do not respond to PCI memory access. I/O Space (Default: 0) 1: Respond to PCI I/O access. 0: Do not respond to PCI I/O access. Read/Write R/W 0 IOSP I/O Space R/W Figure 10.4.2 PCI Status, Command Register (3/3) 10-29 Chapter 10 PCI Controller 10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008 The Class Code field corresponds to the Class Code Register of the PCI Configuration Space, and the Revision ID field corresponds to the Revision ID Register of the PCI Configuration Space. This register cannot be accessed when in the Satellite mode. 31 CC R/L 0x0600 15 CC R/L 0x00 8 7 RID R/L : Type : Initial value 0 : Type : Initial value 16 Bits 31:8 Mnemonic CC Field Name Class Code Description Class Code (Default: 0x060000) Classifies the device types. The default is 060000h, which defines the PCI Controller as a Host bridge device. It is possible to change the device type by loading data from Configuration EEPROM during initialization. Revision ID Indicates the device revision ID. Please contact our Engineering Department for the exact value. It is possible to change the revision ID by loading data from Configuration EEPROM during initialization. Read/Write R/L 7:0 RID Revision ID R/L Figure 10.4.3 Class Code, Revision ID Register 10-30 Chapter 10 PCI Controller 10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C The following fields correspond to the following registers. BIST field → BIST Register of the PCI Configuration Space Header Type field → Header Type Register in the PCI Configuration Space Latency Timer field → Latency Timer Register of the PCI Configuration Space Cache Line Size field → Cache Line Size Register of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 BISTC R 0 15 30 Reserved 24 23 MFUNS R 0 22 HT R/L 0x00 16 : Type : Initial value 0 CLS R/W 0x00 : Type : Initial value 8 LT R/W 0x00 7 Bit 31 30:24 23 22:16 Mnemonic BISTC Field Name BIST Capable Reserved Description BIST Capable (Fixed Value: 0) Indicates that the BIST function is not being supported. Multi-Function (Fixed Value: 0) 0: Indicates that the device is a single-function device. Header Type (Default: 0x00) Indicates the Header type. 0000000: Header Type 0 It is possible to change the header type by loading data from Configuration EEPROM during initialization. Latency Timer (Default: 0x00) Sets the latency timer value. Specifies the PCI Bus clock count during which to abort access when the GNT* signal is deasserted during PCI access. Since the lower two bits are fixed to “0”, cycle counts can only be specified in multiples of 4. Cache Line Size (Default: 0x00) Is used to select the PCI Bus command during a Burst Read transaction. See “10.3.3 Supported PCI Bus Commands)” for more information. Read/Write R ⎯ R R/L MFUNS HT Multi-Function Header Type 15:8 LT Latency Timer R/W 7:0 CLS Cache Line Size R/W Figure 10.4.4 PCI Configuration 1 Register 10-31 Chapter 10 PCI Controller 10.4.5 P2G Memory Space 0 PCI Lower Base Address Register (P2GM0PLBASE) 0xD010 This register corresponds to the Memory Space 0 Lower Base Address Register at offset address 0x10 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 BA[31:29] R/W 0x00 15 Reserved 4 3 PF R 1 2 TYPE R 00 1 0 MSI R 0 : Type : Initial value 29 28 Reserved : Type : Initial value 16 Bit 31:29 Mnemonic BA[31:29] Field Name Base Address Description Base Address (Default: 0x00) Sets the lower address of the PCI base address in Target Access Memory Space 0. The size of Memory Space 0 is fixed at 512 MB. Prefetchable (Fixed Value: 1) 1: Indicates that memory is prefetchable. Type (Default: 00) 00: Indicades that an address is within a 32-bit address region. Memory Space Indicator (Fixed Value: 0) 0: Indicates that this Base Address Register is for use by the PCI Memory Space. Read/Write R/W 28:4 3 2:1 0 PF TYPE MSI Reserved Prefetchable Type Memory Space R R R ⎯ Figure 10.4.5 P2G Memory Space 0 PCI Lower Base Address Register 10-32 Chapter 10 PCI Controller 10.4.6 P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0xD014 This register is unused since the PCI Controller does not support the target dual-address cycle. It is forbidden to write to this register. 10.4.7 P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0xD018 This register corresponds to the Memory Space 1 Lower Base Address Register at offset address 0x18 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 BA[31:24] R/W 0x00 15 Reserved 24 23 Reserved 16 : Type : Initial value 4 3 PF R 1 2 TYPE R 00 1 0 MSI R 0 : Type : Initial value Bit 31:24 Mnemonic BA[31:24] Field Name Base Address Description Base Address (Default: 0x00) Sets the lower address of the PCI base address in Target Access Memory Space 1. The size of Memory Space 1 is fixed at 16 MB. Prefetchable (Fixed Value: 1) 1: Indicates that memory is prefetchable. Memory Type (Default: 00) 00: Indicates that memory is placed in the 32-bit address space. Memory Space Indicator (Fixed Value: 0) 0: Indicates that this Base Address Register is for use by the PCI Memory Space. Read/Write R/W 23:4 3 2:1 0 PF TYPE MSI Reserved Prefetchable Type Memory Space R R R ⎯ Figure 10.4.6 P2G Memory Space 1 PCI Lower Base Address Register 10-33 Chapter 10 PCI Controller 10.4.8 P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE) 0xD01C This register is unused since the PCI Controller does not support the target dual-address cycle. It is forbidden to write to this register. 10.4.9 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD020 This register corresponds to the Memory Space 2 Base Address Register at offset address 0x20 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 BA[31:20] R/W 0x000 15 Reserved 4 3 PF R 0 2 TYPE R 00 1 0 MSI R 0 : Type : Initial value 20 19 Reserved : Type : Initial value 16 Bit 31:20 Mnemonic BA[31:20] Field Name Base Address Description Base Address (Default: 0x00) Sets the PCI base address in Target Access Memory Space 2. The size of Memory Space 12 is fixed at 1 MB. Prefetchable (Fixed Value: 0) 0: Indicates that memory is not prefetchable. Memory Type (Default: 00) 00: Indicates that an address is within a 32-bit address region. Memory Space Indicator (Fixed Value: 0) 0: Indicates that this Base Address Register is for use by the PCI Memory Space. Read/Write R/W 19:4 3 2:1 0 PF TYPE MSI Reserved Prefetchable Type Memory Space R R R ⎯ Figure 10.4.7 P2G Memory Space 2 PCI Base Address Register 10-34 Chapter 10 PCI Controller 10.4.10 P2G I/O Space PCI Base Address Register (P2GIOPBASE) 0xD024 This register corresponds to the I/O Space Base Address at offset address 0x24 of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved 1 0 IOSI R 1 : Type : Initial value : Type : Initial value 16 Bit 31:8 Mnemonic BA[31:8] Field Name Base Address Description Read/Write Base Address (Default: 0x00) R/W Sets the PCI base address of the Target Access I/O Space. The size of this I/O space is fixed at 256 Bytes. ⎯ I/O Space Indicator (Fixed Value: 1) 1: Indicates that this Base Address Register is for use by the PCI I/O Space. R 7:1 0 IOSI Reserved I/O Space Figure 10.4.8 P2G I/O Space PCI Base Address Register 10-35 Chapter 10 PCI Controller 10.4.11 Subsystem ID Register (PCISID) 0xD02C The Subsystem ID field corresponds to the Subsystem ID Register of the PCI Configuration Space, and the Subsystem Vendor ID field corresponds to the Subsystem Vendor ID Register of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 SSID R/L 0x0000 15 SSVID R/L 0x0000 : Type : Initial value 0 : Type : Initial value 16 Bits 31:16 Mnemonic SSID Field Name Subsystem ID Description Subsystem ID (Default: 0x0000) This register is used to acknowledge either a subsystem that has a PCI device or an add-in board. It is possible to change the Subsystem ID by loading data from Configuration EEPROM during initialization. Subsystem Vendor ID (Default: 0x0000) This register is used to acknowledge either a subsystem that has a PCI device or an add-in board. It is possible to change the Subsystem ID by loading data from Configuration EEPROM during initialization. Read/Write R/L 15:0 SSVID Subsystem Vendor ID R/L Figure 10.4.9 Subsystem ID Register 10-36 Chapter 10 PCI Controller 10.4.12 Capabilities Pointer Register (PCICAPPTR) 0xD034 The Capabilities Pointer field corresponds to the Capabilities Pointer Register of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 Reserved : Type : Initial value 15 Reserved 8 7 CAPPTR R 0xDC : Type : Initial value 0 16 Bits 31:8 7:0 Mnemonic CAPPTR Field Name Reserved Capabilities Pointer Description Capabilities Pointer (Fixed Value: 0xDC) Indicates as an offset value the starting address of the capabilities list that indicates extended functions. Read/Write ⎯ R Figure 10.4.10 Capabilities Pointer Register 10-37 Chapter 10 PCI Controller 10.4.13 PCI Configuration 2 Register (PCICFG2) 0xD03C The following fields correspond to the following registers: Max. Latency field → Max_Lat Register of the PCI Configuration Space Min. Grant field → Min_Gnt Register of the PCI Configuration Space Interrupt Pin field → Interrupt Pin Register of the PCI Configuration Space Interrupt Line field → Interrupt Line Register of the PCI Configuration Space This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 ML R/L 0x0A 15 IP R/L 0x01 8 7 IL R/W 0x00 : Type : Initial value 24 23 MG R/L 0x02 0 : Type : Initial value 16 Bits 31:24 Mnemonic ML Field Name Maximum Latency Description Max_Lat (Maximum Latency) (Default: 0x0A) 00h: Does not use this register to determine PCI Bus priority. 01h-FFh: Specifies the time interval for requesting bus ownership. In units of 250 ns, assuming the PCICLK is 33 MHz. It is possible to change the maximum latency by loading data from Configuration EEPROM during initialization. Min_Gnt (Minimum Grant) (Default: 0x02) 00h: Is not used to calculate the latency timer value. 01h-FFh: Sets the time required for Burst transfer. In units of 250 ns, assuming the PCICLK is 33 MHz. It is possible to change this value by loading data from Configuration EEPROM during initialization. Interrupt Pin (Default: 0x01) Valid values: 00 - 04h 00h: Do not use interrupt signals. 01h: Use Interrupt signal INTA* 02h: Use Interrupt signal INTB* 03h: Use Interrupt signal INTC* 04h: Use Interrupt signal INTD* 05h - FFh: Reserved It is possible to change this value by loading data from Configuration EEPROM during initialization. When using either the REQ[2]* signal or the PIO signal to report an interrupt to an external device as the PCI device, please use EEPROM to set the connection with that device. Interrupt Line (Default: 0x00) This is a readable/writable 8-bit register. The software uses this register to indicate information such as the interrupt signal connection information. Operation of the TX4938 is not affected. Read/Write R/L 23:16 MG Minimum Grant R/L 15:8 IP Interrupt Pin R/L 7:0 IL Interrupt Line R/W Figure 10.4.11 PCI Configuration 2 Register 10-38 Chapter 10 PCI Controller 10.4.14 G2P Timeout Count Register (G2PTOCNT) 0xD040 The Retry Timeout field corresponds to the Retry Timeout Value Register of the PCI Configuration Space, and the TRDY Timeout field corresponds to the TRDY Timeout Value Register of the PCI Configuration Space. This register cannot be accessed when the PCI Controller is in the Satellite mode. 31 Reserved : Type : Initial value 15 RETRYTO R/W 0x80 8 7 TRDYTO R/W 0x80 : Type : Initial value 0 16 Bits 31:16 15:8 Mnemonic RETRYTO Field Name Reserved Retry Timeout Description Read/Write ⎯ R/W Retry Time Out (Default: 0x80) Sets the maximum number of retries to accept when operating as the initiator on the PCI Bus. Ends with an error when receiving more retry terminations than the set maximum number. Setting a “0” disables this timeout function. Note: Generally, disable retry time-out detection by setting this field to zero. Some PCI devices invoke more than 128 retries at normal times. TRDY Time Out (Default: 0x80) Sets the maximum value of the time to wait for assertion of the TRDY* signal when operating as the initiator on the PCI Bus. Setting a “0” disables this timeout function. Note: Generally, disable TRDY time-out detection by setting this field to zero. Some PCI devices exhibit a TRDY delay longer than 128 PCI clocks at normal times. R/W 7:0 TRDYTO TRDY Timeout Figure 10.4.12 G2P Timeout Count Register 10-39 Chapter 10 PCI Controller 10.4.15 G2P Status Register (G2PSTATUS) 31 Reserved : Type : Initial value 15 Reserved 2 1 0 0xD080 16 IDTTOE IDRTOE R/W1C R/W1C : Type 0x0 0x0 : Initial value Bit 31:2 1 0 Mnemonic IDTTOE IDRTOE Field Name Reserved TRDY Timeout Error Retry Timeout Error Description Initiator Detected TRDY Time Out Error (Default: 0x0) This bit is set when the initiator detects a TRDY timeout. Initiator Detected Retry Time Out Error (Default: 0x0) This bit is set when the initiator detects a Retry timeout. Read/Write ⎯ R/W1C R/W1C Figure 10.4.13 G2P Status Register 10-40 Chapter 10 PCI Controller 10.4.16 G2P Interrupt Mask Register (G2PMASK) 0xD084 31 Reserved : Type : Initial value 15 Reserved 2 1 0 16 IDTTOEIE IDRTOEIE R/W 0x0 R/W : Type 0x0 : Initial value Bit 31:2 1 Mnemonic IDTTOEIE Field Name Reserved TRDY Timeout Error Interrupt Enable Retry Timeout Error Interrupt Enable Description Initiator Detected TRDY Time Out Interrupt Enable (Default: 0x0) The initiator generates an interrupt when it detects a TRDY timeout. 1: Generates an interrupt. 0: Does not generate an interrupt. Initiator Detected Retry Time Out Interrupt Enable (Default: 0x0) The initiator generates an interrupt when it detects a Retry timeout. 1: Generates an interrupt. 0: Does not generate an interrupt. Read/Write ⎯ R/W 0 IDRTOEIE R/W Figure 10.4.14 G2P Interrupt Mask Register 10-41 Chapter 10 PCI Controller 10.4.17 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088 The PCI Status, Command Register (PCISTATUS) or the PMCSR Register of the Configuration Space cannot be accessed when the PCI Controller is in the Satellite mode. It is possible however to read values from either of these registers. 31 Reserved 26 25 PS R 0x0 15 DPE R 0x0 14 SSE R 0x0 13 RMA R 0x0 12 RTA R 0x0 11 STA R 0x0 10 DT R 0x1 9 8 MDPE R 0x0 24 23 PMEEN 22 Reserved 16 R 0x0 7 Reserved 0 : Type : Initial value : Type : Initial value Bit 31:24 25:24 Mnemonic PS Field Name Reserved Power State Description Read/Write ⎯ R PowerState (Default: 0x0) This is a shadow register of the PowerState field in the PMCSR Register. Note: Read this field in the following procedures. If other procedures are used, incorrect data may be read. (1) General procedures After checking the P2GSTATUS.PMSC bit is set, read the PS field. (2) Procedures to read at any time To read PS field directly, but not using the procedures shown above (1), read the PS field twice consecutively. Use the value if the same value is read. PME_En (Default: 0x0) This is a shadow register of the PME_En bit of the PMCSR Register. Detected Parity Error (Default: 0x0) This is a shadow register of the PCISTATUS.DPE bit. Signaled System Error (Default: 0x0) This is a shadow register of the PCISTATUS.SSE bit. Received Master Abort (Default: 0x0) This is a shadow register of the PCISTATUS.RMA bit. Received Target Abort (Default: 0x0) This is a shadow register of the PCISTATUS.RTA bit. Signaled Target Abort (Default: 0x0) This is a shadow register of the PCISTATUS.STA bit. DEVSEL Timing (Fixed Value: 0x1) This is a shadow register of the PCISTATUS.DT field. Master Data Parity Error Detected (Default: 0x0) This is a shadow register of the PCISTATUS.MDPE bit. R ⎯ R R R R R R R ⎯ 23 22:16 15 14 13 12 11 10:9 8 7:0 PMEEN PME Enable Reserved DPE SSE RMA RTA STA DT MDPE Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Set DEVSEL Timing Data Parity Detected Reserved Figure 10.4.15 Satellite Mode PCI Status Register 10-42 Chapter 10 PCI Controller 10.4.18 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C 31 Reserved : Type : Initial value 15 14 13 12 11 10 9 8 MDPEIE 16 7 Reserved 0 DPEIE SSEIE RMAIE RTAIE STAIE R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 Reserved R/W 0x0 : Type : Initial value Bit 31:16 15 Mnemonic DPEIE Field Name Reserved Detected Parity Error Interrupt Enable Description Detected Parity Error Interrupt Enable (Default: 0x0) Generates an interrupt when a parity error is detected. Usually, this interrupt is masked and a Master Data Parity error signals the error to the system. 1: Generates an interrupt. 0: Does not generate an interrupt. Signaled System Error Interrupt Enable (Default: 0x0) Generates an interrupt when a system error is signaled. 1: Generates an interrupt. 0: Does not generate an interrupt. Received Master Abort Interrupt Enable (Default: 0x0) Generates an interrupt when a Master Abort is received. 1: Generates an interrupt. 0: Does not generate an interrupt. Received Target Abort Interrupt Enable (Default: 0x0) Generates an interrupt when a Target Abort is received. 1: Generates an interrupt. 0: Does not generate an interrupt. Signaled Target Abort Interrupt Enable (Default: 0x0) Generates an interrupt when a Target Abort is signaled. 1: Generates an interrupt. 0: Does not generate an interrupt. Received Master Abort (Default: 0x0) This is a shadow register of the PCISTATUS.RMA bit. Received Target Abort (Default: 0x0) This is a shadow register of the PCISTATUS.RTA bit. Signaled Target Abort (Default: 0x0) This is a shadow register of the PCISTATUS.STA bit. Master Data Parity Detected Interrupt Enable (Default: 0x0) Generates an interrupt when data parity is detected. 1: Generates an interrupt. 0: Does not generate an interrupt. Read/Write ⎯ R/W 14 SSEIE Signaled System Error Interrupt Enable Received Master Abort Interrupt Enable Received Target Abort Interrupt Enable Signaled Target Abort Interrupt Enable Received Master Abort Received Target Abort Signaled Target Abort Reseved R/W 13 RMAIE R/W 12 RTAIE R/W 11 STAIE R/W 13 12 11 10:9 8 RMA RTA STA R/W R/W R/W ⎯ R/W MDPEIE Master Data Parity Detected Interrupt Enable Reserved 7:0 ⎯ Figure 10.4.16 PCI Status Interrupt Mask Register 10-43 Chapter 10 PCI Controller 10.4.19 P2G Configuration Register (P2GCFG) 31 Reserved 23 22 PME R/W1S 0x0 15 FTRD R/W 0x0 14 FTA R/W 0x0 13 12 11 10 9 8 7 Reserved : Type : Initial value 0xD090 21 20 19 Reserved : Type : Initial value 0 16 TPRBL R/W 0x3 Reserved MEM0PD MEM1PD MEM2PD TOBFR TIBFR R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 Bit 31:23 22 Mnemonic PME Field Name Reserved PME Description Read/Write ⎯ R/W1S PME (Default: 0x0) When the PCI Controller is in the Satellite mode, writing “1” to this bit signals a PME (Power Management Event) to the PCI Host device. The PME* signal is asserted if the PME_Status bit of the PMCSR Register is set and the PME_En bit of the PMCSR Register is set. This bit is cleared when the PCI Host device writes a “1” to the PME_Status bit of the PMCSR Register. This bit is invalid when the PCI Contoller is in the Host mode since the PME* signal is an input signal. Target Prefetch Read Burst Length (Default: 0x3) These bits set the number of DWORDS (32-bit words) to be read into the data FIFO when prefetching is valid during a target memory Read operation. Extra data transferred to the data FIFO is deleted when performing a memory Read operation of a PCI Bus transfer that is smaller than the set size. This setting is invalid when prefetching is disabled. 0x00: Access and transfer each 2 DWORDs of data to the target read FIFO. 0x01: Access and transfer each 4 DWORDs of data to the target read FIFO. 0x10: Access and transfer each 6 DWORDs of data to the target read FIFO. 0x11: Access and transfer each 8 DWORDs of data to the target read FIFO. R/W 21:20 TPRBL Target Prefetch Read Burst Length 19:16 15 FTRD Reserved Force Target Retry/Disconnect Force Target Abort Reserved MEM0PD Memory 0 Window Prefetch Disable Memory 0 Window Prefetch Disable (Default: 0x0) Prefetching during a G-Bus Burst Read transfer cycle to the Memory 0 Space is disabled when this bit is set to “1”. PCI Burst Read transactions are not supported when prefetching is disabled. Even if the setting of this bit is changed, prefetchable bits in the Base Address Register of the PCI Configuration Space will not reflect this change. We recommend using the default setting when the PCI Controller is in the Satellite mode. R/W Force Target Retry/Disconnect (Default: 0x0) The PCI Controller executes Retry Termination on a PCI Read access transaction if this bit is set to “1”. This is a diagnostic function. Force Target Abort (Default: 0x0) The PCI Controller executes a Target Abort on a PCI Read access transaction if this bit is set to “1”. This is a diagnostic function. R/W ⎯ 14 FTA R/W 13 12 ⎯ Figure 10.4.17 P2G Configuration Register (1/2) 10-44 Chapter 10 PCI Controller Bit 11 Mnemonic MEM1PD Field Name Memory 1 Window Prefetch Disable Description Memory 1 Window Prefetch Disable (Default: 0x0) Prefetching during a G-Bus Burst Read transfer cycle to the Memory 1 Space is disabled when this bit is set to “1”. PCI Burst Read transactions are not supported when prefetching is disabled. Even if the setting of this bit is changed, prefetchable bits in the Base Address Register of the PCI Configuration Space will not reflect this change. We recommend using the default setting when the PCI Controller is in the Satellite mode. Memory 2 Window Prefetch Disable (Default: 0x1) Prefetching during a G-Bus Burst Read transfer cycle to the Memory 2 Space is disabled when this bit is set to “1”. PCI Burst Read transactions are not supported when prefetching is disabled. Even if the setting of this bit is changed, prefetchable bits in the Base Address Register of the PCI Configuration Space will not reflect this change. We recommend using the default setting when the PCI Controller is in the Satellite mode. Read/Write R/W 10 MEM2PD Memory 2 Window Space Prefetch Disable R/W 9 TOBFR Target Out-Bound Target Out-Bound FIFO Reset (Default: 0x0) FIFO Reset The PCI Controller flushes the CORE internal Target Out-Bound FIFO when “1” is written to this bit. This bit always reads out “0” when it is read. This is a diagnostic function. Target In-Bound FIFO Reset R/W 8 TIBFR R/W Target In-Bound FIFO Reset (Default: 0x0) The PCI Controller flushes the CORE internal Target In-Bound FIFO when “1” is written to this bit. This bit always read out “0” when it is read. This is a diagnostic function. ⎯ 7:0 Reserved Figure 10.4.17 P2G Configuration Register (2/2) 10-45 Chapter 10 PCI Controller 10.4.20 P2G Status Register (P2GSTATUS) 31 Reserved 25 24 23 22 PMECLR 0xD094 21 20 19 18 17 16 Reserved PMSC PMEES M66EN IOBFE IIBFE TOBFE TIBFE R 0x0 R 0x1 R 0x1 R 0x1 R 0x1 R/W1C R/W1C R/W1C 0x0 0x0 0x0 15 Reserved : Type : Initial value 0 : Type : Initial value Bit 31:25 24 Mnemonic PMSC Field Name Reserved Description Read/Write ⎯ PM State Change Power Management State Change (Default: 0x0) R/W1C Detected “1” is set to this bit when the PowerState field of the Power Management Register (PMCSR) is rewritten. This bit is cleared to “0” when a “1” is written to it. This bit is only valid when the PCI Controller is in the Satellite mode. PME_En Set Detected R/W1C PME_En Set (Default: 0x0) This bit is set to “1” when the PME_En bit of the PMCSR Register is set to “1”. When this bit is set, it indicates that the PCI Master (Host) device enabled PME* signal output. 1: Indicates that the PME_En bit is set. 0: Indicates that the PME_En bit is not set. This bit is cleared to “0” when a “1” is written to it. This bit is only valid when the PCI Controller is in the Satellite mode. 23 PMEES 22 PMECLR R/W1C PME Status Clear PME_Status Clear (Default: 0x0) Detected This bit indicates that the PME_Status bit of the PMCSR Register was cleared. 1: Indicates that the PME_Status bit was cleared. 0: Indicates that the PME_Status bit was not cleared. This bit is cleared to “0” when a “1” is written to it. This bit is only valid when the PCI Controller is in the Satellite mode. 66 MHz Drive Status M66EN Status (Default: 0x0) This bit indicates the current status of the M66EN signal. This bit can only be read. Writes to this bit are invalid. 1: The M66EN signal is asserted. 0: The M66EN signal is deasserted. Initiator Out-Bound FIFO Empty (Default: 0x1) 1: Indicates that the Initiator Out-Bound FIFO is empty. 0: Indicates that the Initiator Out-Bound FIFO is not empty. This is a diagnostic function. Initiator In-Bound FIFO Empty (Default: 0x1) 1: Indicates that the Initiator In-Bound FIFO is empty. 0: Indicates that the Initiator In-Bound FIFO is not empty. This is a diagnostic function. R 21 M66EN 20 IOBFE Initiator OutBound FIFO Empty Initiator In-Bound FIFO Empty R 19 IIBFE R 18 TOBFE Target Out-Bound Target Out-Bound FIFO Empty (Default: 0x1) FIFO Empty 1: Indicates that the Target Out-Bound FIFO is empty. 0: Indicates that the Target Out-Bound FIFO is not empty. This is a diagnostic function. Target In-Bound FIFO Empty Target In-Bound FIFO Empty (Default: 0x1) 1: Indicates that the Target In-Bound FIFO is empty. 0: Indicates that the Target In-Bound FIFO is not empty. This is a diagnostic function. R 17 TIBFE R 16:0 Reserved ⎯ Figure 10.4.18 P2G Status Reigster 10-46 Chapter 10 PCI Controller 10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098 31 Reserved 25 24 23 22 21 20 Reserved : Type : Initial value 0 Reserved : Type : Initial value 16 PMSCIE PMEESIE PMECLRIE M66ENIE R/W 0x0 15 R/W 0x0 R/W 0x0 R/W 0x0 Bit 31:25 24 Mnemonic PMSCIE Field Name Reserved Power Management State Change Interrupt Enable PME_En Set Interrupt Enable Description Power Management State Change Interrupt Enable (Default: 0x0) Generates an interrupt when the PowerState field of the Power Management Register (PMCSR) is rewritten. 1: Generates an interrupt. 0: Does not generate an interrupt. PME_En Set Interrupt Enable (Default: 0x0) Generates an interrupt when the PME_En bit of the PMCSR Register is set. 1: Generates an interrupt. 0: Does not generate an interrupt. Read/Write ⎯ R/W 23 PMEESIE R/W 22 PMECLRIE PME Status Clear PME_Status Clear Interrupt Enable (Default: 0x0) R/W Interrupt Enable Generates an interrupt when the PME_Status bit of the PMCSR Register is cleared. 1: Generates an interrupt. 0: Does not generate an interrupt. 66 MHz Drive Interrupt Enable M66EN Detected Interrupt Enable (Default: 0x0) Generates an M66EN interrupt when the PCI Controller is in the Satellite mode. Note: This bit must be masked in order to clear an M66EN interrupt since the M66EN bit of the P2GSTATUS Register itself cannot be cleared. When the PCI Controller is in the Host mode, M66EN interrupts are invalid and will not be signaled even if this bit is set to “1”. 1: Generates an interrupt. 0: Does not generate an interrupt. R/W 21 M66ENIE 20:0 Reseved ⎯ Figure 10.4.19 P2G Interrupt Mask Register 10-47 Chapter 10 PCI Controller 10.4.22 P2G Current Command Register (P2GCCMD) 31 Reserved : Type : Initial value 15 Reserved 4 3 TCCMD R 0x0 : Type : Initial value 0 0xD09C 16 Bits 31:4 3:0 Mnemonic TCCMD Field Name Reserved Target Current Command Register Description Target Current Command (Default: 0x0) Indicates the PCI command within the target access process that is currently in progress. This is a diagnostic function. Read/Write ⎯ R Figure 10.4.20 P2G Current Command Register 10-48 Chapter 10 PCI Controller 10.4.23 PCI Bus Arbiter Request Port Register (PBAREQPORT) 0xD100 This register sets the correlation between each PCI Bus request source (PCI Controller and REQ[3:0]) and each Internal PCI Bus Arbiter Request port (Master A - D, W - Z) (see Figure 10.3.8). When changing the settings of this register, unused ports must be programmed to a reserved value. The eight non-reserved fields must be programmed to different values. After changing this register, the Broken Master Register (BM) value becomes invalid since the bit mapping changes. This register is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved 30 ReqAP R/W 111 28 27 Reserved 26 ReqBP R/W 110 24 23 Reserved 22 ReqCP R/W 101 20 19 Reserved 18 ReqDP R/W 100 16 : Type : Initial value 0 15 Reserved 14 ReqWP R/W 011 12 11 Reserved 10 ReqXP R/W 010 8 7 Reserved 6 ReqYP R/W 001 4 3 Reserved 2 ReqZP R/W 000 : Type : Initial value Bit 31 30:28 Mnemonic ReqAP Field Name Reserved Request A Port Description Request A Port (Default: 111) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request A Port (Master A). 111: Makes the PCI Controller Master A. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master A. 010: Makes REQ*[2] Master A. 001: Makes REQ*[1] Master A. 000: Makes REQ*[0] Master A. Request B Port (Default: 110) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request B Port (Master B). 111: Makes the PCI Controller Master B. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master B. 010: Makes REQ*[2] Master B. 001: Makes REQ*[1] Master B. 000: Makes REQ*[0] Master B. Request C Port (Default: 101) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request C Port (Master C). 111: Makes the PCI Controller Master C. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master C. 010: Makes REQ*[2] Master C. 001: Makes REQ*[1] Master C. 000: Makes REQ*[0] Master C. Read/Write ⎯ R/W 27 26:24 ReqBP Reserved Request B Port R/W ⎯ 23 22:20 ReqCP Reserved Request C Port R/W ⎯ Figure 10.4.21 PCI Bus Arbiter Request Port Register (1/2) 10-49 Chapter 10 PCI Controller Bit 19 18:16 Mnemonic ReqDP Field Name Reserved Request D Port Description Request D Port (Default: 100) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request D Port (Master D). 111: Makes the PCI Controller Master D. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master D. 010: Makes REQ*[2] Master D. 001: Makes REQ*[1] Master D. 000: Makes REQ*[0] Master D. Request W Port (Default: 011) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request W Port (Master W). 111: Makes the PCI Controller Master W. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master W. 010: Makes REQ*[2] Master W. 001: Makes REQ*[1] Master W. 000: Makes REQ*[0] Master W. Request X Port (Default: 010) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request X Port (Port X). 111: Makes the PCI Controller Master X. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master X. 010: Makes REQ*[2] Master X. 001: Makes REQ*[1] Master X. 000: Makes REQ*[0] Master X. Request Y Port (Default: 001) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request Y Port (Port Y). 111: Makes the PCI Controller Master Y. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master Y. 010: Makes REQ*[2] Master Y. 001: Makes REQ*[1] Master Y. 000: Makes REQ*[0] Master Y. Request Z Port (Default: 000) Sets the PCI Bus Master that connects to the Internal PCI Bus Arbiter Request Z Port (Port Z). 111: Makes the PCI Controller Master Z. 110: Reserved 101: Reserved 100: Reserved 011: Makes REQ*[3] Master Z. 010: Makes REQ*[2] Master Z. 001: Makes REQ*[1] Master Z. 000: Makes REQ*[0] Master Z. Read/Write ⎯ R/W 15 14:12 ReqWP Reserved Request W Port R/W ⎯ 11 10:8 ReqXP Reserved Request X Port R/W ⎯ 7 6:4 ReqYP Reserved Request Y Port R/W ⎯ 3 2:0 ReqZP Reserved Request Z Port R/W ⎯ Figure 10.4.21 PCI Bus Arbiter Request Port Register (2/2) 10-50 Chapter 10 PCI Controller 10.4.24 PCI Bus Arbiter Configuration Register (PBACFG) 0xD104 This register is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 4 3 2 1 0 16 FIXPA RPBA PBAEN BMCEN R/W 0 R/W 0 R/W 0 R/W : Type 0 : Initial value Bit 31:4 3 Mnemonic FIXPA Field Name Reserved Fixed Park Master Description Fixed Park Master (Default: 0) Selects the method for determining the Park Master. 0: The last Bus Master becomes the Park Master. 1: Internal PCI Bus Arbiter Request Port A is the Park Master. Read/Write ⎯ R/W 2 RPBA Reset PCI Bus Arbiter R/W Reset PCI Bus Arbiter (Default: 0) Resets the PCI Bus Arbiter. However, the PCI Bus Arbiter Register settings are saved. Please use the software to clear this bit. 1: The PCI Bus Arbiter is currently being reset. 0: The PCI Bus Arbiter is not currently being reset. PCI Bus Arbiter Enable (Default: 0) This is the Bus Arbiter Enable bit. After Reset, External PCI Bus requests to the PCI Arbiter cannot be accepted until this bit is set to “1”. The PCI Controller is the default Parking Master after Reset. 1: Enables the PCI Bus Arbiter. 0: Disables the PCI Bus Arbiter. Broken Master Check Enable (Default: 0) Controls Broken Master detection. 1: Enables the Broken PCI Bus Master check. 0: Disables the Broken PCI Bus Master check. R/W 1 PBAEN PCI Bus Arbiter Enable 0 BMCEN Broken Master Check Enable R/W Figure 10.4.22 PCI Bus Arbiter Configuration Register 10-51 Chapter 10 PCI Controller 10.4.25 PCI Bus Arbiter Status Register (PBASTATUS) 0xD108 This register is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 1 0 BM R/W1C : Type 0 : Initial value 16 Bit 31:1 0 Mnemonic BM Field Name Reserved Broken Master Detected Description Broken Master Detected (Default: 0) This bit indicates that a Broken Master was detected. This bit is set to “1” if even one of the bits in the PCI Bus Arbiter Broken Master Register (PBABM) is “1”. 1: Indicates that a Broken Master was detected. 0: Indicates that no Broken Master has been detected. Read/Write ⎯ R/W1C Figure 10.4.23 PCI Bus Arbiter Status Register 10-52 Chapter 10 PCI Controller 10.4.26 PCI Bus Arbiter Interrupt Mask Register (PBAMASK) This register is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 1 0 BMIE R/W : Type 0 : Initial value 16 0xD10C Bit 31:1 0 Mnemonic BMIE Field Name Reserved Description Read/Write ⎯ R/W Broken Master Broken Master Detected Interrupt Enable (Default: 0) Detected Interrupt Generates an interrupt when a Broken Master is detected. Enable 1: Generates an interrupt. 0: Does not generate an interrupt. Figure 10.4.24 PCI Bus Arbiter Interrupt Mask Register 10-53 Chapter 10 PCI Controller 10.4.27 PCI Bus Arbiter Broken Master Register (PBABM) 0xD110 This register indicates the acknowledged Broken Master. This register sets the bit that corresponds to the PCI Master device that was acknowledged as the Broken Master when the Broken Master Check Enable bit (BMCEN) in the PCI Bus Arbiter Configuration Register (PBACFG) is set. Regardless of the value of the Broken Master Check Enable bit, a PCI Master device is removed from the arbitration scheme when “1” is written to the corresponding BM bit. This register must be cleared to “0” since bit mapping changes, making this register value invalid when the PCI Bus Arbiter Request Port Register (PBAREQPORT) is changed. This register is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 8 7 6 5 4 3 2 1 0 BM_A BM_B BM_C BM_D BM_W BM_X BM_Y BM_Z R/W 0x00 : Type : Initial value 16 Bit 31:8 7 Mnemonic BM_A Field Name Reserved Broken Master Description Broken Master A (Default: 0) Indicates whether PCI Bus Master A is a Broken Master. 1: PCI Bus Master A was acknowledged as a Broken Master. 0: PCI Bus Master A was not acknowledged as a Broken Master. Broken Master B (Default: 0) Indicates whether PCI Bus Master B is a Broken Master. 1: PCI Bus Master B was acknowledged as a Broken Master. 0: PCI Bus Master B was not acknowledged as a Broken Master. Broken Master C (Default: 0) Indicates whether PCI Bus Master C is a Broken Master. 1: PCI Bus Master C was acknowledged as a Broken Master. 0: PCI Bus Master C was not acknowledged as a Broken Master. Broken Master D (Default: 0) Indicates whether PCI Bus Master D is a Broken Master. 1: PCI Bus Master D was acknowledged as a Broken Master. 0: PCI Bus Master D was not acknowledged as a Broken Master. Broken Master W (Default: 0) Indicates whether PCI Bus Master W is a Broken Master. 1: PCI Bus Master W was acknowledged as a Broken Master. 0: PCI Bus Master W was not acknowledged as a Broken Master. Broken Master X (Default: 0) Indicates whether PCI Bus Master X is a Broken Master. 1: PCI Bus Master X was acknowledged as a Broken Master. 0: PCI Bus Master X was not acknowledged as a Broken Master. Broken Master Y (Default: 0) Indicates whether PCI Bus Master Y is a Broken Master. 1: PCI Bus Master Y was acknowledged as a Broken Master. 0: PCI Bus Master Y was not acknowledged as a Broken Master. Broken Master Z (Default: 0) Indicates whether PCI Bus Master Z is a Broken Master. 1: PCI Bus Master Z was acknowledged as a Broken Master. 0: PCI Bus Master Z was not acknowledged as a Broken Master. Read/Write ⎯ R/W 6 BM_B Broken Master R/W 5 BM_C Broken Master R/W 4 BM_D Broken Master R/W 3 BM_W Broken Master R/W 2 BM_X Broken Master R/W 1 BM_Y Broken Master R/W 0 BM_Z Broken Master R/W Figure 10.4.25 PCI Bus Arbiter Broken Master Register 10-54 Chapter 10 PCI Controller 10.4.28 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 This register is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 8 7 CPCIBRS R/W 0x00 : Type : Initial value 0 16 Bits 31:8 7:0 Mnemonic CPCIBRS Field Name Reserved Current PCI Bus Request Status Description Current PCI Bus Request Status (Default: 0x00) This register indicates the status of the current PCI Bus Request Input Signal (PCI Controller and REQ*[3:0]). CPCIBRS[7] corresponds to the PCI Controller and CPCIBRS[3:0] correspond to REQ*[3:0]. Read/Write ⎯ R/W Figure 10.4.26 PCI Bus Arbiter Current Request Register 10-55 Chapter 10 PCI Controller 10.4.29 PCI Bus Arbiter Current Grant Register (PBACGNT) 0xD118 This is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 8 7 CPCIBGS R/W 0x80 : Type : Initial value 0 16 Bits 31:8 7:0 Mnemonic CPCIBGS Field Name Reserved Current PCI Grant Status Description Current PCI Bus Grant Status (Default: 0x80) This register indicates the current PCI Bus Grant output signal (PCI Controller and GNT*[3:0]). CPCIBGS[7] corresponds to the PCI Controller, and CPCIBGS[3:0] correspond to GNT*[3:0]. Read/Write ⎯ R/W Figure 10.4.27 PCI Bus Arbiter Current Grant Register 10-56 Chapter 10 PCI Controller 10.4.30 PCI Bus Arbiter Current State Register (PBACSTATE) 0xD11C This is a diagnostic register that is only valid when using the on-chip PCI Bus Arbiter. 31 Reserved : Type : Initial value 15 Reserved 8 7 FSM R/W 0 6 5 4 CPAS R 0x00 : Type : Initial value 0 16 Reserved Bit 31:8 7 Mnemonic FSM Field Name Reserved Observe PCI Arbiter State Machine Reserved Description Observe PCI Arbiter Finite State Machine (Default: 0) Specifies which State Machine to observe. 1: Observe the Level 1 State Machine. 0: Observe the Level 2 State Machine. Read/Write ⎯ R/W 6:5 ⎯ Figure 10.4.28 PCI Bus Arbiter Current State Register (1/2) 10-57 Chapter 10 PCI Controller Bit 4:0 Mnemonic CPAS Field Name Current PCI Bus Arbiter State Description Current PCI Bus Arbiter State (Default: 0x00) Displays the State Machine that was selected by the FSM bit. Please refer to Figures 12.5.3 and 12.11.1 for an explanation of Agent/Grant A - W and Level 2. When FSM =1: 0x00: Preparation state for transferring bus ownership to PCI Agent A. 0x01: State in which Grant A is provided to PCI Agent A when PCI Bus ownership is being held elsewhere. 0x02: State in which Grant A is provided to PCI Agent A when PCI Bus ownership is not being held elsewhere. 0x03: The agent that was provided Grant A exists in this state. If there is bus ownership, the PCI Bus Arbiter transfers bus ownership to another agent. 0x04: Preparation state for transferring bus ownership to PCI Agent B. 0x05: State in which Grant B is provided to PCI Agent B when PCI Bus ownership is being held elsewhere. 0x06: State in which Grant B is provided to PCI Agent B when PCI Bus ownership is not being held elsewhere. 0x07: The agent that was provided Grant B exists in this state. If there is bus ownership, the PCI Bus Arbiter transfers bus ownership to another agent. 0x08: Preparation state for transferring bus ownership to PCI Agent C. 0x09: State in which Grant C is provided to PCI Agent C when PCI Bus ownership is being held elsewhere. 0x0A: State in which Grant C is provided to PCI Agent C when PCI Bus ownership is not being held elsewhere. 0x0B: The agent that was provided Grant C exists in this state. If there is bus ownership, the PCI Bus Arbiter transfers bus ownership to another agent. 0x0C: Preparation state for transferring bus ownership to PCI Agent D. 0x0D: State in which Grant D is provided to PCI Agent D when PCI Bus ownership is being held elsewhere. 0x0E: State in which Grant D is provided to PCI Agent D when PCI Bus ownership is not being held elsewhere. 0x0F: The agent that was provided Grant D exists in this state. If there is bus ownership, the PCI Bus Arbiter transfers bus ownership to another agent. 0x10: Preparation state for transferring bus ownership to PCI Agent Level 2. 0x11: State in which Grant Level 2 is provided to PCI Agent Level 2 when PCI Bus ownership is being held elsewhere. 0x12: State in which Grant Level 2 is provided to PCI Agent Level 2 when PCI Bus ownership is not being held elsewhere. 0x13: The agent that was provided Grant Level 2 exists in this state. If there is bus ownership, the PCI Bus Arbiter transfers bus ownership to another agent. When FSM=0, the FSM=1 description is replaced as follows: A→W, B→X, C→Y, D→Z, Level 2→N/A. Read/Write R Figure 10.4.28 PCI Bus Arbiter Current State Register (2/2) 10-58 Chapter 10 PCI Controller 10.4.31 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 63 Reserved : Type : Initial value 47 Reserved 38 37 36 35 BA[35:32] R/W 0x0 16 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value : Type : Initial value 32 0xD120 48 BSWAP EXFER R/W R/W 0x0/0x1 0x1/0x0 31 Bit 63:38 37 Mnemonic BSWAP Field Name Reserved Byte Swap Description Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 0. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 0. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address (Default: 0x0_0000_00) Sets the G-Bus base bus address of Memory Space 0 for initiator access. Can set the base address in 256-byte units. Read/Write ⎯ R/W 36 EXFER Endian Transfer R/W 35:8 BA[35:8] Base Address R/W 7:0 Reserved R Figure 10.4.29 G2P Memory Space 0 G-Bus Base Address Register 10-59 Chapter 10 PCI Controller 10.4.32 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 63 Reserved : Type : Initial value 47 Reserved 38 37 36 35 BA[35:32] R/W 0x0 16 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value : Type : Initial value 32 0xD128 48 BSWAP EXFER R/W R/W 0x0/0x1 0x1/0x0 31 Bit 63:38 37 Mnemonic BSWAP Field Name Reserved Byte Swap Description Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 1. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 1. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address (Default: 0x0_0000_00) Sets the G-Bus base bus address of Memory Space 1 for initiator access. Can set the base address in 256-byte units. Read/Write ⎯ R/W 36 EXFER Endian Transfer R/W 35:8 BA[35:8] Memory Space Base Address 1 Reserved R/W 7:0 R Figure 10.4.30 G2P Memory Space 1 G-Bus Base Address Register 10-60 Chapter 10 PCI Controller 10.4.33 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 63 Reserved : Type : Initial value 47 Reserved 38 37 36 35 BA[35:32] R/W 0x0 16 BA[31:16] R/W 0x0000/0x1FC0 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value : Type : Initial value 32 0xD130 48 BSWAP EXFER R/W R/W 0x0/0x1 0x1/0x0 31 Bit 63:38 37 Mnemonic BSWAP Field Name Reserved Byte Swap Description Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 0. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 0. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address (Default: Normal Mode: 0x0_0000_00; PCI Boot Mode: 0x0_1FC0_00) Sets the G-Bus base bus address of Memory Space 2 for initiator access. Can set the base address in 256-byte units. Read/Write ⎯ R/W 36 EXFER Endian Transfer R/W 35:8 BA[35:8] Base Address R/W 7:0 Reserved R Figure 10.4.31 G2P Memory Space 2 G-Bus Base Address Register 10-61 Chapter 10 PCI Controller 10.4.34 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 63 Reserved : Type : Initial value 47 Reserved 38 37 36 35 BA[35:32] R/W 0x0 16 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value : Type : Initial value 32 0xD138 48 BSWAP EXFER R/W R/W 0x0/0x1 0x1/0x0 31 Bit 63:38 37 Mnemonic BSWAP Field Name Reserved Byte Swap Description Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of the I/O space. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to the I/O Memory Space through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of the I/O Space. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address (Default: 0x0_0000_00) Sets the G-Bus base bus address of the I/O Memory Space for initiator access. Can set the base address in 256-byte units. Read/Write ⎯ R/W 36 EXFER Endian Transfer R/W 35:8 BA[35:8] Base Address R/W 7:0 Reserved R Figure 10.4.32 G2P I/O Space G-Bus Address Register 10-62 Chapter 10 PCI Controller 10.4.35 G2P Memory Space 0 Address Mask Register (G2PM0MASK) 31 AM[35:20] R/W 0x0000 15 AM[19:8] R/W 0x000 4 3 Reserved R 0x0 : Type : Initial value 0 : Type : Initial value 0xD140 16 Bit 31:4 Mnemonic AM[35:8] Field Name Address Mask Description Read/Write R/W G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) Sets the bits to be subject to address comparison. See 10.3.4 for more information. When setting a memory space size of 256 MB (0x1000_0000) for example, the value becomes 0x00FF_FFF0. R 3:0 Reserved Figure 10.4.33 G2P Memory Space 0 Address Mask Register 10-63 Chapter 10 PCI Controller 10.4.36 G2P Memory Space 1 Address Mask Register (G2PM1MASK) 31 AM[35:20] R/W 0x0000 15 AM[19:8] R/W 0x000 4 3 Reserved R 0x0 : Type : Initial value 0 : Type : Initial value 0xD144 16 Bit 31:4 Mnemonic AM[35:8] Field Name Address Mask Description Read/Write R/W G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) Sets the bits to be subject to address comparison. See 10.3.4 for more information. When setting a memory space size of 256 MB (0x1000_0000) for example, the value becomes 0x00FF_FFF0. R 3:0 Reserved Figure 10.4.34 G2P Memory Space 1 Address Mask Register 10-64 Chapter 10 PCI Controller 10.4.37 G2P Memory Space 2 Address Mask Register (G2PM2MASK) 31 AM[35:20] R/W 0x0000/0x003F 15 AM[19:8] R/W 0x000/0xFFF 4 3 Reserved R 0x0 : Type : Initial value 0 : Type : Initial value 0xD148 16 Bit 31:4 Mnemonic AM[35:8] Field Name Address Mask Description Read/Write G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) R/W (Default: Normal Mode: 0x0_0000_00; PCI Boot Mode: 0x0_03FF_FF) Sets the bits to be subject to address comparison. See 10.3.4 for more information. When setting a memory space size of 256 MB (0x1000_0000) for example, the value becomes 0x00FF_FFF0. Note: To boot PCI, set 0x0_003F_FF (4 Mbyte space) to AM[35:8] in the boot code. R 3:0 Reserved Figure 10.4.35 G2P Memory Space 2 Address Mask Register 10-65 Chapter 10 PCI Controller 10.4.38 G2P I/O Space Address Mask Register (G2PIOMASK) 31 AM[35:20] R/W 0x0000 15 AM[19:8] R/W 0x000 4 3 Reserved R 0x0 : Type : Initial value 0 : Type : Initial value 0xD14C 16 Bits 31:4 Mnemonic AM[35:8] Field Name Address Mask Description Read/Write R/W G-Bus to PCI-Bus Address Mask (Default: 0x0_0000_00) Sets the bits to be subject to address comparison. See 10.3.4 for more information. When setting a memory space size of 256 MB (0x0000_0100) for example, the value becomes 0x0000_0000. R 3:0 Reserved Figure 10.4.36 G2P I/O Space Address Mask Register 10-66 Chapter 10 PCI Controller 10.4.39 G2P Memory Space 0 PCI Base Address Register (G2PM0PBASE) 63 Reserved : Type : Initial value 47 Reserved 40 39 BA[39:32] R/W 0x00 31 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 0xD150 48 Bits 63:40 39:8 Mnemonic BA[39:8] Field Name Reserved Base Address Register Base Address (Default: 0x00_0000_00) Sets the PCI Base address of Memory Space 0 for initiator access. Can set the base address in 256-Byte units. Read/Write ⎯ R/W 7:0 Reserved R Figure 10.4.37 G2P Memory Space 0 G-Bus Base Address Register 10-67 Chapter 10 PCI Controller 10.4.40 G2P Memory Space 1 PCI Base Address Register (G2PM1PBASE) 63 Reserved : Type : Initial value 47 Reserved 40 39 BA[39:32] R/W 0x00 31 BA[31:16] R/W 0x0000/0xBFC0 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 0xD158 48 Bit 63:40 39:8 Mnemonic BA[39:8] Field Name Reserved Base Address Description Base Address (Default: 0x00_0000_00) Sets the PCI Base address of Memory Space 1 for initiator access. Can set the base address in 256-Byte units. Read/Write ⎯ R/W 7:0 Reserved R Figure 10.4.38 G2P Memory Space 1 G-Bus Base Address Register 10-68 Chapter 10 PCI Controller 10.4.41 G2P Memory Space 2 PCI Base Address Register (G2PM2PBASE) 63 Reserved : Type : Initial value 47 Reserved 40 39 BA[39:32] R/W 0x00 31 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 0xD160 48 Bits 63:40 39:8 Mnemonic BA[39:8] Field Name Reserved Base Address Description Base Address (Default: 0x00_0000_00) Sets the PCI Base address of Memory Space 2 for initiator access. Can set the base address in 256-Byte units. Read/Write ⎯ R/W 7:0 Reserved R Figure 10.4.39 G2P Memory Space 2 G-Bus Base Address Register 10-69 Chapter 10 PCI Controller 10.4.42 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 63 Reserved : Type : Initial value 47 Reserved 40 39 BA[39:32] R/W 0x00 31 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 Reserved R 0x00 : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 0xD168 48 Bits 63:40 39:8 Mnemonic BA[39:8] Field Name Reserved Base Address Description Base Address (Default: 0x00_0000_00) Sets the PCI Base address of the I/O Space for initiator access. Can set the base address in 256-Byte units. Read/Write ⎯ R/W 7:0 Reserved R Figure 10.4.40 G2P I/O Space G-Bus Address Register 10-70 Chapter 10 PCI Controller 10.4.43 PCI Controller Configuration Register (PCICCFG) 31 Reserved 28 27 GBWC R/W 0xfff 15 Reserved 12 11 10 9 8 7 6 5 4 3 2 1 0 : Type : Initial value 0xD170 16 HRST SRST IRBER R/W 0x0 R/W 0x0 R/W 0x1 G2PM0EN G2PM1EN G2PM2EN G2PIOEN TCAR ICAEN LCFG R/W 0x0 R/W 0x0 R/W 0x0 Reserved : Type : Initial value R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 Bit 31:28 27:16 Mnemonic GBWC Field Name Reserved G-Bus Wait Counter Setting Description Read/Write ⎯ R/W G Bus Wait Counter (Default: 0xFFF) Sets the Retry response counter at the G-Bus during a PCI initiator Read transaction. When the initiator Read access cycle exceeds the setting of this counter, a Retry response is sent to the G-Bus and the G-Bus is released. PCI Read operation continues. This counter uses the G-Bus clock (GBUSCLK) when operating. When 0x000 is set, a Retry response is not sent to the G-Bus by a long response cycle count. When the G-Bus timeout count is used with the value other than the initial value 4096 GBUSCLK, G-BUS timeout may occur before a Retry response is sent. When G-Bus timeout of the configuration register (CCFG.GTOT) is used with the value other than the initial value (11), set the following maximum values to the register. GTOT value Maximum value of the register 10 (2048 GBUSCLK) : 0x7f0 01 (1024 GBUSCLK) : 0x3f0 00 ( 512 GBUSCLK) : 0x1f0 15:12 11 HRST Reserved Hardware Reset R/W Hard Reset (Default: 0x0) Performs PCI Controller hardware reset control. EEPROM reloading is also performed. This bit is automatically cleared when Reset ends. This is a diagnostic function. The PCI Controller cannot be accessed for 32 G-Bus clock cycles after this bit is set. 1: Perform a hardware reset on the PCI Controller. 0: Do not perform a hardware reset on the PCI Controller. ⎯ Figure 10.4.41 PCI Controller Configuration Register (1/3) 10-71 Chapter 10 PCI Controller Bit 10 Mnemonic SRST Field Name Software Reset Description Read/Write R/W Soft Reset (Default: 0x0) Performs PCI Controller software reset control. Data is also reloaded to the Configuration Space Register from EEPROM or from the Configuration Data Register. Please set this bit after the EEPROM Load End bit (PCICSTATUS.E2PDONE) is set. Also, please use the software to clear this bit at least four PCI Bus Clock cycles after Reset. Other registers of the PCI Controller cannot be accessed while this bit is set. This bit differs from the Hardware Reset bit (HRST). The following register values are not initialized. • G2P Status Register (G2PSTATUS) • PCI Bus Arbiter Status Register (PBASTATUS) • PCI Controller Status Register (PCICSTATUS) • Software Reset bit (PCICCFG.SRST) • Load Configuration Register bit (PCICCFG.LCFG) 1: The PCI Controller is reset by the software. 0: The PCI Controller is not reset by the software. 9 IRBER Bus Error Response Setting During Initiator Read R/W Initiator Read Bus Error Response (Default: 0x1) Bus error responses on the G-Bus are controlled when the following phenomena indicated by the PCI Status, Command Register (PICSTATUS) and the G2P Status Register (G2PSTATUS) occur during initiator Read access. Detected Parity Error (PCISTATUS.DPE) Received Master Abort (PCISTATUS.RMA) Received Target Abort (PCISTATUS.RTA) Initiator Detected TRDY Time Out Error (G2PSTATUS.IDTTOE) Initiator Detected Retry Time Out Error (G2PSTATUS.IDRTOE) 1: Responds with a Bus error on the G-Bus. 0: Does not respond with a Bus error on the G-Bus. (Normally terminates the Read transaction on the G-Bus. Read data is invalid.) 8 G2PM0EN Initiator Memory Space 0 Enable Initiator Memory Space 0 Enable (Default: 0x0) Controls PCI initiator access to Memory Space 0. 1: Memory Space 0 is valid. 0: Memory Space 0 is invalid. Initiator Memory Space 1 Enable (Default: 0x0) Controls PCI initiator access to Memory Space 1. 1: Memory Space 1 is valid. 0: Memory Space 1 is invalid. Initiator Memory Space 2 Enable (Default: Normal Mode: 0x0; PCI Boot Mode: 0x1) Controls PCI initiator access to Memory Space 2. 1: Memory Space 2 is valid. 0: Memory Space 2 is invalid. R/W 7 G2PM1EN Initiator Memory Space 1 Enable R/W 6 G2PM2EN Initiator Memory Space 2 Enable R/W 5 G2PIOEN Initiator I/O Space Initiator I/O Space Enable (Default: 0x0) Enable Controls PCI initiator access to the I/O Space.. 1: I/O Space is valid. 0: I/O Space is invalid. R/W Figure 10.4.41 PCI Controller Configuration Register (2/3) 10-72 Chapter 10 PCI Controller Bit 4 Mnemonic TCAR Field Name Target Configuration Access Ready Description Read/Write R/W Target Configuration Access Ready (Default: 0x0/0x1) Specifies whether to accept PCI access as a target. PCI controller receives a target access, when this bit is 1 and PCISTATUS.E2PDONE bit is 1. Configuration access from the PCI Bus can be accepted during PCI Boot up after initialization from EEPROM or after each initialization ends. Please use the software to set this bit after initialization ends. Retry response to PCI configuration access is performed until this bit is set. This bit becomes “1” only when in the PCI Boot Mode and the Satellite Mode. Operation when this bit is set to “1” then reset to “0” is not defined. 1: Responds to PCI target access. 0: Performs a Retry response to PCI target access. Initiator Configuration Access Enable (Default: 0x1) Controls initiator PCI configuration access using the G2P Configuration Address Register (G2PCFGADRS) and the G2P Configuration Data Register (G2PCFGDATA). This is a diagnostic function. 1: Initiator configuration access is possible. 0: Initiator configuration access is not possible. R/W 3 ICAEN Initiator Configuration Access Enable 2 LCFG Load Configuration Data Register R/W Load PCI Configuration Data Register (Default: 0x0) When a software reset is performed on this bit using the Software Reset bit (PCICFG.SRST) when this bit is already set, data is loaded to the Configuration Space Register from the Configuration Data 0/1/2/3 Register. 1: Load from the Configuration Data 0/1/2/3 Register. 0: Load from EEPROM. ⎯ 1:0 Reserved Figure 10.4.41 PCI Controller Configuration Register (3/3) 10-73 Chapter 10 PCI Controller 10.4.44 PCI Controller Status Register (PCICSTATUS) 31 Reserved : Type : Initial value 15 Reserved 11 10 PME 9 TLB 8 NIB 7 ZIB 6 Reserved 0xD174 16 5 4 3 GBE 2 Reserved 1 IWB R 0x0 0 E2PDONE PERR SERR R/W1C R/W1C R/W1C R/W1C 0x0 0x0 0x0 0x0 R/W1C R/W1C R/W1C 0x0 0x0 0x0 R ⎯ : Type : Initial value Bit 31:11 10 Mnemonic PME Field Name Reserved PME Detect Description PME Detect (Default: 0x0) When the PCI Controller is in the Host mode, this bit indicates that assertion of the PME* signal was detected. 1: Indicates that assertion of the PME* signal was detected. 0: Indicates that assertion of the PME* signal was not detected. Too Long Burst Detect (Default: 0x0) Indicates that a Burst transfer by the on-chip DMA Controller exceeding 8 DWORDs was detected. 1: Indicates that a Burst transfer exceeding 8 DWORDs was detected. 0: Indicates that no Burst transfer exceeding 8 DWORDs was detected. Negative Increment Burst Detect (Default: 0x0) Indicates that Burst transfer by the on-chip DMA Controller in the negative direction was detected. 1: Indicates that a Burst transfer in the negative direction was detected. 0: Indicates that no Burst transfer in the negative direction was detected. Zero Increment Burst Detect (Default: 0x0) Indicates that Burst transfer by the on-chip DMA Controller without an address increment was detected. 1: Indicates that a Burst transfer without an address increment was detected. 0: Indicates that no Burst transfer without an address increment was detected. PERR* Occurred (Default: 0x0) Indicates that the Parity Error signal (PERR*) was asserted. This bit is a monitor status bit that records assertion of the PERR* signal even if the TX4938 is not accessing PCI. 1: Indicates that the PERR* signal was asserted. 0: Indicates that the PERR* signal was not asserted. SERR* Occurred (Default: 0x0) Indicates that the System Error signal (SERR*) was asserted. This bit is a monitor status bit that records assertion of the SERR* signal even if the TX4938 is not accessing PCI. 1: Indicates that the SERR* signal was asserted. 0: Indicates that the SERR* signal was not asserted. Read/Write ⎯ R/W1C 9 TLB Long Burst Transfer Detect R/W1C 8 NIB Negative Increment Burst Detect R/W1C 7 ZIB Zero Increment Burst Detect R/W1C 6 5 PERR Reserved PERR* Detected ⎯ R/W1C 4 SERR SERR* Detected R/W1C 3 GBE G-Bus Error Detect R/W1C G-Bus Error Detect (Default: 0x0) Indicates that a G-Bus Error occurred in the G-Bus Master cycle of the PCI Controller. This error is indicated when a timeout occurs on the G-Bus. This bit is only set by Master cycle Bus Errors. 1: Indicates that a G-Bus Error was detected. 0: Indicates that no G-Bus Error was detected. Figure 10.4.42 PCI Controller Status Register (1/2) 10-74 Chapter 10 PCI Controller Bit 2 1 Mnemonic IWB Field Name Reserved Initiator Write Busy Description Initiator Write Busy (Busy: 0x0) Indicates that a Write cycle was in progress when a Write cycle to the PCI Bus was executed. While a Write cycle is in progress, no error status to that Write cycle is reflected. Therefore, this bit is used to confirm the status when it changes from “1” to “0” after the Write cycle ends. 1: Indicates that a Write cycle is in progress. 0: Indicates that no Write cycle is in progress. Read/Write ⎯ R 0 E2PDONE EEPROM Load Done R EEPROM Load Done (Default--) When using EEPROM, this bit indicates that data loading from EEPROM is complete. This bit is set to “1” when the internal process ends even if no EEPROM is connected. 1: Indicates that data loading from EEPROM is complete. 0: Indicates that data loading from EEPROM is not complete. Figure 10.4.42 PCI Controller Status Register (2/2) 10-75 Chapter 10 PCI Controller 10.4.45 PCI Controller Interrupt Mask Register (PCICMASK) 31 Reserved : Type : Initial value 15 Reserved 11 10 9 8 7 6 5 4 3 GBEIE R/W 0x0 2 1 Reserved : Type : Initial value 0 0xD178 16 PMEIE TLBIE NIBIE ZIBIE R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 Reserved PERRIE SERRIE R/W 0x0 R/W 0x0 Bit 31:11 10 Mnemonic PMEIE Field Name Reserved PME Detect Interrupt Enable Description PME* Signal Interrupt Enable (Default: 0x0) When in the Host mode, this bit generates an interrupt when input of the PME* signal is detected. 1: Generates an interrupt. 0: Does not generate an interrupt. Too Long Burst Interrupt Enable (Default: 0x0) This bit generates an interrupt when a Burst transfer by the on-chip DMA Controller exceeding 8 DWORDs was detected. 1: Generates an interrupt. 0: Does not generate an interrupt Negative Increment Burst Interrupt Enable (Default: 0x0) This bit generates an interrupt when a negative direction Burst transfer by the on-chip DMA Controller is detected. 1: Generates an interrupt. 0: Does not generate an interrupt. Zero Increment Burst Interrupt Enable (Default: 0x0) This bit generates an interrupt when a Burst transfer by the on-chip DMA Controller without an address increment is detected. 1: Generates an interrupt. 0: Does not generate an interrupt. PERR* Interrupt Enable (Default: 0x0) This bit generates an interrupt when the Parity Error signal (PERR*) is asserted. 1: Generates an interrupt. 0: Does not generate an interrupt. SERR* Interrupt Enable (Default: 0x0) This bit generates an interrupt when the System Error signal (SERR*) is asserted. 1: Generates an interrupt. 0: Does not generate an interrupt. G-Bus Bus Error Interrupt Enable (Default: 0x0) This bit generates an interrupt when a Bus Error is asserted while the PCI Controller is the G-Bus Master. 1: Generates an interrupt. 0: Does not generate an interrupt. Read/Write ⎯ R/W 9 TLBIE Long Burst Transfer Detect Interrupt R/W 8 NIBIE Negative Increment Burst Transfer Detect Interrupt Enable Zero Increment Burst Transfer Detect Interrupt Enable Reserved R/W 7 ZIBIE R/W 6 5 PERRIE ⎯ R/W PERR* Detect Interrupt Enable 4 SERRIE SERR* Detect Interrupt Enable R/W 3 GBEIE G-Bus Bus Error Detect Interrupt Enable R/W 2:0 Reserved ⎯ Figure 10.4.43 PCI Controller Interrupt Mask Register 10-76 Chapter 10 PCI Controller 10.4.46 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 63 Reserved : Type : Initial value 47 Reserved 39 38 P2GM0EN 0xD180 48 37 36 35 BA[35:32] R/W 0x0 32 BSWAP EXFER R/W 0x0 31 BA[31:29] R/W 0x00 15 Reserved 29 28 R/W R/W 0x0/0x1 0x1/0x0 : Type : Initial value 16 Reserved : Type : Initial value 0 : Type : Initial value Bit 63:39 38 Mnemonic P2GM0EN Field Name Reserved Memory Space 0 Enable Description Target Memory Space 0 Enable (Default: 0x0) Controls whether Memory Space 0 for target access is valid or invalid. When this bit is set to invalid, Writes to the Memory Space 0 Lower Base Address Register or the Memory Space 0 Upper Base Address Register of the PCI Configuration Register become invalid. Also, “0” is returned to Reads as a response. 1: Validates Memory Space 0 for target access. 0: Invalidates Memory Space 0 for target access. Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 0 for target access.. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 0 for target access. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address 0 (Default: 0x000) Sets the G-Bus base bus address of Memory Space 0 for target access. Can set the base address in 512-MB units. Read/Write ⎯ R/W 37 BSWAP Byte Swap R/W 36 EXFER Endian Transfer R/W 35:29 BA[35:29] Base Address R/W 28:0 Reserved ⎯ Figure 10.4.44 P2G Memory Space 0 G-Bus Base Address Register 10-77 Chapter 10 PCI Controller 10.4.47 P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 63 Reserved : Type : Initial value 47 Reserved 39 38 P2GM1EN 0xD188 48 37 36 35 BA[35:32] R/W 0x0 32 BSWAP EXFER R/W 0x0 31 BA[31:24] R/W 0x00 15 Reserved 24 23 R/W R/W 0x0/0x1 0x1/0x0 : Type : Initial value 16 Reserved : Type : Initial value 0 : Type : Initial value Bit 63:39 38 Mnemonic P2GM1EN Field Name Reserved Memory Space 1 Enable Description Target Memory Space 1 Enable (Default: 0x0) Controls whether Memory Space 1 for target access is valid or invalid. When this bit is set to invalid, Writes to the Memory Space 1 Lower Base Address Register or the Memory Space 1 Upper Base Address Register of the PCI Configuration Register become invalid. Also, “1” is returned to Reads as a response. 1: Validates Memory Space 1 for target access. 0: Invalidates Memory Space 1 for target access. Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 1 for target access. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 0 through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 1 for target access. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address 0 (Default: 0x0_0000_00) Sets the G-Bus base bus address of Memory Space 1 for target access. Can set the base address in 16-MB units. Read/Write ⎯ R/W 37 BSWAP Byte Swap R/W 36 EXFER Endian Transfer R/W 35:24 BA[35:24] Memory Space Base Address 1 Reserved R/W 23:0 ⎯ Figure 10.4.45 P2G Memory Space 1 G-Bus Base Address Register 10-78 Chapter 10 PCI Controller 10.4.48 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 63 Reserved : Type : Initial value 47 Reserved 39 38 P2GM2EN 0xD190 48 37 36 35 BA[35:32] R/W 0x0 19 Reserved 32 BSWAP EXFER R/W 0x0 31 BA[31:20] R/W 0x000 15 Reserved R/W R/W 0x0/0x1 0x1/0x0 : Type : Initial value 16 20 : Type : Initial value 0 : Type : Initial value Bit 63:39 38 Mnemonic P2GM2EN Field Name Reserved Memory Space 2 Enable Description Target Memory Space 2 Enable (Default: 0x0) Controls whether Memory Space 2 for target access is valid or invalid. When this bit is set to invalid, Writes to the Memory Space 2 Lower Base Address Register or the Memory Space 2 Upper Base Address Register of the PCI Configuration Register become invalid. Also, “0” is returned to Reads as a response. 1: Validates Memory Space 2 for target access. 0: Invalidates Memory Space 2 for target access. Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of Memory Space 2 for target access. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to Memory Space 2 through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of Memory Space 2 for target access. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address 2 (Default: 0x000) Sets the G-Bus base bus address of Memory Space 2 for target access. Can set the base address in 1-MB units. Read/Write ⎯ R/W 37 BSWAP Byte Swap R/W 36 EXFER Endian Transfer R/W 35:20 BA[35:20] Memory Space Base Address 2 Reserved R/W 19:0 ⎯ Figure 10.4.46 P2G Memory Space 2 G-Bus Base Address Register 10-79 Chapter 10 PCI Controller 10.4.49 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 63 Reserved : Type : Initial value 47 Reserved 39 38 P2GIOEN 0xD198 48 37 36 35 BA[35:32] R/W 0x0 32 BSWAP EXFER R/W 0x0 31 BA[31:16] R/W 0x0000 15 BA[15:8] R/W 0x00 8 7 R/W R/W 0x0/0x1 0x1/0x0 : Type : Initial value 16 : Type : Initial value 0 Reserved : Type : Initial value Bit 63:39 38 Mnemonic P2GIOEN Field Name Reserved Description Read/Write ⎯ R/W I/O Space Enable Target I/O Space Enable (Default: 0x0) Controls whether the I/O Space for target access is valid or invalid. When this bit is set to invalid, Writes to the I/O Space Base Address Register of the PCI Configuration Register become invalid. Also, “0” is returned to Reads as a response. 1: Validates I/O Space for target access. 0: Invalidates I/O Space for target access. Byte Swap Byte Swap Disable (Default: Little Endian Mode: 0x1; Big Endian Mode: 0x0) Sets the byte swapping of the I/O Space for target access. 1: Do not perform byte swapping. 0: Perform byte swapping. Please use the default state in most situations. If this bit is changed to “1” when in the Big Endian Mode, the byte order of transfer to the I/O Space through DWORD (32-bit) access will not change. Endian Transfer (Default: Little Endian Mode: 0x0; Big Endian Mode: 0x1) Sets the Endian Transfer of the I/O Space for target access. 1: Performs Endian Transfer. 0: Does not perform Endian Transfer. Please use the default state. Base Address 2 (Default: 0x000) Sets the G-Bus base bus address of the I/O Space for target access. Can set the base address in 256-byte units. 37 BSWAP R/W 36 EXFER Endian Transfer R/W 35:8 BA[35:8] Memory Space Base Address 2 Reserved R/W 7:1 ⎯ Figure 10.4.47 P2G I/O Space G-Bus Base Address Register 10-80 Chapter 10 PCI Controller 10.4.50 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0 The operation of any access to this register is undefined when the PCI Controller is in the Satellite mode. 31 Reserved 24 23 BUSNUM R/W 0x00 15 DEVNUM R/W 0x00 11 10 FNNUM R/W 000 8 7 REGNUM R/W 0x00 2 1 TYPE R/W 00 : Type : Initial value 0 : Type : Initial value 16 Bit 31:24 23:16 15:11 Mnemonic BUSNUM DEVNUM Field Name Reserved Bus Number Device Number Description Bus Number (Default: 0x00) Indicates the target PCI Bus Number (one of 256). Device Number (Default: 0x00) This field is used to identify the target physical device number. (This is one number out of 32 devices. 21 of these 32 devices are used.) When in the address phase of Type 0 configuration access, AD[31:11] of the upper 21 address lines are used as the IDSEL signal. 0x00: Use AD [11] as IDSEL. 0x01: Use AD [12] as IDSEL. 0x02: Use AD [13] as IDSEL. : : 0x13: Use AD [30] as IDSEL. 0x14: Use AD [31] as IDSEL. 0x15 - 0x1F: Reserved Function Number (Default: 000) This field is used to identify the target logic function number (one out of 8). Register Number (Default: 0x00) This field is used to identify the DWORD (one out of 64) inside the Configuration Space of the target function Type (Default; 00) This field is used to identify the address type in the address phase of the target function configuration cycle. 0x0: Type 0 configuration (Use the AD[31:11] signal as the IDSEL signal.) 0x1: Type 1 configuration (Output all bits unchanged as the address to the AD[ ] signal.) Read/Write ⎯ R/W R/W 10:8 7:2 FNNUM REGNUM Function Number Register Number R/W R/W 1:0 TYPE Type R/W Figure 10.4.48 G2P Configuration Address Register 10-81 Chapter 10 PCI Controller 10.4.51 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4 This is the only register that supports Byte access and 16-bit Word access. The upper address bit of the PCI Configuration Space is specified by the G2P Configuration Address Register (G2PCFGADRS). The lower two bits of the address are specified by the lower two bits of the offset address in this register as shown in Figure 10.4.2. The operation of any access to this register is undefined when the PCI Controller is in the Satellite mode. Table 10.4.2 PCI Configuration Space Access Address Access Size 32-bit 16-bit Configuration Space Address [1:0] 00 00 10 00 01 10 11 Offset Address Little Endian Mode 0xD1A4 0xD1A4 0xD1A6 0xD1A4 0xD1A5 0xD1A6 0xD1A7 Big Endian Mode 0xD1A4 0xD1A6 0xD1A4 0xD1A7 0xD1A6 0xD1A5 0xD1A4 8-bit 31 ICD R/W ⎯ 15 ICD R/W ⎯ 16 : Type : Initial value 0 : Type : Initial value Bits 31:0 Mnemonic ICD Field Name Initiator Configuration Data Description Initiator Configuration Data Register (Default--) This is a data port that is used when performing initiator PCI configuration access. PCI configuration Read or Write transactions are issued when this register is read to or written from. Read/Write R/W Figure 10.4.49 G2P Configuration Data Register 10-82 Chapter 10 PCI Controller 10.4.52 G2P Interrupt Acknowledge Data Register (G2PINTACK) 31 IIACKD R ⎯ 15 IIACKD R ⎯ : Type : Initial value 0 : Type : Initial value 0xD1C8 16 Bits 31:0 Mnemonic IIACKD Field Name Initiator Interrupt Acknowledge Address Port Description Read/Write R Initiator Interrupt Acknowledge Address Port (Default--) An Interrupt Acknowledge cycle is generated on the PCI Bus when this register is read. The data that is returned by this Read transaction becomes the Interrupt Acknowledge data. Figure 10.4.50 G2P Interrupt Acknowledge Data Register 10-83 Chapter 10 PCI Controller 10.4.53 G2P Special Cycle Data Register (G2PSPC) 31 ISCD W ⎯ 15 ISCD W ⎯ : Type : Initial value 0 : Type : Initial value 0xD1CC 16 Bits 31:0 Mnemonic ISCD Field Name Initiator Special Cycle Data Port Description Initiator Special Cycle Data Port (Default--) When this register is written to, Special Cycles are generated on the PCI Bus depending on the data that is written. Read/Write W Figure 10.4.51 G2P Special Cycle Data Register 10-84 Chapter 10 PCI Controller 10.4.54 Configuration Data 0 Register (PCICDATA0) 31 DID R/W 0x0000 15 VID R/W 0x0000 : Type : Initial value 0 : Type : Initial value 0xD1D0 16 Bits 31:16 Mnemonic DID Field Name Device ID Description Device ID (Default: 0x0000) This is the data loaded in the Device ID Register of the PCI Configuration Space. Vendor ID (Default: 0x0000) This is the data loaded in the Vendor ID Register of the PCI Configuration Space. Read/Write R/W 15:0 VID Vendor ID R/W Figure 10.4.52 ID Register 10-85 Chapter 10 PCI Controller 10.4.55 Configuration Data 1 Register (PCICDATA1) 31 CC R/W 0x0000 15 CC R/W 0x00 8 7 RID R/W 0x00 : Type : Initial value 0 : Type : Initial value 0xD1D4 16 Bis 31:8 Mnemonic CC Field Name Class Code Description Read/Write R/W Class Code (Default: 0x000000) This is the data loaded in the Class Code Register of the PCI Configuration Space. R/W Revision ID (Default: 0x00) This is the data loaded in the Revision ID Register of the PCI Configuration Space. 7:0 RID Revision ID Figure 10.4.53 Class Code/Revision ID Register 10-86 Chapter 10 PCI Controller 10.4.56 Configuration Data 2 Register (PCICDATA2) 31 SSID R/W 0x0000 15 SSVID R/W 0x0000 : Type : Initial value 0 : Type : Initial value 0xD1D8 16 Bits 31:16 Mnemonic SSID Field Name Sub System ID Description Subsystem ID (Default: 0x0000) This is the data loaded in the Sub System ID Register of the PCI Configuration space. Subsystem Vendor ID (Default: 0x0000) This is the data loaded in the Sub System Vendor ID Register of the PCI Configuration space. Read/Write R/W 15:0 SSVID Sub System Vendor ID R/W Figure 10.4.54 Sub System ID Register 10-87 Chapter 10 PCI Controller 10.4.57 Configuration Data 3 Register (PCICDATA3) 31 ML R/W 0x00 15 IP R/W 0x00 8 7 HT R/W 0x00 : Type : Initial value 24 23 MG R/W 0x00 0 : Type : Initial value 0xD1DC 16 Bits 31:24 Mnemonic ML Field Name Maximum Latency Minimum Grant Description Max_Lat (Maximum Latency) (Default: 0x00) This is the data loaded in the Max_Lat Register of the PCI Configuration Space. Min_Gnt (Minimum Grant) (Default: 0x00) This is the data loaded in the Min_Gnt Register of the PCI Configuration Space. Interrupt Pin (Default: 0x00) This is the data loaded in the Interrupt Pin Register of the PCI Configuration Space. Header Type (Default: 0x00) This is the data loaded in the Header Type Register of the PCI Configuration Space. Read/Write R/W 23:16 MG R/W 15:8 IP Interrupt Pin R/W 7:0 HT Header Type R/W Figure 10.4.55 PCI Configuration 2 Register 10-88 Chapter 10 PCI Controller 10.4.58 PDMAC Chain Address Register (PDMCA) 63 Reserved : Type : Initial value 47 Reserved 36 35 PDMCA[35:32] R/W undefined 31 PDMCA[31:16] R/W Undefined 15 PDMCA[15:3] R/W Undefined 3 2 Reserved : Type : Initial value 0 : Type : Initial value 16 : Type : Initial value 32 0xD200 48 Bits 63:36 35:3 Mnemonic PDMCA Field Name Reserved Chain Address Description PDMAC Chain Address (Default is undefined) The address of the next PDMAC Data Command Descriptor to be read is specified by a G-Bus physical address on a 64-bit address boundary. This register value is held without being affected by a Reset. 0 value judgement is performed when the lower 32 bits of this register are rewritten. DMA transfer is automatically initiated if the result is not “0”. Read/Write ⎯ R/W 2:0 Reserved ⎯ Figure 10.4.56 PDMAC Chain Address Register 10-89 Chapter 10 PCI Controller 10.4.59 PDMAC G-Bus Address Register (PDMGA) 63 Reserved : Type : Initial value 47 Reserved 36 35 PDMGA[35:32] R/W Undefined 31 PDMGA[31:16] R/W Undefined 15 PDMGA[15:2] R/W Undefined 2 1 0 : Type : Initial value 16 : Type : Initial value 32 0xD208 48 Reserved : Type : Initial value Bits 63:36 35:2 Mnemonic PDMGA Field Name Reserved G-Bus Address Description Read/Write ⎯ R/W PDMAC G-Bus Address (Default is undefined) The G-Bus DMA transfer address is specified by a G-Bus physical address on a 32-bit address boundary. This register value is used for G-Bus Read access during DMA transfer from the G-Bus to the PCI Bus, or it is used for G-Bus Write access during DMA transfer from the PCI Bus to the G-Bus. This register value is held without being affected by a Reset. ⎯ 1:0 Reserved Figure 10.4.57 G-Bus Address Register 10-90 Chapter 10 PCI Controller 10.4.60 PDMAC PCI Bus Address Register (PDMPA) 63 Reserved : Type : Initial value 47 Reserved 38 39 PDMPA[39:32] R/W Undefined 31 PDMPA[31:16] R/W Undefined 15 PDMPA[15:2] R/W Undefined 2 1 0 : Type : Initial value 16 : Type : Initial value 32 0xD210 48 Reserved : Type : Initial value Bits 63:38 39:2 Mnemonic PDMPA Field Name Reserved PCI Bus Address Description PDMAC PCI-Bus Address (Default is undefined) The PCI Bus DMA transfer address is specified by a PCI Bus physical address on a 32-bit address boundary. This register value is held without being affected by a Reset. Note: This register value is used for PCI Bus Write access during DMA transfer from the G-Bus to the PCI Bus, or it is used for PCI Bus Read access during DMA transfer from the PCI Bus to the G-Bus. Read/Write ⎯ R/W 1:0 Reserved ⎯ Figure 10.4.58 PCI Bus Address Register 10-91 Chapter 10 PCI Controller 10.4.61 PDMAC Count Register (PDMCTR) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 Reserved 24 23 PDMCTR[23:16] R/W Undefined 15 PDMCTR[15:2] R/W Undefined 2 1 0 : Type : Initial value 16 32 0xD218 48 Reserved : Type : Initial value Bits 63:24 23:2 Mnemonic PDMCTR Field Name Reserved Transfer Byte Count Description PDMAC Transfer Count (Default is undefined) Sets an uncoded 24-bit transfer byte count in 32-bit word units. Also, the setting of this register must always be a multiple of the transfer size specified inside the PDMAC Configuration Register. No data transfer is performed if a count of “0” is set. This byte count value is calculated from the transferred byte size as the PDMAC performs a DMA transfer. This register value is held without being affected by a Reset. Read/Write ⎯ R/W 1:0 Reserved ⎯ Figure 10.4.59 Count Register 10-92 Chapter 10 PCI Controller 10.4.62 PDMAC Configuration Register (PDMCFG) 0xD220 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 Reserved 22 21 RSTFIFO 48 32 20 EXFER R/W 0x0 4 19 Reserved 16 R/W 0x0 15 14 13 REQDLY R/W 0x0 11 10 ERRIE R/W 0x0 9 NCCMPIE : Type : Initial value 3 2 1 XFRDIRC 8 NTCMPIE 7 6 5 0 CHRST R/W : Type 0x1 : Initial value Reserved CHNEN XFRACT Reserved BSWAP XFRSIZE R/W 0x0 R/W 0x0 R/W 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 Bit 63:22 21 Mnemonic RSTFIFO Field Name Reserved Reset FIFO Description Reset FIFO (Default: 0x0) Initializes the Read pointer and Write pointer to the FIFO in the PDMAC, and sets the FIFO hold count to “0”. Please use the software to clear this bit when it is set. This is a function for a diagnosis. Usually, it is not used. 1: Performs FIFO reset. 0: Does not perform FIFO reset. Read/Write ⎯ R/W 20 EXFER Endian Transfer Endian Transfer (Default: 0x0) Specifies whether to perform Endian transfer. Please use the default as is. Set up EXFER as follows according to a Endian setup of G-Bus. 1: G-Bus in Little Endian 0: G-Bus in Big Endian Request Delay (Default: 0x0) G-Bus transactions for DMA transfer must be performed separated at least by the interval this field specifies. 000: Continuously try to perform G-Bus transfer. 001: 16 G-Bus clocks 010: 32 G-Bus clocks 011: 64 G-Bus clocks 100: 128 G-Bus clocks 101: 256 G-Bus clocks 110: 512 G-Bus clocks 111: 1024 G-Bus clocks Interrupt Enable on Error (Default: 0x0) 1: PDMAC generates an error during error detection. 0: PDMAC does not generate an error during error detection. Interrupt Enable on Chain Done (Default: 0x0) 1: PDMAC generates an interrupt when the current chain is complete. 0: PDMAC does not generate an interrupt when the current chain is complete. R/W 19:14 13:11 REQDLY Reserved Request Delay Time R/W ⎯ 10 ERRIE Error Detect Interrupt Enable Normal Chain Complete Interrupt Enable R/W 9 NCCMPIE R/W Figure 10.4.60 PDMAC Configuration Register (1/2) 10-93 Chapter 10 PCI Controller Bit 8 Mnemonic NTCMPIE Field Name Description Read/Write 7 CHNEN 6 XFRACT Interrupt Enable on Transfer Done (Default: 0x0) Normal Data R/W Transfer Complete 1: PDMAC generates an interrupt when the current data transfer is complete. Interrupt Enable 0: PDMAC does not generate an interrupt when the current data transfer is complete. Chain Enable (Default: 0x0) (Read Only) Chain Enable R When the current data transfer is complete, this field reads the next data command Descriptor from the address indicated by the PDMAC Chain Address Register then indicates whether to continue the transfer or not. This bit is only set to “1” when either a CPU Write process or a Descriptor Read process sets a value other than “0” in the PDMAC Chain Address Register. This bit is cleared to “0” if either the Channel Reset bit is set, or “0” is set in the PDMAC Chain Address Register by a CPU Write or a Descriptor Read process. The above 0 value judgement is not performed when the TX49/H3 core stores the upper 32 bits in the PDMAC Chain Address Register. 1: Reads the next data command Descriptor. 0: Does not read the next data command Descriptor. Transfer Active (Default: 0x0) Transfer Active R/W Specifies whether to perform DMA transfer or not. Setting this bit after setting the appropriate value in the register group initiates DMA data transfer. This bit is not set if the PDMAC Count Register value is “0” and the Chain Enable bit is cleared when “1” is written to this bit. Even when a value other than “0” is written to the Chain Address Register, “1” is set to this bit and DMA transfer automatically starts. The above 0 value judgement is not performed when the TX49/H3 core stores the upper 32 bits in the PDMAC Chain Address Register. Data transfer will be stopped after a short delay if this bit is cleared while the data transfer is in progress. This bit is automatically cleared to “0” either when data transfer ends normally or is stopped by an error. Never clear XFRACT by software, because it stops guaranteeing a normal operation,. 1: Perform data transfer. 0: Do not perform data transfer. Reserved ⎯ R/W Byte Swap Within Swap Bytes in DWORD (Default: 0x0) Specifies whether to perform 32-bit data byte swapping. DWORD Please leave this bit at “0” for normal usage. Setting this bit when in the Big Endian mode executes data transfer so the byte order of the 32-bit data on the PCI Bus (which is Little Endian) does not change. 1: Swap the byte order of each 32-bit DWORD data, then transfer. 0: Transfer without swapping the byte order of each 32-bit DWORD data. Transfer Size (Default: 0x0) Transfer Size Specifies the data transfer size in one G-Bus transaction on the G-Bus. 00: 1 DWORD (32-bit) 01: 1 QWORD (64-bit) 10: 4 QWORD (Burst transfer) 11: Reserved Transfer Direction Transfer Direction (Default: 0x0) Specifies the DMA data transfer direction. 1: Transfers data from the G-Bus to the PCI Bus. 0: Transfers data from the PCI Bus to the G-Bus. Channel Reset (Default: 0x1) Channel Reset Resets the DMA channel. This bit must be cleared by the software in advance so the channel can start the data transfer. This reset function is not supported when PDMAC is in operation. Ensure that the Transfer Active (XFARCT) bit in the PDMSTATUS register is cleared prior to resetting the DMA channel. For chained DMA, also ensure either the Abnormal Chain Complete (ACCMP) or Normal Chain Complete (NCCMP) bit in the PDMSTATUS register is set. 1: All logic and State Machines are reset. 0: The channel becomes valid. 5 4 BSWAP 3:2 XFRSIZE R/W 1 XFRDIRC R/W 0 CHRST R/W Figure 10.4.60 PDMAC Configuration Register (2/2) 10-94 Chapter 10 PCI Controller 10.4.63 PDMAC Status Register (PDMSTATUS) 63 Reserved : Type : Initial value 47 Reserved : Type : Initial value 31 30 29 REQCNT R 0x00 15 Reserved 12 11 10 9 8 7 6 24 23 FIFOCNT R 0x0 5 4 Reserved 0xD228 48 32 20 19 18 17 16 Reserved FIFOWP R 0x0 3 2 FIFORP R 0x0 1 0 : Type : Initial value ERRINT DONEINT CHNEN XFRACT ACCMP NCCMP NTCMP CFGERR PCIERR CHNERR DATAERR R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R/W1C R/W1C 0x0 0x0 R/W1C R/W1C R/W1C R/W1C : Type 0x0 0x0 0x0 0x0 : Initial value Bit 63:30 29:24 Mnemonic REQCNT Field Name Reserved Request Delay Time Counter FIFO Hold Count Description Read/Write ⎯ R Request Delay Counter (Default: 0x00) This field indicates the request delay time counter value as 16 × n when the 6-bit value of this field is n. R FIFO Valid Entry Count (Default: 0x0) This field indicates the number of bytes that was written in the FIFO but not yet read. This is a diagnostic function. FIFO Write Pointer (Default: 0x0) This field indicates the next Write position in the FIFO. This is a diagnostic function. FIFO Read Pointer (Default: 0x0) This field indicates the next Read position in the FIFO. This is a dianostic function. Error Interrupt Status (Default: 0x0) Indicates whether to signal an error interrupt. 1: An error interrupt request exists. 0: No error interrupt request exists. Normal Transfer Complete Interrupt Status (Default: 0x0) Indicates whether a Normal Transfer Complete Interrupt is signaled. This bit becomes “1” when either the Normal Chain Complete bit (NCCMP) is set and the Normal Chain Complete Interrupt Enable bit (NCCMPIE) is set, or when the Normal Data Transfer Complete bit (NTCMP) is set and the Normal Data Transfer Complete Interrupt Enable bit (NTCMPIE) is set. 1: A Normal Transfer Complete Interrupt request exists. 0: No Normal Transfer Complete Interrupt request exists. Chain Enable (Default: 0x0) This bit is a copy of the Chain Enable bit in the PDMAC Configuration Register. R 23:20 FIFOCNT 19:18 FIFOWP FIFO Write Pointer FIFO Read Pointer Reserved 17:16 FIFORP R 15:12 11 ERRINT ⎯ R Error Interrupt Status 10 DONEINT Normal Transfer Complete Interrupt Status R 9 CHNEN Chain Enable R Figure 10.4.61 Status Register (1/2) 10-95 Chapter 10 PCI Controller Bit 8 Mnemonic XFRACT Field Name Transfer Active Description Transfer Active (Default: 0x0) This bit is a copy of the Transfer Active bit in the PDMAC Configuration Register. Abnormal Chain Complete (Default: 0x0) 1: Indicates that the Chain transfer ended in an error state. In other words, this reflects an OR operation of the PDMAC Status Register bits [3:0]. 0: Indicates that no error has occurred in the Chain transfer since the previous error bit was cleared. Note: Bits [3:0] of the PDMAC Status Register must be cleared in order to clear this bit. Normal Chain Complete (Default: 0x0) 1: Indicates that the Chain transfer ended in the Normal state. 0: Indicates that Chain transfer has not ended since this bit was previously cleared. Normal Data Transfer Complete (Default: 0x0) 1: Indicates that the data transfer specified by the PDMAC Register ended in the Normal state. 0: Indicates that data transfer has not ended since this bit was previously cleared. Configuration Error (Default: 0x0) 1: Indicates that either the current setting of the control portion in the Control Register and the Address/Count Register are not consistent with each other or the PDMAC stipulation is not being obeyed. DMA transfer stops. 0: Indicates that the current setting of the control portion in the Control Register can be tolerated. PCI Fatal Error (Default: 0x0) 1: Indicates that an error was signaled on the PCI Bus during the Chain process. 0: Indicates that no error has been signaled on the PCI Bus since this bit was previously cleared. G-Bus Chain Bus Error (Default: 0x0) 1: Indicates that a G-Bus error occurrred during the Chain process. DMA transfer stops. 0: Indicates that no G-Bus error has occurred during the Chain process since this bit was cleared. G-Bus Data Bus Error (Default: 0x0) 1: Indicates that a G-Bus error occurred during the data transfer process. DMA transfer stops. 0: Indicates that no G-Bus error has occurred during the data transfer process since this bit was cleared. Read/Write R 7 ACCMP Abnormal Chain Completion R 6 NCCMP Normal Chain Completion R/W1C 5 NTCMP Normal Data Transfer Complete R/W1C 4 3 CFGERR Reserved Configuration Error ⎯ R/W1C 2 PCIERR PCI Fatal Error R/W1C 1 CHNERR G-Bus Chain Error R/W1C 0 DATAERR G-Bus Data Error R/W1C Figure 10.4.61 Status Register (2/2) 10-96 Chapter 10 PCI Controller NCCMP NCCMPIE DONEINT Interrupt Controller (Interrupt No. 15) NTCMP NTCMPIE STLTRF ERRIE ERRINT CFGERR PCIERR CHNERR DATAERR ACCMP Figure 10.4.62 PDMAC Interrupt Signaling 10-97 Chapter 10 PCI Controller 10.5 PCI Configuration Space Register The PCI Configuration Space Register is accessed using PCI Configuration cycles by way of an external PCI host device only when in the Satellite mode. Table 10.5.1 lists registers contained within the PCI Configuration Space Register. The registers in the table with a shaded background are those whose values can be rewritten using EEPROM. (See 10.3.14.) Registers at addresses 0x00 through 0x41 can use the corresponding PCI Controller Control Register to access from the TX49/H3 core when in the Host mode. Please refer to the explanation of the corresponding PCI Controller Control registers for more information about these registers. This section only describes the registers that are accessed from the PCI Configuration Space. Also, it is possible to read some of the fields in the Status Register and PMCSR register from the Satellite Mode PCI Status Register. Please refer to the PCI Bus Specifications for more information on the PCI Configuration Register. Table 10.5.1 PCI Configuration Space Register Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h-DBh DCh E0h E4h-FFh Max_Lat Reserved Min_Gnt Reserved Reserved Interrupt Pin Retry Timeout Value Reserved Power Management Capabilities (PMC) Reserved Reserved Next Item Ptr (Next_Item_Ptr) Capability ID (Cap_ID) Interrupt Line TRDY Timeout Value Subsystem ID Reserved Capabilities Pointer (Cap_Ptr) BIST 31 Device ID Status Class Code Header Type Latency Timer Memory Space 0 Lower Base Address Memory Space 0 Upper Base Address Memory Space 1 Lower Base Address Memory Space 1 Upper Base Address Memory Space 2 Base Address I/O Space Base Address Reserved Subsystem Vendor ID 16 15 Vendor ID Command Revision ID Cache Line Size 0 Corresponding Register PCIID PCISTATUS PCICCREV PCICFG1 P2GM0PLBASE P2GM0PUBASE P2GM1PLBASE P2GM1PUBASE P2GM2PBASE P2GIOPBASE ⎯ PCISID ⎯ PCICAPPTR ⎯ PCICFG2 G2PTOCNT ⎯ ⎯ ⎯ ⎯ Power Management Control/Status Register (PMCSR) Reserved 10-98 Chapter 10 PCI Controller 10.5.1 15 Reserved Capability ID Register (Cap_ID) 8 7 0xDC 0 CID R 0x01 : Type : Initial value Bits 15:8 7:0 Mnemonic CID Field Name Reserved Capability ID Description Capability ID (Default: 0x01) Indicates that a list is the link list of the Power Management Register. Read/Write ⎯ R Figure 10.5.1 Capability ID Register 10-99 Chapter 10 PCI Controller 10.5.2 15 Reserved Next Item Pointer Register (Next_Item_Ptr) 8 7 0xDD 0 NIP R 0x00 : Type : Initial value Bits 15:8 7:0 Mnemonic NIP Field Name Reserved Next Item Pointer Description Next Item Pointer (Default: 0x0) This is the Next Item pointer. Indicates the end of a list. Read/Write ⎯ R Figure 10.5.2 Next Item Pointer Register 10-100 Chapter 10 PCI Controller 10.5.3 15 PMESPT R 0x19 Power Management Capability Register (PMC) 11 10 9 8 Reserved 6 5 DSI R 0 0xDE 4 3 2 PMVER R 0x2 : Type : Initial value 0 D2SPT D1SPT R 0 R 0 Reserved PMECLK R 0 Bit 15:11 Mnemonic PMESPT Field Name PME Output Support Description Read/Write R PME_ Support (Fixed Value: 0x09) Indicates that the PME* signal can be output from the state where the bit is set to “1”. Bit 15: Can output the PME* signal from the D3cold state. Bit 14: Can output the PME* signal from the D3hot state. Bit 13: Can output the PME* signal from the D2 state. Bit 12: Can output the PME* signal from the D1 state. Bit 11: Can output the PME* signal from the D0 state. Note: With the TX4938 PCI Controller, it is possible to output the PME* signal from the D0 and the D3hot states. D2_Support (Fixed Value: 0) 0: Indicates that the D2 state is not supported. D1_Support (Fixed Value: 0) 0: Indicates that the D1 state is not supported. DSI (Fixed Value: 0) 0: Indicates that Device Specific Initialization is not required. PME Clock (Fixed Value: 0) 0: Indicates that the PCI Clock is not required to assert the PME* signal. Version (Fixed Value: 0x2) 2: Indicates compliance with "PCI Power Management Interface Specification" Version 1.1. R R ⎯ R ⎯ R R 10 9 8:6 5 4 3 2:0 D2SPT D1SPT D2 Support D1 Support Reserved DSI DSI Reserved PMECLK PMVER PME Clock Power Management I/F Version Figure 10.5.3 PMC Register 10-101 Chapter 10 PCI Controller 10.5.4 15 PMESTA Power Management Control/Status Register (PMCSR) 9 Reserved 8 PMEEN 0xE0 2 1 PS R/W 0x0 : Type : Initial value 0 14 7 Reserved R/W1C 0x0 R/W 0x0 Bit 15 Mnemonic PMESTA Field Name PME Status Description PME_Status (Default: 0x0) Indicates the existence of a PME (Power Management Event) . 1: There is a PME. 0: There is no PME. The value of this bit becomes “1” when Writing a “1” to the PME bit (P2GCFG.PME) of the P2G Configuration Register. This bit is cleared when the Host Bridge writes a “1”. It is possible to signal a PME* Clear Interrupt at this time. PME_En (Default: 0x0) Sets PME* signal assertion to enable or disable. 1: Enables assertion of the PME* signal. 0: Disables assertion of the PME* signal. The PME_En set bit of the P2G Status Register (P2GSTATUS.PMEES) is set when this bit is set. At this time, it is possible to signal the PME_En set interrupt. PowerState (Default: 0x0) Sets the Power Management state. The Power Management State Change bit (P2GSTATUS.PMSC) of the P2G Status Register is set when the value of this field is changed. It also becomes possible to generate a Power State Change Interrupt at this time. The TX4938 can read the value of this field from the PowerState field (PCISSTATUS.PS) of the Satellite Mode PCI Status Register. 00b: D0 (no change) 01b: D1 :Reserved 10b: D2 :Reserved 11b: D3hot Read/Write R/W1C 14:9 8 PMEEN Reserved PME Enable R/W ⎯ 7:2 1:0 PS Reserved Power State R/W ⎯ Figure 10.5.4 PMCSR Register 10-102 Chapter 11 Serial I/O Port 11. Serial I/O Port 11.1 Features The TX4938 asynchronous Serial I/O (SIO) interface has two full duplex UART channels (SIO0 and SIO1). SIO has the following features. (1) Full duplex transmission (simultaneous transmission and reception) (2) On-chip baud rate generator (3) Modem flow control (CTS/RTS) (4) FIFO • • Transmit FIFO: 8 bits × 8 stages Reception FIFO: 13 bits × 16 stages (data: 8 bits, status: 5 bits) (5) Supports DMA transfer (6) Supports multi-controller systems • Supports Master/Slave operation 11-1 Chapter 11 Serial I/O Port 11.2 Block Diagram SCLK Baud Rate IMBUSCLK SIOCLK Baud Rate Control Register IM Bus Receiver Receive Data Register Receive Data FIFO Read Buffer Receiver Shift Register RTS* RXD DMA/INT Control Register Interrupt I/F Read /Write DMA/INT Status Register FIFO Control Register Line Control Register Status Change Interrupt Status Register Reset* Request Control Transmitter Transmit Data Register Transmit Data FIFO TEMP Buffer Transmitter Shift Register CTS* TXD TX4938 Figure 11.2.1 SIO Internal Block Diagram 11-2 Chapter 11 Serial I/O Port 11.3 Detailed Explanation 11.3.1 Overview During reception, serial data that are input as an RXD signal from an external source are converted into parallel data, then are stored in the Receive FIFO buffer. Parallel data stored in the FIFO buffer are fetched by either CPU or DMA transfer. During transmission, parallel data written to the Transmit FIFO buffer by CPU or DMA transfer are converted into serial data, then are output as a TXD signal. 11.3.2 Data Format The TX4938 SIO can use the following data formats. Data Length Stop Bit Parity Bit Parity Format Start Bit : 8/7 bits : 1/2 bits : Yes/No : Even/Odd : Fixed to 1 bit Figure 11.3.1 illustrates the data frame when making each setting. 11-3 Chapter 11 Serial I/O Port 8-bit Data Transfer Direction 1 2 3 4 5 6 7 8 9 10 11 12 stop bit2, parity Start stop bit1, parity Start stop bit2 Start stop bit1 Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 stop stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Parity stop stop 7-bit Data 1 stop bit2, parity Start stop bit1, parity Start stop bit2 Start stop bit1 Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 stop stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 Parity stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 Parity stop stop 2 3 4 5 6 7 8 9 10 11 12 8-bit Data Multi-Control System WUB = W ake Up bit 1: Address (ID) Frame 0: Data Frame 3 4 5 6 7 8 9 10 11 12 1 stop bit2 Start stop bit1 Start 2 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 W UB stop stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 W UB stop 7-bit Data Multi-Control System 1 stop bit2 Start stop bit1 Start bit0 bit1 bit2 bit3 bit4 bit5 bit6 W UB stop bit0 bit1 bit2 bit3 bit4 bit5 bit6 WUB stop stop 2 3 4 5 6 7 8 9 10 11 12 Figure 11.3.1 Data Frame Configuration 11-4 Chapter 11 Serial I/O Port 11.3.3 Serial Clock Generator Generates the Serial Clock (SIOCLK). SIOCLK determines the serial transfer rate and has a frequency that is 16× the baud rate. One of the following can be selected as the source for the Serial Clock (SIOCLK). • • • Internal System Clock (IMBUSCLK) External Clock Input (SCLK) Baud rate generator circuit output The IMBUSCLK frequency can be selected from frequencies that are 1/2, 1/2.5, 1/3, or 1/4 the frequency of the CPU clock. The maximum frequency tolerance of the external clock input (SCLK) is 45% the frequency of IMBUSCLK. For example, if IMBUSCLK = 60 MHz, then set SCLK to 27 MHz or less. The baud rate generator is a circuit that divides these clock signals according to the following formula. Baud Rate = fc Prescalar × Divisor ×16 • • • fc: Clock frequency of IMBUSCLK or an external clock input (SCLK) Prescalar Value: 2, 8, 32, 128 Divide Value: 1, 2, 3,…255 Table 11.3.1 shows example settings of divide values relative to representative baud rates. 1/2 1/8 1/32 1/128 Selector Prescalar T0 T2 T4 T6 Selector Divider Selector 1/1 − 1/255 IMBUSCLK fc SCLK SIOCLK Select SIOCLK SILCR. SCS [1] Select CLK SIBGR. BCLK Baud Rate Generator Baud Rate Divide value SIBGR. BRD Select SIOCLK SILCR. SCS [0] Figure 11.3.2 Baud Rate Generator and SIOCLK Generator It is possible to correctly receive data if the error of the baud rate set by this controller is within 3.12 % of the target baud rate (communication baud rate). 11-5 Chapter 11 Serial I/O Port Table 11.3.1 Example Divide Value Settings (and error [%] from target baud rate value) fc[MHz] IMBUSCLK 66 kbps 0.11 0.15 0.30 0.60 1.20 2.40 4.80 9.60 14.40 19.20 28.80 38.40 57.60 76.80 115.20 60 0.11 0.15 0.30 0.60 1.20 2.40 4.80 9.60 14.40 19.20 28.80 38.40 57.60 76.80 115.20 Prescalar Value (SIBGR.BLCK) and Divide Value (SIBGR.BRD) 2 8 32 128 215 -0.07% 107 215 -0.07% 107 215 -0.07% 107 215 -0.07% 143 107 0.16% 0.39% 0.39% 54 -0.54% 36 -0.54% 27 -0.54% 18 -0.54% 13 3.29% 9 -0.54% 7 -4.09% 255 195 195 195 195 130 65 0.16% 0.16% 0.16% 0.16% 0.16% 4.45% 0.16% 0.39% 54 -0.54% 27 -0.54% 13 3.29% 9 -0.54% 7 -4.09% 0.39% 54 -0.54% 27 -0.54% 13 3.29% 7 -4.09% 72 -0.54% 54 -0.54% 36 -0.54% 27 -0.54% 18 -0.54% 98 -0.35% 49 -0.35% 24 12 6 1.73% 1.73% 1.73% 98 -0.35% 49 -0.35% 24 12 8 6 1.73% 1.73% 1.73% 1.73% 98 -0.35% 49 -0.35% 33 -1.36% 24 16 12 8 6 1.73% 1.73% 1.73% 1.73% 1.73% 131 -0.07% 96 48 96 48 96 48 24 16 12 8 6 4 3 2 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 1 0.00% 24 12 6 4 3 2 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 1 0.00% 24 12 6 3 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 33 -0.82% 24 12 6 3 0.00% 0.00% 0.00% 0.00% 98 -0.35% 49 -0.35% 33 -1.36% 24 16 1.73% 1.73% SCLK 7.373 0.11 0.15 0.30 0.60 1.20 2.40 4.80 9.60 14.40 19.20 28.80 38.40 57.60 76.80 115.20 11-6 Chapter 11 Serial I/O Port 11.3.4 Data Reception When the Serial Data Reception Disable bit (RSDE) of the Flow Control Register (SIFLCRn) is set to “0”, reception operation starts after the RXD signal start bit is detected. Start bits are detected when the RXD signal transitions from the High state to the Low state. Therefore, the RXD signal is not interpreted as a start bit if it is Low when the Serial Data Reception Disable bit is set to “0”. The received data are stored in the Receive FIFO. The Reception Data Full bit (RDIS) of the DMA/Interrupt Status Register (SIDISRn) is set if the byte count of the stored reception data exceeds the value set by the Receive FIFO Request Trigger Level field (RDIL) of the FIFO Control Register (SIFCRn). An interrupt is signaled when the Reception Data Interrupt Enable bit (RIE) of the DMA/Interrupt Control Register (SIDICRn) is set. The received data can be read from the Receive FIFO Data Register (SIRFIFOn). In addition, DMA transfer is initiated when the Reception Data DMA Enable bit (RDE) of the DMA/Interrupt Control Register (SIDICRn) is set. 11.3.5 Data Transmission Data stored in the Transmission Data FIFO are transmitted when the Serial Data Transmission Disable bit (TSDE) of the Flow Control Register (SIFLCRn) is set to “0”. If the available space in the Transmit FIFO is equal to or greater than the byte count set by the Transmit FIFO Request Trigger Level (TDIL) of the Control Register (SIFCRn), the transmission data empty bit (TDIS) of the DMA/Interrupt Status Register (SIDISRn) is set. An interrupt is signaled when the Transmission Data Interrupt Enable bit (TIE) of the DMA/Interrupt Control Register (SIDICRn) is set. In addition, DMA transfer is initiated when the Transmission Data DMA Enable bit (TDE) of the DMA/Interrupt Control Register (SIDICRn) is set. 11.3.6 DMA Transfer The DMA Request Select field (INTDMA[7:0]) of the Pin Configuration Register (PCFG) can be used to allocate DMA channels for each reception and transmission channel in the following manner. SIO Channel 1 Reception SIO Channel 1 Transmission SIO Channel 0 Reception SIO Channel 0 Transmission DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 Set the DMA Channel Control Register of the DMA Controller as described below. DMA Request Polarity DMA Acknowledge Polarity Request Detection Low Active Low Active Level Detection DMCCRn.ACKPOL = 0 DMCCRn.REQPOL = 0 DMCCRn.EGREQ = 0 11-7 Chapter 11 Serial I/O Port Transfer Size Transfer Address Mode 1 Byte Dual DMCCRn.XFSZ = 000b DMCCRn.SNGAD = 0 In the case of transmission channels, the address of the Transmit FIFO Register (SITFIFOn) is set in the DMAC Destination Address Register (DMDARn). In the case of reception channels, the address of the Receive FIFO Register (SIRFIFOn) is set in the DMAC Source Address Register (DMSARn). Please set the addresses specified in “11.4.8 Transmit FIFO Register” and “11.4.9 Receive FIFO Register” since the set address differs depending on the Endian mode. 11.3.7 Flow Control SIO supports hardware flow control that uses the RTS*/CTS* signal. The CTS* (Clear to Send) input signal indicates that data can be received from the reception side when it is Low. Setting the Transmission Enable Select bit (TES) of the Flow Control Register (SIFLCRn) makes transmission flow control that uses the CTS* signal more effective. It is also possible to generate status change interrupts by changing the state of the CTS* signal. The conditions in which interrupts are generated can be selected by the CTSS Active Condition field of the DMA/Interrupt Control Register (SIDICRn). Setting the RTS* (Request to Send) output signal to High requests the transmission side to pause transmission. Transmission resumes when the reception side becomes ready and the RTS* signal is set to Low. Setting the Reception Enable Select bit (RCS) of the flow Control Register (SIFLCRn) makes reception flow control that uses the RTS* signal more effective. The RTS* signal pin status becomes High when data of the byte count set by the RTS Active Trigger Level field (RTSTL) of the Flow Control Register (SIFLCRn) accumulates in the Receive FIFO. The RTS* signal can also be made High by setting the RTS Software Control bit (RTSSC) of the Flow Control Register (SIFLCRn). Setting this bit requests the transmission side to pause transmission. 11.3.8 Reception Data Status Status data such as the following is also stored in the Receive FIFO. • Overrun error An overrun error is generated if all 16-stage Receive FIFO buffers become full and more data is transferred to the Reception Read buffer. When this occurs, the Overrun Status bit is set by the last stage of the Receive FIFO. • Parity error A parity error is generated when a parity error is detected in the reception data. • Framing error A framing error is generated when “0” is detected at the first stop bit of the reception data. • Break reception A break is detected when a framing error occurs in the reception data and all data in a single frame are “0”. When this occurs, 2 frames (2 Bytes) of 0x00 data are stored in the Receive FIFO. 11-8 Chapter 11 Serial I/O Port The Reception Error Interrupt bit (SIDISR.ERI) of the DMA/Interrupt Status Register (SIDISRn) is set when one of the following errors is detected: an overrun error, a parity error, or a framing error. An interrupt is signaled if the Reception Error Interrupt Enable bit of the DMA/Interrupt Control Register (SIDICRn) is set. The Break Detected bit (UBRKD) and the Receiving Break bit (RBRKD) of the Status Change Interrupt Status Register (SISCISR) is set when a break is detected. The Break Detected bit (UBRKD) remains set until it is cleared by the software. The Receiving Break bit (RBRKD) is automatically cleared when a frame is received that is not a break. The status of the next reception data to be read is set to the Overrun Error bit (UOER), Parity Error bit (UPER), Framing Error bit (UFER), and the Receive Break bit (RBRKD). Each of these statuses is updated when reception data is read from the Receive FIFO Register (SIRFIFOn). During DMA transfer, an error is signaled and DMA transfer stops with error data remaining in the Receive FIFO if either an error (Framing Error, Parity Error, or Overrun Error) or a Reception time out (TOUT) is detected. If a Reception Error occurs during DMA transfer, use the Receive FIFO Reset bit (RFRST) of the FIFO Control Register (SIFCRn) to clear the Receive FIFO. However, a software reset will be required if a reception overrun error has occurred. Refer to “11.3.10 Software Reset” for more information. 11.3.9 Reception Time Out A Reception time out is detected and the Reception Time Out bit (TOUT) of the DMA/Interrupt Status Register (SIDISR) is set under the following conditions. • Non-DMA transfer mode (SIDICRn.RDE = 0): When at least 1 Byte of reception data exists in the Receive FIFO and the data reception time for the 2 frames (2 Bytes) after the last reception has elapsed • DMA transfer mode (SIDICRn.RDE = 1): When the data reception time for the 2 frames (2 Bytes) after the last reception has elapsed regardless of whether reception data exists in the Receive FIFO 11.3.10 Software Reset It is necessary to reset the FIFO and perform a software reset in the following situations. 1. 2. After transmission data is set in FIFO, etc., transmission started but stopped before its completion An overrun occurred during data reception Software reset is performed by setting the Software Reset bit (SWRST) of the FIFO Control Register (SIFCR). This bit automatically returns to “0” after initialization is complete. This bit must be set again since all SIO registers are initialized by software resets. 11-9 Chapter 11 Serial I/O Port 11.3.11 Error Detection/Interrupt Signaling An interrupt is signaled if an error or an interrupt cause is detected, the corresponding status bit is set and the corresponding Interrupt Enable bit is set. The following figure shows the relationship between the status bit for each interrupt cause and each interrupt enable bit. Please refer to the explanation for each status bit for more information about each interrupt cause. Transmission DMA Acknowledge DMAC Transmission DMA Request SIDICR.TDE “0” Write R Transmission Data Empty SIDSR.TDIS SIDICR.TIE SISCISR.OERS SIDICR.STIE[5] R “0” Write SISCISR.CTSS SIDICR.STIE[4] S SIDICR.CTSAC SIDISR.STIS R “0” Write SISCISR.RBRKD SIDICR.STIE[3] SISCISR.TRDY SIDICR.STIE[2] SISCISR.TXALS SIDICR.STIE[1] During Break Reception Transmission Data Empty Transmission Complete CTS Pin CTS Status Overrun Error SISCISR.UBRKD SIDICR.STIE[0] R “0” Write Break Detected Frame Error SIDISR.ERI To IRC SIDICR.SPIE R “0” Write Parity Error SIDISR.TOUT Reception Time Out R SIDICR.RIE “0” Write SIDISR.RDIS Reception DMA Acknowledge DMAC Transmission DMA Acknowledge SIDICR.RDE “0” Write R Reception Data Full Figure 11.3.3 Relationship Between Interrupt Status Bits and Interrupt Signals 11-10 Chapter 11 Serial I/O Port 11.3.12 Multi-Controller System The Multi-Controller System consists of one Master Controller, and multiple Slave Controllers as shown below in Figure 11.3.4. In the case of the Multi-Controller System, the Master Controller transmits an address (ID) frame to all Slave Controllers, then transmits and receives data with the selected Slave Controller. Slave Controllers that were not selected will ignore this data. Data frames whose data frame Wake Up bits (WUB) are “1” are handled as address (ID) frames. Data frames whose Wake Up bit (WUB) is “0” are handled as data frames. Master TXD RXD RXD TXD Slave #1 RXD TXD Slave #2 RXD TXD Slave #3 Figure 11.3.4 Example Configuration of Multi-Controller System The data transfer procedure for the Multi-Controller System is as follows. (1) The Master and Slave Controllers set the Mode field (UMODE) of the Line Control Register (SILCR) to “10” or “11” to set the Multi-Controller System mode. Also, the Slave Controller sets the open drain enable bit (UODE) of the Line Control Register (SILCR), setting the TXD output signal to open drain output. (2) The Slave Controller sets the Reception Wake Up bit (RWUB) of the Line Control Register (SILCR), making it possible to receive address (ID) frames from the Master Controller. (3) The Master Controller sets the Transmission Wake Up bit (TWUB) of the Line Control Register (SILCR), and transmits the address (ID) of the selected Slave Controller. This causes the address (ID) frame to be transmitted. The Reception after Address Transmission Wake Up bit (RWUB) is cleared, enabling reception of data frames. (4) Since the Reception Wake Up bit (RWUB) is set, the Slave Controller generates an interrupt to the CPU by receiving an address (ID) frame. The CPU compares its own address (ID) and the received data together. If they do not match, the Reception Wake Up bit (RWUB) is cleared, making data frame reception possible. (5) The Master Controller and the selected Slave Controller clear the Transmission Wake Up bit (TWUB) of the Line Control Register (SILCR), then set the mode that transmits data frames. (6) Transmit/Receive data between the Master Controller and the selected Slave Controller. Then, Slave Controllers that were not selected ignore data frames since the Reception Wake Up bit (RWUB) is still set. 11-11 Chapter 11 Serial I/O Port 11.4 Registers With the exception of DMA access to the Transmit FIFO Register or the Receive FIFO Register, please use Word access when accessing register in the Serial I/O Port. Table 11.4.1 SIO Registers Offset Address SIO0 (Channel 0) 0xF300 0xF304 0xF308 0xF30C 0xF310 0xF314 0xF318 0xF31C 0xF320 SIO1 (Channel 1) 0xF400 0xF404 0xF408 0xF40C 0xF410 0xF414 0xF418 0xF41C 0xF420 SILCR1 SIDICR1 SIDISR1 SISCISR1 SIFCR1 SIFLCR1 SIBGR1 SITFIFO1 SIRFIFO1 Line Control Register 1 DMA/Interrupt Control Register 1 DMA/Interrupt Status Register 1 Status Change Interrupt Status Register 1 FIFO Control Register 1 Flow Control Register 1 Baud Rate Control Register 1 Transmit FIFO Register 1 Receive FIFO Register 1 SILCR0 SIDICR0 SIDISR0 SISCISR0 SIFCR0 SIFLCR0 SIBGR0 SITFIFO0 SIRFIFO0 Line Control Register 0 DMA/Interrupt Control Register 0 DMA/Interrupt Status Register 0 Status Change Interrupt Status Register 0 FIFO Control Register 0 Flow Control Register 0 Baud Rate Control Register 0 Transmit FIFO Register 0 Receive FIFO Register 0 Mnemonic Register Name 11-12 Chapter 11 Serial I/O Port 11.4.1 Line Control Register 0 (SILCR0) Line Control Register 1 (SILCR1) 0xF300 (Ch. 0) 0xF400 (Ch. 1) 16 Reserved : Type : Initial value 15 14 13 R/WUB TWUB UODE R/W 0 R/W 1 R/W 0 12 Reserved 7 6 SCS R/W 10 5 4 3 2 UEPS UPEN USBL R/W 0 R/W 0 R/W 0 1 0 UMODE R/W 00 : Type : Initial value These registers specify the format of asynchronous transmission/reception data. 31 Bit 31:16 15 Mnemonic RWUB Field Name Reserved Receive Wake Up Bit Description Read/Write ⎯ R/W Wake Up Bit for Receive (Default: 0) When in the Multi-Controller System mode, this field selects whether to receive address (ID) frames whose Wake Up bits (WUB) are “1” or to receive data frames whose Wake Up bits (WUB) are “0”. This value is undefined when not in the Multi-Controller System mode. 0: Receive data frames. 1: Receive address (ID) frames. R/W Wake Up Bit for Transmit (Default: 1) When in the Multi-Controller System mode, this field specifies the Wake Up bit (WUB). This value is undefined when not in the Multi-Controller System mode. 0: Data frame transfer (WUB = 0) 1: Address (ID) frame transfer (WUB = 1) R/W TXD Open Drain Enable (Default: 0) This field selects the output mode of the TXD signal. When in the Multi-Controller System mode, the Slave Controller must set the TXD signal to Open Drain. 0: Totem pole output 1: Open drain output ⎯ SIO Clock Select (Default: 00) This field selects the serial transfer clock. The clock frequency that is the serial transfer clock divided by 16 becomes the baud rate (bps). 00: Internal clock (IMBUSCLK) 01: Baud rate generator output that divided IMBUSCLK 10: External clock (SCLK) 11: Baud rate generator output that divided SCLK UART Even Parity Select (Default: 0) This field selects the parity mode. 0: Odd parity 1: Even parity UART Parity Enable (Default: 0) This field selects whether to perform the parity check. This bit must be cleared in multidrop systems (i.e., when the UMODE field is 10 or 11.) 0: Disable the parity check 1: Enable the parity check R/W 14 TWUB Transmit Wake Up Bit 13 UODE Open Drain Enable 12:7 6:5 SCS Reserved Clock Select 4 UEPS Even Parity Select R/W 3 UPEN Parity Check Enable R/W Figure 11.4.1 Line Control Register (1/2) 11-13 Chapter 11 Serial I/O Port Bit 2 Mnemonic USBL Field Name Stop Bit Length Description UART Stop Bit Length (Default: 0) This field specifies the stop bit length. 0: 1 bit 1: 2 bit UART Mode (Default: 00) This field sets the data frame mode. 00: 8-bit data length 01: 7-bit data length 10: Multi-Controller 8-bit data length 11: Multi-Controller 7-bit data length Read/Write R/W 1:0 UMODE Mode R/W Figure 11.4.1 Line Control Register (2/2) 11-14 Chapter 11 Serial I/O Port 11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) DMA/Interrupt Control Register 1 (SIDICR1) 0xF304 (Ch. 0) 0xF404 (Ch. 1) 16 Reserved : Type : Initial value 15 TDE R/W 0 14 RDE R/W 0 13 TIE R/W 0 12 RIE R/W 0 11 SPIE R/W 0 10 9 8 Reserved 6 5 STIE R/W 000000 : Type : Initial value 0 These registers use either DMA or interrupts to execute the Host Interface. 31 CTSAC R/W 00 Bit 31:16 15 Mnemonic TDE Field Name Reserved Transmit DMA Transfer Enable Description Transmit DMA Enable (Default: 0) This field sets whether to use DMA in the method for writing transmission data to the Transmit FIFO. 0: Do not use DMA. 1: Use DMA. Receive DMA Enable (Default: 0) This field sets whether to use DMA in the method for reading reception data from the Receive FIFO. 0: Do not use DMA. 1: Use DMA. Transmit Data Empty Interrupt Enable (Default: 0) When there is open space in the Transmit FIFO, this field sets whether to signal an interrupt. Set “0” when in the DMA Transmit mode (TDE = 1). 0: Do not signal an interrupt when there is open space in the Transmit FIFO. 1: Signal an interrupt when there is open space in the Transmit FIFO. Read/Write ⎯ R/W 14 RDE Receive DMA Transfer Enable R/W 13 TIE Transmit Data Empty Interrupt Enable R/W 12 RIE Reception Data Full Interrupt Enable Receive Data Full Interrupt Enable (Default: 0) This field sets whether to signal interrupts when reception data is full (SIDISRn.RDIS = 1) or a reception time out (SIDISRn.TOUT = 1) occurs. Set to “0” when in the DMA Receive mode (RDE = 1). 0: Do not signal interrupts when reception data is full/reception time out occurred. 1: Signal interrupts when reception data is full/reception time out occurred. Receive Data Error Interrupt Enable (Default: 0) This field sets whether to signal interrupts when a reception error (Frame Error, Parity Error, Overrun Error) occurs (SIDISR.ERI = 1). 0: Do not signal reception error interrupts. 1: Signal reception error interrupts. CTSS Active Condition (Default: 00) This field specifies status change interrupt request conditions using the CTS Status (CTSS) of the Status Change Interrupt Status Register. 00: Do not detect CTS signal changes. 01: Rising edge of the CTS pin 10: Falling edge of the CTS pin 11: Both edges of the CTS pin R/W 11 SPIE Reception Error Interrupt Enable R/W 10:9 CTSAC CTSS Active Condition R/W 8:6 Reserved ⎯ Figure 11.4.2 DMA/Interrupt Control Register (1/2) 11-15 Chapter 11 Serial I/O Port Bit 5:0 Mnemonic STIE Field Name Status Change Interrupt Enable Description Status Change Interrupt Enable (Default: 0x00) This field sets the set conditions of the Status Change bit (STIS) of the DMA/Interrupt Status Register (SIDISR). The condition is selected depending on which bit of the Status Change Interrupt Status Register (SISCISR) is set. (Multiple selections are possible.) An SIO interrupt is asserted when STIC is “1”. 000000: Do not detect status changes. 1*****: Set “1” to STIS when the Overrun bit (OERS) is “1”. *1****: Set “1” to STIS when a change occurs in a condition set by the CTSS Active Condition field (CTSAC) in the CTS Status bit (CTSS). **1***: Set “1” to STIS when the Break bit (RBRKD) becomes “1”. ***1**: Set “1” to STIS when the Transmit Data Empty bit (TRDY) becomes “1”. ****1*: Set “1” to STIS when the Transmission Complete bit (TXALS) becomes “1”. *****1: Set “1” to STIS when the Break Detection bit (UBRKD) becomes “1”. Read/Write R/W Figure 11.4.2 DMA/Interrupt Control Register (2/2) 11-16 Chapter 11 Serial I/O Port 11.4.3 DMA/Interrupt Status Register 0 (SIDISR0) DMA/Interrupt Status Register 1 (SIDISR1) 0xF308 (Ch. 0) 0xF408 (Ch. 1) 16 Reserved : Type : Initial value 15 14 13 12 11 10 ERI 9 TOUT 8 TDIS 7 RDIS 6 STIS 5 Reserved These registers indicate the DMA or interrupt status information. 31 4 RFDN R 00000 0 UBRK UVALID UFER UPER UOER R 0 R 1 R 0 R 0 R 0 R/W0C R/W0C R/W0C R/W0C R/W0C 0 0 1 0 0 : Type : Initial value Bit 31:16 15 Mnemonic UBRK Field Name Reserved Receive Break Description UART Break (Default: 0) This field indicates the break reception status of the next data in the Receive FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates the status. 0: No breaks 1: Detect breaks UART Available Data (Default: 1) This field indicates whether or not data exists in the Receive FIFO (SIRFIFO). 0: Data exists in the Receive FIFO. 1: No data exists in the Receive FIFO. UART Frame Error (Default: 0) This field indicates the frame error status of the next data in the Receive FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates the status. 0: There are no frame errors. 1: There are frame errors. UART Parity Error (Default: 0) This field indicates the parity error status of the next data in the Receive FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates the status. 0: There are no parity errors. 1: There are parity errors. UART Overrun Error (Default: 0) This register indicates the overrun status of the next data in the Receive FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates the status. 0: There are no overrun errors. 1: There are overrun errors. Receive Data Error Interrupt (Default: 0) This bit is immediately set to “1” when a reception error (Frame Error, Parity Error, or Overrun Error) is detected. Time Out (Default: 0) This bit is set to “1” when a reception time out occurs. Read/Write ⎯ R 14 UVALID Receive FIFO Available Status R 13 UFER Frame Error R 12 UPER Parity Error R 11 UOER Overrun Error R 10 ERI Reception Error Interrupt Reception Time Out Transmission Data Empty R/W0C 9 8 TOUT TDIS R/W0C Transmit DMA/Interrupt Status (Default: 1) R/W0C This bit is set when available space of the amount set by the Transmit FIFO Request Trigger Level (TDIL) of the FIFO Control Register (SIFCR) exists in the Transmit FIFO. Figure 11.4.3 DMA/Interrupt Status Register (1/2) 11-17 Chapter 11 Serial I/O Port Bit 7 Mnemonic RDIS Field Name Reception Data Full Description Read/Write R/W0C Receive DMA/Interrupt Status (Default: 0) This bit is set when valid data of the amount set by the Receive FIFO Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored in the Receive FIFO. R/W0C Status Change Interrupt Status (Default: 0) This bit is set when at least one of the interrupt statuses selected by the Status Change Interrupt Condition field (STIE) of the DMA/Interrupt Control Register (SIDICR) becomes “1”. ⎯ Receive FIFO Data Number (Default: 00000) This field indicates how many stages of reception data remain in the Receive FIFO (0 – 16 stages). R 6 STIS Status Change 5 4:0 RFDN Reserved Reception Data Stage Status Figure 11.4.3 DMA/Interrupt Status Register (2/2) 11-18 Chapter 11 Serial I/O Port 11.4.4 Status Change Interrupt Status Register 0 (SISCISR0) Status Change Interrupt Status Register 1 (SISCISR1) 0xF30C (Ch. 0) 0xF40C (Ch. 1) 16 Reserved : Type : Initial value 15 Reserved 6 5 4 3 2 1 0 31 OERS CTSS RBRKD TRDY TXALS UBRKD R/W0C 0 R 0 R 0 R 1 R 1 R/W0C : Type 0 : Initial value Bit 31:6 5 Mnemonic ⎯ OERS Field Name Reserved Overrun Error Description ⎯ Overrun Error Status (Default: 0) This bit is immediately set to “1” when an overrun error is detected. This bit is cleared when a “0” is written. CTS Terminal Status (Default: 0) This field indicates the status of the CTS signal. 1: The CTS signal is High. 0: The CTS signal is Low. Receive Break (Default: 0) This bit is set when a break is detected. This bit is automatically cleared when a frame that is not a break is received. 1: Current status is Break. 0: Current status is not Break. Transmit Ready (Default: 1) This bit is set to “1” if at least one stage in the Transmit FIFO is free. Transmit All Sent (Default: 1) This bit is set to “1” if the Transmit FIFO and all transmission shift registers are empty. UART Break Detect (Default: 0) This bit is set when a break is detected. Once set, this bit remains set until cleared by writing a “0” to it. Read/Write ⎯ R/W0C 4 CTSS CTS Status R 3 RBRKD Receiving Break R 2 1 TRDY TXALS Transmission Data Empty Transmission Complete Break Detected R R 0 UBRKD R/W0C Figure 11.4.4 Status Change Interrupt Status Register 11-19 Chapter 11 Serial I/O Port 11.4.5 FIFO Control Register 0 (SIFCR0) FIFO Control Register 1 (SIFCR1) 0xF310 (Ch. 0) 0xF410 (Ch. 1) 16 Reserved : Type : Initial value 15 SWRST These registers set control of the Transmit/Receive FIFO buffer. 31 14 Reserved 9 8 RDIL R/W 00 7 6 5 4 TDIL R/W 00 3 2 1 0 Reserved TFRST RFRST FRSTE R/W 0 R/W 0 R/W 0 R/W : Type 0 : Initial value Bit 31:16 15 Mnemonic ⎯ SWRST Field Name Reserved Software Reset Description ⎯ Software Reset (Default: 0) This field performs SIO resets except for the FIFOs. Setting this bit to “1” initiates the reset. Set registers are also initialized. This bit returns to “0” when initialization is complete. 0: Normal operation 1: SIO software reset ⎯ Receive FIFO DMA/Interrupt Trigger Level (Default: 00) This register sets the level for reception data transfer from the Receive FIFO. 00: 1 Byte 01: 4 Bytes 10: 8 Bytes 11: 12 Bytes ⎯ Transmit FIFO DMA/Interrupt Trigger Level (Default: 00) This register sets the level for transmission data transfer to the Transmit FIFO. 00: 1 Byte 01: 4 Bytes 10: 8 Bytes 11: Setting disabled Transmit FIFO Reset (Default: 0) The Transmit FIFO buffer is reset when this bit is set. This bit is valid when the FIFO Reset Enable bit (FRSTE) is set. Cancel reset by using the software to clear this bit. 0: During operation 1: Reset Transmit FIFO Receive FIFO Reset (Default: 0) The Receive FIFO buffer is reset when this bit is set. This bit is valid when the FIFO Reset Enable bit (FRSTE) is set. Cancel reset by using the software to clear this bit. 0: During operation 1: Reset Receive FIFO FIFO Reset Enable (Default: 0) This field is the Reset Enable for the Transmit/Receive FIFO buffer. The FIFO is reset by combining the Transmit FIFO Reset bit (TFRST) and Receive FIFO Reset bit (RFRST). 0: During operation 1: Reset Enable Read/Write ⎯ R/W 14:9 8:7 ⎯ RDIL Reserved Receive FIFO Request Trigger Level ⎯ R/W 6:5 4:3 ⎯ TDIL Reserved Transmit FIFO Request Trigger Level ⎯ R/W 2 TFRST Transmit FIFO Reset R/W 1 RFRST Receive FIFO Reset R/W 0 FRSTE FIFO Reset Enable R/W Figure 11.4.5 FIFO Control Register 11-20 Chapter 11 Serial I/O Port 11.4.6 Flow Control Register 0 (SIFLCR0) Flow Control Register 1 (SIFLCR1) 0xF314 (Ch. 0) 0xF414 (Ch. 1) 16 Reserved : Type : Initial value 15 Reserved 13 12 RCS R/W 0 11 TES R/W 0 10 9 8 7 6 5 4 RTSTL R/W 0001 1 0 TBRK R/W : Type 0 : Initial value 31 Reserved R TSSC RSDE TSDE R/W 1 R/W 1 Reserved R/W 0 Bit 31:13 12 Mnemonic RCS Field Name Reserved RTS Signal Control Select Description RTS Control Select (Default: 0) This field sets the reception flow control using RTS output signals. 0: Disable flow control using RTS signals. 1: Enable flow control using RTS signals. CTS Control Select (Default: 0) This field sets the transmission flow control using CTS input signals. 0: Disable flow control using CTS signals. 1: Enable flow control using CTS signals. RTS Software Control (Default: 0) This register is used for software control of RTS output signals. 0: Set the RTS signal to Low (can receive data). 1: Sets the RTS signal to High (transmission pause request) Receive Serial Data Disable (Default: 1) This is the Serial Data Disable bit. When this bit is cleared, data reception starts after the start bit is detected. The RTS signal will not become High even if this bit is cleared. 0: Enable (can receive data) 1: Disable (halt reception) Transmit Serial Data Disable (Default: 1) This is the Serial Data Transmission Disable bit. When this bit is cleared, data transmission starts. When set, transmission stops after completing transmission of the current frame. 0: Enable (can transmit data) 1: Disable (halt transmission) RTS Trigger Level (Default: 0001) The RTS hardware control assert level is set by the reception data stage count of the Receive FIFO. 0000: Disable setting 0001: 1 : 1111: 15 Break Transmit (Default: 0) Transmits a break. The TXD signal is Low while TBRK is set to “1”. 0: Disable (clear break) 1: Enable (transmit break) Read/Write ⎯ R/W 11 TES CTS Signal Control Select R/W 10 9 RTSSC Reserved RTS Software Control R/W ⎯ 8 RSDE Serial Data Reception Disable R/W 7 TSDE Serial Data Transmit Disable R/W 6:5 4:1 RTSTL Reserved RTS Active Trigger Level R/W ⎯ 0 TBRK Break Transmission R/W Figure 11.4.6 Flow Control Register 11-21 Chapter 11 Serial I/O Port 11.4.7 Baud Rate Control Register 0 (SIBGR0) Baud Rate Control Register 1 (SIBGR1) 0xF318 (Ch. 0) 0xF418 (Ch. 1) 16 Reserved : Type : Initial value 15 Reserved 10 9 BCLK R/W 11 8 7 BRD R/W 0xFF : Type : Initial value 0 These registers select the clock that is provided to the baud rate generator and set the divide value. 31 Bit 31:10 9:8 Mnemonic BCLK Field Name Reserved Baud Rate Generator Clock Description Baud Rate Generator Clock (Default: 11) This field sets the input clock for the baud rate generator. 00: Select prescalar output T0 (fc/2) 01: Select prescalar output T2 (fc/8) 10: Select prescalar output T4 (fc/32) 11: Select prescalar output T6 (fc/128) Baud Rate Divide Value (Default: 0xFF) This field set divide value BRG of the baud rate generator. This value is expressed as a binary value. Read/Write ⎯ R/W 7:0 BRD Baud Rate Divide Value R/W Figure 11.4.7 Baud Rate Control Register 11-22 Chapter 11 Serial I/O Port 11.4.8 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0) Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller. • • 31 Reserved : Type : Initial value 15 Reserved 8 7 TxD W ⎯ : Type : Initial value 0 Little Endian: Big Endian: 0xF31C (Ch.0), 0xF41C (Ch.1) 0xF31F (Ch.0), 0xF41F (Ch.1) 16 Bit 31:8 7:0 Mnemonic TxD Field Name Reserved Transmission Data Description Transmit Data Data written to this register are written to the Transmit FIFO. Read/Write ⎯ W Figure 11.4.8 Transmit FIFO Register 11-23 Chapter 11 Serial I/O Port 11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0) Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1) When using the DMA Controller to perform DMA transmission, set the following addresses in the Destination Address Register (DMDARn) of the DMA Controller according to the Endian Mode bit (DMCCRn.LE) setting of the DMA Controller. • • 31 Reserved : Type : Initial value 15 Reserved 8 7 RxD R Undefined : Type : Initial value 0 Little Endian: Big Endian: 0xF320 (Ch.0), 0xF420 (Ch.1) 0xF323 (Ch.0), 0xF423 (Ch.1) 16 Bit 31:8 7:0 Mnemonic RxD Field Name Reserved Reception Data Description Receive Data This field reads reception data from the Receive FIFO. Reading this register updates the Reception Data Status. Read/Write ⎯ R Figure 11.4.9 Receive FIFO Register 11-24 Chapter 12 Timer/Counter 12. Timer/Counter 12.1 Features The TX4938 has an on-chip 3-channel timer/counter. • • • • • • • 32-bit Up Counter: 3 Channels Interval Timer Mode (Channel 0, 1, 2) Pulse Generator Mode (Channel 0, 1) Watchdog Timer Mode (Channel 2) Timer Output Signal (TIMER[1:0]) × 2 Counter Input Signal (TCLK): × 1 Watchdog Timer Reset Output (WDRST*): × 1 12-1 Chapter 12 Timer/Counter 12.2 Block Diagram TX4938 IM-Bus I/F Signal Counter Input Clock Timer Interrupt 0 IM-Bus I/F Signal Counter Input Clock Timer Interrupt 1 IM-Bus I/F Signal Counter Input Clock Timer Interrupt 2 NMI* Internal Reset Chip Configuration Register (CCFG.WR) Timer-0 Interval Timer Mode TIMER[0] Timer-1 Pulse Generator Mode Interval Timer Mode TIMER[1] Timer-2 Interval Timer Mode Watchdog Timer Mode Selector TCLK Figure 12.2.1 Connecting Timer Module Inside the TX4938 IM-Bus Register R/W Control Logic Timer Timer Read Register Reset Signal Clock Signal Clock Divider x1/21/256 32-bit Counter Clock Select Compare Register A Compare Register B Clear Interval Mode Reg. Pulse Gen. Mode Reg. Watchdog Mode Reg. Timer Control Register Comparator (=) TIMER[1:0] Interrupt Control Logic Timer Interrupt Request Signal (Internal Signal) Watchdog Request Signal (Internal Signal) Interrupt Control Register Figure 12.2.2 Timer Internal Block Diagram 12-2 Chapter 12 Timer/Counter 12.3 Detailed Explanation 12.3.1 Overview The TX4938 has an on-chip 3-channel 32-bit timer/counter. Each channel supports the following modes. (1) Interval Timer Mode (Timer 0, 1, 2) This mode periodically generates interrupts. (2) Pulse Generator Mode (Timer 0, 1) This is the pulse signal output mode. (3) Watchdog Timer Mode (Timer 2) This mode is used to monitor system abnormalities. 12.3.2 Counter Clock The clock used for counting can be set to a frequency that is 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, or 1/256 of the internal clock (IMBUSCLK) frequency, or can be selected from nine counter input signal (TCLK) types. Divide Register n (TMCCDRn) and the Counter Clock Select bit (TMTCRn.CCS) are used to select the counter clock. In this situation, IMBUSCLK is the internal clock signal which is the G-Bus clock divided by 2. See “Chapter 6 Clocks” for more information. The counter input signal (TCLK) is used by three channels. Using TCLK makes it possible to count external events. The External Clock Edge bit (TMTCRn.ECES) can be used to select the clock rising/falling count. Set the TCLK clock frequency to 45% or less of IMBUSCLK (TCLK = 27 MHz or less when IMBUSCLK = 60 MHz). The following tables shows example count times when using 60 MHz or 66 MHz IMBUSCLK. Table 12.3.1 Divide Value and Count (IMBUSCLK = 60 MHz) Divide Rate 2 4 8 16 32 64 128 256 TMCCDRn. CCD 000 001 010 011 100 101 110 111 Counter Clock Frequency (Hz) 30.0 M 15.0 M 7.5 M 3.75 M 1.9 M 937.5 K 468.8 K 234.4 K Resolution (ns) 33.33 66.67 133.33 266.67 533.33 1066.67 2133.33 4266.67 Max. Set Time TMCPRAn Value (sec.) for 1 sec. 143.17 286.33 572.66 1145.32 2290.65 4581.30 9162.60 18325.20 30000000 15000000 7500000 3750000 1875000 937500 468750 234375 12-3 Chapter 12 Timer/Counter Table 12.3.2 Divide Value and Count (IMBUSCLK = 66 MHz) Divide Rate 2 4 8 16 32 64 128 256 TMCCDRn. CCD 000 001 010 011 100 101 110 111 Counter Clock Frequency (Hz) 33.0 M 16.5 M 8.3 M 4.1 M 2.1 M 1031.3 K 515.6 K 257.8 K Resolution (ns) 30.30 60.61 121.21 242.42 484.85 969.70 1939.39 3878.79 Max. Set Time TMCPRAn Value (sec.) for 1 sec. 130.15 260.30 520.60 1041.20 2082.41 4164.82 8329.63 16659.27 33000000 16500000 8250000 4125000 2062500 1031250 515625 257813 12.3.3 Counter Each channel has an independent 32-bit counter. Set the Timer Count Enable bit (TMTCRn.TCE) and the 32-bit counter will start counting. Clear the Timer Count Enable bit to stop the counter. If the Counter Reset Enable bit (TMTCRn.CRE) is set, then the counter will be cleared also. The Watchdog Timer Disable bit (TMWTRM2.WDIS) must be set in order to stop and clear this counter when in the Watch Dog Timer mode. Also, reading the Timer Read Register (TMTRR) makes it possible to fetch the counter value. 12.3.4 Interval Timer Mode The Interval Timer mode is used to periodically generate interrupts. Setting the Timer Mode field (TMTCRn.TMODE) of the Timer Control Register to “00” sets the timer to the Interval Timer mode. This mode can be used by all timers. When the count value matches the value of Compare Register A (TMCPRAn), the Interval Timer TMCPRA Status bit (TMTISRn.TIIS) of the Timer Interrupt Status Register is set. When the Interval Timer Interrupt Enable bit (TMITMRn.TIIE) of the Interval Timer Mode Register is set, timer interrupts occur. When a “0” is written to the Interval Timer TMCPRA Status bit (TMTISRn.TIIS), TIIS is cleared and timer interrupts stop. If the Timer Zero Clear Enable bit (TMITMRn.TZCE) is set, the counter is cleared to 0 if the count value matches the Compare Register A (TMCPRAn) value. Count operation stops when the Timer Zero Clear Enable bit (TMITMRn.TZCE) is cleared. The level of the TIMER[1:0] output signal stays in the initial state (Low) in this mode. Output is undefined when changing from the Pulse Generator mode to this mode. Figure 12.3.1 shows an outline of the count operation and generation of interrupts when in the Interval Timer mode and Figure 12.3.2 shows the operation when using an external input clock. 12-4 Chapter 12 Timer/Counter Count Value TMCPRA Reg. Compare Value 0x000000 Time TCE = 0 TCE = 1 TCE = 0 TCE = 1 TCE = 0 TCE = 1 CRE = 1 CRE = 0 CRE = 0 TZCE = 1 TZCE = 0 TZCE = 1 TIIE = 1 TIIE = 0 TIIE = 1 Timer Interrupt* TIIS = 0 TIIS = 0 TIIS = 0 TIIS = 0 TMODE = 00 (Interval Timer Mode), CCS = 0 (Internal Clock) Figure 12.3.1 Operation Example of Interval Timer (Using Internal Clock) Count Value TMCPRA Reg. Compare Value 0x000000 TCE = 1 TIIE = 1 TCE = 0 TCE = 1 TIIE = 0 Time TCLK Interrupt* TIIS = 1 TMODE = 00 (Interval Timer Mode), CCS = 0 (External Clock), ECES = 0 (Falling Edge) CRE = 0 (Counter Reset Disable), TZCE = 1 (Zero Clear Enable) Figure 12.3.2 Operation Example of the Interval Timer (External Input Clock: Rising Edge Operation) 12-5 Chapter 12 Timer/Counter 12.3.5 Pulse Generator Mode When in the Pulse Generator mode, use Compare Register A (TMCPRAn) and Compare Register B (TMCPRBn) to output a particular period and particular duty square wave to the TIMER[n] signal. Setting the Timer Mode field (TMTCRn.TMODE) of the Timer Control Register to “01” sets the timer to the Pulse Generator mode. Timer 0 and Timer 1 can be used, but Timer 2 cannot. The initial state of the TIMER[n] signal can be set by the Flip Flop Default bit (TMPGMRn.FFI) of the Pulse Generator Mode Register. The TIMER[n] output signal reverses when the counter value matches the value set in Compare Register A (TMCPRAn). The TIMER[n] output signal reverse again, clearing the counter when the counter continues counting and the value set in Compare Register B (TMCPRBn) and the counter value match. Consequently, a value greater than that in Compare Register A (TMCPRAn) must not be set in Compare Register B (TMCPRBn). Interrupts can be generated in the Pulse Generator mode as well. However, this is not standard practice. The Pulse Generator TMCPRA Status bit (TMTISRn.TPIAS) of the Timer Interrupt Status Register is set when the count value matches the value of Compare Register A (TMCPRAn). Timer interrupts are generated when the TMCPRA Interrupt Enable bit (TMPGMRn.TPIAE) of the Pulse Generator Mode Register is set. Similarly, the Pulse Generator TMCPRB Status bit (TMTISRn.TPIBS) of the Timer Interrupt Status Register is set when the count value matches the value of Compare Register B (TMCPRBn). Timer interrupts are generated when the TMCPRB Interrupt Enable bit (TMPGMRn.TPIBE) of the Pulse Generator Mode Register is set. Count Value TMCPRBn Compare Value TMCPRAn Compare Value 0x000000 TCE = 1 TCE = 0 TCE = 1 Time TIMER[n] TMODE1 = 01 (Pulse Generator Mode), CCS= 0 (Internal Clock) FFI = 1 (Initial High), CRE = 0 (Counter Reset Disable) Figure 12.3.3 Operation Example of the Pulse Generator Mode 12-6 Chapter 12 Timer/Counter 12.3.6 Watchdog Timer Mode The Watchdog Timer mode is used to monitor system anomalies. The software periodically clears the counter and judges an anomaly to exist if the counter is not cleared within a specified period of time. Then, either the TX4938 is internally reset or an NMI is signaled to the TX49/H3 core. Set the Timer mode field (TMTCR2.TMODE) of the Timer Control Register to “10” to set the timer to the Watchdog Timer mode. This mode can only be used by Timer 2. Use the Watchdog Reset bit (WR) of the Chip Configuration Register (CCFG) to select whether to perform an internal reset or signal an NMI. Set this bit to “1” to select Watchdog Reset, or set it to “0” to select NMI Signaling. When the timer count reaches the value programmed in Compare Register A (TMCPRA2), the Watchdog Timer TMCPRA Match Status bit in the Timer Interrupt Status Register (TMTISR2.TWIS) is set. Either the watchdog timer reset or NMI is issued if the Timer Watchdog Enable bit in the Watchdog Timer Mode Register (TMWTMR2.TWIE) is set. When the watchdog timer reset is selected, the Watchdog Reset Status bit in the Chip Configuration Register (CCFG.WDRST) is set. If the Watchdog Reset External Output bit in the Chip Configuration Register (CCFG.WDREXEN) is cleared, the entire TX4938 is initialized but the configuration registers. Setting the Watchdog Reset External Output bit (CCFG.WDREXEN) causes the WDRST* signal to be asserted. This does not initialize the TX4938. The WDRST* signal remains asserted until the RESET* signal is asserted. Assertion of the RESET* signal deasserts the WDRST* signal and initializes the TX4938. There are three ways of stopping NMI signaling from being performed. 1. 2. 3. Clear the Watchdog Timer Interrupt Status bit (TMTISR2.TWIS) of the timer Interrupt Status Register. Clear the counter by writing “1” to the Watchdog Timer Clear bit (TMWTMR2.TWC) of the Watchdog Timer Mode Register. Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.TWIE) while the Watchdog Timer Disable bit (TMWTMR2.WDIS) is still set. It is possible to stop the counter when in the Watchdog Timer mode by clearing the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control Register while the Watchdog Timer Disable bit (TMWTMR2.WDIS) of the Watchdog Timer Mode Register is set to “1”. It is also possible to stop the counter by clearing the Counter Clock Divide Cycle Enable bit (TMTCR2.CCDE) of the Timer Control Register when the internal clock is being used as the counter clock. It is not possible to directly write “0” to the Watchdog Timer Disable bit (TMWTMR2.WDIS). There are two ways to clear this bit. 1. 2. Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.WDIS) Clear the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control Register 12-7 Chapter 12 Timer/Counter In Watchdog Timer mode, the TIMER[1:0] outputs remain at logic high. Count Value TMCPRA2 Compare Value 0x000000 TCE = 1 TCE = 0 TCE = 1 TWC = 1 TWC = 1 TWC = 1 TWIE = 0 TWIE = 0 TWIE = 1 TWIE = 1 TWIS = 1 TWIS = 1 TWIS = 0 TWIS = 1 Internal Reset Signal or Internal NMI Signal Watchdog Timer Disable Bit (TMWTMR2.WDIS) TMODE = 10 (Watch Dog Timer Mode), CRE = 0 (Counter Reset Disable) WDIS = 1 WDIS = 1 Time Figure 12.3.4 Operation Example of the Watchdog Timer Mode 12-8 Chapter 12 Timer/Counter 12.4 Registers Table 12.4.1 Timer Register List Offset Address Time 0 (TMR0) 0xF000 0xF004 0xF008 0xF00C 0xF010 0xF020 0xF030 0xF040 0xF0F0 Timer 1 (TMR1) 0xF100 0xF104 0xF108 0xF10C 0xF110 0xF120 0xF130 0xF140 0xF1F0 Timer 2 (TMR2) 0xF200 0xF204 0xF208 0xF20C 0xF210 0xF220 0xF230 0xF240 0xF2F0 TMTCR2 TMTISR2 TMCPRA2 TMCPRB2 TMITMR2 TMCCDR2 TMPGMR2 TMWTMR2 TMTRR2 Timer Control Register 2 Timer Interrupt Status Register 2 Compare Register A 2 (Reserved) Interval Timer Mode Register 2 Divide Cycle Register 2 (Reserved) Watchdog Timer Mode Register 2 Timer Read Register 2 TMTCR1 TMTISR1 TMCPRA1 TMCPRB1 TMITMR1 TMCCDR1 TMPGMR1 TMWTMR1 TMTRR1 Timer Control Register 1 Timer Interrupt Status Register 1 Compare Register A 1 Compare Register B 1 Interval Timer Mode Register 1 Divide Cycle Register 1 Pulse Generator Mode Register 1 (Reserved) Timer Read Register 1 TMTCR0 TMTISR0 TMCPRA0 TMCPRB0 TMITMR0 TMCCDR0 TMPGMR0 TMWTMR0 TMTRR0 Timer Control Register 0 Timer Interrupt Status Register 0 Compare Register A 0 Compare Register B 0 Interval Timer Mode Register 0 Divide Cycle Register 0 Pulse Generator Mode Register 0 (Reserved) Timer Read Register 0 Register Symbol Register Name 12-9 Chapter 12 Timer/Counter 12.4.1 Timer Control Register n (TMTCRn) TMTCR0 TMTCR1 TMTCR2 0xF000 0xF100 0xF200 16 Reserved : Type : Initial value 15 Reserved 8 7 TCE R/W 0 6 CCDE R/W 0 5 CRE R/W 0 4 Reserved 31 3 ECES R/W 0 2 CCS R/W 0 1 0 TMODE R/W 00 : Type : Initial value Bit 31:8 7 Mnemonic TCE Field Name Reserved Timer Counter Enable Description Timer Count Enable (Default: 0) This field controls whether the counter runs or stops. When in the Watchdog mode, counter operation only stops when the Watchdog Timer Disable bit (TMWTMR2.WDIS) of the Watchdog Timer Mode Register is set. When the Watchdog Timer Disable bit is cleared, the value of this Timer Count Enable bit becomes “0”, but the count continues. 0: Stop counter (the counter is also cleared to “0” when CRE = 1) 1: Counter operation Counter Clock Divide Enable (Default: 0) This bit enables the divide operation of the internal clock (IMBUSCLK). The counter stops if this bit is set to “0” when the internal bus clock is in use. 0: Disable 1: Enable Counter Reset Enable (Default: 0) This bit controls the counter reset when the TCE bit was used to stop the counter. During CRE = 1, reset the counter if TCE is set from 1 to 0. During TCE = 0, the counter isn’t reset if CRE is set from 0 to 1. When TCE = 1 and CRE = 0, stop and reset the counter if TCE is set to 0 and CRE is set to 1 simultaneously. 1: Stop and reset the counter to “0” when the TCE bit is cleared to “0”. 0: Only stop the counter when the TCE bit is cleared to “0”. External Clock Edge Select (Default: 0) This bit specifies the counter operation edge when using the counter input signal (TCLK). 0: Falling edge of the counter input signal (TCLK) 1: Rising edge of the counter input signal (TCLK) Counter Clock Select (Default: 0) This bit specifies the timer clock. 0: Internal clock (IMBUSCLK) 1: External input clock (TCLK) Timer Mode (Default: 00) This bit specifies the timer operation mode. 11: Reserved 10: Watchdog Timer mode (Timer 2), Reserved (Timer 0, 1) 01: Pulse Generator mode (Timer 0, 1), Reserved (Timer 2) 00: Interval Timer mode Read/Write ⎯ R/W 6 CCDE Counter Clock Divider Enable R/W 5 CRE Counter Reset Enable R/W 4 3 ECES Reserved External Clock Edge Select R/W ⎯ 2 CCS Counter Clock Select R/W 1:0 TMODE Timer Mode R/W Figure 12.4.1 Timer Control Register 12-10 Chapter 12 Timer/Counter 12.4.2 Timer Interrupt Status Register n (TMTISRn) TMTISR0 TMTISR1 TMTISR2 0xF004 0xF104 0xF204 16 Reserved : Type : Initial value 15 Reserved 4 3 2 1 0 TIIS 31 TWIS TPIBS TPIAS RW0C RW0C RW0C RW0C : Type 0 0 0 0 : Initial value Bit 31:4 3 Mnemonic TWIS Field Name Reserved Watchdog Timer Status Description Read/Write ⎯ 2 TPIBS Pulse Generator TMCPRB Status 1 TPIAS Pulse Generator TMCPRA Status Watchdog Timer TMCPRA Match Status (Default: 0) R/W0C (This bit is Reserved in the case of the TMTISR0 Register and the TMTISR1 Register.) When in the Watchdog Timer mode, this bit is set when the counter value matches Compare Register 2 (TMCPRA2). This bit is cleared by writing a “0” to it. During Read 0: Did not match the Compare Register 1: Matched the Compare Register During Write 0: Negate interrupt 1: Invalid Pulse Generator TMCPRB Match Status (Default: 0) R/W0C (This bit is Reserved in the case of the TMTISR2 Register.) When in the Pulse Generator mode, this bit is set when the counter value matches Compare Register Bn (TMCPRBn). This bit is cleared by writing a “0” to it. During Read 0: Did not match the Compare Register 1: Matched the Compare Register During Write 0: Clear 1: Invalid Pulse Generator TMCPRA Match Status (Default: 0) R/W0C (This bit is Reserved in the case of the TMTISR2 Register.) When in the Pulse Generator mode, this bit is set when the counter value matches Compare Register A n (TMCPRAn). This bit is cleared by writing a “0” to it. During Read 0: Did not match the Compare Register 1: Matched the Compare Register During Write 0: Clear 1: Invalid Interval Timer TMCPRA Match Status (Default: 0) When in the Interval Timer mode, this bit is set when the counter value matches Compare Register A n (TMCPRAn). This bit is cleared by writing a “0” to it. During Read 0: Did not match the Compare Register 1: Matched the Compare Register During Write 0: Clear 1: Invalid R/W0C 0 TIIS Interval Timer TMCPRA Status Figure 12.4.2 Timer Interrupt Status Register 12-11 Chapter 12 Timer/Counter 12.4.3 Compare Register An (TMCPRAn) TMCPRA0 0xF008 TMCPRA1 0xF108 TMCPRA2 0xF208 16 TCVA R/W 0xFFFF 15 TCVA R/W 0xFFFF : Type : Initial value 0 : Type : Initial value 31 Bits 31:0 Mnemonic TCVA Field Name Timer Compare Register A Description Timer Compare Value A (Default: 0xFFFFFFFF) Sets the timer compare value as a 32-bit value. This register can be used in all modes. Read/Write R/W Figure 12.4.3 Compare Register A 12-12 Chapter 12 Timer/Counter 12.4.4 Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C TMCPRB1 0xF10C 16 TCVB R/W 0xFFFF 15 TCVB R/W 0xFFFF : Type : Initial value 0 : Type : Initial value 31 Bits 31:0 Mnemonic TCVB Field Name Timer Compare Value B Description Timer Compare Value B (Default: 0xFFFFFFFF) Sets the timer compare value as a 32-bit value. This register can only be used when in the Pulse Generator mode. Please set a value greater than that in Compare Register A. Read/Write R/W Figure 12.4.4 Compare Register B 12-13 Chapter 12 Timer/Counter 12.4.5 Interval Timer Mode Register n (TMITMRn) TMITMR0 0xF010 TMITMR1 0xF110 TMITMR2 0xF210 16 Reserved : Type : Initial value 15 TIIE R/W 0 14 Reserved 1 0 TZCE R/W : Type : Initial value 0 31 Bit 31:16 15 Mnemonic TIIE Field Name Reserved Interval Timer Interrupt Enable Description Timer Interval Interrupt Enable (Default: 0) Sets Interval Timer TMCPRA Interrupt Enable/Disable. 0: Disable (mask) 1: Enable Interval Timer Zero Clear Enable (Default: 0) This bit specifies whether or not to clear the counter to “0” after the count value matches Compare Register A. Count stops at this value if it is not cleared. 0: Do not clear 1: Clear Read/Write ⎯ R/W 14:1 0 TZCE Reserved Interval Timer Clear Enable R/W ⎯ Figure 12.4.5 Interval Timer Mode Register 12-14 Chapter 12 Timer/Counter 12.4.6 Divide Register n (TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 16 Reserved : Type : Initial value 15 Reserved 3 2 CCD R/W 000 : Type : Initial value 0 31 Bits 31:3 2:0 Mnemonic CCD Field Name Reserved Counter Clock Divide Value Description Counter Clock Divide (Default: 000) These bits specify the divide value when using the internal clock (IMBUSCLK) as the counter input clock source. The binary value n is divided by 2n+1. 000: Divide by 21 (f/2) 001: Divide by 22 (f/4) 010: Divide by 23 (f/8) 011: Divide by 24 (f/16) 100: Divide by 25 (f/32) 101: Divide by 26 (f/64) 110: Divide by 27 (f/128) 111: Divide by 28 (f/256) Read/Write ⎯ R/W Figure 12.4.6 Divide Register 12-15 Chapter 12 Timer/Counter 12.4.7 Pulse Generator Mode Register n (TMPGMRn) TMPGMR0 0xF000 TMPGMR1 0xF130 16 Reserved : Type : Initial value 15 14 13 Reserved 1 0 FFI R/W : Type : Initial value 0 31 TPIBE TPIAE R/W 0 R/W 0 Bit 31:16 15 Mnemonic TPIBE Field Name Reserved TMCPRB Interrupt Enable Description Timer Pulse Generator Interrupt by TMCPRB Enable (Default: 0) When in the Pulse Generator mode, this bit sets Interrupt Enable/Disable for when TMCPRB and the counter value match. 0: Mask 1: Do not mask Timer Pulse Generator Interrupt by TMCPRA Enable (Default: 0) When in the Pulse Generator mode, this bit sets Interrupt Enable/Disable for when TMCPRA and the counter value match. 0: Mask 1: Do not mask Initial TIMER Output Level (Default: 0) This bit specifies the TIMER[n] signal default when in the Pulse Generator mode. 0: Low 1: High Read/Write ⎯ R/W 14 TPIAE TMCPRA Interrupt Enable R/W 13:1 0 FFI Reserved Flip Flop Default R/W ⎯ Figure 12.4.7 Pulse Generator Mode Register 12-16 Chapter 12 Timer/Counter 12.4.8 31 Reserved : Type : Initial value 15 TWIE R/W 0 14 Reserved 8 7 WDIS RW1S 0 6 0 1 0 TWC R/W1C : Type : Initial value 0 Watchdog Timer Mode Register n (TMWTMRn) TMWTMR2 0xF240 16 Bit 31:16 15 Mnemonic TWIE Field Name Reserved Watchdog Timer Signaling Enable Description Timer Watchdog Enable (Default: 0) This bit sets NMI signaling enable/disable either when in the Watchdog Timer mode or during a reset. This bit cannot be cleared when the Watchdog Timer Disable bit (WDIS) is “0”. 0: Disable (mask) 1: Enable Watchdog Timer Disable (Default: 0) Only when this bit is set can the counter be stopped by clearing the Watchdog Timer Signaling Enable bit (TWIE) or by clearing the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control Register. Writing “0” to this bit is not valid. This bit can be cleared in either of the following ways. Clear the Watchdog Timer Interrupt Enable bit (TMWTMR2.TWIE). Clear the Timer Counter Enable bit (TMTCR2.TCE) of the Timer Control Register. Watchdog Timer Clear (Default: 0) Setting this bit to “1” clears the counter. Writing “0” to this bit is not valid. This bit is always read as “0”. Read/Write ⎯ R/W 14:8 7 W DIS Reserved Watchdog Timer Disable ⎯ R/W1S 6:1 0 TWC Reserved Watchdog Timer Clear ⎯ R/W1C Figure 12.4.8 Watchdog Timer Mode Register 12-17 Chapter 12 Timer/Counter 12.4.9 Timer Read Register n (TMTRRn) 0xF0F0 TMTRR0 TMTRR1 TMTRR2 0xF0F0 0xF1F0 0xF2F0 16 TCNT R 0x0000 15 TCNT R 0x0000 : Type : Initial value 0 : Type : Initial value 31 Bits 31:0 Mnemonic TCNT Field Name Timer Counter Description Timer Counter (Default: 0x00000000) This Read Only register is a 32-bit counter. Operation when this register is written to is undefined. Read/Write R Figure 12.4.9 Timer Read Register 0 12-18 Chapter 13 Parallel I/O Port 13. Parallel I/O Port 13.1 Characteristics The TX4938 on-chip Parallel I/O port (PIO) is a 16-bit general-purpose parallel port. The input/output direction and the port type during output (totem pole output/open drain output) can be set for each bit. 13.2 Block Diagram 8 SDRAMC CB[7:0] ADDR[18] (SEL1) IM-Bus PIO Input Data Register 8 PIO[7:0] 8 CB[7:0]/PIO[15:8] Output Data Register 8 Direction Control Register OD Control Register 8 Figure 13.2.1 Parallel I/O Block Diagram 13-1 Chapter 13 Parallel I/O Port 13.3 Detailed Description 13.3.1 Selecting PIO Pins Of the 16-bit PIO signals, signals PIO[15:8] can be used in combination with 8-bit ECC check bit signals. The configuration signal (ADDR[18]) at boot up determines which function will be used. See “3.2 Boot Configuration” for more information. 13.3.2 General-purpose Parallel Port The four following registers are used to control the PIO port. • • • • PIO Output Data Register (PIODO) PIO Input Data Register (PIODI) PIO Direction Control Register (PIODIR) PIO Open Drain Control Register (PIOOD) PIO signals can be selected by the PIO Direction Control Register (PIODIR) for each bit as either input or output. Signals selected as output signals output the values written into the PIO Data Output Register (PIODO). The PIO Open Drain Control Register (PIOOD) can select whether each bit is either an open drain output or a totem pole output. PIO signal status is indicated by the PIO Data Input Register. This register can be read out at any time regardless of the pin direction settings. 13.4 Registers Table 13.4.1 PIO Register Map Offset Address 0xF500 0xF504 0xF508 0xF50C Mnemonic PIODO PIODI PIODIR PIOOD Output Data Register Input Data Register Register Name Direction Control Register Open Drain Control Register 13-2 Chapter 13 Parallel I/O Port 13.4.1 31 Reserved :Type :Initial value 15 14 13 12 11 10 9 8 PDO R/W 0x0000 :Type :Initial value 7 6 5 4 3 2 1 0 PIO Output Data Register (PIODO) 0xF500 16 Bit 31:16 15 :0 Mnemonic PDO [15:0] Field Name Reserved Data Out Description Port Data Output [15:0] (Initial value:0x0000) Data that is output to the PIO pin (PIO [15:0]). Read/Write ⎯ R/W Figure 13.4.1 PIO Output Data Register 13.4.2 31 PIO Input Data Register (PIODI) 0xF504 16 Reserved :Type :Initial value 15 14 13 12 11 10 9 8 PDI R Undefined :Type :Initial value 7 6 5 4 3 2 1 0 Bit 31:16 15 :0 Mnemonic PDI [15:0] Field Name Reserved Data In Description ⎯ Port Data Input [15:0] (Initial value:TBD) Data that is input to the PIO pin (PIO [15:0]). R Figure 13.4.2 PIO Input Data Register 13-3 Chapter 13 Parallel I/O Port 13.4.3 31 Reserved :Type :Initial value 15 14 13 12 11 10 9 8 PDIR R/W 0x0000 :Type :Initial value 7 6 5 4 3 2 1 0 PIO Direction Control Register (PIODIR) 0xF508 16 Bit 31:16 15 :0 Mnemonic PDIR [15:0] Field Name Reserved Direction Control Description Port Direction Control [15:0] (Initial value: 0x0000) Sets the I/O direction of the PIO pin (PIO [15:0]). 0: Input (Reset) 1: Output Read/Write ⎯ R/W Figure 13.4.3 PIO Direction Control Register 13.4.4 31 PIO Open Drain Control Register (XPIOOD) 0xF50C 16 Reserved :Type :Initial value 15 14 13 12 11 10 9 8 POD R/W 0x0000 :Type :Initial value 7 6 5 4 3 2 1 0 Bit 31:16 15 :0 Mnemonic POD [15:0] Field Name Reserved Open Drain Control Description Port Open Drain Control [15:0] (Initial value: 0x0000) Sets whether to use the PIO pin (PIO [15:0]) as an open drain. 0: Open drain (Reset) 1: Totem pole Read/Write ⎯ R/W Figure 13.4.4 PIO Open Drain Control Register 13-4 Chapter 14 AC-link Controller 14. AC-link Controller 14.1 Features ACLC, AC-link controller module can be connected to audio and/or modem CODECs described in the “Audio CODEC ’97 Revision 2.1” (AC’97) defined by Intel and can operate them. Refer to the following Web site for more information regarding the AC’97 specification. http://developer.intel.com/ial/scalableplatforms/audio/ Its features are summarized as follows. • • • • • • • • • • • Up to two CODECs are supported. AC’97 compliant CODEC register access protocol is supported. CODEC register access completion is recognized by polling or interrupt. Recording and playback of 16-bit PCM Left&Right channels are supported. Recording can be selected from PCM L&R or Mic. Playback of 16-bit Surround, Center, and LFE channels is supported. Variable Rate Audio recording is supported. Variable Rate Audio playback is supported. Line 1 and GPIO slots for Modem CODEC are supported. AC-link low-power mode, wake-up, and warm-reset are supported Sample-data I/O via DMA transfer is supported. 14-1 Chapter 14 AC-link Controller 14.2 Configuration Figure 14.2.1 illustrates the ACLC configuration. DMAC IM-bus aclcimbif Bus I/F aclc Data I/O Master Slave Register Wakeup Control System-side (imclk / imreset* ) Asynchronous Handshake Slot-data Transfer Slot Valid/Req & Register Access Link-side (BITCLK / ACRESET* ) Bitstream Receive & Transmit AC-link Figure 14.2.1 ACLC Module Configuration 14-2 Chapter 14 AC-link Controller 14.3 Functional Description ACLC provides four mechanisms to operate AC’97-compliant CODEC(s): • • • • AC-link status control (start-up and low-power mode) CODEC register access Sample-data transmission and reception GPIO operation This section first describes the CODEC connection, chip configuration, and overall usage-flow. Then AClink start-up sequence and the other mechanisms will be described. Using low-power mode comes last. 14.3.1 CODEC Connection The ACLC module has two SDIN (named as SDATA_IN in the AC’97 specification) signals and supports up to two CODECs to be connected. This section shows some system configuration diagrams for typical usages. Note that the diagrams shown here is intended to provide conceptual understanding and some components may be necessary on the actual circuit board to ensure proper electrical signals. The diagrams assume CODECs compliant with the CODEC ID strapping recommendation described in the section D.5.2 of the AC’97 revision 2.1 specification. 14.3.1.1 Stereo Audio and Optional Modem Connection ACLC SYNC BITCLK SDOUT ACRESET* SDIN0 SDIN1 Audio CODEC (CODEC ID=‘00’) SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN CID1 CID0 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN CID1 CID0 GND Optional Modem CODEC (CODEC ID=’01’) Figure 14.3.1 Stereo Audio and Optional Modem Connection Diagram 14-3 Chapter 14 AC-link Controller 14.3.1.2 5.1 Channel Audio Connection This sample assumes one CODEC with four DACs mapped to stereo front (3&4) and stereo rear (7&8) slots, and another CODEC with two DACs mapped to center (6) and LFE (9) slots. ACLC SYNC BITCLK SDOUT ACRESET* SDIN0 SDIN1 4Channel Audio CODEC (CODEC ID=’0’) SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN CID1 CID0 SYNC BIT_CLK SDATA_OUT RESET# SDATA_IN CID1 CID0 GND 2Channel Audio CODEC (CODEC ID=‘3’) Figure 14.3.2 5.1 Channel Audio Connection Diagram 14.3.2 Boot Configuration To utilize ACLC, the CPU must boot up with ACLC enabled by setting Pin Configuration Register’s Shared Pin Select2 via the boot configuration. Refer to the sections 3.2 and 5.2.3 for the detail of the boot configuration. 14-4 Chapter 14 AC-link Controller 14.3.3 Usage Flow This section outlines a process flow when using the AC’97 connected to ACLC. Refer to the subsequent sections for the details of each operation performed in this process flow. The diagrams below describe the audio playback and recording processes. The modem transmission and reception can be done in a similar way. System Software Enable ENLINK Deassert ACRESET* Start BITCLK ACLC and DMAC AC’97 Set CODEC Ready CODECRDY Interrupt Check AC’97 status Start up AC-link DAC Ready response Register setting such as Volume (*) Set volume, etc. Setup DMA buffer Configure DMAC Start DMA Channel and enable transmit-data DMA Start transmit-data DMA Start sending data to slot Start audio playback Write to DMA buffer and update DMA descriptor (repeatedly) DMAC generates Transfer Completion interrupt (repeatedly) Stop updating DMA descriptor DMAC channel goes inactive DMA underrun error occurs Check completion status Stop transmit-data DMA Disable transmit-data DMA Stop sending data to slot Dummy write to data register to clear pending DMA request if any Stop audio playback Disable ENLINK Assert ACRESET* Stop AC-link Stop BITCLK (*) Register settings such as volume can be made during data playback. Figure 14.3.3 Audio Playback Process Flow 14-5 Chapter 14 AC-link Controller System Software Enable ENLINK ACLC and DMAC Deassert ACRESET* AC’97 Start BITCLK Set CODEC Ready Check AC’97 status CODECRDY Interrupt Start recording audio ADC Ready response Start up AC-link Register setting such as gain (*) Set gain, etc. Clear DMA buffer Configure DMAC Start DMA Channel and enable receive-data DMA Start receiving data from slot Start receive-data DMA Send sample data Read from DMA buffer and update DMA descriptor (repeatedly) DMAC generates Transfer Completion interrupt (repeatedly) Stop updating DMA descriptor DMAC channel goes inactive DMA overrun error occurs Check completion status Receive-data DMA halts Disable receive-data DMA Dummy read from data register to clear pending DMA request if any Disable ENLINK Assert ACRESET * Stop AC-link Stop BITCLK (*) Register settings such as gain can be made during data recording Figure 14.3.4 Audio Recording Process Flow 14-6 Chapter 14 AC-link Controller 14.3.4 AC-link Start Up Figure 14.3.5 shows the conceptual sequence of AC-link start-up. The ACLC Control Enable Register’s Enable AC-link bit is used to deassert/assert the ACRESET* signal to the link side (including AC-link). This bit defaults to ‘0’, so the CPU asserts the ACRESET* signal when it boots up. The AC’97 specification requires that the reset assertion period is 1µs or longer. The software is responsible for controlling the length of this period. The AC’97 specification also requires that the primary CODEC stops the AC-link clock (BITCLK) signal during the period from ACRESET* signal assertion to 162.8ns after ACRESET* signal deassertion. ACLC assumes the primary CODEC meet this requirement. Deasserting the link-side reset makes the primary CODEC start driving the BITCLK signal. When the BITCLK signal is provided, ACLC starts the SYNC signal output, which indicates the start of the AC-link frame, and starts the frame-length counting. When a CODEC becomes ready to receive access to its own register, the CODEC sets the “CODEC Ready” bit of the Tag slot. When ACLC detects that this bit has been set, the ACLC Interrupt Status Register (ACINTSTS)’s CODEC[1:0] Ready (CODEC[1:0]RDY) bit is set. The system software is able to recognize the readiness of the CODEC(s) by detecting this event by way of either polling or interrupt. In case of 5.1 channel audio connection example (Figure 14.3.2), because the secondary CODEC is connected to the SDIN1 signal of ACLC, the software must watch ACINTSTS.CODEC1RDY bit to determine the CODEC’s readiness for the register access. ACRESET* BITCLK SYNC SDIN ENLINK CODECRDY Boot up Software sets ENLINK bit CODEC becomes ready to accept register access ACLC internal clock becomes active Note: The number of BITCLK cycles relative to other signals is not to scale. Figure 14.3.5 Cold Reset and CODEC Ready Recognition 14-7 Chapter 14 AC-link Controller 14.3.5 CODEC Register Access By accessing registers in the CODEC, the system software is able to detect or control the CODEC state. This section describes how to read and write CODEC registers via ACLC. For details about AC’97 register set and proper sequence to operate CODEC, refer to the AC’97 specification and target CODEC datasheet. It takes several frame periods for a read or write access to complete. Taking this into account, ACLC is equipped with a function for reporting CODEC register access completion as status-change or interrupt. In order to read an AC’97 register, write the access destination CODEC ID and register address in ACLC CODEC Register Access Register (ACREGACC) with its CODECRD bit set to “1”. After the ACLC Interrupt Status Register (ACINTSTS)’s REGACC Ready (REGACCRDY) bit is set, the software is able to get the data returned from the AC’97 by reading the ACREGACC register and issue another access. In order to write to an AC’97 register, write the access destination CODEC ID, register address, and the data in ACLC’s ACREGACC register with ACREGACC.CODECRD bit set to “0”. After the ACINTSTS.REGACCRDY bit has been set, the software is able to issue another access. In case of 5.1 channel audio connection example (Figure 14.3.2), because the secondary CODEC has CODEC ID of ‘3’, the software must write ‘3’ into ACREGACC.CODECID field when it issues secondary CODEC register access. 14-8 Chapter 14 AC-link Controller 14.3.6 Sample-data Transmission and Reception This section describes the mechanism for transmission and reception of PCM audio and modem wave-data. An overview is described first. The DMA (Direct Memory Access) operation, error detection and recovery procedure follow. A special case using slot activation control is described last. 14.3.6.1 Overview Figure 14.3.6 and Figure 14.3.7 show conceptual views of the sample-data transmission and reception mechanisms. ACLC REQ Latch DMAREQ Read DMA Buffer Data Write Data Strobe Valid Flag Data ACCTLEN FIFO ACSLTEN Linkside AC-link Slot Req Slot Valid, Slot Data Memory DMAC Underrun Error Figure 14.3.6 Sample-data Transmission Mechanism ACLC REQ Latch DMAREQ Write DMA Buffer Data Read Data Strobe Data ACCTLEN FIFO ACSLTEN Linkside AC-link Slot Valid, Slot Data Memory DMAC Overrun Error Figure 14.3.7 Sample-data Reception Mechanism The CODEC requests ACLC to transmit and receive sample-data via ‘slot-request’ and ‘slotvalid’ bit-fields on the SDIN signal of AC-link. For transmission, ACLC transmits the data with ‘slot-valid’ tag set. For reception, ACLC captures the slot-data. Transmission or reception through each stream can be independently activated or deactivated under control of ACLC Slot Enable Register (ACSLTEN). ACLC is equipped with a separate FIFO for each data-stream. The data to transmit is prefetched from memory to FIFO through DMA. The received data is buffered on FIFO and then stored to memory through DMA. In this stage, each DMA is independently activated or deactivated under control of ACLC Control Enable Register (ACCTLEN). 14-9 Chapter 14 AC-link Controller 14.3.6.2 DMA Channel Mapping ACLC uses four DMA request channels. These DMA channels are allocated to four out of seven data-streams, or slots, on the AC-link frame, according to ACLC DMA Channel Selection Register (ACDMASEL) setting as shown in Table 14.3.1. The pin configuration register allocates these DMA channels of ACLC to the DMAC (DMA controller) channels according to Pin Configuration Register (PCFG)’s DMA Request Selection (DMASEL[7:0]) bits as described in section 8.3.1. Table 14.3.1 DMA Channel Mapping Modes AC-link Slot Number PCM L&R out (3&4) Surround L&R out (7&8) Center out (6) LFE out (9) PCM L&R in (3&4) or Mic in (6) Modem Line1 out (5) Modem Line 1 in (5) ACLC ch1 ACLC ch2 ACLC ch3 ACLC ch2 ACLC ch3 ACDMASEL 0 ACLC ch0 1 ACLC ch0 ACLC ch1 2 ACLC ch0 ACLC ch1 ACLC ch2 ACLC ch3 3 ACLC ch0 ACLC ch1 ACLC ch3 ACLC ch2 14.3.6.3 Sample-data Format ACLC transmits/receives 16 bits per sample for each data slot shown in Table 14.3.1. The data resides on the first 16 bits of the 20 bits assigned to each slot on AC-link. Each sample-data register allows access by word (32-bit) unit only. Therefore the DMA count must be a multiple of word. Note that the transmit-data DMA count also must be the FIFO depth (refer to Table 14.3.8) or more for a reason described later. For audio PCM front and surround streams, every data-word is loaded with a couple of left and right samples. For audio MIC stream, valid data is loaded in the same field as the left sample while the other field is filled with ‘0’. For audio center, LFE, and modem line 1 streams, two consecutive samples are packed into every word. The data format at the sample-data register is arranged so that the data format on the DMA buffer follows the rules below. • • • Each sample data is put in the byte order in which the CPU operates (big- or little-endian). Samples are put in the time-sequential order at increasing addresses on memory. For a DMA channel which couples left and right samples, each left sample precedes the corresponding right sample. Refer to the sections 14.4.16 and later for the register format. 14-10 Chapter 14 AC-link Controller Figures below show the format of DMA buffer for each type of DMA channel. #0, #1, … means the sample’s sequential number for the AC-link slot. Subscript ‘L’ means lower 8-bit of each sample and subscript ‘H’ means upper 8-bit. Table 14.3.2 Front and Surround DMA Buffer Format in Little-endian Mode Address offset +0 +4 +8 : +0 Left#0L Left#1L Left#2L : +1 Left#0H Left#1H Left#2H : +2 Right#0L Right#1L Right#2L : +3 Right#0H Right#1H Right#2H : Table 14.3.3 Center, LFE, and Modem DMA Buffer Format in Little-endian Mode Address offset +0 +4 +8 : +0 #0L #2L #4L : +1 #0H #2H #4H : +2 #1L #3L #5L : +3 #1H #3H #5H : Table 14.3.4 Mic DMA Buffer Format in Little-endian Mode Address offset +0 +4 +8 : +0 #0L #1L #2L : +1 #0H #1H #2H : +2 0 0 0 : +3 0 0 0 : Table 14.3.5 Front and Surround DMA Buffer Format in Big-endian Mode Address offset +0 +4 +8 : +0 Left#0H Left#1H Left#2H : +1 Left#0L Left#1L Left#2L : +2 Right#0H Right#1H Right#2H : +3 Right#0L Right#1L Right#2L : Table 14.3.6 Center, LFE, and Modem DMA Buffer Format in Big-endian Mode Address offset +0 +4 +8 : +0 #0H #2H #4H : +1 #0L #2L #4L : +2 #1H #3H #5H : +3 #1L #3L #5L : Table 14.3.7 Mic DMA Buffer Format in Big-endian Mode Address offset +0 +4 +8 : +0 #0H #1H #2H : +1 #0L #1L #2L : +2 0 0 0 : +3 0 0 0 : 14-11 Chapter 14 AC-link Controller 14.3.6.4 DMA Operation When ACLC’s REQ latch (refer to Figure 14.3.6 and Figure 14.3.7) needs to read or write sample-data, it issues a DMA request. When DMAC acknowledges the request by performing write- or read-access to the ACLC sample-data register, ACLC deasserts the request. Therefore, the software must properly set up DMAC so that the source or destination points to the corresponding sample-data register for the DMA channel. Setup the DMA Channel Control Registers (DMCCRn) in DMAC as follows. Immediate chain DMA request polarity DMA acknowledge polarity Request sense Sample chain Transfer size Transfer address mode Enable Low-active Low-active Level-sensitive 1 word 1 word Dual DMCCRn.IMMCHN = 1 [Note] DMCCRn.REQPOL = 0 DMCCRn.ACKPOL = 0 DMCCRn.EGREQ = 0 DMCCRn.SMPCHN = 1 DMCCRn.XFSZ = 010b DMCCRn.SNGAD = 0 Note: Use this setting when DMA chain operation is utilized For a transmission channel, assign the address of ACLC Audio PCM Output/Surround/Center/LFE/Modem Output Register (ACAUDO/SURR/CENT/LFE/ MODODAT) to the DMAC destination address register (DMDARn). For a reception channel, assign the address of ACLC Audio input/Modem Input Register (ACAUDI/MODIDAT) to the DMAC source address register (DMSARn). When any DMA request is pending, the REQ latch will not deasserted the request until the corresponding sample-data register is accessed. Just unsetting ACLC Control Enable Register (ACCTLEN)’s DMA Enable (xxxxDMA) bit corresponding to the DMA will not clear the REQ latch. The procedure to continuously push or pull the sample-data stream through the chain DMA operation follows the DMAC specification. Refer to section 8.3.10 for this respect. 14-12 Chapter 14 AC-link Controller 14.3.6.5 Sample-data FIFO For a transmission stream, as long as ACLC Control Enable Register (ACCTLEN) allows that transmission and the FIFO has any room to fill data in, the FIFO issues a request via the REQ latch. On the other side, when a transmission FIFO receives a data-request from the link-side, it provides data with valid-flag set if it has any valid data. If it has no valid data, it responds with valid-flag unset and an underrun error bit is set. At the transmit-data DMA start-up, until the FIFO becomes full, it responds to the link-side with valid-flag unset, in order to maximize the buffering effect. Therefore, the DMA size must be the FIFO depth or more. Table 14.3.8 Transmission FIFO Depth Data-stream PCM L&R out Surround L&R out Center out LFE out Modem Line 1 out FIFO Depth (Word) 3 3 2 2 1 The link-side drives the slot-valid bit and slot-data on AC-link. When underrun occurs, these bits are driven to all ‘0’. For a reception stream, as long as the FIFO has any valid data, the FIFO issues a request via the REQ latch. On the other side, when ACCTLEN allows that reception and the link-side issues a data strobe, the FIFO stores the valid data. If the FIFO is full when it receives a data strobe, the data is discarded and an overrun error bit is set. 14.3.6.6 Error Detection and Recovery In most usages, since the CODEC continuously requests sample-data transmission and reception, after DMA is finished, underrun and overrun will occur. The procedure described below allows the software to determine whether an error has occurred during DMA operation. The software sets ACLC Control Enable Register (ACCTLEN)’s Error Halt Enable (xxxxEHLT) bit before it starts a DMA channel. After it starts the DMA channel, it waits until ACLC Interrupt Status Register (ACINTSTS)’s Underrun or Overrun Error (xxxxERR) bit is set. When the event is detected, the software checks DMA Channel Control Register (DMCCRn)’s Transfer Active (XFACT) bit and ACLC DMA Request Status Register (ACDMASTS)’s Request (xxxxDMA) bit and determines the DMA completion status as follows. Table 14.3.9 DMA Completion Status Determination DMCCRn.XFACT Inactive Inactive Active ACDMASTS.xxxxDMA Pending Not Pending * Completion Status No Error during DMA Underrun or Overrun Underrun or Overrun To recover from error, disable and enable the stream via ACCTLEN, and restart the DMA. 14-13 Chapter 14 AC-link Controller 14.3.6.7 Slot Activation Control In case ACLC is required to begin transmission or reception of multiple streams at the same time, slot activation control will be useful. To use this feature, the software must deactivate the relevant streams first, enable ACLC Control Enable Register (ACCTLEN), make sure the transmission FIFO becomes full by checking ACLC FIFO Status Register (ACFIFOSTS)’s Full (xxxxFULL) bit, and finally enable ACLC Slot Enable Register (ACSLTEN). This procedure assures that all the reception streams are activated at a frame and all the transmission streams begin to respond to the slot-request bits of that frame. Note that access to ACSLTEN and ACLC Slot Disable Register (ACSLTDIS) needs special care to synchronize with the link-side. Refer to the register description for detail. Since operating ACCTLEN register and DMAC without touching ACSLTEN is sufficient for most usages, the initial ACSLTEN value enables all the transmission and reception through the slots by default. 14.3.6.8 Variable Rate Limitation To improve compatibility with existing AC’97 CODECs and controllers on the market, ACLC combines sample-data for the slots 3 and 4 into one DMA channel, and similarly for the slots 7 and 8. This feature effectively considers that the slot request bit from the CODEC for slot 4 shall be always same (in tandem) as for slot 3 for each frame, and similarly for the slots 7 and 8. ACLC also considers that the slot valid bit from the CODEC for slot 4 shall be always same (in tandem) as for slot 3 for each frame. 14.3.7 GPIO Operation ACLC supports the slot 12 for the MC’97 (Modem Codec) GPIO. The slot 12 is shadowed in the ACLC GPI Data Register (ACGPIDAT) and ACLC GPO Data Register (ACGPODAT) in the following way: • • ACLC copies the slot 12 input data into the ACGPIDAT register, if the slot 12 input is marked by the CODEC as valid in the AC-link frame period. ACLC generates the slot 12 output data from the ACGPODAT register and mark it as valid, if the slot 12 is required from the CODEC in the previous AC-link frame. This shadowing function is enabled as long as ACSLTEN allows. The bit 0 of the slot 12 is defined as ‘GPIO_INT’ and can cause ACLC to request an interrupt. 14-14 Chapter 14 AC-link Controller 14.3.8 Interrupt ACLC generate two kinds of interrupt to the interrupt controller as below. • ACLC Interrupt Logical OR of all the valid bits of ACLC Interrupt Masked Status Register (ACINTMSTS) is connected. Refer to the section 14.4.5. • ACLCPME Interrupt This interrupt shows the wake-up from CODEC in AC-link low-power mode. Refer to the description for ACLC Control Enable Register (ACCTLEN)’s Wake-up Enable (WAKEUP) bit in section 14.4.1. 14.3.9 AC-link Low-power Mode The AC’97 specification makes provision for saving power during system suspension by poweringdown both the controller and CODEC except the minimum circuit to detect modem RING/Caller-ID event and wake up the system. AC’97 CODEC is required to go into the low-power mode when they receive a special register-write access. In this mode, the AC-link controller must drive all output signals to low level to allow the CODEC digital I/O power cut. ACLC provides ‘AC-link low-power mode’ setting. When this mode is enabled by ACLC Control Enable Register (ACCTLEN)’s Enable AC-link Low-power Mode (LOWPWR) bit, all the output signals except the ACRESET* signal to the AC-link are forced to low level. The AC-link will be reactivated out of the low-power mode when the SYNC signal is driven high for 1 µs or longer by the AC-link controller while the BITCLK signal is inactive. The software is responsible for controlling the length of this period. ACLC also provides the ‘wake-up’ function. While this function is enabled by ACCTLEN Register’s Enable Wake-up (WAKEUP) bit, high-level input at any SDIN[x] signal will force ACLCPME interrupt assertion. When ACLCPME interrupt is recognized, the software must disable the low-power mode and assert warm reset to the AC-link via ACCTLEN Register’s Enable Warm Reset (WRESET) bit. After the warm reset is deasserted, the CODEC will start providing the BITCLK signal, and then ACLC will generate the SYNC signal for usual AC-link frames. Refer to section B.5.1 of AC’97 specification revision 2.1 for the power-down and wake-up sequence in AC-link power-down mode. 14-15 Chapter 14 AC-link Controller 14.4 Registers The base address for the ACLC registers is described in section 4.2. Only word (32-bit) accesses are allowed. These registers return to their initial values when the module gets reset by power-on or configuration-register operation. The ‘Disable AC-link’ operation initializes the ACREGACC, ACGPIDAT, ACGPODAT, and ACSLTEN registers while keeping the other registers. Do not access any location which is not mentioned in this section. All the register bits marked as ‘Reserved’ are reserved. The value of the reserved bit when read is undefined. When any register is written, write to the reserved bit(s) the same value as the previous value read. Table 14.4.1 ACLC Registers Address 0xF700 0xF704 0xF708 0xF710 0xF714 0xF718 0xF71C 0xF720 0xF740 0xF744 0xF748 0xF74C 0xF750 0xF780 0xF784 0xF7A0 0xF7A4 0xF7A8 0xF7AC 0xF7B8 0xF7B0 0xF7BC 0xF7FC Mnemonic ACCTLEN ACCTLDIS ACREGACC ACINTSTS ACINTMSTS ACINTEN ACINTDIS ACSEMAPH ACGPIDAT ACGPODAT ACSLTEN ACSLTDIS ACFIFOSTS ACDMASTS ACDMASEL ACAUDODAT ACSURRDAT ACCENTDAT ACLFEDAT ACMODODAT ACAUDIDAT ACMODIDAT ACREVID Register Name ACLC Control Enable Register ACLC Control Disable Register ACLC CODEC Register Access Register ACLC Interrupt Status Register ACLC Interrupt Masked Status Register ACLC Interrupt Enable Register ACLC Interrupt Disable Register ACLC Semaphore Register ACLC GPI Data Register ACLC GPO Data Register ACLC Slot Enable Register ACLC Slot Disable Register ACLC FIFO Status Register ACLC DMA Request Status Register ACLC DMA Channel Selection Register ACLC Audio PCM Output Data Register ACLC Surround Data Register ACLC Center Data Register ACLC LFE Data Register ACLC Modem Output Data Register ACLC Audio PCM Input Data Register ACLC Modem Input Data Register ACLC Revision ID Register Type R/W1S W1C R/W R/W1C R R/W1S W1C RS/WC R R/W R/W1S W1C R R R/W W W W W W R R R Initial Value 0x00000000 — 0x00000000 0x00000010 0x00000000 0x00000000 — 0x00000000 0x00000000 0x00000000 0x000003DF — 0x00000000 0x00000000 0x00000000 — — — — — 0xXXXXXXXX 0xXXXXXXXX 0x00000203 14-16 Chapter 14 AC-link Controller 14.4.1 ACLC Control Enable Register 0xF700 This register is used to check the setting of various ACLC features and to enable them. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved AUDIE LFEEH CENTE SURRE AUDO MODIE MODOE Reserved HLT LT HLT HLT EHLT HLT HLT R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S : Type 0 15 14 13 12 11 10 9 8 AUDO DMA 0 6 5 0 4 0 3 0 2 0 1 LOW PWR 0 0 ENLINK : Initial value 7 MODID MODO AUDID LFEDM CENTD SURR MA DMA Reserved MA A MA DMA R/W1S R/W1S Reserved RDYCLR MICSEL WRESET WAKEUP R/W1S R/W1S R/W1S R/W1S R/W1S W 1S R/W1S R/W1S R/W1S R/W1S R/W1S : Type 0 0 0 0 0 0 0 0 0 0 0 0 0 : Initial value Bit 31:24 23 Mnemonic ⎯ Field Name Reserved Enable Modem Receive-data DMA Error Halt Description MODIEHLT: Enable Modem Receive-data DMA Error Halt. R 0: Indicates that MODIDMA error halt is disabled. 1: Indicates that MODIDMA error halt is enabled. W 1S 0: No effect 1: Enables MODIDMA error halt. When MODIDMA overrun occurs, subsequent DMA will not be issued. MODOEHLT: Enable Modem Transmit-data DMA Error Halt. R W 1S 0: Indicates that MODODMA error halt is disabled. 1: Indicates that MODODMA error halt is enabled. 0: No effect 1: Enables MODODMA error halt. When MODODMA underrun occurs, subsequent DMA will not be issued. Read/Write ⎯ R/W1S 22 MODOEHLT Enable Modem Transmit-data DMA Error Halt R/W1S 21 20 ⎯ AUDIEHLT Reserved Enable Audio Receive-data DMA Error Halt AUDIEHLT: Enable Audio Receive-data DMA Error Halt. R W 1S 0: Indicates that AUDIDMA error halt is disabled. 1: Indicates that AUDIDMA error halt is enabled. 0: No effect 1: Enables AUDIDMA error halt. When AUDIDMA overrun occurs, subsequent DMA request will not be issued. ⎯ R/W1S 19 LFEEHLT Enable Audio LFE Transmit-data DMA Error Halt LFEEHLT: Enable Audio LFE Transmit-data DMA Error Halt. R 0: Indicates that LFEDMA error halt is disabled. 1: Indicates that LFEDMA error halt is enabled. W1S 0: No effect 1: Enables LFEDMA error halt. When LFEDMA underrun occurs, subsequent DMA request will not be issued. CENTEHLT: Enable Audio Center Transmit-data DMA Error Halt. R W1S 0: Indicates that CENTDMA error halt is disabled. 1: Indicates that CENTDMA error halt is enabled. 0: No effect 1: Enables CENTDMA error halt. When CENTDMA underrun occurs, subsequent DMA request will not be issued. R/W1S 18 CENTEHLT Enable Audio Center Transmit-data DMA Error Halt R/W1S Figure 14.4.1 ACCTLEN Register (1/3) 14-17 Chapter 14 AC-link Controller Bit 17 Mnemonic Field Name Description SURREHLT: Enable Audio Surround L&R Transmit-data DMA Error Halt. R 0: Indicates that SURRDMA error halt is disabled. 1: Indicates that SURRDMA error halt is enabled. W1S 0: No effect 1: Enables SURRDMA error halt. When SURRDMA underrun occurs, subsequent DMA request will not be issued. AUDOEHLT: Enable Audio PCM L&R Transmit-data DMA Error Halt. R 0: Indicates that AUDODMA error halt is disabled. 1: Indicates that AUDODMA error halt is enabled. W1S 0: No effect 1: Enables AUDODMA error halt. When AUDODMA underrun occurs, subsequent DMA request will not be issued. MODIDMA: Enable Modem Receive-data DMA. R W 1S 0: Indicates that modem receive-data DMA is disabled. 1: Indicates that modem receive-data DMA is enabled. 0: No effect 1: Enables modem receive-data DMA. Read/Write R/W1S SURREHLT Enable Audio Surround L&R Transmit-data DMA Error Halt 16 AUDOEHLT Enable Audio PCM L&R Transmit-data DMA Error Halt R/W1S 15 MODIDMA Enable Modem Receive-data DMA R/W1S 14 MODODMA Enable Modem Transmit-data DMA MODODMA: Enable Modem Transmit-data DMA. R 0: Indicates that modem transmit-data DMA is disabled. 1: Indicates that modem transmit-data DMA is enabled. W 1S 0: No effect 1: Enables modem transmit-data DMA. [Note: DMA size must be internal FIFO depth or more.] AUDIDMA: Enable Audio Receive-data DMA. R 0: Indicates that audio receive-data DMA is disabled. 1: Indicates that audio receive-data DMA is enabled. W 1S 0: No effect 1: Enables audio receive-data DMA. LFEDMA: Enable Audio LFE Transmit-data DMA. R W1S 0: Indicates that audio LFE transmit-data DMA is disabled. 1: Indicates that audio LFE transmit-data DMA is enabled. 0: No effect 1: Enables audio LFE transmit-data DMA. [Note: DMA size must be internal FIFO depth or more.] R/W1S 13 12 ⎯ AUDIDMA Reserved Enable Audio Receive-data DMA ⎯ R/W1S 11 LFEDMA Enable Audio LFE Transmit-data DMA R/W1S 10 CENTDMA Enable Audio Center Transmit- data DMA CENTDMA: Enable Audio Center Transmit-data DMA. R 0: Indicates that audio Center transmit-data DMA is disabled. 1: Indicates that audio Center transmit-data DMA is enabled. W1S 0: No effect 1: Enables audio Center transmit-data DMA. [Note: DMA size must be internal FIFO depth or more.] R/W1S 9 SURRDMA Enable Audio Surround L&R Transmit-data DMA SURRDMA: Enable Audio Surround L&R Transmit-data DMA. R/W1S R 0: Indicates that audio Surround L&R transmit-data DMA is disabled. 1: Indicates that audio Surround L&R transmit-data DMA is enabled. W1S 0: No effect 1: Enables audio Surround L&R transmit-data DMA. [Note: DMA size must be internal FIFO depth or more.] AUDODMA: Enable Audio PCM L&R Transmit-data DMA. R 0: Indicates that audio PCM L&R transmit-data DMA is disabled. 1: Indicates that audio PCM L&R transmit-data DMA is enabled. W1S 0: No effect 1: Enables audio PCM L&R transmit-data DMA. [Note: DMA size must be internal FIFO depth or more.] R/W1S 8 AUDODMA Enable Audio PCM L&R Transmit-data DMA Figure 14.4.1 ACCTLEN Register (2/3) 14-18 Chapter 14 AC-link Controller Bit 7:6 5 Mnemonic ⎯ RDYCLR Field Name Reserved Clear CODEC Ready Bit Description RDYCLR: Clear CODEC Ready Bit W1C Read/Write ⎯ W1S 4 MICSEL 3 W RESET 2 W AKEUP 0: No effect 1: Clear CODEC[1:0] ready bits [Note: This bit should only be written to reevaluate the CODEC ready status after power-down command is sent to CODEC.] MIC Selection MICSEL: MIC Selection. R/W1S R 0: Indicates that PCM L&R (Slot 3&4) is selected for audio reception. 1: Indicates that MIC (Slot 6) is selected for audio reception. W 1S 0: No effect 1: Selects MIC (Slot 6) for audio reception. W RESET: Assert Warm Reset. R/W1S Assert Warm Reset R 0: Indicates that warm reset is not asserted. 1: Indicates that warm reset is asserted. W 1S 0: No effect 1: Asserts warm reset. [Note 1: Do not assert warm reset during normal operation.] [Note 2: The software must guarantee the warm reset assertion time meets the AC’97 specification (1.0 µs or more).] R/W1S Enable Wake-up W AKEUP: Enable Wake-up. R 0: Indicates that wake-up from low-power mode is disabled. 1: Indicates that wake-up from low-power mode is enabled. While any SDIN signal is driven high, ACLC asserts ACLCPME interrupt request to the interrupt controller. W 1S 0: No effect 1: Enables wake-up from low-power mode. [Note: Do not enable wake-up during normal operation.] R/W1S 1 LOWPWR 0 ENLINK Enable AC-link LOWPWR: Enable AC-link Low-power Mode. low-power mode R 0: SYNC and SDOUT signals are not forced to low. 1: SYNC and SDOUT signals are forced to low. W 1S 0: No effect 1: Forces SYNC and SDOUT signals low. [Note: Do not enable AC-link low-power mode during normal operation.] Enable AC-link ENLINK: Enable AC-link. R 0: Indicates that the ACRESET* signal to AC-link is asserted. 1: Indicates that the ACRESET* signal to AC-link is not asserted. W 1S 0: No effect 1: Deasserts the ACRESET* signal to AC-link [Note: The software must guarantee the ACRESET* signal assertion time meets the AC’97 specification (1.0 µs or more).] R/W1S Figure 14.4.1 ACCTLEN Register (3/3) 14-19 Chapter 14 AC-link Controller 14.4.2 ACLC Control Disable Register This register is used to disable various ACLC features. 31 Reserved 0xF704 24 23 22 21 20 19 18 17 16 MODIE MODO AUDIE LFEEH CENTE SURRE AUDO HLT EHLT Reserved HLT LT HLT HLT EHLT W 1C 15 14 13 12 11 10 9 8 AUDO DMA W1C 5 Reserved W1C 4 MIC SEL W1C 3 W1C 2 W1C 1 W1C : Type : Initial value 0 ENLINK 7 MODID MODO AUDID MA DMA Reserved MA LFED CENTD SURR MA MA DMA WRE LOW SET WAKEUP PWR W 1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C W1C : Type : Initial value Bit 31:24 23 Mnemonic — MODIEHLT Field Name Reserved Disable Modem Receive-data DMA Error Halt Description MODIEHLT: Disable Modem Receive-data DMA Error Halt. W1C 0: No effect 1: Disables MODIDMA error halt. MODIDMA request(s) will continue to be issued even after MODIDMA overrun occurs. Read/Write ⎯ W1C 22 MODOEHLT Disable Modem Transmit-data DMA Error Halt Reserved AUDIEHLT Disable Audio Receive-data DMA Error Halt Disable Audio LFE Transmit-data DMA Error Halt MODOEHLT: Disable Modem Transmit-data DMA Error Halt. W1C 0: No effect 1: Disables MODODMA error halt. MODODMA request(s) will continue to be issued even after MODODMA underrun occurs. W1C 21 20 ⎯ AUDIEHLT: Disable Audio Receive-data DMA Error Halt. W1C 0: No effect 1: Disables AUDIDMA error halt. AUDIDMA request(s) will continue to be issued even after AUDIDMA overrun occurs. W1C 0: No effect 1: Disables LFEDMA error halt. LFEDMA request(s) will continue to be issued even after LFEDMA underrun occurs. W1C 0: No effect 1: Disables CENTDMA error halt. CENTDMA request(s) will continue to be issued even after CENTDMA underrun occurs. W1C 0: No effect 1: Disables SURRDMA error halt. SURRDMA request(s) will continue to be issued even after SURRDMA underrun occurs. W1C 0: No effect 1: Disables AUDODMA error halt. AUDODMA request(s) will continue to be issued even after AUDODMA underrun occurs. W1C 0: No effect 1: Disables modem receive-data DMA. W1C 0: No effect 1: Disables modem transmit-data DMA. W1C 19 LFEEHLT LFEEHLT: Disable Audio LFE Transmit-data DMA Error Halt. W1C 18 CENTEHLT Disable Audio Center Transmit-data DMA Error Halt SURREHLT Disable Audio Surround L&R Transmit-data DMA Error Halt AUDOEHLT Disable Audio PCM L&R Transmit-data DMA Error Halt MODIDMA Disable Modem Receive-data DMA CENTEHLT: Disable Audio Center Transmit-data DMA Error Halt. W1C 17 SURREHLT: Disable Audio Surround L&R Transmit-data DMA Error Halt. W1C 16 AUDOEHLT: Disable Audio PCM L&R Transmit-data DMA Error Halt. W1C 15 MODIDMA: Disable Modem Receive-data DMA. W1C 14 MODODMA Disable Modem Transmit-data DMA MODODMA: Disable Modem Transmit-data DMA. W1C Figure 14.4.2 ACCTLDIS Register (1/2) 14-20 Chapter 14 AC-link Controller Bit 13 12 Mnemonic Field Name Reserved — Description AUDIDMA: Disable Audio Receive-data DMA. W1C 0: No effect 1: Disables audio receive-data DMA. Read/Write ⎯ W1C 11 — LFEDMA: Disable Audio LFE Transmit-data DMA. W1C 0: No effect 1: Disables audio LFE transmit-data DMA. W1C 10 — CENTDMA: Disable Audio Center Transmit-data DMA. W1C 0: No effect 1: Disables audio Center transmit-data DMA. W1C 9 — SURRDMA: Disable Audio Surround L&R Transmit-data DMA. W 1C 0: No effect 1: Disables audio Surround L&R transmit-data DMA. W1C 8 — AUDODMA: Disable Audio PCM L&R Transmit-data DMA. W 1C 0: No effect 1: Disables audio PCM L&R transmit-data DMA. W1C 7:5 4 Reserved — MICSEL: MIC Selection W 1C 0: No effect 1: Selects PCM L&R (Slot 3&4) for audio reception W1C 0: No effect 1: Deasserts warm reset. [Note: The software must guarantee the warm reset assertion time meets the AC’97 specification (1.0 µs or more).] W1C 0: No effect 1: Disables wake-up from low-power mode. W1C 0: No effect 1: Releases SYNC and SDOUT signals from low. W1C 0: No effect 1: Asserts the ACRESET* signal to AC-link. [Note: The software must guarantee the ACRESET* signal assertion time meets the AC’97 specification (1.0 µs or more).] W1C ⎯ 3 — W RESET: Deassert Warm Reset. W 1C 2 — W AKEUP: Disable Wake-up. W 1C 1 — LOWPWR: Disable AC-link Low-power Mode. W 1C 0 — ENLINK: Disable AC-link. W 1C Figure 14.4.2 ACCTLDIS Register (2/2) Clear xxxxDMA bits in ACCTLEN to “0” by using this register to disable transmit/receive-data DMA and to stop transmission/reception by the AC-link. Note that if these bits are cleared while output-slot data is flowing in the FIFO, ACLC may output a wrong data as the last sample. This behavior will not occur if the software waits for data-flow completion by detecting underrun before it disables the corresponding slot. 14-21 Chapter 14 AC-link Controller 14.4.3 ACLC CODEC Register Access Register CODEC registers can be accessed through this register. 31 CODE CRD W 15 REGDAT R/W : Type : Initial value 30 Reserved 26 25 24 23 Reserved 0xF708 22 REGADR 16 CODECID W R/W 0 : Type : Initial value Bit 31 Mnemonic CODECRD Field Name AC’97 register read access Reserved AC’97 CODEC ID CODECID: AC’97 CODEC ID W W Description CODECRD: AC’97 register read access 0: Indicates a write access. 1: Indicates a read access. Read/Write W 30:26 25:24 — CODECID ⎯ W Specifies the CODEC ID of the read/write access destination. The values “0” through “3” can be specified as the CODEC ID, but the number of CODECs actually supported depends on the configuration. ⎯ REGADR: AC’97 register address Read address. Valid address can be read after read access is R complete. W Specifies the read/write access destination address. REGDAT: AC’97 register data R W Read data. Valid data can be read after read access is complete. W rite data. R/W 23 22:16 — REGADR Reserved AC’97 register address 15:0 REGDAT AC’97 register data R/W Figure 14.4.3 ACREGACC This register must not be read from or written to until access completion is reported through the ACINTSTS register. 14-22 Chapter 14 AC-link Controller 14.4.4 ACLC Interrupt Status Register 0xF710 This register shows various kinds of AC-link and ACLC status. 31 Reserved : Type : Initial value 15 MODIE RR 16 14 MODOE RR 13 Reserved 12 AUDIE RR 11 LFEERR 10 CENTE RR 9 SURRE RR 8 AUDOE RR 7 6 5 GPIOINT 4 REGAC CRDY 3 2 1 CODEC 1RDY 0 CODEC 0RDY Reserved Reserved R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R R : Type : Initial value 0 0 0 0 0 0 0 0 1 0 0 Bit 31:16 15 Mnemonic — MODIERR Field Name Reserved Modem Receive-data DMA Overrun Modem Transmit-data DMA Underrun Reserved Audio Receive-data DMA Overrun Audio LFE Transmit-data DMA Underrun Audio Center Transmit-data DMA Underrun Audio Surround L&R Transmit-data DMA Underrun Audio PCM L&R Transmitdata DMA Underrun Reserved GPIO Interrupt GPIOINT: GPIO Interrupt R W1C Description MODIERR: Modem Receive-data DMA Overrun R W1C R W1C 1: Indicates that the modem receive-data DMA overran. This bit is cleared when “1” is written to it. Read/Write ⎯ R/W1C 14 MODOERR MODOERR: Modem Transmit-data DMA Underrun 1: Indicates that the modem transmit-data DMA underran. This bit is cleared when “1” is written to it. R/W1C 13 12 ⎯ AUDIERR ⎯ AUDIERR: Audio Receive-data DMA Overrun R W1C R W1C R W1C R W1C R W1C 1: Indicates that the audio receive-data DMA overran. This bit is cleared when “1” is written to it. R/W1C 1: Indicates that the audio LFE transmit-data DMA underran. This bit is cleared when “1” is written to it. R/W1C 1: Indicates that the audio center transmit-data DMA underran. This bit is cleared when “1” is written to it. R/W1C 1: Indicates that the audio surround L&R transmit-data DMA underran. This bit is cleared when “1” is written to it. R/W1C 1: Indicates that the audio PCM L&R transmit-data DMA underran. This bit is cleared when “1” is written to it. ⎯ R/W1C 1: Indicates that the incoming slot 12 bit[0] is ‘1’ (the modem CODEC GPIO interrupt). This bit is cleared if “1” is written to it while the incoming slot 12 bit[0] is ‘0’. R/W1C 11 LFEERR LFEERR: Audio LFE Transmit-data DMA Underrun 10 CENTERR CENTERR: Audio Center Transmit-data DMA Underrun 9 SURRERR SURRERR: Audio Surround L&R Transmit-data DMA Underrun 8 AUDOERR AUDOERR: Audio PCM L&R Transmit-data DMA Underrun 7:6 5 ⎯ GPIOINT Figure 14.4.4 ACINTSTS Register (1/2) 14-23 Chapter 14 AC-link Controller Bit 4 Mnemonic Field Name R Description REGACCRDY: ACREGACC Ready 1: Indicates that the ACREGACC register is ready to get the value (in case the previous operation was a read access) and to initiate another R/W access to an AC’97 register. The result of reading or writing to the ACREGACC register before the completion notification is undefined. This bit is cleared if “1” is written to it. This bit automatically becomes ‘0’ when the ACREGACC register is written. Read/Write R/W1C REGACCRDY ACREGACC Ready W1C 3:2 1 0 ⎯ Reserved ⎯ R R R R 1: Indicates that the CODEC Ready bit of SDIN1 Slot0 is set. 1: Indicates that the CODEC Ready bit of SDIN0 Slot0 is set. CODEC1RDY CODEC1 Ready CODEC1RDY: CODEC1 Ready CODEC0RDY CODEC0 Ready CODEC0RDY: CODEC0 Ready Figure 14.4.4 ACINTSTS Register (2/2) 14-24 Chapter 14 AC-link Controller 14.4.5 ACLC Interrupt Masked Status Register Every bit in this register is configured as follows: ACINTMSTS = ACINTSTS & ACINTEN Bit placement is the same as for the ACINTSTS register. The logical OR of all bits in this register is used as ACLC interrupt request to the interrupt controller. 0xF714 14.4.6 ACLC Interrupt Enable Register 0xF718 Interrupt request enable (R/W1S). Bit placement is the same as for the ACINTSTS register. Its initial value is all ‘0’. When a value is written to this register, the bit in the position where “1” was written is set to “1.” 14.4.7 ACLC Interrupt Disable Register 0xF71C Interrupt request enable clear (W1C). Bit placement is the same as for the ACINTSTS register. When a value is written to this register, the ACINTEN register bit in the position where a “1” was written is cleared to “0.” 14-25 Chapter 14 AC-link Controller 14.4.8 ACLC Semaphore Register 0xF720 This register is used for mutual exclusion control for resource. 31 SEMAPH RS/WC 0 15 SEMAPH RS/WC 0 : Type : Initial value 0 : Type : Initial value 16 Bit 31:0 Mnemonic SEMAPH Field Name Semaphore flag SEMAPH: Semaphore flag. RS Description 0: Indicates that the semaphore is unlocked. The read operation to this register will atomically set the bit[0] to lock the semaphore. 1: Indicates that the semaphore is locked. x: Writing any value to this register clears the bit[0] to release the semaphore. Read/Write RS/WC WC Figure 14.4.5 ACSEMAPH Register This register is provided primarily for the mutual exclusion between the audio and modem drivers to share the common resources of ACLC, such as the ACREGACC register and the link-control bits in the ACCTLEN/DIS register. 14-26 Chapter 14 AC-link Controller 14.4.9 ACLC GPI Data Register This register shows GPIO (slot 12) input data. 31 Reserved 20 19 GPIDAT R 0x00000 15 GPIDAT R 0x00000 1 0 GPIO INT 0xF740 16 : Type : Initial value R 0 : Type : Initial value Bit 31:20 19:1 0 Mnemonic ⎯ GPIDAT GPIOINT Field Name Reserved GPIO-In data GPIO Interrupt Indication GPIDAT: GPIO-In data R R Description Read/Write ⎯ R R Read data. The incoming slot 12 bits[19:1] are shadowed here. GPIO Interrupt. The incoming slot 12 bit[0] is shadowed here. GPIOINT: GPIO Interrupt Indication Figure 14.4.6 ACGPIDAT Register 14-27 Chapter 14 AC-link Controller 14.4.10 ACLC GPO Data Register This register specifies GPIO (slot 12) output data. 31 Reserved 21 20 W RPEND 0xF744 19 GPODAT R/W 0x00000 1 16 R 0 15 GPODAT R/W 0x00000 : Type : Initial value 0 R 0 : Type : Initial value Bit 31:20 20 Mnemonic ⎯ WRPEND Field Name Reserved Write Pending W RPEND: Write Pending R Description Read/Write ⎯ R 0: Indicates that the previous write operation is complete and the ACGPODAT register is ready to be written. 1: Indicates that the previous write operation is not complete and the ACGPODAT register is not yet ready to be written. R/W Reads back the value previously written to this field. Writes data to the outgoing slot 12 bits[19:1]. Reads always ‘0’. R 19:1 GPODAT GPIO-Out data GPODAT: GPIO-Out data R W 0 ⎯ ⎯ R Figure 14.4.7 ACGPODAT Register Writing a value into this register needs several BITCLK cycles to take effect. The software must guarantee that no write access be executed until the previous write access takes effect (completes), by reading the ACGPODAT.WRPEND bit prior to writing this register. If it is set for a long time, the BITCLK signal on the AC-link is probably inactive for whatever reason. 14-28 Chapter 14 AC-link Controller 14.4.11 ACLC Slot Enable Register 0xF748 This register enables independently the AC-link slot data streams. 31 Reserved 17 16 W RPEND R : Type : Initial value 0 15 Reserved 10 9 8 7 6 MODO SLT 5 4 3 2 CENT SLT 1 SURR SLT 0 AUDO SLT GPISLT GPOSLT MODISLT Reserved AUDISLT LFESLT R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S R/W1S : Type 1 1 1 1 1 1 1 1 1 : Initial value Bit 31:17 16 Mnemonic ⎯ WRPEND Field Name Reserved Write Pending W RPEND: Write Pending R Description Read/Write ⎯ R 0: Indicates that the previous write operation is complete and the ACSLTEN and ACSLTDIS registers are ready to be accessed. 1: Indicates that the previous write operation is not complete and the ACSLTEN and ACSLTEDIS registers are not yet ready to be accessed. ⎯ R/W1S 15:10 9 ⎯ GPISLT Reserved Enable GPI slot reception GPISLT: Enable GPI slot reception. R W1S 0: Indicates that GPI slot reception is disabled. 1: Indicates that GPI slot reception is enabled. 0: No effect 1: Enables GPI slot reception. 8 GPOSLT Enable GPO Slot transmission GPOSLT: Enable GPO Slot transmission. R W1S 0: Indicates that GPO slot transmission is disabled. 1: Indicates that GPO slot transmission is enabled. 0: No effect 1: Enables GPO slot transmission. R/W1S 7 MODISLT Enable Modem slot reception MODISLT: Enable Modem slot reception. R W1S 0: Indicates that modem slot reception is disabled. 1: Indicates that modem slot reception is enabled. 0: No effect 1: Enables modem slot reception. R/W1S 6 MODOSLT Enable Modem slot transmission MODOSLT: Enable Modem slot transmission. R W1S 0: Indicates that modem slot transmission is disabled. 1: Indicates that modem slot transmission is enabled. 0: No effect 1: Enables modem slot transmission. R/W1S 5 ⎯ Reserved ⎯ Figure 14.4.8 ACSLTEN Register (1/2) 14-29 Chapter 14 AC-link Controller Bit 4 Mnemonic AUDISLT Field Name Enable Audio slot reception R W1S Description AUDISLT: Enable Audio slot reception. 0: Indicates that audio slot reception is disabled. 1: Indicates that audio slot reception is enabled. 0: No effect 1: Enables audio slot reception. Read/Write R/W1S 3 LFESLT Enable Audio LFE slot transmission LFESLT: Enable Audio LFE slot transmission. R W1S 0: Indicates that audio LFE slot transmission is disabled. 1: Indicates that audio LFE slot transmission is enabled. 0: No effect 1: Enables audio LFE slot transmission. R/W1S 2 CENTSLT Enable Audio Center slot transmission CENTSLT: Enable Audio Center slot transmission. R W1S 0: Indicates that audio Center slot transmission is disabled. 1: Indicates that audio Center slot transmission is enabled. 0: No effect 1: Enables audio Center slot transmission. R/W1S 1 SURRSLT Enable Audio Surround L&R slot transmission SURRSLT: Enable Audio Surround L&R slot transmission. R W1S 0: Indicates that audio Surround L&R slot transmission is disabled. 1: Indicates that audio Surround L&R slot transmission is enabled. 0: No effect 1: Enables audio Surround L&R slot transmission. R/W1S 0 AUDOSLT Enable Audio PCM L&R slot transmission AUDOSLT: Enable Audio PCM L&R slot transmission. R W1S 0: Indicates that audio PCM L&R Slot transmission is disabled. 1: Indicates that audio PCM L&R Slot transmission is enabled. 0: No effect 1: Enables audio PCM L&R slot transmission. R/W1S Figure 14.4.8 ACSLTEN Register (2/2) Writing a value into this register needs several BITCLK cycles to take effect. The software must guarantee that no write access be executed until the previous write access takes effect (completes), by reading the ACSLTEN.WRPEND bit prior to writing this register. If it is set for a long time, the BITCLK signal on the AC-link is probably inactive for whatever reason. 14-30 Chapter 14 AC-link Controller 14.4.12 ACLC Slot Disable Register 0xF74C This register disables independently the AC-link slot data streams. 31 Reserved : Type : Initial value 15 Reserved 10 9 8 7 MODI SLT 16 6 MODO SLT 5 Reserved 4 AUDI SLT 3 LFESLT 2 CENT SLT 1 SURR SLT 0 AUDO SLT GPISLT GPOSLT W 1C W1C W1C W1C W1C W1C W1C W1C W1C : Type : Initial value Bit 31:10 9 Mnemonic ⎯ GPISLT Field Name Reserved Disable GPI slot reception Disable GPO Slot transmission Disable Modem slot reception Disable Modem slot transmission Reserved Disable Audio slot reception Disable Audio LFE slot transmission Disable Audio Center slot transmission Disable Audio Surround L&R slot transmission Disable Audio PCM L&R slot transmission Description GPISLT: Disable GPI slot reception. W1C 0: No effect 1: Disables GPI slot reception. Read/Write ⎯ W1C 8 GPOSLT GPOSLT: Disable GPO Slot transmission. 0: No effect 1: Disables GPO slot transmission. MODISLT: Disable Modem slot reception. 0: No effect 1: Disables modem slot reception. MODOSLT: Disable Modem slot transmission. W1C 0: No effect 1: Disables modem slot transmission. W1C W1C W1C 7 MODISLT W1C 6 MODOSLT W1C 5 4 ⎯ AUDISLT ⎯ AUDISLT: Disable Audio slot reception. 0: No effect 1: Disables audio slot reception. LFESLT: Disable Audio LFE slot transmission. 0: No effect 1: Disables audio LFE slot transmission. CENTSLT: Disable Audio Center slot transmission. 0: No effect 1: Disables audio Center slot transmission. SURRSLT: Disable Audio Surround L&R slot transmission. W1C 0: No effect 1: Disables audio Surround L&R slot transmission. W1C W1C W1C W1C W1C 3 LFESLT W1C 2 CENTSLT W1C 1 SURRSLT W1C 0 AUDOSLT AUDOSLT: Disable Audio PCM L&R slot transmission. W1C 0: No effect 1: Disables audio PCM L&R slot transmission. Figure 14.4.9 ACSLTDIS Register Writing a value into this register needs several BITCLK cycles to take effect. The software must guarantee that no write access be executed until the previous write access takes effect (completes), by reading the ACSLTEN.WRPEND bit prior to writing this register. If it is set for a long time, the BITCLK signal on the AC-link is probably inactive for whatever reason. 14-31 Chapter 14 AC-link Controller 14.4.13 ACLC FIFO Status Register 0xF750 This register indicates the AC-link slot data FIFO status. 31 Reserved : Type : Initial value 15 Reserved 16 14 MODO FULL 13 12 11 LFE FULL 10 CENT FULL 9 SURR FULL 8 AUDO FULL 7 MODI FILL 6 MODO FILL 5 Reserved 4 AUDI FILL 3 LFEFILL 2 CENT FILL 1 SURR FILL 0 AUDO FILL Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 : Type : Initial value Bit 31:15 14 Mnemonic ⎯ Field Name Reserved Description MODOFULL: Modem Transmit-data Full. R 0: Indicates modem transmit-data FIFO is not full. 1: Indicates modem transmit-data FIFO is full. Read/Write ⎯ R MODOFULL Modem Transmit-data Full Reserved LFEFULL Reserved Audio LFE Transmit-data Full Audio Center Transmit-data Full Audio Surround L&R Transmit-data Full 13:12 11 ⎯ LFEFULL: Audio LFE Transmit-data Full. R 0: Indicates audio LFE transmit-data FIFO is not full. 1: Indicates audio LFE transmit-data FIFO is full. R 0: Indicates audio Center transmit-data FIFO is not full 1: Indicates audio Center transmit-data FIFO is full. R 0: Indicates audio Surround L&R transmit-data FIFO is not full. 1: Indicates audio Surround L&R transmit-data FIFO is full. R R 10 CENTFULL CENTFULL: Audio Center Transmit-data Full. R 9 SURRFULL SURRFULL: Audio Surround L&R Transmit-data Full. R 8 AUDOFULL Audio PCM L&R AUDOFULL: Audio PCM L&R Transmit-data Full. Transmit-data R 0: Indicates audio PCM L&R transmit-data FIFO is not full. Full 1: Indicates audio PCM L&R transmit-data FIFO is full. Modem Receive-data Filled Modem Transmit-data Filled Reserved Audio Receive-data Filled Audio LFE Transmit-data Filled AUDIFILL: Audio Receive-data Filled. R 0: Indicates audio receive-data FIFO is empty. 1: Indicates audio receive-data FIFO is not empty. MODIFILL: Modem Receive-data Filled. R 0: Indicates modem receive-data FIFO is empty. 1: Indicates modem receive-data FIFO is not empty. 7 MODIFILL R 6 MODOFILL MODOFILL: Modem Transmit-data Filled. R 0: Indicates modem transmit-data FIFO is empty. 1: Indicates modem transmit-data FIFO is not empty. R 5 4 ⎯ AUDIFILL ⎯ R 3 LFEFILL LFEFILL: Audio LFE Transmit-data Filled. R 0: Indicates audio LFE transmit-data FIFO is empty. 1: Indicates audio LFE transmit-data FIFO is not empty. R Figure 14.4.10 ACFIFOSTS Register (1/2) 14-32 Chapter 14 AC-link Controller Bit 2 Mnemonic CENTFILL Field Name Audio Center Transmit-data Filled Audio Surround L&R Transmit-data Filled R Description CENTFILL: Audio Center Transmit-data Filled. 0: Indicates audio Center transmit-data FIFO is empty. 1: Indicates audio Center transmit-data FIFO is not empty. Read/Write R 1 SURRFILL SURRFILL: Audio Surround L&R Transmit-data Filled. R 0: Indicates audio Surround L&R transmit-data FIFO is empty. 1: Indicates audio Surround L&R transmit-data FIFO is not empty. R 0 AUDOFILL Audio PCM L&R AUDOFILL: Audio PCM L&R Transmit-data Filled. Transmit-data R 0: Indicates audio PCM L&R transmit-data FIFO is empty. Filled 1: Indicates audio PCM L&R transmit-data FIFO is not empty R Figure 14.4.10 ACFIFOSTS Register (2/2) 14-33 Chapter 14 AC-link Controller 14.4.14 ACLC DMA Request Status Register 0xF780 This register indicates the AC-link slot data DMA request status. 31 Reserved : Type : Initial value 15 Reserved 8 7 MODI REQ 16 6 MODO REQ 5 Reserved 4 AUDI REQ 3 LFEREQ 2 CENT REQ 1 SURR REQ 0 AUDO REQ R 0 R 0 R 0 R 0 R 0 R 0 R 0 : Type : Initial value Bit 31:8 7 Mnemonic ⎯ MODIREQ Field Name Reserved Modem Data Reception Request Modem Data Transmission Request Reserved Audio Data Reception Request Audio LFE Data Transmission Request Audio Center Data Transmission Request Audio Surround L&R Data Transmission Request Description MODIREQ: Modem Data Reception Request R 0: No request is pending. 1: Request is pending. Read/Write ⎯ R 6 MODOREQ MODOREQ: Modem Data Transmission Request R 0: No request is pending. 1: Request is pending. R 5 4 ⎯ AUDIREQ ⎯ AUDIREQ: Audio Data Reception Request R 0: No request is pending. 1: Request is pending. R 0: No request is pending. 1: Request is pending. R 0: No request is pending. 1: Request is pending. R R 3 LFEREQ LFEREQ: Audio LFE Data Transmission Request R 2 CENTREQ CENTREQ: Audio Center Data Transmission Request R 1 SURRREQ SURRREQ: Audio Surround L&R Data Transmission Request R 0: No request is pending. 1: Request is pending. 0 AUDOREQ Audio PCM L&R AUDOREQ: Audio PCM L&R Data Transmission Request Data R 0: No request is pending. Transmission 1: Request is pending. Request R Figure 14.4.11 ACDMASTS Register This read-only register shows if any DMA request is pending for each data I/O channel. A DMA request can be pending after the software deactivates the DMAC channel or disables DMA by ACCTLDIS register bit to complete DMA operation. In this case, write or read the sample data register (ACAUDODAT and others) to clear the DMA request. 14-34 Chapter 14 AC-link Controller 14.4.15 ACLC DMA Channel Selection Register 0xF784 This register is used to select and check the channel allocation for AC-link slot data DMA. 31 Reserved : Type : Initial value 15 Reserved 2 1 0 ACDMASEL R/W 0 : Type : Initial value 16 Bit 31:2 1:0 Mnemonic ⎯ Field Name Reserved Description ACDMASEL: DMA Channel Selection R/W ACDMASEL: DMA Channel Selection 0: PCM L&R out, Audio in, and Modem out&in. 1: PCM L&R out, Surround L&R out, and Modem out&in. 2: PCM L&R out, Surround L&R out, Center out, and LFE out. 3: PCM L&R out, Surround L&R out, Center out, and Audio in. Read/Write ⎯ R/W ACDMASEL DMA Channel Selection Figure 14.4.12 ACDMASEL Register This register selects DMA channel mapping mode. The software is recommended to make sure no DMA request is pending before changing this register value. 14-35 Chapter 14 AC-link Controller 14.4.16 ACLC Audio PCM Output Data Register ACLC Surround Data Register 0xF7A0 0xF7A4 These registers are used to write audio PCM and surround L&R output data. 31 DAT1: Sample Right (Little-endian mode) / DAT0: Sample Left (Big-endian mode) W 15 DAT0: Sample Left (Little-endian mode) / DAT1: Sample Right (Big-endian mode) W : Type : Initial value 0 : Type : Initial value 16 Bit 31:16 15:0 Mnemonic — — Field Name — — W W Description Little-endian mode DAT1: Sample Right DAT0: Sample Left Big-endian mode DAT0: Sample Left Left DAT1: Sample Right Read/Write W W Figure 14.4.13 ACAUDODAT/ACSURRDAT Register 14-36 Chapter 14 AC-link Controller 14.4.17 ACLC Center Data Register ACLC LFE Data Register ACLC Modem Output Data Register 0xF7A8 0xF7AC 0xF7B8 This registers are used to write audio center, LFE, and modem output data. 31 DAT1: Sample data 1 (Little-endian mode) / DAT0: Sample data 0 (Big-endian mode) W 15 DAT0: Sample data 0 (Little-endian mode) / DAT1: Sample data 1 (Big-endian mode) W : Type : Initial value 0 : Type : Initial value 16 Bit 31:16 15:0 Mnemonic — — Field Name — — W W Description Little-endian mode DAT1: Sample data 1 DAT0: Sample data 0 Big-endian mode DAT0: Sample data 0 DAT1: Sample data 1 Read/Write W W Figure 14.4.14 ACCENDAT/ACLFEDAT/ACMODODAT Register 14-37 Chapter 14 AC-link Controller 14.4.18 ACLC Audio PCM Input Data Register This register is used to read audio PCM input data. 31 DAT1: Sample Right or ‘0’ (Little-endian mode) / DAT0: Sample Left or MIC (Big-endian mode) R Undefined 15 DAT0: Sample Left or MIC (Little-endian mode) / DAT1: Sample Right or ‘0’ (Big-endian mode) R Undefined : Type : Initial value 0 : Type : Initial value 16 0xF7B0 Bit 31:16 15:0 Mnemonic — — Field Name — — R R Description Little-endian mode DAT1: Sample Right or ‘0’ DAT0: Sample Left or MIC Big-endian mode DAT0: Sample Left or MIC DAT1: Sample Right or ‘0’ Read/Write R R Figure 14.4.15 ACAUDIDAT Register 14-38 Chapter 14 AC-link Controller 14.4.19 ACLC Modem Input Data Register This register is used to read modem input data. 31 DAT1: Sample data 1 (Little-endian mode) / DAT0: Sample data 0 (Big-endian mode) R Undefined 15 DAT0: Sample data 0 (Little-endian mode) / DAT1: Sample data 1 (Big-endian mode) R Undefined : Type : Initial value 0 : Type : Initial value 16 0xF7BC Bit 31:16 15:0 Mnemonic — — Field Name — — R R Description Little-endian mode DAT1: Sample data 1 DAT0: Sample data 0 Big-endian mode DAT0: Sample data 0 DAT1: Sample data 1 Read/Write R R Figure 14.4.16 ACMODIDAT Register 14-39 Chapter 14 AC-link Controller 14.4.20 ACLC Revision ID Register 0xF7FC This register is used to read ACLC module’s revision ID. 31 Reserved : Type : Initial value 15 Major Revision R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 1 R 0 R 0 R 0 8 7 Minor Revision R 0 R 0 R 0 R 1 R 0 : Type : Initial value 0 16 Bit 31:16 15:8 Mnemonic ⎯ ⎯ Field Name Reserved ⎯ R Description Major Revision Contact Toshiba technical staff for an explanation of the revision value. Minor Revision Contact Toshiba technical staff for an explanation of the revision value. Read/Write ⎯ R 7:0 ⎯ ⎯ R R Figure 14.4.17 ACREVID Register This read-only register shows the revision of ACLC module. Note that this number is not related to the AC’97 specification revision. 14-40 Chapter 15 Interrupt Controller 15. Interrupt Controller 15.1 Characteristics The TX4938 on-chip Interrupt Controller (IRC) receives interrupt requests from the TX4938 on-chip peripheral circuitry as well as external interrupt requests then generates interrupt requests to the TX49/H3 processor core. Also, the Interrupt Controller has a 16-bit flag register that generates interrupt requests to either external devices or to the TX49/H3 core. The Interrupt Controller has the following characteristics. • • • • Supports interrupts from 18 types of on-chip peripheral circuits and a maximum of 6 external interrupt signal inputs Sets 8 priority interrupt levels for each interrupt input Can select either edge detection or level detection for each external interrupt when in the interrupt detection mode As a flag register used for interrupt requests, the Interrupt Controller contains a 16-bit readable/writeable register and can issue interrupt requests to external devices as well as to the TX49/H3 core (IRC interrupt). 15-1 Chapter 15 Interrupt Controller 15.2 Block Diagram TX49/H3 Core Internal Timer Interrupt Request Interrupt Request (IP[7:2]) 0 1 [7] [6:2] [7:2] 6 Interrupt Controller 1 1 2 Detection Circuit Set Interrupt Level 4 4 3 2 1 1 1 1 1 TINTDIS 1 1 1 1 1 External Interrupt Signal (INT[5:0]) ECC Error TX49 Write time out Error SIO[1:0] DMA0[3:0] DMA1[3:0] TMR[2:0] ACLC PDMAC0 PCIC0 PCIERR0 PCIPME0 ETHERC0 ETHERC1 NDFMC PCIC1 SPI Internal Interrupt Request Non-maskable Interrupt Signal (NMI*) (active Low) Watchdog Timer Interrupt Watch-dog timer Interrupt (TMR2) (active Low) Internal Interrupt Signal Non-maskable Interrupt Request Set Interrupt Mask Process Priority External Interrupt Request Flag Register REQ[1]*/INTOUT Polarity Register PCIC Mask Register Interrupt Control Register Figure 15.2.1 Interrupt Controller Outline 15-2 Chapter 15 Interrupt Controller Interrupt Detection IDE Interrupt Detection Interrupt Level Mode IRDM0-1 IRLVL0-7 Interrupt Mask Level IRMSK Detection Circuit Low Level High Level Edge Detector Edge Detector Negative Edge Positive Edge Interrupt Source 1 Encoder Interrupt Pending IRPND 3 Interrupt Prioritization 1 Interrupt IRCS.FL 5 Interrupt Cause IRCS.CAUSE IP [2] IP [7:3] 3 3 3 Interrupt Level IRCS.LVL Figure 15.2.2 Internal Block Diagram of Interrupt Controller 15-3 Chapter 15 Interrupt Controller 15.3 Detailed Explanation 15.3.1 Interrupt sources The TX4938 has as interrupt sources interrupts from 18 types of on-chip peripheral circuits and 6 external interrupt signals. Table 15.3.1 lists the interrupt sources. Signals with the lower interrupt number have the higher priority. The priorities are explained below in section 15.3.4. The interrupt number 5 is shared between INT[3] and ETHERC1. When ETHERC1 is used, an interrupt is noticed from ETHERC1 to the IRC interrupt number 5 internal of a chip. The external pin INT[3] is used when ETHERC1 is used for the purpose other than an interrupt. This is the same as for the interrupt number 6. Refer to “3.3 Pin multiplex” for muliplexed pins. Table 15.3.1 Interrupt Sources and Priorities Priority High Interrupt Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Interrupt Source SDRAM ECC Error (Internal) TX49 Write Timeout Error (Internal) INT[0] (External) INT[1] (External) INT[2] (External) INT[3] (External) / ETHERC1 (Internal) INT[4] (External) / ETHERC0 (Internal) INT[5] (External) SIO0 (Internal) SIO1 (Internal) DMA0[0] (Internal) DMA0[1] (Internal) DMA0[2] (Internal) DMA0[3] (Internal) IRC (Internal) PDMAC0 (Internal) PCIC0 (Internal) TMR0 (Internal) TMR1 (Internal) TMR2 (Internal) (Reserved) NDFMC (Internal) PCIERR (Internal) PCIPMC (Internal) ACLC (Internal) ACLCPME (Internal) PCIC1INT (Internal) DMAC1[0] (Internal) DMAC1[1] (Internal) DMAC1[2] (Internal) DMAC1[3] (Internal) SPI (Internal) Low 31 15-4 Chapter 15 Interrupt Controller In addition to the above, the TX49/H3 core has a TX49/H3 core internal timer interrupt and two software interrupts, but these interrupts are directly reported to the TX49/H3 core independently of this Interrupt Controller. Please refer to the 64-bit TX System RISC TX49/H3 Core Architecture Manual for more information. 15.3.2 Interrupt request detection In order to perform interrupt detection, each register of the Interrupt Controller is initialized, then the IDE bit of the Interrupt Detection Enable Register (IRDEN) is set to “1.” All interrupts detected by the Interrupt Controller are masked when this bit is cleared. It is possible to set each interrupt factor detection mode using Interrupt Detection Mode Register 0 (IRDM0) and Interrupt Detection Mode Register 1 (IRDM1). There are four detection modes: Low level, High level, falling edge, and rising edge. The detected interrupt factors can be read out from the Interrupt Pending Register (IRPND). 15.3.3 Interrupt level assigning Interrupt levels from 0 to 7 are assigned to each detected interrupt using the Interrupt Level Register (IRLVL0-7). Interrupt level 7 is the highest priority and interrupt level1 is the lowest priority. Level 0 interrupts will be masked. (Table 15.3.2). The priorities set by these interrupt levels will be given higher priority than the priorities provided for each interrupt source indicated in Table 15.3.1. Table 15.3.2 Interrupt Levels Priority High Interrupt Level (IRLVLn.ILm) 111 110 101 100 011 010 Low Mask 001 000 15-5 Chapter 15 Interrupt Controller 15.3.4 Interrupt priority assigning When multiple interrupt requests exist, the Interrupt Controller selects the interrupt with the highest priority according to the priority level and interrupt number. Interrupt factors with an interrupt level equal to or lower than the interrupt level specified by the Interrupt Mask Level Register (IRMSK) will be excluded (masked). When the interrupt with the highest priority is selected, then the interrupt number of that interrupt is set in the interrupt factor field (CAUSE) of the Interrupt Current Status Register (IRCS), the interrupt level is set in the Interrupt Level field (LVL), and the Interrupt Flag bit (IF) is set. Priorities are assigned as follows. • • When interrupt levels differ, the interrupt with the higher interrupt level has priority (Table 15.3.2) When multiple interrupts with the same interrupt level are simultaneously detected, the interrupt with the smaller interrupt number has priority (Table 15.3.1). In the following cases, interrupts are reprioritized. If any new interrupt requests are generated before reprioritization, the highest-priority interrupt is accepted, changing the Interrupt Cause (CAUSE) and Interrupt Level (LVL) fields in the Interrupt Current Status (IRCS) register. • When an interrupt request with a higher interrupt level than that of the currently selected interrupt is detected. If the interrupt levels are equal, the Interrupt Cause (CAUSE) field does not change, even if the interrupt number is smaller. When the interrupt level (IRLVLn.ILm) of the currently selected interrupt changes to a value smaller than the current setting. When the currently selected interrupt is cleared (refer to 15.3.6 Clearing interrupt requests). • • Changing the Interrupt Mask Level (IRMSK.LML) does not cause the IRC to reprioritize interrupts. However, if the Interrupt Mask Level (IRMSK.LML) is set to a value equal to or greater than the current interrupt level (IRLVLn.ILm), the Interrupt Flag bit in the Interrupt Current Status register (IRCS.IF) is set to mask the interrupt. 15-6 Chapter 15 Interrupt Controller 15.3.5 Interrupt notification When the interrupt with the highest priority is selected, then the interrupt factor is reported to the Interrupt Current Status Register (IRCS) and an interrupt is reported to the TX49/H3 core. The TX49/H3 core distinguishes interrupt factors using the IP field (IP[7:2]) of the Cause Register. The interrupt notification from the Interrupt Controller is reflected in the IP[2] bit. The Interrupt Handler uses the IP[2] bit to judge whether or not there are interrupts from this Interrupt Controller and uses the Interrupt Current Status Register (IRCS) to determine the interrupt cause. The Interrupt Factor field (IRCS.CAUSE) value is reflected in the remaining bits of the IP field. Since bit IP[7] is also being used for notification of TX49/H3 CPU core internal timer interrupts, the contents specified by IP[7] differ according to whether internal timer interrupts are set to valid (TINTDIS=0) or invalid (TINTDIS=1), as indicated Table 15.3.3. TINTDIS is the value that is set from DATA[7] at the timing when the RESET* signal is deasserted. See the explanation “3.2 Boot Configuration” for more information. Table 15.3.3 Interrupt Notification to IP[7:2] of the CP0 Cause Register TINTDIS 0 (Internal Timer Interrupts: Valid) 1 (Internal Timer Interrupts: Invalid) IP[7] Internal Timer Interrupt Notification IP[6:3] IRCS.CAUSE[3:0] IP[2] IRCS.IF IRCS.IF IRCS.CAUSE[4:0] 15.3.6 Clearing interrupt requests Interrupt requests are cleared according to the following process. • When the detection mode is set to the High level or Low level: Operation is performed to deassert the request of a source that is asserting an interrupt request. When the detection mode is set to Rising edge or Falling edge Edge detection requests are cleared by first specifying the interrupt source of the interrupt request to be cleared in the Edge Detection Clear Source field (EDCS0 or EDCS1) of the Interrupt Edge Detection Clear Register (IREDC) then writing the resulting value when the corresponding Edge Detection Clear Enable bit (EDCE0 or EDCE1) is set to “1.” • 15-7 Chapter 15 Interrupt Controller 15.3.7 Interrupt requests It is possible to make interrupt requests to external devices and interrupt requests (IRC interrupts) to the TX49/H3 core by using a 16-bit interrupt request flag register. REQ[1]* signals are used as interrupt output signals. Consequently, external interrupt requests can only be used when in the PCI External Arbiter mode. Also, internal interrupt requests are assigned to interrupt number 13 of the Interrupt Controller (IRC). The following six registers set the interrupts. • • • • Interrupt Request Flag Register (IRFLAG0, IRFLAG1) Interrupt Request Polarity Control Register (IRPOL) Interrupt Request Mask Register (IRMASKINT, IRMASKEXT) Interrupt Request Control Register (IRRCNT) The following formulas derive the interrupt generation conditions: Internal interrupt request = (|((IRFLAG[15:0] ^ IRPOL[15:0]) & IRMASKINT[15:0]))^ IRRCNT.INTPOL External interrupt request = (|((IRFLAG[15:0] ^ IRPOL[15:0] ) & IRMASKEXT[15:0]))^ IRRCNT.EXTPOL In the above formulas, “^” indicates Exclusive OR operations and “|” indicates reduction operators that perform an OR operation on all bits. Also, the External Interrupt OD Control bit (IRRCNT.OD) of the Interrupt Request Control Register can select whether the external interrupt supply signal is open drain output or totem pole output. IRRCNT.INTPOL IRFLAG[15] IRPOL[15] IRMASK[15] Internal Interrupt Request (0: Request present) External Interrupt Request IRRCNT.EXTPOL Figure 15.3.1 External Interrupt Request Logic 15-8 Chapter 15 Interrupt Controller There are two flag registers: Flag Register 0 (IRFLAG0), and Flag Register 1 (IRFLAG1). These registers have two different Write methods. Accordingly, Writes to one register are reflects in the other. Either “0” or “1” can be written to Flag Register 0 In the case of Flag Register 1 however, “1” can be written from the TX49/H3 core, but “0” cannot be written. On the other hand, bits that wrote “1” are cleared to “0” in the case of access from a device other than the TX49/H3 core (access from an external PCI device for example). The bit value at this time will not change even if “0” is written. This register sends interrupt notification from the TX49/H3 core to external devices. External devices can be used in applications that clear these interrupt notifications. 15-9 Chapter 15 Interrupt Controller 15.4 Registers Table 15.4.1 Interrupt Control Registers Address 0xF600 0xF604 0xF608 0xF610 0xF614 0xF618 0xF61C 0xF620 0xF624 0xF628 0xF62C 0xF640 0xF660 0xF680 0xF6A0 0xF510 0xF514 0xF518 0xF51C 0xF520 0xF524 Register IRDEN IRDM0 IRDM1 IRLVL0 IRLVL1 IRLVL2 IRLVL3 IRLVL4 IRLVL5 IRLVL6 IRLVL7 IRMSK IREDC IRPND IRCS IRFLAG0 IRFLAG1 IRPOL IRRCNT IRMASKINT IRMASKEXT Register Name Interrupt Detection Enable Register Interrupt Detection Mode Register 0 Interrupt Detection Mode Register 1 Interrupt Level Register 0 Interrupt Level Register 1 Interrupt Level Register 2 Interrupt Level Register 3 Interrupt Level Register 4 Interrupt Level Register 5 Interrupt Level Register 6 Interrupt Level Register 7 Interrupt Mask Register Interrupt Edge Detection Clear Register Interrupt Pending Register Interrupt Current Status Register Interrupt Request Flag Register 0 Interrupt Request Flag Register 1 Interrupt Request Polarity Control Register Interrupt Request Control Register Interrupt Request Internal Interrupt Mask Register Interrupt Request External Interrupt Mask Register 15-10 Chapter 15 Interrupt Controller 15.4.1 31 Reserved : Type : Default 15 Reserved 1 0 IDE R/W : Type 0 : Default Interrupt Detection Enable Register (IRDEN) 0xF600 16 Bit(s) 31:1 0 Mnemonic ⎯ IDE Field Name ⎯ Interrupt Control Enable Reserved Explanation Interrupt Detection Enable (Default: 0) Enables interrupt detection. 0: Stop interrupt detection. 1: Start interrupt detection Read/Write ⎯ R/W Figure 15.4.1 Interrupt Detection Enable Register 15-11 Chapter 15 Interrupt Controller 15.4.2 31 IC23 R/W 0 15 IC7 R/W 0 14 13 IC6 R/W 0 Interrupt Detection Mode Register 0 (IRDM0) 30 29 IC22 R/W 0 12 11 IC5 R/W 0 28 27 IC21 R/W 0 10 9 IC4 R/W 0 8 7 IC3 R/W 0 24 Reserved 23 IC19 R/W 0 6 22 0xF604 21 IC18 R/W 0 5 IC2 R/W 0 4 3 IC1 R/W 0 20 19 IC17 R/W 0 2 1 IC0 R/W 0 : Type : Default 18 17 IC16 R/W 0 0 : Type : Default 16 Bits 31:30 Mnemonic IC23 Field Name Interrupt Source Control 23 Explanation Interrupt Source Control 23 (Default: 00) These bits specify the active state of PCIPMC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 22 (Default: 00) These bits specify the active state of PCIERR0 interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 21 (Default: 00) These bits specify the active state of NDFMC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Reserved Interrupt Source Control 19 (Default: 00) These bits specify the active state of TMR[2] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 18 (Default: 00) These bits specify the active state of TMR[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 17 (Default: 00) These bits specify the active state of TMR[0] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Read/Write R/W 29:28 IC22 Interrupt Source Control 22 R/W 27:26 IC21 Interrupt Source Control 21 R/W 25:24 23:22 ⎯ IC19 ⎯ Interrupt Source Control 19 ⎯ R/W 21:20 IC18 Interrupt Source Control 18 R/W 19:18 IC17 Interrupt Source Control 17 R/W Figure 15.4.2 Interrupt Detection Mode Register 0 (1/2) 15-12 Chapter 15 Interrupt Controller Bits 17:16 Mnemonic IC16 Field Name Interrupt Source Control 16 Explanation Interrupt Source Control 16 (Default: 00) These bits specify the active state of PCIC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 7 (Default: 00) These bits specify the active state of external INT[5] interrupts. 00: Low level active 01: High level active 10: Falling edge active 11: Rising edge active Interrupt Source Control 6 (Default: 00) These bits specify the active state of external INT[4] interrupts. 00: Low level active 01: High level active 10: Falling edge active 11: Rising edge active Interrupt Source Control 5 (Default: 00) These bits specify the active state of external INT[3] interrupts. 00: Low level active 01: High level active 10: Falling edge active 11: Rising edge active Interrupt Source Control 4 (Default: 00) These bits specify the active state of external INT[2] interrupts. 00: Low level active 01: High level active 10: Falling edge active 11: Rising edge active Interrupt Source Control 3 (Default: 00) These bits specify the active state of external INT[1] interrupts. 00: Low level active 01: High level active 10: Falling edge active 11: Rising edge active Interrupt Source Control 2 (Default: 00) These bits specify the active state of external INT[0] interrupts. 00: Low level active 01: High level active 10: Falling edge active 11: Rising edge active Interrupt Source Control 1 (Default: 00) These bits specify the active state of TX49 Write Timeout Error interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 0 (Default: 00) These bits specify the active state of ECC Error interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Read/Write R/W 15:14 IC7 Interrupt Source Control 7 R/W 13:12 IC6 Interrupt Source Control 6 R/W 11:10 IC5 Interrupt Source Control 5 R/W 9:8 IC4 Interrupt Source Control 4 R/W 7:6 IC3 Interrupt Source Control 3 R/W 5:4 IC2 Interrupt Source Control 2 R/W 3:2 IC1 Interrupt Source Control 1 R/W 1:0 IC0 Interrupt Source Control 0 R/W Figure 15.4.2 Interrupt Detection Mode Register 0 (2/2) 15-13 Chapter 15 Interrupt Controller 15.4.3 31 IC31 R/W 0 15 IC15 R/W 0 14 13 IC14 R/W 0 Interrupt Detection Mode Register 1 (IRDM1) 30 29 IC30 R/W 0 12 11 IC13 R/W 0 28 27 IC29 R/W 0 10 9 IC12 R/W 0 26 25 IC28 R/W 0 8 7 IC11 R/W 0 24 23 IC27 R/W 0 6 22 0xF608 21 IC26 R/W 0 5 IC10 R/W 0 4 3 IC9 R/W 0 20 19 IC25 R/W 0 2 1 IC8 R/W 0 : Type : Default 18 17 IC24 R/W 0 0 : Type : Default 16 Bit 31:30 Mnemonic IC31 Field Name Interrupt Source Control 31 Explanation Interrupt Source Control 31 (Default: 00, R/W) These bits specify the active state of SPI interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 30 (Default: 00, R/W) These bits specify the active state of DMA1[3] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 29 (Default: 00, R/W) These bits specify the active state of DMA1[2] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 28 (Default: 00, R/W) These bits specify the active state of DMA1[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 27 (Default: 00, R/W) These bits specify the active state of DMA1[0] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 26 (Default: 00, R/W) These bits specify the active state of PCIC1 interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Read/Write R/W 29:28 IC30 Interrupt Source Control 30 R/W 27:26 IC29 Interrupt Source Control 29 R/W 25:24 IC28 Interrupt Source Control 28 R/W 23:22 IC27 Interrupt Source Control 27 R/W 21:20 IC26 Interrupt Source Control 26 R/W Figure 15.4.3 Interrupt Detection Mode Register 1 (1/3) 15-14 Chapter 15 Interrupt Controller Bit 19:18 Mnemonic IC25 Field Name Interrupt Source Control 25 Explanation Interrupt Source Control 25 (Default: 00, R/W) These bits specify the active state of ACLCPME interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 24 (Default: 00, R/W) These bits specify the active state of ACLC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 15 (Default: 00) These bits specify the active state of PDMAC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 14 (Default: 00) These bits specify the active state of IRC interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 13 (Default: 00) These bits specify the active state of DMA0 [3] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 12 (Default: 00) These bits specify the active state of DMA0 [2] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 11 (Default: 00) These bits specify the active state of DMA0 [1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 10 (Default: 00) These bits specify the active state of DMA0 [0] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Read/Write R/W 17:16 IC24 Interrupt Source Control 24 R/W 15:14 IC15 Interrupt Source Control 15 R/W 13:12 IC14 Interrupt Source Control 14 R/W 11:10 IC13 Interrupt Source Control 13 R/W 9:8 IC12 Interrupt Source Control 12 R/W 7:6 IC11 Interrupt Source Control 11 R/W 5:4 IC10 Interrupt Source Control 10 R/W Figure 15.4.3 Interrupt Detection Mode Register 1 (2/3) 15-15 Chapter 15 Interrupt Controller Bit 3:2 Mnemonic IC9 Field Name Interrupt Source Control 9 Explanation Interrupt Source Control 9 (Default: 00) These bits specify the active state of SIO[1] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Interrupt Source Control 8 (Default: 00) These bits specify the active state of SIO[0] interrupts. 00: Low level active 01: Disable 10: Disable 11: Disable Read/Write R/W 1:0 IC8 Interrupt Source Control 8 R/W Figure 15.4.3 Interrupt Detection Mode Register 1 (3/3) 15-16 Chapter 15 Interrupt Controller 15.4.4 31 Reserved Interrupt Level Register 0 (IRLVL0) 27 26 IL17 R/W 000 24 0xF610 23 Reserved 19 18 IL16 R/W 000 : Type : Default 0 IL0 R/W 000 : Type : Default 16 15 Reserved 11 10 IL1 R/W 000 8 7 Reserved 3 2 Bit 31:27 26:24 Mnemonic ⎯ IL17 Field Name ⎯ Interrupt Level 17 Reserved Explanation Interrupt Level of INT [17] (Default: 000) These bits specify the interrupt level of [TMR [0] 000: Interrupt Level 0 (Interrupt disable) 001:Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [16] (Default: 000) These bits specify the interrupt level of PCIC0 interrupts. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [1] (Default: 000) These bits specify the interrupt level for TX49 Write Timeout Error interrupts. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010:Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL16 ⎯ Interrupt Level 16 ⎯ R/W 15:11 10:8 ⎯ IL1 ⎯ Interrupt Level 1 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.4 Interrupt Level Register 0 (1/2) 15-17 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL0 Field Name Interrupt Level 0 Explanation Interrupt Level of INT [0] (Default: 000) These bits specify the interrupt level of ECC Error interrupts. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.5 Interrupt Level Register 0 (2/2) 15-18 Chapter 15 Interrupt Controller 15.4.5 31 Reserved Interrupt Level Register (IRLVL1) 27 26 IL19 R/W 000 24 0xF614 23 Reserved 19 18 IL18 R/W 000 : Type : Default 0 IL2 R/W 000 : Type : Default 16 15 Reserved 11 10 IL3 R/W 000 8 7 Reserved 3 2 Bit 31:27 26:24 Mnemonic ⎯ IL19 Field Name ⎯ Interrupt Level 19 Reserved Explanation Interrupt Level of INT [19] (Default: 000) These bits specify the interrupt level of TMR [2]. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [18] (Default: 000) These bits specify the interrupt level of TMR[1]. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [3] (Default: 000) These bits specify the interrupt level of external INT[1]. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL18 ⎯ Interrupt Level 18 ⎯ R/W 15:11 10:8 ⎯ IL3 ⎯ Interrupt Level 3 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.5 Interrupt Level Register 1 (1/2) 15-19 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL2 Field Name Interrupt Level 2 Explanation Interrupt Level of INT [2] (Default: 000) These bits specify the interrupt level of external INT[0]. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.5 Interrupt Level Register 1 (2/2) 15-20 Chapter 15 Interrupt Controller 15.4.6 31 Reserved Interrupt Level Register 2 (IRLVL2) 27 26 IL21 24 0xF618 23 Reserved : Type : Default 16 15 Reserved 11 10 IL5 R/W 000 8 7 Reserved 3 2 IL4 R/W 000 0 : Type : Default Bit 31:27 26:24 Mnemonic ⎯ IL21 Field Name ⎯ Interrupt Level 21 Reserved Explanation Interrupt Level of INT [21] (Default: 000) These bits specify the interrupt level of NDFMC. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [5] (Default: 000) These bits specify the interrupt level of external INT[3] / ETHERC1. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [4] (Default: 000) These bits specify the interrupt level of external INT[2]. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write ⎯ R/W 23:11 10:8 ⎯ IL5 ⎯ Interrupt Level 5 ⎯ R/W 7:3 2:0 ⎯ IL4 ⎯ Interrupt Level 4 ⎯ R/W Figure 15.4.6 Interrupt Level Register 2 15-21 Chapter 15 Interrupt Controller 15.4.7 31 Reserved Interrupt Level Register 3 (IRLVL3) 27 26 IL23 R/W 000 24 0xF61C 23 Reserved 19 18 IL22 R/W 000 : Type : Default 0 IL6 R/W 000 : Type : Default 16 15 Reserved 11 10 IL7 R/W 000 8 7 Reserved 3 2 Bit 31:27 26:24 Mnemonic ⎯ IL23 Field Name ⎯ Interrupt Level 23 Reserved Explanation Interrupt Level of INT [23] (Default: 000) These bits specify the interrupt level of PCIPME0 interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [22] (Default: 000) These bits specify the interrupt level of PCIERR0 interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [7] (Default: 000) These bits specify the interrupt level of external INT[5]. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL22 ⎯ Interrupt Level 22 ⎯ R/W 15:11 10:8 ⎯ IL7 ⎯ Interrupt level 7 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.7 Interrupt Level Register 3 (1/2) 15-22 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL6 Field Name Interrupt level 6 Explanation Interrupt Level of INT [6] (Default: 000) These bits specify the interrupt level of external INT[4] / ETHERC0. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.7 Interrupt Level Register 3 (2/2) 15-23 Chapter 15 Interrupt Controller 15.4.8 31 Reserved Interrupt Level Register 4 (IRLVL4) 27 26 IL25 R/W 000 24 0xF620 23 Reserved 19 18 IL24 R/W 000 : Type : Default 0 IL8 R/W 000 : Type : Default 16 15 Reserved 11 10 IL9 R/W 000 8 7 Reserved 3 2 Bit 31:27 26:24 Mnemonic ⎯ IL25 Field Name ⎯ Interrupt level 25 Reserved Explanation Interrupt Level of INT [25] (Default: 000, R/W) These bits specify the interrupt level of ACLCPME interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [24] (Default: 000, R/W) These bits specify the interrupt level of ACLC interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [9] (Default: 000) These bits specify the interrupt level of SIO [1] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL24 ⎯ Interrupt level 24 ⎯ R/W 15:11 10:8 ⎯ IL9 ⎯ Interrupt level 9 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.8 Interrupt Level Register 4 (1/2) 15-24 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL8 Field Name Interrupt level 8 Explanation Interrupt Level of INT [8] (Default: 000) These bits specify the interrupt level of SIO [0] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.8 Interrupt Level Register 4 (2/2) 15-25 Chapter 15 Interrupt Controller 15.4.9 31 Reserved Interrupt Level Register 5 (IRLVL5) 27 26 IL27 R/W 000 24 23 0xF624 19 Reserved 18 IL26 R/W 000 : Type : Default 0 IL10 R/W 000 : Type : Default 16 15 Reserved 11 10 IL11 R/W 000 8 7 Reserved 3 2 Bit 31:27 26:24 Mnemonic ⎯ IL27 Field Name ⎯ Interrupt level 27 Reserved Explanation Interrupt Level of INT [27] (Default: 000) These bits specify the interrupt level of DMA1 [0] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [26] (Default: 000) These bits specify the interrupt level of PCIC1 interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [11] (Default: 000) These bits specify the interrupt level of DMA0 [1] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL26 ⎯ Interrupt level 26 ⎯ R/W 15:11 10:8 ⎯ IL11 ⎯ Interrupt level 11 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.9 Interrupt Level Register 5 (1/2) 15-26 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL10 Field Name Interrupt Level 10 Explanation Interrupt Level of INT [10] (Default: 000) These bits specify the interrupt level of DMA0 [0] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.9 Interrupt Level Register 5 (2/2) 15-27 Chapter 15 Interrupt Controller 15.4.10 Interrupt Level Register 6 (IRLVL6) 31 Reserved 27 26 IL29 R/W 000 15 Reserved 11 10 IL13 R/W 000 8 7 Reserved 3 2 IL12 R/W 000 : Type : Default 24 0xF628 23 Reserved 19 18 IL28 R/W 000 0 : Type : Default 16 Bit 31:27 26:24 Mnemonic ⎯ IL29 Field Name ⎯ Interrupt level 29 Reserved Explanation Interrupt Level of INT [29] (Default: 000) These bits specify the interrupt level of DMA1 [2] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [28] (Default: 000) These bits specify the interrupt level of DMA1 [1] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [13] (Default: 000) These bits specify the interrupt level of DMA0 [3] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL28 ⎯ Interrupt level 28 ⎯ R/W 15:11 10:8 ⎯ IL13 ⎯ Interrupt level 13 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.10 Interrupt Level Register 6 (1/2) 15-28 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL12 Field Name Interrupt level 12 Explanation Interrupt Level of INT [12] (Default: 000) These bits specify the interrupt level of DMA0 [2] interrupts. 000: Interrupt level 0 (Interrupt disable) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.10 Interrupt Level Register 6 (2/2) 15-29 Chapter 15 Interrupt Controller 15.4.11 Interrupt Level Register 7 (IRLVL7) 31 Reserved 27 26 IL31 R/W 000 15 Reserved 11 10 IL15 R/W 000 8 7 Reserved 3 2 IL14 R/W 000 : Type : Default 24 0xF62C 23 Reserved 19 18 IL30 R/W 000 0 : Type : Default 16 Bit 31:27 26:24 Mnemonic ⎯ IL31 Field Name ⎯ Interrupt level 31 Reserved Explanation Interrupt Level of INT [31] (Default: 000) These bits specify the interrupt level of SPI interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [30] (Default: 000) These bits specify the interrupt level of DMA1[3] interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Interrupt Level of INT [15] (Default: 000) These bits specify the interrupt level of PDMAC interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Reserved Read/Write ⎯ R/W 23:19 18:16 ⎯ IL31 ⎯ Interrupt level 30 ⎯ R/W 15:11 10:8 ⎯ IL15 ⎯ Interrupt level 15 ⎯ R/W 7:3 ⎯ ⎯ ⎯ Figure 15.4.11 Interrupt Level Register 7 (1/2) 15-30 Chapter 15 Interrupt Controller Bit 2:0 Mnemonic IL14 Field Name Interrupt Level 14 Explanation Interrupt Level of INT [14] (Default: 000) These bits specify the interrupt level of IRC interrupts. 000: Interrupt level 0 (Interrupt disabled) 001: Interrupt level 1 010: Interrupt level 2 011: Interrupt level 3 100: Interrupt level 4 101: Interrupt level 5 110: Interrupt level 6 111: Interrupt level 7 Read/Write R/W Figure 15.4.11 Interrupt Level Register 7 (2/2) 15-31 Chapter 15 Interrupt Controller 15.4.12 Interrupt Mask Level Register (IRMSK) 31 Reserved : Type : Default 15 Reserved 3 2 IML R/W 0 : Type : Default 0 0xF640 16 Bit 31:3 2:0 Mnemonic ⎯ IML Field Name ⎯ Interrupt Mask Level Reserved Explanation Interrupt Mask Level (Default: 000) These bits specify the interrupt mask level. Masks interrupts with a mask level equal to or lower than the set mask level. 000: Interrupt mask level 0 (No interrupts masked) 001: Interrupt mask level 1 (Levels 2-7 enabled) 010: Interrupt mask level 2 (Levels 3-7 enabled) 011: Interrupt mask level 3 (Levels 4-7 enabled) 100: Interrupt mask level 4 (Levels 5-7 enabled) 101: Interrupt mask level 5 (Levels 6-7 enabled) 110: Interrupt mask level 6 (Level 7 enabled) 111: Interrupt mask level 7 (Interrupts disabled) Read/Write ⎯ R/W Figure 15.4.12 Interrupt Mask Register 15-32 Chapter 15 Interrupt Controller 15.4.13 Interrupt Edge Detection Clear Register (IREDC) 31 Reserved : Type : Default 15 Reserved 9 8 EDCE0 RW1C 0xF660 16 7 Reserved 4 3 EDCS0 R/W 0000 0 0 : Type : Default Bit 31:9 8 Mnemonic ⎯ EDCE0 Field Name ⎯ Edge Detection Clear Enable 0 Reserved Explanation Edge Detection Clear Enable 0 (Default: 0) Clears edge detection of interrupts specified by the EDCS0 field. 0: Does not clear. 1: Clears. Value always becomes “0” when this bit is read. Reserved Edge Detection Clear Source 0 (Default: 0x0) These bits specify the interrupt source to be cleared. 1111: Reserved 1110: Reserved 1101: Reserved 1100: Reserved 1011: Reserved 1010: Reserved 1001: Reserved 1000: Reserved 0111: External INT [5] interrupt 0110: External INT [4] interrupt 0101: External INT [3] interrupt 0100: External INT [2] interrupt 0011: External INT [1] interrupt 0010: External INT [0] interrupt 0001: Reserved 0000: Reserved Read/Write ⎯ R/W1C 7:4 3:0 ⎯ EDCS0 ⎯ Edge Detection Clear Source 0 ⎯ R/W Figure 15.4.13 Interrupt Status Control Register 15-33 Chapter 15 Interrupt Controller 15.4.14 Interrupt Pending Register (IRPND) 0xF680 Indicates the status of each interrupt request regardless of the IRLVL 7-0 and IRMSK value. 31 IS31 R 0 15 IS15 R 0 30 IS30 R 0 14 IS14 R 0 29 IS29 R 0 13 IS13 R 0 28 IS28 R 0 12 IS12 R 0 27 IS27 26 IS26 25 IS25 R 0 9 IS9 R 0 24 IS24 R 0 8 IS8 R 0 23 IS23 R 0 7 IS7 R 0 22 IS22 R 0 6 IS6 R 0 21 IS21 R 0 5 IS5 R 0 20 Reserved 19 IS19 R 0 18 IS18 R 0 2 IS2 R 0 17 IS17 R 0 1 IS1 R 0 16 IS16 R 0 0 IS0 R 0 : Type : Default : Type : Default R 0 11 IS11 R 0 R 0 10 IS10 R 0 4 IS4 R 0 3 IS3 R 0 Bit 31 Mnemonic IS31 Field Name Interrupt Status 31 Explanation IRINTREQ [31] Status (Default: 0, R) This bit indicates the SPI interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [30] Status (Default: 0, R) This bit indicates the DMA1[3] interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [29] Status (Default: 0, R) This bit indicates the DAM1[2] interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [28] Status (Default: 0, R) This bit indicates the DMA1[1] interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [27] Status (Default: 0, R) This bit indicates the DMA1[0] interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [26] Status (Default: 0, R) This bit indicates the PCIC1 interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [25] Status (Default: 0, R) This bit indicates the ACLCPME interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [24] Status (Default: 0, R) This bit indicates the ACLC interrupt status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [23] status This bit indicates the PCIPMC interrupt status 1: Interrupt requests 0: No interrupt requests Read/Write R 30 IS30 Interrupt Status 30 R 29 IS29 Interrupt Status 29 R 28 IS28 Interrupt Status 28 R 27 IS27 Interrupt Status 27 R 26 IS26 Interrupt Status 26 R 25 IS25 Interrupt Status 25 R 24 IS24 Interrupt Status 24 R 23 IS23 Interrupt Status 23 R Figure 15.4.14 Interrupt Source Status Register (1/3) 15-34 Chapter 15 Interrupt Controller Bit 22 Mnemonic IS22 Field Name Interrupt Status 22 Explanation IRINTREQ [22] status This bit indicates the PCIERR error status. 1: Interrupt requests 0: No interrupt requests IRINTREQ [21] status This bit indicates the NDFMC interrupt status. 1: Interrupt requests 0: No interrupt requests Read/Write R 21 IS21 Interrupt Status 21 R 20 19 ⎯ IS19 ⎯ Interrupt Status 19 Reserved IRINTREQ [19] status This bit indicates the TMR [2] interrupt status. 1: Interrupt requests 0: No interrupt requests R ⎯ 18 IS18 Interrupt Status 18 IRINTREQ [18] status This bit indicates the TMR [1] interrupt status. 1: Interrupt requests 0: No interrupt requests R 17 IS17 Interrupt Status 17 IRINTREQ [17] status This bit indicates the TMR[0] interrupt status 1: Interrupt requests 0: No interrupt requests R 16 IS16 Interrupt Status 16 IRINTREQ [16] status This bit indicates the PCIC interrupt status 1: Interrupt requests 0: No interrupt requests R 15 IS15 Interrupt Status 15 IRINTREQ [15] status This bit indicates the PDMAC interrupt status. 1: Interrupt requests 0: No interrupt requests R 14 IS14 Interrupt Status 14 IRINTREQ [14] status This bit indicates the IRC interrupt status 1: Interrupt requests 0: No interrupt requests R 13 IS13 Interrupt Status 13 IRINTREQ [13] status This bit indicates the DMA [3] interrupt status 1: Interrupt requests 0: No interrupt requests R 12 IS12 Interrupt Status 12 IRINTREQ [12] status This bit indicates the status of DMA [2] interrupts. 1: Interrupt requests 0: No interrupt requests R 11 IS11 Interrupt Status 11 IRINTREQ [11] status This bit indicates the status of DMA [1] interrupts. 1: Interrupt requests 0: No interrupts requests R 10 IS10 Interrupt Status 10 IRINTREQ [10] status This bit indicates the status of DMA [0] interrupts. 1: Interrupt requests 0: No interrupt requests R Figure 15.4.14 Interrupt Source Status Register (2/3) 15-35 Chapter 15 Interrupt Controller Bit 9 Mnemonic IS9 Field Name Interrupt Status 9 IRINTREQ [9] status Explanation This bit indicates the status of SIO [1] interrupts. 1: Interrupt requests 0: No interrupt requests Read/Write R 8 IS8 Interrupt Status 8 IRINTREQ [8] status This bit indicates the status of SIO [0] interrupts. 1: Interrupt requests 0: No interrupt requests R 7 IS7 Interrupt Status 7 IRINTREQ [7] status This bit indicates the status of external INT [5] interrupts. 1: Interrupt requests 0: No interrupt requests R 6 IS6 Interrupt Status 6 IRINTREQ [6] status This bit indicates the status of external INT [4] interrupts. 1: Interrupt requests 0: No interrupt requests R 5 IS5 Interrupt Status 5 IRINTREQ [5] status This bit indicates the status of external INT [3] interrupts. 1: Interrupt requests 0: No interrupt requests R 4 IS4 Interrupt Status 4 IRINTREQ [4] status This bit indicates the status of external INT [2] interrupts. 1: Interrupt requests 0: No interrupt requests R 3 IS3 Interrupt Status 3 IRINTREQ [3] status This bit indicates the status of external INT [1] interrupts. 1: Interrupt requests 0: No interrupt requests R 2 IS2 Interrupt Status 2 IRINTREQ [2] status This bit indicates the status of external INT [0] interrupts. 1: Interrupt requests 0: No interrupt requests R 1 IS1 Interrupt Status 1 IRINTREQ [1] status This bit indicates the status of TX49 Write Timeout Error interrupts. 1: Interrupt requests 0: No interrupt requests R 0 IS0 Interrupt Status 0 IRINTREQ [0] status This bit indicates the status of ECC Error interrupts. 1: Interrupt requests 0: No interrupt requests R Figure 15.4.14 Interrupt Source Status Register (3/3) 15-36 Chapter 15 Interrupt Controller 15.4.15 Interrupt Current Status Register (IRCS) 31 Reserved 0xF6A0 17 16 IF R 1 : Type : Default 15 Reserved 11 10 LVL R 000 8 7 Reserved 5 4 CAUSE R 11111 0 : Type : Default Bit 31:17 16 Mnemonic ⎯ IF Field Name ⎯ Interrupt Flag Reserved Interrupt Flag (Default: 1) Explanation Read/Write ⎯ R This bit indicates the interrupt generation status. 0: Interrupt requests have been generated. 1: Interrupt requests have not been generated 15:11 10:8 ⎯ LVL ⎯ Interrupt Level Reserved Interrupt Level (Default: 000) These bits specify the level of the interrupt request that was reported to the TX49/H3 core. This field becomes undefined if no interrupt request is pending (i.e., the IF bit is set). 000: Interrupt level 0 001: Interrupt level 1 : 7:5 ⎯ ⎯ Reserved : ⎯ 111: Interrupt level 7 R ⎯ Figure 15.4.15 Interrupt Current Status Register (1/2) 15-37 Chapter 15 Interrupt Controller Bit 4:0 Mnemonic CAUSE Field Name Interrupt Cause Explanation Interrupt Cause (Default: 0x1F) These bits specify the interrupt cause that was reported to the TX49/H3 core. This field becomes undefined if no interrupt request is pending (i.e., the IF bit is set). 00000: ECC Error 00001: TX49 Write Timeout Error 00010: External INT [0] interrupt 00011: External INT [1] interrupt 00100: External INT [2] interrupt 00101: External INT [3] interrupt 00110: External INT [4] interrupt 00111: External INT [5] interrupt 01000: SIO [0] interrupt 01001: SIO [1] interrupt 01010: DMA0 [0] interrupt 01011: DMA0 [1] interrupt 01100: DMA0 [2] interrupt 01101: DMA0 [3] interrupt 01110: IRC interrupt 01111: PDMAC0 interrupt 10000: PCIC0 interrupt 10001: TMR [0] interrupt 10010: TMR [1] interrupt 10011: TMR [2] interrupt 10100: (Reserved) 10101: NDFMC interrupt 10110: PCIERR interrupt 10111: PCIPME interrupt 11000: ACLC interrupt 11001: ACLCPME interrupt 11010: PCIC1 interrupt 11011: DMA1[0] interrupt 11100: DMA1[1] interrupt 11101: DMA1[2] interrupt 11110: DMA1[3] interrupt 11111: SPI interrupt Read/Write R Figure 15.4.15 Interrupt Current Status Register (2/2) 15-38 Chapter 15 Interrupt Controller 15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 31 Reserved : Type : Default 15 PF0 [15] 14 PF0 [14] 13 PF0 [13] 12 PF0 [12] 11 PF0 [11] 10 PF0 [10] 9 PF0 [9] 8 PF0 [8] 7 PF0 [7] 6 PF0 [6] 5 PF0 [5] 4 PF0 [4] 3 PF0 [3] 2 PF0 [2] 1 PF0 [1] 0 PF0 [0] : Type : Default 0xF510 16 R/W 0x0000 Bit 31:16 15:0 Mnemonic ⎯ PF0 [15:0] Field Name ⎯ Flag 0 Reserved Explanation Interrupt Request Flag 0 [15:0] (Default: 0x0000) Changes made to this register are reflected in Flag Register 1 also since they are the same registers. The bits in this field accept writes of both 1s and 0s. Read/Write ⎯ R/W Figure 15.4.16 Interrupt Request Flag Register 0 15-39 Chapter 15 Interrupt Controller 15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 31 Reserved : Type : Default 15 PF1 [15] 14 PF1 [14] 13 PF1 [13] 12 PF1 [12] 11 PF1 [11] 10 PF1 [10] 9 PF1 [9] 8 PF1 [8] 7 PF1 [7] 6 PF1 [6] 5 PF1 [5] 4 PF1 [4] 3 PF1 [3] 2 PF1 [2] 1 PF1 [1] 0 PF1 [0] : Type : Default 0xF514 16 R/W 0x0000 Bit 31:16 15:0 Mnemonic ⎯ PF1 [15:0] Field Name ⎯ Flag 1 Reserved Explanation Interrupt Request Flag 1 [15:0] (Default: 0x0000) Changes made to this register are reflected in Flag Register 0 also since they are the same registers. Writes to Flag Register 1 operate as follows: Write Write from the TX49/H3 core 1: Set the flag bit 0: No change Write from other devices (DMAC, PCIC) 1: Clear the flag bit 0: No change Read: Read the flag bit Read/Write ⎯ R/W Figure 15.4.17 Interrupt Request Flag Register 1 15-40 Chapter 15 Interrupt Controller 15.4.18 Interrupt Request Polarity Control Register (IRPOL) 31 Reserved : Type : Default 15 FPC [15] 14 FPC [14] 13 FPC [13] 12 FPC [12] 11 FPC [11] 10 FPC [10] 9 FPC [9] 8 FPC [8] 7 FPC [7] 6 FPC [6] 5 FPC [5] 4 FPC [4] 3 FPC [3] 2 FPC [2] 1 FPC [1] 0 FPC [0] : Type : Default 0xF518 16 R/W 0x0000 Bit 31:16 15:0 Mnemonic ⎯ FPC [15:0] Field Name ⎯ Flag Polarity Control Reserved Explanation Flag Polarity Control [15:0] (Default: 0x0000) These bits specify the polarity of the flag bit that generated the interrupt. An interrupt request is generated when the XOR of the FPC bit and the flag bit is “1.” Flag bit (PF) 0 0 1 1 FPC bit 0 1 0 1 Interrupt request No Yes Yes No Read/Write ⎯ R/W Figure 15.4.18 Interrupt Requests Polarity Control Register 15-41 Chapter 15 Interrupt Controller 15.4.19 Interrupt Request Control Register (IRRCNT) 31 Reserved : Type : Default 15 Reserved 3 2 ODC 0xF51C 16 1 0 EXTPOL INTPOL R/W 0 R/W 1 R/W : Type 1 : Default Bit 31:3 2 Mnemonic ⎯ ODC Field Name ⎯ External Interrupt OD Control Reserved Explanation External Interrupt Open Drain Control (Default: 0) This bit specifies whether to make the external interrupt signal (IRC[2]*) an open drain pin or not. 0: Open drain (reset) 1: Totem pole Read/Write ⎯ R/W 1 EXTPOL External Interrupt Request Polarity Control External Interrupt Polarity Control (Default: 1) This bit specifies the polarity of external interrupt requests. 0: Do not reverse polarity of interrupt requests. 1: Reverse polarity of interrupt requests Internal Interrupt Polarity Control (Default: 1) This bit specifies the polarity of internal interrupt requests. 0: Do not reverse polarity of interrupt requests. 1: Reverse polarity of interrupt requests R/W 0 INTPOL Internal Interrupt Request Polarity Control R/W Figure 15.4.19 Interrupt Request Control Register 15-42 Chapter 15 Interrupt Controller 15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 31 Reserved : Type : Default 15 [15] 14 [14] 13 [13] 12 [12] 11 [11] 10 [10] 9 [9] 8 [8] 7 [7] 6 [6] 5 [5] 4 [4] 3 [3] 2 [2] 1 [1] 0 [0] : Type : Default MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT MINT R/W 0x0000 0xF520 16 Bit 31:16 15:0 Mnemonic ⎯ MINT [15:0] Field Name ⎯ Internal Request Mask Reserved Explanation Internal Interrupt Mask (Default: 0x0000) These bits specify whether to use the corresponding flag bit as an internal interrupt cause. Interrupt causes are masked when this bit is “0.” 0: Mask (Reset) 1: Do not mask Read/Write ⎯ R/W Figure 15.4.20 Interrupt Request Internal Interrupt Mask Register 15-43 Chapter 15 Interrupt Controller 15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524 31 Reserved : Type : Default 15 [15] 14 [14] 13 [13] 12 [12] 11 [11] 10 [10] 9 [9] 8 [8] 7 [7] 6 [6] 5 [5] 4 [4] 3 [3] 2 [2] 1 [1] 0 [0] : Type : Default MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT MEXT R/W 0x0000 16 Bit 31:16 15:0 Mnemonic ⎯ MEXT [15:0] Field Name ⎯ External Request Mask Reserved Explanation Read/Write ⎯ R/W External Interrupt Mask (Default: 0x0000) These bits specify whether to use the corresponding flag bit as an external interrupt cause. Interrupt causes are masked when this bit is “0.” 0: Mask (reset) 1: Do not mask Figure 15.4.21 Interrupt Request External Interrupt Mask Register 15-44 Chapter 16 Ethernet Controller 16. Ethernet Controller 16.1 Features Mounted in the TX4938 is a 2-channel 10/100 Mbps Ethernet Controller. This Ethernet Controller has circuits equivalent to the Toshiba TC35815CF (but partially modified) built in. 16.2 Block diagram G-Bus PCI Controller Ethernet Controller Bus Control Layer Bus Master Burst Clock 33/66 MHz 32-bit PCI Clock Bus Slave Clock PCI Config Register BII DMA Layer DMA Tx Block DMA SRAM DMA Rx Block DMA Control Status Register DII MAC Layer ARC Flow Control MAC Tx Block MAC Tx FIFO MAC Control Status Register MAC Rx FIFO MAC Rx Block MII I/F PHY Layer 10BASE-TPHY or 100BASE-XPHY Figure 16.2.1 Ethernet Controller Block Diagram 16-1 Chapter 16 Ethernet Controller 16.3 Detailed explanation 16.3.1 Accessing the Ethernet Controller The Ethernet Controller is connected to the chip-internal PCI Bus. The chip-internal PCI Bus is connected to the G-Bus via the PCI Controller (PCIC1). Therefore, you access the Ethernet Controller via PCI Controller 1. PCI Controller 1 is a circuit that is equivalent to the PCI Controller (PCIC0) in Chapter 10. The Ethernet Controller only supports the PCI Controller 1 functions that it requires to operate. Following are the differences with PCIC0. • • • • • • Host mode only. (Does not support the Satellite mode.) Does not support EEPROM for Config data storage Does not support an external PCI arbiter Does not support type 1 configuration Does not support the Interrupt Acknowledge command Does not support the Special Cycle command 16.3.1.1 PCI Controller 1 control registers Table 16.3.1 lists the PCI Controller 1 registers. For the details of each register or the operation of the PCI Controller, see Chapter 10. Table 16.3.1 PCI Controller Control Registers (1/2) Reference 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 Address 0x7000 0x7004 0x7008 0x700C 0x7010 0x7014 Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Mnemonic PCIID PCISTATUS PCICCREV PCICFG1 P2GM0PLBASE Register Name ID Register (Device ID, Vendor ID) PCI Status, Command Register Class Code, Revision ID Register (Class Code, Revision ID) PCI Configuration 1 Register (BIST, Header Type, Latency Timer, Cache Line Size) P2G Memory Space 0 PCI Lower Base Address Register (Base Address 0 Lower) Reserved P2G Memory Space 1 PCI Lower Base Address Register (Base Address 1 Lower) Reserved P2G Memory Space 2 PCI Base Address Register (Base Address 2) P2G I/O Space PCI Base Address Register (Base Address 3) Subsystem ID Register (Subsystem ID, Subsystem Vendor ID) Capabilities Pointer Register (Capabilities Pointer) PCI Configuration 2 Register (Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line) G2P Timeout Count Register (Retry Timeout Value, TRDY Timeout Value) G2P Status Register G2P Interrupt Mask Register Reserved PCI Status Interrupt Mask Register 10.4.7 0x7018 0x701C P2GM1PLBASE 10.4.9 10.4.10 10.4.11 10.4.12 10.4.13 10.4.14 10.4.15 10.4.16 10.4.18 0x7020 0x7024 0x702C 0x7034 0x703C 0x7040 0x7080 0x7084 0x7088 0x708C P2GM2PBASE P2GIOPBASE PCISID PCICAPPTR PCICFG2 G2PTOCNT G2PSTATUS G2PMASK PCIMASK 16-2 Chapter 16 Ethernet Controller Table 16.3.1 PCI Controller Control Registers (2/2) Reference 10.4.19 10.4.20 10.4.21 10.4.22 10.4.23 10.4.24 10.4.25 10.4.26 10.4.27 10.4.28 10.4.29 10.4.30 10.4.31 10.4.32 10.4.33 10.4.34 10.4.35 10.4.36 10.4.37 10.4.38 10.4.39 10.4.40 10.4.41 10.4.42 10.4.43 10.4.44 10.4.45 10.4.46 10.4.47 10.4.48 10.4.49 10.4.50 10.4.51 10.4.52 10.4.53 Address 0x7090 0x7094 0x7098 0x709C 0x7100 0x7104 0x7108 0x710C 0x7110 0x7114 0x7118 0x711C 0x7120 0x7128 0x7130 0x7138 0x7140 0x7144 0x7148 0x714C 0x7150 0x7158 0x7160 0x7168 0x7170 0x7174 0x7178 0x7180 0x7188 0x7190 0x7198 0x71A0 0x71A4 0x71C8 0x71CC 0x71D07228 Size 32 32 32 32 32 32 32 32 32 32 32 32 64 64 64 64 32 32 32 32 64 64 64 64 32 32 32 64 64 64 64 32 32 32 32 - Mnemonic P2GCFG P2GSTATUS P2GMASK P2GCCMD PBAREQPORT PBACFG PBASTATUS PBAMASK PBABM PBACREQ PBACGNT PBACSTATE G2PM0GBASE G2PM1GBASE G2PM2GBASE G2PIOGBASE G2PM0MASK G2PM1MASK G2PM2MASK G2PIOMASK G2PM0PBASE G2PM1PBASE G2PM2PBASE G2PIOPBASE PCICCFG PCICSTATUS PCICMASK P2GM0GBASE P2GM1GBASE P2GM2GBASE P2GIOGBASE G2PCFGADRS G2PCFGDATA G2PINTACK G2PSPC P2G Status Register Register Name P2G Configuration Register P2G Interrupt Mask Register P2G Current Command Register PCI Bus Arbiter Request Report Register PCI Bus Arbiter Configuration Register PCI Bus Arbiter Status Register PCI Bus Arbiter Interrupt Mask Register PCI Bus Arbiter Broken Master Register PCI Bus Arbiter Current Request Register (for diagnostics) PCI Bus Arbiter Current Grant Register (for diagnostics) PCI Bus Arbiter Current State Register (for diagnostics) G2P Memory Space 0 G-Bus Base Address Register G2P Memory Space 1 G-Bus Base Address Register G2P Memory Space 2 G-Bus Base Address Register G2P I/O Space G-Bus Base Address Register G2P Memory Space 0 Address Mask Register G2P Memory Space 1 Address Mask Register G2P Memory Space 2 Address Mask Register G2P I/O Space Address Mask Register G2P Memory Space 0 PCI Base Address Register G2P Memory Space 1 PCI Base Address Register G2P Memory Space 2 PCI Base Address Register G2P I/O Space PCI Base Address Register PCI Controller Configuration Register PCI Controller Status Register PCI Controller Interrupt Mask Register P2G Memory Space 0 G-Bus Base Address Register P2G Memory Space 1 G-Bus Base Address Register P2G Memory Space 2 G-Bus Base Address Register P2G I/O Space G-Bus Base Address Register G2P Configuration Address Register G2P Configuration Data Register G2P Interrupt Acknowledge Data Register G2P Special Cycle Data Register Reserved 16-3 Chapter 16 Ethernet Controller 16.3.1.2 Interrupt signaling PCI Controller 1 signals the following interrupt to the Interrupt Controller (IRC): PCIC1 Interrupt (Interrupt Number: 26, PCIC1INT) This interrupt is similar to a combination of four PCI Controller 0 interrupt signals into a single interrupt signal. For the content of each interrupt, see subsection 10.3.11. The Ethernet Controller signals the following interrupts to the Interrupt Controller (IRC): Ethernet Channel 0 Interrupt (Interrupt Number: 6) Ethernet Channel 1 Interrupt (Interrupt Number: 5) For the content of these interrupts, see 16.4.3.9 Interrupt Source Register. 16.3.1.3 IDSEL signal connections Internal PCI Bus AD (Address, Data) signals are connected to Ethernet Controller 0, 1 IDSEL signals. Each connection destination follows below. Ethernet Channel 0 IDSEL signal: Internal PCI Bus AD[31] Ethernet Channel 1 IDSEL signal: Internal PCI Bus AD[30] 16.3.1.4 On-chip PCI bus clock frequency The on-chip PCI bus can be programmed to operate at one half or one fourth of the GBUSCLK frequency. Apply a logic High to ADD[16] at boot time to set the on-chip PCI bus clock frequency to one fourth of GBUSCLK. When it is necessary to increase the on-chip PCI bus clock frequency to one half of GBUSCLK, program the relevant register bits in the following order: 1. 2. 3. 4. Set the PCIC1RST bit in the Clock Control (CLKCTR) register to 1. This asserts the reset signals to the PCIC1, ETHER0 and ETHER1 modules. Set PCI1-66 bit in the Chip Configuration (CCFG) register to 1. Set the PCI1DMD bit in the Chip Configuration (CCFG) register to 1. Clear the PCIC1RST bit in the Clock Control (CLKCTR) register to 0. This asserts the reset signals to the PCIC1, ETHER0 and ETHER1 modules. 16.3.2 Data structure The Ethernet Controller exchanges control information and data using the following data structure. • • • Frame Descriptors Buffer Descriptors Data Buffer Figure 16.3.1 shows the relationships of the above data structures. A frame descriptor consists of a 4-byte pointer that points to the next frame, a field dedicated to a system or application program, a frame status field, a control field for all frames, and a corresponding group buffer descriptor. The buffer descriptor contains a pointer to the data buffer and buffer control information. The data buffer is a data storage area in Byte units that is stored in either the Little Endian or Big Endian order. For details on these data structures, see 16.3.7 Memory configuration. 16-4 Chapter 16 Ethernet Controller The DMA engine responds to the transfer of data that is positioned at the byte boundaries. Frame descriptors must be aligned to 16-Byte boundaries. Also, buffer descriptors must be aligned to 8-Byte boundaries. The DMA engine Burst transfers 4-Byte aligned data as much as possible. However, whether data buffers are aligned to 4-Byte boundaries or not does not have much effect on performance. The DMA engine accesses only words or parts of words not aligned to 4-Byte boundaries at the start and end of Block transfer. Part way through Block transfer however, the DMA engine performs wordunit 4-Byte access. Q ueue Access Head Tail Fram e Descriptor Next System FStatus Control Data BStatus Data BStatus Data BStatus Next System FStatus Control Data BStatus Data BStatus Next System FStatus Control Data BStatus Data BStatus Data BStatus ... Buffer Descriptor Data Buffer Figure 16.3.1 Data Structure Outline 16.3.3 System control model The Ethernet Controller as two programmable modes: the Interrupt Drive mode and the Polling mode. • • Interrupt Drive mode This mode generates an interrupt each time a packet or group packet transmits or receives. Polling mode This mode always polls to see if there is a subsequent packet to transmit or receive. When data or a descriptor is added to the frame descriptor queue, the Ethernet Controller performs transmission. The Host CPU checks the status of the frame descriptor for the received packet and judges reception completion. The CPU does not use an interrupt. By enabling or disabling interrupts for each frame descriptor, the Ethernet Controller can arrange the stage layout to enable the handling of multiple packets between interrupts. In this way, the ability of the system to handle multiple packets at once and to cache the handling instructions makes it possible to reduce interrupt handling overhead and improve performance. Furthermore, unless major errors occur, you can set the Ethernet Controller to not issue interrupts. In this situation, you have to put several controls in the Enable state so start/end of traffic and polling in the Idle state is handled efficiently. For details, see 16.3.9 DMA Operation. 16-5 Chapter 16 Ethernet Controller 16.3.4 Functional overview Figure 16.2.1 is a diagram of the entire Ethernet system. Figure 16.3.2 and Figure 16.3.3 are more detailed function block diagrams of the Ethernet Controller. Figure 16.3.2 is a function block diagram of DMA. Figure 16.3.3 is a function block diagram of MAC. G-Bus PCIC PCI Address Data PCI Config Register PCI I/O Control PCI Slave PCI Master Pipe Register PCI Bus/DMA Buffer Arbiter BII DMA Reception Consumer Control Status Register DMA Transmission Producer DMA Reception Buffer DMA Transmission Buffer 32 32 DMA Reception Producer 8 8 DMA Transmission Consumer DII Figure 16.3.2 DMA Function Block 16-6 Chapter 16 Ethernet Controller Figure 16.3.2 and Figure 16.3.3 both show the relationship with the DMA-independent interface (DII). DII is an internal interface that has simple handshake signals and interfaces MAC-internal FIFO with the DMA block-internal DMA buffer. The two FIFOs in the MAC are 1 Byte wide. The DMA block contains DMA buffers that are wider and deeper than MAC. Figure 16.3.2 shows the relationship with the bus-independent interface (BII). The BII is an internal interface that has Bus Request/Bus Grant protocols for Burst access performed by the Bus Master. The BII makes it possible to connect the DMA engine to a 32-bit PCI Bus Controller or another bus controller. 16.3.4.1 Overview of PCI and DMA Figure 16.3.2 shows the PCI Bus configuration, blocks that perform control, DMA buffer and data exchange. • • • • PCI I/O Control Block Generates and acknowledges PCI control signals. PCI Slave Control Block Acknowledges and controls transactions when the Ethernet Controller is the target device. PCI Master Control Block Starts and controls transactions requested by the DMA engine of the Ethernet Controller. PCI Pipe Register Group Buffers data so the DMA engine can continue Burst transfer with 1-1-1-1 timing over a long period of time. PCI Configuration Register Flexibly performs PCI system setup. DMA Control Status Register Sets up and controls DMA. Arbiter Block Arbitrates access to the PCI Bus or the DMA buffer. Producer Block, Consumer Block Controls transmission/reception data output/input to/from the DMA buffer. • • • • The DMA buffer the DMA engine controls has a transmission area and a reception area. The DMA Transmission buffer stores the data and status information of multiple packets that are currently being transmitted. The DMA Reception buffer stores the data and status information of multiple packets that were received. Each buffer has a Producer Block that controls the data stored in a buffer and a Consumer Block that controls data removed from a buffer. The PCI Bus/DMA Buffer arbiter determines whether the consumer or producer State Machine has higher priority access permission to the PCI Bus/DMA Buffer. The priority changes dynamically and, if possible during Burst transfer, gives priority to the State Machine that controls the PCI Bus. However, when either the MAC Reception FIFO becomes nearly full or the MAC Transmission FIFO becomes nearly empty during transmission, priority is given to that FIFO. In other situations, the round-robin scheme is used to provide service in a fair manner. The DMA Controller block consists of the circuits required for the Bus Master to perform read/write operations via the PCI Bus. 16-7 Chapter 16 Ethernet Controller • • • • Busrt Size Control Circuit Optimizes PCI and system performance. Transmission Threshold Control Circuit Matches transmission latency to PCI Bus latency. Big Endian Byte Translation Circuit Supports data transfer to Big Endian format processors. Buffer Distribution/Sharing Control Circuit Can distribute then store one frame in multiple buffers. Can also store multiple frames in a single buffer and increase the usage efficiency. Polling Control Circuit Polls transmission packets. Is optional. Transmission Wakeup Control Circuit Performs control required to start transmission when the data is prepared. Early Notification Circuit Circuit that generates signals for starting to handle reception data before the data ends. Interrupt Enable Control Circuit Adjusts controller operation as the protocol requires. • • • • 16-8 Chapter 16 Ethernet Controller 16.3.4.2 MAC overview Figure 16.3.3 is a function block diagram of MAC. MAC consists of a Transmission Block, Reception Block, Control/Status Register group, Flow Control Block, and a Serial Controller. The Serial Controller is an MII station management interface. DII 32 Reception Block CRC/ARC Filter Flow Control 8 Transmission Block Back-off, Intergap Timer MAC Transmission FIFO 8 MAC Control Status Register Group ARC MAC Reception FIFO Parity Generator Parity Generator Preamble, Jam Generator Pad, CRC Generator MII Station Manager Loop Back MDC MDIO RxD[3:0] MII TxD[3:0] Figure 16.3.3 MAC Function Block The media-independent interface (MII) transfers signals between the 100Base-T compatible physical layer and the Transmission/Reception Block. MII is described in the IEEE 802.3 standard. The Transmission Block buffers data transmitted from the MAC Transmission FIFO, assembles packets, and then transfers them to the MII. Included in the Transmission Block are circuits that generate Preamble Bytes, Jam Bytes, Pad Bytes, and CRC values. Also included is a parity check circuit, a timer that creates back-off delay when a collision occurs, and a time that creates a cap between packets that were transmitted. The Reception Block expands packets received from MII, and then stores them in MAC Reception FIFO. Included in the Reception Block are a circuit that checks the CRC value, a circuit that generates parity to protect data in the FIFO, and a circuit that checks the packet length. Also included is an address recognition circuit (ARC) that, based on the receiving address, judges whether to accept or discard a packet. 16-9 Chapter 16 Ethernet Controller You can use a loop back circuit to separate MAC from the MII and physical layer and perform MAC layer testing. The MAC function block performs control to perform network manipulation such as the following: • • • • • • • • Control to include a stop request at the end of a packet currently being transmitted or received, and enable or disable the transmission/reception circuit Interrupt enable/disable control for each condition Address recognition control for up to 21 addresses Counter, status bit for collecting network management data Loop back or other control that aids network failure diagnosis Pause operation enable control for pausing the transmitter when a MAC control frame described by Pause operation is received MAC control frame transmission control for enabling Pause or other MAC control frame generation even when the transmitter has paused MAC control frame pass through control for enabling hardware or software to handle MAC control frames in another format 16.3.5 DMA function block 16.3.5.1 DMA Transmission Controller The DMA Transmission Controller consists of two State Machines: Producer and Consumer. The Producer checks the frame descriptor of the transmission queue, then controls data transfer from the transmission queue to the DMA Transmission buffer. Also, after transmission ends, the Producer controls the writing of transmission status information that expresses the MAC status information for the transmitted data. The Consumer controls transfer of data from the MAC transmission engine or a large-capacity DMA transmission buffer to a small MAC transmission FIFO. 16.3.5.2 DMA Reception Controller The DMA Reception Controller consists of two State Machines: Producer and Consumer. Producer controls data transfer from MAC Reception FIFO to the DMA reception buffer. Consumer allocates buffers from the empty buffer list, writes the frame descriptor and related buffer descriptor of the packet in the free descriptor area, then controls data transfer via the PCI Bus from the DMA Reception buffer to the system memory. 16-10 Chapter 16 Ethernet Controller 16.3.6 MAC function blocks 16.3.6.1 MAC Transmission Block The Transmission Block takes charge of data transmission. The Transmission Block is compliant with the IEEE 802.3 carrier sense multiple access with collision detection method (CSMA/CD) protocol. This block also supports full duplex modes that can simultaneously perform transmission and reception. The Transmission Block consists of the following parts. • • • • • Transmission FIFO, FIFO Control Counter Preamble, Jam Oscillator Pad Byte, CRC Generator Parity Checker Back Off, Intergap Timer For details of the Transmission Block, see 16.3.8 MAC operation. 16.3.6.2 MAC Reception Block The Reception Block takes charge of data reception. The Reception Block is compliant with the IEEE 802.3 carrier sense multiple access with collision detection method (CSMA/CD) protocol. This block also supports full duplex modes that can simultaneously perform transmission and reception. The Reception Block consists of the following parts. • • • • Reception FIFO, FIFO Control Counter Address Recognition ARC Block CRC Generator, Tester Parity Generator For details on the Reception block, see 16.3.8 MAC operation. 16.3.6.3 Flow Control Block The Flow Control Block has the following functions: • • • • • Recognize MAC control frames the Reception Block received Transmit MAC control frames (even when the transmitter is paused) Pause operation timer and counter Command/Status Register Interface Options for handing off MAC control frames to the software driver The reception circuit in the Flow Control Block recognizes the MAC control frame, and then performs the following Pause operation. First, the Data Length/Data Type field must have a specific value for a MAC control frame. Second, the ARC must recognize the destination address. Third, the frame length must by 64 Bytes including CRC. Fourth, the CRC test result must confirm the correctness of the frame. Finally, the frame must include a valid Pause operation code and operand. 16-11 Chapter 16 Ethernet Controller If the Data Length/Data Type field does not contain a specific value that expresses a MAC control frame, MAC performs no operation and the packet is treated as a typical packet. If the ARC cannot recognize the destination address, MAC ignores the packet. If the packet length including CRC is not 64 Bytes, MAC does not perform Pause operation. In this case, if Pass Through is in the Enabled state, the driver is handed off. If the Control bit of the Transmission Status Register is set, you can detect full duplex mode Pause operation or other MAC control function frames even if the transmitter itself is in the Pause state. The Flow Control Block has two timers for Pause operation and a Control/Status Register for each timer. One timer, register pair is used when the received packet pauses the transmitter. The other timer, register pair is used to estimate the pause status of the transmission destination after the transmitter transmits a Pause command. The Command/Status Register Interface is used to access the Transmission Control Register, the Transmission Status Register, the Reception Control Register, and the Reception Status Register. You can use these registers to start transmission of a MAC Control frame, enable or disable the MAC control function, or access the Flow Control counter. You can use the Control bit to select whether to completely handle MAC Control frames inside the Ethernet Controller or hand them off to the software driver. Therefore, default flow control is possible even if the software driver itself does not support flow control. 16.3.6.4 MAC Control Register, Status Registers MAC has a group of Control Registers and Status Registers. These registers are used to control the Transmission Block or Reception Block, display MAC status, are used in the communication interface with CAM, and are used in the interface with the MII Station Manager. These registers can also access from PCI using the memory map or I/O map. For details on the MAC Control Register or Status Register, see 16.4.5 MAC Control, Status Register group. 16.3.6.5 MII Station manager MAC in the Ethernet Controller handles station management data signals (MDIO and MDC) from the MII Controller, but it does not interpret them. Using a serial interface defined by MII, the MII Station Manager reads and writes to/from the Control Registers and Status Registers in a PHY device whose configuration is set up. When it is necessary to access these registers to negotiate configuration using an application specialized for a bridge, router, switching hub, etc., you can use the MAC Control Registers and Status Registers to trigger reads and writes through the Station Management Data Interface. For details, see 16.4.5.5 Station Management Registers. 16.3.6.6 Reception packet alignment When storing Reception packets in the buffer, the Ethernet Controller can skip by the set byte count. By default, the Ethernet Controller does not skip Reception packets and these packets are on double-word boundaries. You can set the DMA Control Register to have the first buffer skip 13 Bytes. This function is convenient when aligning packets when internally necessary by handling IPs and decoding. 16-12 Chapter 16 Ethernet Controller 16.3.7 Memory configuration This subsection describes the data structure the PCI-mounted Ethernet Controller uses when exchanging data with the Host system. The data structures are stored in system memory. There are three basic data structures: • • • Frame descriptor Buffer descriptor Data buffer These data structures are used in the following manners: • • • Transmission queue: Reception queue: Buffer list: Listing the frame descriptors of packets ready for transmission Listing the frame descriptors of received packets Listing the frame descriptors that have unused buffers for receiving data Figure 16.3.1 shows an outline of each data structure. This subsection describes each data structure in detail. Depending on the type of data structure, some queues in use may include different information. Each following item will describes this in detail. During continuous polling operation, a queue never becomes empty once it is created. One frame descriptor is always appended to the end of a queue. This dummy frame descriptor is used in processes that generate a descriptor to be transmitted. For details, see 16.3.9 DMA Operation. To start transmission, the system sets the address of the first frame descriptor in the Transmission queue in the Transmission Frame Pointer Register. The Ethernet Controller transmits while tracing the Transmission queue, then updates the status of the transmitted packet. The owner bit of the Frame Descriptor Status Field and Frame Descriptor Control field indicates “Transmission complete”. This enables the system software to handle the queue in situations such as when releasing the buffer. The Ethernet Controller fetches the buffer from the buffer list, and then writes the new frame descriptor or new buffer descriptor in a free descriptor area. Subsection 16.3.9 DMA Operation. describes this. 16.3.7.1 Frame descriptor A frame descriptor consists of a pointer to the next frame descriptor in the queue, a System Data field, a Frame Length field, a Control field, and a Status field. Table 16.3.2 shows the frame descriptor format. Table 16.3.2 Frame Descriptor Format Byte 3 Byte 2 FDNext FDSystem FDStat FDCtl FDNext FDSystem FDStat FDCtl FDLength Next frame descriptor Frame system data Frame descriptor status Frame descriptor control Frame descriptor length FDLength Byte 1 Byte 0 Offset 00 h 04 h 08 h 0C h Address of the next frame descriptor in the queue Is used by the system or application software Status field of this frame descriptor Control field of this frame descriptor Field that expresses the length of this field 16-13 Chapter 16 Ethernet Controller The Ethernet Controller retains the Frame System Data field (FDSystem). The FDSystem field can be used by system or application programs. The initial value of the frame descriptor written to the Reception queue is fetched from the frame descriptor of the current buffer list. Depending on the queue type, the usage of the FDNext, FDCtl, FDStat, or FDLength fields varies. See the following items for an explanation. 16.3.7.1.1 FDNext field (next frame descriptor) The FDNext field stores a flag that indicates the end of list (EOL) or a pointer to the next frame descriptor in the same queue. The frame descriptor must be aligned to a 16-byte boundary. In other words, bits 0-3 of the valid pointer must be "0". 31 Pointer 16 15 Pointer 4 3 0 0 1 0 0 EOL Bit(s) 31:4 Mnemonic Pointer Field Name 28-bit Pointer Description 28 bit Pointer When EOL=0, the upper 28 bits of the address of the next frame descriptor in this queue is stored. Is fixed to 000 EOL 0: Pointer is valid. 1: End of list. You have to wait until this flag is cleared. 3:1 0 EOL End Of List flag Figure 16.3.4 FDNext Field Regardless of the queue type, by setting the EOL bit, you can use the FDNext field stop the list consumer (consumption side processing mechanism). The consumer must wait for the list producer (generation side processing mechanism) to clear the EOL bit and store a valid pointer. In the case of a buffer list queue, you can use the FDNext field to create a chain to the next buffer pool from any buffer pool. When not creating a buffer list chain, the software driver has to set its own address in the FDNext field. Doing so makes it possible for the Ethernet Controller to recheck so it can reuse the same buffer area. You can also set the EOL bit and stop the Ethernet Controller. 16.3.7.1.2 FDSystem field (frame descriptor system data) The FDSystem field is a 32-bit field that is reserved for use by the system software. You can use this field to store pointers to the information table, pointers to C++ virtual functions, etc. The Transmission queue does not use the FDSystem field. In the case of a Reception queue, the Ethernet Controller copies the content of the FDSystem field of a frame descriptor that retains a buffer list to which is allocated the first buffer descriptor that stores the frame. 16-14 Chapter 16 Ethernet Controller 16.3.7.1.3 FDStat field (frame descriptor status) The Transmission queue or Reception queue uses the FDStat field to display the transmission/reception complete status. For the meaning of each Status bit, see the descriptions of the TX_Stat Register and Rx_Stat Register in subsection 16.4.5 MAC Control, Status Register group. The reception empty buffer list does not use the FDStat field. 16.3.7.1.4 FDLength field (frame descriptor length) The Transmission queue does not use the FDLength field. In the case of the Reception queue, the Ethernet Controller sets the FDLength field to the total packet length. In the case of a buffer list, the FDLength field is used to count the number of empty buffer descriptors allocated to the queue. The Ethernet Controller accesses the buffer list frame descriptor through the Buffer List Frame Pointer Register. When the Ethernet Controller encounters a buffer that it does not own, it sets the BL_Ex bit of the Interrupt Source Register and then waits for the system to clear it. The Ethernet Controller treats the FDLength field value as the upper limit, then reads the buffer descriptor. As the Ethernet Controller nears the end of the list, it reads out the next frame descriptor that the FDNext field indicates, as described in 16.4.3.8 Free Descriptor Area (FDA) Register. 16-15 Chapter 16 Ethernet Controller 16.3.7.1.5 FDCtl field (frame descriptor control) This item shows the FDCtl field configuration and application. The Transmission queue or Reception queue uses the COwnsFD bit to synchronize the Ethernet Controller and System process. The Transmission queue or buffer list uses the FrmOpt field. The Transmission queue or Reception queue uses the BDCount field (the buffer list uses the Frame Descriptor Length field (FDLength) to enable the use of buffer pools larger than the BDCount field permits). For each reception packet, an excessive buffer descriptor error is issued when more than 28 buffer descriptors are used. 15 COwnsFD 14 FrmOpt 10 9 Reserved 5 4 BD Count 0 Bit(s) 15 Mnemonic COwnsFD Field Name Frame Descriptor Owner Description COwnsFD 1: The Ethernet Controller owns the frame descriptor after the system sets the COwnsFD bit. 0: The system owns the frame descriptor after the Ethernet Controller clears the COwnsFD bit. Frame Option Control option for each frame (see the following description) BDCount This is the number of allocated buffer descriptors (1-28). 14:10 4:0 FrmOpt BDCount Frame Option Buffer Descriptor Count Figure 16.3.5 FDCtl Field The Transmission queue uses the FrmOpt field and sets the transmission characteristics of each packet. • • • • 10000 01000 00100 00010 Big Endian order Issue interrupt after transmission Do not add CRC For short frames, do not add PAD You can use combinations of the above bits to set various transmission characteristics. For example, "01110" means "Little Endian, issue interrupt after transmission, no CRC, no padding for short packets". In applications such as hubs where transmission packets are being received from both Big Endian and Little Endian transmission sources, controlling Big Endian for each packet is useful. In computer applications, it is easier to use the global Big Endian control bit described in 16.4.3.1 DMA Control Register. Unless you set a global enable bit like that described in 16.4.3.6 Reception Fragment Size Register, the Reception buffer list uses the option set in the FrmOpt field to control packing and the endian. 16-16 Chapter 16 Ethernet Controller • • 10000 00001 Big Endian order Enables packing for this frame's buffer, ignores any global enable bit When packing is enabled, the RxFragSize Register controls the packing algorithm. 16.3.7.2 Buffer descriptor Each buffer descriptor consists of a pointer to the data buffer, a control byte, a status byte, and a 2-byte Buffer Length field. Table 16.3.3 indicates the buffer descriptor format. Table 16.3.3 Buffer Descriptor Format Byte 3 BDCtl BuffData BDCtl BDStat Buff Length Byte 2 BuffData BDStat Buffer Data Pointer Buffer Descriptor Control Buffer Descriptor Status Buffer Length Byte 1 BuffLength Byte 0 Offset 00h 04h Address of the buffer that stores data (32 bits) Control of this buffer descriptor Status of this buffer descriptor Field that expresses the length of this buffer When a buffer is listed in the buffer list, the BuffData field indicates the buffer head and the BuffLength field indicates the size of buffers allocated as unused buffers. When the buffer is used in the Transmission queue or Reception queue, the BuffData field indicates the descriptor head and the BuffLength field indicates the data length. When a buffer is placed in the buffer list, the system software is responsible for allocating the Buffer Length field and setting the size. Similar to the frame descriptor, usage of the BDCtl field or BDStat field varies depending on the queue type. Note: As shown in step 4 of 16.3.8.4 Frame transmission procedure, more than 8 bytes of data is required as a Transmission packet data. One Transmission packet cannot consist of multiple data buffers, so you have to implement your design so the BuffLength (buffer length) total is 8 bytes or more. 16-17 Chapter 16 Ethernet Controller 16.3.7.2.1 BDCtl field (buffer descriptor control) The transmission queue does not use the BDCtl field. In the case of the reception queue, the number of buffer descriptors per buffer area is set in the BDCtl field. The first buffer descriptor in a frame is number 0, and the subsequent buffer descriptors are number 1 and number 2. 7 COwnsBD 6 RxBDSeqN 0 Bit(s) 7 Mnemonic COwnsBD Field Name Buffer Descriptor Owner Description COwnsBD 1: The Ethernet Controller owns the buffer descriptor. When the system sets the COwnsBD bit, the buffer can freely receive data. 0: The system owns the buffer descriptor. When the Ethernet Controller clears the COwnsBD bit, it indicates that the buffer is full. RxBDSeqN After receiving data, this field indicates the running number of this buffer in the current buffer area. 6:0 RxBDSeqN Reception Buffer Descriptor Number Figure 16.3.6 BDCtl Field In an empty buffer list, the BDCtl field is used to record buffer ownership. This makes it possible to allocate the buffer descriptor and synchronize release of the buffer. This also prevents the Ethernet Controller from using the buffer in a loop before the system empties the buffer. 16-18 Chapter 16 Ethernet Controller 16.3.7.2.2 BDStat field (buffer descriptor status) In the case of a transmission queue, the Ethernet Controller does not use the BDStat field. In the case of a reception queue, the BDStat field is used as the buffer ID. This value is copied from an empty buffer queue. 7 RxBDID 0 Bits 7:0 Mnemonic RXBDID Field Name Reception Buffer Descriptor ID Description RXBDID Value of the buffer descriptor identification number Figure 16.3.7 BDStat Field In the case of an empty buffer queue, the BDStat field is used to hand the buffer descriptor identification number to the Ethernet Controller. Note: You can only apply buffer descriptor identification numbers freely if there are no more than 256 buffers in a single buffer pool. 16-19 Chapter 16 Ethernet Controller 16.3.8 MAC operation This subsection describes MAC operation in detail with respect to the following content: • • • • • • • • • Format of MAC frames and packets Initializing MAC Access MAC Registers Frame transmission procedure Frame reception procedure Operation of the address recognition circuit (ARC) Pause operation in full duplex transfers Signaling transmission/reception errors Accessing station management data 16.3.8.1 Format of MAC frames and packets Figure 16.3.8 shows the format of IEEE 802.3 Ethernet packets. Standard packets have the following fields. Transmission Packet (Encoded in media by MAC transmission part_ Added by MAC Tx Part Deleted by MAC Rx Part Preamble 7 Bytes 1 Byte ... 1 Byte 1 Byte 6 Bytes 6 Bytes SFD Recipient Address Tx Data Frame (Transmitted by MAC Client) Rx Data Frame (Transmit to MAC Client) Sender Address Frame Length, Frame Type Upper 1 Byte Lower LLC Data User Pad MSB 4 Bytes Added by MAC Tx Part Deleted by Rx Part CRC (FCS) LSB Rx Packet (Received from media by MAC Rx Part) 1 Byte 0-1500 Bytes 0-46 Bytes Figure 16.3.8 Ethernet Packet Frame Fields • Preamble— repeat the same byte 7 times Each byte is fixed to 10101010 and is transmitted from left to right. The preamble is sometimes shortened during transmission and is not necessary when receiving data. Start Frame Delimiter (SFD)— 1 Byte The SFD is fixed to 10101011 and is transmitted from left to right. It is necessary when receiving data. Recipient address— 6 Bytes This is a unicast or multicast address. ARC can use the recipient address and can freely perform address filtering. Sender address— 6 Bytes MAC does not check the sender address. However, to make the sender address a valid station address, the first bit (LSB) of the first Byte transmitted must be “0”. Frame length or frame type— 2 Bytes Is transmitted upper byte first. In the IEEE802.3 standard, a value of 1500 or less is defined as the frame length, and any value greater than 1535 is defined as the frame type. If the value is 1500 or less, it indicates the byte count of the logic link control (LLC) data in the Data field. MAC recognizes 8808h as the MAC control frame and specially recognizes 8100h as a tagged VLAN frame. • • • • 16-20 Chapter 16 Ethernet Controller • • • Logic link control (LLC) data— 0-1500 Bytes LLC data consists of two fields: User Data and Pad Data. User Data— 0-1500 Bytes Pad Data— 0-46 Bytes When the user data is less than 46 Bytes long, MAC can add padding bytes and make the LLC data 46 Bytes long. Cyclic redundancy check (CRC)— 4 Bytes Also referred to as the frame check sequence (FCS), this value is calculated from all other fields except the preamble, SFD, and CRC itself. The preamble, SFD, pad data, and CRC are added on by the transmission side. You can also pad data using the software. CRC can use the Transmission Control Register to suppress padding. You can use the Reception Control Register to control deletion of CRC. You can delete pad data using either the DMA engine or the software driver. Except for CRC, the MAC transmits each byte starting from the least significant byte. In this document, all bytes transmitted or received are collectively referred to as “packets”. The term “frame” refers to a part that you provide during transmission or a part that is provided to you during reception. Standard IEEE802.3 frames are transformed by various factors and options. • Depending on the PHY, there are cases where the preamble length is not 7 Bytes. Sometimes a repeater shortens the preamble. The transmission part sends the preamble in a standard format, but the reception part does not care even if there is no preamble or the preamble is more than 7 Bytes long. SFD follows the preamble. When in the Short Packet mode, LLC data less than 46 Bytes long is allowed. In this case, there are options for suppressing padding when transmitting data or for allowing the reception of short packets. When in the Long Packet mode, LLC data larger than 1500 Bytes is allowed. There is an option for allowing the reception of long packets. There is an option for suppressing the addition of CRC fields. There is also an option for allowing the reception of packets that do not have a valid CRC field. • • • • • 16-21 Chapter 16 Ethernet Controller 16.3.8.1.1 Format of recipient addresses Bit 0 of a recipient address specifies the address type. This bit indicates whether the address is an individual address or a group address. Group addresses are also referred to as multicast addresses. Individual addresses are also referred to as unicast addresses. Broadcast addresses are special group addresses that are FF-FF-FF-FF-FF-FF hexadecimal addresses. Bit 1 distinguishes locally managed addresses from globally managed addresses. If an address is managed globally (universal), bit 1 is set to "0". If an address is allocated locally, bit 1 is set to "1". Bit 1 is set to "1" for broadcast addresses. Recipient address (first Byte) 7 Rest 2 1 U/L 0 I/G : Type : Default Bit(s) 7:2 1 Mnemonic Rest U/L Field Name Remaining Bit Universal/Local Description Rest Remaining bits of the first Byte are the recipient bits. U/L 0: Universal address 1: Local address I/G 0: Individual address 1: Group address 0 I/G Individual/Group Figure 16.3.9 Format of Recipient Addresses 16.3.8.1.2 Special flow control recipient address The IEEE802.3 standard specially prescribes a recipient address of 01-80-C2-01-00-01 for PAUSE manipulation packets to realize full duplex flow control. In order for the MAC to receive packets including the special recipient address for PAUSE manipulation, you have to set the address in one entry in ARC memory, enable that entry, and then activate ARC itself. The details are described in the following paragraphs. However, part of the ARC entry uses the SdPause bit of the Transmission Control Register and is also used when generating flow control frames. 16-22 Chapter 16 Ethernet Controller 16.3.8.2 Initializing MAC After powering up or after performing reset, the MAC Control Status Register is initialized as described in section 16.4 Registers. The transmission collision count and ARC data is not initialized when you power up or reset the Ethernet Controller. The transmission collision count is reset when a new packet is transmitted. Initialize ARC memory before enable ARC. 16.3.8.3 MAC Register access Access to the MAC Register is controlled through the PCI Bus Interface. For details on read access and write access of the register, including the MAC Control Register, see 16.3.9 DMA operation. 16.3.8.3.1 Clearing special registers The Lost Packet Error Count Register is cleared when it is read. This makes it possible to synchronize it to software drivers that tabulate the total error count. The Transmission Status Register and Reception Status Register are cleared at the beginning of the next packet. Therefore, values read from the Register Interface may not be stable. These register values are stored in the FDStatus field of the frame descriptor in memory for each transmission or reception packet. You have to use the software to check the status value retained in the system data structure. 16.3.8.4 Frame transmission procedure (1) To transmit a frame, the Transmission Enable bit (TxEn) of the Transmission Control Register must be set, and the Transmission Halt Request bit (TxHalt) must be cleared. Furthermore, the Halt Transmission Immediately bit (TxHalt) and the Halt Request bit (HaltReq) of the MAC Control Register must be cleared. Usually, the above conditions (such as storing a valid frame descriptor address in the Transmission Frame Descriptor address) are set after initializing the DMA Controller. In this way, MAC instructs the DMA engine to transmit a frame to MAC Transmission FIFO. At this time, the DMA Transmission Controller controls transfers to the MAC Transmission FIFO. (2) The MAC Transmission Block starts transmitting data in the FIFO. However, the first 64 Bytes are held in the FIFO until the net is fetched. Then, the MAC Transmission Block requests the next data and continues to transmit until the DMA Transmission Controller indicates the end of transmission data. The MAC Transmission Block generates pad bytes when necessary, adds CRC to the end of a packet, then ends transmission. The MAC Transmission Block will then set the Transmission Complete bit (Comp) of the Transmission Status Register to signal that transmission has ended. Finally, depending on the Interrupt Enable Register settings, an interrupt may occur. (3) Data transfer via the MII Interface is driven by a 25 MHz or 2.5 MHz MII Transmission Clock (Tx_clk). 16-23 Chapter 16 Ethernet Controller (4) The MAC Transmission Block must not start transmitting to the net until 8-byte data is stored in the MAC Transmission FIFO. The first 8 bytes transmitted are the preamble and Start Frame Delimiter (SFD), so the allowable DMA latency when starting transmission is 16-byte time. The DMA Transmission Block does not transmit data to the MAC Transmission FIFO until either the entire packet is stored in the DMA Transmission buffer or the byte count set in the Transmission Threshold Register is stored in the DMA Transmission buffer. If a Transmission Underrun error is generated, you can avoid an underrun by increasing the setting of the Transmission Threshold Register. (5) The MAC Transmission Block performs a parity check. If a Parity error is generated, the MAC Transmission Block aborts transmission, then resets the FIFO and sets the Transmission Parity Error bit (TxPar) of the Transmission Status Register. 16.3.8.4.1 IEEE 802.3 transmission protocol The MAC Transmission Block consists of three State Machines. The Main State Machine executes MAC layer protocol and controls the other two State Machines (Gap State Machine and Back Off State Machine). The Gap State Machine fetches the timing gap between packets, then counts them. The Back Off State Machine executes the Back Off or Resend algorithms of the 802.3 CSMA/CD protocol. 16.3.8.4.2 Interpacket gap (IPG) timing When in the half duplex mode, the Gap State Machine measures 96-bit time from the point when the Carrier Sense signal is deasserted. This time becomes the interpacket gap. Gap State Machine splits the 96-bit time into 64-bit and 32-bit time, then precisely controls the timing at which transmission starts. If there is traffic with the first 64-bit time, the Gap State Machine resets the counter to 0, then starts counting from the beginning. If there is traffic during the remaining 32-bit time, the count continues as is and signals that 96-bit time has elapsed. When in the full duplex mode, Gap State Machine starts counting along with transmission completion, then signals transmission completion after 96-bit time passes. 16.3.8.4.3 Collision process and back off When the Main State Machine detects a collision, it starts up the counter of the Back Off State Machine, waits for the Back Off time to elapse, then attempts to resend the packet that caused the collision. The Back Off time is a multiple of 512-bit time (including × 0). When a collision happens in the same packet, the Main State Machine advances the internal Trial Count counter by 1 each time this happens. Then, it causes an 11-bit pseudorandom number generator to generate random numbers and output a subset of it. Each time this is retried, the subset increases in size by 1 bit. In this way, the following formula is invoked by the hardware. 0 ≤ r < 2k k = min(n, 10) 16-24 Chapter 16 Ethernet Controller r is the slot time count that the MAC must wait when a collision occurs. n is the number of retransmission attempts. For example, after the first collision, n=1 and r is a random number between 0 and 1. In this case, the pseudorandom number generator is 1-bit wide and generates either 0 or 1 as a random number. For the second and subsequent attempts, r is a random number between 0 and 3. In other words, State Machine is n=2, so the pseudorandom number generator looks at the lower 2 bits and generates random numbers between 0 and 3. To reduce the statistical probability of similar random number sequences being generated between multiple MACs using the same random number generator, MAC uses the CRC value of the packet that was previously transmitted successfully to recalculate a basic random number sequence. 16.3.8.4.4 MII transmission operation If there is data to be transmitted, there is no problem with the interpacket gap, and MII preparations are complete (in other words, there are no collisions for full duplex or for half duplex there are no collisions and there is no CrS),MAC transmits the preamble and SFD. After that, unless Short Packet transmission is enabled, MAC transmits 64 Bytes of data regardless of the packet length. If the packet length is less than 64 Bytes, the MAC Transmission Block pads the LLC Data field with zeroes. If CRC generation is enabled, the MAC Transmission Block appends CRC to the end of the packet. If a collision occurs during the first 64 Bytes (7-Byte preamble + SFD + 56-Byte frame), the MAC Transmission Block aborts transmission and transmits a jam pattern (a 32-bit sequence of ones). In this case, it advances the transmission retry counter by 1, then transfers control to the Back Off State Machine. After the Back Off time elapses, the MAC Transmission Block tries to resend the packet if there is no problem with the interpacket gap. If no collisions occur, the MAC Transmission Block transmits the rest of the packet. If the first 64 Bytes are transmitted without any collision, the MAC Transmission Block provides the DMA engine with permission to overwrite these 64 Bytes. After transmitting the 64 Bytes, the MAC Transmission Block transmits the reset of the packet and appends CRC to the end of it. If an underrun occurs in the FIFO or there is a collision that occurs more than 16 times, the MAC Transmission Block makes no attempt to resend the packet and makes preparations to transmit the next packet registered in the queue. If a transmission error occurs, the MAC Transmission Block sets the appropriate bit of the Transmission Status Register. Also, depending on the Transmission Control Register settings, an interrupt may occur. Tx_clk Tx_en TxD[3:0] CrS Col Figure 16.3.10 Transmission with no Collisions 16-25 Chapter 16 Ethernet Controller Figure 16.3.10 shows the transmission timing of packets with MII. Tx_end and TxD[3:0] change after the rising edge of Tx_clk, then are stable until sampled at the next rising edge. When in the full duplex transfer mode, CrS and Col become undefined. When in the half duplex transfer mode, CrS must be asserted after Tx_en and must be asserted during packet transmission. If CrS is deasserted during packet transmission, a Carrier Lost error will occur. Col retaining the “L” setting indicates that no collisions have occurred. Tx_clk Tx_en TxD[3:0] CrS Col Figure 16.3.11 Transmission when Collision Occurred in the Preamble Figure 16.3.11 shows the method the Transmission Block uses to handle collisions. It adds 4-Byte jam data before deasserting Tx_en. If a collision occurs in the preamble, the jam data is added on after SFD ends. P1 P2 P3 P4 P5 P6 P7 SFD J1 J3 J4 16.3.8.5 Frame reception procedure To receive a frame, the Reception Enable bit (RxEn) of the Reception Control Register must be set, and the Reception Halt Request bit (RxHalt) must be cleared. Furthermore, the Halt Transmission Immediately bit (TxHalt) and the Halt Request bit (HaltReq) of the MAC Control Register must be cleared. Usually, before programming the above registers, the DMA Controller is initialized. This allows the DMA Reception Controller to control transfers from the MAC Reception FIFO. For the method of initializing data structures to enable reception, see the descriptions in subsections 16.3.9 DMA Operation and 16.3.9.5 Receiving frames. When enabled, the MAC Reception Block always monitors the data stream coming in from MII. When in the Loop-back mode, the data stream is inputted from the MAC Transmission Block via MII. The MAC Reception Block receives a 0- to 7-Byte preamble and the Start Frame Delimiter (SFD). The MAC Reception Block checks whether the first nibble received is a preamble, then checks whether there is an SFD in the first 8 Bytes of the packet. Except for the preamble, the MAC Reception Block treats a packet that does not have the SFD as its first Byte as a packet fragment and deletes it. 16-26 Chapter 16 Ethernet Controller Following after the SFD is the first nibble of the recipient address. The MAC Reception Block generates parity when it receives 1 Byte of data, then stores it with the data in the MAC Reception FIFO. After that, it signals the existence of reception data. The MAC Reception Block collects subsequent nibbles into Byte units and stores them in the appropriate FIFO. The DMA Reception Controller reads them from the MAC Reception FIFO in Byte units, performs a parity check, and then transfers the data to the DMA Reception buffer. When either the MAC Reception FIFO becomes empty or it transmits the last Byte of a packet and ends transmission, the MAC Reception Block signals this fact. If PHY asserts both the Rx_DV and Rx_er signals while receiving a frame, the MAC Reception Block reports that a CRC error occurred in the current packet. When the MAC Reception Block receives the recipient address, the ARC tries to recognize the received address. If the ARC refuses a packet, the MAC Reception Block signals this fact and the DMA Reception Block destroys the data packet. 16.3.8.6 Address Recognition Circuit (ARC) operation To read from or write to ARC memory, first the system software sets the ARC Address Register, and then it reads and writes the ARC Data Register. All Bytes are written to regardless of the Byte Enable status. To write either the upper 2 Bytes or lower 2 Bytes of a double word, the driver software has to handle the data to correctly and simultaneously write 2 adjoining Bytes. The Ethernet Controller does not support Read, Modify, or Write cycles to internal DMA RAM. Figure 16.3.12 shows how the MAC reads entries from the ARC. ARC entries are in the Big Endian Byte order. In other words, if #0-0 is the first Byte of the first entry, then #0-5 is the sixth and therefore last Byte of the first entry. After entry #20 are the 2 Bytes Rsv-2 and Rsv-3, then the 2 double words MC#1 and MC#2. MC#1 and MC#2 cannot be used by ARC operation, but they are used when generating the MAC control frame. Item 16.3.8.7 Pause operation during full duplex transfer describes this. Byte 3 #0-0 #0-4 #1-2 #2-0 #2-4 #3-2 #4-0 #4-4 #5-2 #18-0 #18-4 #19-2 #20-0 #20-4 MC#1-0 MC#2-0 Byte 2 #0-1 #0-5 #1-3 #2-1 #2-5 #3-3 #4-1 #4-5 #5-3 #18-1 #18-5 #19-3 #20-1 #20-5 MC#1-1 MC#2-1 Byte 1 #0-2 #1-0 #1-4 #2-2 #3-0 #3-4 #4-2 #5-0 #5-4 #18-2 #19-0 #19-4 #20-2 Rsv-2 MC#1-2 MC#2-2 Byte 0 #0-3 #1-1 #1-5 #2-3 #3-1 #3-5 #4-3 #5-1 #5-5 #18-3 #19-1 #19-5 #20-3 Rsv-3 MC#1-3 MC#2-3 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h ... 6Ch 70h 74h 78h 7Ch 80h 84h Figure 16.3.12 ARM Memory Map 16-27 Chapter 16 Ethernet Controller 16.3.8.7 Pause operation during full duplex transfer 16.3.8.7.1 Local Pause operation To enable Pause operation during full duplex transfer, you have to set a special multicast address for the MAC control frame in ARC memory and set the corresponding bit in the ARC Enable Register. You can store the special multicast address for the MAC control frame anywhere in ARC memory, but there are cases where you will have to be careful of the storage location to optimize the usage efficiency of ARC memory (see 16.3.8.7.2 Remote Pause operation). The MAC reception circuit recognizes full duplex Pause operation when the following conditions are met. • • • • A particular value (0x8808) is set in the Frame Length/Frame Type field of the MAC control frame. The ARC recognizes a packet. The packet is 64 Bytes long. The Operation field specifies Pause operation (0x0001). After recognizing full duplex transfer Pause operation, the MAC reception circuit loads the operand values into the Pause Count Register then instructs both the MAC and DMA engines to pause when processing of the current packet ends. If no packet is currently being processed, then both engines immediately pause. The pause circuit manages the Pause Count Register and counts down the pause time. When the pause time count becomes 0, the pause circuit issues an instruction to end pausing and operation of the transmission circuit resumes. If another Pause operation is recognized during Pause operation, the Pause Count Register is reset by a new operand value. An operand value of 0 will abort the Pause operation currently in progress. 16.3.8.7.2 Remote Pause operation The program can freely set the MAC control frame of the Ethernet Controller, so even when performing Pause operation or using MAC control in the future, it will still support this function. For remote Pause operation or transmission of other MAC control frames, follow the procedure below. • • • Set the recipient address to #0 of the ARC memory. Set the sender address to #1 of the ARC memory. To #20 of the ARC memory set the special MAC control type value (0x0808), the Pause operation opcode (0x0001), and the operand value (pause time: 0x0000 to 0xFFFF). Write 0x0000 to the 2 Bytes after ARC #20. Write 0x0000_0000 to MC#1 and MC#2. Then, remote Pause transmission is complete at one bus operation. Write to the Transmission Control Register and set the SdPause bit. • • 16-28 Chapter 16 Ethernet Controller Usually, the recipient address is the special multicast address of the MAC control frame and the sender address is the local station address. You can enable these ARC entries to be used for address filtering. Since ARC entry #20 does not include a valid network address, you must not enable it when using it as part of a flow control transmission. When transmission ends, the transmission status is written in the Transmission Control Frame Status Register. If the End of Transmission Control bit (bit 10) of the Interrupt Enable Control Register is set, the DMA engine will issue interrupts. 16.3.8.8 Error display The Error flags and Abnormal Operation flags are divided into those that are set during transmission and those that are set during reception. These flags are each set in the Transmission Status Register (Tx_Stat) and the Reception Status Register (Rx_Stat), respectively. Also, the Missing Packet Count Register (Miss_Cnt) contains the number of deleted packets and is used to manage the system network. See 16.4 Registers for the format of these flags and the counter. 16.3.8.8.1 Transmission error display Transmission operation ends when an entire packet (preamble, SFD, data, CRC) is transferred to a physical medium without any collisions occurring. If an internal error or network error occurs, the MAC Transmission Block reports the content of that error. If one of the states described below occurs, transmission is aborted and the Status bit is set. After the Status bit is set, an interrupt occurs if the corresponding Interrupt Enable bit in the Transmission Control Register is set. Table 16.3.4 Transmission Error Display (1/2) Error Display MAC Transmission Parity Error Description The data that the DMA Transmission Controller transmits to the MAC Transmission FIFO via DII is protected by the Parity bit. If a Parity error occurs, the DMA Transmission Controller halts transmission if the TxParErr bit of the Transmission Status Register is set and interrupts are enabled. The MAC Transmission FIFO has a capacity of 80 Bytes so even if a collision occurs, it holds 64 Bytes for retransmission and can support DMA latency up to 1.28 µs (128-bit late time=16-Byte time). The DMA Transmission Controller has sufficient bandwidth, so if an underrun occurs in the MAC Transmission FIFO, this usually indicates that there is a problem with the latency of the PCI Bus. When such an underrun occurs, the Underrun bit of the Transmission Status Register is set. Carrier Sense (CrS) is monitored from the beginning of the Start Frame Delimiter to the last transmission Byte. This error indicates that transmission was not aborted even though CrS either does not exist or was lost due to a network fault or other cause. When in the Loop-back mode, Tx_en drives CrS. With full duplex transfers, Carrier Sense Lost is not asserted since CrS is not handed off to the Transmission Block. When Carrier Sense is lost, the LostCrS bit of the Transmission Status Register is set. If the MAC encounters a collision during transmission, it backs off, updates the collision counter, and then tries to retransmit the data after a specific time interval elapses. When the counter becomes “16”, transmission is aborted if transmission is attempted 16 times and a collision occurred every time. A network fault could cause excessive collisions. When excessive collisions occur, the ExColl bit of the Transmission Status Register is set. MAC Transmission FIFO Underrun Carrier Sense Lost Excessive Collision 16-29 Chapter 16 Ethernet Controller Table 16.3.4 Transmission Error Display (2/2) Error Display Late Collision (Collision Outside Window) Description When the network is operating properly, the MAC detects a collision in the first 64 Bytes of the transmitted data. When a collision occurs after this time elapses (when one occurs outside the window), this means that there is a network fault. In this case, the LateColl bit of the Transmission Status Register is set and packet transmission is aborted. In other words, transmission is not retried after a late collision occurs. When in the 10 Mbps mode, “heartbeat” is checked at the end of the transmitted packet. A heartbeat is a short collision signal that occurs within the first 40-bit late time period after the transmission ends. When a heartbeat is not detected, the SQErr bit of the Transmission Status Register is set. This state indicates that it is necessary to defer transmission since the transmission route was already in use when packet transmission was attempted. This is not an error, but unless an error occurs, this state is used to indicate the state of the transmission route. When the Defer state occurs, the TxDefer bit of the Transmission Status Register is set. There are cases where it is necessary to defer transmission since the transmission route was already in use when the MAC attempted to transmit a packet the first time. If the deferral time is longer than MAX_DEFERRAL (2.4288 ms when in the 10 Mbps mode, 0.24288 ms when in the 100 Mbps mode) and the NoExDef bit of the Transmission Control Register is disabled, then the ExDefer bit of the Transmission Status Register is set. When the Excessive Deferral state occurs, transmission is not aborted, but a network fault may have occurred. It is possible to transmit an Excessive Deferral interrupt before packet transmission is complete and display it in the IntExDefer bit of the Interrupt Factor Register. When attempting to transmit a packet, there are cases where the MAC has to defer transmission since the reception of a MAC control frame including Pause operation caused the Transmission Block to stop transmitting. This is not an error, but this state is reported to indicate the network status. Marking the aborted packet sets the Paused bit of the Transmission Status Register for the final packet before Pause becomes effective to complement the software process. SQE Defer Excessive Deferral Transmission PAUSE 16-30 Chapter 16 Ethernet Controller 16.3.8.8.2 Reception error display After detecting the Start Frame Delimiter (SFD), the MAC writes the data received from the physical medium to the MAC Reception FIFO. The MAC Reception Block checks whether an overflow occurred in the MAC Reception FIFO during reception. Also, when reception ends, it checks for external errors (Alignment, CRC, Maximum Frame Length Exceeded). Table 16.3.5 Reception Error Display Error Display MAC Reception Parity Error Alignment Error Description Once data enters the MAC Reception FIFO, it is protected by the Parity bit. If the RxParErr bit of the Reception Status Register is set and interrupts are enabled when a Parity error occurs, the MAC Reception Block aborts reception. After reception ends, the MAC Reception Block checks whether reception packets are properly framed at the 8-bit boundaries. If they are not properly framed and CRC is invalid, the data is corrupted as it passes along the network and the MAC Reception Block signals an Alignment error. The MAC Reception Block also signals a CRC error at this time. The AlignErr bit and CRCErr bit of the Reception Status Register are set. After reception ends, if the MAC Reception Block checks CRC and there was an error, it signals that error. The CRC error, Frame Alignment error, and the Maximum Frame Length Exceeded error are network errors that the Reception Block detects. These errors could be detected in the following combinations. CRC Error • • • • Overflow Error CRC error only Alignment error and CRC error only Maximum Frame Length Exceeded error and CRC error only Alignment error, Maximum Frame Length Exceeded error, and CRC error During reception, the data is first stored in the MAC Reception FIFO, and then is transferred to the DMA Reception Controller. If the MAC Reception FIFO becomes full due to a cause such as excessive system latency, then the MAC Reception Block sets the Overflow bit of the Reception Status Register. The MAC Reception Block checks the packet length when reception ends. If it receives a frame that is longer than the maximum frame length of 1518 Bytes when the Long Frame mode is not enabled, the MAC Reception Block signals this error. When PHY detects a media error such as a coding violation, it signals MAC by asserting Rx_er. When MAC acknowledges the assertion of Rx_er, it deletes the received packet. A CRC error is forcibly issued and reception of the packet is terminated. There are also cases where an Alignment error or Minimum Frame Length error are detected. Maximum Frame Length Exceeded Error MII Error 16.3.8.9 Accessing station management data Following is the basic sequence of events when accessing station management data. • • • • • The system software checks the Busy bit and confirms that MD is not Busy. For a write operation, you have to write data to the Data Register before setting up the Control Register. The software writes the MDC address, the Read or Write flag, and sets the Busy bit. The Ethernet Controller ends operation then clears the Busy bit. In the case of a read operation, the system software can read the Data Register after it detects that the Busy bit was cleared. 16-31 Chapter 16 Ethernet Controller 16.3.9 DMA operation This subsection describes the programming of the PCI-mounted Ethernet Controller. The programming details differ slightly depending on whether you select batch processing as the control mode or select Continuous Polling. Unless otherwise stated, the descriptions in this subsection assume the use of Continuous Polling. Following is the structure of this subsection. • • • • • • Initial setup of PCI Initial setup of DMA and MAC Initializing the queues Transmitting frames Receiving frames Handling interrupts Note: If you use the SRAM in the DMA Controller without initializing it, Packet errors may be mistakenly detected during packet reception. Implement the following initialization procedure to prevent this phenomenon from occurring. 1) Prepare for initial setup Set (write "1" to) the TestMode bit (bit 13) of the DMA_Ctl (0x00) Register. 2) Initialize on-chip memory Implement the following on all addresses (0x000-0x3FF) of the on-chip SRAM. (i) Set the on-chip SRAM address in ARC_Adr (0x60). (ARC_Loc field: 0x0000x3FF) (ii) Write initialization data 0x0000_0000 to ARC_Data (0x064). (32-bit write) You can implement the following to confirm the written data. Read ARC_Data(0x64). (32-bit read) 3) Cancel the Test mode Reset (write "0" to) 1 in the TestMode bit (bit 13) of the DMA_Ctl (0x00) Register. 16-32 Chapter 16 Ethernet Controller 16.3.9.1 Initial setup of PCI When initially setting up the system, you can use the IDSel signal to write to the PCI Configuration Register. This makes it possible for the system to map the Ethernet Controller to a memory boot address space then transfer data to the boot address space to output the IDSel signal. Registers such as the following require initial setup. • • • • PCI I/O Base Address Register or PCI Memory Base Address Register: To map the register to an I/O address space or memory space PCI Command Register: To customize the PCI function There are also situations where the following register requires initial setup. PCI Interrupt Register: To customize latency or signal interrupt factors to external pins 16.3.9.2 Initial setup of DMA and MAC After initially setting up the PCI, the DMA Control Register and MAC Control Register are usually mapped to an I/O address space or memory address space and are available for reading and writing. Registers such as the following require initial setup. • • • • • • • • • • DMA Transmission Frame Pointer: To start transmission DMA Buffer List Frame Pointer: To provide buffer for receiving data DMA Free Descriptor Area Base Register or DMA Free Descriptor Area Size Register: To initialize the reception signaling area DMA Transmission Polling Control Register: To customize polling of transmission packets DMA Transmission Threshold Register: To customize transmission latency handling MAC Transmission Control Register: To change the default transmission settings MAC Reception Control Register: To change the default reception settings MAC ARC Control Register: To customize the recognition conditions of station addresses and multicast addresses MAC ARC Address Register and MAC ARC Data Register: To set the filtering of station addresses and other addresses MAC ARC Enable Register: To enable each ARC entry after setting up the ARC There are also situations where the following registers require initial setup. • • MAC Control Register: To customize the MAC configuration DMA Control Register: To customize the Burst size 16-33 Chapter 16 Ethernet Controller 16.3.9.3 Initializing the queues The system has to set up the transmission queue, buffer list, and reception descriptor area before starting up the Ethernet Controller. 16.3.9.3.1 Initializing the transmission queue The Transmission Block has two operation modes: Batch Processing and Continuous Polling. When in the Batch Processing mode, the system software prepares a link list of the frame descriptors to be transmitted. The final descriptor must have "1" set in the EOL (end of list) field. When the last frame descriptor is transmitted, the Transmission Frame Pointer Register reads EOL and transmission ends. To resume transmission after this, the system resets the Transmission Frame Pointer Register. When in the Continuous Polling mode, the system software also prepares a link list of the frame descriptors to be transmitted. However, the last frame descriptor is a dummy frame descriptor. The beginning of a link list is only a dummy frame descriptor, so it is okay for it to be empty. The system owns the dummy descriptor to prevent the Ethernet Controller from accessing it. Transmitting a new packet overwrites the dummy frame descriptor. This is explained in 16.4.4 Flow Control Register group. 16.3.9.3.2 Initializing the buffer list The buffer list queue is either a single frame descriptor or multiple frame descriptors combined into a link list containing a list of the empty buffer descriptors that is initialized. It is okay for the buffer list to have one of the following configurations. 1. One frame descriptor containing many free buffer descriptors 2. A link list of frame descriptors 3. Wrap-around queue in which the last frame descriptor points to the first frame descriptor In configurations 1 and 2 above, the EOL bit of the FDNext field is set while in configuration 3, the FDNext field of the last frame descriptor points to the first frame descriptor. You can use the Reception Fragment Size Register to globally pack a buffer. Also, you can use the Control field (FDCtl) of a frame descriptor to select whether to pack in buffer area units. Setting up the Buffer ID field when packing a buffer is useful in managing memory. For details on packing buffers, see 16.4.3.6 Reception Fragment Size Register, 16.4.3.8 Free Descriptor Area (FDA) Registers, and 16.3.7.2.1 BDCtl field (buffer descriptor control). 16.3.9.3.3 Initializing a reception descriptor area You can initialize a reception descriptor by writing in the Free Descriptor Area Base Register or the Free Descriptor Area Size Register. The Ethernet Controller starts writing to the reception queue in the reception descriptor area according to these registers. 16-34 Chapter 16 Ethernet Controller 16.3.9.4 Transmitting frames Paragraph 16.3.9.3.1 Initializing the transmission queue described transmission in a batch process. For each frame transmission batch, the system initializes the transmission queue and sets a Transmission Frame Pointer Register at the head of the queue. In the case of continuous polling transmission, the frame descriptor list ends at the dummy frame descriptor owned by the system. The Ethernet Controller enters the Polling mode when it reaches a dummy record. In this mode, the Ethernet Controller periodically checks the frame descriptor Control (FDCtl) field and waits for the system to set the COwnsFD bit. The Transmission Polling Counter Register controls the polling frequency. To transmit frames in the Continuous Polling mode, the system writes the frame descriptor of the frame to be transmitted at the end of the transmission queue. The system overwrites the old dummy frame descriptor, creates a new dummy frame descriptor, and sets the FDNext field of the old frame descriptor in a new dummy frame descriptor. After that, it sets the COwnsFD bit of the old frame descriptor and transfers ownership to the Ethernet Controller. 16.3.9.4.1 Signaling transmission completion The system can fetch transmission completion information in various ways. • • • Request an interrupt. Poll the FDCtl field of the transmitted frame descriptor and confirm system ownership. Poll the Transmission Frame Pointer Register. You can set interrupts to occur either at the end of each frame or at the end of selected frames. When polling the Transmission Frame Pointer Register, it has an invalid value (a value set in FDNext while EOL=1) in the Batch Processing mode or has a dummy frame descriptor address when in the Continuous Polling mode. 16.3.9.5 Receiving frames For the MAC to receive a frame, the system software has to perform the following operations. • • • As described in 16.3.9.3 Initializing the queues, initialize a free buffer list or free descriptor area. Write a dummy frame descriptor in a free descriptor area. Set the COwnsFD bit of the FDCtl field so the Ethernet Controller becomes the owner. Initialize Free Descriptor Area Base Register to the address of the dummy frame descriptor in the free descriptor area. There are two ways for the system software to get notification of a reception frame: • • Request an interrupt for each reception frame. Poll the dummy frame descriptor and check whether the COwnsFD bit is set. You can enable interrupts by setting the Reception Complete Interrupt Enable bit of the Reception Control Register. The system must perform the following processes after it receives a frame. • • Process the frame descriptor, and then release it for reuse. Release the buffer returned from the above protocol layer and add it to the free buffer list. 16-35 Chapter 16 Ethernet Controller 16.3.9.5.1 Processing reception frame descriptors Free descriptor areas are used by FIFOs. However, the frame processing and time required for returning the corresponding buffer differ depending on the application. Then, the frame descriptor mapped by the Ethernet Controller copies that content to a different area, the frame descriptor of the free descriptor area is released in the order received, and the copied descriptor contents are handed to the upper layer of the protocol stack. 16.3.9.5.2 Releasing buffers There are two methods of mapping a buffer: • • Start a new frame in a new buffer (Single Frame mode). Place several frames or parts of a frame in one buffer (Packed Buffer mode). The Control field of the Reception Fragment Size Register or Frame Descriptor controls the method of mapping the buffer. The Single Frame mode has the advantage of allowing easy memory management, but has the disadvantage of decreasing the memory usage efficiency. Conversely, the Packed Buffer mode has the advantage when considering memory usage efficiency, but has the disadvantage since memory management becomes complex. When in the Packed Buffer mode, multiple frames or parts of frames may be placed in the same buffer area, so you must keep several points in mind when managing the memory. The Ethernet Controller counts the number of buffers created in the same buffer area then provides that value as the RxBDSeqN value of the BDCtl field in the buffer descriptor. Then, the system software counts the returned fragments, confirms that all fragments were returned, then releases them. The buffer ID value (RxBDID) is copied from the buffer descriptor of the free buffer list queue to the buffer descriptor in the reception frame queue. You can use up to 256 buffer IDs. When you require more buffer IDs than that, there are several techniques you can use. For example, you can specify the buffer ID expansion bit in the FDSystem field. You can also use the upper bit of the buffer pointer. 16.3.9.6 Handling interrupts Interrupts generally use one common interrupt line. To confirm whether this PCI device is the interrupt source, use the system software to read the Interrupt Factor Register. Depending on the content of the Interrupt Factor Register, you may have to read other registers such as the Transmission Status Register or Reception Status Register. 16-36 Chapter 16 Ethernet Controller 16.4 Registers 16.4.1 Overview This subsection describes the Ethernet Controller registers you can access. These registers are grouped as follows below. • • • • PCI Configuration Register Group DMA Control, Status Register Group Flow Control Register Group MAC Control, Status Register Group During normal operation, once you finish setting them up, few registers require direct access. Transmission/Reception operation is performed using a cyclic queue with a ring-like structure. Control information and status information is transmitted by the data structures described in 16.3.7 Configuration. You have to initialize the DMA Control Registers before starting any transfer operation. You have to access the MAC Registers when it requires a special configuration such as address filtering by the ARC. When using an interrupt drive type, you have to access several of the DMA Registers or MAC Registers from inside the Interrupt Handler, enable or disable interrupts, check the interrupt factors, or clear the Interrupt Condition bit. Also, the Flow Control Register can use a driver to access them in order to monitor the run status of Pause commands issued from a local terminal or remote terminal. 16.4.1.1 Accessing registers Except for those that use part of RAM, the reserved bits of a register are initialized to "0" or "1". To maintain compatibility even if the method of using the registers changes in the future, do not change the values of the reserved bits when using the software to write to registers. Also, do not implement programming that depends on the values of the reserved bits. 16-37 Chapter 16 Ethernet Controller 16.4.1.2 Overview of PCI Configuration Registers Table 16.4.1 lists the name, mnemonic, address, size, and access type of each PCI Configuration Register. PCI Configuration Registers are used by standard Master/Slave PCI devices. Included in PCI Configuration Registers are Device ID Registers, Control Registers, registers that display status information, and registers that make various settings. These registers are setting during initialization. Table 16.4.1 PCI Configuration Registers Address 00h 02h 04h 06h 08h 0Ch 10h 14h 2Ch 2Eh 34h 3Ch 40h 44h Mnemonic Vend_ID Dev_ID PCI_Cmd PCI_Stat PCI_Clas PCI_Ctl IO_BaseA MLo_BaseA Sub_Vend_ID Sub_ID PCI_Cap_Ptr PCI_Int PM_Cap PM_CSR Register Name Vendor ID Register Device ID Register PCI Command Register PCI Status Register Class Code Register PCI Control Register I/O Base Address Register Memory Base Address Register Subsystem Vendor ID Register Subsystem ID Register PCI Function Pointer PCI Interrupt Register Power Management Function Power Management Control Status The address of a PCI Configuration Register is valid when the input signal IDSel is asserted. The addresses of DMA Registers and MAC Registers are valid when IDSel is not asserted and the upper bits of the addresses match either the I/O Base Address Register (IO_BaseA) or the Memory Base Address Register (MLo_BaseA). 16.4.1.3 Overview of DMA Control, Status Registers Table 16.4.2 shows the name, mnemonic, address, size, and access type of each DMA Control, Status Register. DMA Control, Status Registers control the transmission queue, reception queue, free buffer list, and free descriptor area. Registers for controlling the fragment size and polling rate are also available. Table 16.4.2 DMA Control, Status Registers Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h Mnemonic DMA_Ctl TxFrmPtr TxThrsh TxPollCtl BLFrmPtr RxFragSize Int_En FDA_Bas FDA_Lim Int_Src Register Name DMA Control Register Transmission Frame Pointer Transmission Threshold Register Transmission Polling Control Register Buffer List Frame Pointer Reception Fragment Size Register Interrupt Enable Register Free Descriptor Area Base Register Free Descriptor Area Size Register Interrupt Function Register 16-38 Chapter 16 Ethernet Controller 16.4.1.4 Overview of MAC Control, Status Registers MAC layer registers are broken down into the Flow Control Register and MAC Control, Status Register groups. Table 16.4.3 shows the name, mnemonic, address, size, and access type of each Flow Control Register. Table 16.4.3 Flow Control Registers Address 30h 34h 38h Mnemonic PauseCnt RemPauCnt TxConFrmStat Register Name Pause Count Register Remote Pause Count Register Transmission Control Frame Status Register Table 16.4.4 shows the name, mnemonic, address, size, and access type of each MAC Control, Status Register. Similar to the ARC Control Register and Error Count Register, some registers are accessed by the system software driver when the MAC is activated. A standard DMA engine controls the MAC Transmission Control Register, MAC Transmission Status Register, MAC Reception Control Register, and MAC Reception Status Register after the system software driver sets them up. Table 16.4.4 MAC Control, Status Register Address 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 7Ch Mnemonic MAC_Ctl ARC_Ctl Tx_Ctl Tx_Stat Rx_Ctl Rx_Stat MD_Data MA_CA ARC_Adr ARC_Data ARC_Ena Miss_Cnt Register Name MAC Control Register ARC Control Register Transmission Control Register Transmission Status Register Reception Control Register Reception Status Register Station Management Data Register Station Management Control, Address Register ARC Address Register ARC Data Register ARC Enable Register Missed Error Count Register MAC layer Control Registers include registers such as the Master MAC Control Register, Transmission/ Reception Control Register, and the ARC Control Register. 16-39 Chapter 16 Ethernet Controller 16.4.1.5 Register address maps Figure 16.4.1 through Figure 16.4.4 show the memory addresses of the PCI Configuration Registers, DMA Control, Status Registers, Flow Control Registers, and MAC Control, Status Registers. System memory addresses are listed in the Little Endian mode. Byte 3 Dev_ID PCI_Stat PCI_Clas PCI_Ctl Base_Cl BIST Sub_Cl Hdr_Typ Byte 2 Byte 1 Vend_ID PCI_Cmd Prog_IF Lat_Timr Rev_ID Cache_Sz Byte 0 00 04 08 0C 10 14 18 ... Sub_Vend_ID Reserved Reserved Reserved PCI_Int Max_Lat Min_Gnt PM_Cap PM_CSR Int_Pin Int_Line Cap_Ptr 2C 30 34 38 3C 40 44 IO_BaseA MLo_BaseA Reserved (MHi_BaseA) Reserved Sub_ID Figure 16.4.1 Address Map of PCI Configuration Registers Byte 3 Reserved Byte 2 TxFrmPtr Byte 1 DMA_Ctl TxThrsh TxPollCtl Byte 0 00 04 08 0C 10 14 18 1C FDA_Lim 20 24 Reserved Reserved BLFrmPtr Reserved Reserved FDA_Bas Reserved Reserved Int_Src RxFragSize Int_En Figure 16.4.2 Address Map of DMA Control, Status Registers 16-40 Chapter 16 Ethernet Controller Byte 3 Byte 2 Byte 1 Byte 0 30h 34h 38h Reserved Reserved Reserved PauseCnt RemPauCnt TxConFrmStat Figure 16.4.3 Address Map of Flow Control Registers Reserved Reserved Reserved Reserved Reserved Rx_Stat Reserved Reserved Reserved ARC_Data[3:0] Reserved Reserved Reserved Reserved Reserved MAC_Ctl Reserved Tx_Ctl Tx_Stat Rx_Ctl MD_Data MD_CA ARC_Adr ARC_Ena[2:0] Reserved Reserved Miss_Cnt ARC_Ctl 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 … 7C Figure 16.4.4 Address Map of MAC Control, Status Registers 16-41 Chapter 16 Ethernet Controller 16.4.2 PCI Configuration Register group Each PCI device has a configuration address space totaling 256 Bytes. The PCI specification prescribes the first 72 Bytes of this space in advance. An Ethernet Controller that has the wakeup service only uses the first 74-Byte address space. 16.4.2.1 Vendor ID Register (Vend_ID) 31 0x00 16 : Type : Default 15 Vendor ID Number R 0x102F : Type : Default 0 Figure 16.4.5 Vendor ID Register The Vendor ID Register stores the ID code PCI SIG, which denotes Toshiba as the component manufacturer. The ID code 0xFFFF is reserved and is invalid. Toshiba's PCI SIG number is 0x102F. 16.4.2.2 Device ID Register (Dev_ID) 31 0x02 16 : Type : Default 15 Device ID Number R 0x0031 : Type : Default 0 Figure 16.4.6 Device ID Register The Device ID Register stores a 16-bit value for identifying a particular device. The device ID number Toshiba allocated is 0x0031. The Class Code Register stores the device's revision ID. 16-42 Chapter 16 Ethernet Controller 16.4.2.3 PCI Command Register (PCI_Cmd) 31 0x04 16 : Type : Default 15 Reserved 10 9 FastEn 8 SErrEn 7 WaitCC 6 ParER 5 VGA_PS 4 MWIEn 3 SpecC 2 BusMas 1 MemS 0 IOS R 0 R/W 0 R 0 R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 : Type : Default Bit(s) 15:10 9 Mnemonic FastEn Field Name Reserved Fast Back-to-back Enable Description FastEn (fixed to "0", R) The Ethernet Controller cannot perform two consecutive bus transactions. SerrEn (Default: 0, R/W) Enables the system error (SERR#) driver. WaitCC (fixed to "0", R) The Ethernet Controller does not generate address/data stepping. ParER (Default: 0, R/W) The device responds to a parity error. VGA_PS (fixed to "0", R) Does not perform special VGA Palette Snoop. MWIEn (Default: 0, R) The Ethernet Controller does not issue the Memory Write and Invalidate command. SpecC (fixed to "0", R) The Ethernet Controller ignores special cycles. BusMas (Default: 0, R/W) The device can operate as a Bus Master. MemS (Default: 0, R/W) The device responds to memory access. IOS (Default: 0, R/W) The device responds accesses to the I/O space. 8 7 SErrEn W aitCC System Error Enable Wait Cycle Control 6 5 4 ParER VGA_PS MWIEn Parity Error Response VGA Palette Snoop Memory Write and Invalidate Enable Special Cycle Bus Master Memory Space I/O Space 3 2 1 0 SpecC BusMas MemS IOS Figure 16.4.7 PCI Command Register Hardware reset initializes the PCI Command Register to 0x0000. Software reset does not initialize the register contents. The PCI Command Register defines the method of generating and responding to PCI cycles. For details, see Subsection 6.2.2 Device Control in the PCI specification. For the Ethernet Controller to function properly, you have to set the BusMas bit and MemS bit or IOS bit. Set the SErrEn bit and the ParER bit to match the system. The FastEn, WaitCC, VGA_PS, MWIEn and SpecC bits are always "0". The Ethernet Controller ignores any writes to these bits. 16-43 Chapter 16 Ethernet Controller The Ethernet Controller has only one address comparator. The address comparator shares memory access and I/O access as described below. If MemS=0 and IOS=1, the Ethernet Controller responds to any accesses made to the I/O space. If MemS=0 and IOS=0, the Ethernet Controller does not respond to any accesses made to the I/O space or to the memory space. If MemS=1, then the Ethernet Controller only responds to accesses made to the memory space regardless of the IOS value. Also, you have to initialize the corresponding base address registers in addition to MemS and IOS. 16-44 Chapter 16 Ethernet Controller 16.4.2.4 PCI Status Register (PCI_Stat) 31 0x06 16 : Type : Default 15 DParErr 14 SSysErr 13 RMasAbt 12 RTarAbt 11 STarAbt 10 9 8 DParD R/W1C 7 FastCap 6 UDF 5 Cap66 4 ExCap 3 Reserved 0 DEVSEL R/W1C R/W1C R/W1C R/W1C R/W1C R 0 1 0 0 0 0 0 0 R 0 R 0 R 1 R 1 : Type : Default Bit(s) 15 Mnemonic DParErr Field Name Detected Parity Error Description DParErr (Default: 0, R/W) Indicates that a parity error was detected. This bit is set if a parity error is detected even when the register's Parity Error Response bit is not set. This also applies to parity errors occurring during an address cycle. SSysErr (Default: 0, R/W) This bit is set when the device asserts SERR#. RMasAbt (Default: 0, R/W) Indicates that the current device is the Bus Master and that Master Abort ended the Bus Master transaction (excluding special cycles). 14 13 SSysErr RMasAbt Signal System Error Receive Master Abort 12 RTarAbt Receive Target Abort RTarAbt (Default: 0, R/W) Indicates that the current device is the Bus Master and that Target Abort ended the Bus Master transaction. STarAbt (Default: 0, R/W) Indicates the current device is the target and that Target Abort ended the Bus Master transaction. DEVSEL (Fixed to "01", R) The latest output timing of DEVSEL# when the Ethernet Controller is accessed as the target device is "medium speed". This field is encoded as follows. 00: Fast 01: Medium Speed 10: Slow DParD (Default: 0, R/W) This bit is set when all of the three following conditions are met. 1: PERR# was asserted as the Bus Master, but the target asserted it. 2. The agent that set PERR# was the Bus Master. 3. The Parity Error Response bit of the PCI Control Register is set to "1". 11 STarAbt Signal Target Abort 10:9 DEVSEL Device Select Timing 8 DParD Detect Data Parity Error 7 FastCap Fast Back-to-back Capable FastCap (fixed to "0", R) The Ethernet Controller cannot perform consecutive transactions from different agents. UDF (fixed to "0", R) Indicates that there are no user-defined functions in the Ethernet Controller. Cap66 (fixed to "1", R) Indicates that the Ethernet Controller can operate at 33-66 MHz. ExCap (fixed to "1", R) Indicates that the Ethernet Controller has extended functions. 6 UDF User Defined Function 5 Cap66 66 MHz Operation Capable 4 3:0 ExCap Extended Function Reserved Figure 16.4.8 PCI Status Register 16-45 Chapter 16 Ethernet Controller Software reset initializes the PCI Status Register to 0x0230. The PCI Status Register retains status information on events relating to the PCI Bus. There are several points about this register that you should keep in mind. First, writing "1" to a bit in this register clears it to "0". Also, the value of each bit does not change when you write "0" to it. This enables the system and PCI device to simultaneously update the status information. For details, see Subsection 6.2.3 Device Status of the PCI specification. 16-46 Chapter 16 Ethernet Controller 16.4.2.5 Class Code Register (PCI_Clas) 31 Base_Cl R 0x02 15 Prog_IF R 0x00 8 7 Rev_ID R 0x41 : Type : Default 24 0x08 23 Sub_Cl R 0x00 0 : Type : Default 16 Bit(s) 31:24 23:16 15:8 7:0 Mnemonic Base_CI Sub_Cl Prog_IF Rev_ID Field Name Base Class ID Subclass ID Programming Interface Revision ID Description Base_Cl (fixed to "0x02", R) Sub_Cl (fixed to "0x00", R) Is defined in the Ethernet Controller. Prog_IF (fixed to "0x00", R) The register-level programming interface is not defined. Rev_ID (fixed to "0x41", R) Is set to "0x41" for this Ethernet Controller. Figure 16.4.9 Class Code Register 16-47 Chapter 16 Ethernet Controller 16.4.2.6 PCI Control Register (PCI_Ctl) 31 BIST R 1 15 R/W 0 Lat_Timr R/W 0x00 R 0x0 8 7 Reserved 0x0C 24 23 Hdr_Typ R 0x00 6 Cache_Sz R/W 0x00 : Type : Default 0 : Type : Default 16 Bit(s) 31:24 23:16 Mnemonic BIST Hdr_Typ Field Name Embedded Self-Test Header Type Description BISAT (Default: 0x80, R/W) Controls whether to invoke BIST during startup. Hdr_Typ (fixed to "0x00", R) This is a single-function device. The range 0x10-0x3F of the configuration space is the standard layout. Lat_Tmr (DefaultA: 0x00, R/W) Sets the time the Ethernet Controller operates as the Bus Master as a PCI Bus Clock count. Cache_Sz (Default: 0x00, R/W) Sets the system cache line size. 15:8 Lat_Timr Latency Timer 7 6:0 Cache_Sz Reserved Cache Line Size Figure 16.4.10 PCI Control Register Hardware reset initializes the PCI Control Register to 0x8000_0000. Software reset does not change the register contents. BIST is used for testing the buffers on the chip. Bit 31 of the BIST field is read only and is fixed to "1". In other words, the Ethernet Controller supports BIST. Bit 30 is used to start invoking BIST. Writing "1" to bit 30 starts a test. This bit is cleared when a test ends. If an error occurs in a test, then either bit 25 or bit 24 is set. Bit 25 is set if a parity error occurs when starting up SRAM inside DMA. Bit 24 indicates that there is a fault in the SRAM in DMA. In other words, it indicates that the read data and the expected value (read data) do not match. Bits 29:26 are reserved. The software driver invokes BIST during initialization. (Note: Invoking BIST affects operation since RAM data and RAM registers are overwritten.) When the clock is 33 MHz, testing 1 K × 4-Byte memory requires approximately 123 µs. The default value of the latency timer is 0. You can use a program to set the latency timer. After performing a hardware reset, the cache line size is initialized to 0. You must use the software driver to set an appropriate default value. In most cases, the recommended value is 8 double words (32 Bytes). The maximum value of the cache line size is 127 double words. The cache line size is used to select the Memory Read Multiple command or Memory Read Line command and perform Burst reads. 16-48 Chapter 16 Ethernet Controller 16.4.2.7 I/O, Memory Base Address Registers I/O Base Address Register (IO_BaseA) 0x10 The I/O Base Address Register and Memory Base Address Register are used to map the DMA and MAC Control Registers or Status Registers to the I/O address space or system memory space. Both the I/O address space and memory address space have a maximum size of 32 bits. In addition to setting the Base Address Register, you have to set the corresponding Control bits in the PCI Command Register. 31 BaseAddr R/W 0x0000 8 7 BaseAddr R/W 0x00 : Type : Default 16 15 0 0 I/O R 1 : Type : Default Bit(s) 31:8 7:1 0 Mnemonic BaseAddr Field Name Base Address Description BaseAddr (Default: 0x000000, R/W) This field sets the upper 24 bits of the base address Fixed to “0”. I/O I/O Flag I/O (fixed to “1”, R) Indicates that this base address is relative to the I/O space. Figure 16.4.11 I/O Base Address Register 16-49 Chapter 16 Ethernet Controller Hardware resets initialize the I/O Base Address Register to 0x0000_0001. Software resets do not change the register contents. Memory Address Register (MLo_BaseA) 31 BaseAddr R/W 0x0000 8 7 BaseAddr R/W 0x00 0 : Type : Default 4 3 2 Loc R 0x0 1 0 I/O R 0 : Type : Default 0x14 16 15 Bit(s) 31:8 7:3 2:1 Mnemonic BaseAddr Field Name Base Address Description BaseAddr (Default: 0x00_0000, R/W) This field sets the upper 24 bits of the base address. Fixed to “0”. Loc Location Bit Loc (Default: 00, R) This field indicates that memory is placed in a 32-bit address space. I/O (Default: 1, R) Indicates that this base address is relative to the memory space. 0 I/O I/O Flag Figure 16.4.12 Memory Base Address Register Hardware resets initialize the Memory Base Address Register to 0x0000_0000. Software resets do not change the register contents. 16-50 Chapter 16 Ethernet Controller 16.4.2.8 Subsystem Vendor ID Register, Subsystem ID Register Subsystem Vendor ID Number Register (Sub_Vend_ID) 31 0x2C 16 : Type : Default 15 Subsystem Vendor ID Number R 0x0000 : Type : Default 0 Figure 16.4.13 Subsystem Vendor ID Number Register The Subsystem Vendor ID Register stores the PCI SIG ID number that denotes the adapter card manufacturer. In the case of the TX4938, this value is 0 since it uses an on-chip PCI device. Subsystem ID Register (Sub_ID) 0x2E 31 16 : Type : Default 15 Subsystem ID Number R 0x0000 : Type : Default 0 Figure 16.4.14 Subsystem ID Register The Subsystem ID Register stores a 16-bit value for identifying a particular device. In the case of the TX4938, this value is 0. 16-51 Chapter 16 Ethernet Controller 16.4.2.9 PCI Function Pointer Register (PCI_Cap_Ptr) 31 Reserved : Type : Default 15 Reserved 8 7 CapPtr R 0x40 : Type : Default 0 0x34 16 Bit(s) 31:8 7:0 Mnemonic CapPtr Field Name Reserved Function Pointer Description CapPtr (Fixed to “0x40”, R) This field is the offset of the first entry in the function list. Figure 16.4.15 PCI Function Pointer Register 16.4.2.10 PCI Interrupt Register (PCI_Int) 31 Max Lat R 0x00 15 Int Pin R 0x01 8 7 Int Line R/W 0x00 : Type : Default 24 0x3C 23 Min Gnt R 0x00 0 : Type : Default 16 Bit(s) 31:24 23:16 Mnemonic Max_Lat Min_Gnt Field Name Maximum Latency Minimum Grant Description Max_Lat (Fixed to “0x00”, R) Sets the latency timer value (unit: 1/4 µs). Min_Gnt (Fixed to “0x00”, R) Assuming the PCI clock is 33 MHz, this field sets the time required for Burst transfer (unit: 1/4 µs). Int_Pin (Fixed to “0x01”, R) Is set to INTA#. Int_Line (Default: 0x00, R/W) Is set by the system. Is the connection information of the interrupt line. 15:8 7:0 Int_Pin Int_Line Interrupt Pin Function Pointer Figure 16.4.16 PCI Interrupt Register When the value of Max_Lat and Min_Gnt is 0, you do not use the PCI Interrupt Register to determine Maximum Latency and Minimum Grant. To check whether this PCI device caused an interrupt, use the software to access the Interrupt Source Register. For details, see 16.4.3.9 Interrupt Source Register. 16-52 Chapter 16 Ethernet Controller 16.4.2.11 PCI Power Management Registers Power Management Function Register (PM_Cap) 31 27 26 25 24 Reserved 22 0x40 21 20 19 18 16 : Type : Default 15 8 7 Reserved 0 : Type : Default Bit(s) 31:0 Mnemonic Field Name Reserved Description Reserved The Ethernet Controller does not support the Power Management Function Register. Figure 16.4.17 Power Management Function Register Power Management Control, Status Register (PM_CSR) 31 24 23 Reserved 0x44 16 : Type : Default 15 14 13 12 9 8 7 Reserved 2 1 0 : Type : Default Bit(s) 31:0 Mnemonic Field Name Reserved Description Reserved The PCI Controller does not support the Power Management Control, Status Register. Figure 16.4.18 Power Management Control, Status Register 16-53 Chapter 16 Ethernet Controller 16.4.3 DMA Control, Status Register group The DMA engine and system software jointly manage three queues: the transmission queue, the reception queue, and the buffer list. The transmission queue is used for frame descriptors that are ready for transmission and are standing by. The reception queue is used for frame descriptors that have been received and are waiting for processing by the system software. The buffer list is a buffer descriptor queue. Buffer descriptors describe system memory areas that can be used to store reception data. The free descriptor area (FDA) is a memory area that the Ethernet Controller can write transmission queue frame descriptors and buffer list descriptors to. 16-54 Chapter 16 Ethernet Controller 16.4.3.1 DMA Control Register (DMA_Ctl) 31 Reserved 24 0x00 23 22 21 20 19 M66En Stat 18 IntMask 17 SWInt Req 16 TxWake Up RxAlign R/W 0x0 Reserved R 0/1 DmBurst 15 RxBigE 14 TxBigE 13 Test Mode 12 Reserved 9 8 R/W 0 2 R/W R/W 0 0 1 0 Reserved : Type : Default R/W 0 R/W 0 R/W 0 R/W 0x08 : Type : Default Bit(s) 31:24 23:22 Mnemonic RxAlign Field Name Reserved Reception Alignment Description D2Supp (Default: 0x0, R/W) This field controls the alignment of reception packets as follows: 01: Skips the first byte of the first buffer. 10: Skips the first or second byte of the first buffer. 11: Skips the first through third byte of the first buffer. M66EnStat (Fixed to 0/1, R) 1: Indicates that the PCI Bus operates at a maximum of 66 MHz. 0: Indicates that the PCI Bus operates at 33 MHz or less. IntMask (Default: 0, R/W) Setting this bit to “1” disables the interrupt request signal. SWIntReq (Default: 0, R/W) Setting this bit to “1” issues an interrupt request. TxWakeUp (Default 0, R/W) Setting this bit to “1” ends the current polling cycle and starts transmission. RxBigE (Default: 0, R/W) Setting this bit to “1” processes reception data in the Big Endian mode. TxBigE (Default: 0, R/W) Setting this bit to “1” processes transmission data in the Big Endian mode. TestMode (Default: 0, R/W) Enables the test mode function. 21:20 19 M66EnStat Reserved 66 MHz Enable State 18 17 16 IntMask SWIntReq TxWakeUp Interrupt Mask Software Interrupt Request Transmission Wake Up 15 RxBigE Reception Big Endian 14 TxBigE Transmission Big Endian 13 12:9 8:2 TestMode Test Mode Reserved DmBurst DMA Burst Size DmBurst (Default: 0x08, R/W) Indicates the Burst size of data transfer executed in the Master mode. 1:0 Reserved Figure 16.4.19 DMA Control Register 16-55 Chapter 16 Ethernet Controller Hardware resets initialize the DMA Control Register as follows: • • 0000_1020h: 0008_1020h: When the PCI Bus speed is 0-33 MHz When the PCI Bus speed is 33-66 MHz 0x20 of the lower byte denotes the default (32 Bytes = 8 double words) of the DMBurst field. The DMA Control Register controls data transfer functions in the Master mode such as the Burst side, Big Endian handling, and the test mode. This register also controls various DMA functions during transmission such as wake up and software interrupts. The DmBurst field controls the data transfer size with which the PCI Bus was used when operating in the Master mode. Bits 8:0 set the data transfer size (DMA Burst size), but the lower 2 bits are fixed to “0” and must be a multiple of 4. After a hardware reset, the default value becomes 32 Bytes, in other words 8 double words. You can change this value using a software driver. You cannot set the DmBurst field to “0”. Writing of “0” to this field is ignored. Generally, a multiple of the PCI cache line size is set in the DmBurst field. If the Burst size is 4, 8 or 12 when in the 100 Mbps full duplex mode, you have to take into consideration throughput reduction of the PCI Bus. The TestMode bit enables test functions such as those that enable reading or writing to all areas of the internal DMA buffer or those that display internal status information in the reserved bits of a register. The TxBigE bit and RxBigE bit enable the transmitting or receiving of data with Big Endian mode devices. However, it is important to note that only the data (bytes in the area designated by the buffer descriptor) is handled in the Big Endian mode. Control information such as frame descriptors and buffer descriptors are always in a format unique to the PCI Bus. In other words, they are in the Little Endian format. The TxWakeUp bit enables immediate data transmission without waiting for the end of the current polling cycle. Setting the TxWakeUp bit to “1” while the transmitter is polling aborts the current polling cycle. When the current polling cycle ends, the current TxWakeUp bit is cleared. Any writing of “0” to the TxWakeUp bit is ignored. Software interrupts are made available to support software drivers. The IntMask bit disables all interrupt sources. Therefore, even when the processing of interrupt sources is in progress, the software driver can put interrupts in the Enable state again. The M66EnStat bit is used to control the MAC clock divide circuit when driving serial addresses of the MII station manager. 16-56 Chapter 16 Ethernet Controller 16.4.3.2 Transmission Frame Pointer Register 0x04 31 Addr R/W 0x0000 15 Adrr R/W 0x000 4 3 2 Reserved 1 0 EOL R/W 1 : Type : Default : Type : Default 16 Bit(s) 31:4 Mnemonic Address Field Name Description Addr (Default: 0x000_0000, R/W) Retains the address of the first frame descriptor to be transmitted. EOL (Default: 1, R/W) When this bit is set to “1”, the Address field is ignored. The Ethernet Controller waits for the system to clear it. 3:1 0 EOL Reserved End of List Figure 16.4.20 Transmission Frame Pointer Register Software resets initialize the Transmission Frame Pointer Register to 0x0000_0001. Software resets set the EOL bit to “1”. To enable polling of a transmission or the packet to be transmitted, the system has to set this register in a properly initialized frame descriptor. The address has to be aligned to a 16-Byte boundary. Therefore, bits 0-3 must be “0”. For information on polling control methods, see the description in 16.4.3.4 Transmission Polling Control Register. 16-57 Chapter 16 Ethernet Controller 16.4.3.3 Transmission Threshold Register (TxThrsh) 31 Reserved : Type : Default 15 Reserved 11 10 TxThold R/W : Type : Default 0 0x08 16 Bit(s) 31:11 10:0 Mnemonic TxThold Field Name Reserved Transmission Threshold Register Description TxThold (Default: -, R/W) The Transmission Threshold Register controls buffer latency when transmitting packets. Figure 16.4.21 Transmission Threshold Register The Transmission Threshold Register uses part of internal RAM, so it is not affected by hardware resets or software resets. The Transmission Threshold Register controls buffer latency when transmitting packets. If the threshold value is not “0”, data transfer to the MAC starts either when the number of data bytes set by the threshold value (TxThold) has accumulated in the DMA Transmission buffer or when an entire packet is stored in the DMA Transmission buffer. When the threshold value is “0”, data is transferred to the MAC immediately after the data is fetched from the PCI Bus. The software driver initializes the Transmission Threshold Register. When the threshold value (TxThold) is too small, the DMA Transmission buffer immediately becomes free due to the PCI Bus latency. This situation is displayed in the MAC transmission status, so the system software increases the threshold value. Be careful to not make the threshold value greater than 1620. Having a threshold value greater than 1620 when in the Long Packet mode causes buffer memory to become full before transmission is enabled, therefore causing the transmission circuit to hang. 16-58 Chapter 16 Ethernet Controller 16.4.3.4 Transmission Polling Control Register (TxPollCtl) 31 Reserved : Type : Default 15 Reserved 12 11 TxPollCtl R/W : Type : Default 0 0x0C 16 Bit(s) 31:12 11:0 Mnemonic TxPollCtl Field Name Reserved Transmission Polling Control Register Description TxPollCtl (Default: -, R/W) The Transmission Polling Control Register controls the frequency at which packets to be transmitted are polled. Figure 16.4.22 Transmission Polling Control Register The Transmission Polling Control Register uses part of internal RAM, so it is not affected by hardware resets or software resets. The Transmission Polling Control Register controls the frequency at which packets to be transmitted are polled. The TxPollCtl field operates as a counter. When a value is set to it, it decrements until it reaches 0. When it reaches 0, it polls to see if preparations for the next transmission packet are complete. No polling is performed when 0 is set in the TxPollCtl field. When the clock frequency is 33 MHz, the counter units equate to 61.44 µs. The software driver initializes this register. The software driver also sets the count value. 16-59 Chapter 16 Ethernet Controller 16.4.3.5 Buffer List Frame Pointer (BLFrmPtr) 0x10 31 Addr R/W 0x0000 15 Addr R/W 0x00 4 3 2 1 Reserved 0 EOL R/W : Type 1 : Default : Type : Default 16 Bit(s) 31:4 4:1 0 Mnemonic Address Field Name Reserved Description Addr (Default: 0x000_0000, R/W) EOL (Default: 1, R/W) When this bit is set to “1”, the Address field is ignored. You have to wait until the system clears this bit. EOL End of List Figure 16.4.23 Buffer List Frame Pointer Software resets initialize the Buffer List Frame Pointer to 0x0000_0001. When it fetches a free buffer descriptor, the Buffer List Frame Pointer holds the address of the first frame descriptor to be read. To enable data reception, the system has to set this register in a properly initialized frame descriptor. The address must be aligned to a 16-Byte boundary. In other words, bits 0-3 must be “0”. 16-60 Chapter 16 Ethernet Controller 16.4.3.6 Reception Fragment Size Register (RxFragSize) 31 Reserved : Type : Default 15 EnPack 0x14 16 14 Reserved 12 11 MinFrag R/W 0x000 2 1 0 Reserved : Type : Default R/W 0 Bit(s) 31:16 15 Mnemonic EnPack Field Name Reserved Enable Packing Description EnPack (Default: 0, R/W) 1: Uses the MinFrag value for buffer packing control. 0: Uses the FDCtl field of the frame descriptor for buffer packing control. 14:12 11:2 MinFrag Reserved Minimum Fragments MinFrag (Default: 0x000, R/W) The minimum byte count when partially writing to a buffer that contains data. 1:0 Reserved Figure 16.4.24 Reception Fragment Size Register Hardware resets initialize the Reception Fragment Size Register to 0x0000_0000. Software resets do not change the register contents. The Reception Fragment Size Register specifies the size of minimum data fragments that the Ethernet Controller generates. The minimum fragment size must be a multiple of 4. Therefore, the lower 2 bits are always “0”. You can use the EnPack bit to globally enable packing, or you can enable packing in buffer-area units. For more information on the enabling of packing in bufferarea units, see the description in 16.3.7.1.5 FDCtl field (frame descriptor control). The Ethernet Controller always stores reception data in addresses aligned to 4-Byte boundaries. Therefore, the last 1-3 bytes of a frame may be unused. When enabling packing, the MinFrag value must be greater than 0 for the Ethernet Controller to function properly. When using packing, use a software driver to set the MinFrag field and EnPack bit. When not enabling packing, the MinFrag value must remain at “0”. Packing is performed when more than the Minimum Fragment Size + 4 Bytes in the buffer is free. Packing is not performed when the amount of free space in the buffer is less than the Minimum Fragment Size. In this case, data is stored starting from the next buffer. 16-61 Chapter 16 Ethernet Controller 16.4.3.7 Interrupt Enable Register (Int_En) 31 Reserved : Type : Default 15 Reserved 12 11 NRAbt En 0x18 16 10 TxCtlC mpEn 9 DmPar ErrEn 8 DPar DEn 7 EarNot En 6 5 4 3 RTarg AbtEn 2 STarg AbtEn 1 BLExE n 0 FDAE xEn DPar SSvsEr Rmas ErrEn rEn AbtEn R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 : Type : Default Bit(s) 31:12 11 Mnemonic NRAbtEn Field Name Reserved Non-recoverable Abort Enable Description NRAbtEn (Default: 0, R/W) Enables interrupts when a non-recoverable abort occurs internally. TxCtlCmpEn (Default: 0, R/W) Enables interrupts when transmission of the MAC control frame is complete. DmParErrEn (Default: 0, R/W) Enables interrupts if a parity error is detected when reading or writing from/to DMA-internal RAM. DParDEn (Default: 0, R/W) Enables interrupts when bit 8 of the PCI Status Register is set. EarNotEn (Default: 0, R/W) When receiving a reception packet, issues an interrupt not only when reaching the tail of a packet, but also issues an interrupt when writing the first buffer or its descriptor. DParErrEn (Default: 0, R/W) Enables interrupts if a parity error is detected during PCI Bus transfer while the Ethernet Controller is accessing the Bus Master. SSvsErrEn (Default: 0, R/W) Enables interrupts if the Ethernet Controller signals a system error. RmasAbtEn (Default: 0, R/W) Enables interrupts if a Master Abort is received while the Ethernet Controller is operating as the Target. RTargAbtEn (Default: 0, R/W) Enables interrupts if a Target Abort is received while the Ethernet Controller is operating as the Target. STargAbtEn (Default: 0, R/W) Enables interrupts if a Target Abort is issued while the Ethernet Controller is operating as the Target. BLExEn (Default: 0, R/W) Enables interrupts when the buffer list is completely used up. In other words, enables interrupts when the Ethernet Controller encounters descriptors owned by the system that still remain in the buffer list. FDAExEn (Default: 0, R/W) Enables interrupts when the free descriptor area is totally used up. In other words, enables interrupts when the Ethernet Controller encounters blocks owned by the system that still remain in the FDA. 10 TxCtlCmpEn MAC Control Frame Transmission Complete Enable DMA Parity Error Enable 9 DmParErrEn 8 7 DParDEn EarNotEn Data Parity Detection Enable Early Notification Enable 6 DParErrEn Parity Error Detection Enable 5 SSvsErrEn System Error Notification Enable Master Abort Reception Enable 4 RmasAbtEn 3 RTargAbtEn Target Abort Reception Enable 2 STargAbtEn Target Abort Notification Enable 1 BLExEn Buffer List Exhaustion Notification Enable 0 FDAExEn Free Descriptor Area Exhaust Notification Enable Figure 16.4.25 Interrupt Enable Register 16-62 Chapter 16 Ethernet Controller Hardware resets initialize the Interrupt Enable Register to 0x0000_0000. Software resets do not change the register contents. The Interrupt Enable Register controls whether to issue an interrupt in response to errors detected by the DMA engine or in response to some other conditions. The Early Notification Enable (EarNotEn) bit is shared by applications that are required to reduce latency. When handling Early Notification, note that the frame descriptor becomes invalid. Only the first buffer descriptor is valid if an Early Notification interrupt occurs. 16-63 Chapter 16 Ethernet Controller 16.4.3.8 Free Descriptor Area (FDA) Registers Free Descriptor Area Base Register (FDA_Bas) 31 Addr R/W 0x0000 15 Addr R/W 0x000 4 3 2 1 Reserved 0 : Type : Default 0x1C 16 : Type : Default Bit(s) 31:4 Mnemonic Address Field Name Description Addr (Default: 0x000_0000, R/W) The Free Descriptor Area Base Register contains the start address of the area for writing the frame descriptors and buffer descriptors of reception packets. The address must be a multiple of 16 Bytes. Therefore, bits 0-3 are fixed to "0". 3:0 Reserved Figure 16.4.26 Free Descriptor Area Base Register Hardware resets initialize the Free Descriptor Area Base Register to 0x0000_0000. Software resets do not change the register contents. Free Descriptor Area Size Register (FDA_Lim) 31 Reserved : Type : Default 15 Count/Offset R/W 0x000 4 3 Reserved : Type : Default 0 0x20 16 Bit(s) 31:16 15:4 Mnemonic Count/Offset Field Name Reserved Count/Offset Description Count/Offset (Default: 0x000, R/W) This field sets the size of the Reception Descriptor Area in 16Byte units. You could also consider the lower 16 bits as being an offset from the base address. 3:0 Reserved Figure 16.4.27 Free Descriptor Area Size Register 16-64 Chapter 16 Ethernet Controller Hardware resets initialize the Free Descriptor Area Size Register to 0x0000_0000. Software resets do not change the register contents. Note: You have to specify in the FDA_Lim Register the minimum offset value of the free descriptor area from which it is safe to start the next frame descriptor. You have to secure an area that is sufficient for storing a maximum size packet that includes one frame descriptor and the maximum number of buffer descriptors. For example, if the maximum number of buffer descriptors required to store a maximum length frame is 28, then this area requires a capacity of 256 (16 + 28 × 8 in 16-Byte units) Bytes. 16-65 Chapter 16 Ethernet Controller 16.4.3.9 Interrupt Source Register (Int_Src) 31 Reserved 0x24 17 16 IntEX Defer R/W1C 15 Reserved 14 NRAbt 13 DmPar ErrStat R/W1C 12 BLEx 11 FDAEx 10 IntNRA bt R 9 IntTxCtl Cmp R/W1C 8 IntExB D R/W1C 7 DmPar Err R 6 IntEarN ot R/W1C 5 SWInt 4 IntBLEx 3 IntFDA Ex R 2 IntPCI 1 0 0 : Type : Default IntMacR IntMacT x x R/W1C R/W1C R/W1C R/W1C R/W1C R R R : Type : Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit(s) 31:17 16 Mnemonic IntEXDefer Field Name Reserved Description IntEXDefer (Default: 0, R/W1C) This bit is set if an excessive delay is detected and the EnExDefer (Excessive Defer Enable) bit of the Transmission Control Register (Tx_Ctl) is set. 15 14 13 12 11 NRAbt DmParErrStat BLEx FDAEx Reserved NRAbt (Default: 0, R/W1C) This bit is set to "1" when a non-recoverable abort occurs. DmParErrStat (Default: 0, R/W1C) This bit is set to "1" when a DMA parity error occurs. BLEx (Default: 0, R/W1C) This bit is set to "1' when the buffer list (BL) becomes full. FDAEx (Default: 0, R/W1C) This bit is set to "1" when the free descriptor area (FDA) becomes full. IntNRAbt (Default: 0, R) The interrupt source is a non-recoverable abort state. IntTxCtlCmp (Default: 0, R/W1C) The interrupt source is the completion of MAC control frame transmission. IntExBD (Default: 0, R/W1C) The interrupt source is excessive buffer descriptors (more than 28 buffer descriptors). DmParErr (Default: 0, R) The interrupt source is a DMA parity error. IntEarNot (Default: 0, R/W1C) The interrupt source is early notification. SWInt (Default: 0, R) The interrupt source is a software interrupt request. IntBLEx (Source: 0, R) The interrupt source is the buffer list being completely used up. IntFDAEx (Default: 0, R) The interrupt source is the free descriptor area being completely used up. IntPCI (Default: 0, R) The PCI Status Register (PCI_Stat) displays the interrupt source. 10 9 IntNRAbt IntTxCtlCmp 8 IntExBD 7 6 5 4 DmParErr IntEarNot SWInt IntBLEx 3 IntFDAEx 2 IntPCI Figure 16.4.28 Interrupt Source Register (1/2) 16-66 Chapter 16 Ethernet Controller Bit(s) 1 Mnemonic IntMacRx Field Name Description IntMacRx (Default: 0, R/W1C) The MAC Reception Status Register (Rx_Stat) displays the interrupt source. IntMacTx (Default: 0, R/W1C) The MAC Transmission Status Register (Tx_Stat) displays the interrupt source. 0 IntMacTx Figure 16.4.28 Interrupt Source Register (2/2) Writing "1" to W1Clr clears it to "0". This bit denotes the bits that clear interrupts. Any writing of "0" to these bits is ignored. "R" indicates that a bit is Read Only. Either clearing the source that set these bits to "1" or resetting Ethernet control clears these bits to "0". Software resets initialize the Interrupt Source Register to 0x0000_0000. The system software reads the Interrupt Source Register to check whether there are any interrupts related to Ethernet control. Also, the Interrupt Source Register contains several status bits that can only be displayed here. If bits 15:0 are all "0", this indicates that the Ethernet Controller did not issue any interrupts. If the Ethernet Controller causes any interrupts, then setting the IntMask bit of the DMA Control Register makes it possible to mask any subsequent interrupts that the Ethernet Controller issues. Bit 8 is set when there are more than 28 buffer descriptors are in a single frame descriptor. If excessive buffer descriptors occur, the controller aborts transmission or reception operation. To resume transmission or reception operation, you have to perform a software reset and rebuild the transmission queue, reception queue, and buffer list. Bit 13 is set when a parity error is detected in the DMA RAM. However, bit 7 is only set if the DParErrEn bit of the Interrupt Enable Register is set. To make it possible to handle as many completed transmission frames or reception frames as possible, the software driver has to clear the IntMACTx bit or the IntMACRx bit. Since the frame that is the interrupt source is handled as a part of the immediately previous interrupt, there are cases where there are no complete frames in an interrupt. Take this into account when creating your software driver. 16-67 Chapter 16 Ethernet Controller 16.4.4 Flow Control Register group Pause Count Register (PauseCnt) 0x30 31 Reserved : Type : Default 15 8 7 PauseCnt R 0x0000 0 16 : Type : Default Bit(s) 31:16 15:0 Mnemonic PauseCnt Field Name Reserved Reception Pause Count Description PauseCnt (Default: 0, R) This is the number of time slots that the transmitter pauses as a result of receiving a MAC control Pause operation packet. Figure 16.4.29 Pause Count Register Remote Pause Count Register (RemPauCnt) 31 Reserved : Type : Default 15 8 7 RemPauCnt R 0x0000 0 0x34 16 : Type : Default Bit(s) 31:16 15:0 Mnemonic RemPauCnt Field Name Reserved Remote Pause Count Description RemPauCnt (Default: 0, R) This is the number of time slots that the remote MAC pauses as a result of transmitting a Pause operation packet. Figure 16.4.30 Remote Pause Count Register Software resets initialize the Pause Count Register and Remote Pause Count Register to 0x0000_0000. The Pause Count Register displays the current value of the received Pause count. When a Pause operation MAC control frame is received, the specified Pause count is set and the count is decremented at each unit time stamp. When the count is "0", it indicates that MAC is not pausing. The Remote Pause Count Register displays a rough value of the pause counter that the remote station has based on the transmitted Pause command. In either case, the unit is 1 slot time. In other words, it is 512-bit late time. 16-68 Chapter 16 Ethernet Controller Transmission Control Frame Status Register (TxCtlFrmStat) 31 Reserved 22 21 Tx_Stat Value R/W 15 Tx_Stat Value R/W : Type : Default 0 : Type : Default 0x38 16 Bit(s) 31:22 21:0 Mnemonic Tx_Stat Value Field Name Reserved Transmission Control Frame Status Description Tx_Stat (Default: -, R/W) The Transmission Control Frame Status Register displays via the SdPause bit of the Transmission Control Register the status from when the MAC control frame was transmitted to a remote station. Figure 16.4.31 Transmission Control Frame Status Register The Transmission Control Frame Status Register uses part of the internal RAM, so it is not affected by hardware resets or software resets. The Transmission Control Frame Status Register displays via the SdPause bit of the Transmission Control Register the status when the MAC control frame was transmitted to a remote station. After transmission ends, the software driver fetches the status from this register. The software can reset this register before starting transmission of the MAC control frame. The software can use the TxCtlCmpEn bit of the Interrupt Enable Register to issue an interrupt when transmission of the MAC control frame ends. For information on the bit fields, see the explanation of the Transmission Status Register (Tx_Stat) in 16.4.5.3 Transmission Control, Status Registers. 16-69 Chapter 16 Ethernet Controller 16.4.5 MAC Control, Status Register group 0x40 16 Reserved : Type : Default 15 14 13 EnMiss Roll 16.4.5.1 MAC Control Register (MAC_Ctl) 31 12 11 10 Miss Roll 9 8 Reserved 7 6 Conn 5 4 Mac Loop 3 FullDup 2 Reset 1 HaltI mm 0 Halt Req Reserved Reserved R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 : Type : Default Bit(s) 31:14 13 Mnemonic EnMissRoll Field Name Reserved Missing Error Counter Rollover Enable Reserved Missing Error Counter Rollover Reserved Description EnMissRoll (Default: 0, R/W) Issues an interrupt when the count value of the Missing Error Count Register rolls over from 0x7FFF to 0x8000. MissRoll (Default: 0, R) Indicates that the count value of the Missing Error Count Register rolled over from 0x7FFF to 0x8000. (Read only) Conn (Default: 00, R/W) This field selects the connection mode. 00: Automatic (default) 01: Reserved 10: MII (MII clock determines the transfer rate) 11: Reserved 12:11 10 MissRoll 9:7 6:5 Conn Connection Mode 4 MacLoop MAC Loop Back MacLoop (Default: 0, R/W) Directly provides the transmission signal as the input of the reception circuit without sending it outside the Ethernet Controller. FullDup (Default: 0, R/W) Set this bit to "1" for full duplex. Reset (Default: 0, R/W) Resets all State Machines and FIFOs of the Ethernet Controller. HaltImm (Default: 0, R/W) Immediately halts transmission or reception when set to “1”. When receiving data, if this bit is set after MAC starts processing the recipient address, reception operation for the current packet continues and the data is transferred to system memory. At this time, if the RxHalted bit of the Reception Status Register is set, it indicates that the system sent a Reception Halt Request while a packet was being received. If this bit is set before starting processing of the recipient address, reception operation is immediately halted. The RxHalted bit will then be set. 3 2 1 FullDup Reset HaltImm Full Duplex Mode Software Reset Immediate Halt 0 HaltReq Halt Request HaltReq (Default: 0, R/W) Halts transmission/reception when the packet currently in progress ends. Figure 16.4.32 MAC Control Register 16-70 Chapter 16 Ethernet Controller Hardware resets initialize the MAC Control Register to 0x8000. Setting the Reset bit (bit 2) executes software reset. Starting software reset clears bit 2. The other bits do not affect software resets. The MAC Control Register is used to display total control and status information of MAC. The MissRoll bit is the status bit. All other bits are control bits. After the Reset bit is set, 4 MII transmission or reception clock cycles pass, then software reset is executed for several cycles. Therefore, after writing to the Reset bit, do not access the Ethernet Controller until 320 ns pass for 100 Mbps transfer or until 3,200 ns pass for 10 Mbps transfer. Before performing reset, you can use the MAC Transmission Control Register (Tx_Ctl) or MAC Reception Control Register (Rx_Ctl) to issue a Halt Request to end the current network transaction. The MissRoll bit is set when the counter rolls over from 0x7FFF to 0x8000, and is reset when the software reads the Missing Error Count Register. See 16.4.5.7 Missing Error Count Register for an explanation. Some PHYs do not support full duplex transfer. The MacLoop bit has higher priority than the FullDup bit. 16-71 Chapter 16 Ethernet Controller 16.4.5.2 ARC Control Register 31 Reserved : Type : Default 15 Reserved 5 4 Com pEn 0x44 16 3 NegA RC 2 Broa dAcc 1 Grou pAcc 0 Statio nAcc R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 : Type : Default Bit(s) 31:5 4 Mnemonic CompEn Field Name Reserved Compare Enable CompEn (Default: 0, R/W) Enables the Compare mode. NegARC (Default: 0, R/W) Description 3 NegARC Negative ARC 0: Accepts packets the ARC recognized, but refuses all other packets. 1: Refuses packets the ARC recognized, but accepts all other packets. BroadAcc (Default: 0, R/W) Accepts all packets that have a broadcast address. GroupAcc (Default: 0, R/W) Accepts all packets that have a multicast group address. StationAcc (Default: 0, R/W) Accepts all packets that have a unicast station address. 2 1 0 BroadAcc GroupAcc StationAcc Broadcast Accept Group Accept Station Accept Figure 16.4.33 ARC Control Register Hardware resets initialize the ARC Control Register to 0x0000. Software resets do not change the register contents. • • • The ARC recognizes the three following Ethernet address types. Station addresses: The first byte is even such as in 00-00-00-00-00-00. Broadcast addresses: Defined as FF-FF-FF-FF-FF-FF. Multicast group address: The first byte is odd such as in 01-00-00-00-00-00. However, not FFFF-FF-FF-FF-FF. When the CompEn bit is set and the ARC’s Compare mode is validated, the recipient address of the reception packet is compared with the address stored in ARC memory. For information on the structure of ARC memory, see 16.3.8.6 Address Recognition Circuit (ARC) operation. When the CompEn bit is cleared, the ARC unconditionally halts address comparisons. When an Accept bit (StationAcc, GroupAcc, or BroadAcc) is set, packets the ARC refused are also accepted. To refuse all packets, clear all bits of the ARC Control Register. To put MAC in the Promiscuous mode and accept all normal packets, set the ARC to accept all three of the above address types. You can also put MAC in the Promiscuous mode by setting the Negative ARC bit and clearing the CompEn bit. When the ARC Compare mode is enabled, addresses for filtering reception messages are read from ARC memory. ARC memory has a 6-Byte structure for each entry. You can set it to Valid or Invalid for each entry as described in ARC Enable Register on page 86. 16-72 Chapter 16 Ethernet Controller 16.4.5.3 Transmission Control, Status Registers Transmission Control Register (Tx_Ctl) 31 Reserved : Type : Default 15 14 EnC omp 0x48 16 13 EnTx Par 12 EnLat eColl 11 EnEx Coll 10 EnLC arr 9 EnEx Defer 8 EnUn der 7 MII1 0 6 SdPa use 5 NoEx Def 4 FBac k 3 NoC RC 2 NoPa d 1 TxHal t 0 TxEn R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W : Type 0 : Default Bit(s) 31:15 14 13 12 Mnemonic EnComp EnTxPar EnLateColl Field Name Reserved Enable Complete Enable Transmission Parity Enable Late Collisions Enable Excessive Collisions Enable Lost Carrier EnComp (Default: 0, R/W) Description Issues an interrupt either when MAC transmits or destroys 1 packet. EnTxPar (Default: 0, R/W) Issues an interrupt when a parity error occurs in MAC Transmission FIFO. EnLateColl (Default: 0, R/W) Issues an interrupt if a collision occurs after more than 512-bit late time (64Byte) time passes. EnExColl (Default: 0, R/W) Issues an interrupt if collisions occur in the same packet 16 times. EnLCarr (Default: 0, R/W) Issues an interrupt if either Carrier Sense could be not detected or was lost while transmitting a packet. EnExDefer (Default: 0, R/W) Issues interrupts when MAC causes a MAX_DEFERRAL time delay. MAX_DEFERRAL = 0.24288 ms for 100 Mbps = 2.4288 ms for 10 Mbps 8 EnUnder Underline Enable EnUnder (Default: 0, R/W) Issues an interrupt when the MAC Transmission FIFO becomes empty during transmission. MII10 (Default: 0, R/W) Setting this bit to "1" enables SQE checking. 6 5 4 3 2 1 0 SdPause NoExDef FBack NoCRC NoPad TxHalt TxEn PAUSE Transmission No Excessive Deferrals Fast Back Off No Suppress No Padding Transmission Halt Request Transmission Enable SdPause (Default: 0, R/W) Transmits either the Pause command or another MAC control frame. NoExDef (Default: 0, R/W) Suppresses excessive deferral checking. Fback (Default: 0, R/W) Uses a fast back-off timer during testing. NoCRC (Default: 0, R/W) Does not add CRC to the end of a packet. NoPad (Default: 0, R/W) Does not generate Pad Bytes even for packets with less than 64 Bytes. TxHalt (Default: 0, R/W) Halts transmission if the current packet ends regardless of the packet type. TxEn (Default: 0, R/W) Immediately halts transmission when cleared to "0". 11 10 EnExColl EnLCarr 9 EnExDefer Enable Excessive Defer 7 MII10 MII 10 Mbps Mode Figure 16.4.34 Transmission Control Register 16-73 Chapter 16 Ethernet Controller A hardware reset initializes the Transmission Control register to 0000h. A software reset clears the TxEn and SdPause bits, but does not affect the other bits. Do not set the FBack (Fast Back-off) bit to "1" when in the normal operation mode. The SdPause (Pause Transmission) bit is automatically cleared when transmission of the MAC control frame ends. Any writing of "0" to this bit is ignored. To issue an interrupt for each packet, set the EnComp bit or all MAC Error Enable bits. You can also set interrupts to occur when a specific state occurs. 16-74 Chapter 16 Ethernet Controller Transmission Status Register (Tx_Stat) 31 Reserved 0x4C 23 22 21 TxPAUSE 20 TxMACC 19 TxVLAN 18 TxBCast 17 TxMCast 16 SQErr R 0 15 TxHalted R 0 4 ExColl R 0 3 R 0 R 0 R 0 0 : Type : Default 14 Comp 13 TxPar 12 LateColl 11 Reserved 10 LCarr 9 ExDefer 8 Under 7 IntTx 6 Paused 5 TxDefer TxColl R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 : Type : Default Bit(s) 31:22 21 20 19 18 17 16 Mneminc TxPAUSE TxMACC TxVLAN TxBCast TxMCast SQErr Field Name Reserved Pause Packet Communication MAC Control Packet Transmission VLAN Tag Packet Transmission Broadcast Transmission Multicast Transmission Signal Quality Error TxPAUSE (Default: 0, R) Description This bit is set when MAC transmits a MAC control Pause packet. TxMACC (Default: 0, R) This bit is set when MAC transmits a MAC control packet. TxVLAN (Default: 0, R) This bit is set when MAC transmits a VLAN tag packet. TxBCast (Default: 0, R) This bit is set when MAC transmits a broadcast packet. TxMCast (Default: 0, R) This bit is set when MAC transmits a multicast packet. SQErr (Default: 0, R) Indicates that the Heartbeat signal could not be monitored at the end of a transmission. TxHalted (Default: 0, R) Halts transmission by either clearing the TxEn bit of the Transmission Control Register or setting the HaltImm bit of the MAC Control Register. Comp (Default: 0, R) Indicates that MAC either transmitted or destroyed one packet. TxPar (Default: 0, R) Indicates that a parity error was detected in MAC Transmission FIFO. LateColl (Default: 0, R) Indicates that 512-bit late time (64-Byte time) or more elapsed before a collision occurred. LCarr (Default: 0, R) Indicates that, during transmission, either Carrier Sense could not be detected or it was lost. ExDefer (Default: 0, R) Indicates that MAC deferred transmission for more than MAX_DEFERRAL. Under (Default: 0 ,R) Indicates that MAC Transmission FIFO became empty during transmission. 15 TxHalted Transmission Halted 14 13 12 Comp TxPar LateColl Complete Transmission Parity Error Late Collision 11 10 LCarr Reserved Lost Carrier 9 8 ExDefer Under Excessive Deferral Underrun Figure 16.4.35 Transmission Status Register (1/2) 16-75 Chapter 16 Ethernet Controller Bit(s) 7 Mnemonic IntTx Field Name Transmission Interrupt Transmitter Paused Transmission Deferred Excessive Collisions Description IntTx (Default: 0, R) This bit is set when interrupt conditions specified by the Transmission Control Register are met in a packet transmission. Paused (Default: 0, R) This bit is set if transmission is paused after the current packet ends. TxDefer (Default: 0, R) Indicates that a packet was kept waiting due to transmission delay. ExColl (Default: 0, R) This bit is set if collisions occur 16 times in the same packet. Instead of transmitting that packet, processing of the next packet transmission starts. TxColl (Default: 0, R) Number of collisions that occurred when transmitting one packet. 6 5 4 Paused TxDefer ExColl 3:0 TxColl Transmission Collision Count Figure 16.4.35 Transmission Status Register (2/2) Software resets initialize the Transmission Status Register to 0x00_0000. Also, this register is cleared at the beginning of each transmission packet. The Transmission Status flag is set each time the applicable event occurs. Also, an interrupt occurs if the corresponding bit of the Transmission Control Register is set. The lower 5 bits of the Transmission Status Register indicate the collision count of the packet. In other words, when ExColl=1, TxColl becomes 0. If TxColl is not 0, then ExColl=0. The MAX_DEFERRAL time is 0.24288 ms for 100 Mbps and 2.42880 ms for 10 Mbps. If the TxMCast bit (bit 17) and the TxBCast bit (bit 18) are both "0", they indicate that a unicast packet was transmitted. 16-76 Chapter 16 Ethernet Controller 16.4.5.4 Reception Control, Status Register Reception Control Register (Rx_Ctl) 31 Reserved : Type : Default 15 Reserved 0x50 16 14 EnGood 13 EnRxPar 12 EnLenErr 11 EnLong Err 10 EnOver 9 EnCRC Err 8 EnAlign 7 IgnoreLen 6 Ignore CRC 5 PassCtl 4 Strip CRC 3 ShortEn 2 LongEn 1 RxHalt 0 RxEn R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W : Type 0 : Default Bit(s) 31:15 14 13 12 11 Mnemonic EnGood EnRxPar EnLenErr EnLongErr Field Name Reserved Transmission Enable Enable Reception Parity Enable Frame Length Errors Enable Long Errors EnGood (Default: 0, R/W) Description Issues an interrupt if a packet is received without any error. EnRxPar (Default: 0, R/W) Issues an interrupt if a parity error is detected in the MAC Reception FIFO. EnLenErr(Default: 0, R/W) Issues an interrupt if a Frame Length error is detected. EnLongErr (Default: 0, R/W) If the LongEn bit is not set, an interrupt is issued when a frame longer than 1518 Bytes (1522 Bytes for VLAN) is received. EnOver (Default: 0, R/W) Issues an interrupt if the MAC Reception FIFO becomes full when receiving a packet. EnCRCErr (Default: 0, R/W) Issues an interrupt either when CRC receives an invalid packet or PHY asserts Rx_er while receiving a packet. EnAlign (Default: 0, R/W) Issues an interrupt if CRC receives an invalid packet with a length that is not a multiple of 8. IgnoreLen (Default: 0, R/W) Does not check the frame length. 6 5 4 3 IgnoreCRC PassCtl StripCRC ShortEn Ignore CRC Value Pass MAC Control Frame Strip CRC Value Enable Short IgnoreCRC (Default: 0, R/W) Does not check CRC. PassCtl (Default: 0, R/W) Passes a received MAC control frame to the system. StripCRC (Default: 0, R/W) Checks CRC, but removes it from the message. ShortEn (Default: 0, R/W) Enables the reception of frames shorter than 64 Bytes.1 10 EnOver Enable Overflows 9 EnCRCErr Enable CRC Errors 8 EnAlign Enable Alignment 7 IgnoreLen Ignore Frame Length Figure 16.4.36 Reception Control Register (1/2) 1 The above frame length does not include a preamble and a Start Frame Delimiter (SFD). For details, see 16.3.8.1 Format of MAC frames and packets. 16-77 Chapter 16 Ethernet Controller Bit(s) 2 Mnemonic LongEn Field Name Long Enable Reception Halt Request Description LongEn (Default: 0, R/W) Enables the reception of frames longer than 1518 Bytes (1522 Bytes in the case of VLAN).1 RxHalt (Default: 0, R/W) Halts reception after the current packet ends regardless of the packet type. RxEn (Default: 0, R/W) This bit halts reception when cleared to "0". If this bit is cleared after MAC starts processing the recipient address, reception operation for the current packet continues and data is transferred to the system memory. At this time, the TxHalted bit of the Reception Status Register is set and indicates that the system issued a Reception Halt Request while receiving a packet. If this bit is cleared before processing of the recipient address starts, reception operation immediately halts. At this time, the RxHalted bit is set. 1 RxHalt 0 RxEn Reception Enable Figure 16.4.36 Reception Control Register (2/2) Hardware resets initialize the Reception Control Register to 0x0000. Software resets clear the RxEn bit, but no other bits are changed. To issue an interrupt for each packet, set the EnGood bit or all Error Enable bits. You can also set the Reception Control Register to only issue interrupts when a particular state occurs. 1 The above frame length does not include a preamble and a Start Frame Delimiter (SFD). For details, see 16.3.8.1 Format of MAC frames and packets. 16-78 Chapter 16 Ethernet Controller Reception Status Register (Rx_Stat) 31 30 29 ARCEnt R 0x1f 15 RxHalted 0x54 24 ARCStatus R 0x0 21 20 RxPause 25 19 RxVLAN 18 RxBCast 17 RxMCast 16 Reserved Reserved R 0 6 5 CtlRecd R 0 3 R 0 R 0 R 0 0 : Type : Default 14 13 12 TypePkt 11 LongErr 10 Overflow 9 CRCErr 8 AlignErr 7 Reserved 4 InLenErr Good RxPar R 0 R 0 IntRx Reserved : Type : Default R 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit(s) 31:30 29:25 Mnemonic ARCEnt Field Name Reserved ARC Entry Description ARCEnt (Default: 0x1F, R) This field stores the ARC entry index if the address matches. If the address does not match, all bits become "1". ARCStatus (Default: 0, R) Denotes ARC operation (see the following encoding). RxPause (Default: 0, R) This bit is set when the reception packet is a MAC control PAUSE packet. RxVLAN (Default: 0, R) This bit is set when the reception packet is a VLAN tagged packet. RxBCast (Default: 0, R) This bit is set when the reception packet is a broadcast packet. RxMCast (Default: 0, R) This bit is set when the reception packet is a multicast packet. 24:21 20 19 18 17 16 15 ARCStatus RxPause RxVLAN RxBCast RxMCast ARC Status PAUSE Packet Reception VLAN Tagged Packet Reception Broadcast Reception Multicast Reception Reserved RxHalted Reception Halted RxHalted (Default: 1, R) This bit indicates that reception was halted either when the RxEn bit of the Reception Control Register was cleared or the HaltImm bit of the MAC Control Register was set. Good (Default: 0, R) Indicates that a packet was received without any errors occurring. RxPar (Default: 0, R) Indicates that a parity error was detected in the MAC Reception FIFO. TypePkt (Default: 0, R) The value of the Frame Length field is greater than 1500 (no frame length check is performed). The software can use this bit to check the Protocol Type field. LongErr (Default: 0, R) Indicates that a frame longer than 1518 Bytes (1522 Bytes for VLAN)1 was received. However, if the LongEn bit of the Reception Control Register is set, this bit is not set. Overflow (Default: 0, R) Indicates that the MAC Reception FIFO is full and a reception byte is missing. CRCErr (Default: 0, R) Indicates that either the CRC value at the end of the packet does not match the calculated value or PHY asserted Rx_er while receiving a packet. 14 13 12 Good RxPar TypePkt Normal Reception Reception Parity Error Type Packet 11 LongErr Long Error 10 9 Overflow CRCErr Overflow CRC Error Figure 16.4.37 Reception Status Register (1/2) 1 The above frame length does not include a preamble and a Start Frame Delimiter (SFD). For details, see 16.3.8.1 Format of MAC frames and packets. 16-79 Chapter 16 Ethernet Controller Bit(s) 8 7 6 Mnemonic AlignErr Field Name Alignment Error Reserved AlignErr (Default: 0, R) Description Indicates that the frame length is not an 8-bit multiple and that CRC is invalid. IntRx Reception Interrupt IntRx (Default: 0, R) This bit is set when interrupt conditions are met due to the reception of a packet. If the EnGood bit of the Reception Control Register is set, notification is also sent for packets received without any errors. Note: If the Address Recognition Circuit (ARC) destroys a received packet when the EnGood bit or EnCRCErr bit of the Reception Control Register is set, this IntRx bit is also set if the Good or CRCErr bit of the Reception Status Register is set. In this case however, no interrupt notification is sent and the IntMacRx bit of the Int_Src Register is not set. 5 CtlRecd Control Frame Received In Range Frame Length Error CtlRecd (Default: 0, R) This bit is set if the ARC recognizes an address when the received packet is the MAC control frame (type=0x8808). InLenErr (Default: 0, R) If the value of the Frame Length field is 46 or less, this bit is set when the reception packet size is not 64 Bytes. Also, if the value of the Frame Length field is between 47 and 1500, this bit is set when the reception packet size is not the value of the Frame Length field + 18 (14 when in the Strip CRC mode). 4 InLenErr 3:0 Reserved Figure 16.4.37 Reception Status Register (2/2) Software resets initialize the Reception Status Register to 0x3E00_8000. This register is also cleared at the beginning of each reception packet. The Reception Status flag is set each time the applicable event occurs. Once the Reception Status flag is set, it remains set until the next packet is reached. When the corresponding bit of the Reception Control Register is set, an interrupt is issued. The CtlRecd bit is set when the packet type is 0x8808 and the ARC recognizes an address. If both the RxMCast bit (bit 17) and the RxBCast bit (bit 18) are "0", they indicate that a unicast packet was received. The ARCStatus field is encoded as follows below. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1xx1: 1010: Toss. MAC control frame received. PassCtl=0. Toss. The packet length is less than the minimum packet length, but is 6 Bytes or more. Keep if that is not the case. Toss. Matches ARC. NOT filtering. Reserved Toss. External CAM bit. NOT filtering. Reserved Toss. Address does filtering. not match. No external CAM. Compare disable. AND Toss. State in which the packet length is too short, the ARC result is Invalid, and the ShortEn bit is not set. Keep. Broadcast, multicast, or unicast accepting is enabled and the address matches. Reserved Keep. ARC matches. AND filtering. 16-80 Chapter 16 Ethernet Controller 1100: 1110: Keep. External CAM bit. AND filtering. Keep. ARC does not match. AND filtering. Note: The minimum packet length is 64 Bytes if ShortEn is not asserted, or is 14 Bytes if ShortEn is asserted. Racing occurs between the internal ARC and external CAM. There are cases where the first signal to notify a hit blocks the other signal that notifies a hit and the ARC's Entry Status bit changes. 16-81 Chapter 16 Ethernet Controller 16.4.5.5 Station Management Registers Station Management Data Register (MD_Data) 31 30 29 28 27 26 25 24 23 Reserved 22 0x58 21 20 19 18 17 16 : Type : Default 15 Station Management Data R/W 0x0000 : Type : Default 0 Bits 31:16 15:0 Mnemonic Field Name Reserved Station Management Data Description (Default: 0x0000, R/W ) The MII item of the IEEE802.3 specification that relates the 100Base-T or 100 Mbps Ethernet defines the format of the Stage Management Data Register. For information on other hardware-dependent registers, see the separate PHY data sheet. Figure 16.4.38 Station Management Data Register Software resets initialize the Station Management Data Register to 0x0000. 16-82 Chapter 16 Ethernet Controller Station Management Control, Address Register (MD_CA) 31 30 29 28 27 26 25 24 23 22 21 0x5C 20 19 18 17 16 Reserved : Type : Default 15 13 Reserved 12 11 Busy R/W 0 10 Wr R/W 0 9 PHY R/W 0x00 5 4 Addr R/W 0x00 : Type : Default 0 Bit(s) 31:12 11 Mnemonic Field Name Reserved Description Busy (Default: 0, R/W) This bit is set when operation starts. The Ethernet Controller clears this bit when the operation ends. Wr (Default: 0, R/W) This bit is set to "1" during writes and is cleared to "0" during reads. PHY (Default: 0, R/W) Address of all PHY to be read or written Addr (Default: 0, R/W) Address of PHY-internal register to be read or written. Busy Busy Bit 10 9:5 4:0 Wr PHY Addr Write PHY Address Address Figure 16.4.39 Station Management Control Address Register Before accessing the PHY Control Register, use the software to check the Busy bit of the Station Management Control, Address Register and confirm that it is not set. The Ethernet Controller supports reading or writing of Station Management data to PHY. The setting of the Station Management Control, Address Register does not affect the operation of the Ethernet Controller. 16-83 Chapter 16 Ethernet Controller 16.4.5.6 Address Recognition Circuit (ARC) Access Register ARC Address Register (ARC_Adr) 31 30 29 28 27 26 25 24 0x60 23 22 21 20 19 18 17 16 Reserved : Type : Default 15 14 Reserved 12 11 ARC_Loc R/W 0x000 2 1 0 Reserved : Type : Default Bits 31:12 11:2 1:0 Mnemonic ARC_Loc Field Name Reserved ARC Address Reserved ARC_Loc (Default: 0x00, R/W) ARC address: 4 bytes Description Figure 16.4.40 ARC Address Register Software resets initialize the ARC Address Register to 0x0000. During normal operation, the ARC Address Register and ARC Data Register can perform read or write operation to all ARC areas including two double-word positions immediately after flow control ARC. (See Figure 16.3.12.) During normal operation, writes to all other memory positions are invalid. When the TestMode bit of the DMA Control Register is set, you can use the ARC Address Register and perform read or write operation on all RAM areas in the DMA Block. 16-84 Chapter 16 Ethernet Controller ARC Data Register (ARC_Data) 0x64 31 ARC_Data[0] R/W 15 ARC_Data[2] R/W 8 7 ARC_Data[3] R/W : Type : Default 24 23 ARC_Data[1] R/W 0 : Type : Default 16 Bits 31:24 Mnemonic ARC_Data[0] Field Name ARC Data Register [0] Description ARC_Data[0] (Default -, R/W) 4-Byte data of ARC memory is accessed each time the ARC Data Register is read or written to. ARC_Data[1] (Default -, R/W) 4-Byte data of ARC memory is accessed each time the ARC Data Register is read or written to. ARC_Data[2] (Default: -, R/W) 4-Byte data of ARC memory is accessed each time the ARC Data Register is read or written to. 23:16 ARC_Data[1] ARC Data Register [1] 15:8 ARC_Data[2] ARC Data Register [2] 7:0 ARC_Data[3] ARC Data Register [3] ARC_Data[3] (Default: -, R/W) 4-Byte data of ARC memory is accessed each time the ARC Data Register is read or written to. Figure 16.4.41 ARC Data Register 4-Byte data of ARC memory is accessed each time the ARC Data Register is read or written to. In other words, the PCI Byte Enable signal is ignored. When changing only 2 Bytes of a 4-Byte word, the system software must perform a Read/Modify/Write. The ARC Data Register stores copies of data in ARC at the address specified by the ARC Address Register. You can read the content of the ARC Data Register as many times as you require. Writing data to this register changes the selected ARC data. Note: In contrast to transmission/reception data in the Master mode, data transferred via the ARC Interface is interpreted in Big Endian. 16-85 Chapter 16 Ethernet Controller ARC Enable Register (ARC _Ena) 31 Reserved 0x68 21 20 ARC_Ena R/W 0x00 : Type : Default 0 ARC_Ena R/W 0x0000 : Type : Default 16 15 Bits 31:21 20: 0 Mnemonic ARC_Ena Field Name Reserved ARC Enable Description ARC_Ena (Default: 0x0_0000, R/W) Sets the bits corresponding to an entry valid as address filtering. Figure 16.4.42 ARC Enable Register Hardware resets initialize the ARC Enable Register to 0x00_0000. Software resets do not change the contents of this register. This register indicates which entry to validate as address filtering. This register can validate up to 21 entries numbered from 0 to 20. 16-86 Chapter 16 Ethernet Controller 16.4.5.7 Missed Error Count Register (Miss_Cnt) 31 Reserved : Type : Default 15 Miss_Cnt R/W 0x0000 : Type : Default 0 0x7C 16 Bits 31:16 15:0 Mnemonic Miss_Cnt Field Name Reserved Missed Error Count Description Miss_Cnt (Default: 0x0000, R/W) This register counts the number of valid packets MAC refused due to MAC Reception FIFO overflow, parity error, or the clearing of the Reception Enable bit (RxEn). This count does not include the packets refused by ARC. Figure 16.4.43 Missed Error Count Register Hardware resets initialize the Missed Error Count Register to 0x0000_0000. Software resets do not change the contents of this register. The Missed Error Count Register displays the number of packets destroyed by various error types. This register provides the information required for station management along with the status information of the transmission/reception packet. Performing read access to the Missed Error Count Register clears it. Therefore, the software is responsible for increasing the bit count and retaining the precise total error count. The MissRoll bit of the MAC Control Register is set when the Missed Error Count Register rolls over from 0x7FFF to 0x8000. Also, in this case an interrupt occurs if the EnMissRoll bit is set. To generate interrupts more frequently from the Station Management software, you can set the Missed Error Count Register to a value that is close to the final count value of 0x7FFF. For example, if you set this register to 0x7F00, an interrupt occurs when errors have occurred 256 times. 0x74 through 0x78 is reserved to maintain compatibility with previous Toshiba products. 16-87 Chapter 16 Ethernet Controller 16-88 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17. SPI (Serial Peripheral Interface) Module (SPI) 17.1 Characteristics The SPI is a serial interface that consists of clock, data output, and data input. The SPI is used to interface with serial power, serial A/D converters, other devices including simple serial clocks and data interfaces. The TX4938 only operates as a Master. It generates SPI clocks to Slaves. Multi-slave devices can share the SPI by using a unique Chip Select for each Slave device. Chip Select uses one general-purpose I/O port of the TX4938, or can generate other output ports that the system can use. If the Chip Select of a device is asserted and the device is selected, that device uses the SPICLK and SPIOUT signals to shift data in, and then uses the SPIIN signal to shift data out. If the device is not selected, the data output connected to SPIIN must be put into the tri-state and other devices must be able to share the SPIIN signal. The SPI module contains registers that can program the SPI CLK rate, MSB first or LSB first, clock polarity, data phase polarity, and Byte mode or Word mode operation. The SPI module has the following characteristics: • • • • • • Selectable clock phase and polarity Transfer Size: 8-bit or 16-bit 4-frame Transmitter Buffer and 4-frame Receiver Buffer Master Operation Interframe Delay Time Counter MSB/LSB First 17-1 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.2 Block diagram The SPI Module mainly consists of a 16-bit SPI Data Register (SPDR), a 16-bit Transmitter Buffer, a 16bit Receiver Buffer, a 16-bit Shift Register, a Baud Rate Generator, an Interframe Delay Time counter, and interrupt logic. Figure 17.2.1 is a block diagram of the SPI Module. IM-Bus Bus I/F Baud Rate Generator Interframe Delay Time Counter Interrupt Logic SPDR Read Write Receiver Buffer (FIFO) Transmitter Buffer (FIFO) Shift Register SPIIN SPICLK SPIOUT Figure 17.2.1 SPI Block Diagram 17-2 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.3 Operational description 17.3.1 Operation modes The SPI Module has the two following operation modes: • Configuration Mode (OPMODE = “01”): You can only rewrite the lower byte (bits[7:0]) of SPI Control Register 0 (SPCR0) and all bits of SPI Control Register 1 (SPCR1) when in this mode. Also, the SPSTP bit, Receiver FIFO and Transmitter FIFO are cleared and the SPI Module is reset when in this mode. Setting this mode forcibly terminates even the transfer of a frame that is currently in progress. • Active Mode (OPMODE = “10”) The module operates in this mode during normal operation. You can execute transfers when in this mode. 17.3.2 Transmitter/Receiver The SPI Module is in the Reset state when it is in the Configuration Mode. When in this mode, set the lower byte (bits[7:0]) of SPI Control Register 0 (SPCR0) and SPI Control Register 1 (SPCR1) to the desired value before changing the operation mode to the Active Mode. The SPI Module can start transferring data once it is in the Active Mode. Transfer starts when data is written to the SPI Data Register (SPDR). The data written to the SPI Data Register (SPDR) is sent to the Shift Register, which then outputs the data to the Slave device. When the data is outputted from the SPIOUT pin, it is simultaneously fetched from the SPIIN pin. When fetching of the data is complete, the content of the Shift Register is loaded into the Receiver Buffer, the SRRDY bit of the SPI Status Register (SPSR) becomes “1”, then the Reception Buffer is notified that there is reception data. When the RBSI bit of the SPI Status Register (SPSR) is set to “1”, an interrupt occurs when the accumulated reception data reaches the level set by the RXIFL bit of SPI Control Register 0 (SPCR0). When the content of the Transmitter Buffer is transferred to the Shift Register, the STRDY bit of the SPI Status Register (SPSR) becomes “1” and notification is sent that the Transmitter Buffer is available for use again. If the TBSI bit in the SPI Status Register (SPSR) is set to “1”, an interrupt is generated when the Transmitter Buffer has 1 to 4 locations emptied, as programmed in the TXIFL field in SPI Control Register 0 (SPCR0). Therefore, the software executes the following steps each time it writes data to the Transmitter Buffer. (1) Check whether the STRDY bit or the TBSI bit is “1”. If neither bit is “1”, wait until one of them becomes “1”. (2) Write data to the SPI Data Register (SPDR). In this way, depending on the software used, the SPI Module can continue to seamlessly transmit data as long as the Transmitter Buffer is in the Run state until the data is shifted out from the Shift Register. If the software cannot keep up with the transfer rate, the SPI Module waits until the next data is written to the SPI Data Register (SPDR). 17-3 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) When one series of transmission is complete, the software deasserts the Chip Select signal of the Target device according to the following procedure. (1) Check whether the SRRDY bit or the RBSI bit is “1”. If neither bit is “1”, wait until one of them is asserted. (2) Check whether SIDLE is “1”. If it is not “1”, wait until it is asserted. (3) Deassert the Chip Select signal. The SPI Module supports either 8-bit or 16-bit per character operation as defined by the SSZ bit of SPI Control Register 1 (SPCR1). Also, the software can use the SBOS bit of SPI Control Register 0 (SPCR0) to select whether to shift MSB or LSB first. The other combination of control bits (SPHA and SPOL) determines the transfer format. See 17.3.4 for the transfer format. 17.3.3 Baud Rate Generator The SPI Module operates IMBUSCLK as the Master Clock (SPI Master Clock). This module divides IMBUSCLK to generate (using the Baud Rate Generator) the SPICLK used for SPI transmission/reception. You can set this divide rate and can change the SPICLK to any frequency. Use SER[7:0] of SPI Control Register 1 (SPCR1) to set the divide rate. The following table shows the divide rate (SER[7:0]) and SPICLK frequency for when IMBUSCLK is 66 MHz or 60 MHz. Table 17.3.1 SPICLK Frequency SPI Clock Rate SER[7:0] 00000001b 00000010b 00000011b 00000100b 00000101b … 00001001b … 00010011b … 11111111b 128.91 KHz 117.19 KHz 1.65 MHz 1.5 MHz 3.3 MHz 3 MHz SPI Clock Rate (IMBUSCLK: 60 MHz) (TMPR4938XBG-300) 15 MHz 10 MHz 7.5 MHz 6 MHz 5 MHz (IMBUSCLK: 66MHz) (TMPR4938XBG-333) 16.5 MHz 11 MHz 8.25 MHz 6.6 MHz 5.5 MHz 17-4 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.3.4 Transfer format During SPI transfer, serial data transmission (shift out) and reception (shift in) is executed simultaneously. At this time, serial data is shifted or sampled synchronous to the serial clock. The SPHA bit and SPOL bit of SPI Control Register 0 (SPCR0) determine the transfer format. The setting of the SPHA bit broadly classifies the protocol that is used. Each protocol is described below in items 17.3.4.1 and 17.3.4.2. 17.3.4.1 SPHA =0 format Figure 17.3.1 shows the transfer format when SPHA is “0”. idle 1 2 3 4 5 6 7 8 idle SPICLK (SPOL=0) SPICLK (SPOL=1) SPIIN MSB B6 B5 B4 B3 B2 B1 LSB SPIOUT MSB B6 B5 B4 B3 B2 B1 LSB Sample point Figure 17.3.1 Transfer Format when SPHA is “0” When in this format, data is sequentially fetched from the first clock edge after the Idle state. When the SPOL bit is “0”, data is fetched at the rising edge. When this bit is “1”, data is fetched at the falling edge. The SPIIN or SPIOUT signal is switched at the second clock edge of SPICLK. The signal is switched at the SPICLK falling edge when the SPOL bit is “0”, or is switched at the SPICLK rising edge when the SPOL bit is “1”. When the SPOL bit is “0”, SPICLK is at the Low level during the Idle state. When the SPOL bit is “1”, SPICLK is at the High level during the Idle state. 17-5 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.3.4.2 SPHA = 1 format Figure 17.3.2 shows the transfer format when SPHA is “1”. idle 1 2 3 4 5 6 7 8 idle SPICLK (SPOL=0) SPICLK (SPOL=1) SPIIN MSB B6 B5 B4 B3 B2 B1 LSB SPIOUT MSB B6 B5 B4 B3 B2 B1 LSB Sample point Figure 17.3.2 Transfer Format when SPHA is “1” When in this format, data is sequentially fetched from the second clock edge after the Idle state. When the SPOL bit is “0”, the data is fetched from the second falling edge. When the SPOL bit is “1”, the data is fetched from the second rising edge. When the SPOL bit is “0”, SPICLK is at the Low level during the Idle state. When the SPOL bit is “1”, SPICLK is at the High level during the Idle state. 17.3.5 Interframe Delay Time Counter There are cases where it is preferable to shorten the time between data groups. In such cases, the Interframe Delay Time Counter is used to specify the delay time between data groups. When 16 bits is selected as the data size by SPI Control Register 1, the delay time is inserted after 16-bit data is shifted. When 8 bits is selected, the delay time is inserted after 8-bit data is shifted. When IFS bits [9:0] are set to a value other than “0”, a delay is inserted between the characters. The length of the delay inserted between characters is also changed by the IFSPSE bit of SPI Control Register 0 (SPCR0) as shown below. When SPCR0.IFSPSE=1: SPI Master Clock Cycle × IFS[9:0] × 32 When SPCR0.IFSPSE=0: SPI Master Clock Cycle × IFS[9:0] If the IFS value is “0”, seamless operation is performed. The SPI Module continues to shift data and supply a clock as long as the software does not fall behind the transfer rate of the transmitter. 17-6 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.3.6 Buffer configuration The SPI Module has a Transmitter Buffer and a Receiver Buffer. The buffers use FIFOs to store data. Each FIFO can store 4-frame data. The Transmitter Buffer stores the value written to the SPI Data Register. Either when in the Idle state or when the current transmission is complete, the first data written to the Transmitter Buffer is transferred to the Shift Register. On the other hand, data received in the Shift Register is stored in the Receiver Buffer each time transfer ends. You can issue interrupts each time data equal in size to the data in the buffer accumulates. 17.3.7 SPI system errors The SPI Module signals the following system errors during transfer. 17.3.7.1 Overrun error (SPOE) An overrun error is issued when an attempt is made to write the next data to the Transmitter Buffer regardless of whether the Transmitter Buffer is full. The data to be newly written at this time is not written to the Transmitter Buffer. Also, the SPOE bit of the SPSR Register becomes “1”. 17.3.8 Interrupts The SPI Module has three types of interrupt sources. The result of OR operation performed on three interrupt sources is inputted to the Interrupt Controller (IRC) as SPI interrupts. Check the SPI Status Register (SPSR) to see which interrupts occurred. Type System error or idle Receive Buffer Fill Transmit Buffer Fill RBSI TBSI Status bits SPOE, SIDLE RBSIE TBSIE Mask-able bit SOEIE, SILIE Use System errors or Idle interrupts for error detection or Idle state interrupts. Use Receiver Buffer Fill interrupts and Transmitter Buffer Fill interrupts when setting new transmission data to the buffer or when reading receiver data from the buffer. 17-7 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.4 Registers Access SPI Module registers using 32-bit access. Operation is not guaranteed when accessing these registers using any other access size. Do not write “0” to any undefined bits. Table 17.4.1 SPI Module Registers Offset Address 0xF800 0xF804 0xF808 0xF80C 0xF810 0xF814 0xF818 0xF81C Bit Width 32 32 32 32 32 32 32 32 Register Symbol SPMCR SPCR0 SPCR1 SPFS ⎯ SPSR SPDR ⎯ Register Name SPI Master Control Register SPI Control Register 0 SPI Control Register 1 SPI Interframe Delay Time Register (Reserved) SPI Status Register SPI Data Register (Reserved) 17.4.1 31 SPI Master Control Register (SPMCR) 0xF800 16 0 : Type : Default 15 0 8 7 6 OPMODE R/W 0 R/W 1 5 0 3 2 ⎯ R/W 0 1 0 SPSTP BCLR R/W 0 R/W1C : Type 0 : Default Bit(s) 31:8 7:6 Mnemonic ⎯ OPMODE Field Name Reserved Operation Mode Operation Mode (Default: 00) Sets the operation mode. 00: Don’t care. 01: Configuration Mode 10: Active Mode 11: Reserved Description ⎯ 5:3 2 1 ⎯ ⎯ SPSTP Reserved Reserved SPI Stop Do not write “1” to this bit. ⎯ SPI Stop (Default: 0) When “1” is written to this bit, the SPI Module does not transfer any more data after the current frame is complete. You can only set this bit when in the Active Mode. Entering the Configuration Mode clears this bit. 0: Normal operation 1: Halt after the current transfer ends. SPI Buffer Clear (Default: 0) Use this bit to clear the Transmitter FIFO and Receiver FIFO. Writing “1” to this bit initializes the FIFO. Write “1” to this bit after the SPI Module enters the Idle state (SIDLE=1). Always outputs “0” when read. Write: 0: Don’t care 1:Clear the FIFO 0 BCLR SPI Buffer Clear Figure 17.4.1 SPI Master Control Register (SPMCR) 17-8 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.4.2 31 0 : Type : Default 15 14 TXIFL R/W 0 13 12 RXIFL R/W 0 11 10 9 8 SILIE SOEIE RBSIE TBSIE R/W 0 R/W 0 R/W 0 R/W 0 7 0 6 0 5 0 4 IFSPSE SPI Control Register 0 (SPCR0) 0xF804 16 3 1 2 1 0 SBOS SPHA SPOL R/W 0 R/W 0 R/W : Type 0 : Default R/W 0 Bit(s) 31:16 15:14 Mnemonic ⎯ TXIFL Field Name Reserved Transmit Interrupt Fill Level Description ⎯ Transmit Interrupt Fill Level (Default: 00) You can issue interrupts according to the number of free data in the Transmitter FIFO. This field sets the free data count of the Transmitter FIFO at which interrupts are issued. 00: Issue an interrupt when there is 1 or more free data in the Transmitter FIFO. 01: Issue an interrupt when there are 2 or more free data in the Transmitter FIFO. 10: Issue an interrupt when there are 3 or more free data in the Transmitter FIFO. 11: Issue an interrupt when there are 4 free data in the Transmitter FIFO. Receive Interrupt Fill Level (Default: 00) You can issue interrupts according to the number of data in the Receiver FIFO. This field sets the number of Receiver FIFO data at which to issue an interrupt. 00: Issue an interrupt when there is 1 or more free data in the Receiver FIFO. 01: Issue an interrupt when there are 2 or more free data in the Receiver FIFO. 10: Issue an interrupt when there are 3 or more free data in the Receiver FIFO. 11: Issue an interrupt when there are 4 free data in the Receiver FIFO. SPI IDLE Interrupt Enable (Default: 0) Enables SPI Idle interrupts. 0: Disable 1: Enable SPI IDLE Overrun Enable (Default: 0) Enables SPI Overrun interrupts. 0: Disable 1: Enable Receive Buffer Fill Interrupt Enable (Default: 0) This bit specifies whether to signal an interrupt to the Interrupt Controller based on the number of data actually in the Receiver FIFO or to only display it as a status. 0: Disable (mask) 1: Enable Transmit Buffer Fill Interrupt Enable (Default: 0) This bit specifies whether to signal an interrupt to the Interrupt Controller based on the number of free data actually in the Transmitter FIFO or to only display it as a status. 0: Disable (mask) 1: Enable ⎯ 13:12 RXIFL Receive Interrupt Fill Level 11 SILIE SPI IDLE Interrupt Enable 10 SOEIE SPI Overrun Interrupt Enable 9 RBSIE Receive Buffer Fill Interrupt Enable 8 TBSIE Transmit Buffer Fill Interrupt Enable 7:5 ⎯ Reserved Figure 17.4.2 SPI Control Register 0 (SPCR0) (1/2) 17-9 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) Bit(s) 4 Mnemonic IFSPSE Field Name Inter Frame Space prescaler enable Reserved SPI Bit Order Select Description Inter Frame Space prescaler Enable (Default: 0) Enables prescaler of the Interframe Delay Time Counter. 0: Disable (× 1) 1: Enable (× 32) ⎯ SPI Bit Order Select (Default: 0) This bit specifies the bit order of the transfer data. 0: LSB first (transfer starting from the least significant bit) 1: MSB first (transfer starting from the most significant bit) SPI Clock Phase (Default: 0) Selects the clock phase. 0: Samples at the first clock edge, then shifts at the second edge. 1: Shifts at the first clock edge, then samples at the second edge. SPI Clock Polarity (Default: 0) Selects the SPICLK polarity. 0: High Active (SPICLK is Low when idle) 1: Low Active (SPICLK is High when idle) 3 2 ⎯ SBOS 1 SPHA SPI Phase 0 SPOL SPI Polarity Note 1: You can only write to bits 4, 2, 1, or 0 when the SPI Module is in the Configuration Mode. Note 2: The SPOL and SPHA bits select the SPICLK phase and the clock edge at which to sample data. For details, see 17.3.4 Transfer format. Note 3: The value of the SPOL bit must be changed, with the device's chip select signal deasserted. (For example, the chip select signal can be controlled, using a general-purpose port of the TX4938.) Figure 17.4.2 SPI Control Register 0 (SPCR0) (2/2) 17-10 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.4.3 31 0 : Type : Default 15 14 13 12 SER R/W 0x00 11 10 9 8 7 0 6 0 5 0 4 3 2 SSZ R/W 00000 1 0 SPI Control Register 1 (SPCR1) 0xF808 16 : Type : Default Bits 31:16 15:8 Mnemonic ⎯ SER Field Name Reserved SPI Data Rate Description ⎯ SPI Data Rate (Default: 000000b) This field sets the transfer bit rate. The transfer bit rate is calculated according to the following equation. fBR = fSPI/2 (n + 1) fBR : SPICLK Frequency fSPI : SPI Master Clock Frequency n : SER (Setting “0” is not permitted) (See 17.3.3 for SER and clock frequency examples.) 7:5 4:0 ⎯ SSZ Reserved SPI Transfer Size ⎯ SPI Transfer Size (Default: 00000b) Selects the transfer size. 0x08: 8 bits 0x10: 16 bits Other values: Reserved (not settings are permitted) Note 1: You can only write to this register when the SPI Module is in the Configuration Mode. Figure 17.4.3 SPI Control Register 1 (SPCR1) 17-11 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.4.4 31 0 : Type : Default 15 0 10 9 IFS R/W 0000000000 : Type : Default 0 SPI Interframe Delay Time Counter (SPFS) 0xF80C 16 Bits 31:10 9:0 Mnemonic ⎯ IFS Field Name Reserved Inter Frame Space Description ⎯ Inter Frame Space (Default: 0x00) This register sets the delay time to insert between two consecutive frames. When this register is set to "0", transfer ends, the next transmission data is loaded from the Transmitter FIFO to the Transmitter Buffer, and then the next transfer is performed. (Since the time data is loaded into the buffer is not "0", the delay time from the last clock until the first clock of the next transfer is not actually "0".) When setting the IFSPSE bit of the SPCR0 Register to "0" and not using prescaler, the Interframe delay time is the value calculated using the formula in 17.3.5. (16.7 ns - 17.05 µs when SPI Master Clock Frequency is 60 MHz) When setting the IFSPSE bit of the SPCR0 Register to "1" and using prescalar, the Interframe delay time is the value calculated using the formula in 17.3.5. (533 ns - 545.6 µs when SPI Master Clock Frequency is 60 MHz) Only write to this register when the SIDLE bit is "0". Figure 17.4.4 SPI Interframe Delay Time Counter (SPFS) 17-12 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) 17.4.5 31 0 : Type : Default 15 TBSI R 1 14 RBSI R 0 13 TBS R 000 11 10 RBS R 000 8 7 SPOE R/C 0 6 0 5 0 4 0 3 2 1 0 IFSD SIDLE STRDY SRRDY R 0 R 1 R 1 R 0 : Type : Default SPI Status Register (SPSR) 0xF814 16 Bit(s) 31:16 15 Mnemonic ⎯ TBSI Field Name Reserved Transmit Buffer Status Indicator Description ⎯ Transmit Buffer Status Indicator (Default: 1) Indicates the status of interrupts according to the number of free data in the Transmitter FIFO. 0: No interrupt 1: Interrupt Receive Buffer Status Indicator (Default: 0) Indicates the status of interrupts according to the number of free data in the Receiver FIFO. 0: No interrupts 1: Interrupts Transmit Buffer Status (Default: 000) Indicates how many data are in the Transmit FIFO. 000: No data 001: 1 010: 2 011: 3 100: 4 (FIFO is full) 101 – 111: NA Receive Buffer Status (Default: 000) Indicates how many data are in the Receiver FIFO. 000: No data 001: 1 010: 2 011: 3 100: 4 (FIFO is full) 101 – 111: NA SPI Overrun Error (Default: 0) Indicates that an overrun occurred in the Transmitter FIFO. You can clear this bit by writing "1" to it. You can also clear this flag by putting the SPI Module in the Configuration Mode. Read: 0: No errors 1: Generate overrun errors Write: 0: Don’t care 1: Clear ⎯ 14 RBSI Receive Buffer Status Indicator 13:11 TBS Transmit Buffer Status 10:8 RBS Receive Buffer Status 7 SPOE SPI Overrun Error 6:4 ⎯ Reserved Figure 17.4.5 SPI Status Register (SPSR) (1/2) 17-13 Chapter 17 SPI (Serial Peripheral Interface) Module (SPI) Bit(s) 3 Mnemonic IFSD Field Name SPI Inter Frame Space Delay Indicator Description SPI Inter Frame Space Delay Indicator (Default: 0) This bit becomes "1" when transfer of a frame ends and transfer of the next frame is deferred by the Interframe Delay Time Counter. 0: No interframe cycle 1: Interframe cycle SPI Idle Indicator (Default: 0) This bit becomes "1" either when the Transmitter FIFO is empty or the SPSTP bit is "1" and there is no transfer in progress. 0: Run 1: Idle SPI Transmit Ready (Default: 0) Indicates that there is space in the Transmitter FIFO. 0: Transmitter FIFO is full. 1: Transmitter FIFO has space. SPI Receive Ready (Default: 0) Indicates that there is reception data in the Receiver FIFO. This bit is cleared when the SPDR Register is read and there is no longer any valid data in the Receiver FIFO. 0: Receiver FIFO is empty. 1:There is data in the Receiver FIFO. 2 SIDLE SPI Idle Indicator 1 STRDY SPI Transmit Ready 0 SRRDY SPI Receive Ready Figure 17.4.5 SPI Status Register (SPSR) (2/2) 17.4.6 31 SPI Data Register (SPDR) 0xF818 16 0 : Type : Default 15 DR R/W 0x00 0 : Type : Default Bits 31:16 15:0 Mnemonic ⎯ DR Field Name Reserved SPI Data Register Description ⎯ SPI Data Register (Default: 0x00) The data written to this register is stored in the Transfer Buffer. When the Shift Register is empty, data is written to the Shift Register and transmission begins. You can read the Receiver FIFO data when you read this register. When the transfer data size is 8 bits, use the lower 8 bits of this register. When reading, the upper side (bits[15:8]) are "0". Figure 17.4.6 SPI Data Register (SPDR) 17-14 Chapter 18 NAND Flash Memory IPL 18. NAND Flash Memory IPL 18.1 Features NAND Flash Memory Initial Program Loader (NAND IPL), which is coded in the TX4938 on-chip ROM, enables to boot TX4938 from the NAND flash memory. The user writes NAND IPL control information and a user boot program to the NAND flash memory in the prescribed format. NAND IPL loads the user boot program from the NAND flash memory into RAM and continues the standard boot process. • • Specifying NAND IPL in the boot configuration boot memory starts up NAND IPL. The IPL control information includes the memory controller initialization sequence, the address or the size of the user boot program to be loaded. NAND IPL operates based on NAND IPL control information. NAND IPL supports rewriteable NAND flash memory to be connected to the NAND Flash Memory Controller, Mask ROM type NAND flash memory, and SmartMedia™, but not support the NAND flash memory with partially different configurations. NAND IPL requires a 4 Kbyte stack (work area). Since RAM performs initialization using the NAND IPL control information, you can use various types of RAM. The user may use any memory area in the NAND flash memory except the zone used with NAND IPL, and the area used with NAND IPL when it does not affect operation of NAND IPL. For details on the data specification, see 18.3.5. NAND IPL operates in either Big-endian or Little-endian mode. It also operates in Cache On or Write Through mode. NAND IPL uses PIO [0] bit 1, General Purpose Register ($4) or the lower address of External Bus Controller Channel 0 to signal the NAND IPL operation results. NAND IPL can not be modified since it is written into on-chip ROM. • • • • • • External System Bus RAM TX4938 d) User Boot Program a) NAND IPL NAND Flash Memory b) IPL Control Information c) User Boot Program a) b) c) d) NAND IPL starts up. Read the IPL control information from NAND flash memory. Read the user boot program from the NAND flash memory, then load it into RAM. Start up the user boot program in RAM. Figure 18.1.1 Image Diagram of Booting from NAND Flash Memory 18-1 Chapter 18 NAND Flash Memory IPL 18.2 Block Diagram 18.2.1 System Block Diagram TX4938 TX49/H3 Core Configuration Register SDRAM Control Signal SDRAMC Memory Device such as SDRAM DATA[63:0] On-chip ROM (NAND IPL) EBIF External System Bus DATA[7:0] Command/Data Address Signal NDFMC NAND Flash Memory G-Bus Figure 18.2.1 Block Diagram of System with NAND Flash Memory Connected to SDRAM 18.2.2 Function Block Diagram On-Chip ROM G-Bus G-Bus I/F NAND IPL (8 Kbyte) Figure 18.2.2 Function Block Diagram of NAND IPL 18-2 Chapter 18 NAND Flash Memory IPL 18.3 Detailed Explanation 18.3.1 NAND IPL Operation Conditions (1) NAND IPL supports the Bi-endian (Big- and Little-endian) format. When the TX4938 operates in the Big-endian mode, the Big-endian user boot program may be loaded. When operating in the Little-endian mode, the Little-endian user boot programs may be loaded. (2) The NAND flash memory to be used with NAND IPL is shown below. For the format of the user data to be written in NAND flash memory and data configuration of NAND flash memory, see 18.3.4 and 18.3.5. NAND flash memory must be readable on power up. Table 18.3.1 Usable NAND Flash Memory Device ID Size (MB) 8 16 32 64 128 Flash ROM 0xE6 0x73 0x75 0x76 0x79 Mask ROM 0xD6 0x57 0x58 0xD9 0xDA Bytes/Page Pages/Block 16 Physical Block Count 1024 2048 4096 8192 Zone Count 1 2 4 8 512 + 16 32 (3) NAND IPL uses PIO [0] and General Purpose Register $4 ($a0) to signal the NAND IPL operation results, and external bus controller channel for unusual conditions. (4) Operating NAND IPL requires the 4 Kbyte stack for work area, and RAM having the same size as the user program in which the user boot program is stored. For the address map, see 18.3.3. For initial setting of RAM access and address setting of the work area and user boot program, see 18.3.4. As in the case of booting from the NOR flash memory, the user program requires the work area after jumping to the user boot program. 18-3 Chapter 18 NAND Flash Memory IPL 18.3.2 NAND IPL Operation NAND IPL operates according to the following flow. BEV = 0 or 1 Interrupt to 0xBFC0_0000 Cold/Soft reset, NMI exception (see 18.3.3.2) 1) NAND IPL starts up. 2) Is this a cold reset (≠NMI)? Yes No. NMI Interrupt 3) Is interrupt issued after completion of NAND IPL operation? No BEV = 0 CPU example for BEV=0 Yes Jump to JMPADR specified address. No. Check sum error 1 4) Set PIO[0] Low. CPU interrupt Processing (See 18.3.3.2) 5) Is NAND IPL checksum correct? Yes 6) Is NAND Flash memory ID correct? Yes 7) Is IPL control information is processed correctly? No. NAND Flash memory ID error Yes 8) Hardware initialization No. NAND Flash Memory internal data error 9) Create NAND Flash Memory logical-physical address translation table. No. 1-bit ECC error ECC error correction 10) Was user boot program read correctly? No. 2- or more-bit ECC error Read correctly 11) Load the user boot program. No. Move to the next page 12) Is this the last page of the user boot program? Yes No. Move to the next zone 13) Is this the last zone of the user boot program? Yes 14) Set PIO[0] High. BEV = 1 Except 0xBFC0_0000 (See 18.3.3.2) 1 *1: Jump to the address in the user boot program. End (*1) 15) Set JMPADR. 16) User boot program starts up. 17) Abnormal termination Figure 18.3.1 NAND IPL Program Flow 18-4 Chapter 18 NAND Flash Memory IPL 18.3.2.1 NAND IPL Startup To boot the TX4938, operation usually starts from the 0xBFC0_0000 program (user boot program) connected to External Bus Controller Channel 0. When you specify NAND IPL using Boot Configuration (see section 3.2 Boot Configuration for details), the on-chip ROM is allocated to 0xBFC0_0000 to operate NAND IPL. For details on the NAND IPL address map, see subsection 18.3.3. 18.3.2.2 Cold Reset When cold reset or NMI interrupt occurs, TX49/H3 core transfers the control to 0xBFC0_0000 in NAND IPL. NAND IPL checks whether it is NMI interrupt by referring the SR bit in the Status register. When it is not the NMI interrupt, NAND IPL jumps to kseg0 and goes to the stage 4) Set PIO[0] Low in Figure 18.3.1. Note: NAND IPL refers only the SR bit. 18.3.2.3 MNI Exception When NAND IPL processing is completed, the NAND IPL interrupt handler jumps to the address set in the Jump Address register (JMPADR). When NAND IPL processing is not completed, it jumps to the abnormal processing routine in NAND IPL. For abnormal processing, see 18.3.6. The JMPADR value is used to check whether NAND IPL processing is completed. The initial value 0xBFC0_0000 indicates that NAND IPL processing is not completed, and other values indicate the completion of NAND IPL processing. Note: NAND IPL reads the JMPADR value, which is defined in the IPL control information defined by the user, and sets it in JMPADR. The user must not operate JMPADR. 18.3.2.4 Setting PIO[0] Low NAND IPL uses bit 1 of PIO [0] to signal the program operation status to an external device. When NAND IPL operates, bit 1 of PIO [0] becomes Low. 18.3.2.5 NAND IPL Checksum NAND IPL checks whether the NAND IPL code in on-chip ROM is correct. 18.3.2.6 NAND Flash Memory ID Check NAND IPL checks whether the NAND flash memory being used can respond properly to NAND IPL by reading the NAND flash memory ID. 18-5 Chapter 18 NAND Flash Memory IPL 18.3.2.7 NAND IPL Control Information Processing NAND IPL reads the data defined in compliance with the prescribed format from NAND flash memory. Since NAND IPL can not use RAM at this stage, access to the NAND flash memory by specifying a physical address. You can not use Error Check and Correct (ECC). Therefore, NAND IPL judges the correctness of the IPL control information using the following method. For more information on the prescribed format, see 18.3.4. • The IPL control information consists of the same data set written three times consecutively. NAND IPL compares these three data sets on read of them, and regards as a correct one when at least two of the three data sets are identical. NAND IPL performs the following operation to search the IPL control information. • Performs normal block check of the NAND flash memory only with the data contained in the top page of the block “Block Status Area” (redundant area). NAND IPL does not perform this check on the applicable data in other pages. Since the NAND flash memory may contain bad blocks, you can not fix the IPL control information to a specific physical address. NAND IPL sequentially reads physical blocks 0 through 23, and searches each page within a block to find the IPL control information start ID on the top of the page when the block is good one. • 18.3.2.8 Hardware Initialization NAND IPL secures a stack (work area) which is used for RAM access setup (initialization) or NAND IPL in accordance to the IPL control information defined in the NAND flash memory. Note: The external bus controller channel can be set by writing IPL control information, but that is not recommended due to processing speed. We recommend to perform the minimum hardware setting in NAND IPL such as NAND flash memory and RAM access required to operate IPL, and to use the boot program for other settings. 18.3.2.9 NAND Flash Memory Logical-physical Address Translation Table Creation NAND IPL creates a logical-physical address translation table since NAND flash memory after RAM is secured is accessed using logical addresses. For the logical address, see 18.3.5.1. NAND IPL creates the address translation table for every zone, and recreates it (*1) if the zone is changed. (*1): NAND IPL has the information for only one zone, which indicates relationship between the logical-physical address translation table (translation table) and the target zone. Upon load of the user boot program (program), NAND IPL creates the translation table of the zone which resides in the top block of the program, and remembers the zone number before load of the program in this zone. If a program spans multiple zones, NAND IPL recreates the translation table of the new target zone when the block to be loaded by NAND IPL exits from the target zone, and loads the program of the new zone. 18-6 Chapter 18 NAND Flash Memory IPL 18.3.2.10 Checking Read of the User Boot Program NAND IPL reads the user boot program from NAND flash memory in accordance to the information such as the address defined in the IPL control information. If a 1-bit error is detected upon read of data for one page, NAND IPL performs 1-bit ECC correction (see 18.3.5.1), when 2or more-bit error is detected, NAND IPL jumps to abnormal termination processing. Note that you can not write this data back to the NAND flash memory after correcting 1-bit error on it. 18.3.2.11 Loading the User Boot Program NAND IPL loads the user boot program for one page, which is read from the NAND flash memory, into RAM. As described in 18.3.2.10, NAND IPL corrects the user boot program if 1-bit error is detected, and loads it into RAM. 18.3.2.12 Checking the Last Page of the User Boot Program NAND IPL checks whether the page being loaded is the last page in which the user boot program resides. If it is not the last page, NAND IPL returns to processing of 18.3.2.10 and continues load of the user boot program. 18.3.2.13 Checking the Last Zone of the User Boot Program NAND IPL checks whether the zone being loaded with NAND IPL is the last zone in which the user boot program resides. If it is not the last zone, NAND IPL returns to processing of 18.3.2.9 and recreates the logical-physical address translation table before load of the user boot program. 18.3.2.14 Setting PIO[0] High After loading is terminated normally, NAND IPL sets bit 1 of PIO [0] to High. PIO [0] which remains Low indicates that an error occurred and loading of the user boot program was not completed. For details, see 18.3.6 NAND Flash Memory IPL Error Handling. 18.3.2.15 Setting Jump Address Register (JMPADR) Before transferring the control to the user boot program, NAND IPL rewrites the initial Jumper Address Register (JMPADR) value of 0xBFC0_0000 to the top address of the user boot program. For information on this register, see 5.2.8 Jump Address Register. 18.3.2.16 User Boot Program Startup NAND IPL jumps to the value set with the jump address register (JMPADR), then starts up the user boot program and transfers the control to it. The user needs to write processing for occurrence of CPU exception on the top address of the user boot program. For details, see 18.3.3.2. 18.3.2.17 Abnormal Termination NAND IPL can detect multiple errors. For more information, see 18.3.6 NAND Flash Memory IPL Error Handling. 18-7 Chapter 18 NAND Flash Memory IPL 18.3.3 NAND Flash Memory IPL Address Map 18.3.3.1 Address Information When NAND IPL Starts up When NAND IPL is specified by boot memory setting of Boot Configuration, NAND IPL is allocated to 0xBFC0_0000 which is the reset vector. The area of the user boot program to be loaded by NAND IPL is either kseg0 or kseg1. You can set the load destination address to any address within this range. The user boot program is usually allocated to 0xBFC0_0000 in the TX49/H3 core mounted products. When NAND IPL is used, NAND IPL creates (loads) the user boot program at a RAM address. 18.3.3.2 Address Information When CPU Exception Is Issued (1) Cold Reset/NMI Exception If an exception occurs after startup of the user boot program and BEV=0 or BEV=1 is set to the TX49/H3 core Status Register, TX49/H3 core transfers the control to address 0xBFC0_0000. NAND IPL checks whether an exception is an NMI exception. When it is an NMI exception, NAND IPL refers to the Jump Address Register (JPMADR) and transfers the control to the (JMPADR) address (*1), which is the top address of the user boot program. When it is not an NMI exception, execution starts from address 0xBFC0_0000. Therefore, you need to describe the exception vector for an NMI exception in the JMPADR address of the user boot program. (*1): The jump destination address set in the Jump Address Register (JMPADR) (2) TLB Refill Exception If an exception occurs after startup of the user boot program and BEV=0 is set to the TX49/H3 core Status Register, the TX49/H3 core transfers the control to address 0x8000_0000. When BEV=1, NAND IPL Exception Handler refers to the Jump Address Register (JMPADR) from exception vector address 0xBFC0_0200 and transfers the control to the (JMPADR) + 0x0200 address of the user boot program. Therefore, you need to describe an exception vector to the (JMPADR) + 0x0200 address of the user boot program when this exception occurs. (3) XTLB Refill Exception If an exception occurs after startup of the user boot program and BEV=0 is set to the TX49/H3 core Status Register, the TX49/H3 core transfers the control to address 0x8000_0080. When BEV=1, NAND IPL Exception Handler refers to the Jump Address Register (JMPADR) from exception vector address 0xBFC0_0280 and transfers the control to the (JMPADR) + 0x0280 address of the user boot program. Therefore, you need to describe an exception vector to the (JMPADR) + 0x0280 address of the user boot program when this exception occurs. 18-8 Chapter 18 NAND Flash Memory IPL (4) Other Exceptions (Common Exceptions) If an exception occurs after startup of the user boot program and BEV=0 is set to the TX49/H3 core Status Register, the TX49/H3 core transfers the control to address 0x8000_0180. When BEV=1, NAND IPL Exception Handler refers to the Jump Address Register (JMPADR) from exception vector address 0xBFC0_0380 and transfers the control to the (JMPADR) + 0x0380 address of the user boot program. Therefore, you have to describe an exception vector to the (JMPADR) + 0x0380 address of the user boot program when this exception occurs. For details on interrupts, see the document "64-bit TX System RISC TX49/H3 Core Architecture" provided by Toshiba. 18-9 Chapter 18 NAND Flash Memory IPL 0xBFFF_FFFF Physical Address Space 0xFFFF FFFF 0xFF1F _FFFF 0xFF1F _0000 TX4938 On-chip Register 0xC000 _0000 kseg1 Unmapped Uncached kseg0 (*1) Unmapped Cacheable BEV=1 0xBFC0_0380 0xBFC0_0280 0xBFC0_0200 0xBFC0_0000 Virtual Address Space 0xFFFF _FFFF 0xBFD0_0080 0xBFD0_0000 0xBFC0_1FFF Area Used to Signal Errors NAND IPL 8 Kbyte (Other Exception Vector) (XTLB Exception Vector) (TLB Exception Vector) (Reset, NMI Exception Vector) 0xA000 0000 0x8000 0000 0xA000_0000 Stack Top (*2) Stack (Work Area) 4 Kbyte User Boot Program 0x1FFF _FFFF 0x0000 _0000 BEV=0 (JMPADR)+0x380 (JMPADR)+0x280 (JMPADR)+0x200 (JMPADR) (*3) (Other Exception Vector) (XTLB Exception Vector) (TLB Exception Vector) (NMI Exception Vector) 0x0000 _0000 *1) NAND IPL uses 0x9FC0_0000 through 0x9FC0_1FFF in kseg0. Exception Vector when BEV=1 0x8000_0180 0x8000_0080 0x8000_0000 Other Exception Vector XTLB Exception Vector TLB Exception Vector *2) The stack top address is the value defined in the NAND IPL control information. *3) The user boot program address is the value defined in the NAND IPL control information. This address is stored in the JMPADR Register. Figure 18.3.2 NAND IPL Address Map 18-10 Chapter 18 NAND Flash Memory IPL 18.3.4 NAND Flash Memory IPL Control Information 18.3.4.1 IPL Control Information Configuration To start up NAND IPL, you need to save the IPL control information in the NAND flash memory in advance. Describe the IPL control information using multiple control information commands in compliance with the prescribed format. You need to describe it in the order given below. (1) IPL Control Information Start ID Write the “TX49” ASCII code as the start information. (2) NAND Flash Memory Access Setup Set up the strobe pulse width (SPW) of the NAND Flash Memory Strobe Pulse Width Register (NDFSPR). Note: The NAND flash memory operates at the slowest speed value with the initial NAND IPL setting. If you want to accelerate NAND IPL, set a value appropriate for the speed of the NAND flash memory being used. (3) RAM Access Setup RAM is connected to either the External Bus Controller or the SDRAM Controller, which depends on the type of RAM to be used. You will perform initial setting of memory access required for RAM to be connected. The following shows examples when RAM is connected to the SDRAM Controller. For details, see subsection 9.3.3 Initialization of SDRAM. – SDRAM Channel Control Register (SDCCRn) – SDRAM Timing Register (SDCTR) – SDRAM Command Register (SDCCMD) – Refresh Counter Setup – SDRAM Intialization (4) Stack (Work Area) Setup Set the address of the 4-Kbyte stack (work area) used by NAND IPL. (5) Page Crossing Setup “Page crossing” refers to a situation where the IPL control information can not be contained within a single page (512 bytes) and spans across multiple pages. When performing page crossing, the “page crossing command” indicates that the subsequent command resides on the next page. Write a “IPL control information continuation ID” on the top of the next page. When the IPL control information is contained in a single page, this command is not required. (6) User Boot Program Setup Specify the logical address and program size (bytes) of the NAND flash memory that saves the user boot program, and the load destination address of RAM. Note: To use RAM with memory parity or ECC, initialize the user boot program area of the load destination because reading RAM having no data results in an error. 18-11 Chapter 18 NAND Flash Memory IPL 18.3.4.2 Describing the IPL Control Information Describe the IPL control information in NAND flash memory in the following format. • • • • Describe it in the format of the command or the parameters that the command takes. For details, see Table 18.3.2. Commands and parameters are in units of 32 bits/data. Write the same command or parameter three times in a row. In other words, write the same 32-bit data three times in a row. Always describe it in the Big-endian format regardless of endian during operation. Table 18.3.2 IPL Control Information Command No. 1 2 3 4 5 6 7 8 9 10 11 Command Name STARTID W RITE32 W RITE64 W AITSDRAM W AITTIME MEMORY W ORK NEXTINF NEXTID BOOTLA NOP Command Value 0x5458_3439 0x0000_0001 0x0000_0002 0x0000_0003 0x0000_0004 0x0000_0005 0x0000_0006 0x0000_0007 0x5458_346E 0x0000_0008 0x0000_0009 Function IPL Control Information Start ID 32-bit Write 64-bit Write SDRAM Initialization Completion Wait Wait Time Memory Initialization Specify Stack Page Crossing IPL Control Information Continuation ID User Boot Program Specification No Operation No. 1 Parameter Address Address 0x0000_0000 Loop Count Start Address Stack Top 0xEEEE_EEEE NAND Flash Memory Logical Address 0x0000_0000 No. 2 Parameter Data High Data Size (Bytes) Program Size (Bytes) - No. 3 Parameter Low Data Load Destination RAM Address - (1) IPL Control Information Start ID (STARTID) This command indicates start of the IPL control information. Describe “TX49” (0x5458_3439) in ASCII code. NAND IPL recognizes data from this command to the BOOTLA command, which is written in NAND flash memory, as the IPL control information. (2) 32-bit Write (WRITE32) Use this command to perform operations such as SDRAM initialization using register settings. Write 32-bit data to the specified 32-bit address. (3) 64-bit Write (WRITE64) Use this command to perform operations such as SDRAM initialization for register setting. Combine 32-bit high-order data and 32-bit low-order data into one 64-bit data, and write the 64-bit data to the specified 32-bit addresses. Note: You can use the 32-bit Write command to initialize a 64-bit register, but we recommend to use the 64-bit write command. 18-12 Chapter 18 NAND Flash Memory IPL (4) SDRAM Initialization Completion Wait (WAITSDRAM) This command waits until the count value set in the Refresh Counter (RC) of the SDRAM Timing Register (SDCTR) becomes 0. Before invoking this command, set the refresh counter value required for initialization in accordance with the specifications of the SDRAM being used. (5) Wait Time (WAITTIME) NAND IPL executes the loop among three instructions the number of times specified with this command (operation with the Instruction cache On), and waits. Note that wait time changes depending on the CPU clock. (6) Memory Initialization (MEMORY) This command initializes memory to 0 by specifying the address and size (in bytes) of the target memory. Use this command to initialize RAM with memory parity or ECC. (7) Stack (Work Area) Specifications (WORK) After enabling RAM operation, this command specifies the top address of the 4-Kbyte stack used by NAND IPL. Refer to Figure 18.3.2 NAND IPL Address Map. (8) Page Crossing (NEXTINF) This command is used when the IPL control information spans across multiple pages (exceeds 512 bytes in size). Describing this command indicates that the IPL control information described on this page ends. To use the NEXTINF command, the IPL Control Information Continuation command (NEXTID) is required. (9) IPL Control Information Continuation ID (NEXTID) This command is used when the IPL control information spans across multiple pages (exceeds 512 bytes in size). Describing ASCII code “TX4n” (0x5458_346E), that is the NEXTID command, at the top of the applicable page, indicates that this page is a continuation of the IPL control information. To use the NEXTID command, the Page Crossing command (NEXTINF) is required. (10) User Boot Program Specification (BOOTLA) This command specifies the logical start address of the NAND flash memory containing the user boot program (see 18.3.5.1), the size of the program (in bytes), and the load destination address of RAM to be loaded by NAND IPL. Since NAND IPL recognizes this command as the end of the IPL control information, subsequent commands are not executed. (11) No Operation (NO) This command performs no operation. 18-13 Chapter 18 NAND Flash Memory IPL 18.3.4.3 Example Definition of the IPL Control Information Table 18.3.3 Page Configuration Example of the IPL Control Information Offset Address 0x000 0x004 0x008 0x00c 0x010 0x014 0x018 0x01c 0x020 0x024 0x028 0x02c 0x030 0x034 0x038 0x03c 0x040 0x044 0x048 0x04c 0x050 0x054 0x058 0x05c 0x060 0x064 0x068 0x06c 0x070 0x074 0x078 0x07c 0x080 0x084 0x088 0x08c 0x090 0x094 0x098 0x09c 0x0a0 0x0a4 0x0a8 0x0ac 0x0b0 0x0b4 0x0b8 0x0bc 0x0c0 Command STARTINF ↓ ↓ WRITE64 ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ ↓ No. 3 Parameter ↓ ↓ WRITE64 ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ ↓ No. 3 Parameter ↓ ↓ WRITE64 ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ ↓ No. 3 Parameter ↓ ↓ WRITE64 ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ ↓ No. 3 Parameter Content Indicates “IPL Control Information Start ID” ↓ ↓ Indicates “64-bit Write Command” ↓ ↓ NDFSPR Register Address ↓ ↓ Pulse Width Setting (High Data) of NAND Flash Memory Write Data (Example) 0x5458_3439 ↓ ↓ 0x0000_0002 ↓ ↓ 0xFF1F_5028 ↓ ↓ 0x0000_0000 ↓ ↓ 0x0000_0045 ↓ ↓ 0x0000_0002 ↓ ↓ 0xFF1F_8000 ↓ ↓ 0x0000_000E ↓ ↓ 0x0000_0404 ↓ ↓ 0x0000_0002 ↓ ↓ 0xFF1F_8040 ↓ ↓ 0x0000_0003 ↓ ↓ 0xBE02_0400 ↓ ↓ 0x0000_0002 ↓ ↓ 0xFF1F_8058 ↓ ↓ 0x0000_0000 ↓ ↓ 0x0000_0013 ↓ ↓ Pulse Width Setting (Low Data) of NAND Flash Memory ↓ ↓ Indicates “64-bit Write Command” ↓ ↓ SDCCR0 Register Address ↓ ↓ SDCCR0 Register Setting (High Data) ↓ ↓ SDCCR0 Register Setting (Low Data) ↓ ↓ Indicates “64-bit Write Command” ↓ ↓ SDCTR Register Address ↓ ↓ SDCTR Register Setting (High Data) ↓ ↓ SDCTR Register Setting (Low Data) ↓ ↓ Indicates “64-bit Write Command” ↓ ↓ SDCCMD Register Address ↓ ↓ SDCCMD Register Setting (High Data) ↓ ↓ SDCCMD Register Setting (Low Data) 18-14 Chapter 18 NAND Flash Memory IPL Command 0x0c4 0x0c8 0x0cc 0x0d0 0x0d4 0x0d8 0x0dc 0x0e0 0x0e4 0x0e8 0x0ec 0x0f0 0x0f4 0x0f8 0x0fc 0x100 0x104 0x108 0x10c 0x110 0x114 0x118 0x11c 0x120 0x124 0x128 0x12c 0x130 0x134 0x138 0x13c 0x140 0x144 0x148 0x14c 0x150 0x154 0x158 0x15c 0x160 0x164 0x1f0 0x000 0x004 Next Page 0x008 0x00c 0x010 0x014 0x018 0x01c 0x020 0x024 0x028 ↓ ↓ WRITE64 ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ ↓ No. 3 Parameter ↓ ↓ WAITSDRAM ↓ ↓ No. 1 Parameter ↓ ↓ MEMORY ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ ↓ WORK ↓ ↓ No. 1 Parameter ↓ ↓ NEXTINF ↓ ↓ No. 1 Parameter ↓ ↓ Omitted None NEXTID ↓ ↓ BOOTLA ↓ ↓ No. 1 Parameter ↓ ↓ No. 2 Parameter ↓ None Indicates “IPL Control Information Continuation ID” Content ↓ ↓ Indicates “64-bit Write Command” ↓ ↓ SDCCMD Register Address ↓ ↓ SDCCMD Register Setting (High Data) ↓ ↓ SDCCMD Register Setting (Low Data) ↓ ↓ Indicates “SDRAM Initialization Completion Wait Command” Write Data (Example) ↓ ↓ 0x0000_0002 ↓ ↓ 0xFF1F_8058 ↓ ↓ 0x0000_0000 ↓ ↓ 0x0000_0011 ↓ ↓ 0x0000_0003 ↓ ↓ 0x0000_0000 ↓ ↓ 0x0000_0005 ↓ ↓ 0xA001_0000 ↓ ↓ 0x0000_8000 ↓ ↓ 0x0000_0006 ↓ ↓ 0xA000_8000 ↓ ↓ 0x0000_0007 ↓ ↓ 0xEEEE_EEEE ↓ ↓ 0x0000_0000 0x5458_346E ↓ ↓ 0x0000_0008 ↓ ↓ 0x0000_0001 ↓ ↓ 0x0000_8000 ↓ ↓ ↓ Counter Value 0 ↓ ↓ Indicates “Memory Initialization Command” ↓ ↓ Start Address ↓ ↓ Size (Bytes) ↓ ↓ Indicates “Stack Specification Command” ↓ ↓ Stack Top Address ↓ ↓ Indicates “Page Crossing Command” ↓ ↓ Page Crossing End ID ↓ ↓ ↓ ↓ Indicates “User Boot Program Specification Command” ↓ ↓ NAND Flash Memory Logical Address ↓ ↓ Size of User Boot Program (Bytes) ↓ 18-15 Chapter 18 NAND Flash Memory IPL Command 0x02c 0x030 0x034 0x038 ↓ No. 3 Parameter ↓ ↓ Content ↓ Load Destination SDRAM Address ↓ ↓ Write Data (Example) ↓ 0xA001_0000 ↓ ↓ 18-16 Chapter 18 NAND Flash Memory IPL 18.3.5 Data configuration of NAND Flash Memory This section describes how to use the NAND flash memory of NAND IPL. Subsection 18.3.5.1 describes the standard physical format of the NAND flash memory prescribed in SmartMedia™ Standard 2000, and 18.3.5.2 describes how to used the NAND flash memory referred by NAND IPL. Note: NAND IPL is designed by referring the physical format of SmartMedia™ Standard 2000, but all memory area of the NAND flash memory used by NAND IPL need not satisfy this specification. The data configuration referred by NAND IPL is described 18.3.5.2 or later subsections. 18.3.5.1 Data Configuration of the NAND Flash Memory The standard data format (physical format) of the NAND flash memory is shown in Table 18.3.4. Since the number of zones and blocks depends on the capacitance of the NAND flash memory, use Table 18.3.4 together with Table 18.3.1. Table 18.3.5 and 18.3.6 show Card Information Structure (CIS)/Identify Drive Information (IDI) area, data area and data configuration of each redundant area. This chapter refers to “SmartMedia™ Physical Format Specification”. Table 18.3.4 NAND Flash Memory Physical Format Specification Page 0 Block 0 Page 1 : Page end Page 0 Zone 0 Block 1 Page 1 : Page end : : Page 0 Block end Page 1 : Page end : : : Page 0 Block 0 Page 1 : Page end Page 0 Zone end Block 1 Page 1 : Page end : : Page 0 Block end Page 1 : Page end Data Area (512 bytes) (*1) ↓ : ↓ : ↓ ↓ : ↓ : ↓ ↓ : ↓ ↓ ↓ : ↓ : ↓ ↓ : ↓ Redundant Area (16 bytes) ↓ : ↓ : ↓ ↓ : ↓ : ↓ ↓ : ↓ ↓ ↓ : ↓ : ↓ ↓ : ↓ CIS/ IDI Area (*1) Redundant Area (16 bytes) 18-17 Chapter 18 NAND Flash Memory IPL (*1) Supplemental Remarks In the case of the flash memory type, the CIS/IDI area is allocated to the physical block 0. If the physical block 0 is a bad one, the CIS/IDI area is allocated to the physical block 1 or the first subsequent block that is found good. Only one block is allocated to the physical block 0, and the other blocks are used as the data areas. For the relationship between logical and physical blocks, see Table 18.3.5. When the Mask ROM type is used, the CIS/IDI area is allocated to the physical block 0. The relationship between logical and physical blocks is “( logical block address) = (physical block address) - 1”. The area of the physical block 1 through the data end block address becomes the data area, and the others are the reserved areas. Table 18.3.5 Data Specification of the CIS/IDI Area in NAND Flash Memory Flash Memory Type Byte 0 - 127 Data Area 128 - 255 256 - 383 384 - 511 512 513 514 515 516 517 518 Redundant Area 519 520 521 522 523 524 525 526 527 ECC Area-1 0x0000 (Fixed) ECC Area-2 Invalid Data Flag Area (Information Validity) 0xFF (Fixed) 0x0000 (Fixed) Functional Select Information Area CIS Area-1 IDI Area-1 CIS Area-2 IDI Area-2 Mask ROM Type Description CIS Area-1 IDI Area-1 CIS Area-2 IDI Area-2 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) Description (1) CIS Area (Field) This area contains the data required to check whether the format is based on the physical format specification of SmartMedia™ Standard 2000. The first 10 bytes are fixed to 0x01_03_D9_01_FF_18_02_DF_01_20. The same data is stored in the CIS Area-1 and CIS Area-2 to ensure reliability. Note: We recommend to store the data in the CIS area, though NAND IPL does not use the data in it. (2) IDI Area (Field) This is the area to store the data used with the system having ATA interface. The same data, of which default value is 0x00, is stored in the CIS Area-1 and CIS Area-2 to ensure reliability. Note: NAND IPL does not use the data in the IDI area. 18-18 Chapter 18 NAND Flash Memory IPL (3) Data Stored in the Redundant Area General information on the redundant area is shown below. • • • Functional Select Information Area: The area reserved for function expansion Invalid Data Flag Area: ECC Area-1, ECC Area-2: The area which indicates the validity of the data in the CIS/IDI area 3-byte ECC code of the page data (256 bytes) Note: NAND IPL does not use the data stored in the redundant area of the CIS/IDI area. Table 18.3.6 Data Specification of the Data Area in NAND Flash Memory Flash Memory Type Byte Data Area 0 - 255 256 - 511 512 513 514 515 516 517 518 Redundant Area 519 520 521 522 523 524 525 526 527 ECC Area-1 Block Address Area-2 ECC Area-2 Data Status Area Block Status Area Block Address Area-1 Reserved Area Data Area-1 Data Area-2 Mask ROM Type Description Data Area-1 Data Area-2 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) 0xFF (Fixed) Description Note: For the data in the redundant area of the data area used by NAND IPL, see Table 18.3.10. (1) Data Area (Field)-1 Contains the data of 0 to 255th bytes, that is the first half of the 512-byte data. (2) Data Area (Field)-2 Contains the data of 256th to 512th bytes, that is the last half of the 512-byte data. (3) Reserved Area (Field) This is the area reserved for function expansion, and contains the fixed value 0xFFFF_FFFF. (4) Data Status Area (Field) This area indicates that Data Area-1 and Data Area-2 store incorrect data. 0xFF is set typically. When incorrect data is written, 0x00 is set to this area. 18-19 Chapter 18 NAND Flash Memory IPL (5) Block Status Area (Field) This area indicates whether the block is good or not. 0xFF (good block) is set typically. In the case of the bad block, 0x00 (initial bad block) or 0xF0 (subsequent bad block) is set to this area. Specify the same value in the same block. (6) Block Address Area (Field)-1 This area indicates translation information from physical block address into the logical block address. Table 18.3.7 shows the data specification. Specify the same value in the same block. For details on the logical-physical address translation, see “logical-physical address translation table” described later. Table 18.3.7 Data Specification in Block Address Area D7 0 BA6 D6 0 BA5 D5 0 BA4 D4 1 BA3 D3 0 BA2 D2 BA9 BA1 D1 BA8 BA0 D0 BA7 P 512 + 16 Byte/Page 518,523 Byte 519,524 Byte BA9 ∼ BAO: Block Address (Value = 0 ∼ ‘Max Logical Blocks 1’) P: Even-parity Bit Note: Block Address indicates the logical address partitioned in erase block units, that is 8 bytes. (7) Block Address Area (Field)-2 This area contains the data same as Block Address Area-1. The SmartMedia™ Standard 2000 physical format specification defines that the logical block in NAND flash memory is not assigned to a specific physical block. The Block Address Area in each block contains logical block addresses assigned to physical blocks. Logical-physical address translation is available by searching these addresses. A physical and logical blocks are paired. Since all logical blocks are not assigned to physical blocks, logical blocks reside to which physical blocks are not assigned. Figure 18.3.3 shows an example of a logical-physical address translation table. This subsection refers to “SmartMedia™ Interface library (SMIL) -Software Version-”. 18-20 Chapter 18 NAND Flash Memory IPL Physical Block Address 0 1 2 3 4 5 6 7 8 . . . Block Data block0(Data) block1(Data) block2(Data) block3(Data) block4(Data) block5(Data) block6(Data) block7(Data) block8(Data) . . . NAND Flash Memory Logical Block Address 8 3 4 7 0 6 1 Unused 2 Logical Block Address 0 1 2 3 4 5 6 7 8 . . . Physical Block Address 4 6 8 1 2 Unassigned 5 3 0 . . . Logical-Physical Address Translation Table Figure 18.3.3 Logical-Physical Address Translation Table • • • • The number of physical blocks in one zone is 1024, and that of logical blocks is 1000. The value described in the Block Address Area is 0 to 999. The logical block addresses can not be assigned to the physical block containing the CIS/IDI area. The logical block address is a unique address, which is the sequential number from the logical block 0 in an entire NAND flash memory. The address is obtained with the following equation. Logical block address = (Zone_number × 1000) + (Block_number_described_in_Block_Address_Area) • The logical page address is the sequential page address which starts from the page 0 in the logic block 0 and ends with the last page in the last logic block. The address is obtained with the following equation. Logical page address = (Logical_block_address × the_number_of_pages_in_each_block) + (Page_number_described_in_the_block) (8) ECC AREA (Field)-1 This area presents the 3-byte ECC code for the page data which is assigned to 0 through 255th byte (256 bytes). For details on ECC code, see “ECC Method” described below. (9) ECC AREA (Field)-2 This area presents the 3-byte ECC code of the page data which is assigned to 256th through 511th byte (256 bytes). For details on ECC code, see “ECC Method” described below. 18-21 Chapter 18 NAND Flash Memory IPL 256-byte data area is added with 22-bit ECC code by the physical format specification of SmartMedia™ Standard 2000. Data Area-1 and Data Area-2 are added with ECC Area-1 and ECC Area-2, respectively. The EEC code provides correction capability of 1-bit random error, and detection capability of 2-bit random error. EEC code is generated for the data area, and not for the data in the page redundant area including ECC code. The data in the page redundant area is duplicate to ensure reliability, which enables you to check the correctness of the data. 256-byte data is handled as 2048-bit serial data by ECC equation. When an error occurs, the error occurrence bit is detected with the parity data information, and data can be corrected. • Defining Address of 2048-bit Serial Data 256 bytes are aligned to 2048-bit serial data as shown in Table 18.3.8. Table 18.3.8 2048-bit Serial Data Address bit 7 1 Byte 2nd Byte 255th Byte 256th Byte st bit 6 00000000 110 00000001 110 11111110 110 11111111 110 bit 1 00000000 001 00000001 001 11111110 001 11111111 001 bit 0 00000000 000 00000001 000 11111110 000 11111111 000 00000000 111 00000001 111 11111110 111 11111111 111 The top-line in the above table indicates input of the first byte, and the bottom-line is input of the 256th byte. The bit 0 of the first bite becomes the first bit of 2048 bits (address 00000000 000), and the bit 7 of 256th byte becomes the 2048th bit of 2048 bits (address 11111111 111). 18-22 Chapter 18 NAND Flash Memory IPL • Generating Parity Data Parity data consists of 22 bits; CP0, CP1, CP2, CP3, CP4, CP5, LP00, LP01, LP02, LP03, LP04 through LP14 and LP15. The Column parity (CP) consists of 6 bits and Line Parity (LP) consists of 16 bits. The parity data to be generated is aligned as shown below and stored in the page redundant area data. Table 18.3.9 ECC Data Alignment bit 7 LP07 LP15 CP5 bit 6 LP06 LP14 CP4 bit 5 LP05 LP13 CP3 bit 4 LP04 LP12 CP2 bit 3 LP03 LP11 CP1 bit 2 LP02 LP10 CP0 bit 1 LP01 LP09 “1” bit 0 LP00 LP08 “1” 512 + 16 Byte/Page 520,525 Byte 521,526 Byte 522,527 Byte Line Parity (LP) and Column Parity (CP) are odd-parity of 1024 bits which satisfy the following conditions. LP00 = D (*******0 , ***) LP01 = D (*******1 , ***) LP02 = D (******0* , ***) LP03 = D (******1* , ***) LP04 = D (*****0** , ***) LP05 = D (*****1** , ***) LP06 = D (****0*** , ***) LP07 = D (****1*** , ***) LP08 = D (***0**** , ***) LP09 = D (***1**** , ***) LP10 = D (**0***** , ***) LP11 = D (**1***** , ***) LP12 = D (*0****** , ***) LP13 = D (*1****** , ***) LP14 = D (0******* , ***) LP15 = D (1******* , ***) CP0 = D (******** , **0) CP1 = D (******** , **1) CP2 = D (******** , *0*) CP3 = D (******** , *1*) CP4 = D (******** , 0**) CP5 = D (******** , 1**) where, an asterisk (*) indicates 0 or 1. 18.3.5.2 Writing IPL Control Information • Write IPL control information in the block containing the CIS area, which is assigned to the physical address 0 through 23rd block, or subsequent block. We recommend to write it in the block containing the CIS area, and in the page next to the page containing the CIS area.When IPL control information is not written since there is not good one until the physical address 23, the NAND flash memory can not be used because NAND IPL does not operate correctly. The redundant block data containing the IPL control information must satisfy the following conditions. See Table 18.3.10. − Block Status Area is correct. (0 is not set or set to 1 bit) − The same data is stored in Block Address Area-1 and Block Address Area-2. • 18-23 Chapter 18 NAND Flash Memory IPL 18.3.5.3 Writing the User Boot Program • The user boot program can be written in any logical address of the NAND flash memory, and span across multiple blocks and zones. The user boot program is handled as a single object assigned to continuous space with the logical address in the NAND flash memory. NAND IPL can load only a single object into the continuous space in RAM. The data in the redundant area containing the user boot program must satisfy the following conditions. See Table 18.3.10. Note: NAND IPL neither registers the block which does not satisfy the following conditions in the logical-physical address translation table, nor issues an error of this block because it is not loaded into RAM. See Table 18.3.10. • • − Block Status Area and Data Status Area are good ones (0 is not set or set to 1 bit) − The same data is stored in Block Address Area-1 and Block Address Area-2. − The value in Block Address Area-1 does not match to the value 0x000 in Block Address Field-s fro CIS/IDI. − The value in Block Address Area-1 is not a valid logical address (high-order 4 bits do not match 0001B.) − The even-parity bit in Block Address Area-1 is correct. • When the same address appears multiple times in the logic block address which indicates the user boot program, NAND IPL is not guaranteed to behave correctly. 18-24 Chapter 18 NAND Flash Memory IPL 18.3.5.4 IPL Control Information and Areas Except the User Boot Program • Any data description is allowed in the zone which is not used with NAND IPL, that is the area in which the IPL control information and the user boot program are not stored. Note: NAND IPL creates a logical-physical address translation table based on the data in the redundant area upon accessing to NAND flash memory. The redundant area of the zone containing the IPL control information and user boot program must be written in compliant with the specification shown in 18.3.5.1. Table 18.3.10 Data in the Redundant Area Used with NAND IPL Redundant Block 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 ECC Area-1 − − Used Block Address Area-2 Used Used − ECC Area-2 − − Used Data Status Area Block Status Area Block Address Area-1 − Used Used Used Used Used − − − Reserved Area − − − Area Searching IPL Control Information (*1) Creating the LogicalPhysical Translation Table (*2) Loading the User Boot Program into RAM (*3) (*1) (*2) (*3) Used to search the IPL control information written in the NAND flash memory at the stage “7) Is IPL Control Information processed correctly?” in Figure 18.3.1. Used to create the translation table at the stage “9) Create NAND Flash Memory Logical-Physical address Translation Table.” in Figure 18.3.1. Used to load the user boot program into RAM at the stage “11) Load the User Boot Program.” in Figure 18.3.1. 18-25 Chapter 18 NAND Flash Memory IPL 18.3.6 NAND Flash Memory IPL Error Handling NAND IPL signals the program operation to an external device using 1 bit of PIO[0]. PIO[0] becomes Low upon startup of NAND IPL, and High to transfer the control to the user boot program after it is loaded into RAM correctly. If PIO[0] remains Low, abnormal condition occurs. When NAND IPL detects the abnormal condition, it sets the error ID shown in Table 18.3.4 to $4($a0) in the general register, and continues issuing the EROR ID to the low-order bit of virtual address 0xBFD0_0000 by setting the external bus controller channel 0 of 32-bit bus width (EBCCR0=0x01FD_0000_0013_E008). To signal this error, the area 0xBFD_0000 through 0xBFD0_0080 is used. This information is recognized by connection to the logic analyzer. Even in the case the error is detected, the user boot program is invoked in the following cases. • • When detecting a 1-bit error in the ECC code, NAND-IPL corrects the 1-bit error and loads the user boot program into RAM. When the size of the user boot program is smaller than that written in the IPL control information, the same amount of data as that being written (user boot program + &) is loaded into RAM. PIO[0] remains Low to signal the error condition. When the size of the user boot program is larger than that written in the IPL control information, NAND IPL does not operate correctly since it loads the same amount of data as that being written in the IPL control information. Table 18.3.11 Errors (Address Bit) Error ID 0x010 0x020 0x040 0x080 0x100 0x200 Address [7:0] 0x04 0x08 0x10 0x20 0x40 0x80 Error Type NAND flash memory ID error IPL control information error ECC 2- or more-bit error ECC 1-bit Error User boot program error NAND IPL checksum error Cause of Error Undefined NAND flash memory is used. The IPL control information is incorrect. The NAND flash memory data is corrupted. (ECC code indicates 2- or more-bit error.) The NAND flash memory data is corrupted. (ECC code indicates 1-bit error.) The user boot program is not written in NAND flash memory. NAND IPL is not written to on-chip ROM correctly. A reset or NMI exception which occurs during NAND IPL operation results in abnormal termination since the jump address register (JMPADR) addresses NAND IPL (0xBFC0_0000). When the error detailed information is not generated, NMI exception may occur. When PIO[0] is used for the purpose other than a signal which indicates NAND IPL operation on the system, NAND IPL does not operate as intended. That must be avoided on the system. PIO[0] is multiplexed with SPICLK on TX4938. To use SPICLK, you need to establish connection of PIO[0] so that no electrical problem occurs when NAND IPL outputs PIO[0] upon startup of system. 18-26 Chapter 19 On-Chip SRAM 19. On-Chip SRAM 19.1 Characteristics The TX4938 has 1-channel of on-chip, fast 2-KB SRAM. You can map it to any address space by setting the Base Address Register. You can access SRAM from each G-Bus Master: the TX49/H3 core, DMAC0, DMAC1, PCI0, and PCI1. (1) 2 KB × 1 channel (2) Specifiable base address (3) Accessible in Byte, half-word, word, or double-word units (4) Supports Burst access1 (5) Supports the critical word first function of the TX49/H3 core 19.2 Block diagram On-chip SRAM G-Bus Memory G-Bus I/F 2 KB × 1 Figure 19.2.1 On-chip SRAM Block Diagram 1 On-chip SRAM does not support special Burst access (address decrementing/fixed) of DMAC0, DMAC1. 19-1 Chapter 19 On-Chip SRAM 19.3 Detailed explanation 19.3.1 Base address Specify the base address of the on-chip SRAM in 2-KB boundary units (specify the upper 25 bits of the physical address). Operation is not guaranteed if the address overlaps with an address space set by SDRAMC, EBUSC, etc. Physical Address Space 0x F_FFFF_FFFF SRBA SRAM Area 2 KB 0x 0_0000_0000 Figure 19.3.1 Base Address Specification 19.3.2 Access cycle count The following table shows the GBUSCLK cycle count required to access on-chip SRAM. Table 19.3.1 Access Cycle Count Access Type Single Read Single Write Burst Read Burst Write GBUSCLK Cycle Count (n= Burst Size (1-8)) 3 3 2+n 2+n 19-2 Chapter 19 On-Chip SRAM 19.4 Register 19.4.1 63 SRBA[35:20] R/W 0x0000 47 SRBA[19:11] R/W 000000000 31 SRSIZ[23:8] R 0x0008 15 SRSIZ[7:0] R 0x00 8 7 Reserved 1 0 CE R/W 0 : Type : Default : Type : Default 16 39 38 Reserved : Type : Default 32 : Type : Default On-chip SRAM Control Register (SRAMCR : 0x6000) 48 Bit(s) 63:39 Mnemonic SRBA [35:11] Field Name On-chip SRAM Base Address Description SRAM Base Address (Default: 0, R/W) This field specifies the base address of on-chip SRAM. The upper 25 bits [35:11] of the physical address are compared with the value of this field. A 2-KB physical address space with the base address SRBA0[35:11] is mapped to on-chip SRAM. SRAM Size (Default: 0x00_0800, R) Displays the on-chip SRAM size (2 Bytes). Channel enable (0 , R/W) This bit specifies whether to enable a channel. When using on-chip SRAM, set "1". 0: Disable 1: Enable 38:32 31:8 7:1 0 CE SRSIZ [23:0] Reserved On-chip SRAM Size Reserved Channel Enable Figure 19.4.1 On-Chip SRAM Control Register 19-3 Chapter 19 On-Chip SRAM 19-4 Chapter 20 NAND Flash Memory Controller 20. NAND Flash Memory Controller 20.1 Features The TX4938 has a built-in NAND Flash Controller (NDFMC). The NDFMC generates the control signals required to interface with NAND flash memory. Also, the NDFMC performs ECC calculation. The NAND Flash Controller has the following features. • • Indirect register access to NAND flash memory On-chip ECC calculation circuit 20.2 Block diagram G-Bus NAND Flash Controller (NDFMC) G-Bus I/F Register Register Address Decoder Host I/F timing Control NAND Flash Memory I/F Timing Control ND_CLE ND_ALE ND_CE* ND_RE* ND_WE* ND_RB* EBIF CONTROL EBIF DATA[7:0] BUSSPRT* Figure 20.2.1 NAND Flash Memory Controller Block Diagram 20-1 Chapter 20 NAND Flash Memory Controller 20.3 Detailed operation 20.3.1 Accessing NAND flash memory With the NDFMC, you can access NAND flash memory by controlling registers. The NDFMC also has an ECC calculation function. See 20.3.2 for more information on ECC. This subsection describes the procedure for accessing NAND flash memory. Basically, first set a command in the NDFMCR, then either read or write NDFDTR to access NAND flash memory. Reading NDFDTR executes a read cycle to external NAND flash memory. The read cycle to NDFDTR also ends when the read cycle to external NAND flash memory ends. Similarly, writing NDFDTR executes a write cycle to external NAND flash memory. The write cycle to NDFDTR also ends when the write cycle to external NAND flash memory ends. Note: When reading or writing NDFDTR, the ND_RE* or ND_WE* signal is asserted. The low pulse width and high-level time after the ND_RE* or ND_WE* signal is deasserted can be set in NDFSPR. Other signals are controlled by software to meet AC specifications of NAND flash memory to be used. Be aware of the following AC specifications. Time from ND_WE* High to assertion of ND_RB* Low. (After writing NDFDTR, wait tWB time before reading NDFSR.BUSY, then detect timing of ND_RB* assertion and deassertion. When NDFIMR.MRDY = 1 is set, NDFISR.RDY is set to 1 if ND_RB* changes from Low to High. You can detect deassertion of ND_RB* by checking this register.) tWB: tAR1: Time from ND_ALE Low to ND_RE* Low (ID read) (After writing NDFMCR.ALE to 0, wait tAR1 time and read NDFDTR.) tAR2: Time from ND_ALE Low to ND_RE* Low (Read cycle) (After writing NDFMCR.ALE to 0, wait tAR2 time and read NDFDTR.) 20.3.1.1 Initialization Following is the initialization sequence. 1. 2. NDFSPR (0x5028): Set the low pulse width. NDFIMR (0x5020): Set 0x81 to enable interrupts. 20-2 Chapter 20 NAND Flash Memory Controller 20.3.1.2 Write Following is the write sequence. 1. 2. 3. NDFMCR(0x5008): Set to 0x70 and initialize the ECC data of NDFMC. The NDFMC does not have a WP* signal. Use either PIO or an external circuit to set the WP* signal to “H”. 512-Byte write • • • • • • NDFMCR (0x5008 ): Set to 0x91, assert the ND_CLE* signal, then enter the Command mode. NDFDTR (0x5000): Write 0x80 (Serial Data Input command). NDFMCR (0x5008): Set to 0x92, assert the ND_ALE* signal, then enter the Address mode. NDFDTR (0x5000): NDFDTR (0x5000): Set A[7:0], A[16:9], A[24:17] (and A[25] if necessary) in order. Set 512-Byte data in order. NDFMCR (0x5008): Set to 0xb0 and enter the Data mode. 4. Read ECC data • • NDFMCR (0x5008): Set to 0xd0, and enter the ECC Data Read mode. NDFDTR (0x5000): Read the 6-Byte ECC data the NDFMC calculated. First data: Second data: Third data: Fourth data: Fifth data: Sixth data: LPR[7:0] LPR[15:8] CPR[5:0], 2’b11 LPR[23:16] LPR[31:24] CPR[11:6], 2’b11 5. Write 16-Byte redundant data • • NDFMCR (0x5008): Set to 0x90 and enter a Data mode that does not calculate ECC. NDFDTR (0x5000): Write 16-Byte redundant data. D520: LPR[23:16] D521: LPR[31:24] D522: CPR[11:6], 2’b11 D525: LPR[7:0] D526: LPR[15:8] D527: CPR[5:0], 2’b11 6. Execute a page program • • • • NDFMCR (0x5008): Set 0x91, assert the ND_CLE* signal, and enter the Command mode. NDFDTR (0x5000): Write 0x10 (Page Program command). NDFMCR (0x5008): Set 0x10 and deassert the ND_CLE* signal. NDFSR (0x5010): Check the BUSY flag. Proceed to the next step if “0”. Wait until the flag becomes “0” if it is “1”. 20-3 Chapter 20 NAND Flash Memory Controller 7. Read status • • • • 8. NDFMCR (0x5008): Set 0x11, assert the ND_CLE* signal, and enter the Command mode. NDFDTR (0x5000): Write 0x70 (Read Status command). NDFMCR (0x5008): Set 0x10 and deassert the ND_CLE* signal. NDFDTR (0x5000): Read the status data from NAND flash memory. Repeat steps 1-7 on the other pages. 20.3.1.3 Read Following is the read sequence. 1. 2. NDFMCR (0x5008): Set 0x70 and initialize the NDFMC ECC data. Read 512 bytes • • • • • • • • • • 3. • • NDFMCR (0x5008): Set 0x11, assert the ND_CLE* signal, and enter the Command mode. NDFDTR (0x5000): Write 0x00 (Read command). NDFMCR (0x5008): Set 0x12, assert the ND_ALE* signal, then enter the Address mode. NDFDTR (0x5000): Set A[7:0], A[16:9], A[24:17] (and if necessary A[25]) in order. NDFMCR (0x5008): Set 0x10, and deassert the ND_ALE* signal. NDFSR (0x5010): Check the BUSY flag. Proceed to the next step if it is “0”. Wait until it becomes “0” if it is “1”. NDFMCR (0x5008): Set 0x30, and enter a Data mode that performs ECC calculation. NDFDTR (0x5000): Read 512-Byte data. NDFMCR (0x5008): Set 0x10, and enter a Data mode that does not perform ECC calculation. NDFDTR (0x5000): Read 16-Byte redundant data. NDFMCR (0x5008): Set 0x50, and enter the ECC Data Read mode. NDFDTR (0x5000): First data: Second data: Third data: Fourth data: Fifth data: Sixth data: 4. 5. Read another page. • • • NDFMCR (0x5008): Set 0x10. NDFSR (0x5010): Check the BUSY flag. Proceed to the next step if “0”. Wait until it becomes “0” if it is “1”. Read the 6-Byte ECC data the NDFMC calculated. LPR[7:0] LPR[15:8] CPR[5:0], 2’b11 LPR[23:16] LPR[31:24] CPR[11:6], 2’b11 Read ECC data Compare the ECC data. If the data do not match, invoke the necessary error process. Repeat steps 1-4. However, when performing a sequential read, skip 2-1 through 2-5. 20-4 Chapter 20 NAND Flash Memory Controller 20.3.1.4 Read ID Following is the ID read sequence. 1. 2. 3. 4. 5. 6. 7. NDFMCR (0x5008): NDFDTR (0x5000): NDFMCR (0x5008): NDFDTR (0x5000): NDFMCR (0x5008): NDFDTR (0x5000): NDFDTR (0x5000): Set 0x11, assert the ND_CLE* signal, and enter the Command mode. Write 0x90 (ID Read command). Set 0x12, assert the ND_ALE* signal, and enter the Address mode. Write 0x00. Set 0x10, and enter a Data mode that does not calculate ECC. Read the maker code. Read the device code. 20.3.2 ECC control The NDFMC only performs ECC calculation. Use a program to check ECC for errors and correct any errors that occur. You can read from the NDFDTR Register the ECC data calculated by NDFMC by setting the NDFMCR to either 0xD0 (Write mode) or 0x50 (Read mode). The ECC data you can read is 6-Byte data. Read NDFDTR six times. Data is read in the following order. First data: Third data: Fourth data: Fifth data: Sixth data: LPR[7:0] CPR[5:0], 2’b11 LPR[23:16] LPR[31:24] CPR[11:6], 2’b11 Second data: LPR[15:8] 20-5 Chapter 20 NAND Flash Memory Controller 20.4 Registers Table 20.4.1 NDFMC Registers Offset Address 0x5000 0x5008 0x5010 0x5018 0x5020 0x5028 0x5030 Bit Width 64 64 64 64 64 64 64 Register Symbol NDFDTR NDFMCR NDFSR NDFISR NDFIMR NDFSPR NDFRSTR Register Name NAND Flash Memory Data Transfer Register NAND Flash Memory Mode Control Register NAND Flash Memory Status Register NAND Flash Memory Interrupt Status Register NAND Flash Memory Interrupt Mask Register NAND Flash Memory Strobe Pulse Width Register NAND Flash Memory Reset Register 20.4.1 63 NAND Flash Memory Data Transfer Register (NDFDTR) 0x5000 48 Reserved : Type : Default 47 Reserved 32 : Type : Default 31 Reserved : Type : Default 15 Reserved 8 7 DATA R/W ⎯ : Type : Default 0 16 Bits 63:8 7:0 Mnemonic ⎯ DATA Field Name Reserved DATA Description ⎯ Interrupt Detection Enable (Default: Undefined) NAND Flash memory data Read: Reads NAND flash data when in the Data mode. Write: Writes transmission data in NAND flash memory in each mode. Figure 20.4.1 NAND Flash Memory Data Transfer Register (NDFDTR) 20-6 Chapter 20 NAND Flash Memory Controller 20.4.2 63 Reserved : Type : Default 47 Reserved : Type : Default 31 Reserved : Type : Default 15 Reserved 8 7 WE R/W 0 6 ECC R/W 0 R/W 0 5 4 CE R/W 0 3 2 Reserved 1 ALE R/W 0 0 CLE R/W 0 : Type : Default 16 32 NAND Flash Memory Mode Control Register (NDFMCR) 0x5008 48 Bit(s) 63:8 7 Mnemonic ⎯ WE Field Name Reserved Write Enable Description ⎯ Write Enable (Default: 0) Enables data write operation. Set this bit when writing data to NAND flash memory. 0: Prohibit Write operation. 1: Enable Write operation. ECC Control (Default: 00) This field specifies the operation of the ECC calculation circuit. 11: Reset the ECC circuit. 00: Disable the ECC circuit. 01: Enable the ECC circuit. 10: Read the ECC circuit the NDFMC calculated. 6:5 ECC ECC Control 4 CE Chip Enable Chip Enable Default: 0) Enables access to NAND flash memory. Set this bit when accessing NAND flash memory. 0: Disable (ND_CE* high.) 1: Enable (ND_CE* low.) ⎯ Address Latch Enable (Default: 0) Specifies the ND_ALE* signal. 0: Low 1: High Command Latch Enable (Default: 0) Specifies the value of the NC_CLE signal. 0: Low 1: High 3:2 1 ⎯ ALE Reserved Address Latch Enable 0 CLE Command Latch Enable Figure 20.4.2 NAND Flash Memory Mode Control Register (NDFMCR) 20-7 Chapter 20 NAND Flash Memory Controller 20.4.3 63 Reserved : Type : Default 47 Reserved : Type : Default 31 Reserved : Type : Default 15 Reserved 8 7 BUSY R ⎯ 6 Reserved : Type : Default 0 16 32 NAND Flash Memory Status Register (NDFSR) 0x5010 48 Bit(s) 63:8 7 Mnemonic ⎯ BUSY Field Name Reserved BUSY Description ⎯ BUSY (Default: Undefined) Indicates the status of NAND flash memory. 0: Ready 1: Busy ⎯ 6:0 ⎯ Reserved Figure 20.4.3 NAND Flash Memory Status Register (NDFSR) 20-8 Chapter 20 NAND Flash Memory Controller 20.4.4 63 Reserved : Type : Default 47 Reserved : Type : Default 31 Reserved : Type : Default 15 Reserved 1 0 RDY R/W1C : Type NAND Flash Memory Interrupt Status Register (NDFISR) 0x5018 48 32 16 0 : Default Bit(s) 63:1 0 Mnemonic ⎯ RDY Field Name Reserved Ready Description ⎯ Ready (Default: 0) When the MRDY bit of the NDFIMR Register is "1", this bit is set to "1" when the ND_RB* signal changes from Low to High. Write "1" to clear this bit to "0". Read: 0: No change 1: ND_RB* signal changed from the Busy state to the Ready state. Write: 0: Don’t care 1: Clear to "0". Figure 20.4.4 NAND Flash Memory Interrupt Status Register (NDFISR) 20-9 Chapter 20 NAND Flash Memory Controller 20.4.5 63 Reserved : Type : Default 47 Reserved : Type : Default 31 Reserved : Type : Default 15 Reserved 8 7 INTEN R/W 0 6 Reserved 1 0 MRDY R/W : Type 0 : Default 16 32 NAND Flash Memory Interrupt Mask Register (NDFIMR) 0x5020 48 Bit(s) 63:8 7 Mnemonic ⎯ INTEN Field Name Reserved Interrupt Enable Description ⎯ Interrupt Enable (Default: 0) This bit enables interrupts. If both the MRDY bit of this register and this INTEN bit are set to "1", an interrupt occurs when the RDY bit of the NDFISR Register becomes "1". 0: Disable 1: Enable ⎯ Mask Ready Interrupt (Default: 0) This bit masks the RDY bit of the NDFISR Register. If this bit is "1", the RDY bit of the NDFISR Register is set when the ND_RB* signal changes from "0" to "1". 0: Disable the NDFISR RDY bit. 1: Enable the NDFISR RDY bit. 6:1 0 ⎯ MRDY Reserved Mask RDY interrupt Figure 20.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR) 20-10 Chapter 20 NAND Flash Memory Controller 20.4.6 63 Reserved : Type : Default 47 Reserved : Type : Default 31 Reserved : Type : Default 15 Reserved 8 7 HOLD R/W 1111 4 3 SPW R/W 1111 : Type : Default 0 16 32 NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0x5028 48 Bits 63:8 7:4 Mnemonic ⎯ HOLD Field Name Reserved Hold Time Description ⎯ Hold Time (Default: 1111) The DATA[7:0], ND_CLE, ND_ALE and ND_CE* outputs of the NAND Flash Controller are held constant for HOLDxGBUSCLK cycles from the deassertion of the ND_WE* signal. Note: This field affects the read timing. The BUSSPRT* signal is deasserted after HOLDxGBUSCLK cycles from the deassertion of the ND_RE* signal. 0000: Reserved 0001: 1xGBUSCLK 0010: 2xGBUSCLK 0011: 3xGBUSCLK 0100: 4xGBUSCLK 0101: 5xGBUSCLK 0110: 6xGBUSCLK 0111: 7xGBUSCLK 1000: 8xGBUSCLK 1001: 9xGBUSCLK 1010: 10xGBUSCLK 1011: 11xGBUSCLK 1100: 12xGBUSCLK 1101: 13xGBUSCLK 1110: 14xGBUSCLK 1111: 15xGBUSCLK Strobe Pulse Width (Default: 1111) Specifies the low pulse width of the ND_RE* signal and the ND_WE* signal. 0000: 1xGBUSCLK 0001: 2xGBUSCLK 0010: 3xGBUSCLK 0011: 4xGBUSCLK 0100: 5xGBUSCLK 0101: 6xGBUSCLK 0110: 7xGBUSCLK 0111: 8xGBUSCLK 1000: 9xGBUSCLK 1001: 10xGBUSCLK 1010: 11xGBUSCLK 1011: 12xGBUSCLK 1100: 13xGBUSCLK 1101: 14xGBUSCLK 1110: 15xGBUSCLK 1111: 16xGBUSCLK 3:0 SPW Strobe Pulse Width Figure 20.4.6 NAND Flash Memory Strobe Pulse Width Register (NDFSR) 20-11 Chapter 20 NAND Flash Memory Controller 20.4.7 63 Reserved : Type : Default 47 Reserved : Type : Default 31 Reserved : Type : Default 15 Reserved 1 0 RST R/W1C : Type NAND Flash Memory Reset Register (NDFRSTR) 0x5030 48 32 16 0 : Default Bit(s) 63:1 0 Mnemonic ⎯ RST Field Name Reserved Reset Description ⎯ Reset (Default: 0) Setting "1" to this bit resets NDFMC. After the reset (2 GBUSCLK cycles later), this bit is automatically cleared to "0". 0: Don’t care 1: Reset Figure 20.4.7 NAND Flash Memory Reset Register (NDFRSTR) 20-12 Chapter 20 NAND Flash Memory Controller 20.5 Timing diagram 20.5.1 Command cycles and address cycles NDFMCR.ALE = 0 ND_WE* remains deasserted for at least 6 GBUSCLK cycles. NDFSPR.HOLD NDFSPR.SPW NDFMCR.CLE = 0 NDFMCR.ALE = 1 NDFMCR.CLE = 1 NDFMCR.CE = 1 ND_CLE ND_ALE Figure 20.5.1 Command Cycles and Address Cycles 20-13 BUSSPRT* DATA[7:0] ND_CE* ND_RE* ND_WE* ND_RB* Chapter 20 NAND Flash Memory Controller 20.5.2 Data read cycles GBUSCLK ND_CLE ND_ALE ND_CE* ND_RE* NDFSPR.SPW=0x4 NDFSPR.HOLD=0x2 ND_WE* ND_RB* BUSSPRT* DATA[7:0] At least 6 GBUSCLK cycles TX4938 latches data from NAND flash. Figure 20.5.2 Data Read Cycles 20-14 Chapter 20 NAND Flash Memory Controller 20.5.3 Data write cycles GBUSCLK ND_CLE ND_ALE ND_CE* ND_WE* NDFSPR.SPW=0x3 NDFSPR.HOLD=0x2 ND_RE* ND_RB* BUSSPRT* DATA[7:0] At least 6 GBUSCLK cycles TX4938 places data on the bus. Figure 20.5.3 Data Write Cycles 20-15 Chapter 20 NAND Flash Memory Controller 20.6 NAND flash memory connection example Figure 20.6.1 shows an example connection of NAND flash memory. BUSSPRT* is asserted when you read NAND flash memory. When connecting NAND flash memory to a Data Bus that performs bidirectional control using BUSSPRT*, connect to the TX4938's DATA via a buffer as shown below. When not performing bidirectional control using BUSSPRT*, directly connect to the TX4938's DATA. TX4938 NAND Flash Memory ND_CLE ND_ALE ND_CE* ND_RE* ND_WE* ND_RB* CLE ALE CE* RE* W E* R/B* Flash ROM I/O[7:0] D[15:0] BUSSPRT* DATA[63:0] SDRAM DQ[63:0] Figure 20.6.1 Connection Example of NAND Flash Memory 20-16 Chapter 21 Extended EJTAG Interface 21. Extended EJTAG Interface 21.1 Extended EJTAG Interface The TX4938 Extended EJTAG (Enhanced Joint Test Action Group) Interface provides two real-time debugging functions. One is the IEEE1149.1 standard compliant JTAG Boundary Scan Test, and the other is the Debugging Support Unit (DSU) that is built into the TX49/H3 core. JTAG Boundary Scan Test • • IEEE1149.1 compatible TAP Controller Supports the following five instructions: EXTEST, SAMPLE/PRELOAD, IDCODE, BYPASS, HIGHZ Real-time Debugging • • • Real-time debugging using an emulation probe (made by Corelis or YDC) Execution control (run, break, step, register/memory access) Real-time PC tracing Please contact your local Toshiba Sales representative for more information regarding how to connect the emulation probe. The two functions of the Extended EJTAG Interface operate in one of two modes. PC Trace Mode • • Execution control (fun, pause, access single steps, access internal register/system memory) JTAG Boundary Scan Test Real-time Mode • Real-time PC tracing Refer to Section 3.1.11 for more information regarding signals used with the Extended EJTAG Interface. Table 21.1.1 EJTAG Interface Function and Operation Code PC Tracing Mode JTAG Boundary Scan Real-time Debugging Off Boundary Scan Test Execution Control On ⎯ Real-time PC Tracing 21-1 Chapter 21 Extended EJTAG Interface 21.2 JTAG Boundary Scan Test 21.2.1 JTAG Controller and Register The Extended EJTAG Interface contains a JTAG Controller (TAP Controller) and a Control Register. This section explains only those portions that are unique to the TX4938. Please refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for all other portion not covered here. Please contact your local Toshiba Sales representative for more information regarding the required BSDL files when performing the JTAG Boundary Scan Test. • • Instruction Register (Refer to 21.2.2) Data Register • • • • • • • • Boundary Scan Register (Refer to 21.2.3) Bypass Register Device ID Register (Refer to 21.2.4) JTAG Address Register JTAG Data Register JTAG Control Register EJTAG Mount Register Test Access Port Controller (TAP Controller) (Refer to 21.3) 21-2 Chapter 21 Extended EJTAG Interface 21.2.2 Instruction Register The JTAG Instruction Register consists of an 8-bit shift register. This register is used for selecting either one or both of the test to be performed and the Test Data Register to be accessed. The Data Register is selected according to the instruction code in Table 21.2.1. Refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for more information regarding each instruction. Table 21.2.1 Bit Configuration of JTAG Instruction Register Instruction Code MSB → LSB 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) 00000011 (0x03) 00000100 - 00001111 00010000 (0x10) 00010001 - 01111111 10000000 - 11111110 11111111 (0xFF) Instruction EXTEST SAMPLE/PRELOAD Reserved IDCODE Reserved HIGHZ Reserved BYPASS Selected Data Register Boundary Scan Register Boundary Scan Register Reserved Device ID Register Reserved Bypass Register Reserved Bypass Register Refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” Figure 21.2.1 shows the format of the Instruction Register. 7 MSB 6 5 4 3 2 1 0 LSB Figure 21.2.1 Instruction Register The instruction code is shifted to the Instruction Register starting from the Least Significant Bit. MSB TDI LSB TDO Figure 21.2.2 Shift Direction of the Instruction Register 21.2.3 Boundary Scan Register The Boundary Scan Register contains a single 391-bit shift register to which all TX4938 I/O signals except for power supply, TDI, TCK, TDO, TMS, TRST*, and TEST[4]* are connected. Figure 21.2.3 shows the bits of the Boundary Scan Register. 390 Refer to TX4938 BSDL file 0 Figure 21.2.3 Boundary Scan Register TDI input is fetched to the Most Significant Bit (MSB) of the Boundary Scan Register and the Least Significant Bit (LSB) of the Boundary Scan Register is sent from the TDO output. Table 21.2.2 shows the boundary scan sequence relative to the processor signals. 21-3 Chapter 21 Extended EJTAG Interface Table 21.2.2 TX4938 Processor JTAG Scan Sequence (1/2) JTAG Scan Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal Name TDI PIO[2] PIO[1] BYPASSPLL* SD[1] ACK* BUSSPRT* PIO[0] SWE* ACE* CE[6]* CE[7]* CE[0]* CE[2]* CE[5]* CE[1]* CE[3]* DMADONE* DMAREQ[3] CE[4]* DMAACK[3] DMAACK[2] DMAREQ[2] DMAACK[1] DMAREQ[1] DMAREQ[0] DMAACK[0] BWE[3]* BWE[0]* BWE[2]* BWE[1]* EEPROM_DI DCLK TPC[1] TPC[2] TPC[3] EEPROM_DO EEPROM_SK PCST[6] PCST[7] PCST[8] PCST[5] PCST[4] JTAG Scan Sequence 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Signal Name EEPROM_CS PCST[3] PCST[2] PCST[1] PCST[0] PCIAD[0] PCIAD[2] PCIAD[1] PCIAD[3] PCIAD[5] PCIAD[6] PCIAD[4] PCIAD[7] C_BE[0] PCIAD[8] PCIAD[9] PCIAD[11] PCIAD[12] PCIAD[15] M66EN PCIAD[13] PCIAD[10] C_BE[1] PAR PERR* PCIAD[14] SERR* LOCK* STOP* IRDY* DEVSEL* FRAME* C_BE[2] PCIAD[22] TRDY* PCIAD[17] PCIAD[16] C_BE[3] PCIAD[28] PCIAD[21] PCIAD[18] PCIAD[27] ID_SEL JTAG Scan Sequence 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Signal Name PCIAD[20] PCIAD[19] PCIAD[26] PCIAD[31] PCIAD[29] PCIAD[23] PCIAD[25] PCIAD[24] PCIAD[30] PCICLK[0] GNT[0]* REQ[1]* GNT[1]* PCICLK[1] REQ[0]* PCICLK[2] REQ[2]* GNT[2]* PCICLK[3] REQ[3]* GNT[3]* PME* PCICLK[4] DATA[63] PCICLK[5] PCICLKIN CGRESET* MASTERCLK DATA[31] DATA[62] DATA[30] DATA[61] DATA[29] DATA[60] DATA[59] DATA[27] DATA[28] DATA[58] DATA[26] DATA[57] DATA[56] DATA[24] DATA[25] 21-4 Chapter 21 Extended EJTAG Interface Table 21.2.2 TX4938 Processor JTAG Scan Sequence (2/2) JTAG Scan Sequence 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Signal Name DATA[55] DATA[54] DATA[22] DATA[53] DATA[23] DATA[21] DATA[52] DATA[50] DATA[20] DATA[48] CB[3] DATA[51] DATA[19] DQM[7] DATA[17] CB[2] CB[7] DATA[49] DATA[18] SDCS[3]* DQM[2] DATA[16] CB[6] DQM[6] DQM[3] SDCLK[1] ADDR[17] CKE SDCS[2]* SDCLK[3] ADDR[18] ADDR[19] ADDR[15] ADDR[16] ADDR[14] SDCLKIN SDCLK[0] SDCLK[2] ADDR[12] ADDR[13] ADDR[10] ADDR[11] ADDR[9] JTAG Scan Sequence 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 Signal Name ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[2] ADDR[1] ADDR[3] ADDR[0] RAS* SDCS[1]* DQM[5] DQM[1] SDCS[0]* DQM[4] WE* CAS* CB[5] DQM[0] CB[1] CB[4] DATA[47] CB[0] DATA[12] DATA[42] DATA[46] DATA[15] DATA[40] DATA[44] DATA[14] DATA[9] DATA[13] DATA[45] DATA[11] DATA[7] DATA[43] DATA[41] DATA[10] DATA[39] DATA[8] DATA[4] DATA[37] DATA[6] JTAG Scan Sequence 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Signal Name DATA[38] DATA[36] DATA[5] DATA[34] DATA[3] DATA[33] DATA[35] DATA[2] DATA[1] DATA[0] DATA[32] WDRST* OE* SYSCLK TEST[1]* RESET* TEST[0]* SCLK HALTDOZE TXD[1] TXD[0] RTS[1]* RTS[0]* CTS[1]* RXD[1] CTS[0]* INT[5] INT[4] INT[3] INT[2] INT[1] TCLK RXD[0] INT[0] NMI* TIMER[0] PIO[7] TIMER[1] PIO[6] PIO[5] PIO[4] PIO[3] TDO 21-5 Chapter 21 Extended EJTAG Interface 21.2.4 Device ID Register The Device ID Register is a 32-bit shift register. This register is used for reading the ID code that expresses the IC manufacturer, part number, and version from the IC and sending it to a serial device. The following figure shows the configuration of the Device ID Register. 31 28 27 0 0 0 0 0 Product Number 000001 16 bits 0 0 1 1 12 11 1 0 0 Manufacturer ID Code 0000110 11 bits 0 1 0 0 1 1 Version 0001 4 bits Figure 21.2.4 Device ID Register The device ID code for the TX4938 is 0x10027031. However, the four top bits of the Version field may be changed. The device ID code is shifted out from the Least Significant Bit. MSB …… LSB TDO Figure 21.2.5 Shift Direction of the Device ID Register 21-6 Chapter 21 Extended EJTAG Interface 21.3 Initializing the Extended EJTAG Interface The Extended EJTAG Interface is not reset by asserting the RESET* signal. Operation of the TX49/H3 core is not guaranteed if the Extended EJTAG Interface is not reset. This interface is initialized by either of the following methods. • • Assert the TRST* signal. (TRST* signal is pulled down (by ex. 10 kΩ)) After clearing the processor reset, set the TMS input to High for five consecutive rising edges of the TCK input. The reset state is maintained if TMS is able to maintain the High state. The above methods must be performed while the MASTERCLK signal is being input. The G-Bus Time Out Detection function is disabled when the TRST* signal is deasserted. (Refer to Section 5.1.1.) 21-7 Chapter 21 Extended EJTAG Interface 21-8 Chapter 22 Electrical Characteristics 22. Electrical Characteristics 22.1 Absolute maximum rating (*1) Item Supply Voltage (for I/O pins) Supply Voltage (for internal circuits) Input Voltage (*2) Storage Temperature Symbol VCCIOMax VCCIntMax VIN TSTG −0.3 - 3.9 −0.3 - 3.0 Rating Unit V V V °C −0.3 - VCCIO + 0.3V −40 - +125 (*1) The absolute maximum rating is a rating that must not be exceeded even for an instant even by a single item. Exceeding the absolute maximum rating may cause component damage or degradation, and may result in damage or combustion that causes bodily harm. When designing application devices, be absolutely sure that this absolute maximum rating is never exceeded. (*2) Even with VCCIO + 0.3 V, be sure to never exceed the VCCIOMax maximum rating. 22.2 Recommended operating conditions Item Supply Voltage I/O Internal Circuit Symbol VCCIO VCCInt TC Condition Min. 3.1 1.4 0 Max. 3.5 1.6 70 Unit V V °C Operating Temperature (Package Temperature) (*3) A recommended operating condition is a usage condition that Toshiba recommends for a product to function properly and maintain a uniform level of quality. Using a product such that even one item is not under the recommended operating conditions may cause a malfunction to occur. When designing application devices, be sure that these recommended operating conditions ranges are never exceeded. 22-1 Chapter 22 Electrical Characteristics 22.3 DC characteristics 22.3.1 DC characteristics of pins other than PCI Interface pins (Tc = 0 - 70°C, VddIO = 3.3V ± 0.2V, VCCInt = 1.5V ± 0.1V, VSS = 0V) Item Low-level Input Voltage High-level Input Voltage Low-level Output Current Low-level Output Current High-level Output Current High-level Output Current Low-level Input Leak Current High-level Input Leak Current Hi-Z Output Leak Current Operating Current (Internal) Symbol VIL1 VIH1 IOL1 IOL2 IOL3 IOL4 IOH1 IOH2 IOH3 IOH4 IIL1 IIL2 IIH1 IOZ ICCInt (1) (1) Condition Min. −0.3 2.0 8 4 16 8 ⎯ ⎯ ⎯ ⎯ −10 −200 −10 −10 ⎯ Max. 0.8 VCCIO + 0.3 ⎯ ⎯ ⎯ ⎯ −8 −4 −16 −8 10 −10 10 10 500 Unit V V mA mA mA mA mA mA mA mA µA µA µA µA mA (2)VOL = 0.4 V (3)VOL = 0.4 V (4)VOL = 0.4 V (5)VOL = 0.4 V (2)VOH = 2.4 V (3)VOH = 2.4 V (4)VOH = 2.4 V (5)VOH = 2.4 V (6)VIN=VSS (7)VIN=VSS (8)VIN=VCCIO (9) VddIN = 1.6 V, Internal core frequency = 300 MHz VddIO = 3.5 V, External bus frequency = 100 MHz Pin capacitance load = 25 pF Operating Current (I/O Pin) ICCIO ⎯ 400 mA (1) : All input pins except for the PCI interface signal pins, and all bidirectional pins (during input) (2) : ACE*, ACK*, BUSSPRT*, BWE[3:0]*, CE[7:0]*, DMAACK[3:0], DMADONE*, WDRST*, HALTDOZE, PIO[7:0], RTS[1:0], SWE*, SYSCLK, TIMER[1:0] and TXD[1:0] (3) : DCLK, PCST[8:0], TDO and TPC[3:1] (4) : ADDR[19:0], CAS*, CB[7:0], CKE, DATA[63:0], DQM[7:0], OE*, RAS*, SDCLK[3:0], SDCLKIN, SDCS[3:0]*, and WE* when drive capacity is set to 16 mA. (5) : ADDR[19:0], CAS*, CB[7:0], CKE, DATA[63:0], DQM[7:0], OE*, RAS*, SDCLK[3:0], SDCLKIN, SDCS[3:0]*, and WE* when drive capacity is set to 8 mA. (6) : CGRESET*, RESET*, TRST*, BYPASSPLL*, MASTERCLK, SDCLKIN and SDIN[1] (7) : CTS[1:0]*, DMAREQ[3:0], DMADONE*, RXD[1:0], SCLK, TCLK, INT[5:0], TCK, TDI, TEST[4:0]*, TMS, ACK*, CB[7:0], DATA[63:0], ADDR[19:0], NMI* and PIO[7:0] (8) : Signal in (6) and (7) above (9) : DCLK, TDO 22-2 Chapter 22 Electrical Characteristics 22.3.2 DC characteristics of PCI Interface pins (Tc = 0 – 70°C, VddIO = 3.3 V ± 0.2 V, VddIN = 1.5 V ± 0.1 V, VSS = 0 V) Item Low-level Input Voltage High-level Input Voltage High-level Output Voltage Low-level Output Voltage High-level Output Current Low-level Output Current Input Leak Current High-level Input Leak Current Low-level Input Leak Current Hi-Z Output Leak Current Symbol VILPCI VIHPCI VOHPCI VOLPCI IOH1 IOL1 IIHPCI IILPCI IIL1 IIL2 IOZPCI (1) (1) Conditions Min. −0.5 1.8 VddIO × 0.9 ⎯ ⎯ 8 −10 −10 −10 −200 −10 Max. 0.9 VddIO + 0.3 ⎯ VddIO × 0.1 -8 ⎯ 10 10 10 −10 10 Unit V V V V mA mA µA µA µA µA µA (2) IOUT = −500 µA (2) IOUT = 1500 µA (4) VOH = 2.4 V (4) VOL = 0.4 V 0 < VIN < VddIO (5) VIN = VddIO (5) VIN = VSS (3) (1) : ID_SEL, PCICLKIN, C_BE[3:0], DEVSEL*, FRAME*, GNT[3:0]*, IRDY*, LOCK*, M66EN, PAR, PCIAD[31:0], PERR*, PME*, REQ[3:0], SERR*, STOP*, TRDY* (2) : All PCI interface signals except for ID_SEL, LOCK*, PCICLKIN (3) : PME*, REQ[1], SERR* (4) : EEPROM_CS, EEPROM_DO, EEPROM_SK (5) : EEPROM_DI 22-3 Chapter 22 Electrical Characteristics 22.4 PLL power 22.4.1 PLL power connection example Place C1, C2, C3, R, and L as close to the TX4938 as possible. TX4938 VddInt L R VddPLL2_A VddPLL1_A C1 C2 C3 VddInt R L C3 C2 C1 VssPLL2_A L R VSS VssPLL1_A R VSS L Item Resistance Inductance Condensor (capacitance) Symbol R L C1 C2 C3 Recommended Value 5.6 2.2 1 82 10 1.5 ± 0.1 Unit Ω µH NF NF µF V VddInt / VddPLL Note that the above values are recommended values. Figure 22.4.1 Oscillation Circuit 22-4 Chapter 22 Electrical Characteristics 22.5 AC characteristics 22.5.1 MASTERCLK AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item MASTERCLK Cycle Symbol tMCP Conditions Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L Min. 7.5 30 12.5 3.125 2 2 Max. 80 320 133.3 33.3 ⎯ ⎯ Unit ns ns MHz MHz ns ns MHz ns ns MASTERCLK Frequency *1) fMCK Boot configuration ADDR[2]=H Boot Configuration ADDR[2]=L MASTERCLK High Time MASTERCLK Low Time CPUCLK Frequency MASTERCLK Rise Time MASTERCLK Fall Time tMCH tMCL fCPU tMCR tMCF TMPR4938XBG-300 TMPR4938XBG-333 50 50 ⎯ ⎯ 300 333 1.5 1.5 *1) TX4938 operation is only guaranteed when the power is stable, PLL secures the PLL oscillation stability time tMCP_PLL and is in the Enable state. tMCP MASTERCLK 0.8 VCC 0.2 VCC tMCR tMCF tMCL tMCH Figure 22.5.1 Timing Diagram: MASTERCLK 22.5.2 Power on AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item Symbol tMCP_PLL fMCK_PLL tMCH_PLL Conditions Min. 10 1 1 Max. Unit ms ms PLL Oscillation Stability Time CGRESET* W idth Time RESET* W idth Time VCCInt, VCCIO *1) PLL_Vdd1_A, PLL_Vdd2_A MASTERCLK ⎯ ms MASTERCLK Oscillation Stability Time tMCP_PLL CGRESET* tMCK_PLL tMCH_PLL RESET* *1) VCCInt and VCCIO must start up simultaneously, or VCCInt must be first. The difference of the stand up time of a power supply within in 100 m seconds. Figure 22.5.2 Timing Diagram: Power On Reset 22-5 Chapter 22 Electrical Characteristics 22.5.3 SDRAM Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V, CL = 150 pF) Item SDCLK[3:0] Cycle Time SDCLK[3:0] High Time SDCLK[3:0] Low Time SDCLKIN Input Skew ADDR[19:5] Output Delay SDCS[3:0]* Output Delay RAS* Output Delay CAS* Output Delay W E* Output Delay CKE Output Delay DQM[7:0] Output Delay DATA[63:0] Output Delay (H→L, L→H) Symbol tCYC_SDCLK tHIGH_SDCLK tLOW_SDCLK tBP tVAL_ADDR1 tVAL_SDCS tVAL_RAS tVAL_CAS tVAL_WE tVAL_CKE tVAL_DQM tVAL_DATA1 Conditions CL=50 pF, 16 mA buffer time CL=50 pF, 16 mA buffer time CL=50 pF, 16 mA buffer time W hen in the Non-bypass mode *4) CL=150 pF, 16 mA buffer, *1) CL= 80 pF, 16 mA buffer, *1) CL= 80 pF, 16 mA buffer CL=150 pF, 16 mA buffer, *1) CL= 80 pF, 16 mA buffer, *1) CL=150 pF, 16 mA buffer, *3) CL= 80 pF, 16 mA buffer, *3) CL=150 pF, 16 mA buffer, *3) CL= 80 pF, 16 mA buffer, *3) CL=150 pF, 16 mA buffer CL= 80 pF, 16 mA buffer CL= 50 pF, 16 mA buffer, *2) CL= 30 pF, 16 mA buffer, *2) CL= 50 pF, 16 mA buffer, *2) CL= 30 pF, 16 mA buffer, *2) CL= 50 pF, 16 mA buffer, *2) CL= 30 pF, 16 mA buffer, *2) CL= 50 pF, 16 mA buffer, *2) CL= 30 pF, 16 mA buffer, *2) W hen in the Bypass mode W hen in the Bypass mode W hen in the Non-bypass mode W hen in the Non bypass mode Min. 7.5 2.5 2.5 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 4.0 0.5 1.0 1.0 Max. ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCYC_SDCLK – 5.5 6.5 5.2 5.2 6.5 5.2 6.5 5.2 6.5 5.2 6.5 5.2 6.5 5.2 6.5 5.2 6.5 5.2 6.5 5.2 ⎯ ⎯ ⎯ ⎯ DATA[63:0] Output Delay (Valid → Hi-Z) tVAL_DATA1ZV DATA[63:0] Output Delay (Valid→Hi-Z) tVAL_DATA1VZ DATA[63:0] Input Setup Time DATA[63:0] Input Hold Time DATA[63:0] Input Setup Time DATA[63:0] Input Hold Time tSU_DATA1B tHO_DATA1B tSU_DATA1NB tHO_DATA1NB *1) Becomes a 2-cycle signal when tDACT of SDCTR1 is “1”. *2) Becomes a 2-cycle signal when tSWB of SDCTR1 is “1”. *3) 2-cycle signal For information on 2-cycle operation, see the description in Chapter 9 SDRAM Controller. *4) The MAX value is is tCYC_SDCLK – 5.5 ns. SDCLK[n] tVAL_* OUTPUT tSU_* INPUT tHO_* inputs valid outputs valid Figure 22.5.3 Timing Diagram: Output Signal and Input Signal when in the Bypass Mode (SDCLK Reference) 22-6 Chapter 22 Electrical Characteristics SDCLK[n] tBP SDCLKIN tSU_* INPUT inputs valid tHO_* Figure 22.5.4 Timing Diagram: Input Signal when in the Non-bypass Mode (SDCLK Reference) 22-7 Chapter 22 Electrical Characteristics 22.5.4 External Bus Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item SYSCLK Cycle Time SYSCLK High Time SYSCLK Low Time ADDR[19:5] Output Delay CE[7:0]* Output Delay OE* Output Delay SWE* Output Delay BWE[3:0]* Output Delay ACE Output Delay BUSSPRT* Output Delay DATA[63:0] Output Delay (H→L, L→H) DATA[31:0] Output Delay (Hi-Z→Valid) DATA[31:0] Ouput Delay (Valid→Hi-Z) DATA[31:0] Input Setup Time DATA[31:0] Input Hold Time ACK* Output Delay (H→L, L→H) ACK* Output Delay (Hi-Z→Valid) ACK* Output Delay (Valid→Hi-Z) ACK* Input Setup Time ACK* Input Hold Time Symbol tCYC_SYSCLK tLOW_SYSCLK tVAL_ADDR2 tVAL_CE tVAL_OE tVAL_SWE tVAL_BWE tVAL_ACE tVAL_DQM tVAL_BUS tVAL_DATA2ZV tVAL_DATA2VZ tSU_DATA2 tHO_DATA2 tVAL_ACK tVAL_ACKZV tVAL_ACKVZ tSU_ACK tHO_ACK Condition Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA For CL=150 pF, 16 mA buffer Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA For CL=50 pF, 16 mA buffer For CL=50 pF, 16 mA buffer For CL=50 pF, 16 mA buffer Min. 7.5 4 4 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 6.0 0.5 Max. ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tHIGH_SYSCLK Buffer fixed: CL=50 pF, 8 mA 6.5 8.5 8.5 8.5 8.5 8.5 8.5 6.5 *1) 8.5 8.5 ⎯ ⎯ Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA Buffer fixed: CL=50 pF, 8 mA 1.5 1.5 1.5 6.0 0.5 8.5 8.5 8.5 ⎯ ⎯ *1) When the speed of the External Bus is set to 1/3 speed, the delay becomes the GBUSCLK cycle + 6.5 ns. EBCCRn.SP of the External Bus Controller sets the speed of the External Bus. tCYC_SYSCLK tHIGH_SYSCL SYSCLK tVAL_* OUTPUT tSU_* INPUT inputs valid tHO_* outputs valid tLOW_SYSCL Figure 22.5.5 Timing Diagram: External Bus Interface 22-8 Chapter 22 Electrical Characteristics 22.5.5 PCI Interface AC characteristics (66 MHz) (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item PCICLKIN Cycle Time (66 MHz) PCICLKIN High Time (66 MHz) PCICLKIN Low Time (66 MHz) PCICLKIN Slew Rate (66 MHz) PCICLK[5:0] Cycle Time (66 MHz) PCICLK[5:0] High Time (66 MHz) PCICLK[5:0] Low Time (66 MHz) PCICLK[5:0] Skew (66 MHz) PCI Output Signal*1) Output Delay PCI Input Signal*2) Input Setup Time PCI Input Signal*2) Input Hold Time ID_SEL, REQ[0]*, GNT[3:0]* Output Delay ID_SEL, REQ[3:0]*, GNT[0]* Input Setup Time ID_SEL, REQ[3:0]*, GNT[0]* Input Hold Time Symbol tCYC66 tHIGH66 tLOW66 tSLEW66 tCYCO66 tHIGHO66 tLOWO66 tSKEW tVAL66 tSU66 tHO66 tVALPP66 tSUPP66 tHOPP66 Conditions Min. 15 6 6 1.5 Max. 30 ⎯ ⎯ Unit ns ns ns V/ns ns ns ns ns ns ns ns ns ns ns 4 30 ⎯ ⎯ CL=50 pF CL=50 pF CL=50 pF CL=50 pF, point to point connect CL=30 pF 15 6 6 0 2 3 0.5 1 8 ⎯ ⎯ CL=30 pF, point-to-point connect Point-to-point connection Point-to-point connection 2 5 0 8 ⎯ ⎯ *1) PCIAD[31:0], C_BE[3:0], PAR, FRAME*, IRDY*, TRDY*, STOP*, DEVSEL*, PERR*, SERR*, M66EN, and PME* *2) PCIAD[31:0] , C_BE[3:0] , PAR, FRAME*, IRDY*, TRDY*, STOP*, DEVSEL*, PERR*, SERR*, M66EN, PME*, LOCK*, and ID_SEL 22.5.6 PCI Interface AC characteristics (33 MHz) (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item Symbol tCYC33 tHIGH33 tLOW33 tSLEW33 tCYC33 tHIGH33 tLOW33 tSKEW tVAL33 tSU33 tHO33 tVALPP33 tSUPP33 tHOPP33 CL=70 pF, point to point connect point to point connct point to point connect CL=70 pF CL=70 pF CL=70 pF CL=70 pF, point to point connect CL=70 pF Condition Min. 30 11 11 1 30 11 11 0 2 7 0.5 2 10 0 Max. 40 ⎯ ⎯ Unit ns ns ns V/ns ns ns ns ns ns ns ns ns ns ns PCICLKIN Cycle Time (33 MHz) PCICLKIN High Time (33 MHz) PCICLKIN Low Time (33 MHz) PCICLKIN Slew Rate (33 MHz) PCICLK[5:0] Cycle Time (33 MHz) PCICLK[5:0] High Time (33 MHz) PCICLK[5:0] Low Time (33 MHz) PCICLK[5:0] Skew (33 MHz) PCI Output Signal*1) Output Delay PCI Input Signal*2) Input Setup Time PCI Input Signal*2) Input Hold Time ID_SEL, REQ[0]*, GNT[3:0]* Output Delay ID_SEL, REQ[3:0]*, GNT[0]* Input Setup Time ID_SEL, REQ[3:0]*, GNT[0]* Input Hold Time 4 40 ⎯ ⎯ 2 11 ⎯ ⎯ 12 ⎯ ⎯ *1) PCIAD[31:0], C_BE[3:0] , PAR, FRAME*, IRDY*, TRDY*, STOP*, DEVSEL*, PERR*, SERR*, M66EN, and PME* *2) PCIAD[31:0] , C_BE[3:0] , PAR, FRAME*, IRDY*, TRDY*, STOP*, DEVSEL*, PERR*, SERR*, M66EN, PME*, LOCK*, and ID_SEL 22-9 Chapter 22 Electrical Characteristics tCYC66 / tCYC33 tHIGH66 / tHIGH33 0.6 Vcc 0.5 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc (Vcc=3.3V) tLOW66 / tLOW33 tSLEW66 / tSLEW33 0.4 Vcc p-to-p (minimum) PCICLKIN tsu66 / tsu33 / tSUPP66/tSUPP33 tHO66 / tHO33 / tHOPP66 / tHOPP33 INPUT inputs valid tVAL66 / tVAL33 / tVALPP66 / tVALPP33 OUTPUT outputs valid Figure 22.5.6 Timing Diagram: PCI Interface (3.3 V) tCYCO66 / tCYCO33 tHIGHO66 / tHIGHO33 tLOWO66 / tLOWO33 PCICLK[n] tSKEW PCICLK[except n] n=0∼5 Figure 22.5.7 Timing Diagram: PCI Clock Skew 22-10 Chapter 22 Electrical Characteristics 22.5.7 PCI EEPROM Interface AC characteristics (Tc = 0 ~ 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item EEPROM_SK High Time EEPROM_SK Low Time EEPROM_DO Output Delay Time EEPROM_DI Input Setup Time EEPROM_DI Input Hold Time EEPROM_CS Output Delay Time *1) Symbol tHIGH_EPSK tLOW_EPSK tVAL_EPDO tSU_EPDI tHO_EPDI tVAL_CS Conditions CL=50 pF CL=50 pF CL=50 pF Min. 500 500 ⎯ 100 100 Max. ⎯ ⎯ 100 ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns CL=50 pF 100 *1) The TX4938 controls EEPROM and its control signal synchronous to the falling edge of EEPROM_SK. Since the EEPROM operates at the rising edge of EEPROM_SK, you do not have to take the MIN side of EEPROM_DO into account. tHIGH_EPSK tLOW_EPSK EEPROM_SK EEPROM_DO tVAL_EPDO EEPROM_DI tSU_EPDI EEPROM_CS tHO_EPDI tVAL_EPCS Figure 22.5.8 Timing Diagram: PCI EEPROM Interface 22.5.8 DMA Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item Symbol tVAL_DONE tPW_DONE Conditions CL=50 pF SYSCLK (CL=50 pF) reference Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L tPW_DONE Min. ⎯ tMCP × 1.1 1/4 × tMCP × 1.1 Max. 12 ⎯ ⎯ Unit ns ns ns DMADONE* Delay DMADONE* Input Pulse Width Time DMADONE* SYSCLK tVAL_DONE DMADONE* Figure 22.5.9 Timing Diagram: DMA Interface 22-11 Chapter 22 Electrical Characteristics Notes: (1) DMAREQ[n] Edge Detection: Set the pulse width to 1.1× the GBUSCLK cycle or higher. Level Detection: There is no AC characteristic definition. Continue asserting DMAREQ[3:0] until DMAACK[3:0] is received. (2) DMAACK[n] The DMAACK[n] signal is synchronous to SDCLK. (It is driven by GUBSCLK inside the chip. See Chapter 6 for more information.) The DMAACK[n] signal is asserted by SYSCLK or SDCLK for 3 cycles or more. However, this is changed by the conditions [1] and [2] below. [1] [2] DMAC transfer mode (Single Address transfer, Dual Address transfer) Access time of the device DMAC accesses SDCLK[n] DMAACK[n] Assertion Time • • W hen driving an external device with SYSCLK Is asserted by SYSCLK for at least 3 cycles even in the shortest assertion case. W hen driving an external device with SDCLK Is asserted by SDCLK for at least 3 cycles even in the shortest assertion case. The AC characteristics for Single Address transfer with SDRAM are tight, so we do not recommend Single Address transfer. (3) DMADONE* Is asserted for only 1 SYSCLK cycle synchronous to SYSCLK. 22.5.9 Interrupt Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item Symbol tPW_INT Conditions Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L Min. 2 × tMCP × 1.1 1/2 × tMCP × 1.1 tMCP × 1.1 1/4 × tMCP × 1.1 Max. ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns INT Input Pulse Width Time NMI Input Pulse Width Time tPW_NMI Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L tPW_INT/tPW_NMI Figure 22.5.10 Timing Diagram: INT/NMI Interface 22-12 Chapter 22 Electrical Characteristics 22.5.10 SIO Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item SCLK Cycle time Symbol fCYC_SCLK Conditions Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L Min. 4 × tMCP × 1.1 tMCP × 1.1 ⎯ ⎯ 2 × tMCP × 1.1 1/2 × tMCP × 1.1 2 × tMCP × 1.1 1/2 × tMCP × 1.1 Max. ⎯ ⎯ 1/2 × fMCK × 0.45 2 × fMCK × 0.45 ⎯ ⎯ ⎯ ⎯ Unit ns ns MHz MHz ns ns ns ns SCLK Frequency fSCLK Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L SCLK High Time tHIGH_SCLK Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L SCLK Low Time tLOW_SCLK Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L tHIGH_SCLK SCLK tLOW_SCLK tCYC_SCLK/fSCLK Figure 22.5.11 Timing Diagram: SIO Interface 22.5.11 Timer Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item TCLK Cycle Time Symbol fCYC_TCLK Conditions Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L Min. 4 × tMCP × 1.1 tMCP × 1.1 ⎯ ⎯ 2 × tMCP × 1.1 1/2 × tMCP × 1.1 2 × tMCP × 1.1 1/2 × tMCP × 1.1 Max. ⎯ ⎯ 1/2 × fMCK × 0.45 2 × fMCK × 0.45 ⎯ ⎯ ⎯ ⎯ Unit ns ns MHz MHz ns ns ns ns TCLK Frequency fTCLK Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L TCLK High Time tHIGH_TCLK Boot configuration ADDR[2]=H Boot configuration ADDR[2]=L TCLK Low Time tLOW_TCLK Boot Configuration ADDR[2]=H Boot configuration ADDR[2]=L tHIGH_TCLK TCLK tLOW_TCLK tCYC_TCLK/fTCLK Figure 22.5.12 Timing Diagram: Timer Interface 22-13 Chapter 22 Electrical Characteristics 22.5.12 PIO Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item PIO[15:0] Output Delay Time PIO[15:0] Input Setup Time PIO[15:0] Input Hold Time Symbol tVAL_PIO tSU_PIO tHO_PIO Conditions IMBUSCLK reference (CL=50 pF) IMBUSCLK reference IMBUSCLK Reference Min. ⎯ 12 0 Max. 10 ⎯ ⎯ Unit ns ns ns *1) IMBUSCLK is an internal signal. For more details, see Chapter 6 Clocks. MASTERCLK IMBUSCLK (output) tVAL_PIO (input) tSU_PIO tHO_PIO Figure 22.5.13 Timing Diagram: PIO Interface 22.5.13 AC-link Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item BITCLK High Time BITCLK Low Time SYNC Output Delay Time SDOUT Output Delay Time SDIN[1:0] Input Setup Time SDIN[1:0] Input Hold Time Symbol tHIGH_BCLK tLOW_BCLK tVAL_SYNC tVAL_SDOUT tSU_DSIN tHO_DSIN Condition Min. 36 36 Max. 45 45 15 15 ⎯ ⎯ Unit ns ns ns ns ns ns BITCLK reference, CL = 55 pF BITCLK reference, CL = 55 pF BITCLK reference BITCLK reference ⎯ ⎯ 10 10 BITCLK tHIGH_BCLK SYNC tVAL_SYNC SDOUT tVAL_SDOUT SDIN tSU_SDIN tHO_SDIN tVAL_SYNC tLOW_BCLK Figure 22.5.14 Timing Diagram: AC-link Interface 22-14 Chapter 22 Electrical Characteristics 22.5.14 NAND Flash Memory Interface AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item ND_ALE Output Delay Time ND_CLE Output Delay Time ND_CE* Output Delay Time DATA[7:0] Read Setup Time DATA[7:0] Read Hold Time ND_WE* Low Pulse Width DATA[7:0] Output Delay Symbol tVAL_NDALE tVAL_NDCLE tVAL_NDCE tSU_RDATA tHO_RDATA tPW_NDWE tVAL_DATA Condition GBUSCLK reference GBUSCLK reference GBUSCLK reference ND_RE* rising edge ND_RE* rising edge ⎯ ND_RE* rising edge Min. ⎯ ⎯ ⎯ 12 0 Max. 15 15 15 ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns *1) *2) *1) *2) tVAL_NDWE = (NDFSPR.SPW + 1) × GBUSCLK cycle tVAL_DATA = NDFSPR.HOLD × GBUSCLK cycle – 3 MASTERCLK (Note 1) GBUSCLK tVAL_ND* ND_ALE, ND_CLE ND_CE* ND_RE* tSU_RDAT DATA[7:0] inputs valid tHO_RDATA tPW_NDWE ND_WE* tVAL_DATA DATA[7:0] Note 1: This figure shows the timing diagram when the boot configuration setting is ADDR[2]=H. The NAND Flash Memory Controller operates synchronously to the internal GBUSCLK. GBUSCLK is an internal signal. When ADDR[2]=H, MASTERCLK and GBUSCLK become clocks with the same phase. When ADDR[2]=L, GBUSCLK has a frequency 4 times that of MASTERCLK. The timings of the rising edges match between both clocks. 22-15 Chapter 22 Electrical Characteristics 22.5.15 SPI AC characteristics (Tc = 0 - 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item SPICLK Cycle Time Symbol fCYC_SPICLK Conditions Boot Configuration ADDR[2]=H Boot Configuration ADDR[2]=L Min. 8 × tMCP 2 × tMCP ⎯ ⎯ tMCP × 0.9 tMCP × 0.9 ⎯ 16 0 Max. ⎯ ⎯ 1/8 × fMCK 1/2 × fMCK ⎯ ⎯ 6 ⎯ ⎯ Unit ns ns MHz MHz ns ns ns ns ns SPICLK Frequency fSPICLK Boot Configuration ADDR[2]=H Boot Configuration ADDR[2]=L SPICLK High Time SPICLK Low Time SPIOUT Output Delay Time SPIIN Input Setup Time SPIIN Input Hold Time tHIGH_SPICLK tLOW_SPICLK tVAL_SPIOUT tSU_SPIIN tHO_SPIIN tHIGH_SPICLK SPICLK tLOW_SPICLK tCYC_SPICLK/fSPICLK SPICLK SPIOUT (SPOL = 0) tVAL_SPIOUT SPIIN (SPOL = 0) tSU_SPIIN tHO_SPIIN SPICLK SPIOUT (SPOL = 1) tVAL_SPIOUT SPIIN (SPOL = 1) tSU_SPIIN tHO_SPIIN 22-16 Chapter 22 Electrical Characteristics 22.5.16 Ethernet Interface (MII) AC characteristics (Tc = 0 – 70°C, VCCIO = 3.3 V ± 0.2 V, VCCInt = 1.5 V ± 0.1 V, VSS = 0 V) Item Reception Data Setup Time Reception Data Set Hold Time Transmission Data Output Delay Time E*MDC Cycle Time Symbol tSU_RX tHO_RX tval_TX tCYC_MDC Conditions E*RXCLK reference E*RXCLK reference E*TXCLK reference CLK = 50 pF W hen on-chip PCI bus is clocked at 1/4 of GBUS clock, (GBUSCLK=120 MHz, 120÷4÷14=2.14 MHz) W hen on-chip PCI bus is clocked at 1/2 of GBUS clock, (GBUSCLK=120 MHz, 120÷2÷30=2 MHz) Min. 10 10 0 Max. ⎯ ⎯ 25 Unit ns ns ns 467 ⎯ ns 500 ⎯ ns E*MDIO Input Setup Time E*MDIO Input Hold Time E*MDI Output Delay Time (PHY Setup) E*MDI Output Delay Time (PHY Hold) tSU_MDIO tHO_MDIO tVAL_SU_MDIO tVAL_HO_MDIO E*MDC reference E*MDC reference E*MDC reference E*MDC CL = 30 pF E*MDIO CL = 50 pF 40 0 10 10 ⎯ ⎯ ⎯ ⎯ ns ns ns ns (1) Reception signals E*RXCLK (10 Mbps: 2.5 MHz) (100 Mbps: 25 MHz) E*RXD[3:0] E*RXDV tSU_RX tHO_RX (2) Transmission signals E*TXCLK (10 Mbps: 2.5 MHz) (100 Mbps: 25 MHz) E*TXD[3:0] E*TXEN tval_TX Valid 22-17 Chapter 22 Electrical Characteristics (3) Management signals tCYC_MDC E*MDC E*MDIO (input) Valid tSU_MDIO When TX4938 receives E*MDIO tHO_MDIO E*MDC E*MDIO (output) tVAL_SU_MDIO W hen TX4938 outputs E*MDIO tVAL_HO_MDI 22-18 Chapter 23 Pinout and Package Information 23. Pinout and Package Information 23.1 Pinout Diagram Figure 23.1.1 shows the TX4938 pinout. Table 23.1.1 provides a pin cross reference by pin number. provides a pin cross reference by pin name. Table 23.1.3 provides a pin cross reference for thermal balls. 23-1 Chapter 23 Pinout and Package Information A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C_BE[2] IRDY* VddIO VSS PCIAD [15] PCIAD [11] C_BE[0] PCIAD[5] PCIAD[2] PCST[0] PCST[3] B VSS FRAME* STOP* PERR* C_BE[1] PCIAD [12] PCIAD[8] PCIAD[6] PCIAD[3] PCIAD[0] PCST[2] C PCIAD [16] PCIAD [17] DEVSEL* LOCK* PAR PCIAD [13] PCIAD[9] PCIAD[7] VddIO PCIAD[1] PCST[1] PCST[4] PCST[7] TPC[3] TMS TDI BWE[3]* VddIO DMAREQ [3] CE[1]* CE[2]* ACE* ACK* D PCIAD [18] VddIO TRDY* VddIN SERR* VddIO M66EN VddIO PCIAD[4] VddIN VddIO VddIN VddIO TPC[2] VddIO DMAACK [0] VddIN VSS VddIN CE[0]* VSS BYPASSP LL* VddIN PIO[6] VSS PIO[7] E PCIAD [19] PCIAD [20] PCIAD [21] PCIAD [22] VSS PCIAD [14] PCIAD [10] VSS VSS VSS TRST* VSS PCST[6] TPC[1] VSS DMAREQ [0] VSS DMADON E* VSS VddIO SDIN[1] VSS VddIO TIMER[1] TIMER[0] TCLK F PCIAD [23] VddIO ID_SEL C_BE[3] VddIO G PCIAD [24] PCIAD [25] PCIAD [26] PCIAD [27] PCIAD [28] H PCICLK [0] VddIO PCIAD [29] VddIN VSS J PCICLK [1] GNT[0]* PCIAD [30] VSS PCIAD [31] K PCICLK [2] REQ[0]* GNT[1]* VddIN VSS L PCICLK [3] GNT[2]* REQ[2]* VSS REQ[1]* M PCICLK [4] GNT[3]* REQ[3]* VddIO VSS N PCICLK [5] DATA[63] VSS VddIO PME* VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS EEPROM_ PCST[5] CS EEPROM_ PCST[8] SK VSS TDO EEPROM_ DCLK DO EEPROM_ TCK DI BWE[1]* BWE[0]* DMAACK [1] DMAACK [2] CE[4]* CE[5]* CE[7]* SWE* PIO[0] PIO[1] BWE[2]* DMAREQ [1] DMAREQ [2] DMAACK [3] CE[3]* VddIO CE[6]* TOP View VddIN NMI* INT[0] INT[1] INT[2] VddIN RXD[0] INT[3] INT[4] INT[5] VSS VddIO CTS[0]* RTS[0]* TXD[0] RXD[1] CTS[1]* RTS[1]* TXD[1] SCLK VSS VddIN TEST[1]* TEST[2]* VSS VddIN VddIO W DRST* OE* VddIO VSS DATA[0] DATA[32] DATA[1] BUSSPRT VddIO * PIO[2] PIO[3] PIO[4] PIO[5] HALTDOZE TEST[3]* TEST[0]* RESET* TEST[4]* SYSCLK Figure 23.1.1 Pinout Diagram (1/2) 23-2 Chapter 23 Pinout and Package Information P PCICLKIN R T U VSS DATA[61] VddIO VddIN VSS V DATA[29] DATA[60] VSS DATA[28] VddIO W DATA[59] DATA[27] VSS VddIO VSS Y DATA[58] DATA[26] DATA[57] DATA[25] VddIO AA DATA[56] DATA[24] DATA[55] VSS DATA[23] AB VSS DATA[54] VSS VddIO VSS CB[3] DQM[7] VSS SDCS[3]* AC DATA[22] DATA[53] VSS VddIN DATA[48] VSS CB[2] VddIN DQM[2] VddIN VddIO VddIO VddIO VddIO VddIN ADDR[8] VddIN VddIO VddIO SDCS[0]* VSS VddIO VddIN VSS VSS DATA[14] AD DATA[21] DATA[52] DATA[50] VSS DATA[17] CB[7] VSS VSS DQM[6] CKE ADDR[18] ADDR[15] ADDR[14] ADDR[12] ADDR[10] VSS ADDR[5] VSS VSS SDCS[1]* DQM[4] VSS VSS CB[0] DATA[46] VddIO AE VddIO DATA[20] VddIO VSS DATA[49] VddIO CB[6] DQM[3] VSS SDCS[2]* ADDR[19] ADDR[16] VSS ADDR[13] VSS ADDR[9] ADDR[6] ADDR[4] ADDR[1] RAS* DQM[1] WE* CB[5] CB[4] VddIO DATA[15] AF VSS DATA[51] DATA[19] VddIO DATA[18] DATA[16] VddIO SDCLK[1] VSS SDCLK[3] VSS SDCLKIN SDCLK[0] SDCLK[2] ADDR[11] VddIO VSS VddIO ADDR[2] ADDR[0] DQM[5] VSS CAS* CB[1] DATA[47] VSS MASTERC VSS LK 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PLL2VSS_ PLL1VSS_ DATA[31] A A PLL2VDD_ PLL1VDD_ VddIO A A CGRESET VddIN * VddIN VSS DATA[62] DATA[30] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ADDR[17] VSS VSS VSS VSS ADDR[7] VSS ADDR[3] VSS VddIO TOP View VddIO VSS DATA[33] VSS DATA[2] VSS VddIO DATA[34] DATA[3] DATA[35] DATA[4] VddIO DATA[36] DATA[5] VSS VSS VddIN DATA[37] DATA[6] DATA[38] DATA[7] VddIO VddIO VSS VSS VSS VddIN VSS DATA[39] DATA[8] DATA[40] DATA[9] VSS DATA[41] DATA[10] DATA[42] VSS VddIO DATA[11] DATA[43] DQM[0] VSS DATA[12] DATA[44] DATA[13] DATA[45] Figure 23.1.1 Pinout Diagram (2/2) 23-3 Chapter 23 Pinout and Package Information Table 23.1.1 Pin Cross Reference by Pin Number (1/2) Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Pin Name PIO[1] PIO[0] SWE* CE[7]* CE[5]* CE[4]* DMAACK[2] DMAACK[1] BWE[0]* BWE[1]* EEPROM_DI EEPROM_DO VSS EEPROM_SK EEPROM_CS PCST[3] PCST[0] PCIAD[2] PCIAD[5] C_BE[0] PCIAD[11] PCIAD[15] VSS VddIO IRDY* C_BE[2] PIO[3] PIO[2] BUSSPRT* CE[6]* VddIO CE[3]* DMAACK[3] DMAREQ[2] DMAREQ[1] BWE[2]* TCK DCLK TDO PCST[8] PCST[5] PCST[2] Pin Number B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 Pin Name PCIAD[0] PCIAD[3] PCIAD[6] PCIAD[8] PCIAD[12] C_BE[1] PERR* STOP* FRAME* VSS PIO[5] PIO[4] VddIO ACK* ACE* CE[2]* CE[1]* DMAREQ[3] VddIO BWE[3]* TDI TMS TPC[3] PCST[7] PCST[4] PCST[1] PCIAD[1] VddIO PCIAD[7] PCIAD[9] PCIAD[13] PAR LOCK* DEVSEL* PCIAD[17] PCIAD[16] PIO[7] VSS PIO[6] VddIN BYPASSPLL* VSS Pin Number D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 Pin Name CE[0]* VddIN VSS VddIN DMAACK[0] VddIO TPC[2] VddIO VddIN VddIO VddIN PCIAD[4] VddIO M66EN VddIO SERR* VddIN TRDY* VddIO PCIAD[18] TCLK TIMER[0] TIMER[1] VddIO VSS SDIN[1] VddIO VSS DMADONE* VSS DMAREQ[0] VSS TPC[1] PCST[6] VSS TRST* VSS VSS VSS PCIAD[10] PCIAD[14] VSS Pin Number E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 Pin Name PCIAD[22] PCIAD[21] PCIAD[20] PCIAD[19] INT[2] INT[1] INT[0] NMI* VddIN VddIO C_BE[3] ID_SEL VddIO PCIAD[23] INT[5] INT[4] INT[3] RXD[0] VddIN PCIAD[28] PCIAD[27] PCIAD[26] PCIAD[25] PCIAD[24] TXD[0] RTS[0]* CTS[0]* VddIO VSS VSS VddIN PCIAD[29] VddIO PCICLK[0] SCLK TXD[1] RTS[1]* CTS[1]* RXD[1] PCIAD[31] VSS PCIAD[30] Pin Number J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N22 N23 N24 N25 N26 Pin Name GNT[0]* PCICLK[1] RESET* TEST[0]* HALTDOZE VddIN VSS VSS VddIN GNT[1]* REQ[0]* PCICLK[2] SYSCLK TEST[4]* TEST[3]* TEST[2]* TEST[1]* REQ[1]* VSS REQ[2]* GNT[2]* PCICLK[3] OE* WDRST* VddIO VddIN VSS VSS VddIO REQ[3]* GNT[3]* PCICLK[4] DATA[1] DATA[32] DATA[0] VSS VddIO PME* VddIO VSS DATA[63] PCICLK[5] 23-4 Chapter 23 Pinout and Package Information Table 23.1.1 Pin Cross Reference by Pin Number (2/2) Pin Number P1 P2 P3 P4 P5 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 Pin Name DATA[2] VSS DATA[33] VSS VddIO VddIN CGRESET* PLL2VDD_A PLL2VSS_A PCICLKIN DATA[35] DATA[3] DATA[34] VddIO VSS VSS VddIN PLL1VDD_A PLL1VSS_A MASTERCLK VSS DATA[5] DATA[36] VddIO DATA[4] DATA[30] DATA[62] VddIO DATA[31] VSS DATA[38] DATA[6] DATA[37] VddIN VSS VSS VddIN VddIO DATA[61] VSS VSS VSS Pin Number V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 Pin Name VddIO VddIO DATA[7] VddIO DATA[28] VSS DATA[60] DATA[29] DATA[8] DATA[39] VSS VddIN VSS VSS VddIO VSS DATA[27] DATA[59] DATA[10] DATA[41] VSS DATA[9] DATA[40] VddIO DATA[25] DATA[57] DATA[26] DATA[58] DATA[43] DATA[11] VddIO VSS DATA[42] DATA[23] VSS DATA[55] DATA[24] DATA[56] DATA[45] DATA[13] DATA[44] DATA[12] Pin Number AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 Pin Name VSS DQM[0] VddIO VSS ADDR[3] VSS ADDR[7] VSS VSS VSS VSS ADDR[17] VSS SDCS[3]* VSS DQM[7] CB[3] VSS VddIO VSS DATA[54] VSS DATA[14] VSS VSS VddIN VddIO VSS SDCS[0]* VddIO VddIO VddIN ADDR[8] VddIN VddIO VddIO VddIO VddIO VddIN DQM[2] VddIN CB[2] Pin Number AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 Pin Name VSS DATA[48] VddIN VSS DATA[53] DATA[22] VddIO DATA[46] CB[0] VSS VSS DQM[4] SDCS[1]* VSS VSS ADDR[5] VSS ADDR[10] ADDR[12] ADDR[14] ADDR[15] ADDR[18] CKE DQM[6] VSS VSS CB[7] DATA[17] VSS DATA[50] DATA[52] DATA[21] DATA[15] VddIO CB[4] CB[5] WE* DQM[1] RAS* ADDR[1] ADDR[4] ADDR[6] Pin Number Pin Name AE11 ADDR[9] AE12 VSS AE13 ADDR[13] AE14 VSS AE15 ADDR[16] AE16 ADDR[19] AE17 SDCS[2]* AE18 VSS AE19 DQM[3] AE20 CB[6] AE21 VddIO AE22 DATA[49] AE23 VSS AE24 VddIO AE25 DATA[20] AE26 VddIO AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 VSS DATA[47] CB[1] CAS* VSS DQM[5] ADDR[0] ADDR[2] VddIO AF10 VSS AF11 VddIO AF12 ADDR[11] AF13 SDCLK[2] AF14 SDCLK[0] AF15 SDCLKIN AF16 VSS AF17 SDCLK[3] AF18 VSS AF19 SDCLK[1] AF20 VddIO AF21 DATA[16] AF22 DATA[18] AF23 VddIO AF24 DATA[19] AF25 DATA[51] AF26 VSS 23-5 Chapter 23 Pinout and Package Information Table 23.1.2 Pin Cross Reference by Pin Name (1/2) Pin Number C5 C4 AF7 AE8 AF8 AB9 AE9 AD10 AE10 AB11 AC11 AE11 AD12 AF12 AD13 AE13 AD14 AD15 AE15 AB16 AD16 AE16 B3 A9 A10 B10 C10 D5 AF4 AD3 AF3 AC20 AB21 AE3 AE4 AE20 AD21 D7 C7 C6 B6 A6 Pin Name ACE* ACK* ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] ADDR[8] ADDR[9] ADDR[10] ADDR[11] ADDR[12] ADDR[13] ADDR[14] ADDR[15] ADDR[16] ADDR[17] ADDR[18] ADDR[19] BUSSPRT* BWE[0]* BWE[1]* BWE[2]* BWE[3]* BYPASSPLL* CAS* CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB[6] CB[7] CE[0]* CE[1]* CE[2]* CE[3]* CE[4]* Pin Number A5 B4 A4 P23 AD17 K1 H3 J4 A20 B22 A26 F23 N3 N1 P1 R2 T5 T2 U2 V5 W1 Y4 Y1 AA2 AB4 AB2 AC1 AE1 AF21 AD22 AF22 AF24 AE25 AD26 AC26 AA22 AA25 Y23 Y25 W 25 V23 V26 Pin Name CE[5]* CE[6]* CE[7]* CGRESET* CKE RESET* CTS[0]* CTS[1]* C_BE[0] C_BE[1] C_BE[2] C_BE[3] DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] DATA[22] DATA[23] DATA[24] DATA[25] DATA[26] DATA[27] DATA[28] DATA[29] Pin Number T22 T25 N2 P3 R3 R1 T3 U3 U1 W2 Y5 Y2 AA5 AA1 AB3 AB1 AD2 AF2 AC22 AE22 AD24 AF25 AD25 AC25 AB25 AA24 AA26 Y24 Y26 W26 V25 U25 T23 N25 B12 C24 D11 A8 A7 B7 E9 E11 Pin Name DATA[30] DATA[31] DATA[32] DATA[33] DATA[34] DATA[35] DATA[36] DATA[37] DATA[38] DATA[39] DATA[40] DATA[41] DATA[42] DATA[43] DATA[44] DATA[45] DATA[46] DATA[47] DATA[48] DATA[49] DATA[50] DATA[51] DATA[52] DATA[53] DATA[54] DATA[55] DATA[56] DATA[57] DATA[58] DATA[59] DATA[60] DATA[61] DATA[62] DATA[63] DCLK DEVSEL* DMAACK[0] DMAACK[1] DMAACK[2] DMAACK[3] DMADONE* DMAREQ[0] Pin Number B9 B8 C8 AB6 AE6 AC18 AE19 AD6 AF6 AD18 AB20 A15 A11 A12 A14 B25 J25 K24 L25 M25 K3 F24 F3 F2 F1 G3 G2 G1 A25 C23 D20 R26 F4 M1 C22 B17 C17 A18 B18 D18 A19 B19 Pin Name DMAREQ[1] DMAREQ[2] DMAREQ[3] DQM[0] DQM[1] DQM[2] DQM[3] DQM[4] DQM[5] DQM[6] DQM[7] EEPROM_CS EEPROM_DI EEPROM_DO EEPROM_SK FRAME* GNT[0]* GNT[1]* GNT[2]* GNT[3]* HALTDOZE ID_SEL INT[0] INT[1] INT[2] INT[3] INT[4] INT[5] IRDY* LOCK* M66EN MASTERCLK NMI* OE* PAR PCIAD[0] PCIAD[1] PCIAD[2] PCIAD[3] PCIAD[4] PCIAD[5] PCIAD[6] Pin Number C19 B20 C20 E20 A21 B21 C21 E21 A22 C26 C25 D26 E26 E25 E24 E23 F26 G26 G25 G24 G23 G22 H24 J24 J22 P26 H26 J26 K26 L26 M26 N26 A17 C16 B16 A16 C15 B15 E14 C14 B14 B23 Pin Name PCIAD[7] PCIAD[8] PCIAD[9] PCIAD[10] PCIAD[11] PCIAD[12] PCIAD[13] PCIAD[14] PCIAD[15] PCIAD[16] PCIAD[17] PCIAD[18] PCIAD[19] PCIAD[20] PCIAD[21] PCIAD[22] PCIAD[23] PCIAD[24] PCIAD[25] PCIAD[26] PCIAD[27] PCIAD[28] PCIAD[29] PCIAD[30] PCIAD[31] PCICLKIN PCICLK[0] PCICLK[1] PCICLK[2] PCICLK[3] PCICLK[4] PCICLK[5] PCST[0] PCST[1] PCST[2] PCST[3] PCST[4] PCST[5] PCST[6] PCST[7] PCST[8] PERR* 23-6 Chapter 23 Pinout and Package Information Table 23.1.2 Pin Cross Reference by Pin Name (2/2) Pin Number A2 A1 B2 B1 C2 C1 D3 D1 R24 R25 P24 P25 N22 AE7 K25 L22 L24 M24 H2 J3 G4 J5 J1 E6 Pin Name PIO[0] PIO[1] PIO[2] PIO[3] PIO[4] PIO[5] PIO[6] PIO[7] PLL1VDD_A PLL1VSS_A PLL2VDD_A PLL2VSS_A PME* RAS* REQ[0]* REQ[1]* REQ[2]* REQ[3]* RTS[0]* RTS[1]* RXD[0] RXD[1] SCLK SDIN[1] Pin Number L5 L4 L3 L2 E2 E3 C12 E13 D13 C13 D24 E16 H1 J2 A13 A23 B26 D2 D6 D9 E10 E12 E15 E17 E18 E19 E22 E5 E8 H22 H5 J23 K22 K5 L23 M22 M5 N24 N4 P2 P4 R22 Pin Name TEST[1]* TEST[2]* TEST[3]* TEST[4]* TIMER[0] TIMER[1] TMS TPC[1] TPC[2] TPC[3] TRDY* TRST* TXD[0] TXD[1] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number R5 T1 T26 U22 U26 U5 V1 V2 V24 W22 W 24 W3 W5 Y3 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number Pin Name Pin Number D25 E4 E7 F22 F25 H25 H4 M23 M3 N23 N5 P5 R4 T24 T4 U24 V22 V3 V4 W23 Y22 AA3 Pin Name VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO AE14 VSS AE18 VSS AE23 VSS AF1 VSS AF10 VSS AF16 VSS AF18 VSS AF26 VSS AF5 D10 D15 D17 D23 D4 D8 F5 G5 H23 K23 K4 M4 P22 R23 U23 U4 W4 VSS VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN VddIN AA23 VSS AA4 VSS AB10 VSS AB12 VSS AB13 VSS AB14 VSS AB15 VSS AB17 VSS AB19 VSS AB22 VSS AB24 VSS AB26 VSS AB5 AB8 AC2 VSS VSS VSS AB23 VddIO AB7 VddIO AF15 SDCLKIN AF14 SDCLK[0] AF19 SDCLK[1] AF13 SDCLK[2] AF17 SDCLK[3] AC7 AD7 SDCS[0]* SDCS[1]* AC13 VddIO AC14 VddIO AC15 VddIO AC16 VddIO AC5 AC8 AC9 AD1 AE2 VddIO VddIO VddIO VddIO VddIO AC10 VddIN AC12 VddIN AC17 VddIN AC19 VddIN AC23 VddIN AC4 A24 B5 C18 C3 C9 D12 D14 D16 D19 D21 VddIN VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO VddIO AC21 VSS AC24 VSS AC3 AC6 VSS VSS AE17 SDCS[2]* AB18 SDCS[3]* D22 B24 A3 L1 B11 E1 C11 B13 K2 SERR* STOP* SWE* SYSCLK TCK TCLK TDI TDO TEST[0]* AD11 VSS AD19 VSS AD20 VSS AD23 VSS AD4 AD5 AD8 AD9 VSS VSS VSS VSS AE21 VddIO AE24 VddIO AE26 VddIO AF11 VddIO AF20 VddIO AF23 VddIO AF9 M2 AE5 VddIO WDRST* WE* AE12 VSS 23-7 Chapter 23 Pinout and Package Information Table 23.1.3 Pin Cross Reference for Thermal Balls Pin Number K10 K11 K12 K13 K14 K15 K16 K17 L10 L11 L12 L13 L14 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N10 N11 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number N12 N13 N14 N15 N16 N17 P10 P11 P12 P13 P14 P15 P16 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number P17 R10 R11 R12 R13 R14 R15 R16 R17 T10 T11 T12 T13 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number T14 T15 T16 T17 U10 U11 U12 U13 U14 U15 U16 U17 Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 23-8 Chapter 23 Pinout and Package Information 23.2 Package Dimensions P-BGA484-3535-1.27B9 Unit: mm 23-9 Chapter 23 Pinout and Package Information 23-10 Chapter 24 Notes on Use of TMPR4938 24. Notes on Use of TMPR4938 24.1 Notes on TX49/H3 Core • Restriction on detect of the Bus errors when a data cycle generated by load instruction. [Restriction] Error notification to the TX49/H3 Core using Bus errors is not enabled or Executing a SYNC instruction immediately after the preceding load instruction. [Violation] When a Bus error exception (DBE) occurs during a data Read cycle generated by a preceding load instruction and an exception with a higher priority than the Bus error exception (DBE) occurs in a subsequently executed instruction, the exception of the subsequent instruction is processed first and Bus error exceptions (DBE) are no longer detected. The TX49/H3 Core has a non-blocking load function. With this function, the instruction that follows the preceding load instruction is executed without stalling if it is not dependent on the preceding load instruction. When reading the data from the preceding load instruction and a Bus Error exception (DBE) occurs and an exception (see the following table for the priority order when consecutive instructions issue multiple exceptions at the same timing) with a higher priority than the Bus Error exception (DBE) of the subsequently executed instruction occurs, the exception that the subsequent instruction issued is processed before the Bus Error exception (DBE) and Bus Error exceptions (DBE) can no longer be detected. Priority Order for Exceptions Issued at the Same Timing Priority Sequence (High) Cold Reset Soft Reset NMI Bus Error (IBE) Ov,Tr,Sys,Bp,RI,CpU,FPE Address Error (AdEL/AdES) TLB Refill (TLBL/TLBS) TLB Invalid (TLBL/TLBS) TLB Modify (TLBL/TLBS) Bus Error (DBE) Interrupt Address Error (AdEL) TLB Refill (TLBL) TLB Invalid (TLBL) Instruction Fetch Instruction Fetch Instruction Fetch Data Access Data Access Data Access Data Access Data Access Instruction Fetch Detected PipeStage M M M M M M M M M M M E E E Instruction synchronous or asynchronous Async Async Async Async Sync Sync Sync Sync Sync Async Async Sync Sync Sync Note: The table above differs from Table 11-3 (Priority Order when the Same Instruction Issues Multiple Exceptions at the Same Timing) on page 11-2 of the “TX49/H2, H3, H4 Core Architecture”. 24-1 Chapter 24 Notes on Use of TMPR4938 Bus errors occur the following three conditions. (1) When CCFG.TOE of the Chip Configuration Register is set to “1” (Default: 0), G-Bus timeout error detection is enabled, and the following situation results: • • A Bus timeout occurs when a G-Bus Bus Master (TX49/H3 Core, DMAC, or PCIC) is reading the G-Bus A Bus timeout occurs when a G-Bus Bus Master (other than the TX49/H3 Core) is writing to the G-Bus (2) When ECCCR.MEB of the ECCCR Register in the SDRAM Controller is set to “1” (Default: 0), Parity errors are enabled during a multi-bit error, and the following situation results: • • A 2-bit ECC error or Parity error is detected during SDRAM Read operation by the TX49/H3 Core A 2-bit ECC error or Parity error is detected during Read/Write operation by a G-Bus Bus Master other than the TX49/H3 Core (3) When PCICCFG.IRBER of the PCICCFG Register in the PCI Controller is set to “1” (Default: 1), and the following situation results during initiator Read operation: • • • • • A Parity error is detected A Master ABORT is received A Target ABORT is received A TRDY timeout is detected A Retry timeout is detected There is no problem for ColdReset or SoftReset exceptions because initialization processing is performed after the exception occurs. Also, there is no problem for NMI exceptions if the process after the exception occurs is similar to the above reset process. [Workaround] • • There is no problem if error notification to the TX49/H3 Core using Bus errors is not enabled in the above Conditions. Executing a SYNC instruction immediately after the preceding load instruction allows you to avoid this condition because the next instruction will not be executed until the Load data arrives. 24-2 Chapter 24 Notes on Use of TMPR4938 24.2 Notes on External Bus Controller • Output delay of DATA[63:0] depends on the external bus speed set with EBCCRn.SP. For details on it, see 22.5.4 External Bus Interface AC Characteristics. 24.3 Notes on DMA Controller • • When burst transfer is performed during DMA transfer, the increment value setting for address is restricted. For details, see 8.3.7 Single Address Transfer and 8.3.8 Dual Address Transfer. Restrictions in dual address transfer by the DMA controller [Restriction] Setting the DMA master control register (DMMCRn) is restricted in the dual address transfer mode. [Violation] When a bus error occurs on a channel contained in DMAC, “all 0” may be written repeatedly to the address (DMSARn), that should be read, in all channels including it. In this case, the address value (DMSARn) and count register value (DMCNTRn) are not changed, and write is continued to the same address until CPU terminates DMA transfer (0 is set to DMCCRn.XFACT). This violation occurs in the following conditions. (1) FIFO is disabled. 0 is set to either one channel or more of FIFUM[n] (n=3 to 0) in DMMCR. (2) The channel shown above (1) is set to dual address transfer. 0 is set to SNGAD in DMCCRn (n=3 to 0). (3) A bus error occurs during access to the destination address in the channel which satisfies both (1) and (2). 1 is set to DESERR in DMCSRn (n=3 to 0). (4) When (3) is satisfied, single transfer (non-burst transfer) in dual address transfer mode (see Supplemental Remarks for details) performed in any channel causes the violation shown above. When DMMCR.FIFUM[n]=0 is set in dual address transfer mode, single transfer (non-burst transfer) is performed regardless of the value set to DMCCRn.XFSZ. 24-3 Chapter 24 Notes on Use of TMPR4938 In the case only one channel is used, restarting DMS transfer without a reset of FIFO results in a malfunction when the conditions (1) to (3) are satisfied. When two channels are used in a system, the following table shows settings to cause malfunctions. Ch. A of a bus error FIFO Disable Disable Disable Ch. B FIFO Disable Enable Enable XFSZ Any value Any value Any value Transfer Single Single Single XFSZ Any value 24-8 Chapter 24 Notes on Use of TMPR4938 • Restriction when Initiator Write by PDMAC and Target Read conflict. [Restriction] Don’t perform Target Read from a register on the G-Bus when the condition is the following . [Violation] When an Initiator Write transaction using PDMAC (PCI Dedicated DMA Controller) mounted in the PCI Controller of the target product and a Target Read transaction to the target product by the a device on the PCI Bus conflict, there are cases when the Target Read data is corrupted. (1) In the PCI Controller of the above target product: A. PDMAC performs an Initiator Write transaction to a device on the PCI Bus. B. Device on the PCI Bus becomes the Bus Master and performs a Target Read on the target product. When the two above accesses conflict, (2) The internal bus (G-Bus) of the target product is accessed continuously in the following order. (a) PDMAC reads the Initiator Write data on the G-Bus. (b) TC (Target Controller) reads data from the G-Bus because of a Target Read request. (3) The target of the Target Read in (2) is a register on the G-Bus However, there is no corresponding register on the Internal Bus (IM-Bus). G-Bus SDRAMC SDRAM etc TX49 (CP0) EBIF Data Memory Bus (a) G-Bus Module Reg. (b) TC Device 1 on PCI Bus TX4938 Device 2 on PCI Bus A. PDMAC Initiator Write PCI Bus B. Target Read PDMAC [Workarounds] Do not perform Target Read access from a register on the G-bus or Internal SRAM area under the above conditions. The register on the G-Bus is a register with the 0x5000 to 0x5FFF, 0x6000 to 0x67FF and 0x7000 to 0xEFFF. 24-9 Chapter 24 Notes on Use of TMPR4938 24.5 Notes on Serial I/O Port • Restrictions on use of the break function in SIO [Restriction] To transmit breaks to TX4938, synchronize breaks to the start bit. Set consecutively the transmit data to Low immediately after the start bit. [Violation] When the transmitting end transmits breaks to TX4938 in the middle of a transmission, TX4938 detects the first flame error only, but not breaks. When the break reception is synchronized to the start bit (the receive data is consecutively set to Low immediately after the start bit), breaks can be detected correctly. (Malfunction) Status SIN ↑ Start ↑ Flame Error S12345678PS * Since the start bit is not recognized after a flame error, the receiving status is stopped in idle state. (Correct operation) Status SIN ↑ Start ↑ 1st Break ↑ 2nd Break S12345678PSS12345678PS * W hen the receiving data is consecutively set to Low immediately after the start bit is recognized, breaks can be detected. When breaks are transmitted to TX4938, it may not receive breaks. This malfunction may occur when the transmitting end transmits breaks to TX4938 in the middle of a transmission. [Workarounds] To transmit breaks to TX4938, synchronize breaks to the start bit (set the transmitting data consecutively to Low immediately after the start bit). 24-10 Chapter 24 Notes on Use of TMPR4938 24.6 Notes on Ether Controller • Initializing SRAM containing Ether controller Note: If you use SRAM without initialization, parity errors may be detected incorrectly during packet receiving. To prevent this malfunction, perform the following initialization. (1) Preparation Set TestMode (bit13) of the DMA_Ctl (0x00) register. (Write 1) (2) Initialization of on-chip memory Perform the following for all addresses (0x000 to 0x3ff) of on-chip SRAM. (i) Set the address of on-chip SRAM to ARC_Adr (0x60). (ARC_Loc field: 0x000 to 3ff) (ii) Write 0x00000000 to ARC_Data (0x64) (32-bit write) You can check the data which was written. Read ARC_Data (0x64) (32-bit read) (3) Release test mode Reset TestMode (bit 13) of the DMA_Ctl (0x00) register. (Write 0) 24-11 Chapter 24 Notes on Use of TMPR4938 24-12 Chapter 25 Parts Number when Ordering 25. Parts Number when Ordering Maximum Operating Frequency 300 MHz 333 MHz Parts Number TX4938 TMPR4938XBG-300 TMPR4938XBG-333 Package 484-pin PBGA 484-pin PBGA 25-1 Chapter 25 Parts Number when Ordering 25-2 Appendix A TX49/H3 Core Supplement Appendix A TX49/H3 Core Supplement This section explains items that are unique to the TX4938 of the TX49/H3 Core. Please refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for more information regarding the TX49/H3 Core. A.1 Processor ID PRId Register values of the TX4938 TX49/H3 Core are as follows. Processor Revision Identifier Register: 0x0000 2D30 FPU Implementation/Revision Register (FCR0): 0x0000 2D30 These values may be changed at a later date. Please contact the Toshiba Engineering Department for the most recent information. A.2 Interrupts Interrupt signalling of the on-chip interrupt controller is reflected in bit IP[2] of the Cause Register in the TX49/H3 Core. In addition, interrupt causes are reflected in other bits of the IP field. Please refer to Section “15.3.5 Interrupt notification” for more information. A.3 Bus Snoop The Bus Snoop function is not used with the TX4938 due to restrictions of the Bus Snoop specification. A.4 Halt/Doze mode The Doze mode is not necessary when the Bus Snoop function is not used. Please use the Halt mode, which further reduces power consumption. Clearing the HALT bit of the Config Register makes it possible to shift to the Halt mode by executing the WAIT instruction. A.5 Memory access order The TX49/H3 Core has a 4-stage Write buffer, the PCI Bus Bridge (PCI Controller) has 4 stages for initiator access, and has a 2-stage Post Write buffer (Write buffer) for target access. When data enters the Write buffer of the TX49/H3 Core, Cache Refill Read operations that do not match the address of that data after the Write is issued may be issued to the internal bus (G-Bus) before the Write. Other accesses are issued in order. Executing the SYNC instruction guarantees that bus access invoked by a load/store instruction previously executed will be complete on the internal bus. The PCI Bus Bridge is issued by the issue destination bus in the order all bus accesses are issued on the issue source bus. Please refer to “10.3.6 Post Write Function” for more information regarding methods for guaranteeing the completion of Write transactions of the Post Write Buffer. A-1 Appendix A TX49/H3 Core Supplement A-2 TMPR4938 Revision History TMPR4938 Revision History Page References 2 64-bit TX System RISC TX49/H3 Core Architecture User’s 64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Manual Architecture Modified line 5 of the body text in Section 1.1, Overview 1-1 For details of the TX49/H3 core such as instruction sets, see For details of the TX49/H3 core such as instruction sets, “64-bit TX System RISC TX49/H3 Core Architecture”. see “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture”. Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (1/2) Modified the description of the ADDR[17] and ADDR[15]. 3-14 Reserved Reserved Used for testing. This signal will not be set to 0 upon booting. Rev 1.2 Manual Changes and Additions to Rev 1.2 Modified line 5 of the introduction in Chapter 4, Address Mapping 4-1 Please refer to "64 bit TX System RISC TX49/H3 Core Architecture" about the details of mapping to a physical address from the virtual address of TX49/H3 core. Figure 5.2.1 Chip Configuration Register (1/3) 42 5-3 41 WDRST Please refer to "64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture" about the details of mapping to a physical address from the virtual address of TX49/H3 core. 40 WDREXEN 42 41 WDRST 40 WDREXEN RW1C 0 R/W 0 R/W1C R/W 0 0 Figure 5.2.1 Chip Configuration Register (1/3) 17 5-3 16 BEOW RW1C : Type 0 : Initial value Figure 5.2.1 Chip Configuration Register (1/3) Read/write attribute of the WDRST (Watchdog Reset Status) bit RW1C Figure 5.2.1 Chip Configuration Register (2/3) Read/write attribute of theBEOW (Write-Access Bus Error) bit RW1C R/W1C R/W1C 17 16 BEOW R/W1C : Type 0 : Initial value 5-3 5-4 1 TMPR4938 Revision History Page Rev 1.2 Manual Figure 5.2.3 Pin Configuration Register (1/3) 63 62 61 60 59 58 57 56 55 DRVCB D Changes and Additions to Rev 1.2 63 62 61 60 59 58 57 56 55 DRVCB D ETH0_SEL ETH1_SEL ATA_SEL ISA_SEL SPI_SEL NDF_SEL Reserved DRVDATA ETH0_SEL ETH1_SEL ATA_SEL ISA_SEL SPI_SEL NDF_SEL Reserved DRVDATA R R DATA[3] DATA[6] R/W 0 45 R/W 0 44 R/W 0 R/W 0 41 R/W R/W ADDR[4] ADDR[4] A ~DATA[3] ~DATA[6] R R R/W 0 45 R/W 0 44 R/W 0 R/W 0 41 R/W R/W ADDR[4] ADDR[4] A 47 40 DRVCKIN 39 47 DRVCS[2:0] R/W ADDR[5] 40 DRVCKIN 39 5-7 DRVCS R/W ADDR[5] 31 30 29 28 DRVCK[3:0] R/W ADDR[5] 27 SYSCLKEN DRVCK[3:0] R/W ADDR[5] 29 28 27 SYSCLKEN R/W ADDR[5] R/W ADDR[5] 26 SDCLKEN R/W 1111 23 S 31 30 26 SDCLKEN[3:0] R/W 1111 23 S Reserved SDCLKDLY R/W 00 Reserved SDCLKDLY R/W 00 R/W 1 R/W 1 Figure 5.2.3 Pin Configuration Register (1/3) 21 5-7 PCICLKEN R/W 111111 Figure 5.2.3 Pin Configuration Register (1/3) Initial value of the ETH0_SEL (Status of shared pin) bit DATA[3] Figure 5.2.3 Pin Configuration Register (1/3) Initial value of the ETH1_SEL (Status of shared pin) bit DATA[6] ~DATA[6] Figure 5.2.3 Pin Configuration Register (2/3) Added a note to the description of the DRVCB (CB Signal Control) bit 5-8 Note: CB[7:0]* share pins with PIO[15:8], E0TXD[3:0], E0RXD[3:0]. The driving capability of these pins are below. CB[7:0], E0TXD[3:0], E0RXD[3:0]: 8 mA or 16 mA PIO[15:8]: 8 mA only Figure 5.2.6 G-Bus Arbiter Control Register 15 Reserved 5-14 7 6 5 PRIORITY R/W 00_01_10 10 9 ⎯ R/W 1 8 ARBMD 16 21 PCICLKEN[5:0] R/W 111111 16 5-7 ~DATA[3] 5-7 15 Reserved 14 PRIORITY R/W 000_001_010_011_100 0 PRIORITY R/W 000_001_010_011_100 R/W 1 0 Reserved 2 TMPR4938 Revision History Page Rev 1.2 Manual Figure 6.3.1 Power-On Sequence At least 100 ms (T.B.D) (T.B.D) Changes and Additions to Rev 1.2 PLL settling time (T.B.D) PLL settling time 6-6 ed back) PLL settling time (T.B.D) ed back) PLL settling time Added the following text to line 8 to Section 7.3.6.3, Ready Mode 7-11 W hen the number of wait cycles is 0, READY check is started in 1 cycle after asserting the CE* signal. When the number of wait cycles is other than zero, after waiting only for the specified number of cycles, READY check is started. Figure 7.3.3 Ready Mode 7-11 EBCCRn.PWT:WT=2 Start Ready Check EBCCRn.PWT:WT=2 Start Ready Check Figure 7.3.13 Ready Input Timing (Read Cycle) 7-18 2 clock Acknowledge Ready 2 clocks Acknowledge Ready Latch D E 3 TMPR4938 Revision History Page Rev 1.2 Manual Figure 7.3.13 Ready Input Timing (Read Cycle) Changes and Additions to Rev 1.2 7-18 Start Ready Check Acknowledge Re Start Ready Check Acknowledge Re Figure 7.3.14 Ready Input Timing (Write Cycle) 7-19 3 clock 3 clocks 4 4 clocks Acknowledge Ready Figure 7.3.14 Ready Input Timing (Write Cycle) Acknowledge Ready 7-19 Start Ready Check Acknowledge Read Start Ready Check Acknowledge Ready Modified line 2 of Section 7.3.9, ISA /ATA Mode Since the pins used in ISA/ATA mode are multiplexed pins, Since the pins used in ISA/ATA mode are multiplexed pins, select ISA/ATA before use of these pins. (Refer to “5.2.3 Pin select ISA/ATA before use of these pins. Since the signal of Configuration Register”.) CE* is not used in this mode, when ETHER1 is chosen, this mode can be used by channels 5, 6 and 7. (Refer to “5.2.3 Pin Configuration Register”.) Modified line 3 of the body text in Section 7.3.9.1, Address space 7-20 When access to the ISA I/O space is performed, IOR* and When access to the ISA I/O space is performed, IOR* and IOW * control signals are valid, and OE* and SWE* are IOW * control signals are valid, and OE*, SWE* and CE* invalid. are invalid. Figure 7.5.3 Double-word Single Write (PWT: WT=1, Figure 7.5.3 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) SHWT=0, Normal, 32-bit Bus) Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer 8/0/-8 8/0/-8 7-20 7-31 8-13 4 TMPR4938 Revision History Page Rev 1.2 Manual Changes and Additions to Rev 1.2 Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer Added the following note. 8-13 : When DMSAIRn is set to 0, read access from source device is performed only one time per transmission specified by DMCCRn.XFSZ. For this reason, transfer can not be performed burst transfer to the I/O device which performs FIFO operation. Figure 9.4.4 ECC Control Register (1/2) 63 0x10 R Figure 9.4.4 ECC Control Register (1/2) 55 9-23 0x10 R Figure 9.4.4 ECC Control Register (1/2) Modified the description of the DEEC (Diagnostic ECC) field. The value set by this field is output from CB[7:0] as the check code when the ECCDM bit is set to “Enable.” Figure 9.4.5 ECC Status Register 15 FRRS R — — — — — — — — — Figure 9.6.2 168-pin DIMM Connection Example 128MB un 9-42 ADDR[16:5] A[11:0] ADDR[18] BA0 ADDR[17] BA1 DQMB[7:0] Figure 10.4.1 ID Registers 31 10-26 DID R/L 0x0180 Figure 10.4.1 ID Registers Modified the description of the DID (Device ID) field. Device ID (Default: 0x0180) Device ID (Default: 0x0183) 16 31 DID R/L 0x0183 16 ADDR[16:5] A[11:0] ADDR[19] BA0 ADDR[18] BA1 DQMB[7:0] 128MB un 8 15 ERRS R — — — 8 The value set by this field is output from CB[7:0] as the check code when the DM bit is set to “Enable.” 48 55 VERNO 0x10 48 56 63 MDLNO 0x10 56 9-23 9-23 9-25 10-26 5 TMPR4938 Revision History Page Rev 1.2 Manual Figure 11.4.7 Baud Rate Control Register Modified the description of the BCLK (Baud Rate Generator Clock) field. 11-22 00: Select prescalar output T0 (IMBUSCLK/2) 01: Select prescalar output T2 (IMBUSCLK/8) 10: Select prescalar output T4 (IMBUSCLK/32) 11: Select prescalar output T6 (IMBUSCLK/128) Table 14.3.7 Mic DMA Buffer Format in Big-endian Mode 00: Select prescalar output T0 (fc/2) 01: Select prescalar output T2 (fc/8) 10: Select prescalar output T4 (fc/32) 11: Select prescalar output T6 (fc/128) Changes and Additions to Rev 1.2 Address offset 14-11 +0 #0H #1H #2H : +1 #0L #1L #2L : Address offset +0 +4 +8 : +0 #0H #1H #2H : +1 #0L #1L #2L : z +4 +8 : Deleted the following text from Section16.3.8.5, Frame reception procedure 16-26 Usually, before setting the above code, the DMA Controller Usually, before programming the above registers, the DMA is initialized by storing a valid address in the Buffer List Controller is initialized. Form Pointer Register or initializing a Free Descriptor Area Register and a Free Descriptor Size Register for example. Modified line 20 of Section16.3.9.2, Initial setup of DMA and MAC 16-33 • DMA Transmission Control Register: To customize the Burst sizeC Modified line 9 of Section, 16.3.9.3.2, Initializing the buffer list 16-34 You can use the Reception Buffer Fragment Size Register to globally pack a buffer. Modified line 6 of Section16.3.9.5, Receiving frames 16-35 • DMA Control Register: To customize the Burst size You can use the Reception Fragment Size Register to globally pack a buffer. • Initialize the Reception Frame Pointer Register to the address of the dummy frame descriptor in the free descriptor area. Modified line 4 of Section, 16.3.9.5.2, Releasing buffers • Initialize Free Descriptor Area Base Register to the address of the dummy frame descriptor in the free descriptor area. 16-36 The Control field of the Buffer Fragment Size Register or Frame Descriptor controls the method of mapping the buffer. Modified line 2 of Section 21.2.1, JTAG Controller and Register The Control field of the Reception Fragment Size Register or Frame Descriptor controls the method of mapping the buffer. 21-2 Please refer to the TX49/H3 Core Architecture Manual for Please refer to the “64-bit TX System RISC TX49/H2, all other portion not covered here. TX49/H3, TX49/H4 Core Architecture” for all other portion not covered here. Modified line 3 of 21.2.2, Instruction Register 21-3 Refer to the TX49/H3 Core Architecture Manual for more information regarding each instruction. Refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” for more information regarding each instruction. 6 TMPR4938 Revision History Page Rev 1.2 Manual Table 21.2.1 Bit Configuration of JTAG Instruction Register 21-3 Refer to the TX49/H3 Core Architecture Manual Figure 22.5.1 Timing Diagram: MASTERCLK Refer to the “64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture” Changes and Additions to Rev 1.2 tMCP 22-5 tMCP MASTERCLK 0.8 VCC 0.2 VCC MASTERCL 0.8 VCC 0.2 VCC Figure 22.5.2 Timing Diagram: Power On Reset VCCInt, VCCIO PLL_Vdd1_A, PLL_Vdd2_A MASTERCLK MASTERCLK Oscillation S VCCInt, VCCIO * PLL_Vdd1_A, PLL_Vdd2_A MASTERCLK tMCP_PL CGRESET* CGRESET* tMCP_PL 1) MASTERCLK Oscillation S 22-5 RESET* Note 1: VCCInt and VCCIO must start up simaltaneously, or VCCInt must be first. Note 2: The difference of the stand up time of a power supply within in 100 m seconds. Figure 23.1.1 Pinout Diagram (1/2) *1) RESET* VCCInt and VCCIO must start up simultaneously, or VCCInt must be first. The difference of the stand up time of a power supply within in 100 m seconds. 7 23-2 DMAACK [2] CE[4]* CE[5]* DMAACK [3] CE[3]* VddIO CE[1]* CE[2]* ACE* CE[0]* VSS BYPASSP LL* VddIO SD[1] VSS 7 T OP VddIN DMAACK [2] CE[4]* CE[5]* DMAACK [3] CE[3]* VddIO CE[1]* CE[2]* ACE* CE[0]* VSS BYPASSP LL* VddIO SDIN[1] VSS 6 5 6 5 T OP VddIN 23-4 Table 23.1.1 Pin Cross Reference by Pin Number (1/2) Modified the pin name of the E6 pin. SD[1] Table 23.1.2 Pin Cross Reference by Pin Name (2/2) Modified the pin name of the E6 pin. SD[1] 24. Notes on Use of TMPR4938 24.1 Notes on External Bus Controller 24.2 Notes on DMA Controller 24.3 Note on PCI Controller 24.4 Notes on Serial I/O Port 24.5 Notes on Ether Controller SDIN[1] 24.1 24.2 24.3 24.4 24.5 24.6 Notes on TX49/H3 Core Notes on External Bus Controller Notes on DMA Controller Note on PCI Controller Notes on Serial I/O Port Notes on Ether Controller SDIN[1] 23-7 24-1 24-9 24.4 Note on PCI Controller The section “Restriction when Initiator Write by PDMAC and Target Read conflict” is added. 7 TMPR4938 Revision History Page Rev 1.2 Manual Modified line 2 of the introduction of Appendix A, TX49/H3 Core Supplement A-1 Please refer to the “64-bit TX System RISC TX49/H3 Core Please refer to the “64-bit TX System RISC TX49/H2, Architecture User’s Manual” for more information regarding TX49/H3, TX49/H4 Core Architecture” for more information regarding the TX49/H3 Core. the TX49/H3 Core. Changes and Additions to Rev 1.2 8