UR6512

UNISONIC TECHNOLOGIES CO., LTD UR6512 2A DDR BUS TERMINATION REGULATOR DESCRIPTION The UR6512 is a linear regulator providing up to 2A transient peak current and has sourcing and sinking capability for DDR SDRAM bus terminator applications while regulating an output voltage to within 20mV. It contains a high speed operational amplifier which provides fast load transient response and only requires 10uF of ceramic output capacitance. The UR6512 output termination voltage tracks the reference voltage applied at VREF pin. A resistor divider connected to VIN, GND and VREF pins is used to force the reference voltage to VREF pin. Additional features include current limiting protection and thermal shutdown protection. LINEAR INTEGRATED CIRCUIT FEATURES * DDR1/ DDR2 Termination Voltage Applications * Low Output Voltage Offset within 20mV@±1.8A * Source and Sink 2A Peak Current * Adjustable Output Voltage by External Resistors * Integrated Power MOS Devices * Suspend to RAM(STR) Functionality * Current Limiting Protection * Thermal Shutdown Protection * Cost-Effective and Easy to Use ORDERING INFORMATION Ordering Number UR6512G-SH2-R Package HSOP-8 Packing Tape Reel www.unisonic.com.tw Copyright © 2010 Unisonic Technologies Co., Ltd 1 of 7 QW-R101-030.A UR6512 PIN CONFIGURATIONS VIN GND VREF VOUT 1 2 GND 3 4 LINEAR INTEGRATED CIRCUIT 8 7 6 5 NC NC VCNTL NC PIN DESCRIPTION PIN NO 1 2 3 4 6 5,7,8 PIN NAME VIN GND VREF VOUT VCNTL NC PIN TYPE I O I O I -PIN DESCRIPTION Power supply pin for the VOUT output Ground pin Reference voltage input and active-low shutdown control pin Output voltage pin Power supply pin for the internal control circuits No connect UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 7 QW-R101-030.A UR6512 BLOCK DIAGRAM LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 7 QW-R101-030.A UR6512 LINEAR INTEGRATED CIRCUIT ABSOLUTE MAXIMUM RATING (unless otherwise specified) PARAMETER SYMBOL RATINGS UNIT VCNTL Control Voltage VCNTL 6 V VIN Supply Voltage VIN 6 V Power Dissipation (Ta=25°C) PD 1.176 W Junction Temperature TJ 125 °C Storage Temperature TSTG -65 ~ +150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. THERMAL DATA PARAMETER Junction to Ambient (Note) Junction to Case SYMBOL θJA θJC RATINGS 86 15 UNIT °C/W °C/W RECOMMENDED OPERATING CONDITIONS (Note 1) PARAMETER SYMBOL RATINGS VCNTL Control Voltage VCNTL (3.3 or 5) ±5% VIN Supply Voltage VIN (1.8 ~ 2.5) ±3% VREF Input Voltage VREF (0.9 ~ 1.25) ±3% Junction Temperature TJ -40~+125 Notes: 1. All voltage values are with respect to the network ground terminal unless otherwise noted. 2. The VOUT tracks the VREF with additional voltage offset and load regulation. UNIT V V V °C ELECTRICAL CHARACTERISTICS (Ta=25°C, unless otherwise specified) (VIN=1.8V, VCNTL=5V, VREF=0.9V, COUT = 10µF (Ceramic)) PARAMETER SYMBOL INPUT CURRENT Operation Current of VCNTL ICNTL Standby Current ISTB OUTPUT VOLTAGE (DDR/DDR II/DDR III) Output Voltage Offset (VREF-VOUT) VOS Load Regulation ΔVLOAD PROTECTION Current Limit ILIMIT Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis ΔTSD VREF Shutdown VIH Shutdown Threshold VIL TEST CONDITIONS IOUT =0A VREF