TS16GF300

TS2G~16GCF300 TS2G~16GCF300 Description The Transcend CF 300X is a High Speed Compact Flash Card with high quality Flash Memory assembled on a printed circuit board. 300X CompactFlash Card Features • CompactFlash Specification Version 4.1 Complaint • RoHS compliant products • Single Power Supply: 3.3V 5% or 5V 10% • Operating Temperature: -25 C to 85 C • Storage Temperature: -40 C to 85 C o o o o Placement • Operation Modes: PC Card Memory Mode PC Card IO Mode True IDE Mode • True IDE Mode supports: Ultra DMA Mode 0 to Ultra DMA Mode 5 (Ultra DMA mode 5 must use Power supply: 3.3V) MultiWord DMA Mode 0 to MultiWord DMA Mode 4 PIO Mode 0 to PIO Mode 6 • PC Card Mode supports up to Ultra DMA Mode 5 • True IDE mode: Fixed Disk (Standard) • PC Card Mode: Removable Disk (Standard) • Durability of Connector: 10,000 times • Support S.M.A.R.T (Self-defined) • Support Security Command • Support Wear-Leveling to extend product life • Compliant to CompactFlash, PC Card Mode, and ATA standards Dimensions Transcend Information Inc. 1 V1.1 ± ± TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Transcend Transcend Information Inc. 2 V1.1 TS2G~16GCF300 TS2G~16GCF300 Block Diagram 300X CompactFlash Card Transcend Information Inc. 3 V1.1 TS2G~16GCF300 TS2G~16GCF300 Pin Assignments and Pin Type PC Card Memory Mode Pin Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal Name GND D03 D04 D05 D06 D07 -CE1 A10 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 WP -CD2 -CD1 D11 1 300X CompactFlash Card PC Card I/O Mode Pin Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal Name GND D03 D04 D05 D06 D07 -CE1 A10 -OE A09 A08 A07 VCC A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 -IOIS16 -CD2 -CD1 D11 D12 D13 D14 D15 1 1 1 1 1 1 True IDE Mode4 In, Out Type Ground Pin Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Signal Name GND D03 D04 D05 D06 D07 -CS0 A10 2 Pin Type In, Out Type Ground Pin Type Pin Type In, Out Type Ground I/O I/O I/O I/O I/O I I I I I I I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I/O I/O I/O I/O I/O I I I I I I I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U I1Z I3U I1Z I1Z I1Z Power I/O I/O I/O I/O I/O I I I I I I I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3Z I1Z I3U I1Z I1Z I1Z Power -ATA SEL A09 A08 A07 2 2 2 VCC A06 A05 A04 A03 2 2 2 2 I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 OT3 Ground Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U Ground I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 OT3 Ground Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3U Ground I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I1Z I1Z I1Z I1Z I1Z I1Z I1Z I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 ON3 Ground Ground I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 I3Z Ground A02 A01 A00 D00 D01 D02 -IOCS16 -CD2 -CD1 D11 D12 D13 D14 D15 1 1 1 1 1 1 D121 D13 D14 D15 1 1 1 1 -CE2 -CE2 -CS1 -VS1 -VS1 -VS1 Transcend Information Inc. 4 V1.1 TS2G~16GCF300 TS2G~16GCF300 PC Card Memory Mode Pin Num 34 Signal Name -IORD 10 HSTROBE HDMARDY11 -IOWR STOP 36 37 38 39 40 41 10,11 300X CompactFlash Card PC Card I/O Mode In, Out Type I3U Pin Num 34 Signal Name -IORD 10 HSTROBE -HDMARDY11 -IOWR STOP 10,11 True IDE Mode4 In, Out Type I3U Pin Num 34 Signal Name -IORD HSTROBE8 9 -HDMARDY -IOWR STOP 7 8,9 7 Pin Type I Pin Type I Pin Type I In, Out Type I3Z 35 I I O I3U I3U OT1 Power 35 36 37 38 39 40 41 I I O I3U I3U OT1 Power 35 36 37 38 39 40 41 I I O I3Z I3U OZ1 Power -WE READY VCC -CSEL -VS2 RESET -WAIT 10 5 -WE -IREQ VCC -CSEL -VS2 RESET -WAIT 10 5 -WE3 INTRQ VCC -CSEL -VS2 -RESET IORDY 7 8 I O I I2Z OPEN I2Z I O I I2Z OPEN I2Z I O I I2U OPEN I2Z ON1 42 -DDMARDY DSTROBE O OT1 42 -DDMARDY DSTROBE O OT1 42 -DDMARDY DSTROBE O 11 11 9 OT1 13 43 -INPACK -DMARQ 12 O I OT1 I3U 43 44 -INPACK -DMARQ -REG DMACK 12 12 O OT1 43 DMARQ -DMACK 6 -DASP -PDIAG D08 D09 1 O OZ1 44 45 46 47 48 49 50 -REG -DMACK BVD2 BVD1 D08 D09 1 12 I O O I/O I/O I/O I3U OT1 OT1 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 Ground 44 45 46 47 48 49 50 I I/O I/O I/O I/O I/O I3U I1U, ON1 I1U, ON1 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 Ground O O I/O I/O I/O OT1 OT1 I1Z, OZ3 I1Z, OZ3 I1Z, OZ3 Ground 45 46 47 48 49 50 -SPKR -STSCHG D08 D09 1 1 1 1 D101 GND D101 GND D101 GND Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state signals not to consume current. 2) The signal should be grounded by the host. 3) The signal should be tied to VCC by the host. 4) The mode is required for CompactFlash Storage Cards. 5) The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host. 6) If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal,including a floating condition 7) Signal usage in True IDE Mode except when Ultra DMA mode protocol is active. 8) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active. 9) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active. 10) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active. 11) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active. 12) Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active. Transcend Information Inc. 5 V1.1 TS2G~16GCF300 TS2G~16GCF300 Signal Description Signal Name A10 – A00 (PC Card Memory Mode) 300X CompactFlash Card Dir. I Pin Description 8,10,11,12, These address lines along with the -REG signal are used to select the following: 14,15,16,17, The I/O port address registers within the CompactFlash Storage Card , the memory mapped port address registers within the CompactFlash Storage Card, 18,19,20 a byte in the card's information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal. A10 – A00 (PC Card I/O Mode) A02 - A00 (True IDE Mode) I 18,19,20 In True IDE Mode, only A[02:00] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. This signal is asserted high, as BVD1 is not supported. BVD1 (PC Card Memory Mode) I/O 46 -STSCHG (PC Card I/O Mode) Status Changed This signal is asserted low to alert the host to changes in the READY and Write Protect states, while the I/O interface is configured. Its use is controlled by the Card Config and Status Register. In the True IDE Mode, this input / output is the Pass Diagnostic signal in the Master / Slave handshake protocol. -PDIAG (True IDE Mode) BVD2 (PC Card Memory Mode) I/O 45 This signal is asserted high, as BVD2 is not supported. -SPKR (PC Card I/O Mode) This line is the Binary Audio output from the card. If the Card does not support the Binary Audio function, this line should be held negated. In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. -DASP (True IDE Mode) -CD1, -CD2 (PC Card Memory Mode) O 26,25 These Card Detect pins are connected to ground on the CompactFlash Storage Card. They are used by the host to determine that the CompactFlash Storage Card is fully inserted into its socket. This signal is the same for all modes. -CD1, -CD2 (PC Card I/O Mode) -CD1, -CD2 (True IDE Mode) This signal is the same for all modes. Transcend Information Inc. 6 V1.1 TS2G~16GCF300 TS2G~16GCF300 Signal Name -CE1, -CE2 (PC Card Memory Mode) Card Enable 300X CompactFlash Card Pin 7,32 Description These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. -CE2 always accesses the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29, Table 31, Table 35, Table 36 and Table 37. This signal is the same as the PC Card Memory Mode signal. Dir. I -CE1, -CE2 (PC Card I/O Mode) Card Enable -CS0, -CS1 (True IDE Mode) In the True IDE Mode, -CS0 is the address range select for the task file registers while -CS1 is used to select the Alternate Status Register and the Device Control Register. While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the width of the transfers shall be 16 bits. -CSEL (PC Card Memory Mode) I 39 This signal is not used for this mode, but should be connected by the host to PC Card A25 or grounded by the host. This signal is not used for this mode, but should be connected by the host to PC Card A25 or grounded by the host. This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. -CSEL (PC Card I/O Mode) -CSEL (True IDE Mode) D15 - D00 (PC Card Memory Mode) I/O 31,30,29,28, These lines carry the Data, Commands and Status information between the host 27,49,48,47, and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB 6,5,4,3,2, of the Odd Byte of the Word. 23, 22, 21 This signal is the same as the PC Card Memory Mode signal. D15 - D00 (PC Card I/O Mode) D15 - D00 (True IDE Mode) In True IDE Mode, all Task File operations occur in byte mode on the low order bus D[7:0] while all data transfers are 16 bit using D[15:0]. GND (PC Card Memory Mode) -- 1,50 Ground. GND (PC Card I/O Mode) This signal is the same for all modes. GND (True IDE Mode) This signal is the same for all modes. Transcend Information Inc. 7 V1.1 TS2G~16GCF300 TS2G~16GCF300 Signal Name -INPACK (PC Card Memory Mode except Ultra DMA Protocol Active) 300X CompactFlash Card Pin 43 Description This signal is not used in this mode. The Input Acknowledge signal is asserted by the CompactFlash Storage Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CompactFlash Storage Card and the CPU. Hosts that support a single socket per interface logic, such as for Advanced Timing Modes and Ultra DMA operation may ignore the –INPACK signal from the device and manage their input buffers based solely on Card Enable signals. Dir. O -INPACK (PC Card I/O Mode except Ultra DMA Protocol Active) Input Acknowledge -DMARQ (PC Card Memory Mode -Ultra DMA Protocol Active) -DMARQ (PC Card I/O Mode -Ultra DMA Protocol Active) DMARQ (True IDE Mode) This signal is a DMA Request that is used for DMA data transfers between host and device. It shall be asserted by the device when it is ready to transfer data to or from the host. For Multiword DMA transfers, the direction of data transfer is controlled by -IORD and -IOWR. This signal is used in a handshake manner with (-)DMACK, i.e., the device shall wait until the host asserts (-)DMACK before negating (-)DMARQ, and re-asserting (-)DMARQ if there is more data to transfer. In PCMCIA I/O Mode, the -DMARQ shall be ignored by the host while the host is performing an I/O Read cycle to the device. The host shall not initiate an I/O Read cycle while -DMARQ is asserted by the device. In True IDE Mode, DMARQ shall not be driven when the device is not selected in the Drive-Head register. While a DMA operation is in progress, -CS0 (-CE1)and -CS1 (-CE2) shall be held negated and the width of the transfers shall be 16 bits. If there is no hardware support for True IDE DMA mode in the host, this output signal is not used and should not be connected at the host. In this case, the BIOS must report that DMA mode is not supported by the host so that device drivers will not attempt DMA mode operation. A host that does not support DMA mode and implements both PC Card and True IDE modes of operation need not alter the PC Card mode connections while in True IDE mode as long as this does not prevent proper operation in any mode. -IORD (PC Card Memory Mode except Ultra DMA Protocol Active) I 34 This signal is not used in this mode. This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the CompactFlash Storage Card when the card is configured to use the I/O interface. In True IDE Mode, while Ultra DMA mode is not active, this signal has the same function as in PC Card I/O Mode. In all modes when Ultra DMA mode DMA Read is active, this signal is asserted by the host to indicate that the host is ready to receive Ultra DMA data-in bursts. The host may negate – HDMARDY to pause an Ultra DMA transfer. In all modes when Ultra DMA mode DMA Write is active, this signal is the data out strobe generated by the host. Both the rising and falling edge of HSTROBE cause data to be latched by the device. The host may stop generating HSTROBE edges to pause an Ultra DMA data-out burst. -IORD (PC Card I/O Mode except Ultra DMA Protocol Active) -IORD (True IDE Mode – Except Ultra DMA Protocol Active) -HDMARDY (All Modes - Ultra DMA Protocol DMA Read) HSTROBE (All Modes - Ultra DMA Protocol DMA Write) Transcend Information Inc. 8 V1.1 TS2G~16GCF300 TS2G~16GCF300 Signal Name -IOWR (PC Card Memory Mode– Except Ultra DMA Protocol Active) 300X CompactFlash Card Pin 35 Description This signal is not used in this mode. Dir. I -IOWR (PC Card I/O Mode –Except Ultra DMA Protocol Active) The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the CompactFlash Storage Card controller registers when the CompactFlash Storage Card is configured to use the I/O interface. The clocking shall occur on the negative to positive edge of the signal (trailing edge). -IOWR (True IDE Mode – Except Ultra DMA Protocol Active) In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is supported, this signal must be negated before entering Ultra DMA mode protocol. In All Modes, while Ultra DMA mode protocol is active, the assertion of this signal causes the termination of the Ultra DMA data burst. STOP (All Modes – Ultra DMA Protocol Active) -OE (PC Card Memory Mode) I 9 This is an Output Enable strobe generated by the host interface. It is used to read data from the CompactFlash Storage Card in Memory Mode and to read the CIS and configuration registers. In PC Card I/O Mode, this signal is used to read the CIS and configuration registers. To enable True IDE Mode this input should be grounded by the host. -OE (PC Card I/O Mode) -ATA SEL (True IDE Mode) READY (PC Card Memory Mode) O 37 In Memory Mode, this signal is set high when the CompactFlash Storage Card is ready to accept a new data transfer operation and is held low when the card is busy. At power up and at Reset, the READY signal is held low (busy) until the CompactFlash Storage Card has completed its power up or reset function. No access of any type should be made to the CompactFlash Storage Card during this time. Note, however, that when a card is powered up and used with RESET continuously disconnected or asserted, the Reset function of the RESET pin is disabled. Consequently, the continuous assertion of RESET from the application of power shall not cause the READY signal to remain continuously in the busy state. -IREQ (PC Card I/O Mode) INTRQ (True IDE Mode) I/O Operation – After the CompactFlash Storage Card Card has been configured for I/O operation, this signal is used as -Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE Mode signal is the active high Interrupt Request to the host. Transcend Information Inc. 9 V1.1 TS2G~16GCF300 TS2G~16GCF300 Signal Name -REG (PC Card Memory Mode– Except Ultra DMA Protocol Active) 300X CompactFlash Card Pin 44 Description This signal is used during Memory Cycles to distinguish between Common Memory and Register (Attribute) Memory accesses. High for Common Memory, Low for Attribute Memory. In PC Card Memory Mode, when Ultra DMA Protocol is supported by the host and the host has enabled Ultra DMA protocol on the card the, host shall keep the -REG signal negated during the execution of any DMA Command by the device. The signal shall also be active (low) during I/O Cycles when the I/O address is on the Bus. In PC Card I/O Mode, when Ultra DMA Protocol is supported by the host and the host has enabled Ultra DMA protocol on the card the, host shall keep the -REG signal asserted during the execution of any DMA Command by the device. This is a DMA Acknowledge signal that is asserted by the host in response to (-)DMARQ to initiate DMA transfers. In True IDE Mode, while DMA operations are not active, the card shall ignore the (-)DMACK signal, including a floating condition. If DMA operation is not supported by a True IDE Mode only host, this signal should be driven high or connected to VCC by the host. A host that does not support DMA mode and implements both PC Card and True-IDE modes of operation need not alter the PC Card mode connections while in True-IDE mode as long as this does not prevent proper operation all modes. Dir. I Attribute Memory Select -REG (PC Card I/O Mode –Except Ultra DMA Protocol Active) -DMACK (PC Card Memory Mode when Ultra DMA Protocol Active) DMACK (PC Card I/O Mode when Ultra DMA Protocol Active) -DMACK (True IDE Mode) RESET (PC Card Memory Mode) I 41 The CompactFlash Storage Card is Reset when the RESET pin is high with the following important exception: The host may leave the RESET pin open or keep it continually high from the application of power without causing a continuous Reset of the card. Under either of these conditions, the card shall emerge from power-up having completed an initial Reset. The CompactFlash Storage Card is also Reset when the Soft Reset bit in the Card Configuration Option Register is set. RESET (PC Card I/O Mode) This signal is the same as the PC Card Memory Mode signal. -RESET (True IDE Mode) In the True IDE Mode, this input pin is the active low hardware reset from the host. VCC (PC Card Memory Mode) -- 13,38 +5 V, +3.3 V power. VCC (PC Card I/O Mode) This signal is the same for all modes. VCC (True IDE Mode) This signal is the same for all modes. Transcend Information Inc. 10 V1.1 TS2G~16GCF300 TS2G~16GCF300 Signal Name -VS1 -VS2 (PC Card Memory Mode) 300X CompactFlash Card Pin 33 40 Description Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host so that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is reserved by PCMCIA for a secondary voltage and is not connected on the Card. This signal is the same for all modes. Dir. O -VS1 -VS2 (PC Card I/O Mode) -VS1 -VS2 (True IDE Mode) This signal is the same for all modes. -WAIT (PC Card Memory Mode – Except Ultra DMA Protocol Active) O 42 The -WAIT signal is driven low by the CompactFlash Storage Card to signal the host to delay completion of a memory or I/O cycle that is in progress. This signal is the same as the PC Card Memory Mode signal. -WAIT (PC Card I/O Mode –Except Ultra DMA Protocol Active) IORDY (True IDE Mode – Except Ultra DMA Protocol Active) In True IDE Mode, except in Ultra DMA modes, this output signal may be used as IORDY. In all modes, when Ultra DMA mode DMA Write is active, this signal is asserted by the device during a data burst to indicate that the device is ready to receive Ultra DMA data out bursts. The device may negate -DDMARDY to pause an Ultra DMA transfer. In all modes, when Ultra DMA mode DMA Read is active, this signal is the data in strobe generated by the device. Both the rising and falling edge of DSTROBE cause data to be latched by the host. The device may stop generating DSTROBE edges to pause an Ultra DMA data in burst. -DDMARDY (All Modes – Ultra DMA Write Protocol Active) DSTROBE (All Modes – Ultra DMA Read Protocol Active) -WE (PC Card Memory Mode) I 36 This is a signal driven by the host and used for strobing memory write data to the registers of the CompactFlash Storage Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O Mode, this signal is used for writing the configuration registers. -WE (PC Card I/O Mode) -WE (True IDE Mode) WP (PC Card Memory Mode) Write Protect -IOIS16 (PC Card I/O Mode) O 24 In True IDE Mode, this input signal is not used and should be connected to VCC by the host. Memory Mode – The CompactFlash Storage Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. I/O Operation – When the CompactFlash Storage Card is configured for I/O Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle. -IOCS16 (True IDE Mode) Transcend Information Inc. 11 V1.1 TS2G~16GCF300 TS2G~16GCF300 Electrical Specification 300X CompactFlash Card The following tables indicate all D.C. Characteristics for the CompactFlash Storage Card. Unless otherwise stated, conditions are: Vcc = 5V ±10% Vcc = 3.3V ± 5% Absolute Maximum Conditions DC Characteristics CompactFlash Interface I/O at 5.0V Parameter Symbol Min. Max. Unit Remark High level input voltage Low level input voltage Pull up resistance2 Pull down resistance VIH VIL RPU RPD 4.0 2.92 0.8 1.70 73 97 50 50 CompactFlash Interface I/O at 3.3V Parameter Symbol Min. Max. Unit Remark High level input voltage Low level input voltage Pull up resistance2 Pull down resistance VIH VIL RPU RPD 2.4 2.05 0.6 1.25 141 172 52.7 47.5 1. Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW pins 2. Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW, CSEL (P35), PDIAG, DASP pins Transcend Information Inc. ─ ─ ─ ─ Supply Voltage High level output voltage Low level output voltage VCC VOH VOL 3.135 VCC 0.8 ─ ─ ─ ─ Supply Voltage High level output voltage Low level output voltage VCC VOH VOL 4.5 VCC 0.8 5.5 0.8 V V V V V V V KOhm KOhm Non-schmitt trigger 1 Schmitt trigger Non-schmitt trigger 1 Schmitt trigger 3.465 0.8 V V V V V V V KOhm KOhm Non-schmitt trigger 1 Schmitt trigger Non-schmitt trigger 1 Schmitt trigger 12 V1.1 TS2G~16GCF300 TS2G~16GCF300 Input Power 300X CompactFlash Card Input Leakage Current Input Characteristics for UDMA mode >4 In UDMA modes greater than 4, the following characteristics apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination. Table: Input Characteristics (UDMA Mode > 4) Parameter DC supply voltage to drivers Low to high input threshold High to low input threshold Difference between input thresholds: ((V+ current value) - (V-current value)) Average of thresholds: ((V+ current value) + (V-current value))/2 Symbol VDD3 V+ VVHYS VTHRAVG MIN 3.3 –8% 1.5 1.0 320 1.3 MAX Units 3.3% + 8% Volts 2.0 Volts 1.5 Volts Volts 1.7 Volts Output Drive Type Transcend Information Inc. 13 V1.1 TS2G~16GCF300 TS2G~16GCF300 Output Drive Characteristics for UDMA mode > 4 300X CompactFlash Card In UDMA modes greater than 4, the characteristics specified in the following table apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination. Table: Output Drive Characteristics (UDMA Mode > 4) Parameter Symbol MIN MAX Units DC supply voltage to drivers VDD3 3.3 –8% 3.3% + 8% Volts Voltage output high at -6 mA to +3 mA (at VoH2 the output shall VoH2 VDD3–0.51 VDD3+0.3 Volts be able to supply and sink current toVDD3) Voltage output low at 6 mA VoL2 0.51 Volts Notes: 1) IoLDASP shall be 12 mA minimum to meet legacy timing and signal integrity. 2) IoH value at 400 A is insufficient in the case of DMARQ that is pulled low by a 5.6 k resistor. 3) Voltage output high and low values shall be met at the source connector to include the effect of series termination. Ω μ 4) A device shall have less than 64 state. A of leakage current into a 6.2 K pull-down resistor while the INTRQ signal is in the released Signal Interface Electrical specifications shall be maintained to ensure data reliability. Additional requirements are necessary for Advanced Timing Modes and Ultra DMA modes operations. See next sections for additional information. Transcend Information Inc. 14 V1.1 Ω μ TS2G~16GCF300 TS2G~16GCF300 Item Signal -CE1 -CE2 -REG -IORD -IOWR -OE -WE RESET Status Signal READY -WAIT WP Card 10 300X CompactFlash Card Host 10 Control Signal Pull-up to VCC 500 K R 50 K and shall be sufficient to keep inputs inactive when the pins are not connected at the 1 host. In PCMCIA PC Card modes Pull-up to VCC 4 R 10 K . In True IDE mode, if DMA operation is supported by the host, Pull-down to Gnd R 5 5.6 K . -INPACK PC Card / True IDE hosts switch the pull-up to pull down in True IDE mode if DMA operation is supported. The PC Card mode Pull-up may be left active during True IDE mode if True IDE DMA operation is not supported. Address Data Bus Card Detect Voltage Sense Battery/Detect A[10:00] -CSEL D[15:00] -CD[2:1] -VS1 -VS2 BVD[2:1] 1. Connected to GND in the card Transcend Information Inc. 15 V1.1 Ω ≧ Pull-up R 50 K . 3.6 Ω ≦ ≦Ω Pull-up to Vcc 10 K Ω ≧ Ω Ω ≧ ≧ Ω ≧ ≧Ω Pull-up to VCC 500 K R 50 K . Ω ≧ ≧Ω Pull-up to VCC 500 K R 50 K . Ω ≧ ≧Ω 1,2 1,2,9, Pull-up to VCC R 10 K . 3 R 100K . TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card low state and 150 A high state, including pull-resistor. The socket shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC current 700 A low state and 150 A high state per socket). 2) Resistor is optional. 3) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 1100 A high state. 6) BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.” 7) Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450 A low state and 150 A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing 8) Data Signals: the host and each card shall present a load no larger than 50pF 10 at a DC current of 450 A and 150 A high state. The host and each card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 100pF with DC current 1.6mA low state and 300 A high state. This permits the host to wire two sockets in parallel without derating the card access speeds. 9) Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test. 10) Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the implementation of CF Advanced Timing modes and Ultra DMA modes respectively. Additional Requirements for CF Advanced Timing Modes The CF Advanced Timing modes include PC Card I/O and Memory modes that are 100ns or faster, PC Card Ultra DMA modes 3 or above and True IDE PIO Modes 5,6, Multiword DMA Modes 3,4 and True IDE Ultra DMA modes 3 or above. When operating in CF Advanced timing modes, the host shall conform to the following requirements: 1) Only one CF device shall be attached to the CF Bus. 2) The host shall not present a load of more than 40pF to the device for all signals, including any cabling. 3) The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported. Transcend Information Inc. 16 V1.1 μ μ μ and 150 A high state per socket). μ requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450 μ μ μ μ state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load A low state μ 5) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ μ 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load A low state and 100 A high state. A low μ 4) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ μ 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load A low state and 100 A high state. A low μ Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 A μ μ μ μ μ μ TS2G~16GCF300 TS2G~16GCF300 4) The -WAIT and IORDY signals shall be ignored by the host. 300X CompactFlash Card Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes Transcend Information Inc. 17 V1.1 TS2G~16GCF300 TS2G~16GCF300 Ultra DMA Electrical Requirements Host and Card signal capacitance limits for Ultra DMA operation 300X CompactFlash Card The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at 1 MHz. The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at 1 MHz. Series termination required for Ultra DMA operation Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table describes typical values for series termination at the host and the device. Table: Typical Series Termination for Ultra DMA Signal Host Termination Device Termination -IORD (-HDMARDY,HSTROBE) 22 ohm 82 ohm -IOWR (STOP) 22 ohm 82 ohm -CS0, -CS1 33 ohm 82 ohm A00, A01, A02 33 ohm 82 ohm -DMACK 22 ohm 82 ohm D15 through D00 33 ohm 33 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm IORDY (-DDMARDY, DSTROBE) 82 ohm 22 ohm -RESET 33 ohm 82 ohm NOTE Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA mode. Shows signals also requiring a pull-up or pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable impedance. − Transcend Information Inc. 18 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Table: Ultra DMA Termination with Pull-up or Pull down Example Printed Circuit Board (PCB) Trace Requirements for Ultra DMA On any PCB for a host or device supporting Ultra DMA: The longest D[15:00] trace shall be no more than 0.5" longer than either STROBE trace as measured from the IC pin to the connector. The shortest D[15:00] trace shall be no more than 0.5" shorter than either STROBE trace as measured from the IC pin to the connector. Ultra DMA Mode Cabling Requirement Operation in Ultra DMA mode requires a crosstalk suppressing cable. The cable shall have a grounded line between each signal line. For True IDE mode operation using a cable with IDE (ATA) type 40 pin connectors it is recommended that the host sense the cable type using the method described in the ANSI INCITS 361-2002 AT Attachment - 6 standard, to prevent use of Ultra DMA with a 40 conductor cable. Transcend Information Inc. 19 V1.1 TS2G~16GCF300 TS2G~16GCF300 Attribute Memory Read Timing Specification 300X CompactFlash Card Attribute Memory access time is defined as 300 ns. Detailed timing specs are shown in Table below Speed Version Item Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE Output Disable Time from OE Address Setup Time Output Enable Time from CE Output Enable Time from OE Data Valid from Address Change 300 ns Symbol tc(R) ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) tsu (A) ten(CE) ten(OE) tv(A) IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAVGL tELQNZ tGLQNZ tAXQX Min ns. 300 Max ns. 300 300 150 100 100 30 5 5 0 Note: All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -CE signal or both the -OE signal and the -WE signal shall be de-asserted between consecutive cycle operations. Transcend Information Inc. 20 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Configuration Register (Attribute Memory) Write Timing Specification The Card Configuration write access time is defined as 250 ns. Detailed timing specifications are shown in Table below. Table: Configuration Register (Attribute Memory) Write Timing Speed Version Item W rite Cycle Time W rite Pulse Width Address Setup Time W rite Recovery Time Data Setup Time for WE Data Hold Time Symbol tc(W) tw(WE) tsu(A) trec(WE) tsu(D-WEH) th(D) IEEE Symbol tAVAV tWLWH tAVWL tWMAX tDVWH tWMDX Min ns 250 150 30 30 80 30 250 ns Max ns Note: All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card . Transcend Information Inc. 21 V1.1 TS2G~16GCF300 TS2G~16GCF300 Common Memory Read Timing Specification Cycle Time Mode: Item Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup before OE CE Hold following OE W ait Delay Falling from OE Data Setup for Wait Release W ait Width Time2 Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) tv(WT-OE ) tv(WT) tw(WT) IEEE Symbol tGLQV tGHQZ tAVGL tGHAX tELGL tGHEH tGLWTV tQVWTH tWTLWTH 30 20 0 20 35 0 350 250 ns Min ns. Max ns. 125 100 15 15 0 15 35 0 120 ns Min ns. 300X CompactFlash Card 100 ns Min ns. Max ns. 50 50 10 15 0 15 35 0 350 80 ns Min ns. Ma x ns. 45 45 10 10 0 10 na na na 1 Max ns. 60 60 1 350 1 Notes:1) –WAIT is not supported in this mode. 2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally less in this specification. Transcend Information Inc. 22 V1.1 TS2G~16GCF300 TS2G~16GCF300 Common Memory Write Timing Specification Cycle Time Mode: Item Data Setup before WE Data Hold following WE W E Pulse Width Address Setup Time CE Setup before WE W rite Recovery Time Address Hold Time CE Hold following WE W ait Delay Falling from WE W E High from Wait Release W ait Width Time2 Symbol tsu (D-WEH) th(D) tw(WE) tsu(A) tsu(CE) trec(WE) th(A) th(CE) tv (WT-WE) tv(WT) tw (WT) IEEE Symbol tDVWH tWMDX tWLWH tAVWL tELWL tWMAX tGHAX tGHEH tWLWTV tWTHWH tWTLWTH 0 350 250 ns Min ns. 80 30 150 30 0 30 20 20 35 0 Max ns. 120 ns Min ns. 50 15 70 15 0 15 15 15 300X CompactFlash Card 100 ns Min ns. 40 10 60 10 0 15 15 15 Max ns. 80 ns Min ns. 30 10 55 10 0 15 15 10 Ma x ns. Max ns. 35 0 350 35 na1 350 na1 na1 Notes: 1) –WAIT is not supported in this mode. 2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally less in this specification. Transcend Information Inc. 23 V1.1 TS2G~16GCF300 TS2G~16GCF300 I/O Input (Read) Timing Specification Cycle Time Mode: Item Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG Setup before IORD REG Hold following IORD INPACK Delay Falling from IORD 3 300X CompactFlash Card 250 ns Min ns. Max ns. 100 0 165 70 20 5 20 5 0 0 45 45 35 35 35 0 350 5 120 ns Min ns. Max ns. 50 5 100 ns Min ns. Max ns. 50 5 80 ns Min ns. Ma x ns. 45 Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG (IORD) thREG (IORD) tdfINPACK (IORD) tdrINPACK (IORD) tdfIOIS16 (ADR) tdrIOIS16 (ADR) tdWT(IORD) td(WT) tw(WT) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH tlGLWTL tWTHQV tWTLWTH 70 25 10 5 10 5 0 0 na 1 65 25 10 5 10 5 0 0 na 1 55 15 10 5 10 5 0 0 na 1 INPACK Delay Rising from IORD3 IOIS16 Delay Falling from Address3 IOIS16 Delay Rising from Address3 W ait Delay Falling from IORD3 Data Delay from Wait Rising3 W ait Width Time3 na1 na1 na1 35 0 350 na1 na1 na1 35 0 350 na1 na1 na1 na2 na2 na 2 Transcend Information Inc. 24 V1.1 TS2G~16GCF300 TS2G~16GCF300 I/O Output (Write) Timing Specification Cycle Time Mode: Item Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR REG Setup before IOWR REG Hold following IOWR IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address W ait Delay Falling from IOWR IOWR high from Wait high W ait Width Time3 3 3 3 300X CompactFlash Card 255 ns Min ns. 60 30 165 70 20 5 20 5 0 35 35 35 0 350 0 Max ns. 120 ns Min ns. 20 10 70 25 20 5 20 5 0 na na 35 0 350 1 100 ns Min ns. 20 5 65 25 10 5 10 5 0 na na 35 1 80 ns Min ns. 15 5 55 15 10 5 10 5 0 na1 na na na 2 1 2 Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE (IOWR) thCE (IOWR) tsuREG (IOWR) thREG (IOWR) tdfIOIS16 (ADR) tdrIOIS16 (ADR) tdWT(IOWR) tdrIOWR (WT) tw(WT) IEEE Symbol tDVIWH tlWHDX tlWLIWH tAVIWL tlWHAX tELIWL tlWHEH tRGLIWL tlWHRGH tAVISL tAVISH tlWLWTL tWTJIWH tWTLWT H Max ns. Max ns. Ma x ns. 3 1 1 350 na2 Transcend Information Inc. 25 V1.1 TS2G~16GCF300 TS2G~16GCF300 True IDE PIO Mode Read/Write Timing Specification Item 0 t0 t1 t2 t2 t2i t3 t4 t5 t6 T6Z t7 t8 t9 tRD tA tB tC Cycle time (min) Address Valid to -IORD/-IOWR setup (min) -IORD/-IOWR (min) -IORD/-IOWR (min) Register (8 bit) -IORD/-IOWR recovery time (min) -IOWR data setup (min) -IOWR data hold (min) -IORD data setup (min) -IORD data hold (min) -IORD data tristate (max) Address valid to -IOCS16 assertion (max) Address valid to -IOCS16 released (max) -IORD/-IOWR to address valid hold Read Data Valid to IORDY active (min), if IORDY initially low after tA IORDY Setup time IORDY Pulse Width (max) IORDY assertion to release (max) 600 70 165 290 60 30 50 5 30 90 60 20 0 35 125 0 5 1 383 50 125 290 45 20 35 5 30 50 45 15 0 35 1250 5 2 240 30 100 290 30 15 20 5 30 40 30 10 0 35 1250 5 Mode 3 180 30 80 80 70 30 10 20 5 30 n/a n/a 10 0 35 1250 5 4 300X CompactFlash Card Note 5 100 15 65 65 25 20 5 15 5 20 n/a n/a 10 0 na na na 5 5 5 6 80 10 55 55 20 15 5 10 5 20 n/a n/a 10 0 na na na 5 5 5 120 25 70 70 25 20 10 20 5 30 n/a n/a 10 0 35 1250 5 1 1 1 1 2 4 4 3 Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met. 1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device’s identify device data. A CompactFlash Storage Card implementation shall support any legal host implementation. 2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer driven by the CompactFlash Storage Card (tri-state). 3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash Storage Card is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is not applicable. If the CompactFlash Storage Card is driving IORDY negated at the time tA after the activation of -IORD or -IOWR, then tRD shall be met and t5 is not applicable. 4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid. 5) IORDY is not supported in this mode. Transcend Information Inc. 26 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Transcend Information Inc. 27 V1.1 TS2G~16GCF300 TS2G~16GCF300 True IDE Multiword DMA Mode Read/Write Timing Specification 300X CompactFlash Card The timing diagram for True IDE DMA mode of operation in this section is drawn using the conventions in the ATA-4 specification. Signals are shown with their asserted state as high regardless of whether the signal is actually negative or positive true. Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the diagram inverted from their electrical states on the bus. Item tO tD tE tF tG tH tI tJ tKR tKW tLR tLW tM tN tZ Cycle time (min) -IORD / -IOWR asserted width (min) -IORD data access (max) -IORD data hold (min) -IORD/-IOWR data setup (min) -IOWR data hold (min) DMACK to –IORD/-IOWR setup (min) -IORD / -IOWR to -DMACK hold (min) -IORD negated width (min) -IOWR negated width (min) -IORD to DMARQ delay (max) -IOWR to DMARQ delay (max) CS(1:0) valid to –IORD / -IOWR CS(1:0) hold -DMACK Mode 0 (ns) 480 215 150 5 100 20 0 20 50 215 120 40 50 15 20 Mode 1 (ns) 150 80 60 5 30 15 0 5 50 50 40 40 30 10 25 Mode 2 (ns) 120 70 50 5 20 10 0 5 25 25 35 35 25 10 25 Mode 3 (ns) 100 65 50 5 15 5 0 5 25 25 35 35 10 10 25 Mode 4 (ns) 80 55 45 5 10 5 0 5 20 20 35 35 5 10 25 1 1 Note 1 1 Transcend Information Inc. 28 V1.1 TS2G~16GCF300 TS2G~16GCF300 True IDE Ultra DMA Mode Read/Write Timing Specification 300X CompactFlash Card Ultra DMA operations can take place in any of the three basic interface modes: PC Card Memory mode, PC Card I/O mode, and True IDE (the original mode to support UDMA). The usage of signals in each of the modes is shown in Table 24:Ultra DMA Signal Usage In Each Interface Mode Pin # (Non PC CARD MEM PC CARD IO MODE TRUE IDE MODE UDMA Signal Type UDMA MEM MODE UDMA UDMA UDMA MODE) DMARQ DMACK STOP HDMARDY(R) HSTROBE(W) DDMARDY(W) DSTROBE(R) DATA ADDRESS CSEL INTRQ Card Select Output Input Input Input 43 (-INPACK) 44 (-REG) 35 (-IOWR) 34 (-IORD) -DMARQ -DMACK STOP 1 -HDMARDY(R) 1, 1, 3, 4 2HSTROBE(W) -DDMARDY(W) 1, 3 1. 2. 4 DSTROBE(R) D[15:00] A[10:00] -CSEL READY -CE1 -CE2 -DMARQ DMACK STOP 1 -HDMARDY(R) 1, 2 1, 3, 4 HSTROBE(W) -DDMARDY(W) 1, 3 1. 2. 4 DSTROBE(R) D[15:00] A[10:00] -CSEL -INTRQ -CE1 -CE2 DMARQ -DMACK STOP 1 -HDMARDY(R) 1, 2 1, 3, 4 HSTROBE(W) -DDMARDY(W) 1, 3 1. 2. 4 DSTROBE(R) D[15:00] A[02:00] 5 -CSEL INTRQ -CS0 -CS1 Output Bidir Input Input Output Input 42 (-WAIT) … (D[15:00]) … (A[10:00]) 39 (-CSEL) 37 (READY) 7 (-CE1) 31 (-CE2) Notes:1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst. 2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command. 3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command. 4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge. 5) Address lines 03 through 10 are not used in True IDE mode. Several signal lines are redefined to provide different functions during an Ultra DMA data burst. These lines assume their UDMA definitions when: 1 2 3 4 an Ultra DMA mode is selected, and a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and the device asserts (-)DMARQ, and the host asserts (-)DMACK. These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of -DMACK by the host at the termination of an Ultra DMA data burst. With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst. During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data. Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to Transcend Information Inc. 29 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes. An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset. Both the host and device perform a CRC function during an Ultra DMA data burst. At the end of an Ultra DMA data burst the host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra DMA data bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error has occurred before data transfer for the command is complete, the device may complete the transfer and report the error or abort the command and report the error. NOTE -If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the host software driver regardless of whether all data requested by the command has been transferred. Transcend Information Inc. 30 V1.1 TS2G~16GCF300 TS2G~16GCF300 Name UDMA Mode 0 Min Max UDMA Mode 1 Min 160 73 153 10.0 5.0 48.0 6.2 10.0 5.0 48.0 6.2 0 48.0 230 0 20 0 10 20 0 20 70 75 160 20 0 20 50 0 20 50 125 20 0 20 50 20 0 20 70 70 100 20 0 20 50 150 0 20 0 10 20 0 20 70 60 100 20 0 20 50 200 150 0 20 0 10 20 0 20 55 60 100 20 0 20 50 Max UDMA Mode 2 Min 120 54 115 7.0 5.0 31.0 6.2 7.0 5.0 31.0 6.2 0 31.0 170 150 0 20 0 10 20 0 20 55 60 85 Max UDMA Mode 3 Min 90 39 86 7.0 5.0 20.0 6.2 7.0 5.0 20.0 6.2 0 20.0 130 100 0 20 0 10 20 0 20 Max UDMA Mode 4 Min 60 25 57 5.0 5.0 6.7 6.2 5.0 5.0 6.7 6.2 0 6.7 120 100 0 20 0 Max 300X CompactFlash Card UDMA Mode 5 Min 40 16.8 38 4.0 4.6 4.8 4.8 5.0 5.0 10.0 10.0 35 25 90 75 Max Sender Note 3 Sender Recipient Recipient Sender Sender Device Device Host Host Device Sender Device Note 4 Host Host 10 Note 5 Host Device 50 50 Host Sender Recipient 20 Device Device Host Sender Measure location (see Note 2) t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tFS tLI tMLI tUI tAZ tZAH tZAD tENV tRFS tRP tIORDYZ tZIORDY tACK tSS Notes: 240 112 230 15.0 5.0 70.0 6.2 15.0 5.0 70.0 6.2 0 70.0 1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V. 2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of tRFS, both STROBE and –DMARDY transitions are measured at the sender connector. 3) The parameter tCYC shall be measured at the recipient’s connector farthest from the sender. 4) The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an Transcend Information Inc. 31 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing response shall be measured at the same connector. 5) The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround. Name t2CYCTYP tCYC t2CYC tDS tDH tDVS tDVH tCS tCH tCVS tCVH tZFS tDZFS tFS tLI tMLI tUI tAZ tZAH tZAD tENV tRFS tRP tIORDYZ tZIORDY tACK tSS Comment Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) Data setup time at recipient (from data valid until STROBE edge) Data hold time at recipient (from STROBE edge until data may become invalid) Data valid setup time at sender (from data valid until STROBE edge) Data valid hold time at sender (from STROBE edge until data may become invalid) CRC word setup time at device CRC word hold time device CRC word valid setup time at host (from CRC valid until -DMACK negation) CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid) Time from STROBE output released-to-driving until the first transition of critical timing. Time from data output released-to-driving until the first transition of critical timing. First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) Limited interlock time Interlock time with minimum Unlimited interlock time Maximum time allowed for output drivers to release (from asserted or negated) Minimum delay time required for output drivers to assert or negate (from released) Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of -DMARDY) Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY) Maximum time before releasing IORDY Minimum time before driving IORDY Setup and hold times for -DMACK (before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) 6 4, 6 1 1 1 2, 5 2, 5 3 3 2 2 3 3 Notes Transcend Information Inc. 32 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Notes: 1) The parameters tUI, tMLI : (Ultra DMA Data-In Burst Device Termination Timing and Ultra DMA Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum. 2) 80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes greater than 2. 3) Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 4)For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDY- giving it a known state when released. 5)The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable. This could result in the minimum values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively. Name UDMA Mode 0 (ns) Min tDSIC tDHIC tDVSIC tDVHIC tDSIC tDHIC tDVSIC tDVHIC 14.7 4.8 72.9 9.0 Max UDMA Mode 1 (ns) Min 9.7 4.8 50.9 9.0 Max UDMA Mode 2 (ns) Min 6.8 4.8 33.9 9.0 Max UDMA Mode 3 (ns) Min 6.8 4.8 22.6 9.0 Max UDMA Mode4 (ns) Min 4.8 4.8 9.5 9.0 Max UDMA Mode 5 (ns) Min 2.3 2.8 6.0 6.0 Max Recipient IC data setup time (from data valid until STROBE edge) (see note 2) Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2) Sender IC data valid setup time (from data valid until STROBE edge) (see note 3) Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3) Notes: 1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V. 2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured through 1.5 V). 2) The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values. Transcend Information Inc. 33 V1.1 TS2G~16GCF300 TS2G~16GCF300 Name Comment 300X CompactFlash Card Min [V/ns] Max [V/ns] Notes SRISE SFALL Rising Edge Slew Rate for any signal Falling Edge Slew Rate for any signal 1.25 1.25 1 1 Note: 1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender’s series termination resistor and one half inch or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within one half inch of the connector. The test load and test points should then be soldered directly to the exposed source side connectors. The test loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the test point to ground. Slew rates shall be met for both capacitor values. Measurements shall be taken at the test point using a 100 Kohm, 1 Ghz or faster probe and a 500 MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge. Transcend Information Inc. 34 V1.1 TS2G~16GCF300 TS2G~16GCF300 Card Configuration 300X CompactFlash Card The CompactFlash Storage Cards is identified by appropriate information in the Card Information Structure (CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, these registers provide a method for accessing status information about the CompactFlash Storage Card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate use in I/O cards. Multiple Function CompactFlash Storage Cards Table: CompactFlash Storage Card Registers and Memory Space Decoding -CE2 1 X 1 0 0 X 1 0 0 X 1 1 1 0 0 -CE1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 -REG X 0 1 1 1 0 1 1 1 0 0 0 0 0 0 -OE X 0 0 0 0 1 1 1 1 0 1 0 1 0 1 -WE X 1 1 1 1 0 0 0 0 1 0 1 0 1 0 A10 X 0 X X X 0 X X X 0 0 X X X X A9 X 1 X X X 1 X X X 0 0 X X X X A8-A4 XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX A3 X X X X X X X X X X X X X X X A2 X X X X X X X X X X X X X X X A1 X X X X X X X X X X X X X X X A0 X 0 X X 0 0 X X 0 0 0 1 1 X X SELECTED SPACE Standby and UDMA transfer Configuration Registers Read Common Memory Read (8 Bit D7-D0) Common Memory Read (8 Bit D15-D8) Common Memory Read (16 Bit D15-D0) Configuration Registers Write Common Memory Write (8 Bit D7-D0) Common Memory Write (8 Bit D15-D8) Common Memory Write (16 Bit D15-D0) Card Information Structure Read Invalid Access (CIS Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) Transcend Information Inc. 35 V1.1 TS2G~16GCF300 TS2G~16GCF300 STOP -IOW R X X 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 -DMARDY -IORD (R)-WAIT (W) X X X 1 1 0 X 1 0 1 0 0 1 0 1 1 1 1 STROBE -WAIT (R)-IORD (W) X 1 1 1 1 1 / or \ 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 / 1 1 300X CompactFlash Card Table: PC Card Memory Mode UDMA Function -CE2 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -CE1 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -DMARQ -INPACK 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 -DMACK -REG X 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 / 1 DMA CMD No YES YES YES YES YES YES RD RD WR WR RD RD YES YES YES YES YES A10A00 XX XX XX Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Operation Standby Device UDMA Transfer Request (Assert DMARQ) Host Acknowledge Preparation Host Acknowledge Preparation DMA Acknowledge (Stopped) Burst Initiation / Active Burst Transfer Data In Burst Host Pause Data In Burst Device Pause Data Out Burst Device Pause Data Out Burst Host Pause Device Initiating BurstTermination Host Acknowledement of Device Initiated Burst Termination Host Initiating BurstTermination Device Acknowledging Host Initiated Burst Termination Device Aligning STROBE to Asserted before CRC Transfer CRC Data Transfer for UDMA Burst Burst Completed Table: CompactFlash Storage Card Configuration Registers Decoding -CE2 X X X X X X X X -CE1 0 0 0 0 0 0 0 0 -REG 0 0 0 0 0 0 0 0 -OE 0 1 0 1 0 1 0 1 -WE 1 0 1 0 1 0 1 0 A10 0 0 0 0 0 0 0 0 A9 1 1 1 1 1 1 1 1 A8-A4 00 00 00 00 00 00 00 00 A3 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 0 0 0 0 0 0 0 SELECTED REGISTER Configuration Option Reg Read Configuration Option Reg Write Card Status Register Read Card Status Register Write Pin Replacement Register Read Pin Replacement Register Write Socket and Copy Register Read Socket and Copy Register Write Transcend Information Inc. 36 V1.1 TS2G~16GCF300 TS2G~16GCF300 Attribute Memory Function 300X CompactFlash Card Attribute memory is a space where CompactFlash Storage Card identification and configuration information are stored, and is limited to 8 bit wide accesses only at even addresses. The card configuration registers are also located here. For CompactFlash Storage Cards, the base address of the Card configuration registers is 200h. Table: Attribute Memory Function Function Mode Standby Mode Standby Mode UDMA Operation (see section 4.3.18: Ultra DMA Mode Read/Write Timing Specification) Read Byte Access CIS ROM (8 bits) W rite Byte Access CIS (8 bits) (Invalid) Read Byte Access Configuration CompactFlash Storage (8 bits) W rite Byte Access Configuration CompactFlash Storage (8 bits) Read Word Access CIS (16 bits) W rite Word Access CIS (16 bits) (Invalid) Read Word Access Configuration CompactFlash Storage (16 bits) W rite Word Access Configuration CompactFlash Storage (16 bits) DMA CMD Don’t Care No Yes -REG H X L1 -CE2 H H H -CE1 H H H A10 X X X A9 X X X A0 X X X -OE X X H -WE X X H D15-D8 High Z High Z Odd Byte D7-D0 High Z High Z Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte No No No L L L H H H L2 L2 L L L L L L H L L L L2 H L H L2 H High Z Don’t Care High Z Don’t Care Not Valid Don’t Care Not Valid Don’t Care No No No No L L L L H L2 L2 L2 L L2 L2 L2 L L L L H L L H L X X X H L2 H L2 L H L2 H No L L2 L2 L H X H L2 Transcend Information Inc. 37 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Configuration Option Register (Base + 00h in Attribute Memory) Transcend Information Inc. 38 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Card Configuration and Status Register (Base + 02h in Attribute Memory) Transcend Information Inc. 39 V1.1 TS2G~16GCF300 TS2G~16GCF300 Pin Replacement Register (Base + 04h in Attribute Memory) 300X CompactFlash Card Transcend Information Inc. 40 V1.1 TS2G~16GCF300 TS2G~16GCF300 Socket and Copy Register (Base + 06h in Attribute Memory) 300X CompactFlash Card Transcend Information Inc. 41 V1.1 TS2G~16GCF300 TS2G~16GCF300 I/O Transfer Function 300X CompactFlash Card The I/O transfer to or from the CompactFlash Storage can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the signal -IOIS16 is asserted by the CompactFlash Storage. Otherwise, the -IOIS16 signal is de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the CompactFlash Storage, the system shall generate a pair of 8 bit references to access the word‘s even byte and odd byte. The CompactFlash Storage Card permits both 8 and 16 bit accesses to all of its I/O addresses, so -IOIS16 is asserted for all addresses to which the CompactFlash Storage responds. The CompactFlash Storage Card may request the host to extend the length of an input cycle until data is ready by asserting the -WAIT signal at the start of the cycle. Table: PCMCIA Mode I/O Function Function Code Standby Mode UDMA Write UDMA Read Byte Input Access (8 bits) Byte Output Access (8 bits) W ord Input Access (16 bits) W ord Output Access (16 bits) I/O Read Inhibit I/O Write Inhibit High Byte Input Only (8 bits) High Byte Output Only (8 bits) DMA CMD No Write Read X X X X X X X X -REG X H H L L L L L L H H L L -CE2 H H H H H H H L L X X L L -CE1 H H H L L L L L L X X H H A0 X X X L H L H L L X X X X -IORD X X X L L H H L H L H L H -IOWR X X X H H L L H L H L H L D15-D8 High Z Odd Byte Odd Byte High Z High Z Don’t Care Don’t Care Odd-Byte Odd-Byte Don’t Care High Z Odd-Byte Odd-Byte D7-D0 High Z Even Byte Even Byte Even-Byte Odd-Byte Even-Byte Odd-Byte Even-Byte Even-Byte Don’t Care High Z High Z Don’t Care Transcend Information Inc. 42 V1.1 TS2G~16GCF300 TS2G~16GCF300 -DMARDY -IORD (R)-WAIT (W) X X X 1 1 0 X 1 0 1 0 0 1 0 1 1 1 1 STROBE -WAIT (R)-IORD (W) X 1 1 1 1 1 / or \ 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 / 1 1 300X CompactFlash Card Table: PC Card I/O Mode UDMA Function -CE2 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -CE1 1 X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -DMARQ -INPACK 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 DMACK -REG X 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 \ 0 STOP -IOWR X X 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 DMA CMD No YES YES YES YES YES YES RD RD WR WR RD RD YES YES YES YES YES A10A00 XX XX XX Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Standby Operation Device UDMA Transfer Request (Assert DMARQ) Host Acknowledge Preparation Host Acknowledge Preparation DMA Acknowledge (Stopped) Burst Initiation / Active Burst Transfer Data In Burst Host Pause Data In Burst Device Pause Data Out Burst Device Pause Data Out Burst Host Pause Device Initiating BurstTermination Host Acknowledement of Device Initiated Burst Termination Host Initiating BurstTermination Device Acknowledging Host Initiated Burst Termination Device Aligning STROBE to Asserted before CRC Transfer CRC Data Transfer for UDMA Burst Burst Completed Transcend Information Inc. 43 V1.1 TS2G~16GCF300 TS2G~16GCF300 Common Memory Transfer Function 300X CompactFlash Card The Common Memory transfer to or from the CompactFlash Storage can be either 8 or 16 bits. Table: Common Memory Function Function Code Standby Mode Byte Read (8 bits) Byte Write (8 bits) W ord Read (16 bits) W ord Write (16 bits) DMA None Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Write Read -REG X H H H H H H -CE2 H H H H H L L -CE1 H L L L L L L A0 X L H L H X X -OE X L L H H L H -WE X H H L L H L D15-D8 High Z High Z High Z Don’t Care Don’t Care Odd-Byte Odd-Byte D7-D0 High Z Even-Byte Odd-Byte Even-Byte Odd-Byte Even-Byte Even-Byte Odd Byte Read Only (8 bits) H L H X L H Odd-Byte High Z Odd Byte Write Only (8 bits) Ultra DMA Write Ultra DMA Read H L L L H H H H H X X X H H H L H H Odd-Byte Odd-Byte Odd-Byte Don’t Care Even-Byte Even-Byte Transcend Information Inc. 44 V1.1 TS2G~16GCF300 TS2G~16GCF300 True IDE Mode I/O Transfer Function 300X CompactFlash Card The CompactFlash Storage Card can be configured in a True IDE Mode of operation. The CompactFlash Storage Card is configured in this mode only when the -OE input signal is grounded by the host during the power off to power on cycle. Optionally, CompactFlash Storage Cards may support the following optional detection methods: 1. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to PCMCIA mode upon detecting a high level on the pin. 2. The card is permitted to re-arbitrate the interface mode determination following a transition of the (-)RESET pin. 3. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to True IDE mode upon detection of a continuous low level on pin for an extended period of time. Table: True IDE Mode I/O Function defines the function of the operations for the True IDE Mode. Transcend Information Inc. 45 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Host Configuration Requirements for Master/Slave or New Timing Modes The CF Advanced Timing modes include PCMCIA PC Card style I/O modes that are faster than the original 250 ns cycle time. These modes are not supported by the PCMCIA PC Card specification nor CF by cards based on revisions of the CF specification before Revision 3.0. Hosts shall ensure that all cards accessed through a common electrical interface are capable of operation at the desired, faster than 250 ns, I/O mode before configuring the interface for that I/O mode. Advanced Timing modes are PCMCIA PC Card style I/O modes that are 100 ns or faster, PC Card Memory modes that are 100ns or faster, True IDE PIO Modes 5,6 and Multiword DMA Modes 3,4. These modes are permitted to be used only when a single card is present and the host and card are connected directly, without a cable exceeding 0.15m in length. Consequently, the host shall not configure a card into an Advanced Timing Mode if two cards are sharing I/O lines, as in Master/Slave operation, nor if it is constructed such that a cable exceeding 0.15 meters is required to connect the host to the card. The load presented to the Host by cards supporting Ultra DMA is more controlled than that presented by other CompactFlash cards. Therefore, the use of a card that does not support Ultra DMA in a Master/Slave arrangement with a Ultra DMA card can affect the critical timing of the Ultra DMA transfers. The host shall not configure a card into Ultra DMA mode when a card not supporting Ultra DMA is also present on the same interface When the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported by both cards, but to achieve maximum performance it should use its highest performance mode that is also supported by both cards. Metaformat Overview The goal of the Metaformat is to describe the requirements and capabilities of the CompactFlash Storage Card as thoroughly as possible. This includes describing the power requirements, IO requirements, memory requirements, manufacturer information and details about the services provided. Table: Sample Device Info Tuple Information for Extended Speeds Note: The value “1” defined for D3 of the N+0 words indicates that no write-protect switch controls writing the ATA registers. The value “0” defined for D7 in the N+2 words indicates that there is not more than a single speed extension byte. Transcend Information Inc. 46 V1.1 TS2G~16GCF300 TS2G~16GCF300 CF-ATA Drive Register Set Definition and Protocol 300X CompactFlash Card The CompactFlash Storage Card can be configured as a high performance I/O device through: a) The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ). b) Any system decoded 16 byte I/O block using any available IRQ. c) Memory space. The communication to or from the CompactFlash Storage Card is done using the Task File registers, which provide all the necessary registers for control and status information related to the storage medium. The PCMCIA interface connects peripherals to the host using four register mapping methods. Table 39 is a detailed description of these methods: Transcend Information Inc. 47 V1.1 TS2G~16GCF300 TS2G~16GCF300 I/O Primary and Secondary Address Configurations Table: Primary and Secondary I/O Decoding 300X CompactFlash Card Transcend Information Inc. 48 V1.1 TS2G~16GCF300 TS2G~16GCF300 Contiguous I/O Mapped Addressing 300X CompactFlash Card W hen the system decodes a contiguous block of I/O registers to select the CompactFlash Storage Card, the registers are accessed in the block of I/O space decoded by the system as follows: Table: Contiguous I/O Decoding Transcend Information Inc. 49 V1.1 TS2G~16GCF300 TS2G~16GCF300 Memory Mapped Addressing 300X CompactFlash Card W hen the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2K bytes as follows: True IDE Mode Addressing W hen the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows: Transcend Information Inc. 50 V1.1 TS2G~16GCF300 TS2G~16GCF300 CF-ATA Registers 300X CompactFlash Card The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the “task file.” Data Register (Address - 1F0h[170h];Offset 0,8,9) The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register. Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only) This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low and -CE1 high. Bit 7 (BBK/ICRC): this bit is set when a Bad Block is detected. This bit is also set when an interface CRC error is detected in True IDE Ultra DMA modes of operation. Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered. Bit 5: this bit is 0. Bit 4 (IDNF): the requested sector ID is in error or cannot be found. Bit 3: this bit is 0. Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued. Bit 1 This bit is 0. Bit 0 (AMNF) This bit is set in case of a general error. Transcend Information Inc. 51 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only) This register provides information regarding features of the CompactFlash Storage Card that the host can utilize. This register is also accessed in PC Card modes on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high. Sector Count Register (Address - 1F2h[172h]; Offset 2) This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. Sector Number (LBA 7-0) Register (Address - 1F3h[173h]; Offset 3) This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any CompactFlash Storage Card data access for the subsequent command. 6.1.5.5 Cylinder Low (LBA 15-8) Register (Address - 1F4h[174h]; Offset 4) This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address. Cylinder High (LBA 23-16) Register (Address - 1F5h[175h]; Offset 5) This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. Drive/Head (LBA 27-24) Register (Address 1F6h[176h]; Offset 6) The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. Bit 7: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become obsolete in a future revision of the specification. This bit is ignored by some controllers in some commands. Bit 6: LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows: LBA7-LBA0: Sector Number Register D7-D0. LBA15-LBA8: Cylinder Low Register D7-D0. LBA23-LBA16: Cylinder High Register D7-D0. LBA27-LBA24: Drive/Head Register bits HS3-HS0. Bit 5: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become obsolete in a future revisions of the specification. This bit is ignored by some controllers in some commands. Bit 4 (DRV): DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card) 1 is selected. Setting this bit to 1 is obsolete in PCMCIA modes of operation. If the obsolete functionality is support by a CF Storage Card, the CompactFlash Storage Card is set to be Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration register. Transcend Information Inc. 52 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is Bit 27 in the Logical Block Address mode. Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit 26 in the Logical Block Address mode. Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode. Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode. Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh) These registers return the CompactFlash Storage Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows: Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command. Bit 5 (DWF): This bit, if set, indicates a write fault has occurred. Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready. Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. Bit 1 (IDX): This bit is always set to 0. Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. It is recommended that media access commands (such as Read Sectors and Write Sectors) that end with an error condition should have the address of the first sector in error in the command block registers. Transcend Information Inc. 53 V1.1 TS2G~16GCF300 TS2G~16GCF300 Device Control Register (Address - 3F6h[376h]; Offset Eh) 300X CompactFlash Card This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows: Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0. Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0. Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0. Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0. Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0. Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’ Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset. Bit 0: this bit is ignored by the CompactFlash Storage Card. Transcend Information Inc. 54 V1.1 TS2G~16GCF300 TS2G~16GCF300 Card (Drive) Address Register (Address 3F7h[377h]; Offset Fh) 300X CompactFlash Card This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host’s I/O space because of potential conflicts on Bit 7. Bit 7: this bit is unknown. Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Storage Card. Following are some possible solutions to this problem for the PCMCIA implementation: 1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time. 3) Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7h/377h when a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of I/O address 3F7h/377h when a floppy controller is installed. 4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to I/O locations 3F7h and 377h. With either of these implementations, the host software shall not attempt to use information in the Drive Address Register. Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1. Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register. Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register. Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register. Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register. Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected. Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected. Transcend Information Inc. 55 V1.1 TS2G~16GCF300 TS2G~16GCF300 CF-ATA Command Set 300X CompactFlash Card CF-ATA Command Set summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each. Command 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Check Power Mode Execute Drive Diagnostic Erase Sector Flush Cache Format Track Identify Device Idle Idle Immediate Initialize Drive Parameters Key Management Structure Read Key Management Read Keying Material Key Management Change Key Management Value NOP Read Buffer Read DMA Read Long Sector Read Multiple Read Sector(s) Read Verify Sector(s) Recalibrate Request Sense Security Disable Password Security Erase Prepare Security Erase Unit Security Freeze Lock Security Set Password Security Unlock Seek Code E5 or 98h 90h C0h E7h 50h ECh E3h or 97h E1h or 95h 91h B9 (Feature 0-127) B9 (Feature 80) B9 (Feature 81) 00h E4h C8h 22h or 23h C4h 20h or 21h 40h or 41h 1Xh 03h F6h F3h F4h F5h F1h F2h 7Xh FR – – – – – – – – – Y Y Y – – – – – – – – – – – – – – – – Y Y Y – – – – – – – – – SC – – Y – Y – Y – Y Y Y Y – – Y SN – – Y – – – – – – Y Y Y – – Y Y Y Y Y – – – – – – – – Y CY – – Y – Y – – – – Y Y Y – – Y Y Y Y Y – – – – – – – – Y DH Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y – – – – – – – – Y LBA – – Y – Y – – – – – – – – – Y Y Y Y Y Status Support Support Support Support Support Support Support Support Support NOT Support NOT Support NOT Support Support Support Support NOT Support Support Support Support Support Support Support Support Support Support Support Support Support #2 #1 #1 #1 Note Transcend Information Inc. 56 V1.1 TS2G~16GCF300 TS2G~16GCF300 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Set Feature Set Multiple Mode Set Sleep Mode Standby Standby Immediate Translate Sector W ear Level W rite Buffer W rite DMA W rite Long Sector W rite Multiple W rite Multiple w/o Erase W rite Sector(s) W rite Sector(s) w/o Erase W rite Verify EFh C6h E6h or 99h E2 or 96h E0 or 94h 87h F5h E8h CAh 32h or 33h C5h CDh 30h or 31h 38h 3Ch Y – – – – – – – – – – – – – – – Y – – – Y – – Y – Y Y Y Y Y – – – – – Y – – Y Y Y Y Y Y Y – – – – – Y – – Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y – – – – – Y – – Y Y Y Y Y Y Y 300X CompactFlash Card Support Support Support Support Support Support Support Support Support Not Support Support Support Support Support Support #2 #1: This command is optional, depending on the key Management scheme in use. #2: Use of this command is not recommended by CFA. Definitions FR = Features Register SC =Sector Count register (00H to FFH, 00H means 256 sectors) SN = Sector Number register CY = Cylinder Low/High register DH = Head No. (0 to 15) of Drive/Head register LBA = Logic Block Address Mode Support – = Not used for the command Y = Used for the command Transcend Information Inc. 57 V1.1 TS2G~16GCF300 TS2G~16GCF300 Check Power Mode - 98h or E5h 300X CompactFlash Card If the CompactFlash Storage Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt. If the CompactFlash Storage Card is in Idle mode, the CompactFlash Storage Card sets BSY, sets the Sector Count Register to FFh, clears BSY and generates an interrupt. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 3 2 1 0 98h or E5h Drive X X X X X X Execute Drive Diagnostic - 90h W hen the diagnostic command is issued in a PCMCIA configuration mode, this command runs only on the CompactFlash Storage Card that is addressed by the Drive/Head register. This is because PCMCIA card interface does not allows for direct inter-drive communication (such as the ATA PDIAG and DASP signals). When the diagnostic command is issued in the True IDE Mode, the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with status for both devices. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 90h X 3 2 1 0 Diagnostic Codes are returned in the Error Register at the end of the command. Code 01h 02h 03h 04h 05h 8Xh Error Type No Error Detected Formatter Device Error Sector Buffer Error ECC Circuitry Error Controlling Microprocessor Error Slave Error in True IDE Mode Transcend Information Inc. 58 V1.1 TS2G~16GCF300 TS2G~16GCF300 Erase Sector(s) - C0h 300X CompactFlash Card This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write Multiple without Erase command. There is no data transfer associated with this command but a Write Fault error status can occur. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive 7 6 5 4 C0h Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) Sector Number (LBA 7-0) Sector Count X Flush Cache – E7h This command causes the card to complete writing data from its cache. The card returns status with RDY=1 and DSC=1 after the data in the write cache buffer is written to the media. If the Compact Flash Storage Card does not support the Flush Cache command, the Compact Flash Storage Card shall return command aborted. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E7h X 3 2 1 0 Format Track - 50h This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFh or 00h). To remain host backward compatible, the CompactFlash Storage Card expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the CompactFlash Storage Card. If LBA=1 then the number of sectors to format is taken from the Sec Cnt register (0=256). The use of this command is not recommended. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) 1 LBA 1 Drive 7 6 5 4 50h Head (LBA 27-24) 3 2 1 0 Cylinder High (LBA 23-16) Cylinder Low (LBA 15-8) X (LBA 7-0) Count (LBA mode only) X Transcend Information Inc. 59 V1.1 TS2G~16GCF300 TS2G~16GCF300 Identify Device – Ech Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X Drive X X X X X 7 6 5 4 ECh 3 2 300X CompactFlash Card 1 0 X The Identify Device command enables the host to receive parameter information from the CompactFlash Storage Card. This command has the same protocol as the Read Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table as below. All reserved bits or words are zero. Hosts should not depend on Obsolete words in Identify Device containing 0. Table 47 specifies each field in the data returned by the Identify Device Command. In Table as below, X indicates a numeric nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive. Word Address 0 1 2 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 Default Value 848Ah 0XXX XXXXh 0000h 00XXh 0000h 0000h XXXXh XXXXh XXXXh aaaa 0000h 0000h 0004h aaaa aaaa XXXXh 0000h XX00h 0000h Total Bytes 2 2 2 2 2 2 2 2 4 2 20 2 2 2 8 40 2 2 2 2 Data Field Type Information General configuration - signature for the CompactFlash 0 lash Storage Card General configuration – Bit Significant with ATA-4 definitions. Default number of cylinders Reserved Default number of heads Obsolete Obsolete Default number of sectors per track Number of sectors per card (Word 7 = MSW, Word 8 = LSW) Obsolete Serial number in ASCII (Right Justified) Obsolete Obsolete Number of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII. Big Endian Byte Order in Word Model number in ASCII (Left Justified) Big Endian Byte Order in Word Maximum number of sectors on Read/Write Multiple command Reserved Capabilities Reserved Transcend Information Inc. 60 V1.1 TS2G~16GCF300 TS2G~16GCF300 Word Address 51 52 53 54 55 56 57-58 59 60-61 62 63 64 65 66 67 68 69-79 80-81 82-84 85-87 88 89 90 91 92-127 128 129-159 160 161 162 163 164 165-167 168-255 Default Value 0X00h 0000h 000Xh XXXXh XXXXh XXXXh XXXXh 01XXh XXXXh 0000h 0X0Xh 00XXh XXXXh XXXXh XXXXh XXXXh 0000h 0000h XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000h XXXXh 0000h XXXXh 0000h 0000h XXXXh XXXXh 0000h 0000h Total Bytes 2 2 2 2 2 2 4 2 4 2 2 2 2 2 2 2 20 4 6 6 2 2 2 2 72 2 64 2 2 2 2 2 6 158 Obsolete Field Validity Current numbers of cylinders Current numbers of heads Current sectors per track 300X CompactFlash Card Data Field Type Information PIO data transfer cycle timing mode Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA Mode Reserved Multiword DMA transfer. In PC Card modes this value shall be 0h Advanced PIO modes supported Minimum Multiword DMA transfer cycle time per word. In PC Card modes this value shall be 0h Recommended Multiword DMA transfer cycle time. In PC Card modes this value shall be 0h Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved Reserved – CF cards do not return an ATA version Features/command sets supported Features/command sets enabled Ultra DMA Mode Supported and Selected Time required for Security erase unit completion Time required for Enhanced security erase unit completion Current Advanced power management value Reserved Security status Vendor unique bytes Power requirement description Reserved for assignment by the CFA Key management schemes supported CF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode Capability Reserved for assignment by the CFA Reserved Transcend Information Inc. 61 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Word 0: General Configuration This field indicates the general characteristics of the device. When Word 0 of the Identify drive information is 848Ah then the device is a CompactFlash Storage Card and complies with the CFA specification and CFA command set. It is recommended that PCMCIA modes of operation report only the 848Ah value as they are always intended as removable devices. Bits 15-0: CF Standard Configuration Value Word 0 is 848Ah. This is the recommended value of Word 0. Some operating systems require Bit 6 of Word 0 to be set to 1 (Non-removable device) to use the card as the root storage device. The Card must be the root storage device when a host completely replaces conventional disk storage with a CompactFlash Card in True IDE mode. To support this requirement and provide capability for any future removable media Cards, alternatehandling of Word 0 is permitted. Bits 15-0: CF Preferred Alternate Configuration Values 044Ah: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and Removable Device while preserving all Retired bits in the word. 0040h: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and Removable Device while zeroing all Retired bits in the word Bit 15-12: Configuration Flag If bits 15:12 are set to 8h then Word 0 shall be 848Ah. If bits 15:12 are set to 0h then Bits 11:0 are set using the definitions below and the Card is required to support for the CFA command set and report that in bit 2 of Word 83. Bit 15:12 values other than 8h and 0h are prohibited. Bits 11-8: Retired These bits have retired ATA bit definitions. It is recommended that the value of these bits be either the preferred value of 0h or the value of 4h that preserves the corresponding bits from the 848Ah CF signature value. Bit 7: Removable Media Device If Bit 7 is set to 1, the Card contains media that can be removed during Card operation. If Bit 7 is set to 0, the Card contains nonremovable media. Bit 6: Not Removable Controller and/or Device Alert! This bit will be considered for obsolescence in a future revision of this standard. If Bit 6 is set to 1, the Card is intended to be nonremovable during operation. If Bit 6 is set to 0, the Card is intended to be removable during operation. Bits 5-0: Retired/Reserved Alert! Bit 2 will be considered for definition in a future revision of this standard and shall be 0 at this time. Bits 5-1 have retired ATA bit definitions. Bit 2 shall be 0. Bit 0 is Reserved and shall be 0. It is recommended that the value of bits 5-0 be either the preferred value of 00h or the value of 0Ah that preserves the corresponding bits from the 848Ah CF signature value. Word 1: Default Number of Cylinders This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders. Word 3: Default Number of Heads This field contains the number of translated heads in the default translation mode. Word 6: Default Number of Sectors per Track This field contains the number of sectors per track in the default translation mode. Transcend Information Inc. 62 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Words 7-8: Number of Sectors per Card This field contains the number of sectors per CompactFlash Storage Card. This double word value is also the first invalid address in LBA translation mode. Words 10-19: Serial Number This field contains the serial number for this CompactFlash Storage Card and is right justified and padded with spaces (20h). Word 22: ECC Count This field defines the number of ECC bytes used on each sector in the Read and Write Long commands. This value shall be set to 0004h. Words 23-26: Firmware Revision This field contains the revision of the firmware for this product. Words 27-46: Model Number This field contains the model number for this product and is left justified and padded with spaces (20h). Word 47: Read/Write Multiple Sector Count Bits 15-8 shall be the recommended value of 80h or the permitted value of 00h. Bits 7-0 of this word define the maximum number of sectors per block that the CompactFlash Storage Card supports for Read/Write Multiple commands. Word 49: Capabilities Bit 13: Standby Timer If bit 13 is set to 1 then the Standby timer is supported as defined by the IDLE command If bit 13 is set to 0 then the Standby timer operation is defined by the vendor. Bit 11: IORDY Supported If bit 11 is set to 1 then this CompactFlash Storage Card supports IORDY operation. If bit 11 is set to 0 then this CompactFlash Storage Card may support IORDY operation. Bit 10: IORDY may be disabled Bit 10 shall be set to 0, indicating that IORDY may not be disabled. Bit 9: LBA supported Bit 9 shall be set to 1, indicating that this CompactFlash Storage Card supports LBA mode addressing. CF devices shall support LBA addressing. Bit 8: DMA Supported If bit 8 is set to 1 then Read DMA and Write DMA commands are supported. Bit 8 shall be set to 0. Read/Write DMA commands are not currently permitted on CF cards. PIO Data Transfer Cycle Timing Mode The PIO transfer timing for each CompactFlash Storage Card falls into modes that have unique parametric timing specifications. The value returned in Bits 15-8 shall be 00h for mode 0, 01h for mode 1, or 02h for mode 2. Values 03h through FFh are reserved. Translation Parameters Valid Bit 0 shall be set to 1 indicating that words 54 to 58 are valid and reflect the current number of cylinders, heads and sectors. If bit 1 of word 53 is set to 1, the values in words 64 through 70 are valid. If this bit is cleared to 0, the values reported in words 64-70 are not valid. Any CompactFlash Storage Card that supports PIO mode 3 or above shall set bit 1 of word 53 to one and support the fields contained in words 64 through 70. Current Number of Cylinders, Heads, Sectors/Track These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode. Current Capacity This field contains the product of the current cylinders times heads times sectors. Transcend Information Inc. 63 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Multiple Sector Setting Bits 15-9 are reserved and shall be set to 0. Bit 8 shall be set to 1 indicating that the Multiple Sector Setting is valid. Bits 7-0 are the current setting for the number of sectors that shall be transferred per interrupt on Read/Write Multiple commands. Total Sectors Addressable in LBA Mode This field contains the total number of user addressable sectors for the CompactFlash Storage Card in LBA mode only. Multiword DMA transfer Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA mode selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Only one of bits may be set to one in this field by the CompactFlash Storage Card to indicate the multiword DMA mode which is currently selected. Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one, indicates that Multiword DMA mode 0 has been selected. Bit 9, if set to one, indicates that Multiword DMA mode 1 has been selected. Bit 10, if set to one, indicates that Multiword DMA mode 2 has been selected. Selection of Multiword DMA modes 3 and above are specific to CompactFlash are reported in word 163, Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings. Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate the Multiword DMA modes it is capable of supporting. Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage Card supports Multiword DMA mode 0. Bit 1, if set to one, indicates that the CompactFlash Storage Card supports Multiword DMA modes 1 and 0. Bit 2, if set to one, indicates that the CompactFlash Storage Card supports Multiword DMA modes 2, 1 and 0. Support for Multiword DMA modes 3 and above are specific to CompactFlash are reported in word 163, Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings. Word 64: Advanced PIO transfer modes supported Bits 7 through 0 of word 64 of the Identify Device parameter information is defined as the advanced PIO data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate the advanced PIO modes it is capable of supporting. Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage Card supports PIO mode 3. Bit 1, if set to one, indicates that the CompactFlash StorageCard supports PIO mode 4. Support for PIO modes 5 and above are specific to CompactFlash are reported in word 163. Word 65: Minimum Multiword DMA transfer cycle time W ord 65 of the parameter information of the Identify Device command is defined as the minimum Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer. If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all CompactFlash Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a value of zero in this field. Recommended Multiword DMA transfer cycle time W ord 66 of the parameter information of the Identify Device command is defined as the recommended Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the host, may optimize the data transfer from by reducing the probability that the CompactFlash Storage Card will need to negate the DMARQ signal during the transfer of a sector. Transcend Information Inc. 64 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card If this field is supported, bit 1 of word 53 shall be set to one. The value in word 66 shall not be less than the value in word 65. This field shall be supported by all CompactFlash Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a value of zero in this field. Word 67: Minimum PIO transfer cycle time without flow control W ord 67 of the parameter information of the Identify Device command is defined as the minimum PIO transfer without flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer without utilization of flow control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not be less than the value reported in word 68. If bit 1 of word 53 is set to one because a CompactFlash Storage Card supports a field in words 64-70 other than this field and the CompactFlash Storage Card does not support this field, the CompactFlash Storage Card shall return a value of zero in this field. Word 68: Minimum PIO transfer cycle time with IORDY W ord 68 of the parameter information of the Identify Device command is defined as the minimum PIO transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that the CompactFlash Storage Card supports while performing data transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 68 shall be the fastest defined PIO mode supported by the CompactFlash Storage Card. If bit 1 of word 53 is set to one because a CompactFlash Storage Card supports a field in words 64-70 other than this field and the CompactFlash Storage Card does not support this field, the CompactFlash Storage Card shall return a value of zero in this field. Words 82-84: Features/command sets supported W ords 82, 83, and 84 shall indicate features/command sets supported. The value 0000h or FFFFh was placed in each of these words by CompactFlash Storage Cards prior to ATA-3 and shall be interpreted by the host as meaning that features/command sets supported are not indicated. Bits 1 through 13 of word 83 and bits 0 through 13 of word 84 are reserved. Bit 14 of word 83 and word 84 shall be set to one and bit 15 of word 83 and word 84 shall be cleared to zero to provide indication that the features/command sets supported words are valid. The values in these words should not be depended on by host implementers. Bit 0 of word 82 shall be set to zero; the SMART feature set is not supported. If bit 1 of word 82 is set to one, the Security Mode feature set is supported. Bit 2 of word 82 shall be set to zero; the Removable Media feature set is not supported. Bit 3 of word 82 shall be set to one; the Power Management feature set is supported. Bit 4 of word 82 shall be set to zero; the Packet Command feature set is not supported. If bit 5 of word 82 is set to one, write cache is supported. If bit 6 of word 82 is set to one, look-ahead is supported. Bit 7 of word 82 shall be set to zero; release interrupt is not supported. Bit 8 of word 82 shall be set to zero; Service interrupt is not supported. Bit 9 of word 82 shall be set to zero; the Device Reset command is not supported. Bit 10 of word 82 shall be set to zero; the Host Protected Area feature set is not supported. Bit 11 of word 82 is obsolete. Bit 12 of word 82 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command. Bit 13 of word 82 shall be set to one; the CompactFlash Storage Card supports the Read Buffer command. Bit 14 of word 82 shall be set to one; the CompactFlash Storage Card supports the NOP command. Bit 15 of word 82 is obsolete. Bit 0 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Download Microcode command. Bit 1 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA Queued and Write DMA Queued commands. Bit 2 of word 83 shall be set to one; the CompactFlash Storage Card supports the CFA feature set. Transcend Information Inc. 65 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card If bit 3 of word 83 is set to one, the CompactFlash Storage Card supports the Advanced Power Management feature set. Bit 4 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Removable Media Status feature set. Words 85-87: Features/command sets enabled W ords 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was placed in each of these words by CompactFlash Storage Cards prior to ATA-4 and shall be interpreted by the host as meaning that features/command sets enabled are not indicated. Bits 1 through 15 of word 86 are reserved. Bits 0-13 of word 87 are reserved. Bit 14 of word 87 shall be set to one and bit 15 of word 87 shall be cleared to zero to provide indication that the features/command sets enabled words are valid. The values in these words should not be depended on by host implementers. Bit 0 of word 85 shall be set to zero; the SMART feature set is not enabled. If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the Security Set Password command. Bit 2 of word 85 shall be set to zero; the Removable Media feature set is not supported. Bit 3 of word 85 shall be set to one; the Power Management feature set is supported. Bit 4 of word 85 shall be set to zero; the Packet Command feature set is not enabled. If bit 5 of word 85 is set to one, write cache is enabled. If bit 6 of word 85 is set to one, look-ahead is enabled. Bit 7 of word 85 shall be set to zero; release interrupt is not enabled. Bit 8 of word 85 shall be set to zero; Service interrupt is not enabled. Bit 9 of word 85 shall be set to zero; the Device Reset command is not supported. Bit 10 of word 85 shall be set to zero; the Host Protected Area feature set is not supported. Bit 11 of word 85 is obsolete. Bit 12 of word 85 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command. Bit 13 of word 85 shall be set to one; the CompactFlash Storage Card supports the Read Buffer command. Bit 14 of word 85 shall be set to one; the CompactFlash Storage Card supports the NOP command. Bit 15 of word 85 is obsolete. Bit 0 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Download Microcode command. Bit 1 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA Queued and Write DMA Queued commands. If bit 2 of word 86 shall be set to one, the CompactFlash Storage Card supports the CFA feature set. If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the Set Features command. Bit 4 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Removable Media Status feature set. Word 88: Ultra DMA Modes Supported and Selected W ord 88 identifies the Ultra DMA transfer modes supported by the device and indicates the mode that is currently selected. Only one DMA mode shall be selected at any given time. If an Ultra DMA mode is selected, then no Multiword DMA mode shall be selected. If a Multiword DMA mode is selected, then no Ultra DMA mode shall be selected. Support of this word is mandatory if Ultra DMA is supported. Bits 15-14: Reserved Bit 13: 1 = Ultra DMA mode 5 is selected, 0 = Ultra DMA mode 5 is not selected Bit 12: 1 = Ultra DMA mode 4 is selected, 0 = Ultra DMA mode 4 is not selected Bit 11: 1 = Ultra DMA mode 3 is selected, 0 = Ultra DMA mode 3 is not selected Bit 10: 1 = Ultra DMA mode 2 is selected, 0 = Ultra DMA mode 2 is not selected Bit 9: 1 = Ultra DMA mode 1 is selected, 0 = Ultra DMA mode 1 is not selected Bit 8: 1 = Ultra DMA mode 0 is selected, 0 = Ultra DMA mode 0 is not selected Bits 7-6: Reserved Transcend Information Inc. 66 V1.1 TS2G~16GCF300 TS2G~16GCF300 Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: 300X CompactFlash Card 1 = Ultra DMA mode 5 and below are supported. Bits 0-4 Shall be set to 1. 1 = Ultra DMA mode 4 and below are supported. Bits 0-3 Shall be set to 1. 1 = Ultra DMA mode 3 and below are supported, Bits 0-2 Shall be set to 1. 1 = Ultra DMA mode 2 and below are supported. Bits 0-1 Shall be set to 1. 1 = Ultra DMA mode 1 and below are supported. Bit 0 Shall be set to 1. 1 = Ultra DMA mode 0 is supported Word 89: Time required for Security erase unit completion W ord 89 specifies the time required for the Security Erase Unit command to complete. This command shall be supported on CompactFlash Storage Cards that support security. Value Time 0 1-254 255 Value not specified (Value * 2) minutes >508 minutes Word 90: Time required for Enhanced security erase unit completion W ord 90 specifies the time required for the Enhanced Security Erase Unit command to complete. This command shall be supported on CompactFlash Storage Cards that support security. Value Time 0 1-254 Value not specified (Value * 2) minutes 255 >508 minutes Word 91: Advanced power management level value Bits 7-0 of word 91 contain the current Advanced Power Management level setting. Word 128: Security Status Bit 8: Security Level If set to 1, indicates that security mode is enabled and the security level is maximum. If set to 0 and security mode is enabled, indicates that the security level is high. Bit 5: Enhanced security erase unit feature supported If set to 1, indicates that the Enhanced security erase unit feature set is supported. Bit 4: Expire If set to 1, indicates that the security count has expired and Security Unlock and Security Erase Unit are command aborted until a power-on reset or hard reset. Bit 3: Freeze If set to 1, indicates that the security is Frozen. Bit 2: Lock If set to 1, indicates that the security is locked. Bit 1: Enable/Disable If set to 1, indicates that the security is enabled. If set to 0, indicates that the security is disabled. Bit 0: Capability If set to 1, indicates that CompactFlash Storage Card supports security mode feature set. If set to 0, indicates that CompactFlash Storage Card does not support security mode feature set. Word 160: Power Requirement Description This word is required for CompactFlash Storage Cards that support power mode 1. Bit 15: VLD If set to 1, indicates that this word contains a valid power requirement description. If set to 0, indicates that this word does not contain a power requirement description. Bit 14: RSV This bit is reserved and shall be 0. Transcend Information Inc. 67 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Bit 13: -XP If set to 1, indicates that the CompactFlash Storage Card does not have Power Level 1 commands. If set to 0, indicates that the CompactFlash Storage Card has Power Level 1 commands Bit 12: -XE If set to 1, indicates that Power Level 1 commands are disabled. If set to 0, indicates that Power Level 1 commands are enabled. Bit 0-11: Maximum current This field contains the CompactFlash Storage Card’s maximum current in mA. Word 162: Key Management Schemes Supported Bit 0: CPRM support If set to 1, the device supports CPRM Scheme (Content Protection for Recordable Media) If set to 0, the device does not support CPRM. Bits 1-15 are reserved for future additional Key Management schemes. Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings This word describes the capabilities and current settings for CFA defined advanced timing modes using the True IDE interface. Notice! The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above impose significant restrictions on the implementation of the host: Additional Requirements for CF Advanced Timing Modes. There are four separate fields defined that describe support and selection of Advanced PIO timing modes and Advanced Multiword DMA timing modes. The older modes are reported in words 63 and 64. Word 63: Multiword DMA transfer and 6.2.1.6.19: Word 64: Advanced PIO transfer modes supported. Bits 2-0: Advanced True IDE PIO Mode Support Indicates the maximum True IDE PIO mode supported by the card. Value Maximum PIO mode timing selected 0 Specified in word 64 1 PIO Mode 5 2 PIO Mode 6 3-7 Reserved Bits 5-3: Advanced True IDE Multiword DMA Mode Support Indicates the maximum True IDE Multiword DMA mode supported by the card. Value Maximum Multiword DMA timing mode supported 0 Specified in word 63 1 Multiword DMA Mode 3 2 Multiword DMA Mode 4 3-7 Reserved Bits 8-6: Advanced True IDE PIO Mode Selected Indicates the current True IDE PIO mode selected on the card. Value Current PIO timing mode selected 0 Specified in word 64 1 PIO Mode 5 Transcend Information Inc. 68 V1.1 TS2G~16GCF300 TS2G~16GCF300 2 3-7 PIO Mode 6 Reserved 300X CompactFlash Card Bits 11-9: Advanced True IDE Multiword DMA Mode Selected Indicates the current True IDE Multiword DMA Mode Selected on the card. Value Current Multiword DMA timing mode selected 0 Specified in word 63 1 Multiword DMA Mode 3 2 Multiword DMA Mode 4 3-7 Reserved Bits 15-12 are reserved. Word 164: CF Advanced PCMCIA I/O and Memory Timing Modes Capabilities and Settings This word describes the capabilities and current settings for CFA defined advanced timing modes using the Memory and PCMCIA I/O interface. Notice: The use of PCMCIA I/O or Memory modes that are 100ns or faster impose significant restrictions on the implementation of the host: Additional Requirements for CF Advanced Timing Modes. Bits 2-0: Maximum Advanced PCMCIA I/O Mode Support Indicates the maximum I/O timing mode supported by the card. Value 0 1 2 3 4-7 Maximum PCMCIA IO timing mode Supported 255ns Cycle PCMCIA I/O Mode 120ns Cycle PCMCIA I/O Mode 100ns Cycle PCMCIA I/O Mode 80ns Cycle PCMCIA I/O Mode Reserved Bits 5-3: Maximum Memory timing mode supported Indicates the Maximum Memory timing mode supported by the card. Value Maximum Memory timing mode Supported 0 250ns Cycle Memory Mode 1 120ns Cycle Memory Mode 2 100ns Cycle Memory Mode 3 80ns Cycle Memory Mode 4-7 Reserved Bits 8-6: Maximum PC Card I/O UDMA timing mode supported Indicates the Maximum PC Card I/O UDMA timing mode supported by the card when bit 15 is set. Value 0 1 Maximum PC Card I/O UDMA timing mode Supported PC Card I/O UDMA mode 0 supported PC Card I/O UDMA mode 1 supported 69 V1.1 Transcend Information Inc. TS2G~16GCF300 TS2G~16GCF300 2 3 4 5 6 7 PC Card I/O UDMA mode 2 supported PC Card I/O UDMA mode 3 supported PC Card I/O UDMA mode 4 supported PC Card I/O UDMA mode 5 supported Reserved Reserved 300X CompactFlash Card Bits 11-9: Maximum PC Card Memory UDMA timing mode supported Indicates the Maximum PC Card Memory UDMA timing mode supported by the card when bit 15 is set. Value 0 1 2 3 4 5 6 7 Maximum PC Card Memory UDMA timing mode Supported PC Card Memory UDMA mode 0 supported PC Card Memory UDMA mode 1 supported PC Card Memory UDMA mode 2 supported PC Card Memory UDMA mode 3 supported PC Card Memory UDMA mode 4 supported PC Card Memory UDMA mode 5 supported Reserved Reserved Bits 14-12: PC Card Memory or I/O UDMA timing mode selectedIndicates the PC Card Memory or I/O UDMA timing mode selected by the card. Value 0 1 2 3 4 5 6 7 PC Card Memory or I/O UDMA timing mode Selected PC Card I/O UDMA mode 0 selected PC Card I/O UDMA mode 1 selected PC Card I/O UDMA mode 2 selected PC Card I/O UDMA mode 3 selected PC Card I/O UDMA mode 4 selected PC Card I/O UDMA mode 5 selected Reserved Reserved Bit 15: PC Card Memory and IO Modes Supported This bit, when set, indicates that the PC Card UDMA support values in bits 11-6 are valid. When this bit is cleared, PC Card Memory and IO Modes are not supported by the device. Idle - 97h or E3h This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. Note that this time base (5 msec) is different from the ATA specification. Bit -> 7 6 5 4 3 2 1 0 Transcend Information Inc. 70 V1.1 TS2G~16GCF300 TS2G~16GCF300 Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 97h or E3h Drive X X X Timer Count (5 msec increments) X 300X CompactFlash Card X Idle Immediate - 95h or E1h This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 7 6 5 4 3 2 1 0 95h or E1h Drive X X X X X X Initialize Drive Parameters - 91h This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by this command. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X 0 X Drive X X X Number of Sectors X 7 6 5 4 3 91h Max Head (no. of heads-1) 2 1 0 NOP - 00h This command always fails with the CompactFlash Storage Card returning command aborted. Bit -> Command (7) C/D/H (6) X Drive 7 6 5 4 00h X 3 2 1 0 Transcend Information Inc. 71 V1.1 TS2G~16GCF300 TS2G~16GCF300 Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X X X X X 300X CompactFlash Card Read Buffer - E4h The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card’s sector buffer. This command has the same protocol as the Read Sector(s) command. Bit -> Command (7) C/D/H (6) Cyl High (5) Cyl Low (4) Sec Num (3) Sec Cnt (2) Feature (1) X Drive X X X X X 7 6 5 4 E4h X 3 2 1 0 Read DMA – C8h Read Long Sector - 22h or 23h Transcend Information Inc. 72 V1.1 TS2G~16GCF300 TS2G~16GCF300 Read Multiple - C4h 300X CompactFlash Card Read Sector(s) - 20h or 21h Read Verify Sector(s) - 40h or 41h Recalibrate - 1Xh Transcend Information Inc. 73 V1.1 TS2G~16GCF300 TS2G~16GCF300 Request Sense - 03h 300X CompactFlash Card The extended error code is returned to the host in the Error Register. Seek - 7Xh Transcend Information Inc. 74 V1.1 TS2G~16GCF300 TS2G~16GCF300 Set Features – EFh 300X CompactFlash Card Feature Supported Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature command is issued all data transfers shall occur on the low order D[7:0] data bus and the -IOIS16 signal shall not be asserted for data register accesses. The host shall not enable this feature for DMA transfers. Features 02h and 82h allow the host to enable or disable write cache in CompactFlash Storage Cards that implement write cache. When the subcommand disable write cache is issued, the CompactFlash Storage Card shall initiate the sequence to flush cache to non-volatile memory before command completion. Transcend Information Inc. 75 V1.1 TS2G~16GCF300 TS2G~16GCF300 300X CompactFlash Card Feature 03h allows the host to select the PIO or Multiword DMA transfer mode by specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One PIO mode shall be selected at all times. For Cards which support DMA, one Multiword DMA mode shall be selected at all times. The host may change the selected modes by the Set Features command. Set Multiple Mode - C6h Set Sleep Mode- 99h or E6h Standby - 96h or E2h Transcend Information Inc. 76 V1.1 TS2G~16GCF300 TS2G~16GCF300 Standby Immediate - 94h or E0h 300X CompactFlash Card Translate Sector - 87h Translate Sector Information Transcend Information Inc. 77 V1.1 TS2G~16GCF300 TS2G~16GCF300 Wear Level - F5h 300X CompactFlash Card Write Buffer - E8h Write DMA – CAh Transcend Information Inc. 78 V1.1 TS2G~16GCF300 TS2G~16GCF300 Write Long Sector - 32h or 33h 300X CompactFlash Card Write Multiple Command - C5h Write Multiple without Erase – CDh Transcend Information Inc. 79 V1.1 TS2G~16GCF300 TS2G~16GCF300 Write Sector(s) - 30h or 31h 300X CompactFlash Card Write Sector(s) without Erase - 38h Write Verify - 3Ch Transcend Information Inc. 80 V1.1 TS2G~16GCF300 TS2G~16GCF300 Error Posting Command BBK Check Power Mode Execute Drive Diagnostic1 Erase Sector(s) Flush Cache Format Track Identify Device Idle Idle Immediate Initialize Drive Parameters Key Management Structure Read Key Management Read Keying Material Key Management Change Key Management Value NOP Read Buffer Read DMA Read Multiple Read Long Sector Read Sector(s) Read Verify Sectors Recalibrate Request Sense Security Disable Password Security Erase Prepare Security Erase Unit Security Freeze Lock Security Set Password Security Unlock Seek Set Features V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Error Register UNC IDNF ABRT V AMNF DRDY V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 300X CompactFlash Card Status Register DWF V DSC V V V V V V V V V V V V CORR ERR V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Transcend Information Inc. 81 V1.1 TS2G~16GCF300 TS2G~16GCF300 Command BBK Set Multiple Mode Set Sleep Mode Stand By Stand By Immediate Translate Sector W ear Level W rite Buffer W rite DMA W rite Long Sector W rite Multiple W rite Multiple w/o Erase W rite Sector(s) W rite Sector(s) w/o Erase W rite Verify Invalid Command Code V V V V V V V V V V V V V V V V V V V Error Register UNC IDNF ABRT V V V V V V V V V V V V V V V V V V V V V V V V AMNF DRDY V V V V V V V V V V V V V V V 300X CompactFlash Card Status Register DWF V V V V V V V V V V V V V V V DSC V V V V V V V V V V V V V V V CORR ERR V V V V V V V V V V V V V V V Error and Status Register summarizes the valid status and error value for all the CF-ATA Command set. C.H.S. Table Capacity 2GB 4GB 8GB 16GB SMART SMART Command Set SMART Command Set SMART Feature Register Values D0h D1h D2h D3h Read Data Read Attribute Threshold Enable/Disable Autosave Save Attribute Values D5h D6h D8h D9h Read Log Write Log Enable SMART Operations Disable SMART Operations C 3949 7899 15796 33149 H 16 16 16 15 S 63 63 63 63 D4h Execute OFF-LINE Immediate DAh Return Status 1. If reserved size below the Threshold, the status can be read from Cylinder register by Return Status command (DAh). Transcend Information Inc. 82 V1.1 TS2G~16GCF300 TS2G~16GCF300 SMART Data Structure BYTE 0-1 2-361 362 363 364-365 366 367 368-369 F/V X X V X V X F F Revision code Vendor specific Off line data collection status Self-test execution status byte Decription 300X CompactFlash Card Total time in seconds to complete off-line data collection activity Vendor specific Off-line data collection capability SMART capability Error logging capability 370 F 7-1 Reserved 0 1=Device error logging supported 371 372 373 374 375-385 386-395 396-397 398-399 400 511 X F F F R F F V V V Vendor specific Short self-test routine recommended polling time (in minutes) Extended self-test routine recommended polling time (in minutes) Conveyance self-test routine recommended polling time (in minutes) Reserved Firmware Version/Date Code Number of initial invalid block (396=MSB, 397 =LSB) Number of run time bad block (398=MSB, 399 =LSB) Number of spare block Data structure checksum F=the content (byte) is fixed and does not change. V=the content (byte) is variable and may change depending on the state of the device or the commands executed by the device. X=the content (byte) is vendor specific and may be fixed or variable. R=the content (byte) is reserved and shall be zero. N=Nth Management Unit * 4 Byte value : [MSB] [2] [1] [LSB] Above technical information is based on CFA standard data and tested to be reliable. However, Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice. Transcend Information Inc. 83 V1.1