TMC2160-BOB

POWER DRIVER FOR STEPPER MOTORS INTEGRATED CIRCUITS TMC2160 DATASHEET Universal high voltage driver for two-phase bipolar stepper motor. stealthChop™ for quiet movement. External MOSFETs for up to 20A motor current per coil. With Step/Dir Interface and SPI. APPLICATIONS Robotics & Industrial Drives Textile, Sewing Machines Packing Machines Factory & Lab Automation High-speed 3D Printers Liquid Handling Medical Office Automation CCTV ATM, Cash Recycler Pumps and Valves FEATURES AND BENEFITS DESCRIPTION 2-phase stepper motors up to 20A coil current (external MOSFETs) The TMC2160 is a high-power stepper motor driver IC with SPI interface. It features industries’ most advanced stepper motor driver with simple Step / Direction interface. Using external transistors, highly dynamic, high torque drives can be realized. Based on TRINAMICs sophisticated spreadCycle and stealthChop choppers, the driver ensures absolutely noiseless operation combined with maximum efficiency and best motor torque. High integration, high energy efficiency and a small form factor enable miniaturized and scalable systems for cost effective solutions. The fully compatible TMC5160 offers an additional motion controller to make stepper motor control even easier. Step/Dir Interface with microstep interpolation microPlyer™ Voltage Range 8 … 60V DC SPI Interface Highest Resolution 256 microsteps per full step stealthChop2™ for quiet operation and smooth motion Resonance Dampening for mid-range resonances spreadCycle™ highly dynamic motor control chopper dcStep™ load dependent speed control stallGuard2™ high precision sensorless motor load detection coolStep™ current control for energy savings up to 75% Passive Braking and freewheeling mode Full Protection & Diagnostics Compact Size 9x9mm2 TQFP48 package BLOCK DIAGRAM Step/Dir +VM 1 of 2 full bridges shown TMC2160 Step Multiplyer Diagnostic outputs Standstill current reduction Motor CBOOT SPI SPI Interface Control Register Set Programmable 256 µStep Sequencer spreadCycle stealthChop MOSFET Driver CBOOT Protection & Diagnostics Power Supply Charge Pump CLK Oscillator / Selector stallGuard2 coolStep dcStep Diff. Sensing CLK TRINAMIC Motion Control GmbH & Co. KG Hamburg, Germany Enable RSENSE TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 2 APPLICATION EXAMPLES: HIGH VOLTAGE – MULTIPURPOSE USE The TMC2160 scores with advanced motor commutation algorithms, combined with powerful external MOSFET driver stages, and high-quality current regulation. It offers a versatility that covers a wide spectrum of applications from battery powered, high efficiency systems up to embedded applications with 20A motor current per coil. Based on TRINAMICs unique features stallGuard2, coolStep, dcStep, spreadCycle, and stealthChop, the TMC2160 optimizes drive performance. It trades off velocity vs. motor torque, optimizes energy efficiency, smoothness of the drive, and noiselessness. The small form factor of the TMC2160 keeps costs down and allows for miniaturized layouts. Extensive support at the chip, board, and software levels enables rapid design cycles and fast time-to-market with competitive products. High energy efficiency and reliability deliver cost savings in related systems such as power supplies and cooling. For smaller designs, the compatible, integrated TMC2130 driver provides 1.4A of motor current. MINIATURIZED DESIGN FOR ONE STEPPER MOTOR In this application, the CPU initializes the TMC2160 motor driver via SPI interface and controls motor movement by sending step and direction signals. A real time software realizes motion control. 0A+ High-Level Interface CPU S/D TMC2160 0A- S N 0B+ 0B- SPI DESIGN FOR DEMANDING APPLICATIONS WITH S-SHAPED RAMP PROFILES 0A+ High-Level Interface CPU SPI TMC4361 Motion Controller SPI S/D TMC2160 0A0B+ 0B- SPI S N The CPU initializes the TMC4361 motion controller and the TMC2160. Thereafter, it sends target positions to the TMC4361. Now, the TMC4361 takes control over the TMC2160. Combining the TMC4361 and the TMC2160 offers diverse possibilities for demanding applications including servo drive features. The TMC2160-EVAL is part of TRINAMICs universal evaluation board system which provides a convenient handling of the hardware as well as a user-friendly software tool for evaluation. The TMC2160 evaluation board system consists of three parts: LANDUNGSBRÜCKE (base board), ESELSBRÜCKE (connector board including several test points), and TMC2160-EVAL. ORDER CODES Order code TMC2160-TA TMC2160-TA-T TMC2160-EVAL LANDUNGSBRÜCKE ESELSBRÜCKE www.trinamic.com Description stepper controller/driver for external MOSFETs; TQFP48 -T denotes tape on reel packing Evaluation board for TMC2160 two phase stepper motor controller/driver Baseboard for TMC2160-EVAL and further evaluation boards. Connector board for plug-in evaluation board system. Size [mm2] 9x9 85 x 55 85 x 55 61 x 38 TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 3 Table of Contents 1 PRINCIPLES OF OPERATION ......................... 5 1.1 KEY CONCEPTS ................................................ 6 1.2 CONTROL INTERFACES ..................................... 6 1.3 SOFTWARE ...................................................... 7 1.4 MOVING THE MOTOR ...................................... 8 1.5 AUTOMATIC STANDSTILL POWER DOWN......... 8 1.6 STEALTHCHOP2 & SPREADCYCLE DRIVER ........ 8 1.7 STALLGUARD2 – MECHANICAL LOAD SENSING9 1.8 COOLSTEP – LOAD ADAPTIVE CURRENT CONTROL ...................................................................... 9 1.9 DCSTEP – LOAD DEPENDENT SPEED CONTROL 9 2 PIN ASSIGNMENTS .........................................11 2.1 2.2 3 PACKAGE OUTLINE ........................................11 SIGNAL DESCRIPTIONS .................................11 SAMPLE CIRCUITS ..........................................14 3.1 3.2 3.3 3.4 4 STANDARD APPLICATION CIRCUIT ................14 EXTERNAL GATE VOLTAGE REGULATOR ..........15 CHOOSING MOSFETS AND SLOPE ................16 TUNING THE MOSFET BRIDGE .....................18 SPI INTERFACE ................................................21 4.1 4.2 4.3 5 SPI DATAGRAM STRUCTURE .........................21 SPI SIGNALS ................................................22 TIMING .........................................................23 REGISTER MAPPING .......................................24 5.1 GENERAL CONFIGURATION REGISTERS ..........25 5.2 VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET .............................................31 5.3 MOTOR DRIVER REGISTERS ...........................34 6 STEALTHCHOP™ ..............................................44 11.1 11.2 11.3 11.4 11.5 12 12.1 12.2 12.3 13 13.1 13.2 13.3 STALLGUARD2 LOAD MEASUREMENT ... 68 TUNING STALLGUARD2 THRESHOLD SGT ..... 69 STALLGUARD2 UPDATE RATE AND FILTER .... 71 DETECTING A MOTOR STALL ......................... 71 HOMING WITH STALLGUARD......................... 71 LIMITS OF STALLGUARD2 OPERATION .......... 71 COOLSTEP OPERATION ............................. 72 USER BENEFITS............................................. 72 SETTING UP FOR COOLSTEP .......................... 72 TUNING COOLSTEP........................................ 74 STEP/DIR INTERFACE ................................ 75 TIMING ......................................................... 75 CHANGING RESOLUTION ............................... 76 MICROPLYER AND STAND STILL DETECTION . 77 14 DIAG OUTPUTS ........................................... 78 15 DCSTEP .......................................................... 79 15.1 15.2 15.3 15.4 16 16.1 16.2 USER BENEFITS............................................. 79 DESIGNING-IN DCSTEP ................................. 79 STALL DETECTION IN DCSTEP MODE ............ 80 DCSTEP WITH STEP/DIR INTERFACE ........... 81 SINE-WAVE LOOK-UP TABLE................... 84 USER BENEFITS............................................. 84 MICROSTEP TABLE ........................................ 84 17 EMERGENCY STOP ...................................... 85 18 QUICK CONFIGURATION GUIDE ............ 86 19 GETTING STARTED ..................................... 90 19.1 INITIALIZATION EXAMPLES ........................... 90 AUTOMATIC TUNING .....................................44 STEALTHCHOP OPTIONS ................................47 STEALTHCHOP CURRENT REGULATOR .............47 VELOCITY BASED SCALING ............................49 COMBINING STEALTHCHOP AND SPREADCYCLE .. .....................................................................51 FLAGS IN STEALTHCHOP................................53 FREEWHEELING AND PASSIVE BRAKING ........53 20 STANDALONE OPERATION ...................... 91 21 EXTERNAL RESET ........................................ 93 22 CLOCK OSCILLATOR AND INPUT ........... 93 23 ABSOLUTE MAXIMUM RATINGS ............ 94 SPREADCYCLE AND CLASSIC CHOPPER ...55 24 ELECTRICAL CHARACTERISTICS ............ 94 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 11 7.1 7.2 SPREADCYCLE CHOPPER ................................56 CLASSIC CONSTANT OFF TIME CHOPPER.......59 8 SELECTING SENSE RESISTORS ....................61 9 VELOCITY BASED MODE CONTROL ............63 10 10.1 10.2 10.3 DIAGNOSTICS AND PROTECTION .........65 TEMPERATURE SENSORS ................................65 SHORT PROTECTION ......................................65 OPEN LOAD DIAGNOSTICS ............................67 www.trinamic.com 22.1 22.2 24.1 24.2 24.3 25 25.1 25.2 25.3 25.4 26 USING THE INTERNAL CLOCK ........................ 93 USING AN EXTERNAL CLOCK ......................... 93 OPERATIONAL RANGE ................................... 94 DC AND TIMING CHARACTERISTICS .............. 95 THERMAL CHARACTERISTICS.......................... 97 LAYOUT CONSIDERATIONS..................... 99 EXPOSED DIE PAD ........................................ 99 WIRING GND .............................................. 99 SUPPLY FILTERING........................................ 99 LAYOUT EXAMPLE ....................................... 100 PACKAGE MECHANICAL DATA.............. 102 TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 26.1 26.2 DIMENSIONAL DRAWINGS TQFP48-EP..... 102 PACKAGE CODES ........................................ 104 27 DISCLAIMER .............................................. 105 28 ESD SENSITIVE DEVICE ......................... 105 www.trinamic.com 4 29 TABLE OF FIGURES .................................. 106 30 REVISION HISTORY ................................. 107 31 REFERENCES ............................................... 107 TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 1 5 Principles of Operation The TMC2160 driver chip is an intelligent power component interfacing between a motion controller and a high-power stepper motor. It uses stealthChop, dcStep, coolStep, and stallGuard2 automatically to optimize every motor movement. The TMC2160 ideally extends the TMC2100 and TMC2130 family to higher voltages and higher motor currents. THE TMC2160 OFFERS TWO BASIC MODES OF OPERATION: MODE 1: Step & Direction Driver An external high-performance S-ramp motion controller like the TMC4361 or a central CPU generates step & direction signals synchronized to other components like additional motors within the system. The TMC2160 takes care of intelligent current and mode control and delivers feedback on the state of the motor. The microPlyer automatically smoothens motion. MODE 2: Simple Step & Direction Driver The TMC2160 positions the motor based on step & direction signals. The microPlyer automatically smoothens motion. No CPU interaction is required; configuration is done by hardware pins. Basic standby current control can be done by the TMC2160. Optional feedback signals allow error detection and synchronization. Enable this mode by tying pin SPI_MODE low. 100n VSA 12VOUT 100n 2.2µ 2.2µ 5VOUT CB2 11.5V Voltage regulator TMC2160 charge pump HS step multiplier microPlyer 5V Voltage regulator HS Standstill current reduction 2R2 VCC DIAG1 DIAG0 SPI interface programmable sine table 4*256 entry x RG RG RG RG SRBH B.Dwersteg, © TRINAMIC 2014 47R RS SRBL Stepper driver B.Dwersteg, © Protection TRINAMIC 2014 & diagnostics CA2 HS S CB HS stallGuard2 HA2 470n HA1 CB BMA1 RG RG RG RG BMA2 dcStep +VIO LA1 LS VCC_IO LA2 LS 100n SRAH mode selection 47R RS SRAL +VIO pd dcStep control opt. driver enable Figure 1.1 TMC2160 STEP/DIR application diagram www.trinamic.com GNDD GNDA DIE PAD TST_MODE DRV_ENN 47R DCO DCEN pd DCIN SPI_MODE pd +VM 47R CA1 CLK_IN 3.3V or 5V I/O voltage 470n LB2 spreadCycle & stealthChop Chopper coolStep opt. ext. clock 12-16MHz CB HB1 LB1 LS DIAG / INT out and Single wire interface CB CB1 BMB2 LS Control register set HB2 BMB1 470n CSN SCK SDI SDO CE VS CPI 100n 16V VCP 22n 100V CPO +VM DIR STEP +VM N stepper motor TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 6 100n VSA 100n 2.2µ 2.2µ CB2 12VOUT 11.5V Voltage regulator 5VOUT 5V Voltage regulator TMC2160 charge pump HS step multiplier microPlyer HS Standstill current reduction 2R2 VCC HB2 CB CB1 CB CFG1 CFG4 spreadCycle (GND) / stealthChop (VCC_IO) Current Reduction Enable (VCC_IO) CFG5 pd Configuration interface (GND or VCC_IO level) pd B.Dwersteg, © TRINAMIC 2014 CFG6 Control register set (default values) programmable sine table 4*256 entry x Stepper driver B.Dwersteg, © Protection TRINAMIC 2014 & diagnostics B.Dwersteg, © TRINAMIC 2014 opt. ext. clock 12-16MHz Status out (open drain) CA2 HS OTP S +VM 47R HA2 N stepper motor 470n HA1 CB BMA1 RG RG RG RG BMA2 LA1 LS +VIO VCC_IO 100n RS CB CA1 CLK_IN 3.3V or 5V I/O voltage 47R SRBL HS DIAG0 Driver error RG SRBH spreadCycle & stealthChop Chopper DIAG1 Index pulse RG LB2 LS CFG3 RG LB1 CFG0 CFG2 RG BMB2 LS Run Current Setting 16 / 18 / 20 / 22 / 24 / 26 / 28 / 31 470n HB1 BMB1 470n Microstep Resolution 8 / 16 / 32 / 64 CE VS 100n 16V VCP CPI CPO +VM DIR STEP +VM 22n 100V LA2 LS SRAH mode selection 47R RS SRAL pd GNDD GNDA DIE PAD TST_MODE DRV_ENN SPI_MODE 47R dcStep control Standalone mode opt. driver enable Figure 1.2 TMC2160 standalone driver application diagram 1.1 Key Concepts The TMC2160 implements advanced features which are exclusive to TRINAMIC products. These features contribute toward greater precision, greater energy efficiency, higher reliability, smoother motion, and cooler operation in many stepper motor applications. stealthChop2™ No-noise, high-precision chopper algorithm for inaudible motion and inaudible standstill of the motor. Allows faster motor acceleration and deceleration than stealthChop™ and extends stealthChop to low stand still motor currents. spreadCycle™ High-precision chopper algorithm for highly dynamic motion and absolutely clean current wave. Low noise, low resonance and low vibration chopper. dcStep™ Load dependent speed control. The motor moves as fast as possible and never loses a step. stallGuard2™ Sensorless stall detection and mechanical load measurement. coolStep™ Load-adaptive current control reducing energy consumption by as much as 75%. microPlyer™ Microstep interpolator for obtaining full 256 microstep smoothness with lower resolution step inputs starting from fullstep In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage conditions for enhancing safety and recovery from equipment malfunctions. 1.2 Control Interfaces The TMC2160 supports an SPI interface for parameter setting and diagnostics. Additionally, a standalone mode is provided for pure STEP/DIR operation without use of the serial interface. Selection of the actual interface is done via the configuration pin SPI_MODE, which can be hardwired to GND or VCC_IO depending on the desired interface. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 1.2.1 7 SPI Interface The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus master to the bus slave another bit is sent simultaneously from the slave to the master. Communication between an SPI master and the TMC2160 slave always consists of sending one 40-bit command word and receiving one 40-bit status word. The SPI command rate typically is a few commands per complete motor motion. 1.3 Software From a software point of view the TMC2160 is a peripheral with a number of control and status registers. Most of them can either be written only or read only. Some of the registers allow both read and write access. In case read-modify-write access is desired for a write only register, a shadow register can be realized in master software. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 8 1.4 Moving the Motor 1.4.1 STEP/DIR Interface The motor is controlled by a step and direction input. Active edges on the STEP input can be rising edges or both rising and falling edges as controlled by another mode bit (dedge). Using both edges cuts the toggle rate of the STEP signal in half, which is useful for communication over slow interfaces such as optically isolated interfaces. On each active edge, the state sampled from the DIR input determines whether to step forward or back. Each step can be a fullstep or a microstep, in which there are 2, 4, 8, 16, 32, 64, 128, or 256 microsteps per fullstep. A step impulse with a low state on DIR increases the microstep counter and a high state decreases the counter by an amount controlled by the microstep resolution. An internal table translates the counter value into the sine and cosine values which control the motor current for microstepping. 1.4.2 SPI direct mode The direct mode allows control of both motor coil currents and polarity via SPI. It mainly is intended for use with a dedicated external motion controller IC with integrated sequencer. The sequencer applies sine and cosine waves to the motor coils. This mode is specially designed for combination with the TMC4361 motion controller. 1.5 Automatic Standstill Power Down An automatic current reduction drastically reduces application power dissipation and cooling requirements. Modify stand still current, delay time and decay via register settings. Automatic freewheeling and passive motor braking are provided as an option for stand still. Passive braking reduces motor standstill power consumption to zero, while still providing effective dampening and braking! An option for faster detection of standstill is provided for use with highly frequent motion commands. STEP Standstill flag (stst) CURRENT IRUN IHOLD RMS motor current trace standstill delay TPOWERDOWN IHOLDDELAY 2^20 / 2^18 clocks power down power down ramp time (faststandstill) delay time t Figure 1.3 Automatic Motor Current Power Down 1.6 stealthChop2 & spreadCycle Driver stealthChop is a voltage chopper based principle. It especially guarantees that the motor is absolutely quiet in standstill and in slow motion, except for noise generated by ball bearings. Unlike other voltage mode choppers, stealthChop2 does not require any configuration. It automatically learns the best settings during the first motion after power up and further optimizes the settings in subsequent motions. An initial homing sequence is sufficient for learning. Optionally, initial learning parameters can be pre-configured via the interface. stealthChop2 allows high motor dynamics, by reacting at once to a change of motor velocity. For highest dynamic applications, spreadCycle is an option to stealthChop2. It can be enabled via input pin (standalone mode) or via SPI interface. stealthChop2 and spreadCycle may even be used in a combined configuration for the best of both worlds: stealthChop2 for no-noise stand still, silent and smooth performance, spreadCycle at higher velocity for high dynamics and highest peak velocity at low vibration. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 9 spreadCycle is an advanced cycle-by-cycle chopper mode. It offers smooth operation and good resonance dampening over a wide range of speed and load. The spreadCycle chopper scheme automatically integrates and tunes fast decay cycles to guarantee smooth zero crossing performance. Benefits of using stealthChop2: - Significantly improved microstepping with low cost motors - Motor runs smooth and quiet - Absolutely no standby noise - Reduced mechanical resonance yields improved torque 1.7 stallGuard2 – Mechanical Load Sensing stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like sensorless homing and diagnostics of the drive mechanics. 1.8 coolStep – Load Adaptive Current Control coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement information to adjust the motor current to the minimum amount required in the actual load situation. This saves energy and keeps the components cool. Benefits are: - Energy efficiency - Motor generates less heat - Less or no cooling - Use of smaller motor power consumption decreased up to 75% improved mechanical precision improved reliability less torque reserve required → cheaper motor does the job Figure 1.4 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example. 0,9 Efficiency with coolStep 0,8 Efficiency with 50% torque reserve 0,7 0,6 0,5 Efficiency 0,4 0,3 0,2 0,1 0 0 50 100 150 200 250 300 350 Velocity [RPM] Figure 1.4 Energy efficiency with coolStep (example) 1.9 dcStep – Load Dependent Speed Control dcStep allows the motor to run near its load limit and at its velocity limit without losing a step. If the mechanical load on the motor increases to the stalling load, the motor automatically decreases velocity so that it can still drive the load. With this feature, the motor will never stall. In addition to the increased torque at a lower velocity, dynamic inertia will allow the motor to overcome mechanical overloads by decelerating. dcStep directly integrates with the ramp generator, so that the target position will be reached, even if the motor velocity needs to be decreased due to increased mechanical load. A dynamic range of up to factor 10 or more can be covered by dcStep without any www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 10 step loss. By optimizing the motion velocity in high load situations, this feature further enhances overall system efficiency. Benefits are: - Motor does not loose steps in overload conditions - Application works as fast as possible - Highest possible acceleration automatically - Highest energy efficiency at speed limit - Highest possible motor torque using fullstep drive - Cheaper motor does the job www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 2 11 Pin Assignments CA1 HA1 BMA1 42 41 40 BMA2 CB2 43 37 HB2 44 LA1 BMB2 45 LA2 LB2 46 38 LB1 47 39 BMB1 48 2.1 Package Outline HB1 1 36 HA2 CB1 2 35 CA2 12VOUT 3 34 VCP VSA 4 33 VS 5VOUT 5 32 CPI GNDA 6 31 CPO SRAL 7 30 GNDD SRAH 8 29 VCC SRBH 9 28 DRV_ENN SRBL 10 27 DIAG1 TST_MODE 11 26 DIAG0 CLK 12 25 DCO_CFG6 TMC2160-TA TQFP-48 13 14 15 16 17 18 19 20 21 22 23 24 CSN_CFG3 SCK_CFG2 SDI_CFG1 SDO_CFG0 STEP DIR GNDD VCC_IO VCC_IO SPI_MODE DCEN_CFG4 DCIN_CFG5 PAD = GNDD, GNDP Figure 2.1 TMC2160-TA package and pinning TQFP-EP 48 (7x7mm² body, 9x9mm² with leads) 2.2 Signal Descriptions Pin HB1 CB1 TQFP 1 2 12VOUT 3 VSA 4 5VOUT 5 GNDA 6 SRAL 7 www.trinamic.com Type AI Function High side gate driver output. Bootstrap capacitor positive connection. Output of internal 11.5V gate voltage regulator and supply pin of low side gate drivers. Attach 2.2µF to 10µF ceramic capacitor to GND plane near to pin for best performance. Use at least 10 times more capacity than for bootstrap capacitors. In case an external gate voltage supply is available, tie VSA and 12VOUT to the external supply. Analog supply voltage for 11.5V and 5V regulator. Normally tied to VS. Provide a 100nF filtering capacitor. Output of internal 5V regulator. Attach 2.2µF to 10µF ceramic capacitor to GNDA near to pin for best performance. Output for VCC supply of the chip. Analog GND. Connect to GND plane near pin. Sense resistor GND connection for phase A. Connect to the GND side of the sense resistor in order to compensate for voltage drop on the GND interconnection. TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) Pin TQFP Type SRAH 8 AI SRBH 9 AI SRBL 10 AI TST_MODE 11 DI CLK 12 DI CSN_CFG3 13 DI SCK_CFG2 14 DI SDI_CFG1 15 DI SDO_CFG0 16 DIO STEP DIR GNDD VCC_IO 17 18 19, 30 20, 21 DI DI SPI_MODE 22 DI (pd) DCEN_ CFG4 23 DI (pd) DCIN_ CFG5 24 DI (pd) DCO_ CFG6 25 DIO DIAG0 26 DO (pu+ pd) DIAG1 27 DO (pd) DRV_ENN 28 DI www.trinamic.com Function Sense resistor for phase A. Connect to the upper side of the sense resistor. A Kelvin connection is preferred with high motor currents. Symmetrical RC-Filtering may be added for SRAL and SRAH to eliminate high frequency switching spikes from other drives or switching of coil B. Sense resistor for phase B. Connect to the upper side of the sense resistor. A Kelvin connection is preferred with high motor currents. Symmetrical RC-Filtering may be added for SRBL and SRBH to eliminate high frequency switching spikes from other drives or switching of coil A. Sense resistor GND connection for phase B. Connect to the GND side of the sense resistor in order to compensate for voltage drop on the GND interconnection. Test mode input. Tie to GND using short wire. CLK input. Tie to GND using short wire for internal clock or supply external clock. Internal clock-fail over circuit protects against loss of external clock signal. SPI chip select input (negative active) (SPI_MODE=1) or Configuration input (SPI_MODE=0) SPI serial clock input (SPI_MODE=1) or Configuration input (SPI_MODE=0) SPI data input (SPI_MODE=1) or Configuration input (SPI_MODE=0) or Next address input (NAI) for single wire interface. SPI data output (tristate) (SPI_MODE=1) or Configuration input (SPI_MODE=0) or Next address output (NAO) for single wire interface. STEP input DIR input Digital GND. Connect to GND plane near pin. 3.3V to 5V IO supply voltage for all digital pins. Mode selection input. When tied low with SD_MODE=1, the chip is in standalone mode and pins have their CFG functions. When tied high, the SPI interface is enabled. Integrated pull down resistor. dcStep enable input (SD_MODE=1, SPI_MODE=1) – leave open or tie to GND for normal operation in this mode (no dcStep). Configuration input (SPI_MODE=0) dcStep gating input for axis synchronization (SD_MODE=1, SPI_MODE=1) or Configuration input (SPI_MODE=0) dcStep ready output (SD_MODE=1). With SD_MODE=0, pull to GND or VCC_IO Diagnostics output DIAG0. Interrupt output Use external pullup resistor with 47k or less in open drain mode. Diagnostics output DIAG1. Use external pullup resistor with 47k or less in open drain mode. Enable input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a high level. 12 TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) Pin TQFP VCC 29 CPO 31 CPI 32 VS 33 VCP CA2 HA2 BMA2 LA2 LA1 BMA1 HA1 CA1 CB2 HB2 BMB2 LB2 LB1 BMB1 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Exposed die pad - Type 13 Function 5V supply input for digital circuitry within chip. Provide 100nF or bigger capacitor to GND (GND plane) near pin. Shall be supplied by 5VOUT. A 2.2 or 3.3 Ohm resistor is recommended for decoupling noise from 5VOUT. When using an external supply, make sure, that VCC comes up before or in parallel to 5VOUT or VCC_IO, whichever comes up later! Charge pump capacitor output. Charge pump capacitor input. Tie to CPO using 22nF, 100V capacitor. Motor supply voltage. Provide filtering capacity near pin with short loop to GND plane. Must be tied to the positive bridge supply voltage. Charge pump voltage. Tie to VS using 100nF capacitor. Bootstrap capacitor positive connection. High side gate driver output. Bridge Center and bootstrap capacitor negative connection. Low side gate driver output. Low side gate driver output. Bridge Center and bootstrap capacitor negative connection. High side gate driver output. Bootstrap capacitor positive connection. Bootstrap capacitor positive connection. High side gate driver output. Bridge Center and bootstrap capacitor negative connection. Low side gate driver output. Low side gate driver output. Bridge Center and bootstrap capacitor negative connection. Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane. Serves as GND pin for the low side gate drivers. Ensure low loop inductivity to sense resistor GND. *(pd) denominates a pin with pulldown resistor * All digital pins DI, DIO and DO use VCC_IO level and contain protection diodes to GND and VCC_IO * All digital inputs DI and DIO have internal Schmitt-Triggers www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 3 14 Sample Circuits The following sample circuits show the required external components in different operation and supply modes. The connection of the bus interface and further digital signals are left out for clarity. 3.1 Standard Application Circuit +VM 100n VSA 12VOUT 100n 2.2µ 2.2µ 5VOUT CE VS 100n 16V VCP CPI 22n 100V CPO +VM DIR STEP Optional use lower voltage down to 12V CB2 11.5V Voltage regulator charge pump Step&Dir input with microPlyer HS 5V Voltage regulator HS HB2 CB CB1 CB HB1 BMB1 2R2 470n RG RG RG RG VCC BMB2 470n TMC2160 CSN SCK SDI SDO DIAG0 LB2 LS SRBH SPI interface 47R RS SRBL Sequencer DIAG1 LB1 LS S Chopper CA2 B.Dwersteg, © TRINAMIC 2014 DIAG out interface HS CB N +VM 47R HA2 stepper motor 470n CA1 HS opt. ext. clock 12-16MHz HA1 CB BMA1 RG RG RG RG CLK_IN BMA2 +VIO 3.3V or 5V I/O voltage LA1 LS VCC_IO LA2 LS 100n SRAH dcStep interface +VIO N 47R RS SRAL pd Use low inductivity SMD type, e.g. 1210 or 2512 resistor for RS! Optional dcStep control interface, tie DCEN to GND for normal operation GNDA GNDD DIE PAD TST_MODE 47R DRV_ENN DCIN pd B DCEN SPI_MODE pd A DCO mode selection Keep inductivity of the fat interconnections as small as possible to avoid undershoot of BM 40kHz, or at clock frequency >12MHz, it is recommended to use a VSA supply not higher than 40V. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 16 3.3 Choosing MOSFETs and Slope The selection of power MOSFETs depends on a number of factors, like package size, on-resistance, voltage rating and supplier. It is not true, that larger, lower RDSon MOSFETs will always be better, as a larger device also has higher capacitances and may add more ringing in trace inductance and power dissipation in the gate drive circuitry. Adapt the MOSFETs to the required motor voltage (adding 5-10V of reserve to the peak supply voltage) and to the desired maximum current, in a way that resistive power dissipation still is low for the thermal capabilities of the chosen MOSFET package. The TMC2160 drives the MOSFET gates with roughly 10V, so normal, 10V specified types are sufficient. Logic level FETs (4.5V specified RDSon) will also work, but may be more critical with regard to bridge crossconduction due to lower VGS(th). The gate drive current and MOSFET gate resistors R G (optional) determine switching behavior and should basically be adapted to the MOSFET gate-drain charge (Miller charge). Figure 3.3 shows the influence of the Miller charge on the switching event. Figure 3.4 additionally shows the switching events in different load situations (load pulling the output up or down), and the required bridge brake-before-make time. The following table shall serve as a thumb rule for programming the MOSFET driver current (DRVSTRENGTH setting) and the selection of gate resistors: MOSFET MILLER CHARGE VS. DRVSTRENGTH AND RG Miller Charge [nC] (typ.) 60 DRVSTRENGTH setting 0 0 or 1 1 or 2 2 or 3 3 Value of RG [Ω] ≤ ≤ ≤ ≤ ≤ 15 10 7.5 5 2.7 The TMC2160 provides increased gate-off drive current to avoid bridge cross-conduction induced by high dV/dt. This protection will be less efficient with gate resistors exceeding the values given in the table. Therefore, for larger values of RG, a parallel diode may be required to ensure keeping the MOSFET safely off during switching events. 10 25 VM 8 20 6 15 4 10 2 5 0 0 5 10 15 20 VDS – Drain to source voltage (V) VGS – Gate to source voltage (V) MOSFET gate charge vs. switching event 0 25 QMILLER QG – Total gate charge (nC) Figure 3.3 Miller charge determines switching slope Hints - Choose modern MOSFETs with fast and soft recovery bulk diode and low reverse recovery charge. - A small, SMD MOSFET package allows compacter routing and reduces parasitic inductance effects. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 17 V12VOUT Miller plateau Lx MOSFET drivers 0V VVM Output slope BMx 0V Output slope -1.2V VVM+V12VOUT VVM Hx 0V VCX-VBMx HxBMx Miller plateau 0V tBBM tBBM tBBM Effective break-before-make time Load pulling BMx down Load pulling BMx up Figure 3.4 Slopes, Miller plateau and blank time The following DRV_CONF parameters allow adapting the driver to the MOSFET bridge: Parameter BBMTIME Description Break-before-make time setting to ensure nonoverlapping switching of high-side and low-side MOSFETs. BBMTIME allows fine tuning of times in increments shorter than a clock period. For higher times, use BBMCLKS. BBMCLKS Like BBMTIME, but in multiple of a clock cycle. The longer setting rules (BBMTIME vs. BBMCLKS). DRV_ Selection of gate driver current. Adapts the gate STRENGTH driver current to the gate charge of the external MOSFETs. FILT_ISENSE Filter time constant of sense amplifier to suppress ringing and coupling from second coil operation Hint: Increase setting if motor chopper noise occurs due to cross-coupling of both coils. (Reset Default = %00) Setting 0…24 0…15 0…3 0…3 Comment time[ns] 100ns*32/(32-BBMTIME) Ensure ~30% headroom Reset Default: 0 0: off Reset Default: OTP 4 or 2 Reset Default = 2 00: 01: 10: 11: ~100ns (reset default) ~200ns ~300ns ~400ns DRV_CONF Parameters Use the lowest gate driver strength setting DRVSTRENGTH giving favorable switching slopes, before increasing the value of the gate series resistors. A slope time of nominal 40ns to 80ns is absolutely sufficient and will normally be covered by the shortest possible Break-Before-Make time setting (BBMTIME=0, BBMCLKS=0). In case slower slopes have to be used, e.g. with large MOSFETs, ensure that the break-before-make time (BBMTIME, optionally use BBMCLKS for times >200ns) sufficiently covers the switching event, in order to avoid bridge cross conduction. The shortest break-before-make time, safely covering the switching event, gives best results. Add roughly 30% of reserve, to cover production stray of MOSFETs and driver. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 18 3.4 Tuning the MOSFET Bridge A clean switching event is favorable to ensure low power dissipation and good EMC behavior. Unsuitable layout or components endanger stable operation of the circuit. Therefore, it is important to understand the effect of parasitic trace inductivity and MOSFET reverse recovery. Stray inductance in power routing will cause ringing whenever the opposite MOSFET is in diode conduction prior to switching on a low-side MOSFET or high-side MOSFET. Diode conduction occurs during break-before make time when the load current is inverse to the prior bridge polarity, i.e. following a fast decay cycle. The MOSFET bulk diode has a certain, type specific reverse recovery time and charge. This time typically is in the range of a few 10ns. During reverse recovery time, the bulk diode will cause high current flow across the bridge. This current is taken from the power supply filter capacitors (see thick lines Figure 3.5). Once the diode opens parasitic inductance tries to keep the current flowing. A high, fast slope results and leads to ringing in all parasitic inductivities (see Figure 3.6). This may lead to bridge voltage undershooting the GND level. It must be ensured, that the driver IC does not see spikes on its BM pins to GND going below -5V. Measure the voltage directly at the driver pins to driver GND. The amount of undershooting depends on energy stored in parasitic inductivities from low side drain to low side source and via the sense resistor RS to GND. To improve behavior - Tune MOSFET switching slopes (measure without inductive load) to be slower than the MOSFET bulk diode reverse recovery time. This will reduce cross conduction. - Add optional resistors and capacitors to ensure clean switching by minimizing ringing and reliable operation. Figure 3.5 shows different options. - Some MOSFETs eliminate this problem by integrating a Schottky diode from source to drain. Figure 3.7 shows performance of the basic circuit after adapting switching slope and adding 1nF bridge output capacitors. RG‘: optional position for high side slope control resistor. In case, severe undershooting < -5V of BM occurs at BM terminal, RG’ will protect the driver. CA2 +VM CB HA2 HS 1µF CA1 HA1 HS CB BMA1 RG RG RG‘ Coil out BMA2 RG‘ LA1 LS RG RG 1n, 100V 1n, 100V LA2 LS SRAH SRAL 47R 2n2 RS 100n 470pF to a few nF output capacitors close to bridge reduce ringing and improve EMC Capacitor reduces ringing on sense resistor. GNDD GNDA DIE PAD 47R RC-Filter protects SRAH / SRAL and reduces spikes seen by the chopper Additional 1A type Schottky Diodes (selected for full VM range) in combination with RG’ eliminate undershooting of BM and allow for lower values of RG‘ (e.g., 2R2 to 4R7). Decide use and value of the additional components based on measurements of the actual circuit using the final layout! Figure 3.5 Bridge protection options for power routing inductivity www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 19 Figure 3.6 Ringing of output (blue) and Gate voltages (Yellow, Cyan) with untuned brige Figure 3.7 Switching event with optimized components (without / after bulk diode conduction) BRIDGE OPTIMIZATION EXAMPLE A stepper driver for 6A of motor current has been designed using the MOSFET AOD4126 in the standard schematic. The MOSFETs have a low gate capacitance and offer roughly 50ns slope time at the lowest driver strength setting. At lowest driver strength setting, switching quality is best (Figure 3.6), but still shows a lot of ringing. Low side gate resistors have been added to slightly increase switching slope time following high-side bulk diode conduction by increasing the effect of Gate-Drain (Miller) charge. High side gate resistors have been added for symmetry. Tests showed, that 1nF output capacitors dramatically reduce ringing of the power bridge following bulk diode conduction (Figure 3.7). Figure 3.8 shows the actual components and values after optimization. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) CA2 HS 20 +VM 470n HA2 4.7µF CA1 HS HA1 4x AOD4126 470n BMA1 10R 10R Coil out BMA2 LA1 LS 10R 10R 1n, 100V 1n, 100V LA2 LS SRAH 47R 50m, 2512 SRAL GNDD GNDA DIE PAD 47R Figure 3.8 Example for bridge with tuned components (see scope shots) - - - Hints Tune the bridge layout for minimum loop inductivity. A compact layout is best. Keep MOSFET gate connections short and straight and avoid loop inductivity between BM and corresponding HS driver pin. Loop inductance is minimized with parallel traces, or adjacent traces on adjacent layers. A wider trace reduces inductivity (don’t use minimum trace width). Minimize the length of the sense resistor to low side MOSFET source, and place the TMC2160 near the sense resistor’s GND connection, with its GND connections directly connected to the same GND plane. Optimize switching behavior by tuning gate current setting and gate resistors. Add MOSFET bridge output capacitors (470pF to a few nF) to reduce ringing. Measure the performance of the bridge by probing BM pins directly at the bridge or at the TMC2160 using a short GND tip on the scope probe rather than a GND cable, if available. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 4 21 SPI Interface 4.1 SPI Datagram Structure The TMC2160 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are typically able to communicate using integer multiples of 8 bit. The NCS line of the device must be handled in a way, that it stays active (low) for the complete duration of the datagram transmission. Each datagram sent to the device is composed of an address byte followed by four data bytes. This allows direct 32 bit data word communication with the register set. Each register is accessed via 32 data bits even if it uses less than 32 data bits. For simplification, each register is specified by a one-byte address: - For a read access the most significant bit of the address byte is 0. - For a write access the most significant bit of the address byte is 1. Most registers are write only registers, some can be read additionally, and there are also some read only registers. SPI DATAGRAM STRUCTURE MSB (transmitted first) 40 bit 39 ... → 8 bit address  8 bit SPI status ... 0  → 32 bit data 39 ... 32 → to TMC2160 RW + 7 bit address  from TMC2160 8 bit SPI status W 39 / 38 ... 32 38...32 LSB (transmitted last) 31 ... 0 8 bit data 8 bit data 31 ... 24 31...28 27...24 23 ... 16 23...20 19...16 8 bit data 8 bit data 15 ... 8 15...12 7 ... 0 11...8 7...4 3...0 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 4.1.1 Selection of Write / Read (WRITE_notREAD) The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to be added to the address for a write access. The SPI interface always delivers data back to the master, independent of the W bit. The data transferred back is the data read from the address which was transmitted with the previous datagram, if the previous access was a read access. If the previous access was a write access, then the data read back mirrors the previously received write data. So, the difference between a read and a write access is that the read access does not transfer data to the addressed register but it transfers the address only and its 32 data bits are dummies, and, further the following read or write access delivers back the data read from the address transmitted in the preceding read cycle. A read access request datagram uses dummy write data. Read data is transferred back to the master with the subsequent read or write access. Hence, reading multiple registers can be done in a pipelined fashion. Whenever data is read from or written to the TMC2160, the MSBs delivered back contain the SPI status, SPI_STATUS, a number of eight selected status bits. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 22 Example: For a read access to the register (XACTUAL) with the address 0x21, the address byte has to be set to 0x21 in the access preceding the read access. For a write access to the register (IHOLD_IRUN), the address byte has to be set to 0x80 + 0x10 = 0x90. For read access, the data bit might have any value (-). So, one can set them to 0. action data sent to TMC2160 read TSTEP → 0x1200000000 read TSTEP → 0x1200000000 write IHOLD_IRUN:= 0x00011F10 → 0xA700ABCDEF write IHOLD_IRUN:= 0x00021807 → 0xA700123456 data received from TMC2160  0xSS & unused data  0xSS & TSTEP  0xSS & TSTEP  0xSS00011F10 *)S: is a placeholder for the status bits SPI_STATUS 4.1.2 SPI Status Bits Transferred with Each Datagram Read Back New status information becomes latched at the end of each access and is available with the next SPI transfer. SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32 Bit 7 6 5 4 3 2 1 0 Name Comment Unused Unused Unused Unused standstill sg2 driver_error reset_flag Ignore this bit Ignore this bit Ignore this bit Ignore this bit DRV_STATUS[31] – 1: Signals motor stand still DRV_STATUS[24] – 1: Signals stallGuard flag active GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT) GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT) 4.1.3 Data Alignment All data are right aligned. Some registers represent unsigned (positive) values, some represent integer values (signed) as two’s complement numbers, single bits or groups of bits are represented as single bits respectively as integer groups. 4.2 SPI Signals The SPI bus on the TMC2160 has four signals: - SCK – bus clock input - SDI – serial data input - SDO – serial data output - CSN – chip select input (active low) The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum of 40 SCK clock cycles is required for a bus transaction with the TMC2160. If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a 40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips. CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal shift register are latched into the internal control register and recognized as a command from the master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge of CSN are recognized as the command. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 23 4.3 Timing The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional 10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the timing parameters of an SPI bus transaction, and the table below specifies their values. CSN tCC tCL tCH tCH tCC SCK tDU SDI bit39 tDH bit38 bit0 tDO SDO tZC bit39 bit38 bit0 Figure 4.1 SPI timing Hint Usually this SPI timing is referred to as SPI MODE 3 SPI interface timing Parameter SCK valid before or after change of CSN AC-Characteristics clock period: tCLK Symbol tCC fSCK fSCK assumes synchronous CLK tCSH SCK low time tCL SCK high time tCH www.trinamic.com Min Typ Max 10 *) Min time is for synchronous CLK with SCK high one tCH before CSN high only *) Min time is for synchronous CLK only *) Min time is for synchronous CLK only assumes minimum OSC frequency CSN high time SCK frequency using internal clock SCK frequency using external 16MHz clock SDI setup time before rising edge of SCK SDI hold time after rising edge of SCK Data out valid time after falling SCK clock edge SDI, SCK and CSN filter delay time Conditions Unit ns tCLK*) >2tCLK+10 ns tCLK*) >tCLK+10 ns tCLK*) >tCLK+10 ns 4 MHz 8 MHz tDU 10 ns tDH 10 ns tDO no capacitive load on SDO tFILT rising and falling edge 12 20 tFILT+5 ns 30 ns TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 5 24 Register Mapping This chapter gives an overview of the complete register set. Some of the registers bundling a number of single bits are detailed in extra tables. The functional practical application of the settings is detailed in dedicated chapters. Note - All registers become reset to 0 upon power up, unless otherwise noted. - Add 0x80 to the address Addr for write accesses! NOTATION OF HEXADECIMAL AND BINARY NUMBERS 0x % precedes a hexadecimal number, e.g. 0x04 precedes a multi-bit binary number, e.g. %100 NOTATION OF R/W FIELD R W R/W R+C Read only Write only Read- and writable register Clear upon read OVERVIEW REGISTER MAPPING REGISTER DESCRIPTION General Configuration Registers These registers contain global configuration global status flags interface configuration and I/O signal configuration This register set offers registers for driver current control setting thresholds for coolStep operation setting thresholds for different chopper modes setting thresholds for dcStep operation This register set offers registers for setting / reading out microstep table and counter chopper and driver configuration coolStep and stallGuard2 configuration dcStep configuration reading out stallGuard2 values and driver error flags Velocity Dependent Driver Feature Control Register Set Motor Driver Register Set www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 25 5.1 General Configuration Registers GENERAL CONFIGURATION REGISTERS (0X00…0X0F) R/W Addr n RW 0x00 17 www.trinamic.com Register GCONF Description / bit names Bit GCONF – Global configuration flags 0 recalibrate 1: Zero crossing recalibration during driver disable (via ENN or via TOFF setting) 1 faststandstill Timeout for step execution until standstill detection: 1: Short time: 2^18 clocks 0: Normal time: 2^20 clocks 2 en_pwm_mode 1: stealthChop voltage PWM mode enabled (depending on velocity thresholds). Switch from off to on state while in stand-still and at IHOLD= nominal IRUN current, only. 3 multistep_filt 1: Enable step input filtering for stealthChop optimization with external step source (default=1) 4 shaft 1: Inverse motor direction 5 diag0_error 1: Enable DIAG0 active on driver errors: Over temperature (ot), short to GND (s2g), undervoltage chargepump (uv_cp) DIAG0 always shows the reset-status, i.e. is active low during reset condition. 6 diag0_otpw 1: Enable DIAG0 active on driver over temperature prewarning (otpw) 7 diag0_stall 1: Enable DIAG0 active on motor stall (set TCOOLTHRS before using this feature) 8 diag1_stall 1: Enable DIAG1 active on motor stall (set TCOOLTHRS before using this feature) 9 diag1_index 1: Enable DIAG1 active on index position (microstep look up table position 0) 10 diag1_onstate 1: Enable DIAG1 active when chopper is on (for the coil which is in the second half of the fullstep) 11 diag1_steps_skipped 1: Enable output toggle when steps are skipped in dcStep mode (increment of LOST_STEPS). Do not enable in conjunction with other DIAG1 options. 12 diag0_int_pushpull 0: DIAG0 is open collector output (active low) 1: Enable DIAG0 push pull output (active high) 13 diag1_pushpull 0: DIAG1 is open collector output (active low) 1: Enable DIAG1 push pull output (active high) TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 26 GENERAL CONFIGURATION REGISTERS (0X00…0X0F) R/W Addr n Register R+ WC 0x01 3 GSTAT R 0x04 8 + 8 IOIN W 0x06 www.trinamic.com OTP_PROG Description / bit names 14 small_hysteresis 0: Hysteresis for step frequency comparison is 1/16 1: Hysteresis for step frequency comparison is 1/32 15 stop_enable 0: Normal operation 1: Emergency stop: ENCA_DCIN stops the sequencer when tied high (no steps become executed by the sequencer, motor goes to standstill state). 16 direct_mode 0: Normal operation 1: Motor coil currents and polarity directly programmed via serial interface: Register XDIRECT (0x2D) specifies signed coil A current (bits 8..0) and coil B current (bits 24..16). In this mode, the current is scaled by IHOLD setting. Velocity based current regulation of stealthChop is not available in this mode. The automatic stealthChop current regulation will work only for low stepper motor velocities. 17 test_mode 0: Normal operation 1: Enable analog test output on pin DCO. IHOLD[1..0] selects the function of DCO: 0…2: T120, DAC, VDDH Hint: Not for user, set to 0 for normal operation! Bit GSTAT – Global status flags (Re-Write with ‘1’ bit to clear respective flags) 0 reset 1: Indicates that the IC has been reset. All registers have been cleared to reset values. 1 drv_err 1: Indicates, that the driver has been shut down due to overtemperature or short circuit detection. Read DRV_STATUS for details. The flag can only be cleared when the temperature is below the limit again. 2 uv_cp 1: Indicates an undervoltage on the charge pump. The driver is disabled during undervoltage. This flag is latched for information. Bit INPUT Reads the state of all input pins available 0 STEP 1 DIR 2 DCEN_CFG4 3 DCIN_CFG5 4 DRV_ENN 5 DCO_CFG6 6 1 7 unused 31.. VERSION: 0x30=first version of the IC 24 Identical numbers mean full digital compatibility. Bit OTP_PROGRAM – OTP programming TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 27 GENERAL CONFIGURATION REGISTERS (0X00…0X0F) R/W Addr R 0x07 RW 0x08 n Register OTP_READ 5 FACTORY_ CONF Description / bit names Write access programs OTP memory (one bit at a time), Read access refreshes read data from OTP after a write 2..0 OTPBIT Selection of OTP bit to be programmed to the selected byte location (n=0..7: programs bit n to a logic 1) 5..4 OTPBYTE Set to 00 15..8 OTPMAGIC Set to 0xbd to enable programming. A programming time of minimum 10ms per bit is recommended (check by reading OTP_READ). Bit OTP_READ (Access to OTP memory result and update) See separate table! 7..0 OTP0 byte 0 read data 4..0 FCLKTRIM (Reset default: OTP) 0…31: Lowest to highest clock frequency. Check at charge pump output. The frequency span is not guaranteed, but it is tested, that tuning to 12MHz internal clock is possible. The devices come preset to 12MHz clock frequency by OTP programming. (Reset Default: OTP) Bit SHORT_CONF 3..0 S2VS_LEVEL: Short to VS detector level for lowside FETs. Checks for voltage drop in LS MOSFET and sense resistor. 4 (highest sensitivity) … 15 (lowest sensitivity) 11..8 W 0x09 19 SHORT_ CONF 17..16 18 W 0x0A 22 www.trinamic.com DRV_CONF Bit Hint: Settings from 1 to 3 will trigger during normal operation due to voltage drop on sense resistor. (Reset Default: OTP 6 or 12) S2G_LEVEL: Short to GND detector level for highside FETs. Checks for voltage drop on high side MOSFET 2 (highest sensitivity) … 15 (lowest sensitivity) Attention: Settings below 6 not recommended at >52V operation – false detection might result (Reset Default: OTP 6 or 12) SHORTFILTER: Spike filtering bandwidth for short detection 0 (lowest, 100ns), 1 (1µs), 2 (2µs) 3 (3µs) Hint: A good PCB layout will allow using setting 0. Increase value, if erroneous short detection occurs. (Reset Default = %01) shortdelay: Short detection delay 0=750ns: normal, 1=1500ns: high The short detection delay shall cover the bridge switching time. 0 will work for most applications. (Reset Default = 0) DRV_CONF TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 28 GENERAL CONFIGURATION REGISTERS (0X00…0X0F) R/W Addr n Register Description / bit names 4..0 BBMTIME: Break-Before make delay 0=shortest (100ns) … 16 (200ns) … 24=longest (375ns) >24 not recommended, use BBMCLKS instead 11..8 17..16 19..18 21..20 Hint: Choose the lowest setting safely covering the switching event in order to avoid bridge crossconduction. Add roughly 30% of reserve. (Reset Default = 0) BBMCLKS: 0..15: Digital BBM time in clock cycles (typ. 83ns). The longer setting rules (BBMTIME vs. BBMCLKS). (Reset Default: OTP 4 or 2) OTSELECT: Selection of over temperature level for bridge disable, switch on after cool down to 120°C / OTPW level. 00: 150°C 01: 143°C 10: 136°C (not recommended when VSA > 24V) 11: 120°C (not recommended, no hysteresis) Hint: Adapt overtemperature threshold as required to protect the MOSFETs or other components on the PCB. (Reset Default = %00) DRVSTRENGTH: Selection of gate driver current. Adapts the gate driver current to the gate charge of the external MOSFETs. 00: weak 01: weak+TC (medium above OTPW level) 10: medium 11: strong Hint: Choose the lowest setting giving slopes 128 recommended for best results (Reset Default = 0) Offset calibration result phase A (signed) Offset calibration result phase B (signed) TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 5.1.1 30 OTP_READ – OTP configuration memory The OTP memory holds power up defaults for certain registers. All OTP memory bits are cleared to 0 by default. Programming only can set bits, clearing bits is not possible. Factory tuning of the clock frequency affects otp0.0 to otp0.4. The state of these bits therefore may differ between individual ICs. 0X07: OTP_READ – OTP MEMORY MAP Bit 7 Name otp0.7 Function otp_TBL 6 otp0.6 otp_BBM 5 otp0.5 otp_S2_LEVEL 4 3 2 1 0 otp0.4 otp0.3 otp0.2 otp0.1 otp0.0 OTP_FCLKTRIM www.trinamic.com Comment Reset default for TBL: 0: TBL=%10 (~3µs) 1: TBL=%01 (~2µs) Reset default for DRVCONF.BBMCLKS 0: BBMCLKS=4 1: BBMCLKS=2 Reset default for Short detection Levels: 0: S2G_LEVEL = S2VS_LEVEL = 6 1: S2G_LEVEL = S2VS_LEVEL = 12 Reset default for FCLKTRIM 0: lowest frequency setting 31: highest frequency setting Attention: This value is pre-programmed by factory clock trimming to the default clock frequency of 12MHz and differs between individual ICs! It should not be altered. TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 31 5.2 Velocity Dependent Driver Feature Control Register Set VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET (0X10…0X1F) R/W W Addr n 0x10 5 + 5 + 4 Register Description / bit names Bit IHOLD_IRUN – Driver current control 4..0 IHOLD Standstill current (0=1/32…31=32/32) In combination with stealthChop mode, setting IHOLD=0 allows to choose freewheeling or coil short circuit for motor stand still. 12..8 IRUN Motor run current (0=1/32…31=32/32) IHOLD_IRUN 19..16 Hint: Choose sense resistors in a way, that normal IRUN is 16 to 31 for best microstep performance. IHOLDDELAY Controls the number of clock cycles for motor power down after a motion as soon as standstill is detected (stst=1) and TPOWERDOWN has expired. The smooth transition avoids a motor jerk upon power down. 0: 1..15: W R W 0x11 0x12 0x13 8 20 20 www.trinamic.com TPOWER DOWN TSTEP TPWMTHRS instant power down Delay per current reduction step in multiple of 2^18 clocks TPOWERDOWN sets the delay time after stand still (stst) of the motor to motor current power down. Time range is about 0 to 4 seconds. Attention: A minimum setting of 2 is required to allow automatic tuning of stealthChop PWM_OFFS_AUTO. Reset Default = 10 0…((2^8)-1) * 2^18 tCLK Actual measured time between two 1/256 microsteps derived from the step input frequency in units of 1/fCLK. Measured value is (2^20)-1 in case of overflow or stand still. All TSTEP related thresholds use a hysteresis of 1/16 of the compare value to compensate for jitter in the clock or the step frequency. The flag small_hysteresis modifies the hysteresis to a smaller value of 1/32. (Txxx*15/16)-1 or (Txxx*31/32)-1 is used as a second compare value for each comparison value. This means, that the lower switching velocity equals the calculated setting, but the upper switching velocity is higher as defined by the hysteresis setting. In dcStep mode TSTEP will not show the mean velocity of the motor, but the velocities for each microstep, which may not be stable and thus does not represent the real motor velocity in case it runs slower than the target velocity. This is the upper velocity for stealthChop voltage PWM mode. TSTEP ≥ TPWMTHRS - stealthChop PWM mode is enabled, if configured - dcStep is disabled TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 32 VELOCITY DEPENDENT DRIVER FEATURE CONTROL REGISTER SET (0X10…0X1F) R/W W Addr 0x14 n 20 Register TCOOLTHRS Description / bit names This is the lower threshold velocity for switching on smart energy coolStep and stallGuard feature. (unsigned) Set this parameter to disable coolStep at low speeds, where it cannot work reliably. The stop on stall function (enable with sg_stop when using internal motion controller) and the stall output signal become enabled when exceeding this velocity. In non-dcStep mode, it becomes disabled again once the velocity falls below this threshold. TCOOLTHRS ≥ TSTEP ≥ THIGH: - coolStep is enabled, if configured - stealthChop voltage PWM mode is disabled TCOOLTHRS ≥ TSTEP - Stop on stall is enabled, if configured - Stall output signal (DIAG0/1) is enabled, if configured This velocity setting allows velocity dependent switching into a different chopper mode and fullstepping to maximize torque. (unsigned) The stall detection feature becomes switched off for 2-3 electrical periods whenever passing THIGH threshold to compensate for the effect of switching modes. W 0x15 20 THIGH RW 0x2D 9+9 XDIRECT TSTEP ≤ THIGH: - coolStep is disabled (motor runs with normal current scale) - stealthChop voltage PWM mode is disabled - If vhighchm is set, the chopper switches to chm=1 with TFD=0 (constant off time with slow decay, only). - If vhighfs is set, the motor operates in fullstep mode and the stall detection becomes switched over to dcStep stall detection. This register is used in direct coil current 2x mode, only (direct_mode = 1). It bypasses the -255…+255 internal sequencer. Specifies signed coil A current (bits 8..0) and coil B current (bits 24..16). In this mode, the current is scaled by IHOLD setting. Velocity based current regulation of stealthChop is not available in this mode. The automatic stealthChop current regulation will work only for low stepper motor velocities. Microstep velocity time reference t for velocities: TSTEP = fCLK / fSTEP www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 5.2.1 33 dcStep Miniumum Velocity Register DCSTEP MINIMUM VELOCITY REGISTER R/W Addr n Register W 0x33 23 VDCMIN (0X33) Description / bit names Automatic commutation dcStep minimum velocity. Enable dcStep by DCEN pin. In this mode, the actual position is determined by the sensorless motor commutation and becomes fed back to the external motion controller. In case the motor becomes heavily loaded, VDCMIN is used as the minimum step velocity. Hint: Also set DCCTRL parameters in order to operate dcStep. (Only bits 22… 8 are used for value and for comparison) Time reference t for VDCMIN: t = 2^24 / fCLK www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 34 5.3 Motor Driver Registers MICROSTEPPING CONTROL REGISTER SET (0X60…0X6B) R/W Addr n Register MSLUT[0] W 0x60 32 microstep table entries 0…31 MSLUT[1...7] W W W R R 0x61 … 0x67 0x68 0x69 0x6A 0x6B 7 x 32 32 8 + 8 10 9 + 9 www.trinamic.com microstep table entries 32…255 MSLUTSEL MSLUTSTART MSCNT MSCURACT Description / bit names Each bit gives the difference between entry x and entry x+1 when combined with the corresponding MSLUTSEL W bits: 0: W= %00: -1 %01: +0 %10: +1 %11: +2 1: W= %00: +0 %01: +1 %10: +2 %11: +3 This is the differential coding for the first quarter of a wave. Start values for CUR_A and CUR_B are stored for MSCNT position 0 in START_SIN and START_SIN90. ofs31, ofs30, …, ofs01, ofs00 … ofs255, ofs254, …, ofs225, ofs224 This register defines four segments within each quarter MSLUT wave. Four 2 bit entries determine the meaning of a 0 and a 1 bit in the corresponding segment of MSLUT. See separate table! bit 7… 0: START_SIN bit 23… 16: START_SIN90 START_SIN gives the absolute current at microstep table entry 0. START_SIN90 gives the absolute current for microstep table entry at positions 256. Start values are transferred to the microstep registers CUR_A and CUR_B, whenever the reference position MSCNT=0 is passed. Microstep counter. Indicates actual position in the microstep table for CUR_A. CUR_B uses an offset of 256 (2 phase motor). Hint: Move to a position where MSCNT is zero before re-initializing MSLUTSTART or MSLUT and MSLUTSEL. bit 8… 0: CUR_A (signed): Actual microstep current for motor phase A as read from MSLUT (not scaled by current) bit 24… 16: CUR_B (signed): Actual microstep current for motor phase B as read from MSLUT (not scaled by current) Range [Unit] 32x 0 or 1 reset default= sine wave table 7x 32x 0 or 1 reset default= sine wave table 0 1024 clock STEP input, or via the internal VDCMIN setting. - DCIN – Commands the driver to wait with step execution and to disable DCO. This input can be used for synchronization of multiple drivers operating with dcStep. 15.4.1 Using LOST_STEPS for dcStep Operation This is the simplest possibility to integrate dcStep with an external motion controller: The external motion controller enables dcStep using DCEN or the internal velocity threshold. The TMC2160 tries to follow the steps. In case it needs to slow down the motor, it counts the difference between incoming steps on the STEP signal and steps going to the motor. The motion controller can read out the difference and compensate for the difference after the motion or on a cyclic basis. Figure 15.2 shows the principle (simplified). In case the motor driver needs to postpone steps due to detection of a mechanical overload in dcStep, and the motion controller does not react to this by pausing the step generation, LOST_STEPS becomes incremented or decremented (depending on the direction set by DIR) with each step which is not taken. This way, the number of lost steps can be read out and executed later on or be appended to the motion. As the driver needs to slow down the motor while the overload situation persists, the application will benefit from a high microstepping resolution, because it allows more seamless acceleration or deceleration in dcStep operation. In case the application is completely blocked, VDCMIN sets a lower limit to the step execution. If the motor velocity falls below this limit, however an unknown number of steps is lost and the motor position is not exactly known any more. DCIN allows for step synchronization of two drivers: it stops the execution of steps if low and sets DCO low. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 82 Light motor overload reduces effective motor velocity Actual motor velocity VTARGET VDCMIN 0 +IMAX Phase Current (one phase shown) Steps from STEP input skipped by the driver due to light motor overload Theoretical sine wave corresponding to fullstep pattern 0 -IMAX STEP LOSTSTEPS would count down if motion direction is negative LOSTSTEPS 0 2 4 8 12 16 20 22 24 dcStep enabled continuosly DC_EN DC_OUT DCO signals that the driver is not ready for new steps. In this case, the controller does not react to this information. Figure 15.2 Motor moving slower than STEP input due to light overload. LOSTSTEPS incremented 15.4.2 DCO Interface to Motion Controller In STEP/DIR mode, DCEN enables dcStep. It is up to the external motion controller to enable dcStep either, once a minimum step velocity is exceeded within the motion ramp, or to use the automatic threshold VDCMIN for dcStep enable. The STEP/DIR interface works in microstep resolution, even if the internal step execution is based on fullstep. This way, no switching to a different mode of operation is required within the motion controller. The dcStep output DCO signals if the motor is ready for the next step based on the dcStep measurement of the motor. If the motor has not yet mechanically taken the last step, this step cannot be executed, and the driver stops automatically before execution of the next fullstep. This situation is signaled by DCO. The external motion controller shall stop step generation if DCOUT is low and wait until it becomes high again. Figure 15.4 shows this principle. The driver buffers steps during the waiting period up to the number of microstep setting minus one. In case, DCOUT does not go high within the lower step limit time e.g. due to a severe motor overload, a step can be enforced: override the stop status by a long STEP pulse with min. 1024 system clocks length. When using internal clock, a pulse length of minimum 125µs is recommended. DIR STEP µC or Motion Controller TMC2160 DCEN DCO DCIN Optional axis synchronization Figure 15.3 Full signal interconnection for dcStep www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 83 Increasing mechanical load forces slower motion Theoretical sine wave corresponding to fullstep pattern +IMAX Phase Current (one phase shown) 0 -IMAX Long pulse = override motor block situation STEP STEP_FILT_INTERN ∆2 ∆2 ∆2 ∆2 ∆2 ∆2 ∆2 DCEN INTCOM DCO DC_OUT TIMEOUT (in controller) TIMOUT counter in controller ∆2 = MRES (number of microsteps per fullstep) Figure 15.4 DCO Interface to motion controller – step generator stops when DCO is asserted www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 84 16 Sine-Wave Look-up Table The TMC2160 driver provides a programmable look-up table for storing the microstep current wave. As a default, the table is pre-programmed with a sine wave, which is a good starting point for most stepper motors. Reprogramming the table to a motor specific wave allows drastically improved microstepping especially with low-cost motors. 16.1 User Benefits Microstepping Motor Torque – – – extremely improved with low cost motors runs smooth and quiet reduced mechanical resonances yields improved torque 16.2 Microstep Table In order to minimize required memory and the amount of data to be programmed, only a quarter of the wave becomes stored. The internal microstep table maps the microstep wave from 0° to 90°. It becomes symmetrically extended to 360°. When reading out the table the 10-bit microstep counter MSCNT addresses the fully extended wave table. The table is stored in an incremental fashion, using each one bit per entry. Therefore only 256 bits (ofs00 to ofs255) are required to store the quarter wave. These bits are mapped to eight 32 bit registers. Each ofs bit controls the addition of an inclination Wx or Wx+1 when advancing one step in the table. When Wx is 0, a 1 bit in the table at the actual microstep position means “add one” when advancing to the next microstep. As the wave can have a higher inclination than 1, the base inclinations Wx can be programmed to -1, 0, 1, or 2 using up to four flexible programmable segments within the quarter wave. This way even negative inclination can be realized. The four inclination segments are controlled by the position registers X1 to X3. Inclination segment 0 goes from microstep position 0 to X1-1 and its base inclination is controlled by W0, segment 1 goes from X1 to X2-1 with its base inclination controlled by W1, etc. When modifying the wave, care must be taken to ensure a smooth and symmetrical zero transition when the quarter wave becomes expanded to a full wave. The maximum resulting swing of the wave should be adjusted to a range of -248 to 248, in order to give the best possible resolution while leaving headroom for the hysteresis-based chopper to add an offset. W3: -1/+0 256 W2: +0/+1 W1: +1/+2 W0: +2/+3 y 248 START_SIN90 0 X1 X2 X3 LUT stores entries 0 to 255 255 256 START_SIN -248 Figure 16.1 LUT programming example www.trinamic.com 512 768 0 MSCNT TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 85 When the microstep sequencer advances within the table, it calculates the actual current values for the motor coils with each microstep and stores them to the registers CUR_A and CUR_B. However, the incremental coding requires an absolute initialization, especially when the microstep table becomes modified. Therefore CUR_A and CUR_B become initialized whenever MSCNT passes zero. Two registers control the starting values of the tables: - As the starting value at zero is not necessarily 0 (it might be 1 or 2), it can be programmed into the starting point register START_SIN. - In the same way, the start of the second wave for the second motor coil needs to be stored in START_SIN90. This register stores the resulting table entry for a phase shift of 90° for a 2phase motor. Hint Refer chapter 5.3 for the register set and for the default table function stored in the drivers. The default table is a good base for realizing an own table. The TMC2160-EVAL comes with a calculation tool for own waves. Initialization example for the default microstep table: MSLUT[0]= MSLUT[1]= MSLUT[2]= MSLUT[3]= MSLUT[4]= MSLUT[5]= MSLUT[6]= MSLUT[7]= %10101010101010101011010101010100 %01001010100101010101010010101010 %00100100010010010010100100101001 %00010000000100000100001000100010 %11111011111111111111111111111111 %10110101101110110111011101111101 %01001001001010010101010101010110 %00000000010000000100001000100010 = = = = = = = = 0xAAAAB554 0x4A9554AA 0x24492929 0x10104222 0xFBFFFFFF 0xB5BB777D 0x49295556 0x00404222 MSLUTSEL= 0xFFFF8056: X1=128, X2=255, X3=255 W3=%01, W2=%01, W1=%01, W0=%10 MSLUTSTART= 0x00F70000: START_SIN_0= 0, START_SIN90= 247 17 Emergency Stop The driver provides a negative active enable pin ENN to safely switch off all power MOSFETs. This allows putting the motor into freewheeling. Further, it is a safe hardware function whenever an emergency-stop not coupled to software is required. Some applications may require the driver to be put into a state with active holding current or with a passive braking mode. This is possible by programming the pin DCIN to act as a step disable function. Set GCONF flag stop_enable to activate this option. Whenever DCIN becomes pulled up, the motor will stop abruptly and go to the power down state, as configured via IHOLD, IHOLD_DELAY and stealthChop standstill options. Disabling the driver via ENN will require three clock cycles to safely switch off the driver. www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 86 18 Quick Configuration Guide This guide is meant as a practical tool to come to a first configuration and do a minimum set of measurements and decisions for tuning the driver. It does not cover all advanced functionalities but concentrates on the basic function set to make a motor run smoothly. Once the motor runs, you may decide to explore additional features, e.g. freewheeling and further functionality in more detail. A current probe on one motor coil is a good aid to find the best settings, but it is not a must. CURRENT SETTING AND FIRST STEPS WITH STEALTHCHOP Current Setting stealthChop Configuration Check hardware setup and motor RMS current GCONF set en_pwm_mode Set GLOBALSCALER as required to reach maximum motor current at I_RUN=31 PWMCONF set pwm_autoscale, set pwm_autograd Set I_RUN as desired up to 31, I_HOLD 70% of I_RUN or lower Set I_HOLD_DELAY to 1 to 15 for smooth standstill current decay PWMCONF select PWM_FREQ with regard to fCLK for 2040kHz PWM frequency Set TPOWERDOWN up to 255 for delayed standstill current reduction CHOPCONF Enable chopper using basic config., e.g.: TOFF=5, TBL=2, HSTART=4, HEND=0 Configure Chopper to test current settings Execute automatic tuning procedure AT Move the motor by slowly accelerating from 0 to VMAX operation velocity Is performance good up to VMAX? Y SC2 Figure 18.1 Current setting and first steps with stealthChop www.trinamic.com N Select a velocity threshold for switching to spreadCycle chopper and set TPWMTHRS TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 87 TUNING STEALTHCHOP AND SPREADCYCLE SC2 spreadCycle Configuration Try motion above TPWMTRHRS, if used GCONF en_pwm_mode=0 Coil current overshoot upon deceleration? Y PWMCONF decrease PWM_LIM (do not go below about 5) N Move the motor by slowly accelerating from 0 to VMAX operation velocity Go to motor stand still and check motor current at IHOLD=IRUN Stand still current too high? CHOPCONF Enable chopper using basic config.: TOFF=5, TBL=2, HSTART=0, HEND=0 Y CHOPCONF, PWMCONF decrease TBL or PWM frequency and check impact on motor motion N Optimize spreadCycle configuration if TPWMTHRS used Monitor sine wave motor coil currents with current probe at low velocity Current zero crossing smooth? N CHOPCONF increase HEND (max. 15) Y CHOPCONF decrease TOFF (min. 2), try lower / higher TBL or reduce motor current Y CHOPCONF decrease HEND and increase HSTART (max. 7) Y Move motor very slowly or try at stand still Audible Chopper noise? N Move motor at medium velocity or up to max. velocity Audible Chopper noise? Finished or enable coolStep Figure 18.2 Tuning stealthChop and spreadCycle www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 88 ENABLING COOLSTEP (ONLY IN COMBINATION WITH SPREADCYCLE) Enable coolStep C2 Move the motor by slowly accelerating from 0 to VMAX operation velocity Monitor CS_ACTUAL and motor torque during rapid mechanical load increment within application limits Is coil current sineshaped at VMAX? N Decrease VMAX Does CS_ACTUAL reach IRUN with load before motor stall? Y Set THIGH To match TSTEP at VMAX for upper coolStep velocity limit Finished Monitor SG_RESULT value during medium velocity and check response with mechanical load Does SG_RESULT go down to 0 with load? Y Increase SGT N Increase SEMIN or choose narrower velocity limits N Set TCOOLTHRS slightly above TSTEP at the selected velocity for lower velocity limit COOLCONF Enable coolStep basic config.: SEMIN=1, all other 0 Monitor CS_ACTUAL during motion in velocity range and check response with mechanical load Does CS_ACTUAL reach IRUN with load before motor stall? C2 Figure 18.3 Enabling coolStep (only in combination with spreadCycle) www.trinamic.com N Increase SEUP TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 89 SETTING UP DCSTEP Enable dcStep Configure dcStep Stall Detection CHOPCONF Make sure, that TOFF is not less than 3. Use lowest good TBL. Set vhighfs and vhighchm DCCTRL Set DC_SG to 1 + 1/16 the value of DC_TIME Set VDCMIN to about 5% to 20% of the desired operation velocity Set TCOOLTHRS to match TSTEP at a velocity slightly above VDCMIN for lower stallGuard velocity limit DCCTRL Set DC_TIME depending on TBL: %00: 17; %01: 25 %10: 37; %11: 55 SW_MODE Enable sg_stop to stop the motor upon stall detection Start the motor at the targeted velocity VMAX and try to apply load Does the motor reach VMAX and have good torque? Read out RAMP_STAT to clear event_stop_sg and restart the motor N Increase DC_TIME Accelerate the motor from 0 to VMAX Y Does the motor stop during acceleration? Restart the motor and try to slow it down to VDCMIN by applying load Y Decrease TCOOLTHRS to raise the lower velocity for stallGuard N Increase DC_SG N Does the motor reach VDCMIN without step loss? N Decrease DC_TIME or increase TOFF or increase VDCMIN Slow down the motor to VDCMIN by applying load. Further increase load to stall the motor. Y Finished or configure dcStep stall detection Does the motor stop upon the first stall? Y Finished Figure 18.4 Setting up dcStep (using TMC4361 as motion controller) www.trinamic.com TMC2160 DATASHEET (Rev. 1.01 / 2018-OKT-29) 90 19 Getting Started Please refer to the TMC2160 evaluation board to allow a quick start with the device, and in order to allow interactive tuning of the device setup in your application. Chapter 18 will guide you through the process of correctly setting up all registers. 19.1 Initialization Examples SPI datagram example sequence to enable the driver for step and direction operation and initialize the chopper for spreadCycle operation and for stealthChop at