TMC4361A-EVAL

Motion Controller for Stepper Motors Integrated Circuits TMC4361A DATASHEET TMC4361A Document Revision 1.22 • 2017-JAN-12 SHORT SPEC The S-ramp and sixPoint™ ramp motion controller for stepper motors is optimized for high velocities, allowing on-the-fly changes. TMC4361A offers SPI and Step/Dir interfaces, as well as an encoder interface for closed-loop operation. NOTE:  TMC4361A is a product upgrade of TMC4361. Features Figure 1: Sample Image TMC4361A Closed-Loop Drive *Marking details are explained on page 223.  SPI Interfaces for µC with easy-to-use protocol.  SPI Interfaces for SPI motor stepper drivers.  Encoder interface for incremental or serial encoders.  Closed-loop operation for Step and SPI drivers.  Integrated ChopSync™ and dcStep™ support.  Internal ramp generator generating S-shaped ramps or sixPoint™ ramps supporting on-the-fly changes.  Controlled PWM output.  Reference switch handling.  Hardware and virtual stop switches.  Extensive Support of TMC stepper motor drivers. Applications     Textile, sewing machines CCTV, security Printers, scanners ATM, cash recycler     Office automation POS Factory automation Lab automation     Pumps and valves Heliostat controllers CNC machines Robotics Block Diagram: TMC4361A Interfaces & Features START Ref. Switches TMC4361 SPI to µC INTR / TR to µC CLK NRST SPI to Master Status Flags Interrupt Controller Power-on Reset Ref. Switch Processing Timer Unit S-Ramp Generator incl. trapezoid, rectangle, 4bows dcStep Step Sequencer Current Regulation Driver Interface: SPI / Step/Dir Encoder Interface Safe Ramp Down NFreeze Figure 2: Block Diagram © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com. Read entire documentation; especially the Supplemental Directives in chapter 22 (page 224).  SHORT SPEC  Closed Loop SPI Step/Dir ABN SSI SPI TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 2/230 Functional Scope of TMC4361A TMC4361A is a miniaturized high-performance motion controller for stepper motor drivers, particularly designed for fast and jerk-limited motion profile applications with a wide range of ramp profiles. The S-shaped or sixPoint™ velocity profile, closed-loop and open-loop features offer many configuration options to suit the user’s specifications, as presented below: S-Shaped Velocity Profile S-shaped ramp profiles are jerk-free. Seven ramp segments form the S-shaped ramp that can be optimally adapted to suit the user’s requirements. High torque with high velocities can be reached by calibrating the bows of the ramp, as explained in this user manual. v(t) VMAX t Figure 3: S-shaped Velocity Profile i Closed-loop Operation Feature More information on ramp configurations and other velocity profiles, e.g. sixPoint™ ramps, are provided in chapter 6 (Page 28). A typical hardware setup for closed-loop operation with a TMC262 stepper motor gate driver is shown in the diagram below. In case internal MOSFETs are desired, combine the TMC4361A with the TMC2620, the TMC261 or the TMC2660. High level interface µC SPI TMC4361 Motion Controller SPI TMC262 MOSFET Motor Gate Driver Driver Stage M Encoder ABN/ SSI/SPI Figure 4: Hardware Set-up for Closed-loop Operation with TMC262 Open-loop Operation with dcStep™ Feature A typical hardware setup for dcStep operation with a TMC2130 stepper motor driver is shown in the diagram below. This feature is also available for TMC26x stepper motor drivers. SPI High level interface µC SPI TMC4361 Motion Controller S/D TMC2130 Motor Driver M dcStep™ signals Figure 5: Hardware Set-up for Open-loop Operation with TMC2130 Order Codes Order code Description Size TMC4361A-LA Motion controller with closed-loop and dcStep features, QFN40 6 x 6 mm2 Table 1: TMC4361A Order Codes © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the Supplemental Directives on page 224.  SHORT SPEC  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 3/230 T A BL E O F C O NT E NT S TMC4361A DATASHEET .................................................................................................... 1 SHORT SPEC ..................................................................................................................... 1 Features ........................................................................................................................... 1 Applications ..................................................................................................................... 1 Block Diagram: TMC4361A Interfaces & Features ........................................................... 1 Functional Scope of TMC4361A ........................................................................................ 2 Order Codes ..................................................................................................................... 2 TABLE OF CONTENTS ....................................................................................................... 3 MAIN MANUAL ............................................................................................................... 10 1. Pinning and Design-In Process Information ............................................................ 10 Pin Assignment: Top View .................................................................................................. 10 Pin Description .................................................................................................................. 11 System Overview ............................................................................................................... 13 2. Application Circuits .................................................................................................. 14 TMC4361A TMC4361A TMC4361A TMC4361A TMC4361A Standard Connection: VCC=3.3V ....................................................................... 14 with TMC26x Stepper Connection....................................................................... 14 with TMC248 Stepper Driver .............................................................................. 15 with TMC2130 Stepper Driver ............................................................................ 15 with TMC5130A or TMC5160 ............................................................................. 15 3. SPI Interfacing ........................................................................................................ 16 SPI Datagram Structure ..................................................................................................... 16 SPI Timing Description ....................................................................................................... 19 4. Input Filtering .......................................................................................................... 20 Input Filtering Examples..................................................................................................... 22 Configuration of Step/Dir Input Filter .................................................................................. 23 5. Status Flags and Events ........................................................................................... 24 Status Event Description .................................................................................................... 25 SPI Status Bit Transfer ....................................................................................................... 26 Generation of Interrupts..................................................................................................... 26 Connection of Multiple INTR Pins ........................................................................................ 27 6. Ramp Configurations for different Motion Profiles .................................................. 28 Step/Dir Output Configuration ............................................................................................ 29 Step/Dir Output Configuration Steps ................................................................................... 29 STPOUT: Changing Polarity ............................................................................................... 29 Altering the Internal Motion Direction.................................................................................. 30 Configuration Details for Operation Modes and Motion Profiles ............................................. 31 Starting Point: Choose Operation Mode ............................................................................... 32 Stop during Motion ............................................................................................................ 32 Motion Profile Configuration ............................................................................................... 33 No Ramp Motion Profile...................................................................................................... 34 Trapezoidal 4-Point Ramp without Break Point..................................................................... 35 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 4/230 Trapezoidal Ramp with Break Point .................................................................................... 35 Position Mode combined with Trapezoidal Ramps ................................................................ 36 Configuration of S-Shaped Ramps ....................................................................................... 37 S-Ramps: Changing Ramp Parameters during Motion or Switching to Positiong Mode ............ 38 Configuration of S-shaped Ramp with ASTART and DFINAL .................................................. 38 S-shaped Mode and Positioning: Fast Motion ....................................................................... 39 Start Velocity VSTART and Stop Velocity VSTOP .................................................................. 40 S-shaped Ramps with Start and Stop Velocity ...................................................................... 44 Combined Use of VSTART and ASTART for S-shaped Ramps ............................................... 45 sixPoint Ramps .................................................................................................................. 46 U-Turn Behavior ................................................................................................................ 47 Continuous Velocity Motion Profile for S-shaped Ramps ...................................................... 48 Internal Ramp Generator Units ........................................................................................... 49 Clock Frequency ................................................................................................................ 49 Velocity Value Units ........................................................................................................... 49 Acceleration Value Units ..................................................................................................... 49 Bow Value Units ................................................................................................................ 50 Overview of Minimum and Maximum Values: ....................................................................... 50 7. External Step Control and Electronic Gearing .......................................................... 51 Description of Electronic Gearing ........................................................................................ 52 Indirect External Control .................................................................................................... 52 Switching from External to Internal Control ......................................................................... 53 8. Reference Switches ................................................................................................. 54 Hardware Switch Support ................................................................................................... 55 Stop Slope Configuration for Hard or Linear Stop Slopes ...................................................... 55 How Active Stops are indicated and reset to Free Motion ..................................................... 56 How to latch Internal Position on Switch Events .................................................................. 56 Virtual Stop Switches ......................................................................................................... 57 Enabling Virtual Stop Switches ............................................................................................ 57 Virtual Stop Slope Configuration ......................................................................................... 57 How Active Virtual Stops are indicated and reset to Free Motion ........................................... 58 Home Reference Configuration ........................................................................................... 59 Home Event Selection ........................................................................................................ 59 HOME_REF Monitoring ....................................................................................................... 60 Homing with STOPL or STOPR ............................................................................................ 61 Target Reached / Position Comparison ................................................................................ 62 Connecting several Target-reached Pins .............................................................................. 62 Use of TARGET_REACHED Output ...................................................................................... 63 Position Comparison of Internal Values ............................................................................... 64 Repetitive and Circular Motion ............................................................................................ 65 Repetitive Motion to XTARGET ............................................................................................ 65 Activating Circular Motion ................................................................................................... 65 Uneven or Noninteger Microsteps per Revolution ................................................................. 66 Release of the Revolution Counter ...................................................................................... 67 Blocking Zones .................................................................................................................. 67 Activating Blocking Zones during Circular Motion ................................................................. 67 Circular Motion with and without Blocking Zone ................................................................... 68 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 5/230 9. Ramp Timing and Synchronization .......................................................................... 69 Basic Synchronization Settings ............................................................................................ 70 Start Signal Trigger Selection ............................................................................................. 70 User-specified Impact Configuration of Timing Procedure ..................................................... 70 Delay Definition between Trigger and internally generated Start Signal ................................. 71 Active START Pin Output Configuration ............................................................................... 71 Ramp Timing Examples ...................................................................................................... 72 Shadow Register Settings ................................................................................................... 75 Shadow Register Configuration Options ............................................................................... 76 Delayed Shadow Transfer................................................................................................... 80 Pipelining Internal Parameters ............................................................................................ 81 Configuration and Activation of Target Pipeline .................................................................... 81 Using the Pipeline for different internal Registers ................................................................. 82 Pipeline Mapping Overview ................................................................................................. 83 Cyclic Pipelining ................................................................................................................. 84 Pipeline Examples .............................................................................................................. 84 Masterless Synchronization of Several Motion Controllers via START Pin ................................ 86 10. Serial Data Output ................................................................................................... 87 Getting Started with TMC Motor Drivers .............................................................................. 88 Sine Wave Lookup Tables................................................................................................... 89 Actual Current Values Output ............................................................................................. 90 How to Program the Internal MSLUT ................................................................................... 90 Setup of MSLUT Segments ................................................................................................. 91 Current Waves Start Values ................................................................................................ 92 Default MSLUT .................................................................................................................. 92 Explanatory Notes for Base Wave Inclinations ..................................................................... 93 SPI Output Interface Configuration Parameters ................................................................... 95 How to enable SPI Output Communication .......................................................................... 95 Setup of SPI Output Timing Configuration ........................................................................... 96 Current Diagrams .............................................................................................................. 97 Change of Microstep Resolution .......................................................................................... 97 Cover Datagrams Communication between µC and Driver .................................................... 97 Sending Cover Datagrams .................................................................................................. 98 Configuring Automatic Generation of Cover Datagrams ........................................................ 99 Overview: TMC Motor Driver Connections ...........................................................................100 TMC Stepper Motor Driver Settings ....................................................................................100 TMC Motor Driver Response Datagram and Status Bits ........................................................101 Events and Interrupts based on Motor Driver Status Bits .....................................................101 Stall Detection and Stop-on-Stall........................................................................................102 TMC23x, TMC24x Stepper Motor Driver ..............................................................................103 TMC23x Setup ..................................................................................................................103 TMC24x Setup ..................................................................................................................103 TMC23x/24x Status Bits ....................................................................................................104 Automatic Fullstep Switchover for TMC23x/24x...................................................................104 Mixed Decay Configuration for TMC23x/24x .......................................................................105 ChopSync Configuration for TMC23x/24x Stepper Drivers ....................................................105 Doubling ChopSync Frequency during Standstill ..................................................................105 Using TMC24x stallGuard Characteristics ............................................................................106 TMC26x Stepper Motor Driver ............................................................................................107 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 6/230 TMC26x Setup (SPI mode) ...............................................................................................107 TMC26x Setup (S/D mode) ................................................................................................107 Sending Cover Datagrams to TMC26x ................................................................................108 Automatic Continuous Streaming of Cover Datagrams for TMC26x .......................................108 TMC26x SPI Mode: Automatic Fullstep Switchover .............................................................109 TMC26x S/D Mode: Automatic Fullstep Switchover ..............................................................109 TMC 26x S/D Mode: Change of Current Scaling Parameter ..................................................110 TMC26x Status Bits ...........................................................................................................110 TMC26x Status Response ..................................................................................................110 TMC389 Stepper Motor Driver ...........................................................................................111 TMC2130 Stepper Motor Driver ..........................................................................................112 Set-up TMC2130 Support (SPI Mode) .................................................................................112 Set-up TMC2130 Support (S/D Mode) ................................................................................112 Sending Cover Datagrams to TMC2130 ..............................................................................113 Automatic Continuous Streaming of Cover Datagrams for TMC2130 .....................................113 TMC2130 SPI Mode: Automatic Fullstep Switchover ............................................................114 TMC2130 S/D Mode: Automatic Fullstep Switchover ............................................................114 TMC 2130 S/D Mode: Changing current Scaling Parameter ..................................................114 TMC2130 Status Response ................................................................................................115 Connecting Non-TMC Stepper Motor Driver or SPI-DAC at SPI output interface ....................116 Connecting a SPI-DAC .......................................................................................................117 DAC Data Transfer ............................................................................................................117 Changing SPI Output Protocol for SPI-DAC .........................................................................117 DAC Address Values ..........................................................................................................118 DAC Data Values ..............................................................................................................118 11. Current Scaling ...................................................................................................... 120 Hold Current Scaling .........................................................................................................121 Freewheeling ....................................................................................................................121 Current Scaling during Motion ...........................................................................................122 Drive Scaling ....................................................................................................................122 Alternative Drive Scaling ...................................................................................................122 Boost Current ...................................................................................................................123 Scale Mode Transition Process Control ...............................................................................124 Current Scaling Examples ..................................................................................................126 12. NFREEZE and Emergency Stop ............................................................................... 128 Configuration of FREEZE Function ......................................................................................128 Configuration of DFREEZE for automatic Ramp Stop ...........................................................129 13. Controlled PWM Output ......................................................................................... 130 PWM Output Generation and Scaling Possibilities ................................................................131 PWM Scale Example ..........................................................................................................132 PWM Output Generation for TMC23x/24x ...........................................................................133 Switching between SPI and Voltage PWM Modes ................................................................134 14. dcStep Support for TMC26x or TMC2130 ............................................................... 135 Enabling dcStep for TMC26x Stepper Motor Drivers ............................................................137 Setup: Minimum dcStep Velocity ........................................................................................138 Enabling dcStep for TMC2130 Stepper Motor Drivers ..........................................................140 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 7/230 15. Decoder Unit: Connecting ABN, SSI, or SPI Encoders correctly ............................. 141 Selecting the correct Encoder ............................................................................................142 Disabling digital differential Encoder Signals .......................................................................143 Inverting of Encoder Direction ...........................................................................................143 Encoder Misalignment Compensation .................................................................................144 Incremental ABN Encoder Settings .....................................................................................145 Automatic Constant Configuration of Incremental ABN Encoder ...........................................145 Manual Constant Configuration of Incremental ABN Encoder ...............................................145 Incremental Encoders: Index Signal: N resp. Z ...................................................................146 Setup of Active Polarity for Index Channel .........................................................................146 Configuration of N Event ...................................................................................................146 External Position Counter ENC_POS Clearing ......................................................................147 Latching External Position .................................................................................................148 Latching Internal Position ..................................................................................................148 Absolute Encoder Settings .................................................................................................149 Singleturn or Multiturn Data ..............................................................................................149 Automatic Constant Configuration of Absolute Encoder .......................................................150 Manual Constant Configuration of incremental ABN Encoder ................................................150 Absolute Encoder Data Setup ............................................................................................151 Emitting Encoder Data Variation ........................................................................................152 SSI Clock Generation ........................................................................................................153 Enabling Multicycle SSI request ........................................................................................154 Gray-encoded SSI Data Streams .......................................................................................154 SPI Encoder Data Evaluation .............................................................................................155 SPI Encoder Mode Selection ..............................................................................................156 SPI Encoder Configuration via TMC4361A ...........................................................................157 16. Possible Regulation Options with Encoder Feedback ............................................ 158 Feedback Monitoring .........................................................................................................158 Target-Reached during Regulation .....................................................................................158 PID-based Control of XACTUAL ..........................................................................................159 PID Readout Parameters ...................................................................................................159 PID Control Parameters and Clipping Values .......................................................................160 Enabling PID Regulation ....................................................................................................160 Closed-Loop Operation ......................................................................................................161 Basic Closed-Loop Parameters ...........................................................................................161 Enabling and calibrating Closed-Loop Operation .................................................................162 Limiting Closed-Loop Catch-Up Velocity ..............................................................................163 Enabling the Limitation of the Catch-Up Velocity .................................................................163 Enabling Closed-Loop Velocity Mode ..................................................................................164 Closed-loop Scaling ...........................................................................................................165 Closed-Loop Scaling Transition Process Control ..................................................................166 Back-EMF Compensation during Closed-loop Operation .......................................................167 Encoder Velocity Readout Parameters ................................................................................168 Encoder Velocity Filter Configuration ..................................................................................168 Encoder Velocity equals 0 Event ........................................................................................168 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 8/230 17. Reset and Clock Gating .......................................................................................... 169 Manual Hardware Reset ....................................................................................................169 Manual Software Reset .....................................................................................................169 Reset Indication ...............................................................................................................169 Activating Clock Gating manually .......................................................................................170 Clock Gating Wake-up .......................................................................................................170 Automatic Clock Gating Procedure .....................................................................................171 18. Serial Encoder Output ............................................................................................ 172 Configuration and Enabling of SSI Output Interface ............................................................173 Disabling differential Encoder Output Signals ......................................................................174 Gray-encoded SSI Output Data .........................................................................................174 TECHNICAL SPECIFICATIONS ...................................................................................... 175 19. Complete Register and Switches List ..................................................................... 175 General Configuration Register GENERAL_CONF 0x00 .........................................................175 Reference Switch Configuration Register REFERENCE_CONF 0x01 .......................................178 Start Switch Configuration Register START_CONF 0x02 .......................................................181 Input Filter Configuration Register INPUT_FILT_CONF 0x03 ................................................183 SPI Output Configuration Register SPI_OUT_CONF 0x04 .....................................................184 Current Scaling Configuration Register CURRENT_CONF 0x05 .............................................187 Current Scale Values Register SCALE_VALUES 0x06 ............................................................188 Various Scaling Configuration Registers ..............................................................................189 Encoder Signal Configuration (0x07) ..................................................................................190 Serial Encoder Data Input Configuration (0x08) ..................................................................194 Serial Encoder Data Output Configuration (0x09) ................................................................194 Motor Driver Settings Register STEP_CONF 0x0A ................................................................195 Event Selection Registers 0x0B..0X0D ................................................................................196 Status Event Register (0x0E) .............................................................................................197 Status Flag Register (0x0F) ...............................................................................................198 Various Configuration Registers: S/D, Synchronization, etc. .................................................199 PWM Configuration Registers .............................................................................................200 Ramp Generator Registers.................................................................................................201 External Clock Frequency Register .....................................................................................205 Target and Compare Registers ..........................................................................................205 Pipeline Registers .............................................................................................................206 Shadow Register ...............................................................................................................206 Freeze Register.................................................................................................................207 Reset and Clock Gating Register ........................................................................................207 Encoder Registers .............................................................................................................208 PID & Closed-Loop Registers .............................................................................................210 dcStep Registers ...............................................................................................................212 Transfer Registers ............................................................................................................213 SinLUT Registers ..............................................................................................................214 SPI-DAC Configuration Registers ........................................................................................215 TMC Version Register ........................................................................................................215 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 9/230 20. Absolute Maximum Ratings ................................................................................... 216 21. Electrical Characteristics........................................................................................ 217 Power Dissipation .............................................................................................................217 General IO Timing Parameters ...........................................................................................218 Layout Examples ..............................................................................................................219 Internal Cirucit Diagram for Layout Example.......................................................................219 Components Assembly for Application with Encoder ............................................................220 Top Layer: Assembly Side .................................................................................................220 Inner Layer (GND) ............................................................................................................221 Inner Layer (Supply VS) ....................................................................................................221 Package Dimensions .........................................................................................................222 Package Material Information ............................................................................................223 Marking Details provided on Single Chip .............................................................................223 APPENDICES ................................................................................................................ 224 22. Supplemental Directives ........................................................................................ 224 ESD-DEVICE INSTRUCTIONS ...........................................................................................................224 23. Tables Index .......................................................................................................... 226 24. Figures Index ......................................................................................................... 228 25. Revision History ..................................................................................................... 230 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 10/230 M AI N MA NU AL 1. Pinning and Design-In Process Information In this chapter you are provided with a list of all pin names and a functional description of each. A_SCLK NRST CLK_EXT VCC GND VDD1V8 TEST_MODE INTR STDBY_CLK TARGET_REACHED Pin Assignment: Top View 40 39 38 37 36 35 34 33 32 31 ANEG_NSCLK 1 30 NSCSDRV_SDO NSCSIN 2 29 SCKDRV_NSDO SCKIN 3 28 SDIDRV_NSCLK SDIIN 4 27 SDODRV_SCLK VCC 5 26 VCC GND 6 25 GND SDOIN 7 24 STPOUT_PWMA MP1 8 23 DIROUT_PWMB MP2 9 22 NNEG B_SDI 10 21 N 16 17 18 19 20 DIRIN NFREEZE START HOME_REF 15 STPIN STOPL 14 VDD1V8 13 GND 12 STOPR 11 BNEG_NSDI TMC4361 QFN 40 6mm x 6mm 0.5 pitch Figure 6: Package Outline: Pin Assignments Top View © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 11/230 Pin Description Pin Names and Descriptions Pin Number Type Function Supply Pins GND 6, 15, 25, 36 GND Digital ground pin for IOs and digital circuitry. VCC 5, 26, 37 VCC Digital power supply for IOs and digital circuitry (3.3V… 5V). VDD1V8 16, 35 VDD Connection of internal generated core voltage of 1.8V. CLK_EXT 38 I NRST 39 I (PU) TEST_MODE 34 I NFREEZE 19 I (PU) Clock input to provide a clock with the frequency fCLK for all internal operations. Low active reset. If not connected, Power-on-Reset and internal pull-up resistor is active. Test mode input. Tie to low for normal operation. Low active safety pin to immediately freeze output operations. If not connected, internal pull-up resistor is active. Interface Pins for µC NSCSIN 2 I Low active chip selects input of SPI interface to µC. SCKIN 3 I Serial clock for SPI interface to µC. SDIIN 4 I Serial data input of SPI interface to µC. SDOIN 7 O Serial data output of SPI interface to µC (Z if NSCSIN=1). INTR 33 O Interrupt output, programmable PD/PU for wired-and/or. TARGET_REACHED 31 O Target reached output, programmable PD/PU for wired-and/or. Reference Pins STOPL 12 I (PD) Left stop switch. External signal to stop a ramp. If not connected, internal pull-down resistor is active. HOME_REF 13 I (PD) Home reference signal input. External signal for reference search. If not connected, internal pull-down resistor is active. STOPR 14 I (PD) Right stop switch. External signal to stop a ramp. If not connected, internal pull-down resistor is active. STPIN 17 I (PD) Step input for external step control. If not connected, internal pull-down resistor is active. DIRIN 18 I (PD) Direction input for external step control. If not connected, internal pull-down resistor is active. START 20 IO Start signal input/output. Default: Output S/D Output Pins STPOUT PWMA DACA 24 O Step output. First PWM signal (Sine). First DAC output signal (Sine). DIROUT PWMB DACB 23 O Direction output. Second PWM signal (Cosine). Second DAC output signal (Cosine).  Continued on next page! © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 12/230 Pin Names and Descriptions Pin Number Type Function Interface Pins for Stepper Motor Drivers NSCSDRV PWMB SDO 30 O Low active chip selects output of SPI interface to motor driver. Second PWM signal (Cosine) to connect with PHB (TMC23x/24x). Serial data output of serial encoder output interface. SCKDRV MDBN NSDO 29 O Serial clock output of SPI interface to motor driver. MDBN output signal for MDBN pin of TMC23x/24x. Negated serial data output of serial encoder output interface. SDODRV PWMA SCLK 27 IO Serial data output of SPI interface to motor driver (default). First PWM signal (Sine) to connect with PHA (TMC23x/24x). Clock input of serial encoder output interface. SDIDRV ERR NSCLK 28 I (PD) Serial data input of SPI interface to motor driver. Error input signal to ERR pin of TMC23x/24x. Negated clock input of serial encoder output interface. If not connected, internal pull-down resistor is active. MP1 8 I (PD) DC_IN as external dcStep input control signal. If not connected, internal pull-down resistor is active. MP2 9 IO DCSTEP_ENABLE as dcStep output control signal (default). SPE_OUT as output signal, connect to SPE pin of TMC23x/24x. STDBY_CLK 32 O StandBy signal or internal CLK output or ChopSync output. Encoder Interface Pins N 21 I (PD) N signal input of incremental encoder input interface. If not connected, internal pull-down resistor will be active. NNEG 22 I (PD) Negated N signal input of incremental encoder input interface. If not connected, internal pull-down resistor will be active. B SDI 10 I (PD) B signal input of incremental encoder input interface. Serial data input signal of serial encoder interface (SSI/SPI). If not connected, internal pull-down resistor is active. BNEG NSDI SDO_ENC 11 IO Negated B signal input of incremental encoder interface (default). Negated serial data input signal of SSI encoder input interface. Serial data output of SPI encoder input interface. A SCLK 40 IO A signal input of incremental encoder interface (default). Serial clock output signal of serial encoder interface (SSI/SPI). ANEG NSCLK NSCS_ENC 1 IO Negated A signal input of incremental encoder interface (default). Negated serial clock output signal of serial encoder interface. Low active chip select output of SPI encoder input interface. Table 2: Pin Names and Descriptions © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 13/230 System Overview GND(4x) VDD1V8(2x) VDD5(3x) CLK_EXT NRST I Host CPU SPI Interface I POR NSCSIN I SCKIN I SDIIN I SDOIN O R E S E T Register Block SPI Status Flags / Events for Interrupt Control Motion Profile ShadowReg Target Register(s) O TARGET_REACHED O INTR ClkGating Step/Dir Input CLK_INT Start / Stop / Reference Switches START NFREEZE Parameters from/for all Units Timer Unit IO I STOPL I HOME_REF I STOPR I GearRatio immediate freeze of operation DDS retain Reference processing Ramp-Generator Internal Step Ramp Status Encoder (differential) SPI or SCLK NSCS SSI or SCLK NSCLK SDI SDO NSDI ABN A IO ANEG IO SDI B BNEG SSI External PosCounter External Pos Compare Commutation angle ClosedLoop Unit SPI Decoder Unit Closed Loop Scaling I IO N I NNEG I CoverReg ABN MasterCLK SSI SPI Datagram Generator or Serial Encoder O DC_OUT O DIROUT O NSTDBY_OUT or Clk_Out or ChopSync Clk FS Actual Co-/Sine values Internal (Co)Sine LUT StdBy signal chopSync™ PWM Unit PWM or DAC encrypted co-/sine voltage values DAC Unit IO dcStep Signals DCSTEP_STALL Pos Counter DataOut SSI I SPI Output Internal Pos Scaled current values Drv type Serial Encoder Unit Scale Unit DIR_IN I Step/Dir Output or PWM Output or DAC Output O STPOUT PWMA DACA (Sine) (Sine) PID PID_E STP_IN I O PulseGen v S-Ramps with 4 Bows Trapezoid Ramps Rectangle Ramps Circles dcStep™ ChopperClk/ STEP_READY I Scan Test I TEST_MODE O SDIDRV SCKDRV NSCSDRV SDODRV or or or or SCLK NSCLK SDO NSDO Figure 7: System Overview © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  PWMB (Cosine) DACB (Cosine) TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 2. 14/230 Application Circuits In this chapter application circuit examples are provided that show how external components can be connected. TMC4361A Standard Connection: VCC=3.3V Reference Switches SD Input HOME STOPL STOPR STPIN DIRIN NSCSIN SPI Control Interface to Microcontroller NSCSDRV_SDO SDIIN SDODRV_SCLK SCKIN SCKDRV_NSDO SPI Output Interface to Motor Driver SDIDRV_NSCLK SDOIN Step/Dir Interface to Motor Driver STPOUT_PWMA Ext. Clock DIRPOUT_PWMB CLK_EXT STDBY_CLK A_SCLK ANEG_NSCLK B_SDI BNEG_NSDI N NNEG TMC4361 Start Signal Input or Output START Interrupt Output INTR Target Reached Output TARGET_REACHED Optional Inv. Reset Input Encoder Input Interface for incremental ABN or serial SSI/SPI MP1 NRST Emergency Stop Switch Standby Clock Output Multi-Purpose Pins MP2 NFREEZE VCC GND TEST_MODE VDD1V8 VDD1V8 100 nF 100 nF 100 nF +3.3 V Figure 8: TMC4361A Connection: VCC=3.3V TMC4361A with TMC26x Stepper Connection SS µC CLK NSCSIN MOSI SDIIN SCK SCKIN MISO SDOIN STPOUT_PWMA STEP DIRPOUT_PWMB DIR MP1 TMC4361 CLK_EXT TMC26x SG_TST NSCSDRV_SDO CSN SDODRV_SCLK SDI SCKDRV_NSDO SCK SDO SDIDRV_NSCLK M Figure 9: TMC4361A with TMC26x Stepper Driver in SPI Mode or S/D Mode © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 15/230 NSCSDRV_SDO TMC4361A with TMC248 Stepper Driver SS µC NSCSIN SCKDRV_NSDO MOSI SDIIN SDODRV_SCLK SDI SCK SCKIN SDIDRV_NSCLK SDO MISO SDOIN TMC4361 TMC248 OSC STDBY_CLK CLK CSN SCK CLK_EXT Output for chopSync 15K 680pF M Figure 10: TMC4361A with TMC248 Stepper Driver in SPI Mode TMC4361A with TMC2130 Stepper Driver SS µC CLK NSCSIN MOSI SDIIN SCK SCKIN MISO SDOIN STPOUT_PWMA STEP DIRPOUT_PWMB DIR MP1 MP2 TMC4361 CLK_EXT TMC2130 DCO DCEN_CFG4 NSCSDRV_SDO CSN_CFG3 SDODRV_SCLK SDI_CFG1 SCKDRV_NSDO SCK_CFG2 SDO_CFG0 SDIDRV_NSCLK M Figure 11: TMC4361A with TMC2130 Stepper Driver in SPI Mode or S/D Mode TMC4361A with TMC5130A or TMC5160 TMC5130A and TMC5160 combine motion controller and bi-polar stepper driver in a single device. For some applications, it can be advisable to use TMC4361A in combination with TMC5130A or TMC5160. In case one of these combinations is required, all information and configuration procedures that are stated for TMC2130 hold also true for TMC5130A resp. TMC5160, because all three devices are software compatible from TMC4361A point of view. i For more information, please also refer to the manual of TMC5130A resp. TMC5160. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 3. 16/230 SPI Interfacing TMC4361A uses 40-bit SPI datagrams for communication with a microcontroller. The bit-serial interface is synchronous to a bus clock. For every bit sent from the bus master to the bus slave, another bit is sent simultaneously from the slave to the master. In the following chapter information is provided about the SPI control interface, SPI datagram structure and SPI transaction process. SPI Input Control Interface Pins Pin Name Type Remarks NSCSIN Input Chip Select of SPI-µC interface (low active) SCKIN Input Serial clock of SPI-µC interface SDIIN Input Serial data input of SPI-µC interface SDOIN Output Serial data output of SPI-µC interface Table 3: SPI Input Control Interface Pins  SPI Datagram Structure   i Microcontrollers that are equipped with hardware SPI are typically able to communicate using integer multiples of 8 bit. The NSCSIN line of the TMC4361A has to stay active (low) for the complete duration of the datagram transmission. Each datagram that is sent to TMC4361A is composed of an address byte followed by four data bytes. This allows direct 32-bit data word communication with the register set of TMC4361A. Each register is accessed via 32 data bits; even if it uses less than 32 data bits. Each register is specified by a one-byte address: For read access the most significant bit of the address byte is 0. For write access the most significant bit of the address byte is 1. NOTE:  Some registers are write only registers. Most registers can be read also; and there are also some read only registers. TMC4361A SPI Datagram Structure MSB (transmitted first) 40 bits 39 ...  8-bit address  8-bit SPI status 39 ... 32  to TMC4361: RW + 7-bit address  from TMC4361: 8-bit SPI status 39 / 38 ... 32 W LSB (transmitted last) 38...32 0   32-bit data 31 ... 0 8-bit data 31 ... 24 31...28 27...24 8-bit data 8-bit data 23 ... 16 23...20 19...16 15 ... 8 15...12 11...8 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Figure 12: TMC4361A SPI Datagram Structure © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  8-bit data 7 ... 0 7...4 8 7 6 5 3...0 4 3 2 1 0 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Read/Write Selection Principles and Process 17/230 Read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI datagram). This bit is 0 for read access and 1 for write access. Consequently, the bit named W is a WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. Consequently, 0x80 must be added to the address for a write access. The SPI interface always delivers data back to the master, independent of the Write bit W. Difference between Read and Write Access If … Then … The previous access was a read access. The data transferred back is the data read from the address which was transmitted with the previous datagram. The previous access was a write access The data read back mirrors the previously received write data. Figure 13: Difference between Read and Write Access Conclusion: Consequently, the difference between a read and a write access is that the read access does not transfer data to the addressed register but it transfers the address only; and its 32 data bits are dummies. NOTE:  Please note that the following read delivers back data read from the address AREAS OF SPECIAL CONCERN ! Use of Dummy Write Data Read and Write Access Examples transmitted in the preceding read cycle. The data is latched immediately after the read request. A read access request datagram uses dummy write data. Read data is transferred back to the master with the subsequent read or write access. i Reading multiple registers can be done in a pipelined fashion. Data that is delivered is latched immediately after the initiated data transfer. For read access to register XACTUAL with the address 0x21, the address byte must be set to 0x21 in the access preceding the read access. For write access to register VACTUAL, the address byte must be set to 0x80 + 0x22 = 0xA2. For read access, the data bit can have any value, e.g., 0. Read and Write Access Examples Action Data sent to TMC Data received from TMC read XACTUAL  0x2100000000  0xSS1) & unused data read XACTUAL  0x2100000000  0xSS & XACTUAL  0xA200ABCDEF  0xSS & XACTUAL  0xA200123456  0xSS00ABCDEF write VACTUAL:= 0x00ABCDEF write VACTUAL:= 0x00123456 Table 4: Read and Write Access Examples 1) SS is a placeholder for the status bits SPI_STATUS. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 18/230 Data Alignment All data is right-aligned. Some registers represent unsigned (positive) values; others represent integer values (signed) as two’s complement numbers. Some registers consist of switches that are represented as bits or bit vectors. SPI Transaction Process The SPI transaction process is as follows:    i AREAS OF SPECIAL CONCERN ! System Behavior Specifics The slave is enabled for SPI transaction by a transition to low level on the chip select input NSCSIN. Bit transfer is synchronous to the bus clock SCKIN, with the slave latching the data from SDIIN on the rising edge of SCKIN and driving data to SDOIN following the falling edge. The most significant bit is sent first. A minimum of 40 SCKIN clock cycles is required for a bus transaction with TMC4361A. Take the following aspects into consideration:     Whenever data is read from or written to the TMC4361A, the first eight bits that are delivered back contain the SPI status SPI_STATUS that consists of eight user-selected event bits. The selection of these bits are explained in chapter 5.2. (Page 26). If less than 40 clock cycles are transmitted, the transfer is not valid; even for read access. However, sending only eight clock cycles can be useful to obtain the SPI status because it sends the status information back first. If more than 40 clocks cycles are transmitted, the additional bits shifted into SDIIN are shifted out on SDOIN after a 40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips. NSCSIN must be low during the whole bus transaction. When NSCSIN goes high, the contents of the internal shift register are latched into the internal control register and recognized as a command from the master to the slave. If more than 40 bits are sent, only the last 40 bits received - before the rising edge of NSCSIN - are recognized as the command. NSCSIN tCC tCL tCH tCH tCC SCKIN tDU SDIIN bit39 tDH bit38 bit0 tDO SDOIN tZC bit39 bit38 bit0 Figure 14: SPI Timing Datagram © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 19/230 SPI Timing Description The SPI interface is synchronized to the internal system clock, which limits SPI bus clock SCKIN to a quarter of the system clock frequency. The signal processing of SPI inputs is supported with internal Schmitt Trigger, but not with RC elements. NOTE:  In order to avoid glitches at the inputs of the SPI interface between µC and TMC4361A, external RC elements have to be provided. Figure 14 shows the timing parameters of an SPI bus transaction, and the table below specifies the parameter values. SPI Interface Timing SPI Interface Timing AC Characteristics: External clock period: tCLK Parameter Symbol Min SCKIN valid before or after change of NSCSIN tCC NSCSIN high time tCSH SCKIN low time tCL SCKIN high time tCH SCKIN frequency using external clock (Example: fCLK = 16 MHz) SDIIN setup time before rising edge of SCKIN SDIIN hold time after rising edge of SCKIN Data out valid time after falling SCKIN clock edge fSCK Conditions Type 10 Min. time is for synchronous CLK with SCKIN high one tCH before SCSIN high only. Min. time is for synchronous CLK only. Min. time is for synchronous CLK only. Unit ns tCLK >2·tCLK+10 ns tCLK >tCLK+10 ns tCLK >tCLK+10 ns Assumes synchronous CLK. fCLK / 4 (4) MHz tDU 10 ns tDH 10 ns tDO No capacitive load on SDOIN. Table 5: SPI Interface Timing i Max tCLK = 1 / fCLK © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  tFILT+5 ns TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 4. 20/230 Input Filtering Input signals can be noisy due to long cables and circuit paths. To prevent jamming, every input pin provides a Schmitt trigger. Additionally, several signals are passed through a digital filter. Particular input pins are separated into four filtering groups. Each group can be programmed individually according to its filter characteristics. In this chapter informed on the digital filtering feature of TMC4361A is provided; and how to separately set up the digital filter for input pins. Input Filtering Groups Pin Names A_SCLK B_SDI N ANEG_NSCLK BNEG_NSDI NNEG STOPL HOME_REF STOPR START SDODRV_SCLK SDIDRV_NSCLK STPIN DIRIN Type Remarks Inputs Encoder interface input pins. Inputs Reference input pins. Input START input pin. Inputs Master clock input interface pins for serial encoder. Inputs Step/Dir interface inputs. Table 6: Input Filtering Groups (Assigned Pins) Register Names Register Names Register Address INPUT_FILT_CONF 0x03 RW Remarks Filter configuration for all four input groups. Table 7: Input Filtering (Assigned Register) Input Filter Assignment Every filtering group can be configured separately with regard to input sample rate and digital filter length. The following groups exist:      Encoder interface input pins. Reference input pins. Start input pin. Master clock input pins of encoder output interface. Step/Dir input pins. NOTE:  Differentiated handling for Step/Dir input pins is necessary, as explained on the following pages. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Input Sample Rate (SR) 21/230 Input sample rate = fCLK 1/2SR where: SR i (extended with a particular name extension) is in [0… 7]. This means that the next input value is considered after 2SR clock cycles. Sample Rate Configuration Sample Rate Configuration SR Value Sample Rate 0 fCLK 1 fCLK/2 2 fCLK/4 3 fCLK/8 4 fCLK/16 5 fCLK/32 6 fCLK/64 7 fCLK/128 Table 8: Sample Rate Configuration Digital Filter Length (FILT_L) Digital Filter Length Configuration Table i i The filter length FILT_L can be set within the range [0… 7]. The filter length FILT_L specifies the number of sampled bits that must have the same voltage level to set a new input bit voltage level. Configuration of Digital Filter Length FILT_L value Filter Length 0 No filtering. 1 2 equal bits. 2 3 equal bits. 3 4 equal bits. 4 5 equal bits. 5 6 equal bits. 6 7 equal bits. 7 8 equal bits. Table 9: Configuration of Digital Filter Length © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 22/230 Input Filtering Examples The following three examples depict input pin filtering of three different input filtering groups. i After passing Schmitt trigger, voltage levels are compared to internal signals, which are processed by the motion controller. i The sample points are depicted as green dashed lines. Example 1: Reference Input Pins In this example every second clock cycle is sampled. Two sampled input bits must be equal to receive a valid input voltage. CLK HOME internal home signal STOPL internal left stop signal Figure 15: Reference Input Pins: SR_REF = 1, FILT_L_REF = 1 Example 2: START Input Pin This example shows the START input pattern at every fourth clock cycle: CLK START internal Start input signal START internal Start input signal Figure 16: START Input Pin: SR_S = 2, FILT_L_S = 0 Example 3: Encoder Interface Input Pins This example shows every clock cycle bit. Eight sampled input bits must be equal to receive a valid input voltage. CLK B_SDI internal B input signal N internal N input signal Figure 17: Encoder Interface Input Pins: SR_ENC_IN = 0, FILT_L_ENC_IN = 7 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 23/230 Configuration of Step/Dir Input Filter Step/Dir input filtering setup differs slightly from the other groups, because the other four groups already complete the whole INPUT_FILT_CONF register 0x03. This is why it is possible to assign the Step/Dir input group to one of the existing groups by setting the appropriate bit in front of the setup parameters. i If no group is selected, Step/Dir input filtering is automatically assigned to the encoder input interface filter group. Step/Dir Pin Filter Assignment The following example shows the filter settings for Step/Dir interface input pins, which are taken from the reference input pin group. Step/Dir input pin filter settings are derived from the Reference input filter group: SR_SDIN = 6, FILT_L_SDIN = 3 NOTE:  Other input filter groups are: SR_ENC_IN = 5, FILT_L_ENC_IN = 6 SR_REF = 6, FILT_L_REF = 3 SR_S = 2, FILT_L_S = 4 SR_ENC_OUT = 0, FILT_L_ENC_OUT = 0 Step/Dir Input Filter Parameter Bits of register 0x03: Input filter group: Filter parameter: Example: 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 Serial clock inputs FILT_L_EN C_OUT 0 0 0 0 0 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 START input SR_ENC_O UT 0 2 1 0 FILT_L_S 0 1 0 0 0 1 1 2 1 1 1 0 9 8 6 0 1 0 1 1 0 1 1 0 Figure 18: Step/Dir Input Filter Parameter © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224. 5 4 3 2 1 0 Encoder inputs SR_ENC_R EF FILT_L_REF = possible selection bits to assign Step/Dir input filter parameter  MAIN MANUAL  7 Reference inputs SR_S 0 1 3 FILT_L_ENC_I N 0 1 1 0 SR_ENC_IN 0 1 0 1 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 5. 24/230 Status Flags and Events TMC4361A provides 32 status flags and 32 status events to obtain short information on the internal status or motor driver status. These flags and events can be read out from dedicated registers. In the following chapter, you are informed about the generation of interrupts based on status events. Status events can also be assigned to the first eight SPI status bits, which are sent within each SPI datagram. Pin Names: Status Events Pin Names Type Remarks INTR Output Interrupt output to indicate status events. Table 10: Pins Names: Status Events Register Names: Status Flags and Events Register Name Register Address Remarks GENERAL_CONF 0X00 RW Bits: 15, 29, 30. STATUS_FLAGS 0X0F R 32 status flags of TMC4361A and the connected TMC motor driver chip. EVENTS 0X0E R+C W 32 events triggered by altered TMC4361A status bits. SPI_STATUS_SELECTION 0X0B RW Selection of 8 out of 32 events for SPI status bits. EVENT_CLEAR_CONF 0X0C RW Exceptions for cleared event bits. INTR_CONF 0X0D RW Selection of 32 events for INTR output. Table 11:Register Names: Status Flags and Events © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 25/230 Status Event Description Status events are based on status bits. If the status bits change, related events are triggered from inactive to active level. Resetting events back to inactive must be carried out manually. Association of Status Bits Status bits and status events are associated in different ways:    Status flags reflect the as-is-condition, whereas status events indicate that the dedicated information has changed since the last read request of the EVENTS register. Several status events are associated with one status bit. Some status events show the status transition of one or more status bits out of a status bit group. The motor driver flags, e.g., trigger only one motor driver event MOTOR_EV in case one of the selected motor driver status flags becomes active. In case a flag consists of more than one bit, the number of associated events that can be triggered corresponds to the valid combinations. The VEL_STATE flag, e.g., has two bit but three associated velocity state events (b’00/b’01/b’10). Such an event is triggered if the associated combination switches from inactive to active. NOTE:  Some events have no equivalence in the STATUS_FLAGS register 0x0F (e.g., COVER_DONE which indicates new data from the motor driver chip). The EVENTS register 0x0E is automatically cleared after reading the register; subsequent to an SPI datagram request. Events are important for interrupt generation and SPI status monitoring. Automatic Clearance of EVENTS NOTE:  It is recommended to clear EVENTS register 0x0E by read request before regular operation. AREAS OF SPECIAL CONCERN How to Avoid Lack of Information ! Recognition of a status event can fail; in case it is triggered right before or during EVENTS register 0x0E becomes cleared. In order to prevent events from being cleared, assign EVENT_CLEAR_CONF register 0x0C according to the particular event in the EVENTS register: Action:  Set related EVENT_CLEAR_CONF register bit position to 1. Result: The related event is not cleared when EVENTS register is read out. In order to clear these events, do the following, if necessary: Action:  Set related EVENTS register 0x0E bit position to 1. Result: The related event is cleared by writing to the EVENTS register. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 26/230 SPI Status Bit Transfer Up to eight events can be selected for permanent SPI status report. Consequently, these events are always transferred at the most significant transfer bits within each TMC4361A SPI response. Assign an Event to a Status Bit In order to select an event for the SPI status bits, assign the SPI_STATUS_SELECTION register 0x0B according to the particular event in the EVENTS register: Action:  Set the related SPI_STATUS_SELECTION register bit position to 1. Result: The related event is transferred with every SPI datagram response as SPI_STATUS. NOTE:  The bit positions are sorted according to the event bit positions in the EVENTS register 0x0E. In case more than eight events are selected, the first eight bits (starting from index 0 = LSB) are forwarded as SPI_STATUS. Generation of Interrupts Similar to EVENT_CLEAR_CONF register and SPI_STATUS_SELECTION register, events can be selected for forwarding via INTR output. The selected events are ORed to one signal which means that INTR output switches active as soon as one of the selected events triggers. Generate Interrupts In order to select an event for the INTR output pin, assign the INTR_CONF register 0x0D according to the particular event in the EVENTS register: Action:  Set the related INTR_CONF register bit position to 1. Result: The related event is forwarded at the INTR output. If more than one event is requested, INTR becomes active as soon as one of the selected events is active. INTR Output Polarity Per default, the INTR output is low active. In order to change the INTR polarity to high active, do the following: Action:  Set intr_pol =1 (GENERAL_CONF register 0x00). Result: INTR is high active. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 27/230 Connection of Multiple INTR Pins INTR pin can be configured for a shared interrupt signal line of several TMC4361A interrupt signals to the microcontroller. Connecting several Interrupt Pins In order to make use of a Wired-Or or Wired-And behavior, the below described actions must be taken: Action:  Step 1: Set intr_tr_pu_pd_en = 1 (GENERAL_CONF register 0x00). OPTION 1: WIRED-OR Action:  Step 2: Set intr_as_wired_and = 0 (GENERAL_CONF register 0x00). Result: The INTR pin works efficiently as Wired-Or (default configuration). i In case INTR pin is inactive, the pin drive has a weak inactive polarity output. If one of the connected pins is activated, the whole line is set to active polarity. OPTION 2: WIRED-AND Action:  Step 2: Set intr_as_wired_and = 1 of the GENERAL_CONF register 0x00. Result: In case no interrupt is active, the INTR pin has a strong inactive polarity output. During the active state, the pin drive has a weak active polarity output. Consequently, the whole signal line is activated in case all pins are forwarding the active polarity. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 6. 28/230 Ramp Configurations for different Motion Profiles Step generation is one of the main tasks of a stepper motor motion controller. The internal ramp generator of TMC4361A provides several step generation configurations with different motion profiles. They can be configured in combination with the velocity or positioning mode. Pin Names: Ramp Generator Pin Names Type Remarks STPOUT_PWMA Output Step output signal. DIROUT_PWMB Output Direction output signal. Table 12: Pin Names: Ramp Generator Register Names: Ramp Generator Register Name GENERAL_CONF Register Address Remarks 0x00 RW 0x10 RW Additional time in clock cycles when no steps will occur after a direction change; 16 bits. RAMPMODE 0x20 RW Requested motion profile and operation mode; 3 bits. XACTUAL 0x21 RW Current internal microstep position; signed; 32 bits. VACTUAL 0x22 R Current step velocity; 24 bits; signed; no decimals. AACTUAL 0x23 R Current step acceleration; 24 bits; signed; no decimals. VMAX 0x24 RW Maximum permitted or target velocity; signed; 32 bits= 24+8 (24 bits integer part, 8 bits decimal places). VSTART 0x25 RW Velocity at ramp start; unsigned; 31 bits=23+8. VSTOP 0x26 RW Velocity at ramp end; unsigned; 31 bits=23+8. VBREAK 0x27 RW AMAX 0x28 RW DMAX 0x29 RW ASTART 0x2A RW DFINAL 0x2B RW BOW1 0x2D RW BOW2 0x2E RW BOW3 0x2F RW BOW4 0x30 RW CLK_FREQ 0x31 RW External clock frequency fCLK; unsigned; 25 bits. XTARGET 0x37 RW Target position; signed; 32 bits. STP_LENGTH_ADD DIR_SETUP_TIME Ramp generator affecting bits 5:0. Additional step length in clock cycles; 16 bits. At this velocity value, the aceleration/deceleration will change during trapezoidal ramps; unsigned; 31 bits=23+8. Maximum permitted or target acceleration; unsigned; 24 bits=22+2 (22 bits integer part, 2 bits decimal places). Maximum permitted or target deceleration; unsigned; 24 bits=22+2. Acceleration at ramp start or below VBREAK; unsigned; 24 bits=22+2. Deceleration at ramp end or below VBREAK; unsigned; 24 bits=22+2. First bow value of a complete velocity ramp; unsigned; 24 bits=24+0 (24 bits integer part, no decimal places). Second bow value of a complete velocity ramp; unsigned; 24bits=24+0. Third bow value of a complete velocity ramp; unsigned; 24 bits=24+0. Fourth bow value of a complete velocity ramp; unsigned; 24 bits=24+0. Table 13: Register Names: Ramp Generator © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 29/230 Step/Dir Output Configuration This section focuses on the description of the Step/Dir output configuration. Step/Dir output signals can be configured for the driver circuit. Step/Dir Output Configuration Steps If step signals must be longer than one clock cycle, do as follows: Action:  Set proper STP_LENGTH_ADD register 0x10 (bit 15:0). Result: The resulting step length is equal to STP_LENGTH_ADD+1 clock cycles. This is how the step length is assigned within a range of up to 1-up-to-216 clock cycles. Action:  Set proper DIR_SETUP_TIME register 0x10 (bit 31:16). Result: The delay period between DIROUT and STPOUT voltage level transitions last DIR_SETUP_TIME clock cycles. No steps are sent via STPOUT for DIR_SETUP_TIME clock cycles after a level change at DIROUT. PRINCIPLE: DIROUT does not change the level:   During active step pulse signal For (STP_LENGTH_ADD+1) clock cycles after the step signal returns to inactive level STPOUT characteristics can be set differently, as follows: STPOUT: Changing Polarity Per default, the step output is high active because a rising edge at STPOUT indicates a step. In order to change the polarity, do as follows: Action:  Set step_inactive_pol =1 (bit3 of GENERAL_CONF register 0x00). Result: Each falling edge indicates a step. How to prompt Level Change with every Step In order to prompt a step at every level change, do as follows: Action:  Set toggle_step =1 (bit4 of GENERAL_CONF register 0x00). Result: Every level change indicates a step. DIROUT: Changing the Polarity Per default, voltage level 1 at DIROUT indicates a negative step direction. DIROUT characteristics can be set differently, as shown below. In order to change polarity, do as follows: Action:  Set pol_dir_out =0 (bit5 of GENERAL_CONF register 0x00). Result: A high voltage level at DIROUT indicates a positive step direction. NOTE:  DIROUT is based on the internal µStep position MSCNT and is therefore based on the internal SinLUT, see section 10.2. , page 89 . © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 30/230 Altering the Internal Motion Direction Per default, a positive internal velocity VACTUAL results in a forward motion through internal SinLUT. Consequently, if VACTUAL < 0, the SinLUT values are developed backwards. How to change Motion Direction In order to alter the default setting of the Internal Motion Direction, do as follows: Action:  Set reverse_motor_dir =1 (bit28 of GENERAL_CONF register 0x00). Result: A positive internal velocity for VACTUAL results in a backward motion through the internal SinLUT. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 31/230 Configuration Details for Operation Modes and Motion Profiles This section provides information on the two available operation modes (velocity mode and positioning mode), and on the four possible motion profiles (no ramp, trapezoidal ramp including sixPoint™ ramp, and S-shaped ramp). Different combinations are possible. Each one of them has specific advantages. The choice of configuration depends on the user’s design specification to best suit his design needs. Description of Internal Ramp Generator With proper configuration, the internal ramp generator of the TMC4361A is able to generate various ramps with the related step outputs for STPOUT. In order to configure the internal ramp generator successfully – i.e. to make it fit as best as possible with your specific use case – information about the scope of each possible combination is provided in the table below and on the following pages. Ramp Generator Configuration Options Operation Motion Profile Mode Velocity Mode RAMPMODE(2:0) Description No ramp b’000 Trapezoidal ramp b’001 sixPoint ramp b’001 S-shaped ramp b’010 No Ramp b’100 Trapezoidal ramp b’101 Positioning sixPoint ramp Mode S-shaped ramp b’101 b’110 Follows VMAX request only. Follows VMAX request and considers acceleration and deceleration values. Follows VMAX request and considers acceleration / deceleration values and start and stop velocity values. Follows VMAX request and considers maximum acceleration / deceleration values and adapts these values with 4 different bow values. Follows XTARGET and VMAX requests only. Follows XTARGET request and a maximum velocity VMAX request and considers acceleration and deceleration values. Follows XTARGET request and a maximum velocity VMAX request and considers acceleration / deceleration values and start and stop velocity values. Follows XTARGET request and a maximum velocity VMAX request and considers maximum acceleration / deceleration values and adapts these values with 4 different bow values. Table 14: Overview of General and Basic Ramp Configuration Options © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 32/230 Starting Point: Choose Operation Mode Two operation modes are available: velocity mode and positioning mode. BEFORE YOU BEGIN ! Before setting any parameters: First select:  Operation mode and  Motion profile It is not advisable to change operation mode nor motion profile during motion. Operation Mode: Velocity Mode The RAMPMODE register provides a choice of two operation modes. Either velocity mode or positioning mode can be chosen. In order to use the velocity mode, do as follows: Action:  Set RAMPMODE(2) =0 (RAMPMODE register 0x20). Result: Velocity mode is selected. The target velocity VMAX is reached with the selected motion profile. Operation Mode: Positioning Mode In order to make use of the positioning mode, do as follows: Action:  Set RAMPMODE(2)=1 (RAMPMODE register 0x20). Result: Positioning mode is selected. VMAX is the maximum velocity value of this motion profile that is based on the condition that the ramp stops at target position XTARGET. NOTE:  The sign of VMAX is not relevant during positioning. The direction of the steps depends on XACTUAL, XTARGET, and the current ramp motion profile status. NOTE:  Do NOT exceed VMAX ≤ fCLK ¼ pulses for positioning mode. Stop during Motion In order to stop the motion during positioning, do as follows: Action:  Set VMAX = 0 (register 0x24). Result: The velocity ramp directs to VACTUAL = 0, using the actual ramp parameters. i Motion is proceeded with VMAX ≠ 0. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Motion Profile Configuration 33/230 Three basic motion profiles are provided. Each one of them has a different velocity value development during the drive. See table below. For configuration of the motion profiles, do as follows: Action:  Use the bits 1 and 0 of the RAMPMODE register 0x20. Result: As specified in the table below. You can choose different configuration options from the list below:    No Ramp motion profile Trapezoidal Ramp motion profile (including sixPoint Ramp) S-shaped Ramp motion profiles TMC4361A Motion Profile RAMPMODE (1:0) Motion Profile Function b’00 No Ramp Follow VMAX only (rectangular velocity shape). Trapezoidal Ramp Consideration of acceleration and deceleration values without adaptation of these acceleration values. sixPoint Ramp Consideration of acceleration and deceleration values without adaptation of these acceleration values. Usage of start and stop velocity values. (see section 6.5. , Page 46) b’01 b’10 S-shaped Ramp Use all ramp values (including bow values). Table 15: Description of TMC4361A Motion Profiles © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 34/230 v(t) No Ramp Motion Profile VMAX t Figure 19: No Ramp Motion Profile In order to make use of the no ramp motion profile, which is rectangular, do as follows: Action:  Set RAMPMODE(1:0) =b’00 (register 0x20).  Set proper VMAX register 0x24. Result: The internal velocity VACTUAL is immediately set to VMAX. Positioning Mode combined with No Ramp Motion Profile Combining positioning mode with the no ramp motion profile determines that the ramp holds VMAX until XTARGET is reached. The motion direction depends on XTARGET. In order to make use of the no ramp motion profile in combination with the positioning mode, do as follows: Action:  Set RAMPMODE(2:0) =b’100.  Set proper VMAX register 0x24.  Set proper XTARGET register 0x37. Result: VACTUAL is set instantly to 0 in case the target position is reached. NOTE:  Do NOT exceed VMAX ≤ fCLK / 4 pulses for positioning mode. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 35/230 In order to make use of a trapezoidal 4-point ramp motion profile without break velocity, do as follows: Trapezoidal 4-Point Ramp without Break Point Action:  Set RAMPMODE(1:0) =b’01 (register 0x20).  Set VBREAK =0 (register 0x27).  Set proper AMAX register 0x28 and DMAX register 0x29.  Set proper VMAX register 0x24. Result: The internal velocity VACTUAL is changed successively to VMAX with a linear ramp. Only AMAX and DMAX define the acceleration/deceleration slopes. NOTE:  AMAX determines the rising slope from absolute low to absolute high velocities, whereas DMAX determines the falling slope from absolute high to absolute low velocities.  Acceleration slope and deceleration slopes have only one acceleration and deceleration value each. v(t) VMAX v(t) A1 A2 A3 VMAX VBREAK A1L A1 A2 A3 A3L t t Figure 20: Trapezoidal Ramp without Break Point Trapezoidal Ramp with Break Point Figure 21: Trapezoidal Ramp with Break Point In order to make use of a trapezoidal ramp motion profile with break velocity, do as follows: Action:  Set RAMPMODE(1:0)=b’01 (register 0x20).  Set proper VBREAK register 0x27.  Set proper AMAX register 0x28 and DMAX register 0x29.  Set proper ASTART register 0x2A and DFINAL register 0x2B.  Set proper VMAX register 0x24. Result: The internal velocity VACTUAL is changed successively to VMAX with a linear ramp. In addition to AMAX and DMAX, ASTART and DFINAL define the acceleration or deceleration slopes (see Figure above). NOTES:  AMAX and ASTART determines the rising slope from absolute low to absolute high velocities.  DMAX and DFINAL determines the falling slope from absolute high to absolute low velocities.  The acceleration/deceleration factor alters at VBREAK. ASTART and DFINAL are valid below VBREAK, whereas AMAX and DMAX are valid beyond VBREAK. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Position Mode combined with Trapezoidal Ramps 36/230 Motion direction depends on XTARGET. In order to use a 4-point or sixPoint ramps during positioning mode, do as follows: Action:  Set RAMPMODE(2:0) =b’101 (register 0x20).  Set Trapezoidal ramp type accordingly, as explained above.  Set proper XTARGET register 0x37. Result: The ramp finishes exactly at the |VACTUAL| = VMAX as long as possible. AACTUAL Assignments for Trapezoidal Ramps target position XTARGET by keeping AACTUAL assignments apply both for 4-point and sixPoint ramps. The acceleration/deceleration factor AACTUAL register depends on the current ramp phase and the velocity that needs to be reached. The related sign assignment for different ramp phases is given in the following table: AACTUAL ASSIGNMENTS for Trapezoidal Ramps Ramp phase: A1L A1 A2 A3 A3L v>0: AACTUAL= ASTART AMAX 0 −DMAX −DFINAL v0 DFINAL>0 t Figure 23: S-shaped Ramp with initial and final Acceleration/Deceleration Values  Description is continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12   Definitions for S-shaped Ramps AACTUAL 39/230   The acceleration/deceleration values are altered, based on the bow values. The start phase and the end phase of an S-shaped ramp is accelerated/decelerated by ASTART and DFINAL. The ramp starts with ASTART and stops with DFINAL. DFINAL becomes valid when AACTUAL reaches the chosen DFINAL value. i The parameter DFINAL is not considered during positioning mode. AACTUAL assignments and current bow value selection for S-shaped ramps. The acceleration/deceleration factor depends on the current ramp phase and alters every 64 clock cycles during the bow phases B1, B2, B3, and B4. Assignments for S-shaped Ramps Details are provided in the table below: S-shaped Ramps: Assignments for AACTUAL and Internal Bow Value Ramp phase: B1 B12 B2 B23 B3 B34 B4 v>0: AACTUAL= ASTARTAMAX AMAX AMAX0 0 0-DMAX -DMAX -DMAX-DFINAL BOW1 0 -BOW2 0 -BOW3 0 BOW4 -ASTART-AMAX -AMAX -AMAX0 0 0DMAX DMAX DMAXDFINAL -BOW1 0 0 BOW3 0 -BOW4 BOWACTUAL= v 0 (register 0x25).  Set VSTOP = 0 (register 0x26). Result: The trapezoidal ramp starts with initial velocity. NOTE:  The initial acceleration value is AMAX if VBREAK < VSTART, otherwise the starting acceleration value is ASTART. v(t) VMAX VBREAK A1L A1 A2 A3 A3L VSTART t Figure 24: Trapezoidal Ramp with initial Velocity If trapezoidal ramp with initial velocity VSTART is selected: NOTICE Avoid unintended system behavior during positioning mode!  Use VSTART without setting VSTOP > VSTART only in positioning mode if there is enough distance between the current position XACTUAL and the target position XTARGET. This will ensure smooth operation during positioning mode. Turn page for information on how to configure S-shaped ramps with initial start velocity. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 S-shaped Ramps with initial Start Velocity 41/230 In order to use S-shaped ramps with initial start velocity, do as follows: Action:     Set Set Set Set RAMPMODE(1:0)=b’10 (register 0x20). S-shaped ramp type accordingly, as explained before. proper VSTART > 0 (register 0x25). VSTOP = 0 (register 0x26). Result: The S-shaped ramp starts with initial velocity. PRINCIPLE:  The initial acceleration value is equal to AMAX. The parameter ASTART is not considered. Consequently, ramp phase B1 is not performed. v(t) VMAX B1 B12 B2 B23 B3 B34 B4 VSTART t Figure 25: S-shaped Ramp with initial Start Velocity If S-shaped ramp with initial velocity VSTART is selected: NOTICE Avoid unintended system behavior during positioning mode!   Keep in mind that the S-shaped character of the curve is maintained. Because AMAX is the start acceleration value, the ramp will always execute phase B2 which could result in positioning overshoots. Use VSTART only in positioning mode if there is enough distance between the current position XACTUAL and the target position XTARGET. This will ensure smooth operation during positioning mode. Turn page for information on how to configure finishing ramps with stop velocity. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Finishing Ramps with Stop Velocity 42/230 S-shaped and trapezoidal velocity ramps can be finished with a stop velocity value if you set VSTOP value higher than zero (see figure below). In order to configure trapezoidal ramps with stop velocity, do as follows: Action:  Set RAMPMODE(1:0)=b’01 (register 0x20).  Set Trapezoidal ramp type accordingly, as explained before.  Set VSTART = 0 (register 0x25).  Set proper VSTOP > 0 (register 0x26). Result: The trapezoidal ramp stops with defined velocity. v(t) VMAX VBREAK A1L A1 A2 A3 A3L VSTOP t Figure 20: Trapezoidal Ramp with Stop Velocity If trapezoidal ramps are selected (VBREAK > 0): NOTICE Avoid unintended system behavior during positioning mode!   Set VBREAK > VSTOP. Set VSTART < VSTOP. This will ensure smooth operation during positioning mode. Turn page for configuration information on S-shaped ramps with stop velocity. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 S-shaped Ramps with Stop Velocity 43/230 In order to use S-shaped ramps with stop velocity, do as follows: Action:  Set RAMPMODE(1:0)=b’10 (register 0x20).  Set S-shaped ramp type accordingly, as explained before.  Set VSTART = 0 (register 0x25).  Set proper VSTOP > 0 (register 0x26). Result: The S-shaped ramp finishes with stop velocity. NOTE:  The final deceleration value is equal to DMAX. The parameter DFINAL is not considered. Consequently, ramp phase B4 is not performed. v(t) VMAX B1 B12 B2 B23 B3 B34 B4 VSTOP t Figure 26: S-shaped Ramp with Stop Velocity Interaction of VSTART, VSTOP, VACTUAL and VMAX:     VSTOP can be used in positioning mode, if the target position is reached. In velocity mode, VSTOP is also used if VACTUAL ≠ 0 and the target velocity VMAX is assigned to 0. VSTART and VSTOP are not only used to start or end a velocity ramp. If the velocity direction alters due to register assignments while a velocity ramp is in progress, the velocity values develop according to the current velocity ramp type, using VSTART or VSTOP. The unsigned values VSTART and VSTOP are valid for both velocity directions. Every register value change is assigned immediately. Turn page for information on how to configure S-shaped ramps with start and stop velocity. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 S-shaped Ramps with Start and Stop Velocity 44/230 S-shaped ramps can be configured with a combination of VSTART and VSTOP. It is possible to include both processes in one S-Shaped ramp to decrease the time between start and stop of the ramp. In order to use S-Shaped ramps with a combination of start and stop velocity, do as follows: Action:     Set RAMPMODE(1:0)=b’10. Set S-shaped ramp type accordingly, as explained before, but with BOW2 ≠ BOW4. Set proper VSTART > 0 (register 0x25). Set proper VSTOP > 0 (register 0x26). Result: The S-shaped ramp starts with initial velocity and stops with defined velocity. v(t) VMAX B1 B12 B2 B23 B3 B34 B4 VSTOP VSTART t Figure 27: S-shaped Ramp with Start and Stop Velocity If S-shaped ramp with initial velocity VSTART and stop velocity VSTOP is selected: NOTICE Avoid unintended system behavior during positioning mode!   Keep in mind that the S-shaped character of the curve is maintained. Because AMAX is the start acceleration value, the ramp will always execute phase B2, which could result in positioning overshoots. Use VSTART in positioning mode, if there is enough distance between the current position XACTUAL and the target position XTARGET. This will ensure smooth operation during positioning mode. Turn page for information on how to use VSTART and ASTART for S-shaped ramps. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Combined Use of VSTART and ASTART for S-shaped Ramps 45/230 For some S-shaped ramp applications it can be useful to start with a defined velocity value (VSTART > 0);but not with the maximum acceleration value AMAX. In order to start with a defined velocity value, do as follows: Action:  Set RAMPMODE(1:0) =b’10 (register 0x20).  Set S-shaped ramp type accordingly, as explained before.  Set proper VSTART > 0 (register 0x25).  Set proper VSTOP > 0 (register 0x26).  Set use_astart_and_vstart =1 (bit0 of the GENERAL_CONF register 0x00). Result: The following special ramp types can be generated in this way, as shown below. i Section B1 is passed through although VSTART is used. Using VSTART and starting acceleration of 0 for S-shaped ramps Using VSTART and starting acceleration, which is smaller than AMAX for S-shaped ramps v(t) v(t) B1 B12 B2 B23 B3 B34 B4 VMAX VSTART VSTOP VMAX B1 B12 B2 B23 B3 B34 B4 VSTART VSTOP t aSTART = 0 aSTART > 0 Figure 28: S-shaped Ramps with combined VSTART and ASTART Parameters If S-shaped ramp with VSTART, ASTART, and VSTOP is selected: NOTICE Avoid unintended system behavior during positioning mode!   Keep in mind that the S-shaped character of the curve is maintained. Because ASTART is the start acceleration value, the ramp will always execute phase B2, which could result in positioning overshoots. Use VSTART and ASTART > 0 without setting VSTOP > VSTART only in positioning mode, if there is enough distance between the current position XACTUAL and the target position XTARGET. This will ensure smooth operation during positioning mode. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 46/230 sixPoint Ramps sixPoint ramps are trapezoidal ramps with initial and stop velocity values that also make use of two acceleration and two deceleration values. Configuration of sixPoint Ramps sixPoint ramps are trapezoidal velocity ramps that can be configured with a combination of VSTART and VSTOP. In order to use trapezoidal ramps with a combination of start and stop velocity, do as follows: Action:      Set Set Set Set Set RAMPMODE(1:0)=b’01 (register 0x20). a Trapezoidal ramp type appropriately as explained in section 6.3.6, page 35. proper VSTART > 0 (register 0x25). proper VSTOP > 0 (register 0x26). proper VBREAK > 0 (register 0x27). Result: The sixPoint ramp starts with an initial velocity and stops with a defined velocity. Diagram of sixPoint Ramp v(t) VMAX VBREAK A1L A1 A2 A3 A3L VSTOP VSTART t Figure 29: sixPoint Ramp: Trapezoidal Ramp with Start and Stop Velocity If a sixPoint ramp is used: NOTICE Avoid unintended system behavior during positioning mode!   Set VBREAK > VSTOP. Set VSTART < VSTOP. This will ensure smooth operation during positioning mode. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 47/230 U-Turn Behavior The process that is triggered when motion direction changes during motion, is described below, and applies to all ramp types. U-Turn Behavior In case the motion direction is changed during motion in velocity mode (by direct assignment of VMAX) or in positioning mode (due to XTARGET reassignment), the following process is triggered: 1. Motion is directed to VACTUAL = 0. i 2. A standstill phase of TZEROWAIT clock cycles (register 0x7B) occurs. i 3. It is recommended to assign TZEROWAIT > 0, if VSTOP and/or a trapezoidal ramp type are used, because motor oscillations can occur that must peter out. Motion continues to the actual XTARGET (positioning mode), or to the newly assigned VMAX (velocity mode). i Example: U-Turn for sixPoint Ramps If VSTOP is used (≠ 0), motion terminates at VSTOP. If VSTART is used (≠ 0), motion begins with VSTART if TZEROWAIT > 0. After reaching VSTOP, TZEROWAIT clock cycles are waited until motion continues to peter out motor oscillations. v(t) TZEROWAIT VMAX VBREAK VSTOP VSTART t -VSTART -VSTOP -VBREAK -VMAX Figure 30: Example for U-Turn Behavior of sixPoint Ramp  Turn page for information on U-Turn for S-shaped ramps. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Example: U-Turn for S-shaped Ramps 48/230 When VACTUAL = 0 is reached, motion immediately continues. In most S-shaped ramp applications that do not use VSTOP, a standstill phase is not required. If ASTART > 0 and/or DFINAL > 0, these parameters are also used during U-Turn. v(t) TZEROWAIT =0 -VMAX t -VMAX Figure 31: Example for U-Turn Behavior of S-shaped Ramp Continuous Velocity Motion Profile for S-shaped Ramps There is one exception to the above explained U-Turn process: In case BOW2 equals BOW4, the S-shaped ramp is not stopped at VACTUAL = 0. While passing VACTUAL = 0, motion acceleration does not equal 0. Thus, the fastest possible U-Turn behavior for this ramp is created. In the figure below, this velocity ramp behavior is depicted as bold black line, whereas the velocity ramp behavior of the process explained above is depicted gray line: v(t) BOW2=BOW4! -VMAX t -VMAX Figure 32: Direct transition via VACTUAL=0 for S-shaped Ramps © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 49/230 Internal Ramp Generator Units This section provides information about the arithmetical units of the ramp parameters. Clock Frequency Velocity Value Units All parameter units are real arithmetical units. Therefore, it is necessary to set the CLK_FREQ register 0x31 to proper [Hz] value, which is defined by the external clock frequency fCLK. Any value between fCLK = 4.2 MHz and 32 MHz can be selected. Default configuration is 16 MHz. Velocity values are always defined as pulses per second [pps]. VACTUAL is given as a 32-bit signed value with no decimal places. The unsigned velocity values VSTART, VSTOP, and VBREAK consist of 23 digits and 8 decimal places. VMAX is a signed value with 24 digits and 8 decimal places. The maximum velocity VMAX is restricted as follows: Velocity mode: |VMAX| ≤ ½ pulse · fCLK Positioning mode: |VMAX| ≤ ¼ pulse · fCLK NOTE:  In case VACTUAL exceeds this limit INCORRECT step pulses at STPOUT output occur and/or positioning is not executed properly. Furthermore, VMAX have to be the highest nominal value of all velocity values: |VMAX| > max(VSTART;VSTOP;VBREAK) Acceleration Value Units The unsigned values AMAX, DMAX, ASTART, DFINAL, and DSTOP consist of 22 digits and 2 decimal places. AACTUAL shows a 32-bit nondecimal signed value. Acceleration and deceleration units are defined per default as pulses per second² [pps²]. If higher acceleration/deceleration values are required for short and steep ramps, do as follows: Action:  Set direct_acc_val_en =1 (GENERAL_CONF register 0x00). Result: The parameters are defined as velocity value change per clock cycle with 24-bit unsigned decimal places (MSB =2-14). The values are calculated as follows: AMAX [pps2] = AMAX / 237 · fCLK2 DMAX [pps2] = DMAX / 237 · fCLK2 ASTART [pps2] = ASTART / 237 · fCLK2 DFINAL [pps2] = DFINAL / 237 · fCLK2 DSTOP [pps2] = DSTOP / 237 · fCLK2 The maximum acceleration or deceleration values are as follows: max(AMAX;DMAX;ASTART;DFINAL;DSTOP) [pps²] ≤ VMAX · fCLK / 1024 In case direct_acc_val_en = 1, the maximum value is also limited to: max(AMAX;DMAX;ASTART;DFINAL;DSTOP) ≤ 220  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 50/230 Bow values BOW1…BOW4: Bow values are unsigned 24-bit values without decimal places. They are defined per default as pulses per second³ [pps³]. Bow Value Units In case higher bow values are required for short and steep ramps, do as follows: Action:  Set direct_bow_val_en =1 (GENERAL_CONF register 0x00) Result: The parameters are defined as acceleration value change per clock cycle with 24-bit unsigned decimal places with the MSB defined as 2-29. The particular bow values BOW1, BOW2, BOW3, BOW4 are calculated as follows: BOWx [pps3] = BOWx / 253 · fCLK3 The maximum bow are as follows: max(BOW1…4) [pps²] ≤ max(AMAX;DMAX) [pps²] · fCLK / 1024 In case direct_bow_val_en = 1, the maximum value is also limited to: max(BOW1…4) ≤ 220 Overview of Minimum and Maximum Values: Minimum and Maximum Values (Frequency Mode and in general) Value Classes Affected Registers Minimum Nominal Value Maximum Nominal Value Maximum Related Value Velocity Acceleration Bow Clock VMAX, VSTART, VSTOP, VBREAK AMAX, DMAX, ASTART, DFINAL BOW1, BOW2, BOW3, BOW4 CLK_FREQ 3.906 mpps 0.25 mpps2 1 mpps3 4.194 MHz 8.388 Mpps 4.194 Mpps2 16.777 Mpps3 32 MHz Velocity mode: ½ pulse · fCLK Positioning mode: ¼ pulse · fCLK |VMAX| > max(VSTART;VSTOP;VBREAK) VMAX · fCLK / 1024 max(AMAX;DMAX) · fCLK / 1024 (fCLK) Table 18: Minimum and Maximum Values if Real World Units are selected Minimum and Maximum Values for Steep Slopes (Direct Mode, example with fCLK =16MHz) Value Classes Affected Registers Calculation Minimum Nominal Value Maximum Nominal Value Maximum Related Value Acceleration (direct_acc_val_en =1) Bow (direct_bow_val_en =1) AMAX, DMAX, ASTART, DFINAL, DSTOP BOW1, BOW2, BOW3, BOW4 a[pps²] = (∆v/clk_cycle) / 237 · fCLK2 bow[pps³] = (∆a/clk_cycle) / 253 · fCLK3 ~1.86 kpps² ~454.75 kpps³ ~1.95 Gpps² ~476.837 Gpps3 VMAX · 15625 Hz max(AMAX;DMAX) · 15625 Hz Table 19: Minimum and Maximum Values for Steep Slopes for fCLK =16MHz © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 7. 51/230 External Step Control and Electronic Gearing Steps can also be generated by external steps that are manipulated internally by an electronic gearing process. In the following chapter, steps generation by external control and electronic gearing is presented. Pins for External Step Control Pin Names Type Remarks STPIN Input Step input signal. DIRIN Input Direction input signal. Table 20: Pins used for External Step Control Registers used for external Step Control Register Name Register Address Remarks GENERAL_CONF 0x00 RW Bits 9:6, 26. GEAR_RATIO 0x12 RW Electronic gearing factor; signed; 32 bits=8+24 (8-bit digits, 24-bit decimal places). Table 21: Registers used for External Step Control Enabling External Step Control In order to synchronize with other motion controllers, TMC4361A offers a step direction input interface at the STPIN and DIRIN input pins. i Three options are available. In case one of these options is selected, the internal step generator is disabled. OPTION 1: HIGH ACTIVE EXTERNAL STEPS Action:  Set sdin_mode = b’01 (GENERAL_CONF register 0x00). Result: As soon as the STPIN input signal switches to high state the control unit recognizes an external step. OPTION 2: LOW ACTIVE EXTERNAL STEPS Action:  Set sdin_mode = b’10 (GENERAL_CONF register 0x00). Result: As soon as the STPIN input signal switches to low state the control unit recognizes an external step. OPTION 3: TOGGLING EXTERNAL STEPS Action:  Set sdin_mode = b’11 (GENERAL_CONF register 0x00). Result: As soon as the STPIN input signal switches to low or high state the control unit recognizes an external step.  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Selecting the Input Direction Polarity 52/230 DIRIN polarity can be assigned. Per default, the negative direction is indicated by DIRIN = 0. In order to change this polarity: Action:  Set pol_dir_in = 1 (GENERAL_CONF register 0x00). Result: A negative input direction is assigned by DIRIN = 1. Description of Electronic Gearing If an external step is not congruent with an internal step, the GEAR_RATIO register 0x12 must be set accordingly. This signed parameter consists of eight bit digits and 24 bits decimal places. With every external step the assigned GEAR_RATIO value is added to an internal accumulation register. As soon as an overflow occurs, an internal step is generated and the remainder will be kept for the next external step. Any absolute gearing value between 2-24 and 127 is possible. NOTE:  Gearing ratios beyond 1 are more reasonable for the SPI output. The internal SinLUTable is used that generates multiple steps one after another without interpolation, if the accumulation register value is above 1. In contrast to a burst of steps at the STPOUT pin, the SPI output will only forward the new position in the inner SinLUT where only some values have been skipped if |GEAR_RATIO|>1.  A negative gearing factor GEAR_RATIO < 0 inverts the interpretation of the input direction which is determined by DIRIN and pol_dir_in. Indirect External Control It is possible to use the internal ramp generator in combination with the external S/D interface. In this case, the external step impulses transferred via STPIN and DIRIN cannot influence the internal XACTUAL counter directly. Instead, the XTARGET register is altered by 1 or -1 with every GEAR_RATIO accumulation register overflow. NOTE:  Whether XTARGET is increased or decreased is determined similarly to the direct electronic gearing control. The accumulation register overflow direction indicates the target alteration. Respectively, the accumulation direction is determined by the GEAR_RATIO sign, by pol_dir_in, and by DIRIN.  Consecutive input steps must occur with a distance of minimum 64 clock cycles. i This feature allows a synchronized motion of different positioning ramps for different TMC4361A chips with differently configured ramps. In order to select indirect external control, do as follows: Action:  Set sdin_mode ≠ b’00 according to the required external control option.  Set sd_indirect_control = 1 (GENERAL_CONF register 0x00). Result: As soon as an external step is generated, XTARGET is increased or decreased, according to the accumulation direction. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Switching from External to Internal Control 53/230 In some cases, it is useful to switch from external to internal ramp generation during motion. TMC4361A supports a smooth transfer from direct external control to an internal ramp. The only parameter you need to know and apply is the current velocity when the switching occurs. In more detail, this means that when the external control is switched off, VSTART takes over the definition of the actual velocity value. The ramp direction is then selected automatically. The time step of the last internal step is also taken into account in order to provide a smooth transition from external to internal ramp control. In order to select automatic switching from external to internal control, do as follows: PRECONDITION (EXTERNAL DIRECT CONTROL IS ACTIVE): Action:  Set sdin_mode ≠ b’00 (GENERAL_CONF register 0x00).  Set sd_indirect_control = 0 (GENERAL_CONF register 0x00).  Set ASTART = 0 (register 0x2A). PROCEED WITH: Action:  Set automatic_direct_sdin_switch_off = 1 (GENERAL_CONF register 0x00) once before switching to internal control.  Continually adapt VSTART register 0x25 according to the actual velocity of the TMC4361A that must be calculated in the µC.  If switching must be prompted, set sdin_mode = b’00. Result: The internal ramp velocity is started with the value of VSTART, and the direction is set automatically on the basis of the external steps that have occurred before. Smooth Switching for S-shaped Ramps In order to also support a smooth S-shaped ramp transition - when the external step control is switched off - the starting acceleration value can also be set separately at ASTART register 0x2A. i In contrast to the automatic direction assignment, the sign of ASTART must be set manually. In order to select automatic switching from external to internal control with a starting acceleration value, do as follows: PRECONDITION (EXTERNAL DIRECT CONTROL IS ACTIVE): Action:  Set sdin_mode ≠ b’00 (GENERAL_CONF register 0x00).  Set sd_indirect_control = 0 (GENERAL_CONF register 0x00). PROCEED WITH: Action:  Set automatic_direct_sdin_switch_off = 1 once before switching to internal control.  Continually adapt VSTART register 0x25 according to the actual velocity of the TMC4361A — that must be calculated in the µC.  Continually adapt ASTART according to the actual acceleration (unsigned value) of the TMC4361A — that must be calculated in the µC.  Continually set ASTART(31) = 0 or 1 according to the acceleration direction.  If switching must be prompted, set sdin_mode = b’00. Result: The internal ramp velocity is started with the value of VSTART, and the direction is set automatically on the basis of the external steps that have occurred before. The internal acceleration value is set to: +ASTART if ASTART(31) = 0 or –ASTART if ASTART(31) = 1. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 8. 54/230 Reference Switches The reference input signals of the TMC4361A function partly as safety features. The TMC4361A provides a range of reference switch settings that can be configured for many different applications. The TMC4361A offers two hardware switches (STOPL, STOPR) and two additional virtual stop switches (VIRT_STOP_LEFT, VIRT_STOP_RIGHT). A home reference switch HOME_REF is also available. Pins used for Reference Switches Pin Names Type Remarks STOPL Input Left reference switch. STOPR Input Right reference switch. HOME_REF Input Home switch. TARGET_REACHED Output Reference switch to indicate XACTUAL=XTARGET. Table 22: Pins used for Reference Switches Dedicated Registers for Reference Switches Register Name Register Address Remarks REFERENCE_CONF 0x01 RW Configuration of interaction with reference pins. HOME_SAFETY_MARGIN 0x1E RW Region of uncertainty around X_HOME. DSTOP 0x2C RW Deceleration value if stop switches STOPL / STOPR or virtual stops are used with soft stop ramps. The deceleration value allows for an automatic linear stop ramp. POS_COMP 0x32 RW Free configurable compare position; signed; 32 bits. VIRT_STOP_LEFT 0x33 RW VIRT_STOP_RIGHT 0x34 RW X_HOME 0x35 RW Home reference position; signed; 32 bits. X_LATCH 0x36 RW Stores XACTUAL at different conditions; signed; 32 bits. Virtual left stop that triggers a stop event at XACTUAL ≤ VIRT_STOP_LEFT; signed; 32 bits. Virtual left stop that triggers a stop event at XACTUAL ≥ VIRT_STOP_RIGHT; signed; 32 bits. Table 23: Dedicated Registers for Reference Switches © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 55/230 Hardware Switch Support The TMC4361A offers two hardware switches that can be configured according to your design. STOPL and STOPR The hardware provides a left and a right stop in order to stop the drive immediately in case one of them is triggered. Therefore, pin 12 and pin 14 of the motion controller must be used. NOTE:  Both switches must be enabled before motion occurs. In order to enable STOPL correctly, do as follows: Action:  Determine the active polarity voltage of STOPL and set (REFERENCE_CONF register 0x01) accordingly.  Set stop_left_en =1 (REFERENCE_CONF register 0x01). pol_stop_left Result: The current velocity ramp stops in case the STOPL voltage level matches pol_stop_left and VACTUAL < 0. In order to enable STOPR correctly, do as follows: Action:  Determine the active polarity voltage of STOPR and set pol_stop_right (REFERENCE_CONF register 0x01) accordingly.  Set stop_right_en =1 (REFERENCE_CONF register 0x01). Result: The current velocity ramp stops in case STOPR voltage level matches pol_stop_right and VACTUAL > 0. Stop Slope Configuration for Hard or Linear Stop Slopes The stop slope can be configured for hard or linear stop slopes. Per default, hard stops are selected. If hard stops are required, do as follows: OPTION 1: HARD STOP SLOPES Action:  Set soft_stop_en =0 (REFERENCE_CONF register 0x01). Result: If one of the stop switches is active and enabled, the velocity ramp is set immediately to VACTUAL = 0. OPTION 2: LINEAR STOP SLOPES If linear stop ramps are required: Action:  Set proper DSTOP > max(DMAX; DFINAL) (register 0x2C).  Set soft_stop_en =1 (REFERENCE_CONF register 0x01). Result: If one of the stop switches is active and enabled, the velocity ramp is stopped with a linear deceleration slope until VACTUAL = 0 is reached. In this case the deceleration factor is determined by DSTOP. VSTOP is not considered during the stop deceleration slope. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 How Active Stops are indicated and reset to Free Motion 56/230 When an enabled stop switch becomes active the related status flag is set in the STATUS flags register 0x0F. The flag remains active as long as the stop switch remains active. The particular event is also released in the EVENTS register 0x0E, which remains active until the event bit is reset manually. When VACTUAL = 0 is reached after the stop event no motion toward this particular direction is possible. In order to move into the locked direction, the following is required: PRECONDITION 1: The particular stop switch is NOT active anymore. AND/OR PRECONDITION 2: The stop switch is disabled (stop_left/right_en = 0). Action:  Set back the active event by reading out the EVENTS register 0x0E. i See information about clearing events provided in section 5.1. , page 25. Result: The active stop event is reset to free motion into the locked direction. How to latch Internal Position on Switch Events It is possible to select four different events to store the current internal position XACTUAL in the register X_LATCH. The table below show which transition of the reference signal leads to the X_LATCH transfer. For each transition process the specified reference configurations in the REFERENCE_CONF register 0x01 must be set accordingly. Reference Configuration pol_stop_left=0 pol_stop_left=1 pol_stop_right=0 pol_stop_right=1 latch_x_on_inactive_l=1 STOPL=0  1 STOPL=1  0 --- --- latch_x_on_active_l=1 STOPL=1  0 STOPL=0  1 --- --- latch_x_on_inactive_r=1 --- --- STOPR=0  1 STOPR = 10 latch_x_on_active_r=1 --- --- STOPR=1  0 STOPR = 01 Table 24: Reference Configuration and Corresponding Transition of particular Reference Switch Interchange the Reference Switches without Physical Reconnection If you need to change the directions of the reference switches, do as follows: Action:  Set invert_stop_direction=1 (REFERENCE_CONF register 0x01). Result: STOPL is now the right reference switch and STOPR is now the left reference switch. Consequently, all configuration parameters for STOPL become valid for STOPR and vice versa. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 57/230 Virtual Stop Switches TMC4361A provides additional virtual limits; which trigger stop slopes in case the specific virtual stop switch microstep position is reached. Virtual stop positions are assigned using the VIRTUAL_STOP_LEFT register 0x33 and VIRTUAL_STOP_RIGHT register 0x34. In this section, configuration details for virtual stop switches are provided for various design-in purposes. NOTE:  Virtual stop switches must be enabled in the same manner as nonvirtual reference switches. Hitting a virtual limit switch - by receiving the assigned position - triggers the same process as hitting STOPL or STOPR. Enabling Virtual Stop Switches In order to enable left virtual stop correctly, do as follows: Action:  Set VIRTUAL_STOP_LEFT register 0x33 according to left stop position.  Set virtual_left_limit_en =1 (REFERENCE_CONF register 0x01). Result: The actual velocity ramp stops in case XACTUAL ≤ VIRT_STOP_LEFT. The ramp is stopped according to the selected ramp type. In order to enable right virtual stop correctly, do as follows: Action:  Set VIRTUAL_STOP_RIGHT register 0x34 according to right stop position.  Set virtual_right_limit_en =1 (REFERENCE_CONF register 0x01). Result: The actual velocity ramp stops in case XACTUAL ≥ VIRT_STOP_RIGHT. The ramp is stopped according to the selected ramp type. The virtual stop slope can also be configured for hard or linear stop slopes. Virtual Stop Slope Configuration If virtual hard stops are required, do as follows: Action:  Set virt_stop_mode = b’01 (REFERENCE_CONF register 0x01). Result: If one of the virtual stop switches is active and enabled, the velocity ramp will be set immediately to VACTUAL = 0. If virtual linear stop ramps are required, do as follows: Action:  Set proper DSTOP > max(DMAX; DFINAL) (register 0x2C).  Set virt_stop_mode = b’10 (REFERENCE_CONF register 0x01). Result: If one of the virtual stop switches is active and enabled, the velocity ramp is stopped with a linear deceleration slope until VACTUAL = 0 is reached. In this case the deceleration factor is determined by DSTOP. VSTOP is not considered during the stop deceleration slope.  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 How Active Virtual Stops are indicated and reset to Free Motion 58/230 At the same time when an enabled virtual stop switch becomes active the related status flag is activated in the STATUS flags register 0x0F. The flag remains active as long as the stop switch remains active. The particular event is also released in the EVENTS register 0x0E, which remains active until the event is reset manually. When VACTUAL = 0 is reached after the stop event no motion in the particular direction is possible. In order to move into the locked direction, the following is required: PRECONDITION 1: The particular stop switch is NOT active anymore because the actual position does not exceed the specified limit. AND/OR PRECONDITION 2: Virtual stop switch is disabled (virtual_left/right_limit_en = 0). Action:  Set back active event by reading out EVENTS register 0x0E. i See information about clearing events provided in section 5.1. , page 25. Result: The active virtual stop event bit is reset to free motion into the direction that was locked beforehand. i invert_stop_direction has VIRTUAL_STOP_RIGHT. no influence on VIRTUAL_STOP_LEFT © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  and TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 59/230 Home Reference Configuration In this section home reference switch handling is explained with information about home tracking modes, possible home event configurations and home event monitoring. For monitoring, the switch reference input HOME_REF is provided. Switch Reference Input HOME_REF Perform the following to initiate the homing process: Action:  Assign a ramp according to your needs for the homing process.  Enable the home tracking mode with start_home_tracking = 1 (REFERENCE_CONF register 0x01).  Set the correct home_event (REFERENCE_CONF register 0x01) for the HOME_REF input pin (see table below).  Start the ramp towards the home switch HOME_REF. Result:  When the next home event is recognized, XACTUAL is latched to X_HOME.  At the same time, the start_home_tracking switch is disabled automatically in case XLATCH_DONE event is cleared.  The XLATCH_DONE event is released in the events register 0x0E. This event can be used for an interrupt routine for the homing process to avoid polling. i If an incremental encoder is used to monitor the motion, the N channel can be used to fine-tune the homing position (home_event = b’0000). After performing the homing process - as explained before - the N channel events can be used to obtain a more precise home position. i X_HOME can be overwritten manually. Nine different home events are possible. Home Event Selection i Except for the home_event = b’0000, which uses the index channel of an incremental encoder, home events are related to the the HOME_REF input pin: Home Event Selection Table Description X_HOME (direction: negative / positive) b’0011 HOME_REF = 0 indicates negative direction in reference to X_HOME HOME_REF b’1100 HOME_REF = 0 indicates positive direction in reference to X_HOME HOME_REF b’0110 X_HOME in center HOME_REF X_HOME on the left side HOME_REF b’0100 X_HOME on the right side HOME_REF b’1001 X_HOME in center HOME_REF X_HOME on the right side HOME_REF X_HOME on the left side HOME_REF home_event b’0010 b’1011 b’1101 HOME_REF = 1 indicates home position HOME_REF = 0 indicates home position 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Table 25: Overview of different home_event Settings © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 60/230 HOME_REF Monitoring An error flag HOME_ERROR_F is permanently evaluated. This error flag indicates whether the current voltage level of the HOME_REF reference input is valid in regard to X_HOME and the selected home_event. Defining a Home Range around HOME_REF In order to avoid false error flags (HOME_ERROR_F) because of mechanical inaccuracies, it is possible to setup an uncertainty home range around X_HOME. In this range, the error flag is not evaluated. If you want to define an uncertainty area around X_HOME, do as follows: Action:  Set HOME_SAFETY_MARGIN register 0x1E according to the required range [ustep]. Result: The homing uncertainties – related to the application environment – are considered for the ongoing motion. The error flag is NOT evaluated in the following range: X_HOME − HOME_SAFETY_MARGIN ≤ XACTUAL ≤ X_HOME + HOME_SAFETY_MARGIN NOTE:  It is recommended to assign to a higher range value for HOME_SAFETY_MARGIN in which the HOME_REF level is active for the home_events b’0110, b’0010, b’0100, b’1001, b’1011, and b’1101. It avoids false positive HOME_ERROR_Flags.  After homing with the index channel (home_event = b’0000) for a precise assignment of X_HOME the correct home_event has to be assigned in order to activate the generation of HOME_ERROR_Flags. Note that home_event = b’0000 results in HOME_ERROR_Flag=0 permanently.  The following examples illustrate the points at which the error flag is release – based on the selected home_event – here for home_event = b’0011 (*), b’1100 (**), b’0110 (***), b’0010 (***), b’0100 (***), b’1001 (****), b’1011 (****), and b’1101 (****). HOME_SAFETY_MARGIN HOME_SAFETY_MARGIN X_HOME X_HOME HOME_REF HOME_REF HOME_ERROR_Flag * HOME_ERROR_Flag * HOME_ERROR_Flag ** HOME_ERROR_Flag ** HOME_ERROR_Flag *** HOME_ERROR_Flag *** HOME_ERROR_Flag **** HOME_ERROR_Flag **** Figure 33: HOME_REF Monitoring and HOME_ERROR_FLAG © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 61/230 STOPL and STOPR inputs can also be used as HOME_REF inputs. Homing with STOPL or STOPR OPTION 1: STOPL IS THE HOME SWITCH Action:  Set stop_left_is_home = 1 (REFERENCE_CONF register 0x01). Result: The stop event at STOPL only occurs when the home range is crossed after STOPL becomes active. The home range is given by X_HOME and HOME_SAFETY_MARGIN. OPTION 2: STOPR IS HOME SWITCH Action:  Set stop_right_is_home = 1 (REFERENCE_CONF register 0x01). Result: The stop event at STOPR only occurs when the home region is crossed after STOPR becomes active. The home region is given by X_HOME and HOME_SAFETY_MARGIN. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 62/230 Target Reached / Position Comparison In this section, TARGET_REACHED output pin configuration options are explained, as well as different ways how to compare different values internally. Target Reached Output Pin TARGET_REACHED output pin forwards the TARGET_REACHED_Flag. As soon as XACTUAL equals XTARGET, TARGET_REACHED is active. Per default, the TARGET_REACHED pin is high active. To change the TARGET_REACHED output polarity, do the following: Action:  Set invert_pol_target_reached = 1 (bit16 of the GENERAL_CONF register 0x00). Result: TARGET_REACHED pin is low active. Connecting several Target-reached Pins TARGET_REACHED pins can also be configured for a shared signal line in the same way as several INTR pins can configured for one interrupt signal transfer (see section 5.4. (page 27). To use a Wired-Or or Wired-And behavior, the below described order of action must be executed: Action:  Step 1: Set intr_tr_pu_pd_en = 1 (GENERAL_CONF register 0x00). OPTION 1: WIRED-OR Action:  Step 2: Set tr_as_wired_and = 0 (GENERAL_CONF register 0x00). Result: The TARGET_REACHED pin works efficiently as Wired-Or (default configuration). i In case TARGET_REACHED pin is inactive, the pin drive has a weak inactive polarity output. During active state, the output is driven strongly. Consequently, if one of the connected pins is activated, the whole line is set to active polarity. OPTION 2: WIRED-AND Action:  Step 2: Set tr_as_wired_and = 1 (GENERAL_CONF register 0x00). Result: As long as the target position is not reached, the TARGET_REACHED pin has a strong inactive polarity output. During active state, the pin drive has a weak active polarity output. Consequently, the whole signal line is activated if all connected pins are forwarding the active polarity. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 63/230 Use of TARGET_REACHED Output Per default, TARGET_REACHED pin forwards the TARGET_REACHED_Flag that signifies XACTUAL = XTARGET. The pin can also be used to forward three other flags: VELOCITY_REACHED_Flag, ENC_FAIL_Flag, POS_COMP_REACHED_Flag. NOTE:  Only one option can be selected. Four Options for TARGET_REACHED The TARGET_REACHED output REFERENCE_CONF register 0x01. pin configuration switch is available The available optons are as follows: TARGET_REACHED Output Pin Configuration If pos_comp_output… Then TARGET_REACHED forwards… b’00 TARGET_REACHED_Flag b’01 VELOCITY_REACHED_Flag b’10 ENC_FAIL_Flag b’11 POS_COMP_REACHED_Flag Table 26: TARGET_REACHED Output Pin Configuration © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  at TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 64/230 Position Comparison of Internal Values TMC4361A provides several ways of comparing internal values. The position comparison process is permanently active and associated with one flag and one event. A positive comparison result can be forwarded through the INTR pin using the POS_COMP_REACHED event as interrupt source or by using the TARGET_REACHED pin as explained in section 8.4.2, page 63. Basic Comparison Settings How to compare the internal position with an arbitrary value: Action:  Select a comparison value in the POS_COMP register 0x32.  Select pos_comp_source = 0 (REFERENCE_CONF register 0x01). Result: XACTUAL is compared with POS_COMP. When POS_COMP equals XACTUAL the POS_COMP_REACHED_Flag becomes set and the POS_COMP_REACHED event becomes released. Select External Position as Comparison Base How to compare the external position with an arbitrary value: Action:  Select a comparison value in the POS_COMP register 0x32.  Select pos_comp_source = 1 (REFERENCE _CONF register 0x01). Result: ENC_POS is compared with POS_COMP. When POS_COMP equals ENC_POS the POS_COMP_REACHED_Flag becomes set and the POS_COMP_REACHED event becomes released. NOTE:  Because ENC_POS represents microsteps and not encoder steps, POS_COMP represents also microsteps for the comparison process with external positions.  In case ENC_POS moves past POS_COMP without assuming the same value as POS_COMP, the POS_COMP_REACHED event is not flagged but is nonetheless listed in the EVENTS register in order to indicate that it has traversed. In addition to comparing XACTUAL / ENC_POS with POS_COMP, it is also possible to conduct a comparison of one of both parameters with X_HOME or X_LATCH resp. ENC_LATCH. TMC4361A also allows comparison of the revolution counter REV_CNT against POS_COMP. Comparison selection grid SETTINGS ALERT ! Only the selected combination generates the POS_COMP_REACHED_Flag and the corresponding event. Therefore, select modified_pos_compare in the REFERENCE_CONF register 0x01 as outlined in the table below: Comparison Selection Grid pos_comp_source modified_pos_compare ‘0’ ‘1’ ‘00’ XACTUAL vs. POS_COMP ENC_POS vs. POS_COMP ‘01’ XACTUAL vs. X_HOME ENC_POS vs. X_HOME ‘10’ XACTUAL vs. X_LATCH ENC_POS vs. ENC_LATCH ‘11’ REV_CNT vs. POS_COMP Table 27: Comparison Selection Grid to generate POS_COMP_REACHED_Flag © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 65/230 Repetitive and Circular Motion TMC4361A also provides options for auto-repetitive or auto-circular motion. In this section configuration options are explained. Repetitive Motion to XTARGET Per default, reaching XTARGET in positioning mode finishes a positioning ramp. In order to continuously repeat the specified ramp, do as follows: PRECONDITION:  Set RAMPMODE(2) = 1 (positioning mode is active).  Configure a velocity ramp according to your requirements. Action:  Set clr_pos_at_target =1 (REFERENCE_CONF register 0x01). Result: After XTARGET is reached (TARGET_REACHED_Flag is active), XACTUAL is set to 0. As long as XTARGET is NOT 0, the ramp restarts in order to reach XTARGET again. This leads to repetitious positioning ramps from 0 towards XTARGET. NOTE:  It is possible to change XTARGET during repetitive motion. The reset of XACTUAL to 0 is always executed when XACTUAL equals XTARGET. Activating Circular Motion If circular motion profiles are necessary for your application, TMC4361A offers a position limitation range of XACTUAL with an automatic overflow processing. As soon as XACTUAL reaches one of the two position range limits (positive / negative), the value of XACTUAL is set automatically to the value of the opposite range limit. In order to activate circular motion, do as follows: PRECONDITION: If you want to activate circular motion, XACTUAL must be located within the defined range. PROCEED WITH: Action:  Set X_RANGE ≠ 0 (register 0x36, only writing access!).  Set circular_motion = 1 (REFERENCE_CONF register 0x01). Result: The positioning range of XACTUAL is limited to: −X_RANGE ≤ XACTUAL < X_RANGE. When XACTUAL reaches the most positive position ( X_RANGE – 1) and the motion proceeds in positive direction; the next XACTUAL value is set to −X_RANGE. The same applies to proceeding in negative direction; where (X_RANGE – 1) is the position after −X_RANGE. i During positioning mode, the motion direction will be dependent on the shortest path to the target position XTARGET. For example, if XACTUAL = 200, X_RANGE = 300 and XTARGET = −200, the positioning ramp will find its way across the overflow position (299  −300) (see Figure A) in Table 27 (page 68). © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Uneven or Noninteger Microsteps per Revolution Due to definition of the limitation range, one revolution only consists of an even number of microsteps. TMC4361A provides an option to overcome this limitation.     Example 1: Uneven Number of Microsteps per Revolution 66/230 Some applications demand different requirements because a revolution consists of an uneven or noninteger number of microsteps. TMC4361A allows a high adjustment range of microsteps by using: CIRCULAR_DEC register 0x7C. This value represents one digit and 31 decimal places as extension for the number of microsteps per one revolution. A revolution is completed at overflow position. With every completed revolution the CIRCULAR_DEC value is added to an internal accumulation register. In case this register has an overflow, XACTUAL remains at its overflow position for one step. On average, this leads to the following microsteps per revolution: Microsteps/rev = (2 · X_RANGE) + CIRCULAR_DEC / 231. One revolution consists of 601 microsteps. A definition of X_RANGE = 300 will only provide: 600 microsteps per revolution (−300 ≤ XACTUAL ≤ 299). Whereas X_RANGE = 301 will result in: 602 microsteps per revolution (−301 ≤ XACTUAL ≤ 300). By setting: CIRCULAR_DEC = 0x80000000 (= 231 / 231 = 1). An overflow is generated at the decimals accumulation register with every revolution. Therefore, XACTUAL prolongs the step at the overflow position for one step every time position overflow is overstepped. This results in a microstep count of 601 per revolution. Example 2: Noninteger Number of Microsteps per Revolution One revolution consists of 600.5 microsteps. Example 3: Noninteger and uneven Number of Microsteps per Revolution One revolution consists of 601.25 microsteps. By setting: CIRCULAR_DEC = 0x40000000 (= 230 / 231 = 0.5). Every second revolution an overflow is produced at the decimals’ accumulation register. This leads to a microstep count of 600 every second revolution and 601 for the other half of the revolutions. On average, this leads to 600.5 microsteps per revolution. By setting: CIRCULAR_DEC = 0xA0000000 (= (231 + 229) / 231 = 1.25). With every revolution an overflow is produced at the decimals’ accumulation register. Furthermore, at every fourth revolution an additional overflow occurs, which leads to another prolonged step. This leads to a microstep count of 601 for three of four revolutions and 602 for every fourth revolution. On average, this results in 601.25 microsteps per revolution. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Release of the Revolution Counter 67/230 By overstepping the position overflow, the internal REV_CNT register is increased by one revolution as soon as XACTUAL oversteps from (X_RANGE – 1) to -X_RANGE or is decreased by one revolution as soon as XACTUAL oversteps in the opposite direction. The information about the number of revolutions can be obtained by reading out register 0x36, which by default is the X_LATCH register (read only). In order to gain information on the number of revolutions: Action:  Set circular_cnt_as_xlatch = 1 (GENERAL_CONF register 0x00). Result: Register 0x36 cease to display the X_LATCH value. Instead, the revolution counter REV_CNT can be read out at this register address. NOTE:  As soon as circular motion is inactive (circular_motion=0), REV_CNT is reset to 0. Blocking Zones Activating Blocking Zones during Circular Motion During circular motion, virtual stops can be used to set blocking zones. Positions inside these blocking zones are NOT dedicated for motion. In order to activate the blocking zone, do as follows: PRECONDITION: Circular motion (X_RANGE ≠ 0). is activated (circular_motion = 0) and properly assigned PROCEED WITH: Action:  Set VIRTUAL_STOP_LEFT register 0x33 as left limit for the blocking zone.  Set VIRTUAL_STOP_RIGHT register 0x34 as right limit for the blocking zone.  Enable both virtual limits as explained in section 8.2.1 (page 57). Result: The blocking zone reaches from VIRTUAL_STOP_LEFT to VIRTUAL_STOP_RIGHT. During positioning, the path from XACTUAL to XTARGET does not lead through the blocking zone; which can result in a longer path compared to the direct path through the blocking zone (see Figure B1 in Table 28, page 68). However, the selected virtual stop deceleration ramp is initiated as soon as one of the limits is reached. This can result from the velocity mode or if the target XTARGET is located in the blocking zone.  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Blocking Zone Definition 68/230 The following positions are located within the blocking zone: XACTUAL ≤ VIRT_STOP_LEFT AND / OR XACTUAL ≥ VIRT_STOP_RIGHT NOTE:  In case VIRTUAL_STOP_LEFT < VIRTUAL_STOP_RIGHT, one of these conditions must be met in order to be located inside the blocking zone.  In case VIRTUAL_STOP_LEFT > VIRTUAL_STOP_RIGHT, both conditions must be met in order to be located inside the blocking zone. Circular Motion with and without Blocking Zone The table below shows circular motion (X_RANGE = 300). The green arrow depicts the path which is chosen for positioning. The shortest path selection is shown in Figure A and the consideration of blocking zones are shown in Figures B1 and B2. Circular Motion with (B1, B2) and Without (A) Blocking Zone A B1 0 0 PL=-2 90 VS TO 20 =2 PR Short path -200 TO VS VSTOPL=140 TO -300 299 Long path (but free) VS 200 Long path (and blocked) PR =7 0 0 Long path -200 B2 -300 299 200 Short path (but blocked) 200 -200 -300 299 Short path Table 28: Circular motion (X_RANGE = 300) Moving out of the Blocking Zone When XACTUAL is located inside the blocking zone, it is possible to move out without redefining the blocking zone. In order to get out of the blocking zone, do the following: Action:  Activate positioning mode: RAMPMODE(2) = 1.  Configure velocity ramp according to your needs.  Clear virtual stop events by reading out EVENTS register 0x0E.  Set regular target position XTARGET outside of the blocking zone. Result: TMC4361A initiates a ramp with the shortest way to the target XTARGET. i In order to match an incremental encoder in the same manner, select circular_enc_en =1 (REFERENCE_CONF register 0x01). © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 9. 69/230 Ramp Timing and Synchronization TMC4361A provides various options to initiate a new ramp. By default, every external register change is assigned immediately to the internal registers via an SPI input. With a proper start configuration, ramp sequences can be programmed without any intervention in between. Synchronization Opportunities Three levels of ramp start complexity are available. Predefined ramp starts are available, which are independent of SPI data transfer that are explained in the subsequent section 9.1. (page 70). Two optional features can be configured that can either be used individually or combined, which are as follows: Shadow Register Set A complete shadow motion register set can be loaded into the actual motion registers in order to start the next ramp with an altered motion profile. Target Position Pipeline Different target positions can be predefined, which are then activated successively. This pipeline can be configured as cyclic; and/or it can also be utilized to sequence different parameters. Masterless Synchronization Also, another start state “busy” can be assigned in order to synchronize several motion controllers for one single start event without a master. Dedicated Ramp Timing Pins Pin Names Type Remarks START Input and Output External start input to get a start signal or external start output to indicate an internal start event. Table 29: Dedicated Ramp Timing Pins Dedicated Ramp Timing Registers Register Name Register Address Remarks START_CONF 0x02 RW The configuration register of the synchronization unit. START_OUT_ADD 0x11 RW Additional active output length of external start signal. START_DELAY 0x13 RW Delay time between start triggers and start signal. X_PIPE0… 7 0x38…0x3F RW Target positions pipeline and/or parameter pipeline. SH_REG0…12 0x40…0x4C RW Shadow register set Table 30: Dedicated Ramp Timing Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 70/230 Basic Synchronization Settings Usually, a ramp can be initiated internally or externally. Note that a start trigger is not the start signal itself but the transition slope to the active start state. After a defined delay, the internal start signal is generated. Start Signal Trigger Selection For ramp start configuration, consider the following steps: Action:  Choose internal or external start trigger(s).  Set the triggers according to the table below. i All triggers can be used separately or in combination. Start Trigger Configuration Table trigger_events = START_CONF(8:5) Result b’0000 No start signal will be generated or processed further. b’xxx0 b’xxx1 Set trigger_events(0) = 0 for internal start triggers only. The internally generated start signal is forwarded to the START pin that is assigned as output. Set trigger_events(0) = 1 for an external start trigger. The START pin is assigned as input. For START input take filter settings into consideration. See chapter 4, page 20. b’xx1x TARGET_REACHED event is assigned as start signal trigger for the ramp timer. b’x1xx VELOCITY_REACHED event is assigned as start signal trigger for the ramp timer. b’1xxx POSCOMP_REACHED event is assigned as start signal trigger for the ramp timer. Table 31: Start Trigger Configuration User-specified Impact Configuration of Timing Procedure Per default, every SPI datagram is processed immediately. By selecting one of the following enable switches, the assignment of SPI requests to registers XTARGET, VMAX, RAMP_MODE, and GEAR_RATIO is uncoupled from the SPI transfer. The value assignment is only processed after an internally generated start signal. In order to influence the impact of the start signal on internal parameter assignments, do the following: Action:  Choose between the following options as shown in the table below. Start Enable Switch Configuration Table (All switches can be used separately or in combination.) start_en = START_CONF(4:0) Result b’xxxx1 XTARGET is altered only after an internally generated start signal. b’xxx1x VMAX is altered only after an internally generated start signal. b’xx1xx RAMPMODE is altered only after an internally generated start signal. b’x1xxx GEAR_RATIO is altered only after an internally generated start signal. b’1xxxx Shadow register is assigned as active ramp parameters after an internally generated start signal. This is explained in more detail in section 9.2. (page 75). Table 32: Start Enable Switch Configuration © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 71/230 Per default, the trigger is closely followed by the internal start signal. Delay Definition between Trigger and internally generated Start Signal In order to delay the generation of the internal start signal, do the following: Action:  Set START_DELAY register 0x13 according to your specification. Result: When a start trigger is recognized, the internal start signal is generated after START_DELAY clock cycles. Prioritizing External Input Per default, an external trigger is also delayed for the internal start signal generation. In order to immediately prompt an external start, trigger to an internally generated start signal (regardless of a defined delay), do the following: Action:  Set immediate_start_in = 1 (START_CONF register 0x02). Result: When an external start trigger is recognized, the internal start signal is generated immediately, even if the internal start triggers have already initiated a timing process with an active delay. START Pin Polarity The START pin can be used either as input or as output pin. However, the active voltage level polarity of the START pin can be selected with one configuration switch in the START_CONF register 0x02. Per default, the voltage level transition from high to low triggers a start signal (START is an input), or START output indicates an active START event by switching from high to low level. In order to invert active START polarity, do as follows: Action:  Set pol_start_signal = 1 (START_CONF register 0x02). Result: The START pin is high active. The voltage level transition from low to high triggers a start signal (START is an input), or START output indicates an active START event by switching from low to high level. Per default, the active output voltage level of the START pin lasts one clock cycle. Active START Pin Output Configuration In order to extend this time span, do the following: Condition:  START pin is assigned as output: trigger_events(0) = 1. Action:  Set START_OUT_ADD register 0x11 according to your specification. Result: The active voltage level lasts (START_OUT_ADD + 1) clock cycles. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 72/230 The following three examples depict SPI datagrams, internal and external signal levels, corresponding velocity ramps, and additional explanations. SPI data is transferred internally at the end of each datagram. Ramp Timing Examples Ramp Timing Example 1 In this example, the velocity value change is executed immediately. Process Description     The new XTARGET value is assigned after TARGET_REACHED has been set and START_DELAY has elapsed. A new ramp does not start at the end of the second ramp because no new XTARGET value is assigned. START is an output. Internal start signal forwards with a step length of (START_OUT_ADD + 1) clock cycles. This is how external devices can be synchronized: Parameter Settings Timing Example 1 Parameter Setting RAMPMODE b’101 start_en b’00001 trigger_events b’0010 START_DELAY >0 START_OUT_ADD >0 pol_start_signal 1 Table 33: Parameter Settings Timing Example 1 SPI VMAX =2000 XTARGET =2000 v(t) 2000 XACTUAL=2000 XACTUAL=1800 1000 trigger event t trigger event TARGET_REACHED VMAX_REACHED START_DELAY internal start timer START_DELAY internal start signal START START_OUT_ADD START_OUT_ADD Figure 34: Ramp Timing Example 1 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Ramp Timing Example 2 73/230 In this example, the velocity value and the ramp mode value change is executed after the first start signal.   Process Description The new ramp mode becomes positioning mode with S-shaped ramps. The ramp then stops at target position XTARGET because of the ramp mode change. A further XTARGET change starts the ramp again. The ramp is initiated as soon as the start delay is completed, which was triggered by the first TARGET_REACHED event. The active START output signal lasts only one clock cycle.    Parameter Settings Timing Example 2 Parameter Setting RAMPMODE b’001  b’110 start_en b’00111 trigger_events b’0110 START_DELAY >0 START_OUT_ADD 0 pol_start_signal 0 Table 34: Parameter Settings Timing Example 2 SPI XTARGET =2000 VMAX =1000 RAMPMODE =110 VMAX =2250 XTARGET =2000 v(t) 2000 1000 XACTUAL=2000 t trigger event TARGET_REACHED trigger event trigger event VMAX_REACHED internal start timer START_DELAY START_DELAY internal start signal START Figure 35: Ramp Timing Example 2 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Ramp Timing Example 3 74/230 In this example external start signal triggers are prioritized by making use of START_DELAY > 0 and simultaneously setting immediate_start_in to 1.  Process Description  When XACTUAL equals POSCOMP the start timer is activated and the external start signal in between is ignored. The second start event is triggered by an external start signal. The POSCOMP_REACHED event is ignored. The third start timer process is disrupted by the external START signal, which is forced to be executed immediately due to the setting of: immediate_start_in = 1. Parameter Settings Timing Example 3 Parameter Setting RAMPMODE b’000 start_en b’00010 trigger_events b’1001 immediate_start_in 01 START_DELAY >0 pol_start_signal 1 Table 35: Parameter Settings Timing Example 3 SPI VMAX = -1000 VMAX =250 VMAX =1000 immediate_start_in =1 VMAX = -250 START v(t) ignored trigger event due to ongoing start timer trigger event trigger event 1000 t XACTUAL=POSCOMP XACTUAL=POSCOMP -1000 ignored trigger event due to ongoing start timer trigger event POSCOMP_REACHED internal start timer START_DELAY START_DELAY internal start signal Figure 36: Ramp Timing Example 3 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  trigger event TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 75/230 Shadow Register Settings Some applications require a complete new ramp parameter set for a specific ramp situation / point in time. TMC4361A provides up to 14 shadow registers, which are loaded into the corresponding ramp parameter registers after an internal start signal is generated. Enabling Shadow Registers In order to enable shadow registers, do as follows: Action  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02), see section 9.1.2 (page 70). Result: With every successive internal start signal the shadow registers are loaded into the corresponding active ramp register. Enabling Cyclic Shadow Registers It is also possible to write back the current motion profile into the shadow motion registers to swap ramp motion profiles continually. In order to enable cyclic shadow registers, do as follows: Action  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02) , see section 9.1.2 (page 70).  Set cyclic_shadow_regs = 1 (START_CONF register 0x02). Result: With every successive internal start signal the shadow registers are loaded into the corresponding active ramp register, whereas the active motion profile is loaded into the shadow registers.  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Shadow Register Configuration Options Option 1: Shadow Default Configuration 76/230 Four different optional shadow register assignments are available to match the shadow register set according to your selected ramp type. The available options are described on the next pages. Please note that the only difference between the configuration of shadow option 3 and 4 is that VSTART is exchanged by VSTOP for the transfer of the shadow registers. i If the whole ramp register is needed to set in a single level stack, do as follows: Action:  Set shadow_option = b’00 (START_CONF register 0x02).  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02) Action:  Default configuration: Set cyclic_shadow_regs = 0 (START_CONF register 0x02)  Optional configuration: Set cyclic_shadow_regs = 1 (START_CONF register 0x02) Result: Every relevant motion parameter is altered at the next internal start signal by the corresponding shadow register parameter. In case cyclic shadow registers are used, the shadow register set is altered by the current motion profile set. 20 24 25 26 27 28 29 2A 2B 2D 2E 2F 30 RAMPMODE VMAX VSTART VSTOP VBREAK AMAX DMAX ASTART DFINAL BOW1 BOW2 BOW3 BOW4 4C 40 46 47 45 41 42 43 44 48 49 4A 4B SH_REG12 SH_REG0 SH_REG6 SH_REG7 SH_REG5 SH_REG1 SH_REG2 SH_REG3 SH_REG4 SH_REG8 SH_REG9 SH_REG10 SH_REG11 20 24 25 26 27 28 29 2A 2B 2D 2E 2F 30 RAMPMODE VMAX VSTART VSTOP VBREAK AMAX DMAX ASTART DFINAL BOW1 BOW2 BOW3 BOW4 4C 40 46 47 45 41 42 43 44 48 49 4A 4B SH_REG12 SH_REG0 SH_REG6 SH_REG7 SH_REG5 SH_REG1 SH_REG2 SH_REG3 SH_REG4 SH_REG8 SH_REG9 SH_REG10 SH_REG11 Caption xx XXXX Register address Register name cyclic_shadow_reg=0 cyclic_shadow_reg=1 Figure 37: Single-level Shadow Register Option to replace complete Ramp Motion Profile. i i AREAS OF SPECIAL CONCERN ! Green arrows show default settings Blue arrows show optional settings. In case an S-shaped ramp type is selected and operation mode is switched from velocity to positioning mode (triggered by shadow register transfer), SH_REG10 must not be equal to BOW3; to ensure safe operation mode switching.  On the following pages more options are explained. Pleae turn page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Option 2: Double-stage Shadow Register Set for S-shaped Ramps 77/230 In case S-shaped ramps are configured, a double-stage shadow register set can be used. Seven relevant motion parameters for S-shaped ramps are affected when the shadow registers become active. In order to use a double-stage shadow register pipeline for S-shaped ramps, do as follows: Action:  Set shadow_option = b’01 (START_CONF register 0x02).  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02). Action:  Default configuration: Set cyclic_shadow_regs = 0 (START_CONF register 0x02).  Optional configuration: Set cyclic_shadow_regs =1 (START_CONF register 0x02) Result: Seven motion parameters (VMAX, AMAX, DMAX, BOW1...4) are altered at the next internal start signal by the corresponding shadow register parameters (SH_REG0...6). Simultaneously, these shadow registers are exchanged with the parameters of the second shadow stage (SH_REG7…13). In case cyclic shadow registers are used, the second shadow register set (SH_REG7…13) is altered by the current motion profile set, e.g. 0x28 (AMAX) is written back to 0x48 (SH_REG8). The other ramp registers remain unaltered. 20 24 25 26 27 28 29 2A 2B 2D 2E 2F 30 RAMPMODE VMAX VSTART VSTOP VBREAK AMAX DMAX ASTART DFINAL BOW1 BOW2 BOW3 BOW4 40 SH_REG0 47 SH_REG7 41 SH_REG1 42 SH_REG2 48 SH_REG8 49 SH_REG9 43 44 45 46 4A 4B 4C 4D SH_REG3 SH_REG4 SH_REG5 SH_REG6 SH_REG10 SH_REG11 SH_REG12 SH_REG13 Caption xx XXXX Register address Register name start_en(4)=1 cyclic_shadow_reg=1 Figure 38: Double-stage Shadow Register Option 1, suitable for S-shaped Ramps. i i Green arrows show default settings Blue arrows show optional settings.  Description is continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Option 3: Double-stage Shadow Register Set for Trapezoidal Ramps (VSTART) 78/230 In case trapezoidal ramps are configured, a double-stage shadow register set can be used. Seven relevant motion parameters for trapezoidal ramps are affected when the shadow registers become active. In order to use a double-stage shadow register pipeline for trapezoidal ramps, do as follows: Action:  Set shadow_option = b’10 (START_CONF register 0x02).  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02) Action:  Default configuration: Set cyclic_shadow_regs = 0 (START_CONF register 0x02).  Optional configuration: Set cyclic_shadow_regs = 1 (START_CONF register 0x02). Result: Seven motion parameters (VMAX, AMAX, DMAX, ASTART, DFINAL, VBREAK, and VSTART) are altered at the next internal start signal by the corresponding shadow register parameters (SH_REG0...6). Simultaneously, these shadow registers are exchanged with the parameters of the second shadow stage ( SH_REG7…13). If cyclic shadow registers are used, the second shadow register set ( SH_REG7…13) is altered by the current motion profile set, e.g. 0x27 (VBREAK) is written back to 0x4C (SH_REG12). The other ramp registers remain unaltered. 20 24 25 26 27 28 29 2A 2B 2D 2E 2F 30 RAMPMODE VMAX VSTART VSTOP VBREAK AMAX DMAX ASTART DFINAL BOW1 BOW2 BOW3 BOW4 40 SH_REG0 46 SH_REG6 47 SH_REG7 4D SH_REG13 45 41 42 43 44 4C 48 49 4A 4B SH_REG5 SH_REG1 SH_REG2 SH_REG3 SH_REG4 SH_REG12 SH_REG8 SH_REG9 SH_REG10 SH_REG11 Caption xx XXXX Register address Register name start_en(4)=1 cyclic_shadow_reg=1 Figure 39: Double-stage Shadow Register Option 2, suitable for Trapezoidal Ramps. i i Green arrows show default settings. Blue arrows show optional settings.  Description is continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Option 4: Double-stage Shadow Register Set for Trapezoidal Ramps (VSTOP) 79/230 In case trapezoidal ramps are configured, a double-stage shadow register set can be used. Seven relevant motion parameters for trapezoidal ramps are affected when the shadow registers become active. In order to use a double-stage shadow register pipeline for trapezoidal ramps, do as follows: Action:  Set shadow_option = b’10 (START_CONF register 0x02).  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02) Action:  Default configuration: Set cyclic_shadow_regs = 0 (START_CONF register 0x02).  Optional configuration: Set cyclic_shadow_regs = 1 (START_CONF register 0x02) Result: Seven motion parameters (VMAX, AMAX, DMAX, ASTART, DFINAL, VBREAK, and VSTOP) are altered at the next internal start signal by the corresponding shadow register parameters (SH_REG0...6). Simultaneously, these shadow registers are exchanged with the parameters of the second shadow stage ( SH_REG7…13). If cyclic shadow registers are used, the second shadow register set ( SH_REG7…13) is altered by the current motion profile set, e.g. 0x26 ( VSTOP) is written back to 0x4D (SH_REG13). The other ramp registers remain unaltered. 20 24 25 26 27 28 29 2A 2B 2D 2E 2F 30 RAMPMODE VMAX VSTART VSTOP VBREAK AMAX DMAX ASTART DFINAL BOW1 BOW2 BOW3 BOW4 40 SH_REG0 47 SH_REG7 46 45 41 42 43 44 4D 4C 48 49 4A 4B SH_REG6 SH_REG5 SH_REG1 SH_REG2 SH_REG3 SH_REG4 SH_REG13 SH_REG12 SH_REG8 SH_REG9 SH_REG10 SH_REG11 Caption xx XXXX Register address Register name start_en(4)=1 cyclic_shadow_reg=1 Figure 40: Double-Stage Shadow Register Option 3, suitable for Trapezoidal Ramps i i Green arrows show default settings. Blue Arrows show optional settings.  Turn page to see Areas of Special Concern pertaining to this section. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 AREAS OF SPECIAL CONCERN ! Delayed Shadow Transfer 80/230 The values of ramp parameters, which are not selected by one of the four shadow options stay as originally configured, until the register is changed through an SPI write request. Also, the last stage of the shadow register pipeline retains the values until they are overwritten by an SPI write request if no cyclic shadow registers are selected. Up to 15 internal start signals can be skipped before the shadow register transfer is executed. In order to skip a defined number of internal start signals for the shadow transfer, do as follows: Action:  Set shadow_option according to your specification.  Set start_en(4) = 1 and select one or more trigger_events (START_CONF register 0x02)  OPTIONAL CONFIGURATION: Set cyclic_shadow_regs = 1.  Set SHADOW_MISS_CNT ≠ 0 (START_CONF register 0x02) according to the number of consecutive internal start signals that you specify to be ignored. Result: The shadow register transfer is not executed with every internal start signal. Instead, the specified number of start signals is ignored until the shadow transfer is executed through the (SHADOW_MISS_CNT+1)th start signal. The following figure shows an example of how to make use of SHADOW_MISS_CNT, in which the shadow register transfer is illustrated by an internal signal sh_reg_transfer. The signal miss counter CURRENT_MISS_CNT can be read out at register address START_CONF (23:20): SPI shadow_miss_cnt =0 shadow_miss_cnt =5 shadow_miss_cnt =2 internal start signal sh_reg_transfer current_miss_cnt 0 1 2 3 4 5 0 1 2 0 1 2 0 1 Figure 41: SHADOW_MISS_CNT Parameter for several internal Start Signals AREAS OF SPECIAL CONCERN ! Internal calculations to transfer the requested shadow BOW values into internal structures require at most (320 / fCLK) [sec]. before any shadow register transfer is prompted, it is necessary to wait for the completion of all internal calculations for the shadow bow parameters. In order to make this better understood the following example is provided for a double-stage shadow pipeline for S-shaped ramps: PRECONDITION: Shadow register transfer is activated (start_en(1) = 1 and one or more trigger_events are selected) for S-shaped ramps (shadow_option = b’01) Action  Set SH_REG0, SH_REG1, SH_REG2 (shadow register for VMAX, AMAX, DMAX).  Set SH_REG3, SH_REG4, SH_REG5, SH_REG6 (shadow register for BOW1…4).  Ensure that no shadow register transfer occurs during the next 320 / fCLK [s]. Result: Shadow register transfer can be initiated after this time span. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 81/230 Pipelining Internal Parameters TMC4361A provides a target pipeline for sequencing subordinate targets in order to easily arrange a complex target structure. Configuration and Activation of Target Pipeline The different target values must be assigned to the X_PIPE0…7 register. If the target pipeline is enabled, a new assignment cycle is initiated as soon as an internal start signal is generated; moving the values, as described, simultaneously: PROCESS DESCRIPTION:  A new XTARGET value is assigned that takes over the value of X_PIPE0.  Every X_PIPEn register takes over the value of its successor: X_PIPEn = X_PIPEn+1 In order to activate the target pipeline, do as follows: Action:  Set pipeline_en = b’0001 (START_CONF register 0x02). Result: The above mentioned process description is executed with every new internal start signal prompting. Configuration of a cyclic Target Pipeline It is also possible to reassign the value of XTARGET to one (or more) of the pipeline registers X_PIPE0…7. Thereby, a cyclic target pipeline is created. In order to enable a cyclic target pipeline, do as follows: Action:  Set pipeline_en = b’0001 (START_CONF register 0x02).  Set XPIPE_REWRITE_REG in relation to the pipeline register where XTARGET have to written back (e.g. XPIPE_REWRITE_REG = b’00010000). Result: The above mentioned process description is executed with every new internal start signal prompting, and XTARGET is written back to the selected X_PIPEx register (e.g. XPIPE_REWRITE_REG = 0x10  XTARGET is written back to X_PIPE4). The processes and actions described on the previous page, are depicted in the following figure. The assignment cycle that is initiated when an internal start signal occurs is depicted. 37 XTARGET XPIPE_REWRITE_REG(0) = '1' 38 X_PIPE0 XPIPE_REWRITE_REG(1) = '1' 39 X_PIPE1 XPIPE_REWRITE_REG(2) = '1' 3A X_PIPE2 XPIPE_REWRITE_REG(3) = '1' 3B X_PIPE3 Caption XPIPE_REWRITE_REG(4) = '1' 3C X_PIPE4 XPIPE_REWRITE_REG(5) = '1' 3D X_PIPE5 XPIPE_REWRITE_REG(6) = '1' 3E X_PIPE6 XPIPE_REWRITE_REG(7) = '1' 3F X_PIPE7 XX XXXX Register Register name address Figure 42: Target Pipeline with Configuration Options © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  pipeline_en = b’0001 pipeline_en = b’0001 X_PIPE_REWRITE_REG ≠ 0 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Using the Pipeline for different internal Registers 82/230 The TMC4361A pipeline (registers 0x38…0x3F) can be configured so that it splits up into maximal four segments. These segments can be used to feed the following internal parameters:     XTARGET register 0x37 POS_COMP register 0x32 GEAR_RATIO register 0x12 GENERAL_CONF 0x00 Consequently, these definite parameter value changes can be of importance concerning a continuous ramp motion and/or for reduced overhead synchronizing of several motion controllers. The POS_COMP value can be used to initiate a start signal generation during motion. Therefore, it can be useful to pipeline this parameter in order to avoid dependence on SPI transfer speed. For instance, if the distance between two POS_COMP values is very close and the current velocity is high enough that it misses the second value before the SPI transfer is finished, it is advisable to change POS_COMP immediately after the start signal. The same is true for the GEAR_RATIO parameter, which defines the step response on incoming step impulses. Some applications require very quick gear factor alteration of the slave controller. Note that when the start signal is prompted directly, an immediate change can be very useful instead of altering the parameter by an SPI transfer. Likewise, it can (but must not) be essential to change general configuration parameters at a defined point in time. A suitable application is a clearly defined transfer from a direct external control (sd_in_mode = b’01) to an internal ramp (sd_in_mode = b’00) or vice versa because in this case the master/slave relationship is interchanged. The following pipeline options are available, which can be adjusted accordingly: Pipeline Activation Options pipeline_en(3:0) Description b’xxx1 Pipeline for XTARGET is enabled. b’xx1x Pipeline for POS_COMP is enabled. b’x1xx Pipeline for GEAR_RATIO is enabled. b’1xxx Pipeline for GENERAL_CONF is enabled. Table 36: Pipeline Activation Options © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Pipeline Mapping Overview 83/230 The pipeline_en parameter offers an open configuration for 16 different combinations of the pipeline segregation. As a result, the number of pipelines range from 0 to 4. This also has an impact on the pipeline depth. The possible options are as follows: eight stages, four stages, three stages and two stages. In the “Pipeline Mapping” table below, the allocated according to the pipeline setup. registers are also depicted in order to (X_PIPE0…7) the final target registers GENERAL_CONF) are fed. arrangement and depth of the pipeline is The final register destination of pipeline illustrate from which pipeline registers (XTARGET, POS_COMP, GEAR_RATIO, For example, if POS_COMP and GEAR_RATIO are chosen as parameters that are to be fed by the pipeline, two 4-stage pipelines are created. When an internal start signal is generated, POS_COMP assumes the value of X_PIPE0, whereas X_PIPE4 feeds the GEAR_RATIO register. But if POS_COMP, GEAR_RATIO and XTARGET are selected as parameter destinations, two 3-stage pipelines and one double-stage pipeline are created. When an internal start signal is generated, XTARGET assumes the value of X_PIPE0, POS_COMP assumes the value of X_PIPE3, whereas X_PIPE6 feeds the GEAR_RATIO register. Pipeline Mapping Table More examples are described in detail on the following pages - explaining some of the possible configurations and referencing examples - listed in the Table below. Pipeline Mapping Ex. pipeline_en (3:0) Arrangement No Pipelining Final transfer register for… GENERAL_CONF GEAR_RATIO POS_COMP XTARGET pipeline_en(3) pipeline_en(2) pipeline_en(1) pipeline_en(0) - - - - - - - X_PIPE0 - - X_PIPE0 - - X_PIPE0 - - - b’0000 - b’0001 A b’0010 B b’0100 - b’1000 X_PIPE0 - - - C b’0011 - - X_PIPE4 X_PIPE0 - b’0101 - X_PIPE4 - X_PIPE0 - b’1001 X_PIPE4 - - X_PIPE0 - b’0110 - X_PIPE4 X_PIPE0 - - b’1010 X_PIPE4 - X_PIPE0 - D b’1100 X_PIPE4 X_PIPE0 - - F b’0111 - X_PIPE6 X_PIPE3 X_PIPE0 - b’1011 X_PIPE6 - X_PIPE3 X_PIPE0 E b’1101 X_PIPE6 X_PIPE3 - X_PIPE0 - b’1110 X_PIPE6 X_PIPE3 X_PIPE0 - G/H b’1111 X_PIPE6 X_PIPE4 X_PIPE2 X_PIPE0 One 8-stage pipeline Two 4-stage pipelines Two 3-stage pipelines and one double-stage pipeline Four doublestage pipelines Table 37: Pipeline Mapping for different Pipeline Configurations © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Cyclic Pipelining 84/230 For all of the above shown configuration examples, it is possible to write back the current values of the selected registers (XTARGET, POS_COMP, GEAR_RATIO and/or GENERAL_CONF) to any of the pipeline registers of their assigned pipeline in order to generate cyclic pipelines. By selecting proper XPIPE_REWRITE_REG, the value that is written back to the pipeline register is selected automatically to fit the selected pipeline mapping. Below, several pipeline mapping examples with the corresponding configuration are shown. Pipeline Examples Example A: Cyclic pipeline for POS_COMP, which has eight pipeline stages. Examples A+B: Using one Pipeline Example B: Cyclic pipeline for GEAR_RATIO, which has six pipeline stages. A B 12 GEAR_RATIO 32 POS_COMP 38 X_PIPE0 x_pipe_rewrite_reg(7) = b’00100000 38 X_PIPE0 39 X_PIPE1 3A X_PIPE2 3B X_PIPE3 3C X_PIPE4 39 X_PIPE1 3A X_PIPE2 3B X_PIPE3 3C X_PIPE4 3D X_PIPE5 3D X_PIPE5 3E X_PIPE6 3E X_PIPE6 3F X_PIPE7 3F X_PIPE7 pipline_en=b’0010 XPIPE_REWRITE_REG=b’10000000 pipline_en=b’0100 XPIPE_REWRITE_REG=b’00100000 Figure 43: Pipeline Example A Examples C+D: Using two Pipelines Figure 44: Pipeline Example B Example C: Cyclic pipelines for XTARGET and POS_COMP, which have four pipeline stages each. Example D: Cyclic pipelines for GEAR_RATIO, which has three pipeline stages and GENERAL_CONF, which has two pipeline stages. C D 37 XTARGET 12 GEAR_RATIO 38 X_PIPE0 38 X_PIPE0 39 X_PIPE1 39 X_PIPE1 3A X_PIPE2 3A X_PIPE2 3B X_PIPE3 3B X_PIPE3 32 POS_COMP 10 GENERAL_CONF 3C X_PIPE4 3C X_PIPE4 3D X_PIPE5 3D X_PIPE5 3E X_PIPE6 3E X_PIPE6 3F X_PIPE7 3F X_PIPE7 pipline_en=b’1100 XPIPE_REWRITE_REG=b’00100100 pipline_en=b’0011 XPIPE_REWRITE_REG=b’10001000 Figure 45: Pipeline Example C Figure 46: Pipeline Example D © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 85/230 Example E: Cyclic pipelines for XTARGET and GEAR_RATIO, which have three pipeline stages each and GENERAL_CONF, which has two pipeline stages. Examples E+F: Using three Pipelines Example F: Two cyclic pipelines for XTARGET and GEAR_RATIO, which have two pipeline stages each and a noncyclic pipeline for GEAR_RATIO, which has three pipeline stages. E F 37 XTARGET 37 XTARGET 38 X_PIPE0 38 X_PIPE0 39 X_PIPE1 39 X_PIPE1 3A X_PIPE2 3A X_PIPE2 32 POS_COMP 12 GEAR_RATIO 3B X_PIPE3 3B X_PIPE3 3C X_PIPE4 3C X_PIPE4 3D X_PIPE5 3D X_PIPE5 12 GEAR_RATIO 10 GENERAL_CONF 3E X_PIPE6 3E X_PIPE6 3F X_PIPE7 3F X_PIPE7 pipline_en=b’1101 XPIPE_REWRITE_REG=b’10100100 pipline_en=b’0111 XPIPE_REWRITE_REG=b’10000010 Figure 47: Pipeline Example E Examples G+H: Using four Pipelines Figure 48: Pipeline Example F Example G: Cyclic pipelines for XTARGET, POS_COMP, GEAR_RATIO and GENERAL_CONF, which have two pipeline stages each. Example H: Four noncyclic pipelines for XTARGET, POS_COMP, GEAR_RATIO and GENERAL_CONF, which have two pipeline stages each. G H 37 XTARGET 37 XTARGET 38 X_PIPE0 38 X_PIPE0 39 X_PIPE1 39 X_PIPE1 32 POS_COMP 32 POS_COMP 3A X_PIPE2 3A X_PIPE2 3B X_PIPE3 3B X_PIPE3 12 GEAR_RATIO 12 GEAR_RATIO 3C X_PIPE4 3C X_PIPE4 3D X_PIPE5 3D X_PIPE5 10 GENERAL_CONF 10 GENERAL_CONF 3E X_PIPE6 3E X_PIPE6 3F X_PIPE7 3F X_PIPE7 pipline_en=b’1111 XPIPE_REWRITE_REG=b’10101010 pipline_en=b’1111 XPIPE_REWRITE_REG=b’00000000 Figure 49: Pipeline Example G Figure 50: Pipeline Example H © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 86/230 Masterless Synchronization of Several Motion Controllers via START Pin START pin can also be assigned as tristate input in order to synchronize several microcontroller masterless. Activation of the Tristate START Pin In this case START is assigned as tristate. A busy state is enabled. During this busy state, START is set as output with a strongly driven inactive polarity. If the internal start signal is generated – after the internal start timer is expired –START pin is assigned as input. Additionally, a weak output signal is forwarded at START. During this phase, the active start polarity is emitted. In case the signal at START input is set to active polarity, because all members of the signal line are ready, START output remains active (strong driving strength) for START_OUT_ADD clock cycles. Then, busy state is active again until the next start signal occurs. In order to activate tristate START pin, do as follows: Action:  Set busy_en = 1 (START_CONF register 0x02). Result: The above mentioned process description is executed. START Pin Connection In case START pin is connected with START pins of other TMC4361A devices, it is recommend that a series resistor (e.g. 220 Ω) is connected between the devices to limit the short circuit current flowing that can flow during the configuration phase when different voltage levels at the START pins of the different devices can occur. NOTE:  Avoid that short circuits last too long. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 87/230 10. Serial Data Output TMC4361A provides an SPI interface for initialization and configuration of the motor driver (in addition to the Step/Dir output) before and during motor motion. It is possible to control TMC stepper drivers during SPI motor drive. SPI Interface Configuration The SPI interface is used for the following tasks:    TMC4361A integrates an adjustable cover register for configuration purposes in order to adjust TMC motor driver chips and third parties chips easily. The integrated microstep Sine Wave Lookup Table (MSLUT) generates two current values that represent sine and cosine values. These two current values can be transferred to a TMC motor driver chip at a time, in order to energize the motor coils. This occurs within each SPI datagram. A series of current values is transferred to move the motor. Values of the MSLUT are adjusted using velocity ramp dependent scale values that align the maximum amplitude current values to the requirements of certain velocity slopes. Pin Names for SPI Motor Drive Pin Names Type Remarks NSCSDRV_SDO Output Chip select output to motor driver, low active. SCKDRV_NSDO Output Serial clock output to motor driver. SDODRV_SCLK InOut as Output Serial data output to motor driver. SDIDRV_NSCLK Input Serial data input from motor driver. STDBY_CLK Output Clock output, standby output, or ChopSync clock output. Table 38: Pin Names for SPI Motor Drive Register Names for SPI Output Registers Register Name Register Address Remarks GENERAL_CONF 0x00 RW Affect switches: Bit14:13, bit19, bit20, bit28. REFERENCE_CONF 0x01 RW Affect switches: Bit26, bit27, bit30. SPIOUT_CONF 0x04 RW Configuration register for SPI output communication. STEP_CONF 0x0A RW 0x1D RW DAC_ADDR SPI_SWITCH_VEL Microsteps per fullstep, fullsteps per revolution, and motor status bit event selection. SPI addresses/commands which are put in front of the DAC values: CoilA: DAC_ADDR(15:0), CoilB: DAC_ADDR(31:16) Velocity at which automatic cover datagrams are sent. CHOPSYNC_DIV 0x1F RW FS_VEL 0x60 W Velocity at which fullstep drive are enabled. COVER_LOW 0x6C W Lower 32 bits of the cover register (µC to motor driver). COVER_HIGH 0x6D W Upper 32 bits of the cover register (µC to motor driver). COVER_DRV_LOW 0x6E R COVER_DRV_HIGH 0x6F R CURRENT_CONF 0x05 RW Current scaling configuration. SCALE_VALUES 0x06 RW Current scaling values. STDBY_DELAY 0x15 RW Delay time after standby mode is valid. Chopper clock divider (bit 11:0). Lower 32 bits of the cover response register (motor driver to µC). Upper 32 bits of the cover response register (motor driver to µC). © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 88/230 Register Names for SPI Output Registers Register Name Register Address Remarks FREEWHEEL_DELAY 0x16 RW Delay time after freewheeling is valid. VDRV_SCALE_LIMIT 0x17 RW Velocity setting for changing the drive scale value. UP_SCALE_DELAY 0x18 RW Increment delay to a higher scaling value; 24 bits. HOLD_SCALE_DELAY 0x19 RW Decrement delay to the hold scaling value; 24 bits. DRV_SCALE_DELAY 0x1A RW Decrement delay to the drive scaling value. BOOST_TIME 0x1B RW Delay time after ramp start when boost scaling is valid. SCALE_PARAM CURRENTA CURRENTB CURRENTA_SPI CURRENTB_SPI MSLUT registers 0x7C R 0x7A R 0x7B R 0x70…78 W MSLUT values definitions. 0x79 R Actual microstep position of the MSLUT. 0x7E RW MSCNT START_SIN START_SIN90_120 DAC_OFFSET Actual current scaling parameter; 8 bits. Actual current values of the MSLUT: SIN (coil A) and SIN90_120 (coil B); 9 bit for each. Actual scaled current values of the MSLUT: SIN (coil A) and SIN90_120 (coil B); 9 bits for each. Sine start value of the MSLUT Cosine start value of the MSLUT Offset value for DAC output values (bit7:0). (bit23:16). (bit31:24). Table 39: Dedicated SPI Output Registers Getting Started with TMC Motor Drivers In this chapter information is provided about how to easily start up a connected TMC motor driver. Setting up SPIOUT_CONF correctly In order to start up a connected TMC motor stepper driver, proper setup of SPIOUT_CONF register 0x04 is important. TMC4361A offers presets for current transfer and automatic configuration routines if the correct TMC driver is selected. Status bits of TMC motor drivers are also transmitted to the status register of the motion controller. TMC4361A provides a programmable lookup table for storing the current wave. Per default, the tables are preprogrammed with a sine wave, which is a good starting point for most stepper motors. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 89/230 Sine Wave Lookup Tables TMC4361A provides a programmable lookup table (LUT) for storing the current wave. Reprogramming the table from its predefined values to a motor-specific wave allows improved motor-reliant microstepping, particularly when using low-cost motors. SETTINGS ALERT ! TMC4361A-LA provides a default configuration of the internal microstep table MSLUT. In case internal MSLUT is used, proceed with section 10.3. (page 95) in order to setup a well-defined serial data connection to the stepper motor driver. The following explanations that are provided in this section only address engineers who use their own microstep table definition. Programming Sine Wave Lookup Tables The internal microstep wave table maps the microstep wave from 0° to 90° for 256 microsteps. It becomes automatically and symmetrically extended to 360° that consequently comprises 1024 microsteps. As a result, the microstep counter MSCNT ranges from 0 to 1023. Only a quarter of the wave is stored because this minimizes required memory and the amount of programmable data. Therefore, only 256 bits (ofs00 to ofs255) are required to store the quarter wave. These bits are mapped to eight 32-bit registers MSLUT[0] (register 0x70) to MSLUT[7] (register 0x77). When reading out the table the 10-bit microstep counter MSCNT addresses the fully extended wave table. Sine Wave Table Structure The MSLUT is an incremental table. This means that a certain order and succession is predefined at every next step based on the value before, using up to four flexible programmable segments within the quarter wave. The microstep limits of the four segments are controlled by the position registers X1, X2, and X3. Within these segments the next value of the MSLUT is calculated by adding the base wave inclination Wx-1 (if ofs=0) or its successor Wx (if ofs=1). Because four segments are programmable, four base wave inclinations are available as basic increment value: 0, 1, 2, or 3. Thereby, even a negative wave inclination can be realized. This is shown in the next Figure where the values in last quarter segments are decreased or remain constant with every step towards MSCNT= 255. W3: -1/+0 W2: +0/+1 W1: +1/+2 W0: +2/+3 y 256 248 START_SIN90_120 0 X1 X2 X3 LUT stores entries 0 to 255 255 256 512 768 START_SIN -248 Figure 51: LUT Programming Example © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  0 MSCNT TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 90/230 Actual Current Values Output Actual Current Calculations When the microstep sequencer advances within the microstep table (MSLUT), it calculates the actual current values for the motor coils with each microstep, and stores them to the register 0x7A , which comprises the values of both waves CURRENTA and CURRENTB. However, the incremental coding requires an absolute initialization – especially when the microstep table becomes modified. Therefore, CURRENTA and CURRENTB become re-initialized with the start values whenever MSCNT passes zero. Characteristics of a 2-phase Stepper Motor Microstep Table As mentioned above, the MSLUT can be adapted to the motor requirements. In order to understand the nature of incremental coding of the microstep table, the characteristics of the microstep wave must be understood, as described in the list below: Characteristics of a 2-phase motor microstep table:       In principle, it is a reverse characteristic of the motor pole behavior. It is a polished wave to provide a smooth motor behavior. There are no jumps within the wave. The phase shift between both phases is exactly 90°, because this is the optimum angle of the poles inside the motor. The zero transition is at 0°. The curve is symmetrical within each quadrant (like a sine wave). The slope of the wave is normally positive, but due to torque variations it can also be (slightly) negative. But it must not be strictly monotonic as shown in the figure above. Considering these facts, it becomes clear that the wave table can be compressed. The incremental coding applied to the TMC4361A uses a format that reduces the required information - per entry of the 8-bit by a 256-entry wave table - to slightly more than a single bit. How to Program the Internal MSLUT Principle of Incremental Encoding The principle of incremental encoding only stores the difference between the actual and the next table entry. In order to attain an absolute start value, the first entry is directly stored in START_SIN. Also, for ease-of-use, the first entry of the shifted table for the second motor phase is stored in START_SIN_90_120. Based on these start values, every next table entry is calculated by adding an increment INC to the former value. This increment is the base wave inclination value Wx whenever its corresponding ofs bit is 1 or Wx – 1 if ofs = 0: INC = Wx + (ofs – 1). The base wave inclination can be set to four different values (0, 1, 2, 3), because it consists of two bits. Because the wave inclination does not change dramatically, TMC4361A provides four wave inclination segments with the base wave inclinations (W0, W1, W2, and W3) and the segment borders (0, X1, X2, X3, and 255), as shown in the left quarter of the MSLUT diagram in Figure 48, page 89. Wave Inclination Characteristics Wave Inclination Segment 0 1 2 3 Base Wave Inclination W0 W1 W2 W3 Segment Ranges 0 … X1 X1… X2 X2 … X3 X3 … 255 Table 40: Wave Inclination Characteristics of Internal MSLUT © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 91/230 Setup of MSLUT Segments Base Wave Inclination and Border Values All base wave inclination values (each consists of two bits) as well as the border values (each consists of eight bit) between the segments are adjustable. They are assigned by MSLUTSEL register 0x78. In order to change the base wave inclination values and the segment borders, do as follows: Action:  Define the segment borders X1, X2, and X3 and the base wave inclination values W0…W3 according to the requirements  Set register MSLUTSEL(31:24) = X3.  Set register MSLUTSEL(23:16) = X2.  Set register MSLUTSEL(15:8) = X1.  Set register MSLUTSEL(7:6) = W3.  Set register MSLUTSEL(5:4) = W2.  Set register MSLUTSEL(3:2) = W1.  Set register MSLUTSEL(1:0) = W0. Result: The segments and the base wave inclination values of the internal MSLUT are changed. NOTE:  It is not mandatory to define four segments. For instance, if only two segments are required, set X2 and X3 to 255. Then, W0 is valid for segment 0 between MSCNT = 0 and MSCNT = X1, and W1 is valid between MSCNT = X1 and MSCNT = 255 (segment 1). In order to change the ofs bits, do as follows: Action:  Set MSLUT[0]  Set MSLUT[1]  Set MSLUT[2]  Set MSLUT[3]  Set MSLUT[4]  Set MSLUT[5]  Set MSLUT[6]  Set MSLUT[7] register register register register register register register register 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 = = = = = = = = ofs31…ofs00. ofs63…ofs32. ofs95…ofs64. ofs127…ofs96. ofs159…ofs128. ofs191…ofs160. ofs223…ofs192. ofs255…ofs224. Result: The ofs bits of the internal MSLUT are changed. AREAS OF SPECIAL CONCERN Zero Crossing ! When modifying the wave: Special care has to be applied in order to ensure a smooth and symmetrical zero transition whenever the quarter wave becomes expanded to a full wave. When adjusting the range: The maximum resulting swing of the wave should be adjusted to a range of −248 to 248, in order to achieve the best possible resolution while at the same time leaving headroom for a hysteresis based chopper to add an offset. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 92/230 Current Waves Start Values Starting Current Values of MSLUT Configuration As both waves are shifted by 90° for two-phase stepper motors, the sine wave starts at 0° when MSCNT = 0. By comparison, the cosine wave begins at 90° when MSCNT = 256. At this starting points the current values are CURRENTA = 0 for the sine wave and CURRENTB = 247 for the cosine wave. In contrast to the starting microstep positions that are fixed, these starting current values can be redefined if the default start values do not fit for the actual MSLUT. In order to change the starting current values of the MSLUT, do as follows: Action:  Define the start values START_SIN and START_SIN90_120 according to the requirements.  Set register 0x7E (7:0) = START_SIN  Set register 0x7E (23:16) = START_SIN90_120 Result: The starting values for both waves are adapted to MSLUT. Default MSLUT Base Wave Inclinations The default sine wave table in TMC drivers uses one segment with a base inclination of 2 and one segment with a base inclination of 1 (see default value of the MSLUTSEL register 0x78 = 0xFFFF8056). The segment border X1 is located at MSCNT = 128. The base wave inclinations are W0 = b’10 (=2) and W1 = b’01 (=1). As a result, between MSCNT = 0 and 128, the increment value INC is either 1 (if ofs = 0) or 2 (if ofs = 1). And between MSCNT = 128 and 255, the increment value INC is either 0 (if ofs = 0) or 1 (if ofs = 1). This reflects the stronger rise in the first segment of the MSLUT in contrast to the second segment. The maximum value is START_SIN90_120 = 247. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 93/230 Explanatory Notes for Base Wave Inclinations Definition of Segments 0,1,2,3 In the following example four segments are defined. Each segment has a different base wave inclination to illustrate each possible entry: Segment Segment Segment Segment 0: 1: 2: 3: W0 W0 W0 W0 = = = = 3 2 1 0 which which which which means means means means that that that that the the the the increment increment increment increment value value value value is is is is +2 or +3. +1 or +2. 0 or +1. −1 or 0. i In addition to the MSLUT curve (black line), which is defined by the given ofs bits, all four segments show upper limits (red line); in case all ofs bits in the particular segments are set to 1. i The green line shows the lower limit in case all ofs bits in the particular segments are set to 0. y 256 Segment upper limits Segment lower limits 0 X1 X2 X3 255 -1/+0 +0/+1 +1/+2 +2/+3 Segment inclination W 0 Figure 52: MSLUT Curve with all possible Base Wave Inclinations (highest Inclination first) Standard Sine Wave Setup Considerations prior to SETUP of MSLUT In order to set up a standard sine wave table for the MSLUT, the following considerations have to be taken into account: PRECONSIDERATIONS:      The microstep table for the standard sine wave begins with eight entries (0 to 7) {0, 1, 3, 4, 6, 7, 9, 10 …} etc. The maximum difference between two values in this section is +2, whereas the minimum difference is +1. While advancing according to the table, the very first time the difference between two MSLUT values is lower than +1 is between position 153 and position 154. Both entries are identical. The start value is 0 for the sine wave. The calculated value for position 256 (i.e. start of cosine wave) is 247.  Description is continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Standard Sine Wave Setup 94/230 In order to set up the standard sine wave table, proceed as follows: Action:  Set a starting value START_SIN = 0 matching sine wave entry 0.  Set a base wave inclination range of W0 = b’10 = 2 to skip between +1 / +2, valid from 0 to X1.  Calculate the differences between every entry: {+1, +2, +1, +2, +1, +2, +1,…}.  Set the microstep table entries ofsXX to 0 for the lower value (+1); 1 for the higher value (+2). Thus, the first seven microstep table entries ofs00 to ofs06 are: {0, 1, 0, 1, 0, 1, 0 …}  The base wave inclination must be lowered at position 153, at very latest. Use the next base wave inclination range 1 with W1 = b’01 = 1 to skip between +0 and +1.  Set X1 = 153 in order to switch to the next inclination range. From here on, an offset ofsXX of 0 means add nothing; 1 means add +1.  Set START_SIN90_120 = 247, which is equal to the value at position 256.  Only two of four wave segments with different base wave inclinations are used. The remaining wave inclination ranges W2 and W3 should be set to the same value as W1; and X2 and X3 can be set to 255. Thereby, only two wave inclination segments are effective. Result: A standard sine wave is defined as MSLUT. The following table shows an extract of this curve. Overview of the Microstep Behavior Example Microstep number Desired table entry Difference to next entry Required segment inclination Ofs bit entry 0 1 2 3 4 5 6 7 … 153 154 … 255 0 1 3 4 6 7 9 10 … 200 200 … 247 1 2 1 2 1 2 1 … … 0 … … 0 +2 +2 +2 +2 +2 +2 +2 … … +1 … … +1 0 1 0 1 0 1 0 … … 0 … … 0 Table 41: Overview of the Microstep Behavior Example © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 95/230 SPI Output Interface Configuration Parameters TMC4361A provides an SPI output interface. In the next section, the configuration of the interface parameters is explained in detail. How to enable SPI Output Communication In order to enable SPI output communication, do as follows: Action:  Set serial_enc_out_enable = 0 (bit24 of GENERAL_CONF register 0x00). Result: SPI output is enabled. i Pins dedicated to SPI Output Communication SPI out is the default preconfigured setting. The table below lists the pins that are dedicated to SPI output communication: SPI Output Communication Pins Pin Description NSCSDRV_SDO Low active chip select signal. SCKDRV_NSDO SPI output clock. SDODRV_SCLK SDIDRV_NSCLK MOSI – Output pin to transfer the datagram to the motor driver. MISO – Input pin which receives the response from the motor driver. The response is sampled during the data transfer to the motor driver. Table 42: SPI Output Communication Pins © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Setup of SPI Output Timing Configuration 96/230 Because TMC4361A represents the master of SPI communication to the motor driver – which is the slave – it is mandatory to set up the timing configuration for the SPI output. TMC4361A provides an SPI clock, which is generated at the SCKDRV_NSDO output pin. In order to configure the timing of the SPI clock, set up SPIOUT_CONF register 0x04 as follows: Action:  Set the number of internal clock cycles the serial clock should stay low at SPI_OUT_LOW_TIME = SPIOUT_CONF (23:20).  Set the number of internal clock cycles the serial clock should stay high at SPI_OUT_HIGH_TIME = SPIOUT_CONF (27:24).  Also, an SPI_OUT_BLOCK_TIME = SPIOUT_CONF(31:28) can be set for a minimum time period during which no new datagram is sent after the last SPI output datagram. Result: SPI output communication scheme is set. During the inactive phase between to SPI datagrams - which is at least SPI_OUT_BLOCK_TIME clock cycles long - the SCKDRV_NSDO and NSCSDRV_SDO pins remain at high output voltage level. The timing of the SPI output communication is illustrated in the following figure. spi_out_block_time / fCLK spi_out_high_time / fCLK spi_out_low_time / fCLK NSCSDRV_SCLK SCKDRV_NSDO SDODRV_SCLK bitCDL-1 SDIDRV_NSCLK bitCDL-2 bit39 bit38 bit0 bit0 sample points Figure 53: SPI Output Datagram Timing Minimum and Maximum Time Period The minimum time period for all three parameters is 2/fCLK. If an SPI output parameter is set to 0, it is altered to 2 clock cycles internally. A maximum time period of 15/fCLK can be set for all three parameters. Thus, SPI clock frequency fSPI_CLK covers the following range: fCLK / 30 ≤ fSPI_CLK ≤ fCLK / 2. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Current Diagrams Process Description Basically, SPI output communication serves as automatic current datagram transfer to the connected motor driver. TMC4361A uses the internal microstep lookup table (MSLUT) in order to provide actual current motor driver data.      Change of Microstep Resolution Cover Datagrams Communication between µC and Driver 97/230 With every step that is initialized by the ramp generator the MSCNT value is increased or decreased, dependent on ramp direction. The MSCNT register 0x79 (readable value) contains the current microstep position of the sine value. Accordingly, the current values CURRENTA (0x7A) and CURRENTB (0x7B) are altered. In case the output configuration of TMC4361A allows for automatic current transfer an updated current value leads to a new datagram transfer. Thereby, the motor driver always receives the latest data. The length for current datagrams can be set automatically and TMC4361A converts new values into the selected datagram format, usually divided in amplitude and polarity bit for TMC motor drivers. By altering the microstep resolution from 256 ( MSTEP_PER_FS = b’0000) to a lower value, an internal step results in more than one MSLUT step. For instance, if the microstep resolution is set to 64 ( MSTEP_PER_FS = b‘0010), MSCNT is either increased or decreased by 4 per each internal step. Accordingly, the passage through the MSLUT skips three current values per each internal step to match the new microstep resolution. In addition to automatic current datagram transfer, the microcontroller can communicate directly with the motor driver through TMC4361A by using cover datagrams. This communication channel can be useful for configuration purposes because no additional SPI communication channel between microcontroller and motor driver is necessary. Up to 64 bits can be assigned for one cover datagram. This 64-bit SPI cover register is separated into two 32-bit registers - COVER_HIGH register 0x6D and COVER_LOW register 0x6C. The COVER_HIGH register is only required if more than 32 bits must be sent once. How to Define Cover Datagram Length How many bits are sent within one cover datagram is defined by the cover datagram length COVER_DATA_LENGTH . In order to define the cover datagram length, do as follows: Action:  Set the number of cover datagram bits at COVER_DATA_LENGTH = SPIOUT_CONF (19:13). Result: The cover datagram length is set to COVER_DATA_LENGTH bits. If this parameter is set higher than 64, the cover register data length is still maximum 64 bits. i For TMC motor drivers it is possible to set COVER_DATA_LENGTH = 0. In this case, the cover data length is selected automatically, dependent on the chosen motor driver. More details are provided on the subsequent pages. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Sending Cover Datagrams 98/230 The LSB (last significant bit) of the whole cover datagram register is located at COVER_LOW(0). As long as COVER_DATA_LENGTH < 33, only COVER_LOW or parts of this register are required for cover data transfer. If more than 32 bits are necessary, the complete COVER_LOW and (parts of) the COVER_HIGH register are required for SPI cover data transfer. NOTE:  Every SPI communication starts with the most significant bit (MSB). OPTION 1: COVER_DATA_LENGTH < 33 BITS In order to send a cover datagram - that is smaller than 33 bits - do as follows: Action:  Set COVER_LOW (COVER_DATA_LENGTH-1:0) register 0x6C = cover_data. Result: After a register request to COVER_LOW, COVER_DATA_LENGTH bits of COVER_LOW register. Cover Datagrams with 32 Bits valid SPI output is sent out OPTION 2: COVER_DATA_LENGTH > 32 BITS In order to send a cover datagram - that consists of more than 32 bits - do as follows: Action:  Split cover data into two segments:  cover_data_low = cover_data(31:0).  cover_data_high = cover_data >> 32.  cover_data_high = cover_data(31:0).  Set COVER_HIGH(COVER_DATA_LENGTH−32:0) register 0x6D=cover_data_high.  Set COVER_LOW register 0x6C = cover_data_low. Result: After a valid register request to COVER_LOW, SPI output is sent out COVER_DATA_LENGTH bits that comprises register values of COVER_HIGH and COVER_LOW. The cover register and the datagram structure are illustrated in the figure below: Cover register bit63 bit62 ... bit33 bit32 COVER_HIGH bit31 bit30 ... bit1 bit0 COVER_LOW bit31 bit30 ... bit1 bit0 bit31 bit30 ... bit1 bit0 MSB if CDL=63 MSB if CDL=30 (COVER_HIGH not required) Figure 54: Cover Data Register Composition (CDL – COVER_DATA_LENGTH)  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 99/230 Receiving Responses to Cover Datagrams Because the transfer of a cover datagram is usually accompanied by a data transfer from the motor driver, the response is stored in registers; and is thus available for the microcontroller. COVER_DRV_HIGH register 0x6F and COVER_DRV_LOW register 0x6E form this cover response register that can also comprise up to 64 bits. Similar to COVER_LOW and COVER_HIGH, the motor driver response is divided in the registers COVER_DRV_LOW and COVER_DRV_HIGH. The composition of the response cover register and also the positioning of the MSB follow the same structure. COVER_DONE Event At the end of a successful data transmission, the event COVER_DONE becomes set. This indicates that the cover register data is sent to the motor driver and that the received response is stored in the COVER_DRV_HIGH register 0x6F and COVER_DRV_LOW register 0x6E. Configuring Automatic Generation of Cover Datagrams In certain setups, it can be useful to automatically send ramp velocity-dependent cover datagrams, e.g. to change chopper settings during motion. NOTE:  This feature is only available if the cover datagram length does not exceed 32 bits. In order to activate ramp velocity-dependent automatic cover data transfer, do as follows: Action:  Define the trigger velocity whenever an automatic cover datagram transfer is initiated.  Set SPI_SWITCH_VEL register 0x1D to this absolute velocity [pps].  Set COVER_LOW register 0x6C to the cover_data, which is valid for lower velocity values.  Set COVER_HIGH register 0x6D to the cover_data, which is valid for higher velocity values.  Set automatic_cover = 1 (REFERENCE_CONF register 0x01). Result: Whenever the absolute internal ramp velocity |VACTUAL| passes the SPI_SWITCH_VEL value, the particular cover data is sent to the motor driver, COVER_LOW is sent in case |VACTUAL| < SPI_SWITCH_VEL, COVER_HIGH is sent in case |VACTUAL| ≥ SPI_SWITCH_VEL. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 100/230 Overview: TMC Motor Driver Connections As mentioned before, TMC4361A is able to set the cover register length automatically in case a TMC motor driver is connected. Also, several additional automatic features for the SPI communication are available by selecting TMC motor drivers. TMC Stepper Motor Driver Settings Available SPI and Step/Dir™ Communication Schemes for TMC Motors The SPI and Step/Dir communication schemes are available for the following product lines that are explained in greater detail further below: How to enable SPI Output Settings for TMC Stepper Motor Drivers In order to enable an operating SPI output setting for a connected TMC stepper motor driver, proceed as follows:      TMC236, TMC239 TMC246, TMC248, TMC249 TMC260, TMC261, TMC262, TMC2660 TMC389 TMC2130 Action:  Set SPI_OUT_LOW_TIME, SPI_OUT_HIGH_TIME, and SPI_OUT_BLOCK_TIME according to the TMC motor driver specification, as explained before.  Set COVER_DATA_LENGTH = 0 (bit19:13 of SPIOUT_CONF register 0x04).  Set spi_output_format = SPI_OUT_CONF (3:0) according to the connected SPI motor driver as seen below in the table below. Result: The communication scheme is now prepared for the connected TMC motor driver with all available features. TMC Stepper Motor Driver Options COVER_DATA_LENTGH=0 Automatic Current Datagram Transfer Cover Register Datagram Transfer b’0000 0 -- -- TMC23x b’1000 12   TMC24x b’1001 12   b’1010 b’1011 b’1101 b’1100 20 20 40 40  S/D output  S/D output TMC Motor Driver spi_output_format SPI output off TMC26x/389 TMC2130 =SPI_OUT_CONF (3:0) Cover Register Datagram Length Table 43: TMC Stepper Motor Driver Options © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL    TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC Motor Driver Response Datagram and Status Bits 101/230 When a TMC motor driver receives a current datagram or a cover datagram that is transmitted via SPI output of TMC4361A, status data is sent back to the TMC4361A controller immediately. The response is stored in the COVER_DRV_LOW 0x6E and COVER_DRV_HIGH 0x6F registers, just like all other cover requests. The type and sequence of the status bits that are sent back are dependent on the selected motor driver. A detailed list for every motor driver is presented in the next sections, in which the motor driver communication specifics for every driver family are explained separately. The mapping of the available status bits to the TMC4361A STATUS register is similar for each and every TMC stepper motor driver. The last eight bits – STATUS (31:24) – are equal to the transferred motor status bits. A detailed overview is given in the register chapter 19.15. (page 198). Events and Interrupts based on Motor Driver Status Bits TMC4361A also provides one event at EVENTS (30) that is connected with the motor driver status bits. Here, any of the motor driver status bits can function as the base for this event. In order to activate a motor driver status bit for the motor event EVENTS (30), do as follows: Action:  Selected one or more of the motor driver status for the motor event by assigning MSTATUS_SELECTION = STEP_CONF (23:16) register 0x0A accordingly. Result: In case one of the selected motor status bits is activated (Wired-Or), the motor event switch EVENTS (30) generates an event. In order to generate an interrupt for this motor event, configure the INTR output accordingly, as explained in section 5.3. (page 26). © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 102/230 Stall Detection and Stop-on-Stall stallGuard and stallGuard2 Functionality TMC stepper motor driver chips with stallGuard and stallGuard2 can detect stall and overload conditions based on the motor’s back-EMF without the need of a position sensor. The stall detection status is returned via SPI. For more information, refer to the AppNote “Parameterization of stallGuard2 & coolStep” that is available online at www.trinamic.com . Representation of the Motor Stall Status Except for TMC23x and TMC24x, which forward three load detection bits, the motor stall status is represented by one status bit. TMC4361A is able to stop the internal ramp as soon as a stall is recognized. Because stall bit activation can occur unwanted during motion with a low velocity, it is also possible to set up a velocity threshold for the Stop-on-Stall behavior. Internal Velocity Ramp Stop-on-Stall Activation In order to activate a Stop-on-Stall for the internal velocity ramp, do as follows: Action:  Set VSTALL_LIMIT register 0x67 [pps] according to minimum absolute velocity value for a correct stall recognition.  Set stop_on_stall = 1 (bit26 of REFERENCE_CONF register 0x01).  Set drive_after_stall = 0 (bit27 of REFERENCE_CONF register 0x01). Result: The internal ramp velocity is set immediately to 0 whenever a stall is detected and the following is true: |VACTUAL| > VSTALL_LIMIT. Then, the STOP_ON_STALL event is also generated. Internal Velocity Ramp Activation after Stop-onStall i The status bit stallGuard that is directly mapped from the motor stepper driver, which is listed in STATUS (24). This flag is always activated as soon as the motor driver generates the stall guard status bit. i The ACTIVE_STALL status bit = STATUS (11) is activated as soon as a stall is detected and |VACTUAL| > VSTALL_LIMIT. In order to activate the internal velocity ramp AFTER a Stop-on-Stall, do as follows: Action:  Read out the EVENTS register 0x0E to unlock the event STOP_ON_STALL.  Set drive_after_stall = 1 (bit27 of REFERENCE_CONF register 0x01). Result: The internal ramp velocity is no longer blocked by the Stop-on-Stall event. i In order to activate the Stop-on-Stall behavior again, reset drive_after_stall again manually to 0. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 103/230 TMC23x, TMC24x Stepper Motor Driver In this chapter specific information pertaining to the setup of TMC23x and TMC24x is provided. TMC23x/24x Support TMC4361A provides the following features in order to support the TMC23x motor stepper driver family well:     Automatic Mixed Decay chopper mode ChopSync Automatic switchover between microstep and fullstep operation Controlled PWM signal generation and automatic switchover between SPI and PWM mode; see section 13.2. (page 133). In the following section, the features are explained in greater detail. i TMC23x Setup For further information, please refer to the manual of the particular stepper driver motor. In order to activate the SPI data transfer and SPI feature set for a connected TMC23x stepper motor driver, do as follows: Action:  Set spi_output_format = b’1000 (SPI_OUT_CONF register 0x04).  Set COVER_DATA_LENGTH = 0 (SPI_OUT_CONF register 0x04). Result: TMC23x is selected as connected stepper motor driver. TMC24x Setup In order to activate the SPI data transfer and feature set for a connected TMC24x stepper motor driver, do as follows: Action:  Set spi_output_format = b’1001 (SPI_OUT_CONF register 0x04).  Set COVER_DATA_LENGTH = 0 (SPI_OUT_CONF register 0x04). Result: TMC24x is selected as connected stepper motor driver. i In addition to the TMC23x features mentioned above, the TMC24x stepper driver family provides three stallGuard bits as load measurement indicator. Therefore, the TMC24x stepper family is supported by the TMC4361A for the following:   Stall detection and Stop-on-Stall behavior  Turn to next page for more information. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 TMC23x/24x Status Bits TMC23x/24x Microsteps 104/230 TMC4361A maps the following status bits of TMC23x/24x stepper drivers – which are transferred with each SPI datagram – to the STATUS register 0x0F: Status Register Mapping for TMC23x/24x STATUS bit Status flag Description @TMC4361A @TMC23x/24x STATUS (24) UV Undervoltage flag. STATUS (25) OT Over temperature flag. STATUS (26) OTPW Temperature prewarning flag. STATUS (27) OCA Overcurrent flag for bridge A. STATUS (28) OCB Overcurrent flag for bridge B. STATUS (29) OLA Open load flag for bridge A. STATUS (30) OLB Open load flag for bridge B. STATUS (31) OCHS Overcurrent high side flag. Table 44: Mapping of TMC23x/24x Status Flags TMC4361A only forward new current data (CURRENTA_SPI and CURRENTB_SPI at register 0x7B) for TMC23x/TMC24x in case the upper five bits of one of the two 9-bit current values changes; because TMC23x and TMC24x current data consist of four bit current values and one polarity bit for each coil. Consequently, alterations of the internal microstep resolution only apply in case the new microstep resolution is lower than 16 bits. Automatic Fullstep Switchover for TMC23x/24x Because SPI current data is transmitted, automatic switchover from microsteps to fullsteps and vice versa is only dependent on the internal ramp velocity. In order to activate automatic switchover between microstep and fullstep operation, do as follows: Action:  Set FS_VEL register 0x60 according to the velocity [pps] at which the switchover must happen.  Set fs_en = 1 (bit19 of GENERAL_CONF register 0x00). Result: Now, current values are switched to fullstep values in case |VACTUAL|≥FS_VEL. A switchback from fullsteps to µsteps is executed in case |VACTUAL| DC_VEL, dcStep is activated, dcStep active VMAX AX AM overload DM AX L INA DF DC_VEL AST ART VBREAK 0 t Nominal ramp profile Ramp profile with torque overload and same target position Figure 60: Velocity Profile with Impact through Overload Situation Turn Page for important information about the chopper settings for microstep and fullstep/dcStep mode. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 AREAS OF SPECIAL CONCERN ! 139/230 Different chopper settings for microstep and fullstep/dcStep mode of TMC26x stepper driver can be transferred automatically during motion. Switching between dcStep mode and microstep mode often requires different chopper settings for TMC26x stepper motor drivers. It is possible to automatically transfer cover datagrams to TMC26x (see section 10.3.7, page 99). Thereby, it is possible to switch the chopper settings of TMC26x rapidly, shortly before reaching the dcStep velocity. NOTE:  It is recommended to use this feature because dcStep requires constant off-time chopper settings; whereas driving with µSteps and a spreadCycle chopper provides better driving characteristics. In order to set up a TMC26x dcStep configuration, do as follows: Action:  Set the SPI_SWITCH_VEL register 0x1D value a little bit smaller than the DC_VEL register 0x60 value.  Fill in the COVER_LOW 0x6C register the chopper settings for spreadCycle chopper below the DC_VEL.  Fill in the COVER_HIGH 0x6D register the chopper settings for a constant off-time chopper during dcStep operation (fullstep mode).  Set automatic_cover = 1 (REFERENCE_CONF register 0x01). Result: In case dcStep mode is not activated – because |VACTUAL| < DC_VEL – the spreadCycle chopper mode is activated, which is best suited for microstep operation. In case dcStep is activated, the more suited constant off-time chopper mode for fullstep operation is activated.  Turn Page for more information on enabling dcStep for TMC2130 stepper motor driver. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling dcStep for TMC2130 Stepper Motor Drivers 140/230 dcStep operation with TMC2130 is similar to a handshake procedure: The MP1 input must be connected to the DCO output pin of TMC2130, whereas MP2 must be connected to the DCEN input pin of TMC2130. In order to set up a TMC2130 dcStep configuration, do as follows: The mandatory TMC2130 configuration MUST be executed with cover datagrams, as follows: i Please refer to the TMC2130 manual for correct settings pertaining to the TMC2130 CHOPCONF and DCCTRL registers. Action:  Set spi_output_format = b’1101 or b’1100 (automatic TMC2130 setting)  Set dcstep_mode = b’01 (GENERAL_CONF register 0x00). Result: In case VACTUAL ≥ DC_VEL, MP2 output is set to high voltage level to indicate that dcStep can be activated. TMC2130 will wait for the next fullstep position to switch to dcStep operation. The dcStep signal is provided by the TMC2130 at DCO output pin. TMC4361A is continually providing microsteps even though dcStep is enabled and activated. TMC2130 auto-generates the dcStep behavior internally. Set up minimum dcStep/Fullstep Frequency Because dcStep operates the motor in fullstep mode, a minimum fullstep frequency fFS can be assigned. Therefore, a dcStep low speed timer must be assigned to achieve the following minimum fullstep frequency: fFS = fCLK / DC_LSPTM. In order to set up a minimum dcStep fullstep frequency, do as follows: Action:  Set DC_LSPTM register 0x62. Result: After DC_LSPTM clock cycles expires – without lifting the internal dcStep signal – a step is enforced when dcStep is enabled. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 141/230 15. Decoder Unit: Connecting ABN, SSI, or SPI Encoders correctly TMC4361A is equipped with an encoder input interface for incremental ABN encoders, absolute SSI or SPI encoders. This chapter provides basic setup information for correct analysis of connected encoder signals. Decoder Pins Pin Names Type Remarks A_SCLK Input or Output ANEG_NSCLK Input or Output B_SDI Input BNEG_NSDI Input or Output N Input N signal of ABN encoder. NNEG Input Negated N signal of ABN encoder. A signal of ABN encoder or Serial Clock output for absolute SSI, or SPI encoders. Negated A signal of ABN encoder or Negated Serial Clock output for SSI encoder or Low active Chip Select signal for SPI encoders. B signal of ABN encoder or Serial Data Input of SSI, or SPI encoders. Negated B signal of ABN encoder or Negated Serial Data Input of SSI encoders or Serial Data Output of SPI encoder. Table 55: Dedicated Decoder Unit Pins Decoder Unit Registers Register Name Register address Remarks GENERAL_CONF 0x00 RW Bit11:10: serial_enc_in_mode, Bit12: diff_enc_in_disable INPUT_FILT_CONF 0x03 RW Input filter configuration (SR_ENC_IN, FILT_L_ENC_IN). ENC_IN_CONF 0x07 RW Encoder configuration register. ENC_IN_DATA 0x08 RW Serial encoder input data structure. STEP_CONF 0x0A RW Motor configurations. ENC_POS 0x50 RW Current absolute encoder position in microsteps. ENC_LATCH 0x51 R Latched absolute encoder position. ENC_POS_DEV 0x52 R Deviation between XACTUAL and ENC_POS. ENC_CONST 0x54 R Internally calculated encoder constant. W Encoder configuration parameter. R Current encoder velocity (signed). Current filtered encoder velocity (signed). W Serial encoder request data. R Serial encoder request data response. W Encoder compensation register set. Encoder Register Set Encoder velocity ADDR_TO_ENC DATA_TO_ENC ADDR_FROM_ENC DATA_FROM_ENC Encoder compensation 0x51…58 0x62…63 0x65 0x66 0x68 0x69 0x6A 0x6B 0x7D Table 56: Dedicated Decoder Unit Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Selecting the correct Encoder 142/230 The encoder interface consists of six pins that can be connected with different encoder types. Depending on the encoder type, the pins serve as inputs or as outputs. If inputs are assigned, the incoming signals can be filtered, as explained in chapter 4, page 20. Consequently, SR_ENC_IN and FILT_L_ENC_IN must be set accordingly. In the following, three options are presented to select a connected encoder properly. OPTION 1: INCREMENTAL ABN ENCODERS In order to set up a connected incremental ABN encoder, do as follows: Action:  Set serial_enc_in_mode = b’00 (GENERAL_CONF register 0x00). Result: An incremental ABN encoder is selected. OPTION 2: ABSOLUTE SSI ENCODERS In order to set up a connected absolute SSI encoder, do as follows: Action:  Set serial_enc_in_mode = b’01 (GENERAL_CONF register 0x00). Result: An absolute SSI encoder is selected. i In order to avoid an erroneous status of the connected absolute SSI encoder, a proper configuration is necessary prior to enabling; as described further down below on the subsequent pages: see section 15.4. on page 149. OPTION 3: ABSOLUTE SPI ENCODERS In order to set up a connected absolute SPI encoder: Action:  Set serial_enc_in_mode = b’11 (GENERAL_CONF register 0x00). Result: An absolute SPI encoder is selected. i In order to avoid an erroneous status of the connected absolute SPI encoder, a proper configuration is necessary prior to enabling; as described further down below on the subsequent pages: see section 15.4. on page 149. Turn page for encoder pin assignment overview. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Disabling digital differential Encoder Signals 143/230 If incremental ABN or absolute SSI encoders are selected, the dedicated encoder signals are treated as digital differential signals per default. For internally displaying a valid input level, the levels of a dedicated pair must be digitally inversed. i No analog differential circuit is available. In order to disable the digital differential input signals, do as follows: Action:  Set diff_enc_in_disable = 1 (GENERAL_CONF register 0x00). Result: Dedicated encoder signals are treated as single signals and every negated pin is ignored. i Concerning absolute SPI encoders, this is done automatically. Pin Assignment based on selected Encoder Setup Pin Pin Name No. 40 1 10 11 21 22 A_SCLK ANEG_NSCLK B_SDI BNEG_NSDI N NNEG Incremental ABN Absolute SSI Absolute SPI Differential Single-ended Differential Single-ended Single-ended A ¬A B ¬B N ¬N A B N - SCLK ¬SCLK SDI ¬SDI - SCLK SDI - SCLK CS SDI SDO - Table 57: Pin Assignment based on selected Encoder Setup Inverting of Encoder Direction In order to easily align the encoder direction with the motor direction it is possible to invert the encoder direction by setting one switch. In order to invert the encoder direction, do as follows: Action:  Set invert_direction = 1 (ENC_CONF register 0x07). Result: The calculation of the in external position ENC_POS is inverted, turning increment to decrement and vice versa. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 144/230 If the encoder is installed correctly, the encoder values form a circle for one motor revolution. Thus, the deviation ENC_POS_DEV between real position ENC_POS und internal position XACTUAL forms a constant function over the whole motor revolution. Consequently, the resulting form of a deficiently installed encoder is oval-shaped. This system failure results in a new function of ENC_POS_DEV that is similar to a sine function. In the figure A below, the position deviation is shown as function of one motor revolution, which comprises 51200 microsteps. TMC4361A provides an option to compensate this kind of misalignment by adding a triangular shape function that counteracts the system error. This can improve the encoder value evaluation significantly. Per default, this function is constant at 0. Encoder Misalignment Compensation In order to setup the triangular compensation function, do as follows: Action:  Set proper ENC_COMP_XOFFSET register 0x7D (15:0).  Set proper ENC_COMP_YOFFSET register 0x7D (23:16).  Set proper ENC_COMP_AMPL register 0x7D (31:24). Result: ENC_COMP_XOFFSET is 16-bit register which represents a numeral figure between 0 and 1. The resulting offset on the abscissa is calculated by: XOFF_LOW = ENC_COMP_XOFFSET · microsteps/rev / 65536. A triangular function is generated, which has its lowest point at (XOFF_LOW; ENC_COMP_YOFFSET). The peak is shifted at a distance of half a revolution. The peak coordinate (XOFF_PEAK;YOFF_PEAK) is calculated as follows: XOFF_PEAK = ENC_COMP_XOFFSET · microsteps/rev / 65536 + microsteps/rev / 2. YOFF_PEAK = ENC_COMP_YOFFSET + ENC_COMP_AMPL. In the figure A below, the red line illustrates this compensation function. Internally, the triangular function is added to the ENC_POS value. As a result, the position deviation is harmonized as a function of the motor revolution; which can be seen in the figure B below. A) 8 B) 6 6 AMPL 4 2 XOFF 0 0 µsteps 10000 20000 30000 40000 50000 -2 YOFF position deviation position deviation 4 -4 -6 8 2 µsteps 0 0 10000 20000 30000 40000 50000 -2 -4 -6 position deviation compensation function position deviation -8 -8 Figure 61: Triangular Function that compensates Encoder Misalignments © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 145/230 Incremental ABN Encoder Settings Incremental ABN encoders increment or decrement the external position counter register ENC_POS 0x50. This is based on A- and B-signal level transitions. Automatic Constant Configuration of Incremental ABN Encoder The external position register ENC_POS 0x50 is based on internal microsteps. Thus, every AB transition is transferred to microsteps by a fixed constant value. TMC4361A is able to calculated this constant automatically. In order to configure the incremental ABN encoder constant automatically, do as follows: Action:  Set fullstep resolution of the motor in FS_PER_REV (STEP_CONF register 0x0A).  Set microstep resolution MSTEP_PER_FS (STEP_CONF register 0x0A).  Set encoder resolution – the number of AB transitions during one revolution - in register ENC_IN_RES 0x54 (write access). Result: The encoder constant value ENC_CONST (readable at register 0x54) is calculated as follows: ENC_CONST = MSTEP_PER_FS · FS_PER_REV / ENC_IN_RES This constant is the number of microsteps through which ENC_POS is incremented or decremented by one AB transition. Manual Constant Configuration of Incremental ABN Encoder i i ENC_CONST consists of 15 digits and 16 decimal places. i In case the decimal representation also does not fit completely, the type of the decimal places of ENC_CONST can be selected manually with ENC_IN_CONF (0). Set ENC_IN_CONF (0) to 0 for binary representation; or set it to 1 for the decimal one. Keep in mind that with this approach ENC_POS can slightly differ from the real position; especially the further away the position moves from 0. In case 16 bits are not sufficient for a binary representation of the decimal places, TMC4361A tries to match them to a multiple of 10000 within these 16 decimal places. Thereby, a perfect match can be achieved in case decimal representation is preferred to a binary one. For some applications it can be useful to define the encoder constant value, which in this case does not correspond to the number of microsteps per revolution; e.g. if the encoder is not mounted directly on the motor. In order to configure the incremental ABN encoder constant manually, do as follows: Action:  Set ENC_IN_RES(31) =1.  Set ENC_IN_CONF(0) to 0 for a binary or to 1 for a decimal representation as explained in the previous section.  Set required encoder resolution in ENC_IN_RES (30:0) register 0x54. Result: ENC_CONST consists of 15 digits and 16 decimal places. The constant is the number of microsteps by which ENC_POS is incremented or decremented by one AB transition. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 146/230 Incremental Encoders: Index Signal: N resp. Z The index signal (N or Z channel) represents a recurrence of the same position in one motor encoder revolution. TMC4361A makes use of this signal to clear the external position counter, or to take a snapshot of the external or internal position, which then can be used to refine the home position more precisely. Position -4 -3 -2 -1 0 1 2 3 4 5 6 7 A B N t Figure 62: Outline of ABN Signals of an incremental Encoder Per default, the index channel is configured low active. Setup of Active Polarity for Index Channel In order to set up high active polarity for the index channel, do as follows: Action:  Set pol_n =1 (register ENC_CONF 0x07). Result: The index channel is high active. Configuration of N Event Index Channel Sensitivity The active polarity of the index channel can be used to clear the external position counter or to take a snapshot of the external or internal position. Therefore, N event is created internally. N event is based on the active polarity of the index channel. As addition, they can also be based on the polarities of the A and B channels. Four active polarity configuration options for the index channel are available, which are presented below. Configuration choice depends on customer-specific design wishes. In order to set up the index channel sensitivity based on active polarity, do as follows: Action:  Set n_chan_sensitivity (register ENC_CONF 0x07) to: Index Channel Sensitivity n_chan_sensitivity Result b’00 N event is active in case index voltage level fits pol_n. b’01 b’10 b’11 N event is triggered when the index channel switches to active polarity. N event is triggered when the index channel switches to inactive polarity. N event is triggered at both edges when the index channel switches to either active or inactive polarity. Table 58: Index Channel Sensitivity  Description continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 A and B Channel Signal Polarities for N Event 147/230 It can be useful to specify A and B channel signal polarities for N event. Per default, the polarities of both signal lines are set to 0 (low active). In order to set up A channel polarity to high active for N event, do as follows: Action:  Set pol_a_for_n = 1 (ENC_CONF register 0x07). Result: Now, A channel signal polarity for N event is high active. In order to set up B channel polarity to high active for N event, do as follows: Action:  Set pol_b_for_n = 1 (ENC_CONF register 0x07). Result: Now, B channel signal polarity for N event is high active. In case A and B channel polarities do not have an influence on N event, both A and B channel polarity signals can be ignored. In order to ignore A and B channel polarities, do as follows: Action:  Set ignore_ab = 1 (ENC_CONF register 0x07). Result: Now, the A and B channel signal polarities have no influence on N event. External Position Counter N event can be used to clear the external position register ENC_POS 0x50. Two choices are available: continous clearing and single clearing. Common practice is to clear to 0. However, TMC4361A offers the possibility to clear to any single microstep count. ENC_POS i ENC_POS Continous Clearing In order to set ENC_POS on N event to continuous clearing, do as follows: Clearing Action:  Set ENC_RESET_VAL register 0x51 to the requested microstep position.  Set clr_latch_cont_on_n = 1 (ENC_CONF register 0x07).  Set clear_on_n = 1 (ENC_CONF register 0x07). Result: On every N event ENC_POS is set to ENC_RESET_VAL. ENC_POS Single Clearing In order to only clear ENC_POS for the next N event, do as follows: Action:  Set ENC_RESET_VAL register 0x51 to the requested microstep position.  Set clr_latch_cont_on_n = 0 (ENC_CONF register 0x07).  Set clr_latch_once_on_n = 1 (ENC_CONF register 0x07).  Set clear_on_n = 1 (ENC_CONF register 0x07). Result: When the next N event occurs, ENC_POS is set to ENC_RESET_VAL. After the particular N event, clr_latch_once_on_n is automatically reset to 0. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Latching External Position Continous Encoder Latching 148/230 N event can be used to latch external position register ENC_POS 0x50 to storage register ENC_LATCH 0x51 (read access). Two choices are available: Continous latching and single latching. In order to continuously latch ENC_POS to ENC_LATCH on N event, do as follows: Action:  Set clr_latch_cont_on_n = 1 (ENC_CONF register 0x07).  Set latch_enc_on_n = 1 (ENC_CONF register 0x07). Result: On every N event ENC_POS register 0x50 is latched to ENC_LATCH register 0x51. Single Encoder Latching In order to only latch ENC_POS to ENC_LATCH for the next N event, do as follows: Action:  Set clr_latch_cont_on_n = 0 (ENC_CONF register 0x07).  Set clr_latch_once_on_n = 1 (ENC_CONF register 0x07).  Set latch_enc_on_n = 1 (ENC_CONF register 0x07). Result: When the next N event occurs, ENC_POS register 0x50 is latched to ENC_LATCH register 0x51. After the particular N event, clr_latch_once_on_n is automatically reset to 0. Latching Internal Position N event can be used to latch internal position register X_ACTUAL 0x21 to storage register X_LATCH 0x36 (read access). Two choices are available: Continous latching and single latching. Continous Latching In order to continuously latch X_ACTUAL to X_LATCH on N event, do as follows: Action:  Set clr_latch_cont_on_n = 1 (ENC_CONF register 0x07).  Set latch_enc_on_n = 1 (ENC_CONF register 0x07).  Set latch_x_on_n = 1 (ENC_CONF register 0x07). Result: On every N event X_ACTUAL register 0x21 is latched to X_LATCH register 0x36. Single Latching In order to only latch X_ACTUAL to X_LATCH for the next N event, do as follows: Action:  Set clr_latch_cont_on_n = 0 (ENC_CONF register 0x07).  Set clr_latch_once_on_n = 1 (ENC_CONF register 0x07).  Set latch_enc_on_n = 1 (ENC_CONF register 0x07).  Set latch_x_on_n = 1 (ENC_CONF register 0x07). Result: When the next N event occurs, X_ACTUAL register 0x21 is latched to X_LATCH register 0x36. After the particular N event, clr_latch_once_on_n is automatically reset to 0. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 149/230 Absolute Encoder Settings Serial encoders provide absolute encoder angle data in contrast to step transitions, which are delivered from incremental encoders. TMC4361A provides an external clock for the encoder in order to trigger serial data input, Singleturn or Multiturn Data TMC4361A offers singleturn and multiturn options for the serial data stream interpretation. Per default, multiturn data is not enabled. In case multiturn data is enabled, it is interpreted as unsigned count of revolutions. In case multiturn encoder data is transmitted, do as follows: Action:  Set multi_turn_in_en = 1 (ENC_CONF register 0x07).  OPTIONAL CONFIGURATION: Set multi_turn_in_signed = 1. In case multiturn data is provided as signed count of encoder revolutions. Result: Data from connected encoders are interpreted as multiturn data. In case only singleturn data is transmitted TMC4361A is able to permanently calculate internally the number of encoder revolutions as if it where externally transferred multiturn data. In case singleturn encoder data is transmitted but internally multiturn data is required, do as follows: Action:  Set multi_turn_in_en = 0 (ENC_CONF register 0x07).  Set calc_multi_turn_behav = 1 (ENC_CONF register 0x07). Result: Data from connected singleturn encoders is internally transferred to multiturn data. NOTE:  Multiturn calculations are only correct in case two consecutive singleturn data values differ only by one step less than a half turn difference, or even less. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Automatic Constant Configuration of Absolute Encoder 150/230 The external position register ENC_POS 0x50 is based on internal microsteps. Thus, every input data angle is transferred to microsteps by a fixed constant value. TMC4361A is able to automatically calculate this constant. In order to configure the absolute encoder constant automatically, do as follows: Action:  Set fullstep resolution of the motor in FS_PER_REV (STEP_CONF register 0x0A).  Set microstep resolution MSTEP_PER_FS (STEP_CONF register 0x0A).  Set encoder resolution in register ENC_IN_RES 0x54 (write access). Result: The encoder constant value ENC_CONST (readable at register 0x54) is calculated as follows: ENC_CONST = MSTEP_PER_FS · FS_PER_REV / ENC_IN_RES The external position ENC_POS 0x50 is calculated by multiplying the constant with the transmitted input angle. i i ENC_CONST consists of 15 digits and 16 decimal places. In contrast to incremental ABN encoders, ENC_CONST is always represented as binary constant. Manual Constant Configuration of incremental ABN Encoder For some applications it can be useful to define the encoder constant value, which in this case does not correspond to the number of microsteps per revolution; e.g. if the encoder is not mounted directly on the motor. In order to configure the absolute encoder constant manually, do as follows: Action:  Set ENC_IN_RES (31) =1.  Set required encoder resolution in ENC_IN_RES (30:0) register 0x54. Result: ENC_CONST consists of 15 digits and 16 decimal places. The external position ENC_POS 0x50 is calculated by multiplying the constant with the transmitted input angle. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Absolute Encoder Data Setup 151/230 Encoder Data must be maintained correctly. Consequently, certain settings must be configured so that TMC4361A displays them as specified. In order to configure absolute encoder data, do as follows: Action:  Set SINGLE_TURN_RES (ENC_IN_DATA register 0x08) to the number of singleturn data bits -1. OPTION A1: IF MULTITURN DATA IS TRANSMITTED  Set MULTI_TURN_RES (ENC_IN_DATA register 0x08) to the number of multiturn data bits -1. OR OPTION A2: IF MULTITURN DATA IS NOT TRANSMITTED  Set MULTI_TURN_RES = 0 (ENC_IN_DATA register 0x08).  Set STATUS_BIT_CNT (also register 0x08) to the number of status bits. OPTION B1: IF STATUS FLAGS ARE ORDERED IN FRONT  Set left_aligned_data = 0 (ENC_IN_CONF register 0x07). OR OPTION B2: IF STATUS FLAGS ARE ORDERED IN FRONT  Set left_aligned_data = 1 (ENC_IN_CONF register 0x07). Result: SINGLE_TURN_RES defines the most significant bit (MSB) of the angle data bits, whereas MULTI_TURN_RES defines the MSB of the revolution counter bits. Up to three status bits can be received. The number of transferred clock bits that are sent to the encoder is calculated as follows: #SCLK Cycles= (SINGLE_TURN_RES+1) + (MULTI_TURN_RES+1) + STATUS_BIT_CNT Also, the order in which the status bits occur in one encoder data stream can be configured. In Figure 63, example setups are depicted. NOTE:  In case more than three status bits or additional fill bits are sent from the encoder, clock errors can occur because the number of transferred clock bits does not fit.  In order to prevent clock failures, MULTI_TURN_RES can be set to a higher value than otherwise required; even if the encoder does not provide multiturn data. This can result in erroneous multiturn data, which can be corrected by setting multi_turn_in_en=0 in order to skip multiturn data automatically.  In order to compensate unavailable multiturn data make use of calc_multi_turn_behav, as explained in section 15.4.1 on page 149. Serial data out Serial data b) A2+B1: out Serial data c) A1+B1: out Serial data d) A1+B2: out a) A1+B1: MSBM SB1 SB0 LSBM MSBS LSBS SB0 MSBS LSBS MSBM MSBM LSBM LSBM MSBS MSBS LSBS LSBS SB2 Figure 63:Serial Data Output: Four Examples Key: a) SINGLE_TURN_RES=6; MULTI_TURN_RES=4; STATUS_BIT_CNT=0; left_aligned_data=0 b) SINGLE_TURN_RES=6; MULTI_TURN_RES=0; STATUS_BIT_CNT=2; left_aligned_data=0 c) SINGLE_TURN_RES=5; MULTI_TURN_RES=4; STATUS_BIT_CNT=1; left_aligned_data=0 d) SINGLE_TURN_RES=4; MULTI_TURN_RES=2; STATUS_BIT_CNT=3; left_aligned_data=1 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  SB1 SB0 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Emitting Encoder Data Variation 152/230 For some applications it can be useful to limit the difference between two consecutive encoder data values; for instance, if encoder data lines are subject to too much noise. Per default, encoder data values can show a difference of 1/8th per encoder revolution, only if the limitation is enabled. The difference can be configured to a smaller value, if necessary. In order to enable and configure encoder data variation limitation, do as follows: Action:  OPTIONAL: Set proper SER_ENC_VARIATION register 0x63 (7:0).  Set serial_enc_variation_limit =1 (ENC_IN_CONF register 0x07). Result: The encoder data value that is received subsequently must not exceed the previous data more than: Maximum tolerated deviation = SER_ENC_VARIATION / 256 · 1/8 · ENC_IN_RES. In case the variation exceeds the above mentioned limit, the new data value is rejected internally and the status flag SER_ENC_DATA_FAIL is raised. i In case SER_ENC_VARIATION = 0, the limit is defined by 1/8 · ENC_IN_RES. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 153/230 SSI Clock Generation In order to receive encoder data from the absolute encoder, TMC4361A generates clock patterns according to SSI standard. Data transfer is initiated by switching the clock line SCLK from high to low level. The transfer starts with the next rising edge of SCLK. The number of emitted clock cycles depends on the expected data width, as explained in section 15.4.4. Configuration Details One clock cycle has a high and a low phase, which can be defined separately according to internal clock cycles. Per default, sample points of serial data are set at the falling edges of SCLK. Some encoders need more clock cycles – than are available during the low clock phase – in order to prepare data for transfer. Also, due to long wires, data transfer can take more time. To counteract the above mentioned issues, the delay time SSI_IN_CLK_DELAY (default value equals 0) for compensation can be specified in order to prolong the sampling start. Therefore, this delay configuration can automatically generate more clock cycles. After a data request – when all clock cycles have been emitted – the serial clock must remain idle for a certain interval before the next request is automatically initiated. This interval SER_PTIME can also be configured in internal clock cycles. i According to SSI standard, select an interval that is longer than 21 µs. In order to configure the SSI clock generation, do as follows: Action:  Set SINGLE_TURN_RES (ENC_IN_DATA register 0x08) to the number of singleturn data bits -1.  Set MULTI_TURN_RES (ENC_IN_DATA register 0x08) to the number of multiturn data bits -1 in case multiturn data is enabled and used.  Set STATUS_BIT_CNT (ENC_IN_DATA reg. 0x08) to the number of status bits.  Set proper left_aligned_data (ENC_IN_CONF register 0x07).  Set proper SER_CLK_IN_LOW (register 0x56) in internal clock cycles.  Set proper SER_CLK_IN_HIGH (register 0x56) in internal clock cycles.  OPTIONAL CONFIG: Set proper SSI_IN_CLK_DELAY (register 0x57) in internal clock cycles.  OPTIONAL CONFIG: Set proper SER_PTIME (reg. 0x58) in internal clk cycles.  Finally, set serial_enc_in_mode = b’01. Result: TMC4361A emits serial clock streams at SCLK in order to receive absolute encoder data at SDI. If SSI_IN_CLK_DELAY > 0, the SDI sample points are delayed (see figures below). SER_PTIME defines the interval between two consecutive data requests. i SER_CLK_IN_HIGH If differential encoder is selected, the negated clock emits at ¬SCLK; and ¬SDI is also evaluated. SER_CLK_IN_LOW SSI_IN_CLK_DELAY Serial clock out Serial clock out Serial data in MSB LSB Sample points Figure 64: SSI: SSI_IN_CLK_DELAY=0 Serial data in --- MSB LSB Sample points Figure 65: SSI: SSI_IN_CLK_DELAY>SER_CLK_IN_HIGH © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling Multicycle SSI request 154/230 If safe transmission must be determined, it is possible to send a second request so that the encoder repeats the same encoder data. Therefore, a second interval SSI_WTIME must be defined. i According to SSI standard, select an interval that is shorter than 19 µs. In order to enable multicycle requests, do as follows: Action:  Set ssi_multi_cycle_data =1 (ENC_IN_CONF register 0x07).  Set proper SSI_WTIME (register 0x57) in internal clk cycles. Result: After a data request – when all clock cycles have been emitted – the serial clock remains idle for SSI_WTIME clock cycles. Afterwards, the second request is automatically initiated to receive the same encoder data. If the second encoder data differs from the first one, error flag MULTI_CYCLE_FAIL (register 0x0F) and error event SER_ENC_DATA_FAIL (register 0x0E) is generated. After the second data request, the next interval lasts SER_PTIME clock cycles to request new encoder data. Gray-encoded SSI Data Streams Several but not all SSI encoders emit angle data, which is gray-encoded. TMC4361A is able to decode this data automatically. In order to enable gray-encoded angle data, do as follows: Action:  Set ssi_gray_code_en =1 (ENC_IN_CONF register 0x07). Result: Encoder data is recognized as gray-encoded and thus also decoded accordingly. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 155/230 SPI Encoder Data Evaluation SPI encoder interfaces typically consist of four signal lines. In addition to SSI encoder signal lines (SCLK, MISO), a chip select line (CS) and a data input (MOSI) to the master is provided. SPI Encoder Communication Process The number of bits per transfer is calculated automatically; based on proper multi_turn_in_en, SINGLE_TURN_RES, MULTI_TURN_RES, and STATUS_BIT_CNT, as explained in sections 15.4.1 (page 149) and 15.4.4 (page 151). A typical SPI communication process responds to any SPI data transfer request when the next transmission occurs. When TMC4361A receives an answer from the encoder, it calculates ENC_POS immediately. The encoder slave does not send any data without receiving a request first. Therefore, TMC4361A always sends ADDR_TO_ENC value to request encoder data from the SPI encoder slave device. The LSB of the serial data output is ADDR_TO_ENC (0). Received encoder data is stored in ADDR_FROM_ENC. Thus, encoder values can be verified and compared to microcontroller data later on. i The clock generation works similarly to SSI clock generation, as described in section 15.4.5 on page 153; based on proper SER_CLK_IN_HIGH, SER_PTIME, and SER_CLK_IN_LOW. In order to configure a basic SPI communication procedure, do as follows: Action:  Set SINGLE_TURN_RES (ENC_IN_DATA register 0x08) to the number of singleturn data bits -1.  Set MULTI_TURN_RES (ENC_IN_DATA register 0x08) to the number of multiturn data bits -1 in case multiturn data is enabled and used.  Set STATUS_BIT_CNT (ENC_IN_DATA register 0x08) to the number of status bits.  Set proper left_aligned_data (ENC_IN_CONF register 0x07).  Set correct SPI transfer mode that is described in the next section.  Set ADDR_TO_ENC register 0x68 to the specified SPI encoder address that contains angle data.  Set proper SER_CLK_IN_LOW (register 0x56) in internal clock cycles.  Set proper SER_CLK_IN_HIGH (register 0x56) in internal clock cycles.  OPTIONAL CONFIG: Set proper SER_PTIME (register 0x58) in internal clk cycles.  Finally, set serial_enc_in_mode = b’11. Result: TMC4361A emits serial clock streams at SCLK in order to receive absolute encoder data at SDI pin. The number of generated clock cycles depends on SINGLE_TURN_RES, MULTI_TURN_RES, and STATUS_BIT_CNT. Pin ANEG_NSCLK functions as negated chip select line for the SPI encoder that is generated according to the serial clock and the selected SPI mode; which is described in the next section. Pin BNEG_NSDI is the MOSI line that transfers SPI datagrams to the SPI encoder. Datagrams, which are transferred permanently to receive angle data, consists of ADDR_TO_ENC data. SER_PTIME defines the interval between two consecutive data requests. Turn page for information on SPI mode selection. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 SPI Encoder Mode Selection 156/230 Per default, SPI encoder data transfer is managed in the same way as the communication between microcontroller and TMC4361A. TMC4361A supports all four SPI modes with proper setting of switches spi_low_before_cs and spi_data_on_cs. THE PROCESS IS AS FOLLOWS: By setting spi_low_before_cs = 0, negated chip select line at ANEG_NSCLK is switched to active low before the serial clock line SCLK switches. By setting spi_low_before_cs = 1, negated chip select line at ANEG_NSCLK is switched to active low after the serial clock line SCLK switches. By setting spi_data_on_cs = 0, the first data bit at BNEG_NSDI is changed at the same time as the first slope of the serial clock SCLK. By setting spi_data_on_cs = 1, the first data bit at BNEG_NSDI is changed at the same time as the negated chip select signal at BNEG_NSDI switches to active level. In the table below, all four SPI modes are presented. Per default, the delay between serial clock line and negated chip select line has a time frame of either SER_CLK_IN_HIGH or SER_CLK_IN_LOW clock cycles, which depends on the actual voltage level of the serial clock. This particular interval does not always match the encoder behavior perfectly. Therefore, both the first and last intervals between the serial clock line and the negated chip select line can be specified separately in clock cycles at SSI_IN_CLK_DELAY register 0x57. Below, the SSI_IN_CLK_DELAY interval is highlighted in red in all four diagrams. Supported SPI Encoder Data Transfer Modes spi_low_before_cs: 0 1 spi_data_on_cs 0 1 Serial clock out (A_SCLK) Serial clock out (A_SCLK) Chip Select (ANEG_NSCLK) Chip Select (ANEG_NSCLK) Serial data out (BNEG_NSDI) MSB LSB Serial data out (BNEG_NSDI) Sample points (B_SDI) Sample points (B_SDI) Serial clock out (A_SCLK) Serial clock out (A_SCLK) Chip Select (ANEG_NSCLK) Chip Select (ANEG_NSCLK) Serial data out (BNEG_NSDI) MSB LSB Sample points (B_SDI) Serial data out (BNEG_NSDI) MSB MSB Sample points (B_SDI) Table 59: Supported SPI Encoder Data Transfer Modes © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  LSB LSB TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 157/230 SPI Encoder Configuration via TMC4361A Connected SPI encoder can be configured via TMC4361A., which renders a connection between microcontroller and encoder unnecessary. SPI Encoder Configuration Communication Process A configuration request is sent using the settings of SERIAL_ADDR_BITS and SERIAL_DATA_BITS, which define the transferring bit numbers. In order to prepare SPI encoder configuration procedures, do as follows: Action:  Set SERIAL_ADDR_BITS (ENC_IN_DATA register 0x08) to the number of address bits of any SPI encoder configuration datagram.  Set SERIAL_DATA_BITS (ENC_IN_DATA register 0x08) to the number of data bits of any SPI encoder configuration datagram. Result: In case configuration data is transferred to the SPI encoder, SERIAL_ADDR_BITS bits and SERIAL_DATA_BITS bits are sent in two SPI configuration datagrams; exactly in this order. Because encoder data requests occur as an endless stream, it is necessary to interrupt data requests when a configuration request occurs. Consequently, a handshake behavior is implemented. In order to transfer configuration data to the SPI encoder, do as follows: Action:  Set DATA_TO_ENC register 0x69 to any value.  Set ADDR_TO_ENC register 0x68 to the configuration address of the SPI encoder.  Set DATA_TO_ENC register 0x69 to the configuration data of the SPI encoder. Result: The first DATA_TO_ENC access stops the repetitive encoder data request. After the second DATA_TO_ENC access, three datagrams are sent to SPI encoder: 1. One address datagram is transmitted, which contains the ADDR_TO_ENC value. Data that is received simultaneously with the request is not stored. 2. One data datagram is transmitted that contains the DATA_TO_ENC value. Data that is received simultaneously with the request is stored in ADDR_FROM_ENC register 0x6A because this is the response of the ADDR_TO_ENC request. 3. One no-operation datagram (NOP) is transmitted. Data that is received simultaneously with the request is stored in DATA_FROM_ENC register 0x6B because this is the response of the DATA_TO_ENC request. In order to finalize the configuration procedure and continue with the encoder data requests, do as follows:  Read out ADDR_FROM_ENC register 0x6A first.  Set ADDR_TO_ENC register 0x68 to the specified SPI encoder address that contains angle data.  Obligatory at finalization: Read out DATA_FROM_ENC register 0x6B. Result: The configuration request data is read out. After DATA_FROM_ENC register readout, the encoder data request stream of angle data continues. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 158/230 16. Possible Regulation Options with Encoder Feedback Beyond simple feedback monitoring, encoder feedback can be used for controlling motion controller outputs in such a way that the internal actual position matches or follows the real position ENC_POS. Two options are provided: PID control and closed-loop operation. Closed-loop operation is preferable if the encoder is mounted directly on the back of the motor and position data is evaluated precisely. PID control is preferable if the encoder is located on the drive side with no fixed connection between motor and drive side; e.g. belt drives. Closed-Loop and PID Registers Register Name Register address Remarks Encoder configuration register: Closed-Loop configuration switches. Absolute tolerated deviation to trigger TARGET_REACHED during regulation. ENC_IN_CONF 0x07 RW CL_TR_TOLERANCE 0x51 R ENC_POS_DEV 0x52 R Deviation between XACTUAL and ENC_POS. 0x59…5F 0x60…61 W Closed-Loop and PID configuration parameters. 0x63 W Encoder velocity filter configuration parameters. 0x65 0x66 R Current encoder velocity (signed). Current filtered encoder velocity (signed). Closed-Loop and PID Register Set Encoder velocity configuration Encoder velocity Table 60: Dedicated Closed-Loop and PID Registers Feedback Monitoring Based on the difference ENC_POS_DEV (readout at register 0x52) between internal position XACTUAL and external position ENC_POS, a status flag ENC_FAIL_F and a corresponding error event ENC_FAIL is generated automatically. In order to set a tolerated position mismatch, do as follows: Action:  Set ENC_POS_DEV_TOL register 0x53 to the maximum microstep value that represents no mismatch failure. Result: In case |ENC_POS_DEV| ≤ ENC_POS_DEV_TOL, no encoder failure flag is set. In case |ENC_POS_DEV| > ENC_POS_DEV_TOL, ENC_FAIL_Flag is set. i At this point, the corresponding encoder event ENC_FAIL is also triggered. Target-Reached during Regulation In case one of the regulation modes is selected, TARGET_REACHED event and status flag is only released when: XACTUAL = XTARGET and |ENC_POS_DEV| ≤ CL_TR_TOLERANCE. Consequently, CL_TR_TOLERANCE register 0x52 (only write access) is the maximal tolerated position mismatch for target reached status. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 PID-based Control of XACTUAL 159/230 Based on a position difference error PID_E = XACTUAL – ENC_POS the PID (proportional integral differential) controller calculates a signed velocity value (vPID), which is used for minimizing the position error. During this process, TMC4361A moves with vPID until |PID_E| – PID_TOLERANCE ≤ 0 is reached and the position error is removed. vPID is calculated by: 𝑣𝑃𝐼𝐷 = 𝑡 𝑃𝐼𝐷_𝑃 1 𝑃𝐼𝐷_𝐼 𝑑 ∙ 𝑃𝐼𝐷_𝐸 ∙ [ ] + ∙ ∫ 𝑃𝐼𝐷_𝐸 ∙ 𝑑𝑡 + 𝑃𝐼𝐷_𝐷 ∙ 𝑃𝐼𝐷_𝐸 ∙ 256 𝑠 256 𝑑𝑡 0 𝑣𝑃𝐼𝐷 = 𝑣𝑃𝐼𝐷 = 𝑃𝐼𝐷_𝑃 1 𝑃𝐼𝐷_𝐼 𝑑 ∙ 𝑃𝐼𝐷_𝐸 ∙ [ ] + ∙ 𝑃𝐼𝐷_𝐼𝑆𝑈𝑀 + 𝑃𝐼𝐷_𝐷 ∙ 𝑃𝐼𝐷_𝐸 ∙ 256 𝑠 256 𝑑𝑡 𝑃𝐼𝐷_𝑃 1 𝑃𝐼𝐷_𝐼 𝑓𝐶𝐿𝐾 𝑑 ∙ 𝑃𝐼𝐷_𝐸 ∙ [ ] + ∙ 𝑃𝐼𝐷_𝐸 ∙ + 𝑃𝐼𝐷_𝐷 ∙ 𝑃𝐼𝐷_𝐸 ∙ 256 𝑠 256 128 𝑑𝑡 Key: PID_P = proportional term; PID_I = integral term; PID_D = derivate term The following parameters can be read out during PID operation. PID Readout Parameters PID_VEL 0x5A Actual PID output velocity. PID_E 0x5D Actual PID position deviation between XACTUAL and ENC_POS. PID_ISUM 0x5B Actual PID integrator sum (update frequency: fCLK/128), which is calculated by: PID_ISUM=PID_E · fCLK /128 Turn page for information on configuration of PID regulation. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 PID Control Parameters and Clipping Values 160/230 In order to set parameters and clipping values for PID regulation correctly, consider the following details: PID_DV_CLIP 0x5E Large velocity variations are avoided by limiting vPID value with PID_DV_CLIP (register 0x5E). This clipping parameter limits both vPID and PID_VEL. PID_I_CLIP 0x5D (14:0) The error sum PID_ISUM (read out at 0x5B) is generated by the integral term. PID_ISUM is limited by setting PID_I_CLIP register 0x5D. i i PID_D_CLKDIV 0x5D (23:16) maximum value of PID_I_CLIP must meet the condition PID_I_CLIP ≤ PID_DV_CLIP / PID_I. If the error sum PID_ISUM is not clipped, it is increased with each time step by PID_I · PID_E. This continues as long as the motor does not follow. The Time scaling for deviation (with respect to error correction periods) is controlled by PID_D_CLKDIV register. i During error correction, fixed clock frequency fPID_INTEGRAL is valid: fPID_INTEGRAL[Hz] = fCLK[Hz] / 128 VEL_ACT_PID The internal velocity VEL_ACT_PID alters actual ramp velocity VACTUAL. Two settings are provided: In case regulation_modus = b’11, VACTUAL is assigned as pulse generator base value and VEL_ACT_PID is calculated by VEL_ACT_PID = VACTUAL + vPID. In case regulation_modus = b’10, zero is assigned as pulse generator base value. Now, VEL_ACT_PID = vPID is valid. PID_TOLERANC E 0x5F TMC4361A provides the programmable hysteresis PID_TOLERANCE for target position stabilization; which avoids oscillations through error correction in case XACTUAL is close to the real mechanical position. The PID controller of TMC4361A is programmable up to approximate 100 kHz update rate (at fCLK = 16 MHz). This high speed update rate qualifies PID regulation for motion stabilization. Enabling PID Regulation Now that PID control parameters and clipping values are configured, as explained above, PID regulation can be enabled. Two options can be selected. In order to enable PID control, do as follows: Action: OPTION 1: BASE PULSE GENERATOR VELOCITY = 0  Set regulation_modus = b’10 (ENC_IN_CONF register 0x07). OPTION 2: BASE PULSE GENERATOR VELOCITY = VACTUAL  Set regulation_modus = b’11 (ENC_IN_CONF register 0x07). Result: PID regulation is enabled. NOTE  Detailed knowledge of a particular application (including dynamics of mechanics) is necessary for PID controller parameterization. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 161/230 Closed-Loop Operation The closed-loop unit of TMC4361A directly modifies output currents and Step/Dir outputs of the internal step generator; which is dependent on the feedback data. The 2-phase closed-loop control of TMC4361 follows a different approach than Field-Oriented Control (FOC); which is similar to PID control cascades. The ramp generator, which assigns target and velocity, is independent of position control (commutation angle control); which is also independent of current control. Closed-loop operation can only be used in combination with 256 microsteps per fullstep. Basic ClosedLoop Parameters Closed-loop does not control current values via the internal step generator. The currents values at the SPI output and the Step/Dir outputs are verified using the evaluated difference between internal position XACTUAL and external position ENC_POS; considering the calibrated offset parameter CL_OFFSET. In order to set parameters and clipping values for closed-loop regulation correctly, consider the following details: CL_OFFSET 0x59 This register contains the basic offset value between internal and external position during calibration process, which is necessary for closed-loop operation, and offers read-write access. The write access can be used if a defined fixed offset value is preferred, which is verified beforehand. ENC_POS_DEV 0x52 The continuously updated parameter ENC_POS_DEV displays the deviation between XACTUAL and ENC_POS; considering CL_OFFSET. CL_BETA 0x1C (8:0) CL_BETA is the maximum commutation angle that is used to compensate an evaluated deviation ENC_POS_DEV. In case the deviation reaches CL_BETA value, the commutation angle remains stable at this value to follow the overload. Also, CL_MAX event is triggered at this point. CL_TOLERANCE 0x5F (7:0) This parameter is set to select the tolerance range for position deviation. In case |ENC_POS_DEV| ≤ CL_TOLERANCE, CL_FIT_F lag becomes set. In case a mismatch between internal and external position occurs, CL_FIT event is triggered to signify when the mismatch is removed. CL_DELTA_P 0x5C CL_DELTA_P is a proportional controller that compensates a detected position deviation between internal and external position. See also Figure 66, page 162. In case |ENC_POS_DEV| ≤ CL_TOLERANCE, CL_DELTA_P is automatically set to 1.0. In case |ENC_POS_DEV| > CL_TOLERANCE, the closed-loop unit of TMC4361A multiplies ENC_POS_DEV with CL_DELTA_P and adds the resulting value to the current ENC_POS. Thus, a current commutation angle for higher stiffness position maintenance, which is clipped at CL_BETA, is calculated. i CL_DELTA_P consists of 24 bits. The last 16 bits represent decimal places. The final proportional term is thus calculated by: pPID = CL_DELTA_P / 65536. i Therefore, the higher pPID the faster the reaction on position deviations. NOTE:  A high pPID term can lead to oscillations that must be avoided. CL_CYCLE 0x63 (31:16) In case, one absolute encoder is connected, this value represents the delay time in numbers of clock cycles between two consecutive regulation cycles. It is recommended to adjust this value to the regulation cycle; which is either equal or slower than the encoder request rate. In case incremental ABN encoder is selected, this value is automatically set to fetch the fastest possible regulation rate; which in most cases are five clock cycles. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 New output angle 162/230 ENC_POS+90° (+256 µSteps) –CL_TOLERANCE CL_BETA p PID ENC_POS+45° (+128 µSteps) =4 ID pP = 2 pPID = 1 0° -128 (-45°) = 128 (45°) 256 (90°) 384 (135°) 2 p PID ID -256 (-90°) pP -384 (-135°) ENC_POS_DEV [µSteps] pPID = 1 =4 ENC_POS-45° (-128 µSteps) CL_TOLERANCE –CL_BETA ENC_POS-90° (-256 µSteps) Figure 66: Calculation of the Output Angle with appropriate CL_DELTA_P Enabling and calibrating Closed-Loop Operation Now that basic closed-loop control parameters are configured, as explained above, closed-loop regulation can be enabled. i The presented calibration process is very basic. Refer to the closed-loop Application Note for detailed calibration process information. In order to enable and calibrate closed-loop control, do as follows: PRECONDITION: SET TO BEST POSSIBLE MAXIMUM CURRENT SCALING PROCEED WITH: OPTION 1: CL_OFFSET IS GENERATED DURING CALIBRATION Action:  Set MSTEPS_PER_FS = 0 (STEP_CONF register 0x0A) [256 microsteps per fullstep].  Move to any fullstep position (MSCNT mod 128 = 0).  Set regulation_modus = b’01 (ENC_IN_CONF register 0x07).  Set cl_caclibration_en =1 (ENC_IN_CONF register 0x07).  Wait for a defined time span (system settle down).  Set cl_caclibration_en =0 (ENC_IN_CONF register 0x07). Result: Closed-loop operation is enabled with basic calibration. CL_OFFSET is set to position mismatch during calibration process. OR PROCEED WITH OPTION 2: CL_OFFSET IS USED FOR CALIBRATION In case CL_OFFSET was saved and no position loss has occurred while closed-loop operation was disabled, it can be used to replace the calibration process. Action:  Set MSTEPS_PER_FS = 0 (STEP_CONF register 0x0A)  256 microsteps per fullstep.  Set regulation_modus = b’01 (ENC_IN_CONF register 0x07).  Set CL_OFFSET to any preferred microstep value. Result: Closed-loop operation is enabled. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 163/230 In order to limit catch-up velocities in case a disturbance of regular motor motion must be compensated, the following parameters can be configured accordingly: Limiting Closed-Loop Catch-Up Velocity i Refer to section 16.2. on page 159 for more information about PI regulation of the maximum velocity because it uses the same PI regulator like the position PID regulator. The base velocity is the actual ramp velocity VACTUAL. CL_VMAX_CALC_P 0x5A CL_VMAX_CALC_I 0x5B PID_DV_CLIP 0x5E P parameter of the PI regulator, which controls the maximum velocity. PID_I_CLIP 0x5D This parameter is used together with PID_DV_CLIP in order to limit the velocity for error compensation. The error sum PID_ISUM is generated by the integral term. In case this error sum must be limited, set PID_I_CLIP. It is advisable to set the maximum value of PID_I_CLIP to: I parameter of the PI regulator, which controls the maximum velocity. PID_DV_CLIP can be set in order to avoid large velocity variations; and also to limit the maximum velocity deviation above the maximum velocity VMAX. PID_I_CLIP ≤ PID_DV_CLIP / PID_I. i Enabling the Limitation of the Catch-Up Velocity In case the error sum PID_ISUM is not clipped, it is increased with each time step by PID_I · PID_E. This continues as long as the motor does not follow. Now that PI control parameters and clipping values are configured, as explained above, limiting catch-up velocities can be enabled. In order to enable limitation of closed-loop catch-up velocity, do as follows: Action:  Set cl_vlimit_en = 1 (ENC_IN_CONF register 0x07). Result: Closed-loop catch-up velocity is limited according to the configured parameters. NOTE:  A higher motor velocity than specified VMAX ( for negative velocity: -VMAX) is possible if the following conditions are met: Closed-loop operation is enabled. Closed-loop catch-up velocity is not enabled, or is enabled with PID_DV_CLIP > 0; and CL_VMAX_CALC_P and CL_VMAX_CALC_I are higher than 0. ENC_POS_DEV > CL_TOLERANCE resp. ENC_POS_DEV < CL_TOLERANCE. AREAS OF SPECIAL CONCERN ! In case the internal ramp has stopped, and the position mismatch still needs to be corrected, the base velocity for catch-up velocity limitation is zero. The mismatch correction ramp is a linear deceleration ramp, independent of the specified ramp profile. This occurs because the catch-up velocity is regulated via PI regulation, as explained above. Thus, this final ramp for error compensation is a function of both ENC_POS_DEV and the PI control parameters. Turn page for information on closed-loop velocity mode. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Enabling ClosedLoop Velocity Mode 164/230 Some applications only require maintaining a specified velocity value during closedloop behavior, regardless of position mismatches. TMC4361A also provides this option. NOTE:  The closed-loop velocity mode is set independent of the internal ramp operation mode (velocity or positioning mode). In order to enable and calibrate closed-loop control, do as follows: Action:  Set the catch-up velocity parameters, as explained in detail in section 16.3.3, page 163.  Set cl_vlimit_en = 1 (ENC_IN_CONF register 0x07).  Set cl_velocity_mode_en = 1 (ENC_IN_CONF register 0x07). Result: Closed-loop operation velocity mode is enabled. In case position mismatch |ENC_POS_DEV| exceeds 768 microsteps, internal position counter XACTUAL is set automatically to ENC_POS ± 768 to limit the position mismatch. Thus, closed-loop operation maintains the specified velocity value VMAX. i A higher motor velocity than specified VMAX (for negative velocity: -VMAX ) is possible if PID_DV_CLIP > 0. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 165/230 Closed-loop Scaling In order to save energy, current scaling can be adjusted according to actual load during closedloop operation. Closed-Loop Scaling Configuration and Enabling Closed-loop scaling slightly alters the use of the scaling register while remaining consistent in its use of internal scaling and the transmission to the stepper drivers: 1. Closed-loop scaling uses the same scaling register that is also used for open-loop configuration, as explained in chapter 11, page 120. However, the specified values that are used – and thus are also named – differently. 2. Internal scaling of MSLUT current values and transfer of these values to the motor stepper drivers function exactly in the same way as explained in chapter 10, page 87. In order to configure and enable closed-loop scaling, do as follows: Action:  Set proper CL_IMIN (SCALE_VALUES register 0x06).  Set proper CL_IMAX (SCALE_VALUES register 0x06).  Set proper CL_START_UP (SCALE_VALUES register 0x06).  Set SCALE_VALUES (31:24) to 0.  Set closed_loop_scale_en = 1 (CURRENT_CONF register 0x05). Result: As soon as closed-loop scaling is enabled, all other open-loop scaling options are automatically disabled. The following scaling situations are possible: 1. In case |ENC_POS_DEV| ≤ CL_START_UP, current values are scaled with CL_IMIN. 2. In case |ENC_POS_DEV| > CL_START_UP and |ENC_POS_DEV| ≤ CL_BETA, current values are scaled with a factor that increases linearly from CL_IMIN to CL_IMAX. 3. In case |ENC_POS_DEV| > CL_BETA, current values are scaled with CL_IMAX. The chart below identifies the actual scaling parameter SCALE_PARAM, which is dependent on the above described situations: XACTUAL SCALE_PARAM CL_IMAX CL_IMIN ENC_POS_DEV [µSteps] -384 (-135°) -256 (-90°) -128 (-45°) 0° 128 (45°) 256 (90°) 384 (135°) –CL_START_UP CL_START_UP –CL_BETA CL_BETA Figure 67: Closed-Loop Current Scaling Turn page for information about adaptations on the scaling transformation process during closed-loop operation. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Closed-Loop Scaling Transition Process Control 166/230 Transition from one scale value to the next active value can be configured as slight conversion. Two different parameters can be set in order to convert to higher or lower closed-loop current scale values, as depicted in the chart below. In order to configure a smooth transition from a lower motion current scaling value to a higher motion current scaling value, do as follows: Action:  Set CL_UPSCALE_DELAY register 0x18 according to the delay period after which the actual scale parameter is increased by one step towards the higher current scale value. Result: Whenever a higher current scale value is assigned internally, the actual scale parameter is increased by one step per CL_UPSCALE_DELAY clock cycles until the assigned scale parameter is reached. i If CL_UPSCALE_DELAY = 0, the higher current scaling value is immediately assigned whenever the corresponding current scaling phase is activated. In order to configure a smooth transition from a higher motion current scaling value to a lower motion current scaling value, do as follows: Action:  Set CL_DNSCALE_DELAY register 0x19 according to the delay period after which the actual scale parameter is decreased by one step towards the lower current scale value. Result: Whenever a lower current scale value is assigned internally, the actual scale parameter is decreased by one step per CL_DNSCALE_DELAY clock cycles until the assigned scale parameter is reached. i If CL_DNSCALE_DELAY = 0, the lower current scaling value is immediately assigned whenever the corresponding current scaling phase is activated. SCALE_PARAM AL E_ _U PS C CL 0 Y> A EL _D E AL Actual Current Scale Target Value Actual Current Scale Value CL_IMIN CL _D NS =0 LAY _DE ALE C PS U _ CL C DNS CL _ DE LA Y= 0 CL_IMAX 0 CA LE _D EL A Y> 0 t Figure 68: Closed-Loop Current Scaling Timing Behavior © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 167/230 Back-EMF Compensation during Closed-loop Operation When higher velocities are reached, a phase shift between current and voltage occurs at the motor coils. Consequently, current control is transformed into voltage control. This motor- and setup-dependent effect must be compensated because currents are still continuously assigned for motor control. TMC4361A attributes γ-correction to the compensation process, which adds a velocity-dependent angle - in motion direction - to the current commutation angle. Load Angle Calculation Gamma correction constantly adds one compensation angle, GAMMA, to the actual commutation angle; because the velocity-dependent amount of the influence of BackEMF, GAMMA is also velocity-dependent. Thus, velocity limits are assigned. These limits are based on REAL motor velocity V_ENC (register 0x65). The value of the motor velocity is internally calculated and can be filtered (V_ENC_MEAN register 0x66) to smoothen the γ-correction, which is explained in the next section. In order to configure and enable Back-EMF compensation during closedloop operation, do as follows: Action:  Set proper CL_GAMMA register 0x1C.  Set proper CL_VMIN_EMF register 0x60.  Set proper CL_VMAX_EMF register 0x61.  Set cl_emf_en = 1 (ENC_IN_CONF register 0x07). Result: Back-EMF compensation during closed-loop operation is enabled. CL_GAMMA represents the maximum value of GAMMA. Per default, CL_GAMMA is set to its maximal possible value of 255, which represents a 90° angle. The following compensation situations are possible: 1. In case |V_ENC_MEAN| ≤ CL_VMIN_EMF, GAMMA is set to 0. 2. In case |V_ENC_MEAN| > CL_VMIN_EMF and |V_ENC_MEAN| ≤ (CL_VMIN_EMF + CL_VADD_EMF), GAMMA is scaled linearly between 0 and its maximum value. 3. In case |V_ENC_MEAN| > (CL_VMIN_EMF + CL_VADD_EMF), GAMMA = CL_GAMMA. The chart below identifies the actual parameter GAMMA, which is dependent on the above described situations: Areas of Special Concern ! If γ-correction is turned on, the maximum possible commutation is (CL_BETA + CL_GAMMA ). This value must not exceed 180° (511 microsteps at 256 microsteps per fullstep) because angles of 180° or more will result in unwanted motion direction changes. GAMMA CL_VADD_EMF Usually 255 (=90°) CL_GAMMA CL_VMIN_EMF V_ENC_MEAN Figure 69: Calculation of the actual Load Angle GAMMA © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 168/230 Encoder Velocity Readout Parameters In case an encoder is connected, REAL motor velocity can be read out. The actual encoder velocity flickers. This is system-immanent. TMC4361A provides filter options that back-EMF compensation is based on. The following velocity parameters can be read out. V_ENC 0x65 Actual encoder velocity in pulses (microsteps) per second [pps]. V_ENC_MEAN 0x66 Actual filtered encoder velocity in pulses (microsteps) per second [pps]. In order to set filter parameters correctly, consider the following details: Encoder Velocity Filter Configuration ENC_VMEAN_WAIT 0x63 (7:0) ENC_VMEAN_WAIT represents the delay period in number of clock cycles between two consecutive V_ENC values that are used for the encoder filter velocity calculation. The lower this value, the faster the adaptation process of V_ENC_MEAN is. Accordingly: The higher the gradient of V_ENC_MEAN is. In case incremental ABN encoders are connected, ENC_VMEAN_WAIT must be set above 32. In case absolute encoders are connected, ENC_VMEAN_WAIT is automatically set to SER_PTIME. ENC_VMEAN_FILTER 0x63 (11:8) This filter exponent is used for filter calculations. The lower this value, the faster the adaptation process of V_ENC_MEAN is. Accordingly: The higher the gradient of V_ENC_MEAN is. Every ENC_VMEAN_WAIT clock cycles, the following calculation applies: 𝑉𝐸𝑁𝐶𝑀𝐸𝐴𝑁 = VENCMEAN − ENC_VMEAN_INT 0x63 (31:16) Encoder Velocity equals 0 Event VENCMEAN 𝐸𝑁𝐶_𝑉𝑀𝐸𝐴𝑁_𝐹𝐼𝐿𝑇𝐸𝑅 2 + V𝐸𝑁𝐶 2𝐸𝑁𝐶_𝑉𝑀𝐸𝐴𝑁_𝐹𝐼𝐿𝑇𝐸𝑅 The refresh frequency of high encoder velocity values V_ENC is determined by this encoder velocity update period. In case incremental ABN encoders are connected, the minimum value of ENC_VMEAN_INT is automatically set to 256. In case absolute encoders are connected, ENC_VMEAN_INT is automatically adapted to encoder value request rate. Because internal calculation of low V_ENC values is triggered by AB signal changes and not by the refresh frequency defined by ENC_VMEAN_INT, any occurring idle state of the encoder is not recognized. In order to determine that V_ENC = 0, it is possible to limit the number of clock cycles while no AB signal changes occur; which then signifies encoder idle state. In order to evoke encoder idle state, do as follows: Action:  Set proper ENC_VEL_ZERO register 0x62. Result: In case no AB signal changes occur during ENC_VEL_ZERO clock cycles, ENC_VEL0 event is triggered, which indicates encoder idle state. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 169/230 17. Reset and Clock Gating In addition to the hardware reset pin NRST and the automatic Power-on-Reset procedure, TMC4361A provides a software reset option. If not in operation, clock gating can be used to reduce power consumption. Reset and Clock Pins Pin Names Types Remarks NRST Input Low active hardware reset. STPIN Input High active wake-up signal. CLK_EXT Input Connected external clock signal. Table 61: Dedicated Reset and Clock Pins Reset and Clock Gating Registers Register Name Register address Remarks GENERAL_CONF 0x00 RW Bit18:17 CLK_GATING_DELAY 0x14 RW Dela time before clock gating is enabled. CLK_GATING_REG 0x4F (2:0) RW Trigger for clock gating. RESET_REG 0x4F (31:8) RW Trigger for SW-Reset. Table 62: Dedicated Reset and Clock Gating Registers A hardware reset is provided by the NRST input pin. Manual Hardware Reset In order to reset TMC4361A, do as follows: Action:  Set NRST input to low voltage level. Result: TMC4361A registers are reset to default values. NOTE:  During power-up of TMC4361A, Power-on-Reset is executed automatically. Manual Software Reset In order to reset TMC4361A without use of NRST pin, do as follows: Action:  Set RESET_REG = 0x525354 (Bits31:8 of register 0x4F). Result: TMC4361A registers are reset to default values. NOTE:  A software reset can be activated in all cases, except for one:  Due to safety reasons, only hardware resets are available during the FROZEN event to overcome this freeze condition (see chapter 12, page 128). Reset Indication RST_EV = EVENTS(31) is set as indicator signifying that one of the possible reset conditions was triggered. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Activating Clock Gating manually 170/230 Clock gating must be enabled before activation. In addition, the delay between activation and the active clock gating phase can be configured. In order to activate clock gating manually, do as follows: PRECONDITION: VEL_STATE_F = “00” INDICATING THAT VACTUAL = 0. Action:  Set clk_gating_en = 1 (bit17 of GENERAL_CONF register 0x00).  Set proper CLK_GATING_DELAY register 0x14.  Set CLK_GATING_REG = 0x7 (bit2:0 of register 0x4F). Result: When writing to CLK_GATING_REG, this activates the CLK_GATING_DELAY counter, which specifies the delay between clock gating trigger and activation in [number of cycles]. When the counter reaches 0, clock gating is activated. See figure below. NOTE :  In case CLK_GATING_REG = 0, clock gating is executed immediately after activating the CLK_GATING_REG register. See figure below. In order to conduct clock gating wake-up, do as follows: Clock Gating Wake-up Action:  Set STPIN input pin to high voltage level. Result: Clock-gating is terminated. See figure below. If SPI datagram transfers from microcontroller to TMC4361A prompt wakeup, do as follows: Action:  Set CLK_GATING_DELAY = 0xFFFFFFFF (register 0x14).  Set CLK_GATING_REG = 0x0 (bit2:0 of register 0x4F).  Set CLK_GATING_REG = 0x7 (bit2:0 of register 0x4F).  Set clk_gating_en = 0 (bit17 of GENERAL_CONF register 0x00). Result: Clock-gating is terminated. External clk signal SPI Inputs CLK_GATING_REG =111 CLK_GATING_DELAY =5 CLK_GATING_REG =111 Clock gating delay timer STPIN input signal Internal clk signal Figure 70: Manual Clock Gating Activation and Wake-Up © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 171/230 It is possible to use TMC4361A standby phase to automatically activate clock gating. Automatic Clock Gating Procedure i For further information about standby timer, see section 11.1. , page 121. In order to activate automatic clock gating, do as follows: Action:  Set the time frame for STDBY_DEALY register 0x15 after ramp stop, and before standby phase starts.  Set hold_current_scale_en = 1 (CURRENT_CONF register 0x05).  Set closed_loop_scale_en = 0 (CURRENT_CONF register 0x05).  Set clk_gating_en = 1 (bit17 of GENERAL_CONF register 0x00).  Set proper CLK_GATING_DELAY register 0x14.  Set clk_gating_stdby_en = 1 (bit17 of GENERAL_CONF register 0x00). Result: After standby phase activation, activation of clock gating counter follows. When the counter reaches 0, clock gating is activated. In addition, the start signal generation, presented in chapter 9, page 69, can be used for an automated wake-up. An example is given in the figure below. The chart below shows the TARGET_REACHED (=TR) signal, which signifies ramp stop at which VACTUAL reaches 0. When VACTUAL = 0, the following process occurs: 1. The start delay timer signifies the time frame between ramp stop and next ramp start. 2. When the standby delay timer expires, the standby phase is activated. 3. When the standby phase is activated, the clock gating delay timer is started. 4. After the clock gating delay timer expires, clock gating is activated. 5. Shortly before the start delay timer expires, clock gating is disabled, which occurs so that the next ramp is started with proper assigned registers. External clk signal TR START_DELAY START delay timer Stdby delay timer Clock gating delay timer STDBY_DELAY CLK_GATING_DELAY Internal clk signal Figure 71: Automatic Clock Gating Activation and Wake-Up © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 172/230 18. Serial Encoder Output TMC4361A provides an option to render internal encoder data into absolute SSI encoder data. This encoder data is streamed via the SPI output interface. Pin Names for SPI Motor Drive Pin Names Type Remarks NSCSDRV_SDO Output Serial data output. SCKDRV_NSDO Output Negated serial data output. SDODRV_SCLK InOut as Input Serial clock input. SDIDRV_NSCLK Input Negated serial clock input. Table 63: Pin Names for Encoder Output Interface Register Names for SPI Output Registers Register Name Register Address Remarks GENERAL_CONF 0x00 RW Affect switches: Bit25:24. SSI_OUT_MTIME 0x04 RW Bit24:4: Monoflop time. ENC_IN_CONF 0x07 RW Affect switches: Bit14, Bit30. ENC_OUT_DATA 0x09 RW Encoder output data structure. ENC_OUT_RES 0x55 W Resolution of singleturn data. Table 64: Dedicated SPI Output Registers This topic is continued on the following page. Please turn page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 173/230 The internal [microstep] value of the external position ENC_POS 0x50 can be transferred to a serial data stream using the SPI output interface. SSI output format and structure can be configured freely. Configuration and Enabling of SSI Output Interface In order to provide SSI output data at the SPI output interface, do as follows: Action:  Set encoder resolution in register ENC_OUT_RES 0x55 (write access).  Set SINGLE_TURN_RES_OUT (Bit4:0 of ENC_OUT_DATA register 0x09) to the number of singleturn data bits – 1. OPTIONAL: IF MULTITURN DATA MUST BE TRANSMITTED  Set MULTI_TURN_RES_OUT (Bit9:5 of ENC_OUT_DATA register 0x09) to the number of multiturn data bits – 1.  Set multi_turn_out_en = 1 (Bit14 of ENC_IN_CONF register 0x07).  Set proper SSI_MTIME register 0x04(23:4).  Set serial_enc_out_enable = 1 (Bit24 of GENERAL_CONF register 0x00). Result: Differential SSI output data is streamed via SPI output interface:  Master clock input pin is SDODRV_SCLK  Negated clock input pin is SDIDRV_NSCLK.  NSCSDRV_SDO acts as serial data output  Negated data output is SCKDRV_NSDO.  Output data remains unchanged until SSI_OUT_MTIME clock cycles expires after the last master request to support multicycle data requests. The angle of the singleturn data is calculated considering the external position ENC_POS and the requested encoder resolution ENC_OUT_RES. The number of singleturn bits is equal to SINGLE_TURN_RES_OUT + 1. If multiturn data must be transferred, the number of revolutions is also calculated and transmitted as signed number before singleturn data bits follow. The number of multiturn bits is equal to MULTI_TURN_RES_OUT + 1. An example is provided below: SSI output stream consists of five multiturn bits (MULTI_TURN_RES_OUT = 4) and seven singleturn bits (SINGLE_TURN_RES_OUT = 6) that follow each other successively in one data stream. SDODRV_SCLK SDIDRV_NSCLK NSCSDRV_SDO SCKDRV_NSDO MSBM LSBM MSBS LSBS MSBM LSBM MSBS LSBS Figure 72: Example for SSI Output Configuration: M - Multiturn; S - Singleturn  Turn page for information on additional configuration options. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Disabling differential Encoder Output Signals 174/230 Regular SSI operation makes use differential signals. Thus, TMC4361A expects digital differential serial clock input signals. In order to disable the digital differential output signals, do as follows: Action:  Set serial_enc_out_diff_disable = 1 (Bit25 of GENERAL_CONF register 0x00). Result: Dedicated encoder signals are treated as single signals and every negated pin is ignored. TMC4361A is able to gray-encode SSI data automatically. Gray-encoded SSI Output Data In order to enable gray-encoded SSI output data, do as follows: Action:  Set enc_out_gray =1 (Bit30 of ENC_IN_CONF register 0x07). Result: Encoder data output is gray-encoded. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 175/230 T E C H NI C A L S P E C I F I C AT I O NS 19. Complete Register and Switches List General Configuration Register GENERAL_CONF 0x00 GENERAL_CONF 0x00 (Default value: 0x00006020) R/W Bit Val Remarks use_astart_and_vstart 0 (only valid for S-shaped ramps) 0 Sets AACTUAL = AMAX or –AMAX at ramp start and in the case of VSTART ≠ 0. 1 Sets AACTUAL = ASTART or –ASTART at ramp start and in the case of VSTART ≠ 0. direct_acc_val_en 1 0 Acceleration values are divided by CLK_FREQ. 1 Acceleration values are set directly as steps per clock cycle. direct_bow_val_en 2 0 Bow values are calculated due to division by CLK_FREQ. 1 Bow values are set directly as steps per clock cycle. step_inactive_pol 3 0 STPOUT = 1 indicates an active step. 1 STPOUT = 0 indicates an active step. toggle_step 4 0 Only STPOUT transitions from inactive to active polarity indicate steps. 1 Every level change of STPOUT indicates a step. pol_dir_out RW 5 0 DIROUT = 0 indicates negative direction. 1 DIROUT = 1 indicates negative direction. sdin_mode 7:6 0 Internal step control (internal ramp generator will be used) 1 External step control via STPIN / DIRIN interface with high active steps at STPIN 2 External step control via STPIN / DIRIN interface with low active steps at STPIN 3 External step control via STPIN / DIRIN interface with toggling steps at STPIN pol_dir_in 8 0 DIRIN = 0 indicates negative direction. 1 DIRIN = 1 indicates negative direction. sd_indirect_control 9 0 STPIN/DIRIN input signals will manipulate internal steps at XACTUAL directly. 1 STPIN/DIRIN input signals will manipulate XTARGET register value, the internal ramp generator is used. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 176/230 GENERAL_CONF 0x00 (Default value: 0x00006020) R/W Bit Val Remarks serial_enc_in_mode 11:10 0 An incremental encoder is connected to encoder interface. 1 An absolute SSI encoder is connected to encoder interface. 2 Reserved 3 An absolute SPI encoder is connected to encoder interface. diff_enc_in_disable 12 0 Differential encoder interface inputs enabled. 1 Differential encoder interface inputs is disabled (automatically set for SPI encoder). stdby_clk_pin_assignment 14:13 0 Standby signal becomes forwarded with an active low level at STDBY_CLK output. 1 Standby signal becomes forwarded with an active high level at STDBY_CLK output. 2 STDBY_CLK passes ChopSync clock (TMC23x, TMC24x stepper motor drivers only). 3 Internal clock is forwarded to STDBY_CLK output pin. intr_pol 15 RW 0 INTR=0 indicates an active interrupt. 1 INTR=1 indicates an active interrupt. invert_pol_target_reached 16 0 TARGET_REACHED signal is set to 1 to indicate a target reached event. 1 TARGET_REACHED signal is set to 0 to indicate a target reached event. clk_gating_en 17 0 Clock gating is disabled. 1 Internal clock gating is enabled. clk_gating_stdby_en 18 0 No clock gating during standby phase. 1 Intenal clock gating during standby phase is enabled. fs_en 19 0 Fullstep switchover is disabled. 1 SPI output forwards fullsteps, if |VACTUAL| > FS_VEL. fs_sdout 20 0 No fullstep switchover for Step/Dir output is enabled. 1 Fullsteps are forwarded via Step/Dir output also if fullstep operation is active. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 177/230 GENERAL_CONF 0x00 (Default value: 0x00006020) R/W Bit Val Remarks dcstep_mode 22:21 0 dcStep is disabled. 1 dcStep signal generation will be selected automatically 2 dcStep with external STEP_READY signal generation (TMC2130). 3 dcStep with internal STEP_READY signal generation (TMC26x). i TMC26x config: use const_toff-Chopper (CHM = 1); slow decay only (HSTRRT = 0); TST = 1 and SGT0=SGT1=1 (on_state_xy). pwm_out_en 23 0 PWM output is disabled. Step/Dir output is enabled at STPOUT/DIROUT. 1 STPOUT/DIROUT output pins are used as PWM output (PWMA/PWMB). serial_enc_out_enable 24 0 No encoder is connected to SPI output. 1 SPI output is used as SSI encoder interface to forward absolute SSI encoder data. serial_enc_out_diff_disable 25 0 Differential serial encoder output is enabled. 1 Differential serial encoder output is disabled. automatic_direct_sdin_switch_off RW 26 0 1 VACTUAL=0 & AACTUAL=0 after switching off direct external step control. VACTUAL = VSTART and AACTUAL = ASTART after switching off direct external step control. circular_cnt_as_xlatch 27 0 The register value of X_LATCH is forwarded at register 0x36. 1 The register value of REV_CNT (#internal revolutions) is forwarded at register 0x36. reverse_motor_dir 28 0 The direction of the internal SinLUT is regularly used. 1 The direction of internal SinLUT is reversed intr_tr_pu_pd_en 29 0 INTR and TARGET_REACHED are outputs with strongly driven output values.. 1 INTR and TARGET_REACHED are used as outputs with gated pull-up and/or pull-down functionality. intr_as_wired_and 30 0 INTR output function is used as Wired-Or in the case of intr_tr_pu_pd_en = 1. 1 INTR output function is used as Wired-And. in the case of intr_tr_pu_pd_en = 1. tr_as_wired_and 31 0 1 TARGET_REACHED output function is used as Wired-Or in the case of intr_tr_pu_pd_en = 1. TARGET_REACHED output function is used as Wired-And in the case of intr_tr_pu_pd_en = 1. Table 65: General Configuration 0x00 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 178/230 Reference Switch Configuration Register REFERENCE_CONF 0x01 REFERENCE_CONF 0x01 (Default value: 0x00000000) R/W Bit Val Remarks stop_left_en 0 0 STOPL signal processing disabled. 1 STOPL signal processing enabled. stop_right_en 1 0 STOPR signal processing disabled. 1 STOPR signal processing enabled. pol_stop_left 2 0 STOPL input signal is low active. 1 STOPL input signal is high active. pol_stop_right 3 0 STOPR input signal is low active. 1 STOPR input signal is high active. invert_stop_direction 4 0 STOPL/STOPR stops motor in negative/positive direction. 1 STOPL/STOPR stops motor in positive/negative direction. soft_stop_en 5 RW 0 Hard stop enabled. VACTUAL is immediately set to 0 on any external stop event. 1 Soft stop enabled. A linear velocity ramp is used for decreasing VACTUAL to v = 0. virtual_left_limit_en 6 0 Position limit VIRT_STOP_LEFT disabled. 1 Position limit VIRT_STOP_LEFT enabled. virtual_right_limit_en 7 0 Position limit VIRT_STOP_RIGHT disabled. 1 Position limit VIRT_STOP_RIGHT enabled. virt_stop_mode 9:8 0 Reserved. 1 Hard stop: VACTUAL is set to 0 on a virtual stop event. 2 Soft stop is enabled with linear velocity ramp (from VACTUAL to v = 0). 3 Reserved. latch_x_on_inactive_l 10 0 No latch of XACTUAL if STOPL becomes inactive. 1 X_LATCH = XACTUAL is stored in the case STOPL becomes inactive. latch_x_on_active_l 11 0 No latch of XACTUAL if STOPL becomes active. 1 X_LATCH = XACTUAL is stored in the case STOPL becomes active. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 179/230 REFERENCE_CONF 0x01 (Default value: 0x00000000) R/W Bit Val Remarks latch_x_on_inactive_r 12 0 No latch of XACTUAL if STOPR becomes inactive. 1 X_LATCH = XACTUAL is stored in the case STOPL becomes inactive. latch_x_on_active_r 13 0 No latch of XACTUAL if STOPR becomes active. 1 X_LATCH = XACTUAL is stored in the case STOPL becomes active. stop_left_is_home 14 0 STOPL input signal is not also the HOME position. 1 STOPL input signal is also the HOME position. stop_right_is_home 15 0 STOPR input signal is not lso the HOME position. 1 STOPR input signal is also the HOME position. home_event 0 Next active N event of connected ABN encoder signal indicates HOME position. 2 HOME_REF = 1 indicates an active home event X_HOME is located at the rising edge of the active range. 3 HOME_REF = 0 indicates negative region/position from the home position. 4 RW 19:16 6 9 11 HOME_REF = 1 indicates an active home event X_HOME is located at the falling edge of the active range. HOME_REF = 1 indicates an active home event X_HOME is located in the middle of the active range. HOME_REF = 0 indicates an active home event X_HOME is located in the middle of the active range. HOME_REF = 0 indicates an active home event X_HOME is located at the rising edge of the active range. 12 HOME_REF = 1 indicates negative region/position from the home position. 13 HOME_REF = 0 indicates an active home event X_HOME is located at the falling edge of the active range. start_home_tracking 20 0 No storage to X_HOME by passing home position. 1 Storage of XACTUAL as X_HOME at next regular home event. An XLATCH_DONE event is released. In case the event is cleared, start_home_tracking is reset automatically. clr_pos_at_target 21 0 Ramp stops at XTARGET if positioning mode is active. 1 Set XACTUAL = 0 after XTARGET has been reached. The next ramp starts immediately. circular_movement_en 22 0 Range of XACTUAL is not limited: -231 ≤ XACTUAL ≤ 231-1 1 Range of XACTUAL is limited by X_RANGE: -X_RANGE ≤ XACTUAL ≤ X_RANGE - 1 Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 180/230 REFERENCE_CONF 0x01 (Default value: 0x00000000) R/W Bit Val Remarks pos_comp_output 24:23 0 TARGET_REACHED is set active on TARGET_REACHED_Flag. 1 TARGET_REACHED is set active on VELOCITY_REACHED_Flag. 2 TARGET_REACHED is set active on ENC_FAIL flag. 3 TARGET_REACHED triggers on POSCOMP_REACHED_Flag. pos_comp_source 25 0 POS_COMP is compared to internal position XACTUAL. 1 POS_COMP is compared with external position ENC_POS. stop_on_stall 26 0 SPI and S/D output interface remain active in case of an stall event. 1 SPI and S/D output interface stops motion in case of an stall event (hard stop). drv_after_stall 27 RW 29:28 0 No further motion in case of an active stop-on-stall event. 1 Motion is possible in case of an active stop-on-stall event and after the stop-on-stall event is reset. modified_pos_compare: POS_COMP_REACHED_F / event is based on comparison between XACTUAL resp. ENC_POS and 0 POS_COMP 1 X_HOME 2 X_LATCH resp. ENC_LATCH 3 REV_CNT automatic_cover 30 0 SPI output interface will not transfer automatically any cover datagram. 1 SPI output interface sends automatically cover datagrams when VACTUAL crosses SPI_SWITCH_VEL. circular_enc_en 31 0 Range of ENC_POS is not limited: -231 ≤ ENC_POS ≤ 231-1 1 Range of ENC_POS is limited by X_RANGE: -X_RANGE ≤ ENC_POS ≤ X_RANGE –1 Table 66: Reference Switch Configuration 0x01 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 181/230 Start Switch Configuration Register START_CONF 0x02 START_CONF 0x02 (Default value: 0x00000000) R/W Bit Val Remarks start_en xxxx1 Alteration of XTARGET value requires distinct start signal. 4:0 xxx1x Alteration of VMAX value requires distinct start signal. xx1xx Alteration of RAMPMODE value requires distinct start signal. x1xxx Alteration of GEAR_RATIO value requires distinct start signal. 1xxxx Shadow Register Feature Set is enabled. trigger_events 8:5 0000 Timing feature set is disabled because start signal generation is disabled. xxx0 START pin is assigned as output. xxx1 External start signal is enabled as timer trigger. START pin is assigned as input. xx1x TARGET_REACHED event is assigned as start signal trigger. x1xx VELOCITY_REACHED event is assigned as start signal trigger. 1xxx POSCOMP_REACHED event is assigned as start signal trigger. pol_start_signal 9 0 START pin is low active (input resp. output). 1 START pin is high active (input resp. output). immediate_start_in RW 10 0 Active START input signal starts internal start timer. 1 Active START input signal is executed immediately. busy_state_en 11 0 START pin is only assigned as input or output. 1 Busy start state is enabled. START pin is assigned as input with a weakly driven active start polarity or as output with a strongly driven inactive start polarity. pipeline_en 15:12 0000 No pipelining is active. xxx1 X_TARGET is considered for pipelining. xx1x POS_COMP is considered for pipelining. x1xx GEAR_RATIO is considered for pipelining. 1xxx GENERAL_CONF is considered for pipelining. shadow_option 17:16 0 Single-level shadow registers for 13 relevant ramp parameters. 1 Double-stage shadow registers for S-shaped ramps. 2 Double-stage shadow registers for trapezoidal ramps (excl. VSTOP). 3 Double-stage shadow registers for trapezoidal ramps (excl. VSTART). Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 182/230 START_CONF 0x02 (Default value: 0x00000000) R/W Bit Val Remarks cyclic_shadow_regs 18 19 0 Current ramp parameters are not written back to the shadow register. 1 Current ramp parameters are written back to the appropriate shadow register. Reserved. Set to 0. SHADOW_MISS_CNT 23:20 U Number of unused start internal start signals between two consecutive shadow register transfers. XPIPE_REWRITE_REG Current assigned pipeline registers – START_CONF(15:12) – are written back to X_PIPEx in the case of an internal start signal generation and if assigned in this register with a ‘1’: RW 31:24 XPIPE_REWRITE_REG(0) XPIPE_REWRITE_REG(1) XPIPE_REWRITE_REG(2) XPIPE_REWRITE_REG(3) XPIPE_REWRITE_REG(4) XPIPE_REWRITE_REG(5) XPIPE_REWRITE_REG(6) XPIPE_REWRITE_REG(7)         X_PIPE0 X_PIPE1 X_PIPE2 X_PIPE3 X_PIPE4 X_PIPE5 X_PIPE6 X_PIPE7 Ex.: START_CONF(15:12) = b’0011. START_CONF(31:24) = b’01000010. If an internal start signal is generated, the value of X_TARGET is written back to X_PIPE1, whereas the value of POS_COMP is written back to X_PIPE6. Table 67: Start Switch Configuration START_CONF 0x02 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 183/230 Input Filter Configuration Register INPUT_FILT_CONF 0x03 INPUT_FILT_CONF 0x03 (Default value: 0x00000000) R/W Bit Val Remarks SR_ENC_IN 2:0 3 U Input sample rate = fclk / 2SR_ENC_IN for the following pins: A_SCLK, ANEG_NSCLK, B_SDI, BNEG_NSDI, N, NNEG Reserved. Set to 0. FILT_L_ENC_IN 6:4 U Filter length for these pins: A_SCLK, ANEG_NSCLK, B_SDI, BNEG_NSDI, N, NNEG. Number of sample input bits that must have equal voltage levels to provide a valid input bit. SD_FILT0 7 10:8 11 0 S/D input pins (STPIN/DIRIN) are not assigned to the ENC_IN input filter group. 1 S/D input pins (STPIN/DIRIN) are also assigned to the ENC_IN input filter group. SR_REF U Input sample rate = fclk / 2REF for the following pins: STOPL, HOME_REF, STOPL Reserved. Set to 0. FILT_L_REF 14:12 U Filter length for the following pins: STOPL, HOME_REF, STOPL. Number of sample input bits that must have equal voltage levels to provide a valid input bit. SD_FILT1 15 RW 18:16 19 0 S/D input pins (STPIN/DIRIN) are not assigned to the REF input filter group. 1 S/D input pins (STPIN/DIRIN) are also assigned to the REF input filter group. SR_S U Input sample rate = fclk / 2S for the START pin. Reserved. Set to 0. FILT_L_S 22:20 U Filter length for the START pin. Number of sample input bits that must have equal voltage levels to provide a valid input bit. SD_FILT2 23 26:24 27 0 S/D input pins (STPIN/DIRIN) are not assigned to the S input filter group. 1 S/D input pins (STPIN/DIRIN) are also assigned to the S input filter group. SR_ENC_OUT U Input sample rate = fclk / 2SR_ENC_OUT for these pins: SDODRV_SCLK, SDIDRV_NSCLK Reserved. Set to 0. FILT_L_ENC_OUT 30:28 U Filter length for the following pins: SDODRV_SCLK, SDIDRV_NSCLK. Number of sample input bits that must have equal voltage levels to provide a valid input bit. SD_FILT3 31 0 S/D input pins (STPIN/DIRIN) are not assigned to the ENC_OUT input filter group. 1 S/D input pins (STPIN/DIRIN) are assigned to the ENC_OUT input filter group. Table 68: Input Filter Configuration Register INPUT_FILT_CONF 0x03 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 184/230 SPI Output Configuration Register SPI_OUT_CONF 0x04 SPI_OUT_CONF 0x04 (Default value: 0x00000000) R/W Bit Val Remarks spi_output_format 0 1 2 3 4 3:0 5 6 SPI output interface is connected with a SPI-DAC. SPI output values are mapped to full amplitude: Current=0  VCC/2 Current=-max  0 Current=max  VCC SPI output interface is connected with a SPI-DAC. SPI output values are absolute values. Phase of coilA is forwarded via STPOUT, whereas phase of coilB is forwarded via DIROUT. Phase bit = 0:positive value. SPI output interface is connected with a SPI-DAC. SPI output values are absolute values. Phase of coilA is forwarded via STPOUT, whereas phase of coilB is forwarded via DIROUT. Phase bit = 0: negative value. The actual unsigned scaling factor is forwarded via SPI output interface. Both actual signed current values CURRENTA and CURRENTB are forwarded in one datagram via SPI output interface. SPI output interface is connected with a SPI-DAC. The actual unsigned scaling factor is merged with DAC_ADDR_A value to an output datagram. 8 SPI output interface is connected with a TMC23x stepper motor driver. 9 SPI output interface is connected with a TMC24x stepper motor driver. 10 11 RW SPI output interface is off. 12 13 15 SPI output interface is connected with a TMC26x/389 stepper motor driver. Configuration and current data are transferred to the stepper motor driver. SPI output interface is connected with a TMC26x stepper motor driver. Only configuration data is transferred to the stepper motor driver. S/D output interface provides steps. SPI output interface is connected with a TMC2130 stepper motor driver. Only configuration data is transferred to the stepper motor driver. S/D output interface provides steps. SPI output interface is connected with a TMC2130 stepper motor driver. Configuration and current data are transferred to the stepper motor driver. Only cover datagrams are transferred via SPI output interface. COVER_DATA_LENGTH 19:13 23:20 27:24 U Number of bits for the complete datagram length. Maximum value = 64 Set to 0 in case a TMC stepper motor driver is selected. The datagram length is then selected automatically. SPI_OUT_LOW_TIME U Number of clock cycles the SPI output clock remains at low level. SPI_OUT_HIGH_TIME U Number of clock cycles the SPI output clock remains at high level. SPI_OUT_BLOCK_TIME 31:28 U Number of clock cycles the NSCSDRV output remains high (inactive) after a SPI output transmission. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 185/230 SPI_OUT_CONF 0x04 (Default value: 0x00000000) R/W Bit Val Remarks mixed_decay 5:4 (TMC23x/24x only) 0 Both mixed decay bits are always off. 1 Mixed decay bits are on during falling ramps until reaching a current value of 0. 2 Mixed decay bits are always on, except during standstill. 3 Mixed decay bits are always on. stdby_on_stall_for_24x 6 (TMC24x only) 0 No standby datagram is sent. 1 In case of a Stop-on-Stall event, a standby datagram is sent to the TMC24x. stall_flag_instead_of_uv_en 7 (TMC24x only) 0 Undervoltage flag of TMC24x is mapped at STATUS(24). 1 Calculated stall status of TMC24x is forwarded at STATUS(24). STALL_LOAD_LIMIT 10:8 U (TMC24x only) A stall is detected if the stall limit value STALL_LOAD_LIMIT is higher than the combination of the load bits (LD2&LD1&LD0). pwm_phase_shft_en 11 (TMC24x only) 0 No phase shift during PWM mode. 1 During PWM mode, the internal SinLUT microstep position MSCNT is shifted to MS_OFFSET microsteps. Consequently, the sine/cosine values have a phase shift of (MS_OFFSET / 1024 ∙ 360°) double_freq_at_stdby RW 12 (TMC23x/24x only) 0 ChopSync frequency remains stable during standby. 1 CHOP_SYNC_DIV is halfed during standby. three_phase_stepper_en 4 (TMC389 only) 0 A 2-phase stepper motor driver is connected to the SPI output (TMC26x). 1 A 3-phase stepper motor driver is connected to the SPI output (TMC389). scale_val_transfer_en 5 (TMC26x/2130 in SD mode only) 0 No transfer of scale values. 1 Transmission of current scale values to the appropriate driver registers. disable_polling 6 (TMC26x/2130 in SD mode only) 0 Permanent transfer of polling datagrams to check driver status. 1 No transfer of polling datagrams. autorepeat_cover_en 7 (TMC26x/2130 only) 0 No automatic continuous streaming of cover datagrams. 1 Enabling of automatic continuous streaming of cover datagrams. POLL_BLOCK_EXP 11:8 U (TMC26x in SD mode only, TMC2130 only) Multiplier for calculating the time interval between two consecutive polling datagrams: tPOLL = 2^POLL_BLOCK_EXP ∙ SPI_OUT_BLOCK_TIME / fCLK cover_done_only_for_cover 12 (TMC26x/2130 only) 0 COVER_DONE event is set for every datagram that is sent to the motor driver. 1 COVER_DONE event is only set for cover datagrams sent to the motor driver. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 186/230 SPI_OUT_CONF 0x04 (Default value: 0x00000000) R/W Bit Val Remarks sck_low_before_csn 4 (No TMC driver) 0 NSCSDRV_SDO is tied low before SCKDRV_NSDO to initiate a new data transfer. 1 SCKDRV_NSDO is tied low before NSCSDRV_SDO to initiate a new data transfer. new_out_bit_at_rise 5 RW 11:7 12 (No TMC driver) 0 New value bit at SDODRV_SCLK is assigned at falling edge of SCKDRV_NSDO. 1 New value bit at SDODRV_SCLK is assigned at rising edge of SCKDRV_NSDO. DAC_CMD_LENGTH U (SPI-DAC only) Number of bits for command address. Reserved. Set to 0. SSI_OUT_MTIME 23:4 U (Serial encoder output only) Monoflop time for SSI output interface: Delay time [clock cycles] during which the absolute encoder data remain stable after the last master request. Table 69: SPI Output Configuration Register SPI_OUT_CONF 0x04 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Current Scaling Configuration Register CURRENT_CONF 0x05 CURRENT_CONF 0x05 (Default: 0x00000000) R/W Bit Val Remarks hold_current_scale_en 0 0 No hold current scaling during standstill phase. 1 Hold current scaling during standstill phase. drive_current_scale_en 1 0 No drive current scaling during motion. 1 Drive current scaling during motion. boost_current_on_acc_en 2 0 No boost current scaling for deceleration ramps. 1 Boost current scaling if RAMP_STATE = b’01 (acceleration slopes). boost_current_on_dec_en 3 0 No boost current scaling for deceleration ramps. 1 Boost current scaling if RAMP_STATE = b’10 (deceleration slopes). boost_current_after_start_en 4 0 No boost current at ramp start. 1 Temporary boost current if VACTUAL = 0 and new ramp starts. sec_drive_current_scale_en RW 5 0 One drive current value for the whole motion ramp. 1 Second drive current scaling for VACTUAL > VDRV_SCALE_LIMIT. freewheeling_en 6 0 No freewheeling. 1 Freewheeling after standby phase. closed_loop_scale_en 7 0 No closed-loop current scaling. 1 Closed-loop current scaling – CURRENT_CONF(6:0) = 0 is set automatically Turn off for closed-loop calibration with maximum current! pwm_scale_en 8 15:9 0 PWM scaling is disabled. 1 PWM scaling is enabled. Reserved. Set to 0x00. PWM_AMPL 31:16 U PWM amplitude during Voltage PWM mode at VACTUAL = 0. i Maximum duty cycle = (0.5 + (PWM_AMPL + 1) / 217) Minimum duty cycle = (0.5 – (PWM_AMPL + 1) / 217) PWM_AMPL = 216 – 1 at VACTUAL = PWM_VMAX. Table 70: Current Scale Configuration (0x05) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  187/230 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 188/230 Current Scale Values Register SCALE_VALUES 0x06 SCALE_VALUES 0x06 (Default: 0xFFFFFFFF) R/W RW Bit Val 7:0 U 15:8 U 23:16 U Scaling Value Name BOOST_SCALE_VAL Open-loop boost scaling value. CL_IMIN Closed-loop minimum scaling value. DRV1_SCALE_VAL Open-loop first drive scaling value. CL_IMAX Closed-loop maximum scaling value. DRV2_SCALE_VAL Open-loop second drive scaling value. CL_START_UP HOLD_SCALE_VAL 31:24 U Remarks CL_START_DOWN |ENC_POS_DEV| value at which closed-loop scaling increases the current scaling value above CL_IMIN. Open-loop standby scaling value. |ENC_POS_DEV| value at which closed-loop scaling decreases the current scaling value below CL_IMAX. i Recommended: Set to 0 to automatically assign to CL_BETA. Table 71: Current Scale Values (0x06) NOTE:  BOOST_SCALE_VAL, DRV1/DRV2_SCALE_VAL, HOLD_SCALE_VAL, CL_IMIN, CL_IMAX.  Real scaling value = (x+1) / 32 if spi_output_format = b’1011 or b’1100.  = (x+1) / 256 any other spi_output_format setting. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 189/230 Various Scaling Configuration Registers Various Scaling Configuration Registers R/W Addr Bit 0x15 31:0 Val Description STDBY_DELAY (Default:0x00000000) U Delay time [# clock cycles] between ramp stop and activating standby phase. FREEWHEEL_DELAY (Default:0x00000000) 0x16 31:0 U Delay time [# clock cycles] between initialization of active standby phase and freewheeling initialization. VDRV_SCALE_LIMIT (Default:0x000000) 0x17 23:0 U (Voltage PWM mode is not active) Drive scaling separator: DRV2_SCALE_VAL is active in case VACTUAL > VDRV_SCALE_LIMIT DRV1_SCALE_VAL is active in case VACTUAL ≤ VDRV_SCALE_LIMIT 2nd assignment: Also used as PWM_VMAX if Voltage PWM is enabled (see 19.17. ) UP_SCALE_DELAY (Default:0x000000) U RW 0x18 23:0 Increment delay [# clock cycles]. The value defines the clock cycles, which are used to increase the current scale value for one step towards higher values. CL_UPSCALE_DELAY (Default:0x000000) U 0x19 23:0 (Open-loop operation) Decrement delay [# clock cycles] to decrease the actual scale value by one step towards hold current. CL_DNSCALE_DELAY(Default: 0x000000) U (Closed-loop operation) Increment delay [# clock cycles]. The value defines the clock cycles, which are used to increase the current scale value for one step towards higher current values during closed-loop operation. HOLD_SCALE_DELAY (Default:0x000000) U (Open-loop operation) (Closed-loop operation) Decrement delay [# clock cycles] to decrease the current scale value by one step towards lower current values during closed-loop operation. DRV_SCALE_DELAY (Default:0x000000) 0x1A 23:0 0x1B 31:0 R W 0x7C 8:0 U Decrement delay [# clock cycles], which signifies current scale value decrease by one step towards lower value. BOOST_TIME (Default:0x00000000) U Time [# clk cycles] after a ramp start when boost scaling is active. SCALE_PARAM (Default:0x000) U Actual used scale parameter. 2nd assignment: Also used as CIRCULAR_DEC for write access (see section 19.16. ) Table 72: Various Scaling Configuration Registers (0x15…0x1B) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Encoder Signal Configuration (0x07) ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description enc_sel_decimal 0 0 Encoder constant represents a binary number. 1 Encoder constant represents a decimal number (for ABN only). clear_on_n 0 1 ENC_POS is not set to ENC_RESET_VAL. ENC_POS is set to ENC_RESET_VAL on every N event in case clr_latch_cont_on_n=1, or on the next N event in case clr_latch_once_on_n=1. Do NOT use during closed-loop operation. 1 clr_latch_cont_on_n 2 0 Value of ENC_POS is not cleared and/or latched on every N event. 1 Value of ENC_POS is cleared and/or latched on every N event. clr_latch_once_on_n 3 0 Value of ENC_POS is not cleared and/or latched on the next N event. 1 Value of ENC_POS is cleared and/or latched on the next N event. i This bit is set to 0 after latching/clearing once. pol_n RW 4 0 Active polarity for N event is low active. 1 Active polarity for N event is high active. n_chan_sensitivity 6:5 0 N event is active as long as N equals active N event polarity. 1 N event triggers when N switches to active N event polarity. 2 N event triggers when N switches to inactive N event polarity. 3 N event triggers when N switches to in-/active N event polarity (both slopes). pol_a_for_n 7 0 A polarity has to be low for a valid N event. 1 A polarity has to be high for a valid N event. pol_b_for_n 8 0 1 B polarity has to be low for valid N event B polarity has to be high for valid N event ignore_ab 9 0 TMC4361A considers A and B polarities for valid N event. 1 Polarities of A and B signals for a valid N event are ignored. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  190/230 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 191/230 ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description latch_enc_on_n 10 0 1 ENC_POS is not latched. ENC_POS is latched to ENC_LATCH on every N event on the next N event in case clr_latch_cont_on_n=1, or in case clr_latch_once_on_n=1. latch_x_on_n 11 0 1 XACTUAL is not latched. XACTUAL is latched to X_LATCH on every N event on the next N event in case clr_latch_cont_on_n=1, or in case clr_latch_once_on_n=1. multi_turn_in_en 12 (Absolute encoder only) 0 Connected serial encoder transmits singleturn values. 1 Connected serial encoder input transmits singleturn and multiturn values. multi_turn_in_signed 13 (Absolute encoder only) 0 Multiturn values from serial encoder input are unsigned numbers. 1 Multiturn values from serial encoder input are signed numbers. multi_turn_out_en 14 RW (Serial encoder output only) 0 Serial encoder output transmits singleturn values. 1 Serial encoder output transmits singleturn and multiturn values. use_usteps_instead_of_xrange 15 0 X_RANGE is valid in case circular motion is also enabled for encoders. 1 USTEPS_PER_REV is valid in case circular motion is also enabled for encoders. calc_multi_turn_behav 16 (Absolute encoder only) 0 No multiturn calculation. 1 TMC4361A calculates internally multiturn data for singleturn encoder data. ssi_multi_cycle_data 17 (Absolute encoder only) 0 Every SSI value request is executed once. 1 Every SSI value request is executed twice. ssi_gray_code_en 18 (Absolute encoder only) 0 SSI input data is binary-coded. 1 SSI input data is gray-coded. left_aligned_data 19 (Absolute encoder only) 0 Serial input data is aligned right (first flags, then data). 1 Serial input data is aligned left (first data, then flags). Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 192/230 ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description spi_data_on_cs 20 (SPI encoder only) 0 BNEG_NSDI provides serial output data at next serial clock line (A_SCLK) transition. 1 BNEG_NSDI provides serial output data immediately in case negated chip select line ANEG_NSCLK switches to low level. spi_low_before_cs 21 0 1 (SPI encoder only) Serial clock line A_SCLK switches to low level after negated chip select line ANEG_NSCLK switches to low level. Serial clock line A_SCLK switches to low level before negated chip select line ANEG_NSCLK switches to low level. regulation_modus 0 23:22 1 2 3 No internal regulation on encoder feedback data. Closed-loop operation is enabled. Use full microstep resolution only! (256 µSteps/FS  MSTEPS_PER_FS=0). PID regulation is enabled. Pulse generator base velocity equals 0. PID regulation is enabled. Pulse generator base velocity equals VACTUAL. cl_calibration_en (Closed-loop operation only) 0 Closed-loop calibration is deactivated. 1 Closed-loop calibration is active. Use maximum current without scaling during calibration. It is recommend to keep the motor driver at fullstep position with no motion occurrence during the calibration process. 24 cl_emf_en RW 25 (Closed-loop operation only) 0 Back-EMF compensation deactivated during closed-loop operation. 1 Back-EMF compensation is enabled during closed-loop operation. Closed-loop operation compensates Back-EMF in case |VACTUAL| > CL_VMIN. cl_clr_xact 26 0 1 (Closed-loop operation only) XACTUAL is not reset to ENC_POS during closed-loop operation. XACTUAL is set to ENC_POS in case |ENC_POS_DEV| > ENC_POS_DEV_TOL during closed-loop operation. This feature must only be used if understood completely. cl_vlimit_en 27 (Closed-loop operation only) 0 No catch-up velocity limit during closed-loop regulation. 1 Catch-up velocity during closed-loop operation is limited by internal PI regulator. cl_velocity_mode_en 28 (Closed-loop operation only) 0 Closed-loop velocity mode is deactivated. 1 Closed-loop velocity mode is deactivated. In case |ENC_POS_DEV| > 768, XACTUAL is adjusted accordingly. invert_enc_dir 29 0 Encoder direction is NOT inverted internally. 1 Encoder direction is inverted internally. Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 193/230 ENC_IN_CONF 0x07 (Default 0x00000400) R/W Bit Val Description enc_out_gray 30 (Serial encoder output only) 0 SSI output data is binary-encoded. 1 SSI output data is gray-encoded. no_enc_vel_preproc RW 31 (Incremental ABN encoder) 0 AB signal is preprocessed for internal encoder velocity calculation. 1 No AB signal preprocessing. It is recommend to maintain AB preprocessing in order to filter encoder resonances. serial_enc_variation_limit (Absolute encoder) 0 No variation limit on absolute encoder data. 1 Two consecutive serial encoder values must no deviate from specified limit to be valid. In case |ENC_POSX – ENC_POSX-1| > 1/8 · SER_ENC_VARIATION · ENC_IN_RES, ENC_POSX is not valid and is not assigned to ENC_POS. Table 73: Encoder Signal Configuration ENC_IN_CONF (0x07) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 194/230 Serial Encoder Data Input Configuration (0x08) ENC_IN_DATA 0x08 (Default: 0x00000000) R/W Bit Val Remarks SINGLE_TURN_RES (Default: 0x00) 4:0 9:5 RW 11:10 Number of angle data bits within one revolution = SINGLE_TURN_RES + 1. Set SINGLE_TURN_RES < 31. U MULTI_TURN_RES (Default: 0x00) Number of data bits for revolution count = MULTI_TURN_RES + 1 U STATUS_BIT_CNT (Default: 0x0) U Number of status data bits 15:12 Reserved. Set to 0x0. 23:16 31:24 SERIAL_ADDR_BITS (Default: 0x00) U (SPI encoder only) Number of address bits within one SPI datagram for SPI encoder configuration SERIAL_DATA_BITS (Default: 0x00) U (SPI encoder only) Number of data bits within one SPI datagram for SPI encoder configuration Table 74: Serial Encoder Data Input Configuration ENC_IN_DATA (0x08) Serial Encoder Data Output Configuration (0x09) ENC_OUT_DATA 0x09 (Default: 0x00000000) R/W Bit 4:0 RW 9:5 Val Remarks SINGLE_TURN_RES_OUT (Default: 0x00) U Number of angle data bits within one revolution = SINGLE_TURN_RES_OUT + 1 MULTI_TURN_RES_OUT (Default: 0x00) U Number of data bits for revolution count = MULTI_TURN_RES_OUT + 1 31:12 Reserved. Set to 0x00000. Table 75: Serial Encoder Data Output Configuration ENC_OUT_DATA (0x09) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 195/230 Motor Driver Settings Register STEP_CONF 0x0A STEP_CONF 0x0A (Default: 0x00FB0C80) R/W Bit Val Remarks MSTEP_PER_FS (Default: 0x0) 3:0 RW 15:4 0 Highest microsteps resolution: 256 microsteps per fullstep. i Set to 256 for closed-loop operation. i When using a Step/Dir driver, it must be capable of a 256 resolution via Step/Dir input for best performance (but lower resolution Step/Dir drivers can be used as well). 1 128 microsteps per fullstep. 2 64 microsteps per fullstep. 3 32 microsteps per fullstep. 4 16 microsteps per fullstep. 5 8 microsteps per fullstep. 6 4 microsteps per fullstep. 7 Halfsteps: 2 microsteps per fullstep. 8 Full steps (maximum possible setting) FS_PER_REV (Default: 0x0C8) U Fullsteps per motor axis revolution MSTATUS_SELECTION (Default: 0xFB) 23:16 31:24 Selection of motor driver status bits for SPI response datagrams: ORed with Motor Driver Status Register Set (7:0): if set here and a particular flag is set from the motor stepper driver, an event will be generated at EVENTS(30) Reserved. Set to 0x00. Table 76: Motor Driver Settings (0x0A) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 196/230 Event Selection Registers 0x0B..0X0D Event Selection Registers R/W Addr Bit Remarks SPI_STATUS_SELECTION (Default: 0x82029805) 0x0B Events selection for SPI datagrams: Event bits of EVENTS register 0x0E that are selected (=1) in this register are 31:0 forwarded to the eight status bits that are transferred with every SPI datagram (first eight bits from LSB are significant!). EVENT_CLEAR_CONF (Default: 0x00000000) RW 0x0C Event protection configuration: 31:0 Event bits of EVENTS register 0x0E that are selected in this register (=1) are not cleared during the readout process of EVENTS register 0x0E. INTR_CONF (Default: 0x00000000) 0x0D Event selection for INTR output: All Event bits of EVENTS register 0x0E that are selected here (=1) are ORed with 31:0 interrupt event register set: if any of the selected events is active, an interrupt at INTR is generated. Table 77: Event Selection Regsiters 0x0B…0x0D © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 197/230 Status Event Register (0x0E) Status Event Register EVENTS 0x0E R/W Bit Description 0 TARGET_REACHED has been triggered. 1 POS_COMP_REACHED has been triggered. 2 VEL_REACHED has been triggered. 3 VEL_STATE = b’00 has been triggered (VACTUAL = 0). 4 VEL_STATE = b’01 has been triggered (VACTUAL > 0). 5 VEL_STATE = b’10 has been triggered (VACTUAL < 0). 6 RAMP_STATE = b’00 has been triggered (AACTUAL = 0, VACTUAL is constant). 7 RAMP_STATE = b’01 has been triggered (|VACTUAL| increases). 8 RAMP_STATE = b’10 has been triggered (|VACTUAL| increases). 9 10 MAX_PHASE_TRAP: Trapezoidal ramp has reached its limit speed using maximum values for AMAX or DMAX (|VACTUAL| > VBREAK; VBREAK≠0). FROZEN: NFREEZE has switched to low level. i Reset TMC4361A for further motion. STOPL has been triggered. Motion in negative direction is not executed until this event is cleared and (STOPL is not active any more or stop_left_en is set to 0). STOPR has been triggered. Motion in positive direction is not executed until this event is cleared 12 and (STOPR is not active any more or stop_right_en is set to 0). VSTOPL_ACTIVE: VSTOPL has been activated. No further motion in negative direction until this 13 event is cleared and (a new value is chosen for VSTOPL or virtual_left_limit_en is set to 0). VSTOPR_ACTIVE: VSTOPR has been activated. No further motion in positive direction until this 14 event is cleared and (a new value is chosen for VSTOPR or virtual_right_limit_en is set to 0). 11 R+C W 15 HOME_ERROR: Unmatched HOME_REF polarity and HOME is outside of safety margin. 16 XLATCH_DONE indicates if X_LATCH was rewritten or homing process has been completed. 17 FS_ACTIVE: Fullstep motion has been activated. 18 ENC_FAIL: Mismatch between XACTUAL and ENC_POS has exceeded specified limit. 19 N_ACTIVE: N event has been activated. 20 ENC_DONE indicates if ENC_LATCH was rewritten. 21 SER_ENC_DATA_FAIL: Failure during multi-cycle data evaluation or between two consecutive data requests has occured. 22 Reserved. 23 SER_DATA_DONE: Configuration data was received from serial SPI encoder. 24 One of the SERIAL_ENC_Flags was set. 25 COVER_DONE: SPI datagram was sent to the motor driver. 26 ENC_VEL0: Encoder velocity has reached 0. 27 CL_MAX: Closed-loop commutation angle has reached maximum value. 28 CL_FIT: Closed-loop deviation has reached inner limit. 29 STOP_ON_STALL: Motor stall detected. Motor ramp has stopped. 30 MOTOR_EV: One of the selected TMC motor driver flags was triggered. 31 RST_EV: Reset was triggered. Table 78: Status Event Register EVENTS (0x0E) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 198/230 Status Flag Register (0x0F) Status Flag Register STATUS 0x0F R/W Bit 0 TARGET_REACHED_F is set high if XACTUAL = XTARGET 1 POS_COMP_REACHED_F is set high if XACTUAL = POS_COMP 2 7 VEL_REACHED_F is set high if VACTUAL = |VMAX| VEL_STATE_F: Current velocity state: 0  VACTUAL = 0; 1  VACTUAL > 0; 2  VACTUAL < 0 RAMP_STATE_F: Current ramp state: 0  AACTUAL = 0; 1  AACTUAL increases (acceleration); 2  AACTUAL decreases (deceleration) STOPL_ACTIVE_F: Left stop switch is active. 8 STOPR_ACTIVE_F: Right stop switch is active. 9 VSTOPL_ACTIVE_F: Left virtual stop switch is active. 10 VSTOPR_ACTIVE_F: Right virtual stop switch is active. 11 ACTIVE_STALL_F: Motor stall is detected and VACTUAL > VSTALL_LIMIT. 12 HOME_ERROR_F: HOME_REF input signal level is not equal to expected home level. 13 FS_ACTIVE_F: Fullstep operation is active. 14 ENC_FAIL_F: Mismatch between XACTUAL and ENC_POS is out of tolerated range. 15 N_ACTIVE_F: N event is active. 16 ENC_LATCH_F: ENC_LATCH is rewritten. 4:3 6:5 R Description 17 18 19 23:20 24 Applies to absolute encoders only: MULTI_CYCLE_FAIL_F indicates a failure during last multi cycle data evaluation. Applies to absolute encoders only: SER_ENC_VAR_F indicates a failure during last serial data evaluation due to a substantial deviation between two consecutive serial data values. Reserved. CL_FIT_F: Active if ENC_POS_DEV < CL_TOLERANCE. The current mismatch between XACTUAL and ENC_POS is within tolerated range. Applies to absolute encoders only: SERIAL_ENC_FLAGS received from encoder. These flags are reset with a new encoder transfer request. TMC26x / TMC2130 only: SG: StallGuard2 status Optional for TMC24x only: Calculated stallGuard status. TMC23x / TMC24x only: UV_SF: Undervoltage flag. OT: 25 All TMC motor drivers: 26 All TMC motor drivers: OTPW: TMC26x / TMC2130 only: S2GA: Overtemperature shutdown. TMC23x / TMC24x only: OCB: Overtemperature warning. Short to ground detection bit for high side MOSFE of coil A. Overcurrent bridge A. Short to ground detection bit for high side MOSFET of coil B. Overcurrent bridge B. 29 All TMC motor drivers: OLA: Open load indicator of coil A. 30 All TMC motor drivers: OLB: Open load indicator of coil B. 27 TMC23x / TMC24x only: OCA: TMC26x / TMC2130 only: S2GB: 28 31 TMC26x / TMC2130 only: STST: TMC23x / TMC24x only: OCHS: Standstill indicator. Overcurrent high side. Table 79: Status Flag Register STATUS (0x0F) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 199/230 Various Configuration Registers: S/D, Synchronization, etc. Various Configuration Registers: Closed-loop, Switches… R/W Addr Bit 15:0 0x10 31:16 Val Description STP_LENGTH_ADD (Default: 0x0000) U Additional length [# clock cycles] for active step polarity of a step at STPOUT. DIR_SETUP_TIME (Default: 0x0000) U Delay [# clock cycles] between DIROUT and STPOUT voltage level changes. START_OUT_ADD (Default:0x00000000) 0x11 31:0 U Additional length [# clock cycles] for active start signal. Active start signal length = 1+START_OUT_ADD GEAR_RATIO (Default:0x01000000) 0x12 31:0 0x13 31:0 RW 0x14 31:0 0x1D 23:0 S Constant value that is added to the internal position counter by an active step at STPIN. Value representation: 8 digits and 24 decimal places. START_DELAY (Default:0x00000000) U Delay time [# clock cycles] between start trigger and internal start signal release. CLK_GATING_DELAY (Default:0x00000000) U Delay time [# clock cycles] between clock gating trigger and clock gating start. SPI_SWITCH_VEL U Absolute velocity value [pps] at which automatic cover datagrams are sent 31:0 2nd assignment: Also used as DAC_ADDR_A/B if SPI-DAC mode is enabled (see 19.30. ) HOME_SAFETY_MARGIN (Default: 0x0000) 0x1E 15:0 U HOME_REF polarity can be invalid within X_HOME ± HOME_SAFETY_MARGIN, which is not flagged as error. CHOPSYNC_DIV (Default: 0x0280) 0x1F 11:0 U (ChopSync for TMC23x/24x is enabled) Chopper clock divider that defines the chopper frequency fOSC: fOSC = fCLK/CHOPSYNC_DIV with 96 ≤ CHOPSYNC_DIV ≤ 818 15:0 2nd assignment: Also used as PWM_FREQ if Voltage PWM is enabled (see 19.17. ) FS_VEL(Default:0x000000) 0x60 31:0 W (Closed-loop and dcStep operation are disabled) Minimum fullstep velocity [pps]. In case |VACTUAL| > FS_VEL fullstep operation is active, if enabled. 2nd assignment: Also used as DC_VEL if dcStep is enabled (see section 19.27. ) 3rd assignment: Also used as CL_VMIN_EMF if closed-loop is enabled (see 19.26. ) U 0x64 31:0 Reserved. Set to 0x00000000. VSTALL_LIMIT (Default:0x00000000) 0x67 23:0 U Stop on stall velocity limit [pps]: Only above this limit an active stall leads to a stop on stall, if enabled. TZEROWAIT (Default:0x00000000) 0x7B 31:0 U Standstill phase after reaching VACTUAL = 0. 2nd assignment: Also used as CURRENTA/B_SPI for read out (see section 19.29. ) R CIRCULAR_DEC (Default:0x00000000) W R 0x7C 31:0 8:0 U Decimal places for circular motion if one revolution is not exactly mapped to an even number of µSteps per revolution. Value representation: 1 digit, 31 decimals. 2nd assignment: Also used as SCALE_PARAM for read out (see section 19.8. ) Table 80: Various Configuration Registers: S/D, Synchronization, etc. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 200/230 PWM Configuration Registers PWM Configuration Registers R/W Addr Bit Val Description PWM_VMAX (Default:0x00000000) 0x17 23:0 U (Voltage PWM is enabled) PWM velocity value at which maximal scale parameter value 1.0 is reached. 2nd assignment: Also used as VDRV_SCALE_LIMIT if Voltage PWM is disabled (19.29. ) RW 0x1F 15:0 PWM_FREQ (Default: 0x0280) U (Voltage PWM is enabled) Number of clock cycles for one PWM period. 11:0 2nd assignment: Also used as CHOPSYNC_DIV if Voltage PWM is disabled (see 19.16. ) MSOFFSET (Default:0x000) W 0x79 9:0 U (TMC23x/24x only) Microstep offset for PWM mode. 2nd assignment: Also used as MSCNT for read out (see section 19.29. ) Table 81: PWM Configuration Registers. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 201/230 Ramp Generator Registers Ramp Generator Registers R/W Addr Bit Val Description RAMPMODE (Default:0x0) Operation Mode: 2 1 Positioning mode: XTARGET is superior target of velocity ramp. 0 Velocitiy mode: VMAX is superior target of velocity ramp. RW Motion Profile: 0x20 0 1:0 1 2 RW 0x21 31:0 R 0x22 31:0 R 0x23 31:0 No ramp: VACTUAL follows only VMAX (rectangle velocity shape). Trapezoidal ramp (incl. sixPoint ramp): Consideration of acceleration and deceleration values for generating VACTUAL without adapting the acceleration values. S-shaped ramp: Consideration of all ramp values (incl. bow values) for generating VACTUAL. XACTUAL (Default: 0x00000000) S Actual internal motor position [pulses]: –231 ≤ XACTUAL ≤ 231 – 1 VACTUAL (Default: 0x00000000) S Actual ramp generator velocity [pulses per second]: 1 pps ≤ |VACTUAL| ≤ CLK_FREQ · ½ pulses (fCLK = 16 MHz  8 Mpps) AACTUAL (Default: 0x00000000) S Actual acceleration/deceleration value [pulses per sec 2]: -231 pps² ≤ AACTUAL ≤ 231 – 1 1 pps² ≤ |AACTUAL| VMAX (Default: 0x00000000) Maximum ramp generator velocity in positioning mode or RW 0x24 31:0 S Target ramp generator velocity in velocity mode and no ramp motion profile. Value representation: 23 digits and 8 decimal places Consider maximum values, represented in section 6.7.5, page 50 VSTART (Default: 0x00000000) RW 0x25 30:0 U Absolute start velocity in positioning mode and velocity mode In case VSTART is used: no first bow phase B1 for S-shaped ramps VSTART in positioning mode: In case VACTUAL = 0 and XTARGET ≠ XACTUAL: no acceleration phase for VACTUAL = 0  VSTART. VSTART in velocity mode: In case VACTUAL = 0 and VACTUAL ≠ VMAX: no acceleration phase for VACTUAL = 0  VSTART. Value representation: 23 digits and 8 decimal places. Consider maximum values, represented in section 6.7.5, page 50  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 202/230 Ramp Generator Registers R/W Addr Bit Val Description VSTOP (Default:0x00000000) 0x26 30:0 U Absolute stop velocity in positioning mode and velocity mode. In case VSTOP is used: no last bow phase B4 for S-shaped ramps. In case VSTOP is very small and positioning mode is used, it is possible that the ramp is finished with a constant VACTUAL = VSTOP until XTARGET is reached. VSTOP in positioning mode: In case VACTUAL≤VSTOP and XTARGET=XACTUAL: VACTUAL is immediately set to 0. VSTOP in velocity mode: In case VACTUAL ≤ VSTOP and VMAX = 0: VACTUAL is immediately set to 0. Value representation: 23 digits and 8 decimal places. Consider maximum values, represented in section 6.7.5, page 50 VBREAK (Default:0x00000000) 0x27 30:0 U Absolute break velocity in positioning mode and in velocity mode, This only applies for trapezoidal ramp motion profiles. In case VBREAK = 0: pure linear ramps are generated with AMAX / DMAX only. In case |VACTUAL| < VBREAK: |AACTUAL| = ASTART or DFINAL In case |VACTUAL| ≥ VBREAK: |AACTUAL| = AMAX or DMAX Always set VBREAK > VSTOP! If VBREAK ≠ 0. Value representation: 23 digits and 8 decimal places. Consider maximum values, represented in section 6.7.5, page 50 RW AMAX (Default: 0x000000) S-shaped ramp motion profile: Maximum acceleration value. 0x28 23:0 U Trapezoidal ramp motion profile: Acceleration value in case |VACTUAL| ≥ VBREAK or in case VBREAK = 0. Value representation: Frequency mode: [pulses per sec2] 22 digits and 2 decimal places: 250 mpps2 ≤ AMAX ≤ 4 Mpps2 Direct mode: [∆v per clk cycle] a[∆v per clk_cycle]= AMAX / 237 AMAX [pps2] = AMAX / 237 • fCLK2 Consider maximum values, represented in section 6.7.5, page 50 DMAX (Default: 0x000000) 0x29 23:0 U S-shaped ramp motion profile: Maximum deceleration value. Trapezoidal ramp motion profile: Deceleration value if |VACTUAL| ≥ VBREAK or if VBREAK = 0. Value representation: Frequency mode: [pulses per sec2] 22 digits and 2 decimal places: 250 mpps2 ≤ DMAX ≤ 4 Mpps2 Direct mode: [∆v per clk cycle] d[∆v per clk_cycle]= DMAX / 237 DMAX [pps2] = DMAX / 237 • fCLK2 Consider maximum values, represented in section 6.7.5, page 50  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 203/230 Ramp Generator Registers R/W Addr Bit Val Description ASTART (Default: 0x000000) S-shaped ramp motion profile: start acceleration value. Trapezoidal ramp motion profile: Acceleration value in case |VACTUAL| < VBREAK. 0x2A 23:0 Acceleration value after switching from external to internal step control. U Value representation: Frequency mode: [pulses per sec2] 22 digits and 2 decimal places: 250 mpps2 ≤ ASTART ≤ 4 Mpps2 Direct mode: [∆v per clk cycle] a[∆v per clk_cycle]= ASTART / 237 ASTART [pps2] = ASTART / 237 • fCLK2 Consider maximum values, represented in section 6.7.5, page 50 Sign of AACTUAL after switching from external to internal step control. 31 DFINAL (Default: 0x000000) RW 0x2B 23:0 U S-shaped ramp motion profile: Stop deceleration value, which is not used during positioning mode. Trapezoidal ramp motion profile: Deceleration value in case |VACTUAL| < VBREAK. Value representation: Frequency mode: [pulses per sec2] 22 digits and 2 decimal places: 250 mpps2 ≤ DFINAL ≤ 4 Mpps2 Direct mode: [∆v per clk cycle] d[∆v per clk_cycle]= DFINAL / 237 DFINAL [pps2] = DFINAL / 237 • fCLK2 Consider maximum values, represented in section 6.7.5, page 50 DSTOP (Default: 0x000000) 0x2C 23 U Deceleration value for an automatic linear stop ramp to VACTUAL = 0. DSTOP is used with activated external stop switches (STOPL or STOPR) if soft_stop_enable is set to 1; or with activated virtual stop switches and virt_stop_mode is set to 2. Value representation: Frequency mode: [pulses per sec2] 22 digits and 2 decimal places: 250 mpps2 ≤ DSTOP ≤ 4 Mpps2 Direct mode: [∆v per clk cycle] d[∆v per clk_cycle]= DSTOP / 237 DSTOP [pps2] = DSTOP / 237 • fCLK2 Consider maximum values, represented in section 6.7.5, page 50  Continued on next page! © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 204/230 Ramp Generator Registers R/W Addr Bit Val Description BOW1 (Default: 0x000000) Bow value 1 (first bow B1 of the acceleration ramp). 0x2D 23:0 U Value representation: Frequency mode: [pulses per sec3] 24 digits and 0 decimal places: 1 pps3 ≤ BOW1 ≤ 16 Mpps3 Direct mode: [∆a per clk cycle] bow[av per clk_cycle]= BOW1 / 253 BOW1 [pps3] = BOW1 / 253 • fCLK3 Consider maximum values, represented in section 6.7.5, page 50 BOW2 (Default: 0x000000) Bow value 2 (second bow B2 of the acceleration ramp). 0x2E 23:0 U RW Value representation: Frequency mode: [pulses per sec3] 24 digits and 0 decimal places: 1 pps3 ≤ BOW2 ≤ 16 Mpps3 Direct mode: [∆a per clk cycle] bow[av per clk_cycle]= BOW2 / 253 BOW2 [pps3] = BOW2 / 253 • fCLK3 Consider maximum values, represented in section 6.7.5, page 50 BOW3 (Default: 0x000000) Bow value 3 (first bow B3 of the deceleration ramp). 0x2F 23:0 U Value representation: Frequency mode: [pulses per sec3] 24 digits and 0 decimal places: 1 pps3 ≤ BOW3 ≤ 16 Mpps3 Direct mode: [∆a per clk cycle] bow[av per clk_cycle]= BOW3 / 253 BOW3 [pps3] = BOW3 / 253 • fCLK3 Consider maximum values, represented in section 6.7.5, page 50 BOW 4 (Default: 0x000000) Bow value 4 (second bow B4 of the deceleration ramp). 0x30 23:0 U Value representation: Frequency mode: [pulses per sec3] 24 digits and 0 decimal places: 1 pps3 ≤ BOW4 ≤ 16 Mpps3 Direct mode: [∆a per clk cycle] bow[av per clk_cycle]= BOW4 / 253 BOW4 [pps3] = BOW4 / 253 • fCLK3 Consider maximum values, represented in section 6.7.5, page 50 Table 82: Ramp Generator Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 205/230 External Clock Frequency Register External Clock Frequency Register R/W Addr Bit RW 0x31 24:0 Val Description CLK_FREQ (Default: 0x0F42400) U External clock frequency value fCLK [Hz] with 4.2 MHz ≤ fCLK ≤ 30 MHz Table 83: External Clock Frequency Register Target and Compare Registers Target and Compare Registers R/W Addr Bit RW 0x32 31:0 RW 0x33 31:0 RW 0x34 31:0 RW 0x35 31:0 Val Description POS_COMP (Default: 0x00000000) S Compare position. VIRT_STOP_LEFT (Default: 0x00000000) S Virtual left stop position. VIRT_STOP_RIGHT (Default: 0x00000000) S Virtual right stop position. X_HOME (Default: 0x00000000) S Actual home position. X_LATCH (Default: 0x00000000) R 31:0 0x36 S Storage position for certain triggers. REV_CNT (Default: 0x00000000) S (if circular_cnt_as_xlatch = 0) (if circular_cnt_as_xlatch = 1) Number of revolutions during circular motion. X_RANGE (Default: 0x00000000) 30:0 Limitation for X_ACTUAL during circular motion: U -X_RANGE ≤ X_ACTUAL ≤ X_RANGE - 1 X_TARGET (Default: 0x00000000) W RW 0x37 31:0 U Target motor position in positioning mode. Set all other motion profile parameters before! Table 84: Target and Compare Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 206/230 Pipeline Registers Pipeline Register R/W Addr Bit Val 0x38 31:0 S X_PIPE0 (Default: 0x00000000): 1st pipeline register. 0x39 31:0 S X_PIPE1 (Default: 0x00000000): 2nd pipeline register. 0x3A 31:0 S X_PIPE2 (Default: 0x00000000): 3rd pipeline register. 0x3B 31:0 S X_PIPE3 (Default: 0x00000000): 4th pipeline register. 0x3C 31:0 S X_PIPE4 (Default: 0x00000000): 5th pipeline register. 0x3D 31:0 S X_PIPE5 (Default: 0x00000000): 6th pipeline register. 0x3E 31:0 S X_PIPE6 (Default: 0x00000000): 7th pipeline register. 0x3F 31:0 S X_PIPE7 (Default: 0x00000000): 8th pipeline register. RW Description Table 85: Pipeline Register Shadow Register Shadow Register R/W Addr Bit Val 0x40 31:0 S SH_REG0 (Default: 0x00000000) : 1st shadow register. 0x41 31:0 U SH_REG1 (Default: 0x00000000) : 2nd shadow register. 0x42 31:0 U SH_REG2 (Default: 0x00000000) : 3rd shadow register. 0x43 31:0 U SH_REG3 (Default: 0x00000000) : 4th shadow register. 0x44 31:0 U SH_REG4 (Default: 0x00000000) : 5th shadow register. 0x45 31:0 U SH_REG5 (Default: 0x00000000) : 6th shadow register. 0x46 31:0 U SH_REG6 (Default: 0x00000000) : 7th shadow register. 0x47 31:0 S/U SH_REG7 (Default: 0x00000000) : 8th shadow register. 0x48 31:0 U SH_REG8 (Default: 0x00000000) : 9th shadow register. 0x49 31:0 U SH_REG9 (Default: 0x00000000) : 10th shadow register. 0x4A 31:0 U SH_REG10 (Default: 0x00000000) : 11th shadow register. 0x4B 31:0 U SH_REG11 (Default: 0x00000000) : 12th shadow register. 0x4C 31:0 U SH_REG12 (Default: 0x00000000) : 13th shadow register. 0x4D 31:0 U SH_REG13 (Default: 0x00000000) : 14th shadow register. RW Description Table 86: Shadow Register © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 207/230 Freeze Register The freeze register can only be written once after an active reset and before motion starts. It is always readable. FREEZE Register R/W Addr Bit Val Description DFREEZE (Default: 0x000000) 23:0 RW Freeze event deceleration value. In case NFREEZE switches to low level, this parameter is used for an automatic linear ramp stop. Setting DFREEZE to 0 leads to an hard stop. Value representation: Frequency mode: not available Direct mode: [∆v per clk cycle] a[∆v per clk_cycle]= DFREEZE / 237 DFREEZE [pps2] = DFREEZE / 237 • fCLK2 Set DFREEZE ≤ 220. U 0x4E IFREEZE (Default: 0x00) 31:24 Scaling value in case NFREEZE is tied low. In case IFREEZE=0, actual active scaling value is valid at FROZEN event. U Table 87: Freeze Register Reset and Clock Gating Register Reset and Clock Gating Register R/W Addr Bit Val Description CLK_GATING_REG (Default: 0x0) 2:0 RW 0x4F 0 Clock gating is not activated. 7 Clock gating is activated. RESET_REG (Default: 0x000000) 31:8 0 No reset is activated. 0x525354 Internal reset is activated. Table 88: Reset and Clock Gating Register © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 208/230 Encoder Registers Encoder Registers R/W Addr Bit Val Description RW 0x50 31:0 S Actual encoder position [µsteps]. ENC_LATCH (Default: 0x00000000) R S 0x51 31:0 W Latched encoder position. ENC_RESET_VAL(Default: 0x00000000) S Defined reset value for ENC_POS in case the encoder position must be cleared to another value than 0. ENC_POS_DEV (Default: 0x00000000) R S 0x52 31:0 W W ENC_POS (Default: 0x00000000) CL_TR_TOLERANCE (Default: 0x00000000) S 0x53 31:0 Deviation between XACTUAL and ENC_POS. (Closed-loop operation) Tolerated absolute tolerance between XACTUAL and ENC_POS to trigger TARGET_REACHED (incl. TARGET_REACHED_Flag and event). ENC_POS_DEV_TOL (Default: 0xFFFFFFFF) U Maximum tolerated value of ENC_POS_DEV, which is not flagged as error. ENC_IN_RES (Default: 0x00000000) W U 30:0 R 0x54 Resolution [encoder steps per revolution] of the encoder connected to the encoder inputs. ENC_CONST (Default: 0x00000000) U Encoder constant. i Value representation: 15 digits and 16 decimal places manual_enc_const (Default: 0) W W 31 0x55 31:0 0 1 ENC_CONST will be calculated automatically. Manual definition of ENC_CONST = ENC_IN_RES ENC_OUT_RES (Default: 0x00000000) U Resolution [encoder steps per revolution] of the serial encoder output interface.  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 209/230 Encoder Registers R/W Addr Bit Val Description 15:0 0x56 31:16 SER_CLK_IN_HIGH (Default: 0x00A0) U High voltage level time of serial clock output [# clock cycles]. SER_CLK_IN_LOW (Default: 0x00A0) U Low voltage level time of serial clock output [# clock cycles]. SSI_IN_CLK_DELAY (Default: 0x0000) 15:0 U SSI encoder: Delay time [# clock cycles] between next data transfer after a rising edge of serial clock output. i In case SSI_IN_CLK_DELAY = 0: SSI_IN_CLK_DELAY = SER_CLK_IN_HIGH SPI encoder: Delay [# clock cycles] at start and end of data transfer between serial clock output and negated chip select. i In case SSI_IN_CLK_DELAY = 0: SSI_IN_CLK_DELAY = SER_CLK_IN_HIGH 0x57 SSI_IN_WTIME (Default: 0x0F0) W 31:16 U Delay parameter tw [# clock cycles] between two clock sequences for a multiple data transfer (of the same data). i SSI recommendation: tw < 19 µs. SER_PTIME (Default: 0x00190) 0x58 19:0 U SSI and SPI encoder: Delay time period tp [# clock cycles] between two consecutive clock sequences for new data request. i SSI recommendation: tp > 21 µs. ENC_COMP_XOFFSET (Default:0x0000) 15:0 0x7D 23:16 31:24 U Start offset for triangular compensation in horizontal direction. 0 ≤ ENC_COMP_XOFFSET < 216 ENC_COMP_YOFFSET (Default:0x00) S Start offset for triangular compensation in vertical direction. −128 ≤ ENC_COMP_YOFFSET ≤ 127 ENC_COMP_AMPL (Default:0x00) U Maximum amplitude for encoder compensation. Table 89: Encoder Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 210/230 PID & Closed-Loop Registers PID and Closed-Loop Registers R/W Addr Bit Val Description CL_BETA (0x0FF) 8:0 U RW 0x1C Maximum commutation angle for closed-loop regulation. i i Set CL_BETA > 255 carefully (esp. if cl_vlimit_en = 1). Exactly 255 is recommended for best performance. CL_GAMMA (Default:0xFF) 23:16 U Maximum balancing angle to compensate back-EMF at higher velocities during closed-loop regulation. CL_OFFSET (Default: 0x00000000) RW 0x59 31:0 23:0 0x5A R 31:0 (PID regulation) Parameter P of PID regulator. Proportional term = PID_E · PID_P / 256 CL_VMAX_CALC_P (Default: 0x000000) (Closed-loop operation) Parameter P of PI regulator controls maximum catch-up velocity limitation. PID_VEL (Default: 0x00000000) S (PID regulation) Actual PID output velocity. PID_I ( Default: 0x000000) 23:0 R U U W W Offset between ENC_POS and XACTUAL after closed-loop calibration. It is set during closed-loop calibration process. It can be written manually. PID_P (Default: 0x000000) W W S (Closed-loop operation) 0x5B U Parameter I of PID regulator. Integral term = PID_ISUM / 256 · PID_I / 256 CL_VMAX_CALC_I (Default: 0x000000) U 31:0 (PID regulation) (Closed-loop operation) Parameter I of PI regulator controls maximum catch-up velocity limitation. PID_ISUM_RD ( Default: 0x00000000) S (PID regulation) Actual PID integrator sum. Update frequency = fCLK/128 PID_D (Default: 0x000000) W U 0x5C 23:0 W 14:0 W 0x5D 23:16 R 31:0 W 0x5E 30:0 Parameter D of PID regulator. PID_E is sampled with fCLK / 128 / PID_D_CLKDIV. Derivative term = (PID_ELAST – PID_EACTUAL) · PID_D CL_DELTA_P (Default: 0x000000) U W (PID regulation) Gain parameter that is multiplied with the actual position difference in order to calculate the actual commutation angle for position maintenance stiffness. Clipped at CL_BETA. Real value =CL_DELTA_P / 216 ;Ex: 65536  1.0 (gain=1) Value representation: 8 digits and 16 decimal places. PID_I_CLIP (Default: 0x0000) U (Closed-loop operation) (PID regulation) (Closed-loop operation) Clipping parameter for PID_ISUM. Real value = PID_ISUM • 216 • PID_ICLIP PID_D_CLKDIV (Default:0x00) U (PID regulation) Clock divider for D part calculation. PID_E (Default:0x00000000) S Actual position deviation. PID_DV_CLIP (Default:0x00000000) U (PID regulation) (PID regulation) (Closed-loop operation) Clipping parameter for PID_VEL.  Continued on next page. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 W 19:0 0x5F W 211/230 PID_TOLERANCE (Default:0x00000) U (PID regulation) Tolerated position deviation: PID_E = 0 in case |PID_E| < PID_TOLERANCE CL_TOLERANCE (Default:0x00) 7:0 U (Closed-loop operation) Tolerated position deviation: CL_DELTA_P = 65536 (gain=1) in case |ENC_POS_DEV| < CL_TOLERANCE CL_VMIN_EMF (Default:0x000000) W 0x60 23:0 U (Closed-loop operation) Encoder velocity at which back-EMF compensation starts. 2 assignment: Also used as DC_VEL if dcStep is enabled (see section 19.27. ) 3rd assignment: Also used as FS_VEL if no dcStep or closed-loop is enabled (see 19.16. ) nd CL_VADD_EMF (Default:0x000000) W 0x61 23:0 U Additional velocity value to calculate the encoder velocity at which back-EMF compensation reaches the maximum angle CL_GAMMA. 31:0 2nd assignment: Also used as a dcStep configuration register (see section 19.27. ) ENC_VEL_ZERO (Default:0xFFFFFF) W 0x62 31:0 U Delay time [# clock cycles] after the last incremental encoder change to set V_ENC_MEAN = 0. ENC_VMEAN_WAIT (Default:0x00) 7:0 U (incremental encoders only) Delay period [# clock cycles] between two consecutive actual encoder velocity values that account for calculaton of mean encoder velocity. Set ENC_VMEAN_WAIT > 32. i Is set automatically to SER_PTIME for absolute SSI/SPI encoder. SER_ENC_VARIATION (Default:0x00) 7:0 W U 0x63 11:8 ENC_IN_RES. If ENC_VARIATION = 0: Maximum permitted value = 1/8 • ENC_IN_RES. ENC_VMEAN_FILTER (Default:0x0) U Filter exponent to calculate mean encoder velocity. ENC_VMEAN_INT (Default:0x0000) 31:16 U 0x65 31:0 R 0x66 31:0 U (incremental encoders only) Encoder velocity update time [# clock cycles]. i Minimum value is set automatically to 256. CL_CYCLE (Default:0x0000) 31:16 (absolute encoders only) Multiplier for maximum permitted serial encoder variation between consecutive absolute encoder requests. Maximum permitted value = ENC_VARIATION / 256 • 1/8 • (absolute encoders only) Closed-loop control cycle [# clock cycles]. i Is set automatically to fastest possible cycle for ABN encoders. V_ENC (Default:0x00000000) S Actual encoder velocity [pps]. V_ENC_MEAN (Default:0x00000000) S Filtered encoder velocity [pps]. Table 90: PID and Closed-Loop Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 212/230 dcStep Registers Micellaneous Registers R/W Addr Bit Val Description DC_VEL (Default:0x000000) 0x60 23:0 Minimum dcStep velocity [pps]. In case|VACTUAL| > DC_VEL dcStep is active, if enabled. 2nd assignment: Also used as CL_VMIN_EMF if closed-loop is enabled (section 19.26. ) 3rd assignment: Also used as FS_VEL if no dcStep or closed-loop is enabled (see 19.16. ) U DC_TIME (Default:0x00) 7:0 U (TMC26x only and dcStep only) Upper PWM on-time limit for commutation. i Set slightly above effective blank time TBL of the driver. DC_SG (Default:0x0000) W 0x61 15:8 U (TMC26x and dcStep only) Maximum PWM on-time [# clock cycles ∙ 16] for step loss detection. If a loss is detected (step length of first regular step after blank time of the dcStep input signal is below DC_SG), a stall event will be released. DC_BLKTIME (Default:0x0000) 31:16 (dcStep only) U (TMC26x and dcStep only) Blank time [# clock cycles] after fullstep release when no signal comparison should happen. 23:0 2nd assignment: Also used as CL_VADD_EMF if closed-loop is enabled (see 19.26. ) 0x62 31:0 DC_LSPTM (Default:0x00FFFFFF) U (dcStep only) dcStep low speed timer [# clock cycles] 23:0 2nd assignment: Also used as ENC_VEL_ZERO if dcStep is disabled (see 19.26. ) Table 91: Miscellaneous Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 213/230 Transfer Registers Transfer Registers R/ Addr Bit Val Description W ADDR_TO_ENC (Default:0x00000000) W 0x68 31:0 W 0x69 31:0 - (SPI encoders only) Address data permanently sent to get encoder angle data from the SPI encoder slave device. Address data sent from TMC4361A to SPI encoder for one-time data transfer. DATA_TO_ENC (Default:0x00000000) - (SPI encoders only) Configuration data sent from TMC4361A to SPI encoder for one-time data transfer. ADDR_FROM_ENC (Default:0x00000000) R R 0x6A 31:0 0x6B 31:0 - (SPI encoders only) Repeated request data is stored here. Address data received from SPI encoder as response of the one-time data transfer. DATA_FROM_ENC (Default:0x00000000) - (SPI encoders only) Data received from SPI encoder as response of the one-time data transfer. COVER_LOW (Default:0x00000000) W 0x6C 31:0 - Lower configuration bits of SPI orders that can be sent from TMC4361A to the motor drivers via SPI output. Automatic cover data transfer (automatic_cover = 1): Value in COVER_LOW are sent in case |VACTUAL| crosses SPI_SWITCH_VEL downwards. Set COVER_DATA_LENGTH ≤ 32. In case COVER_DATA_LENGTH = 0, no TMC2130 must be selected. POLLING_STATUS (Default:0x00000000) R - (TMC26x / TMC2130 only) DRV_STATUS response of TMC26x / TMC2130 COVER_HIGH (Default:0x00000000) W 31:0 - 0x6D Upper configuration bits of SPI orders that can be sent from TMC4361A to the motor drivers via SPI output. Automatic cover data transfer (automatic_cover = 1): Value in COVER_LOW are sent if |VACTUAL| crosses SPI_SWITCH_VEL upwards. Set COVER_DATA_LENGTH ≤ 32. In case COVER_DATA_LENGTH = 0, no TMC2130 must be selected. POLLING_REG (Default:0x00000000) R 19:0 - LOST_STEPS response of TMC2130 27:20 - PWM_SCALE response of TMC2130 31:28 - GSTAT response of TMC2130 (TMC2130 only) COVER_DRV_LOW (Default:0x00000000) R 0x6E 31:0 R 0x6F 31:0 - Lower configuration bits of SPI response received from the motor driver connected to the SPI output. COVER_DRV_HIGH (Default:0x00000000) - Upper configuration bits of SPI response received from the motor driver connected to the SPI output. Table 92: Transfer Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 214/230 SinLUT Registers SinLUT Registers R/W Addr Val Description 0x70 MSLUT[0] (Default:0xAAAAB554) 0x71 MSLUT[1] (Default:0x4A9554AA) 0x72 MSLUT[2] (Default:0x24492929) MSLUT[3] (Default:0x10104222) MSLUT[4] (Default:0xFBFFFFFF) 0x75 MSLUT[5] (Default:0xB5BB777D) 0x76 MSLUT[6] (Default:0x49295556) 0x 77 MSLUT[7] (Default:0x00404222) 0x73 W Bit 0x74 31:0 W R 0x78 31:0 0x79 9:0 0x7A 24:16 8:0 0x7B U Definition of the four segments within each quarter MSLUT wave. Actual µStep position of the sine value. 24:16 CURRENTA (Default:0x000) S S 0x7E 23:16 Actual current value of coilB (sine90_120 values). CURRENTA_SPI (Default:0x000) S Actual scaled current value of coilA (sine values) that are sent to the driver. CURRENTB_SPI (Default:0x0F7) S 31:0 2 7:0 Actual current value of coilA (sine values). CURRENTB (Default:0x0F7) nd W W - (Default:0xFFFF8056) 2nd assignment: Also used as MS_OFFSET if Voltage PWM is enabled (see 19.17. ) 8:0 R MSLUTSEL MSCNT (Default:0x000) W R Each bit defines the difference between consecutive values in the microstep look-up table MSLUT (in combination with MSLUTSEL). Actual scaled current value of coilB (sine90_120 values); sent to motor driver. assignment: Also used as TZERO_WAIT for write access (see section 19.16. ) START_SIN (Default:0x00) U Start value for sine waveform. START_SIN90_120 (Default:0xF7) U 31:24 2 nd Start value for cosine waveform. assignment: Also used as DAC_OFFSET for write access (see section 19.30. ) Table 93: SinLUT Registers © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 215/230 SPI-DAC Configuration Registers SPI-DAC Configuration Registers R/W Addr Bit Val Description DAC_ADDR_A (Default:0x0000) 15:0 U Fixed command/address, which is sent via SPI output before sending CURRENTA_SPI values. DAC_ADDR_B (Default: 0x0000) RW 0x1D 31:16 U Fixed command/address, which is sent via SPI output before sending current CURRENTB_SPI values. 23:0 2nd assignment: Also used as SPI_SWITCH_VEL if SPI-DAC mode is disabled (19.16. ) DAC_OFFSET (Default:0x00) W 0x7E 31:24 U S Offset (absolute sine and cosine DAC values). Offset (mapped DAC values). 23:0 2nd assignment: Also used as START_SIN/90_120 for read out (see section 19.29. ) Table 94: SPI-DAC Configuration Registers. TMC Version Register Version Register R/W Addr Bit R 0x7F 15:0 Val Description Version No (Default:0x0002) U TMC4361 version number. Table 95: Version Register © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 216/230 20. Absolute Maximum Ratings The maximum ratings may not be exceeded under any circumstances. Operating the circuit at or near more than one maximum rating at a time for extended periods shall be avoided by application design. Maximum Ratings: 3.3V supply Parameter (VCC = 3.3V nominal  TEST_MODE = 0V) Supply voltage Input voltage IO Symbol Min Max Unit VCC VIN 3.0 −0.3 3.6 3.6 V V Symbol Min Max Unit VCC VIN 4.8 −0.3 5.2 5.2 V V Table 96: Maximum Ratings: 3.3V supply Maximum Ratings: 5.0V supply Parameter (VCC = 5V nominal  TEST_MODE = 0V) Supply voltage Input voltage IO Table 97: Maximum Ratings: 5.0V supply Maximum Ratings: Temperature Parameter Symbol Min Max Unit Temperature T −40 125 °C Table 98: Maximum Ratings: Temperature © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 217/230 21. Electrical Characteristics DC characteristics contain the spread of values guaranteed within the specified supply voltage range unless otherwise specified. Typical values represent the average value of all parts measured at +25°C. Temperature variation also causes stray to some values. A device with typical values will not leave Min/Max range within the full temperature range. DC Characteristics Parameter Symbol Conditions Min Typ −40°C Max Unit 125 °C Extended temperature range TCOM Nominal core voltage VDD 1.8 V Nominal IO voltage VDD 3.3 / 5.0 V Nominal input voltage VIN Input voltage low level VINL Input voltage high level VINH 0.0 3.3 / 5.0 V VDD = 3.3V / 5V −0.3 0.8 / 1.2 V VDD = 3.3V / 5V 2.3 / 3.5 3.6 / 5.2 V Input with pull-down VIN = VDD 5 30 110 µA Input with pull-up VIN = 0V −110 −30 −5 µA Input low current VIN = 0V −10 10 µA Input high current VIN = VDD −10 10 µA 0.4 V Output voltage low level VOUTL VDD = 3.3V / 5V Output voltage high level VOUTH VDD = 3.3V / 5V IOUT_DRV VDD = 3.3V / 5V Output driver strength 2.64 / 4.0 V 4.0 mA Table 99: DC Characteristics Power Dissipation Power Dissipation Parameter Symbol Static power dissipation PDSTAT Dynamic power dissipation PDDYN Total power dissipation PD Conditions All inputs at VDD or GND VDD = 3.3V / 5V All inputs at VDD or GND fCLK variable VDD = 3.3V / 5V fCLK = 16 MHz VDD = 3.3V / 5V Min Typ Max Unit 1.1 / 1.7 mW 2.7 / 4.0 mW / MHz 44.3 / 65.7 mW Table 100: Power Dissipation © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 218/230 General IO Timing Parameters General IO Timing Parameters Parameter Symbol Conditions Min Typ Max 30 Operation frequency fCLK fCLK = 1 / tCLK 4.21) 16 Clock Period tCLK Rising edge to rising edge 33.5 62.5 Unit MHz ns Clock time low 16.5 ns Clock time high 16.5 ns CLK input signal rise time tRISE_IN 20 % to 80 % 20 ns CLK input signal fall time tFALL_IN 80 % to 20 % 20 ns Output signal rise time tRISE_OUT Output signal fall time tFALL_OUT Setup time for SPI input signals in synchronous design tSU Hold time tHD 20 % to 80 % load 32 pF 80 % to 20 % load 32 pF Relative to rising clk edge Relative to rising clk edge 3.5 ns 3.5 ns 5 ns 5 ns Table 101: General IO Timing Parameters The lower limit for fCLK refers to the limits of the internal unit conversion to physical units. The chip will also operate at lower frequencies. 1) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Layout Examples Internal Cirucit Diagram for Layout Example Figure 73: Internal Circuit Diagram for Layout Example © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  219/230 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Components Assembly for Application with Encoder Figure 74: Components Assembly for Application with Encoder Top Layer: Assembly Side Figure 75: Top Layer: Assembly Side © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  220/230 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Inner Layer (GND) Figure 76: Inner Layer (GND) Inner Layer (Supply VS) Figure 77: Inner Layer (Supply VS) © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  221/230 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 222/230 Package Dimensions Package Dimensions Parameter Ref Min Nom Max Total thickness A 0.8 0.85 0.9 0.03 0.05 5 0.65 0.67 Stand off A1 0 Mold thickness A2 - Lead frame thickness A3 Lead width b Body size X D 6 BSC Body size Y E 6 BSC Lead pitch e 0.5 BSC Exposed die pad size X J 4.52 4.62 4.72 Exposed die pad size Y K 4.52 4.62 4.72 Lead length L 0.35 0.203 REF 0.2 0.25 0.4 Package edge tolerance aaa 0.1 Mold flatness bbb 0.1 Coplanarity ccc 0.08 Lead offset ddd 0.1 Exposed pad offset eee 0.1 Table 102: Package Dimensions Figure 78: Package Dimensional Drawings © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  0.3 0.45 TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 223/230 Package Material Information Please refer to the associated document “TMC43xx Package Material Information, V1.00” for information about available package dimensions and the various tray and reel package options. This document informs you about outside dimensions per tray and/reel and the number of ICs per tray/reel. It also provides information about available packaging units and their weight, as well as box dimension and weight details for outer packaging. The document is available for download on the TMC4361A product page at www.trinamic.com. Should you require a custom-made component packaging solution or a different outer packaging solution, or have questions pertaining to the component packaging choice, please contact our customer service. i NOTE: Our trays and reels are JEDEC-compliant.  Marking Details provided on Single Chip The marking on each single chip shows: ❶ Trinamic emblem. ❷ Product code. ❶ ❸ Date code. ❷ ❹ Location of the copyright holder, which is TRINAMIC in Hamburg, Germany. ❸ ❹ ❺ Lot number. Figure 79: Marking Details on Chip1 1 The image provided is not an accurate rendition of the original product but only serves as illustration. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  ❺ TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 224/230 A P P E ND I C E S 22. Supplemental Directives ESD-DEVICE INSTRUCTIONS This product is an ESD-sensitive CMOS device. It is sensitive to electrostatic discharge.    Provide effective grounding to protect personnel and machines. Ensure work is performed in a nonstatic environment. Use personal ESD control footwear and ESD wrist straps, if necessary. Failure to do so can result in defects, damages and decreased reliability. Producer Information The producer of the product TMC4361A is TRINAMIC GmbH & Co. KG in Hamburg, Germany; hereafter referred to as TRINAMIC. TRINAMIC is the supplier; and in this function provides the product and the production documentation to its customers. Copyright TRINAMIC owns the content of this user manual in its entirety, including but not limited to pictures, logos, trademarks, and resources. © Copyright 2015 TRINAMIC®. All rights reserved. Electronically published by TRINAMIC®, Germany. All trademarks used are property of their respective owners. Redistributions of source or derived format (for example, Portable Document Format or Hypertext Markup Language) must retain the above copyright notice, and the complete Datasheet User Manual documentation of this product including associated Application Notes; and a reference to other available product-related documentation. Trademark Designations and Symbols Trademark designations and symbols used in this documentation indicate that a product or feature is owned and registered as trademark and,'or patent either by TRINAMIC or by ather manufacturers, whose products are used or referred to in combination With TRINAMlC's products and TRINAMlC's product documentation. This documentation is a noncommercial publication that seeks to provide concise scientific and technical user information to the target user. Thus, we only enter trademark designations and symbols in the Short Spec of the documentation that introduces the product at a quick glance. We also enter the trademark designation 'symbol when the product or feature name occurs for the first time in the document. All trademarks used are property of their respective owners. Target User The documentation provided here, is for programmers and engineers only, who are equipped with the necessary skills and have been trained to work with this type of product. The Target User knows how to responsibly make use of this product without causing harm to himself or others, and without causing damage to systems or devices, in which the user incorporates the product. Disclaimer: Life Support Systems TRINAMIC Motion Control GmbH & Co. KG does not authorize or warrant any of its products for use in life support systems, without the specific written consent of TRINAMIC Motion Control GmbH & Co. KG. Life support systems are equipment intended to support or sustain life, and whose failure to perform, when properly used in accordance with instructions provided, can be reasonably expected to result in personal injury or death. Information given in this document is believed to be accurate and reliable. However, no responsibility is assumed for the consequences of its use nor for any infringement © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 225/230 of patents or other rights of third parties which may result from its use. Specifications are subject to change without notice. Disclaimer: Intended Use The data specified in this user manual is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. TRINAMIC products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (Safety-Critical Applications) without TRINAMIC’s specific written consent. TRINAMIC products are not designed nor intended for use in military or aerospace applications or environments or in automotive applications unless specifically designated for such use by TRINAMIC. TRINAMIC conveys no patent, copyright, mask work right or other trade mark right to this product. TRINAMIC assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. Product Documentation Details This document Datasheet User Manual contains the User Information for the Target User. Collateral Documents & Tools This product documentation is related and/or associated with additional tool kits, firmware and other items, as provided on the product page at: www.trinamic.com . The Short Spec forms the preface of the document and is aimed at providing a general product overview. The Main Manual contains detailed product information pertaining to functions, and configuration settings. It contains all other pages of this document. © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 226/230 23. Tables Index Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1: TMC4361A Order Codes ............................................................................................................. 2 2: Pin Names and Descriptions ...................................................................................................... 12 3: SPI Input Control Interface Pins ................................................................................................ 16 4: Read and Write Access Examples .............................................................................................. 17 5: SPI Interface Timing ................................................................................................................ 19 6: Input Filtering Groups (Assigned Pins) ....................................................................................... 20 7: Input Filtering (Assigned Register) ............................................................................................ 20 8: Sample Rate Configuration ....................................................................................................... 21 9: Configuration of Digital Filter Length ......................................................................................... 21 10: Pins Names: Status Events...................................................................................................... 24 11:Register Names: Status Flags and Events ................................................................................. 24 12: Pin Names: Ramp Generator ................................................................................................... 28 13: Register Names: Ramp Generator ........................................................................................... 28 14: Overview of General and Basic Ramp Configuration Options ..................................................... 31 15: Description of TMC4361A Motion Profiles ................................................................................. 33 16: Trapezoidal Ramps: AACTUAL Assignments during Motion ........................................................ 36 17: Parameter Assignments for S-shaped Ramps ........................................................................... 39 18: Minimum and Maximum Values if Real World Units are selected ................................................ 50 19: Minimum and Maximum Values for Steep Slopes for fCLK =16MHz .............................................. 50 20: Pins used for External Step Control ......................................................................................... 51 21: Registers used for External Step Control .................................................................................. 51 22: Pins used for Reference Switches ............................................................................................ 54 23: Dedicated Registers for Reference Switches ............................................................................. 54 24: Reference Configuration and Corresponding Transition of particular Reference Switch ................ 56 25: Overview of different home_event Settings .............................................................................. 59 26: TARGET_REACHED Output Pin Configuration ........................................................................... 63 27: Comparison Selection Grid to generate POS_COMP_REACHED_Flag .......................................... 64 28: Circular motion (X_RANGE = 300) ........................................................................................... 68 29: Dedicated Ramp Timing Pins ................................................................................................... 69 30: Dedicated Ramp Timing Registers ........................................................................................... 69 31: Start Trigger Configuration ..................................................................................................... 70 32: Start Enable Switch Configuration ........................................................................................... 70 33: Parameter Settings Timing Example 1 ..................................................................................... 72 34: Parameter Settings Timing Example 2 ..................................................................................... 73 35: Parameter Settings Timing Example 3 ..................................................................................... 74 36: Pipeline Activation Options ...................................................................................................... 82 37: Pipeline Mapping for different Pipeline Configurations ............................................................... 83 38: Pin Names for SPI Motor Drive ................................................................................................ 87 39: Dedicated SPI Output Registers .............................................................................................. 88 40: Wave Inclination Characteristics of Internal MSLUT .................................................................. 90 41: Overview of the Microstep Behavior Example ........................................................................... 94 42: SPI Output Communication Pins .............................................................................................. 95 43: TMC Stepper Motor Driver Options ........................................................................................ 100 44: Mapping of TMC23x/24x Status Flags .................................................................................... 104 45: Mapping of TMC26x Status Flags ........................................................................................... 110 46: Mapping of TMC2130 Status Flags ......................................................................................... 115 47: Non-TMC Data Transfer Options ............................................................................................ 116 48: Available SPI-DAC Options .................................................................................................... 119 49: Pin Description: NFREEZE ..................................................................................................... 128 50: Pin Descriptions DFREEZE and IFREEZE ................................................................................. 128 51: Dedicated PWM Output Pins ................................................................................................. 130 52: Dedicated PWM Output Registers .......................................................................................... 130 53: Dedicated dcStep Pins .......................................................................................................... 135 54: Dedicated dcStep Registers ................................................................................................... 135 Table 55: Dedicated Decoder Unit Pins ................................................................................................. 141 Table 56: Dedicated Decoder Unit Registers ......................................................................................... 141 Table 57: Pin Assignment based on selected Encoder Setup .................................................................. 143 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 227/230 Table 58: Index Channel Sensitivity ...................................................................................................... 146 Table 59: Supported SPI Encoder Data Transfer Modes ......................................................................... 156 Table 60: Dedicated Closed-Loop and PID Registers .............................................................................. 158 Table 61: Dedicated Reset and Clock Pins ............................................................................................. 169 Table 62: Dedicated Reset and Clock Gating Registers .......................................................................... 169 Table 63: Pin Names for Encoder Output Interface ................................................................................ 172 Table 64: Dedicated SPI Output Registers ............................................................................................ 172 Table 65: General Configuration 0x00 .................................................................................................. 177 Table 66: Reference Switch Configuration 0x01 .................................................................................... 180 Table 67: Start Switch Configuration START_CONF 0x02 ....................................................................... 182 Table 68: Input Filter Configuration Register INPUT_FILT_CONF 0x03 ................................................... 183 Table 69: SPI Output Configuration Register SPI_OUT_CONF 0x04 ........................................................ 186 Table 70: Current Scale Configuration (0x05)........................................................................................ 187 Table 71: Current Scale Values (0x06) .................................................................................................. 188 Table 72: Various Scaling Configuration Registers (0x15…0x1B) ............................................................ 189 Table 73: Encoder Signal Configuration ENC_IN_CONF (0x07) ............................................................... 193 Table 74: Serial Encoder Data Input Configuration ENC_IN_DATA (0x08) ............................................... 194 Table 75: Serial Encoder Data Output Configuration ENC_OUT_DATA (0x09) .......................................... 194 Table 76: Motor Driver Settings (0x0A) ................................................................................................. 195 Table 77: Event Selection Regsiters 0x0B…0x0D ................................................................................... 196 Table 78: Status Event Register EVENTS (0x0E) .................................................................................... 197 Table 79: Status Flag Register STATUS (0x0F) ...................................................................................... 198 Table 80: Various Configuration Registers: S/D, Synchronization, etc. .................................................... 199 Table 81: PWM Configuration Registers. ............................................................................................... 200 Table 82: Ramp Generator Registers .................................................................................................... 204 Table 83: External Clock Frequency Register ......................................................................................... 205 Table 84: Target and Compare Registers .............................................................................................. 205 Table 85: Pipeline Register .................................................................................................................. 206 Table 86: Shadow Register .................................................................................................................. 206 Table 87: Freeze Register .................................................................................................................... 207 Table 88: Reset and Clock Gating Register ............................................................................................ 207 Table 89: Encoder Registers ................................................................................................................ 209 Table 90: PID and Closed-Loop Registers ............................................................................................. 211 Table 91: Miscellaneous Registers ........................................................................................................ 212 Table 92: Transfer Registers ................................................................................................................ 213 Table 93: SinLUT Registers .................................................................................................................. 214 Table 94: SPI-DAC Configuration Registers. .......................................................................................... 215 Table 95: Version Register ................................................................................................................... 215 Table 96: Maximum Ratings: 3.3V supply ............................................................................................. 216 Table 97: Maximum Ratings: 5.0V supply ............................................................................................. 216 Table 98: Maximum Ratings: Temperature ........................................................................................... 216 Table 99: DC Characteristics ................................................................................................................ 217 Table 100: Power Dissipation ............................................................................................................... 217 Table 101: General IO Timing Parameters ............................................................................................ 218 Table 102: Package Dimensions ........................................................................................................... 222 Table 100: Document Revision History ................................................................................................. 230 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 228/230 24. Figures Index Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1: Sample Image TMC4361A Closed-Loop Drive............................................................................ 1 2: Block Diagram .......................................................................................................................... 1 3: S-shaped Velocity Profile ........................................................................................................... 2 4: Hardware Set-up for Closed-loop Operation with TMC262 ........................................................... 2 5: Hardware Set-up for Open-loop Operation with TMC2130............................................................ 2 6: Package Outline: Pin Assignments Top View ............................................................................. 10 7: System Overview .................................................................................................................... 13 8: TMC4361A Connection: VCC=3.3V ........................................................................................... 14 9: TMC4361A with TMC26x Stepper Driver in SPI Mode or S/D Mode ............................................. 14 10: TMC4361A with TMC248 Stepper Driver in SPI Mode ............................................................... 15 11: TMC4361A with TMC2130 Stepper Driver in SPI Mode or S/D Mode ......................................... 15 12: TMC4361A SPI Datagram Structure ........................................................................................ 16 13: Difference between Read and Write Access ............................................................................ 17 14: SPI Timing Datagram ............................................................................................................ 18 15: Reference Input Pins: SR_REF = 1, FILT_L_REF = 1 ............................................................... 22 16: START Input Pin: SR_S = 2, FILT_L_S = 0 ............................................................................. 22 17: Encoder Interface Input Pins: SR_ENC_IN = 0, FILT_L_ENC_IN = 7 ........................................ 22 18: Step/Dir Input Filter Parameter .............................................................................................. 23 19: No Ramp Motion Profile ......................................................................................................... 34 20: Trapezoidal Ramp without Break Point ................................................................................... 35 21: Trapezoidal Ramp with Break Point ........................................................................................ 35 22: S-shaped Ramp without initial and final Acceleration/Deceleration Values ................................. 37 23: S-shaped Ramp with initial and final Acceleration/Deceleration Values ...................................... 38 24: Trapezoidal Ramp with initial Velocity ..................................................................................... 40 25: S-shaped Ramp with initial Start Velocity ................................................................................ 41 26: S-shaped Ramp with Stop Velocity ......................................................................................... 43 27: S-shaped Ramp with Start and Stop Velocity ........................................................................... 44 28: S-shaped Ramps with combined VSTART and ASTART Parameters ........................................... 45 29: sixPoint Ramp: Trapezoidal Ramp with Start and Stop Velocity ................................................ 46 30: Example for U-Turn Behavior of sixPoint Ramp ....................................................................... 47 31: Example for U-Turn Behavior of S-shaped Ramp ..................................................................... 48 32: Direct transition via VACTUAL=0 for S-shaped Ramps ............................................................. 48 33: HOME_REF Monitoring and HOME_ERROR_FLAG .................................................................... 60 34: Ramp Timing Example 1 ........................................................................................................ 72 35: Ramp Timing Example 2 ........................................................................................................ 73 36: Ramp Timing Example 3 ........................................................................................................ 74 37: Single-level Shadow Register Option to replace complete Ramp Motion Profile. ......................... 76 38: Double-stage Shadow Register Option 1, suitable for S-shaped Ramps. ................................... 77 39: Double-stage Shadow Register Option 2, suitable for Trapezoidal Ramps. ................................ 78 40: Double-Stage Shadow Register Option 3, suitable for Trapezoidal Ramps ................................. 79 41: SHADOW_MISS_CNT Parameter for several internal Start Signals ............................................ 80 42: Target Pipeline with Configuration Options ............................................................................. 81 43: Pipeline Example A ................................................................................................................ 84 44: Pipeline Example B ................................................................................................................ 84 45: Pipeline Example C ................................................................................................................ 84 46: Pipeline Example D ............................................................................................................... 84 47: Pipeline Example E ................................................................................................................ 85 48: Pipeline Example F ................................................................................................................ 85 49: Pipeline Example G ............................................................................................................... 85 50: Pipeline Example H ............................................................................................................... 85 51: LUT Programming Example .................................................................................................... 89 52: MSLUT Curve with all possible Base Wave Inclinations (highest Inclination first) ....................... 93 53: SPI Output Datagram Timing ................................................................................................. 96 54: Cover Data Register Composition (CDL – COVER_DATA_LENGTH) ........................................... 98 55: Scaling Example 1 ............................................................................................................... 126 56: Scaling Example 2 ............................................................................................................... 127 57: Calculation of PWM Duty Cycles (PWM_AMPL) ...................................................................... 132 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 229/230 58: TMC4361A connected with TMC23x/24x operating in SPI Mode or PWM Mode ........................ 133 59: dcStep extended Application Operation Area ......................................................................... 136 60: Velocity Profile with Impact through Overload Situation ......................................................... 138 61: Triangular Function that compensates Encoder Misalignments ............................................... 144 62: Outline of ABN Signals of an incremental Encoder ................................................................. 146 63:Serial Data Output: Four Examples ........................................................................................ 151 64: SSI: SSI_IN_CLK_DELAY=0 ................................................................................................. 153 65: SSI: SSI_IN_CLK_DELAY>SER_CLK_IN_HIGH ...................................................................... 153 66: Calculation of the Output Angle with appropriate CL_DELTA_P .............................................. 162 67: Closed-Loop Current Scaling ................................................................................................ 165 68: Closed-Loop Current Scaling Timing Behavior ....................................................................... 166 69: Calculation of the actual Load Angle GAMMA ........................................................................ 167 70: Manual Clock Gating Activation and Wake-Up ....................................................................... 170 71: Automatic Clock Gating Activation and Wake-Up ................................................................... 171 72: Example for SSI Output Configuration: M - Multiturn; S - Singleturn ....................................... 173 73: Internal Circuit Diagram for Layout Example ......................................................................... 219 74: Components Assembly for Application with Encoder .............................................................. 220 75: Top Layer: Assembly Side .................................................................................................... 220 76: Inner Layer (GND) .............................................................................................................. 221 77: Inner Layer (Supply VS) ...................................................................................................... 221 78: Package Dimensional Drawings ............................................................................................ 222 79: Marking Details on Chip1 ...................................................................................................... 223 © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL  TMC4361A Datasheet | Document Revision 1.22 • 2017-JAN-12 230/230 25. Revision History Document Revision History Version Date Author Description 1.00 2014-APR-11 HS, SD First complete version. New release variant, which is a product upgrade of TMC4361. New chapter organization with additional information. Specifically for: 1.10 2016-JUL-20 HS, SV   Chapter 17: Reset and Clock Gating, page 169. Chapter 18: Serial Encoder Output, page 172 . New Layout, ANSI-compliant safety notices. 1.20 2016-NOV-10 HS Repair of references  Maximum velocity, acceleration and bow values changed! Section 6.7.5, page 50 1.21 2016-NOV-25 HS Adaption of register overview that is now more arranged according to features. 1.22 2017-JAN-12 HS 1) Section 2.5 added: TMC5130A and TMC5160 are software compatible from TMC4361A point of view. 2) Default settings for IO ports added. Table 103: Document Revision History © 2015 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany — Terms of delivery and rights to technical change reserved. Download newest version at: www.trinamic.com . Read entire documentation; especially the “Supplemental Directives” on page 224.  MAIN MANUAL 