POWER DRIVER FOR STEPPER MOTORS
INTEGRATED CIRCUITS
TMC5031 DATASHEET
Dual, cost-effective controller and driver for up to two 2-phase bipolar stepper motors.
Integrated motion controller with SPI interface.
APPLICATIONS
CCTV, Security
Antenna Positioning
Heliostat Controller
Battery powered applications
Office Automation
ATM, Cash recycler, POS
Lab Automation
Liquid Handling
Medical
Printer and Scanner
Pumps and Valves
FEATURES
AND
DESCRIPTION
BENEFITS
2-phase stepper motors
Drive Capability up to 2 x 1.1A coil current
Motion Controller with sixPoint™ ramp
Voltage Range 4.75… 16V DC
SPI Interface
2x Ref.-Switch input per axis
Highest Resolution 256 microsteps per full step
Full Protection & Diagnostics
stallGuard2™ high precision sensorless motor load detection
coolStep™ load dependent current saves up to 75% energy
spreadCycle™ high-precision chopper for best current sine wave
form and zero crossing with additional chopSync2™
Compact Size 7x7mm QFN48 package
BLOCK DIAGRAM
The TMC5031 is a low cost motion controller
and driver IC for up to two stepper motors.
It combines two flexible ramp motion
controllers with energy efficient stepper
motor drivers. The drivers support two-phase
stepper motors and offer an industry-leading
feature
set,
including
high-resolution
microstepping, sensorless mechanical load
measurement, load-adaptive power optimization, and low-resonance chopper operation.
All features are controlled by a standard
SPI™ interface. Integrated protection and
diagnostic features support robust and
reliable operation. High integration, high
energy efficiency and small form factor
enable miniaturized designs with low
external component count for cost-effective
and highly competitive solutions.
2x Ref. Switches
TMC5031
Power
Supply
Charge
Pump
MOTION CONTROLLER
with Linear 6 Point
RAMP Generator
Programmable
256 µStep
Sequencer
Motor 1
DRIVER 1
Protection
& Diagnostics
SPI
Protection
& Diagnostics
MOTION CONTROLLER
with Linear 6 Point
RAMP Generator
Programmable
256 µStep
Sequencer
stallGuard2
2x Ref. Switches
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
Motor 2
DRIVER 2
coolStep
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
2
APPLICATION EXAMPLES: HIGH FLEXIBILITY – MULTIPURPOSE USE
The TMC5031 scores with power density, complete motion controlling features and integrated power
stages. It offers a versatility that covers a wide spectrum of applications from battery systems up to
embedded applications with 1.1A current per motor. The small form factor keeps costs down and allows for
miniaturized layouts. Extensive support at the chip, board, and software levels enables rapid design cycles
and fast time-to-market with competitive products. High energy efficiency and reliability from TRINAMIC’s
coolStep technology deliver cost savings in related systems such as power supplies and cooling.
MINIATURIZED DESIGN
FOR UP TO TWO
STEPPER MOTORS
Ref.
Switches
High-Level
Interface
CPU
SPI
M
TMC5031
Two
reference
switch
inputs can be used for
each motor. A single CPU
controls
the
whole
system, which is highly
economical and space
saving.
Ref.
Switches
High-Level
Interface
CPU
SPI
M
TMC5031
M
Ref.
Switches
TMC5031-EVAL EVALUATION BOARD
EVALUATION & DEVELOPMENT PLATFORM
TMC5031-EVAL is a tiny evaluation board,
combining the TMC5031 with its basic external
components and a 32 bit microcontroller interfacing
to a PC. The firmware source code is available from
the TRINAMIC website to allow own modifications
and to make design-in easy.
The
ORDER CODES
Order code
TMC5031-LA
TMC5031-EVAL
www.trinamic.com
Description
Dual stallGuard2™ and coolStep™ controller/driver, QFN48
Evaluation board for TMC5031
Size [mm2]
7x7
85 x 55
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
3
TABLE OF CONTENTS
1
PRINCIPLES OF OPERATION
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
KEY CONCEPTS
4
SPI CONTROL INTERFACE
5
SOFTWARE
5
MOVING AND CONTROLLING THE MOTOR
5
PRECISION DRIVER WITH PROGRAMMABLE
MICROSTEPPING WAVE
5
STALLGUARD2 – MECHANICAL LOAD SENSING 5
COOLSTEP – LOAD ADAPTIVE CURRENT CONTROL 6
PIN ASSIGNMENTS
2.1
2.2
3
PACKAGE OUTLINE
SIGNAL DESCRIPTIONS
SAMPLE CIRCUITS
3.1
3.2
3.3
3.4
3.5
4
STANDARD APPLICATION CIRCUIT
5 V ONLY SUPPLY
EXTERNAL VCC SUPPLY
OPTIMIZING ANALOG PRECISION
DRIVER PROTECTION AND EME CIRCUITRY
SPI INTERFACE
4.1
4.2
4.3
5
SPI DATAGRAM STRUCTURE
SPI SIGNALS
TIMING
REGISTER MAPPING
5.1
5.2
5.3
6
6.1
7
GENERAL CONFIGURATION REGISTERS
RAMP GENERATOR REGISTERS
MOTOR DRIVER REGISTERS
7.3
7.4
8
8.1
8.2
8.3
9
7
7
10
10
12
13
14
15
16
16
17
18
19
20
21
26
32
SENSE RESISTORS
33
34
SPREADCYCLE
CHOPPER
35
CLASSIC 2-PHASE MOTOR CONSTANT OFF TIME
CHOPPER
38
RANDOM OFF TIME
39
CHOPSYNC2 FOR QUIET MOTORS
40
9.6
10
RESTRICTIONS OF RAMP GENERATOR (ERRATA) 47
STALLGUARD2 LOAD MEASUREMENT
10.1
10.2
10.3
10.4
10.5
11
COOLSTEP OPERATION
11.1
11.2
11.3
12
TUNING THE STALLGUARD2 THRESHOLD SGT
STALLGUARD2 UPDATE RATE AND FILTER
DETECTING A MOTOR STALL
HOMING WITH STALLGUARD
LIMITS OF STALLGUARD2 OPERATION
USER BENEFITS
SETTING UP FOR COOLSTEP
TUNING COOLSTEP
SINE-WAVE LOOK-UP TABLE
12.1
12.2
USER BENEFITS
MICROSTEP TABLE
50
51
53
53
53
53
54
54
54
56
57
57
57
13
QUICK CONFIGURATION GUIDE
59
14
GETTING STARTED
62
14.1
15
INITIALIZATION EXAMPLES
CLOCK OSCILLATOR AND CLOCK INPUT
15.1
15.2
15.3
USING THE INTERNAL CLOCK
USING AN EXTERNAL CLOCK
CONSIDERATIONS ON THE FREQUENCY
62
63
63
63
63
16
ABSOLUTE MAXIMUM RATINGS
65
17
ELECTRICAL CHARACTERISTICS
65
17.1
17.2
17.3
18
LAYOUT CONSIDERATIONS
18.1
18.2
18.3
18.4
19
OPERATIONAL RANGE
DC CHARACTERISTICS AND TIMING
CHARACTERISTICS
THERMAL CHARACTERISTICS
EXPOSED DIE PAD
WIRING GND
SUPPLY FILTERING
LAYOUT EXAMPLE
PACKAGE MECHANICAL DATA
65
66
68
69
69
69
69
70
71
DRIVER DIAGNOSTIC FLAGS
41
TEMPERATURE MEASUREMENT
SHORT TO GND PROTECTION
OPEN LOAD DIAGNOSTICS
41
41
41
20
DISCLAIMER
72
42
21
ESD SENSITIVE DEVICE
72
42
43
44
44
46
22
TABLE OF FIGURES
73
23
REVISION HISTORY
74
24
REFERENCES
74
RAMP GENERATOR
9.1
9.2
9.3
9.4
9.5
7
CURRENT SETTING
CHOPPER OPERATION
7.1
7.2
4
REAL WORLD UNIT CONVERSION
MOTION PROFILES
INTERRUPT HANDLING
VELOCITY THRESHOLDS
REFERENCE SWITCHES
www.trinamic.com
19.1
19.2
DIMENSIONAL DRAWINGS
PACKAGE CODES
71
71
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
1
4
Principles of Operation
REFL1
REFR1
ref. / stop switches motor 1
+VM
F
tor
p mo
e
t
S
l
coo river
d
F
reference switch
processing
VCP
CPI
100n
charge pump
CPO
VSA
5VOUT
100n
5V Voltage
regulator
VCC
4.7µ
programmable
sine table
4*256 entry
Step &
Direction pulse
generation
2x linear 6 point
RAMP generator
22n
100n
DRV_ENN
TMC5031
Dual stepper motor
driver / controller
x
Half Bridge 1
Half Bridge 1
O1A1
O1A2
S
N
chopper
O1B1
Half Bridge 2
Half Bridge 2
trol
n co n
Motio
Stepper
#1
+VM
VS
2 phase
stepper
motor
O1B2
BR1A / B
coolStep™
RSENSE
RSENSE
GNDP
stallGuard2™
CSN
SCK
SDI
SDO
SPI™
Control register
set
interrupt out
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
PP
2 x current
comparator
temperature
measurement
2 x DAC
RSENSE=0R25 allows for
maximum coil current
SPI interface
f ace
Inter
INT & position
pulse output
CLK oscillator/
selector
Stepper driver
Protection
& diagnostics
2 x current
comparator
ol
contr
n
RSENSE
RSENSE
BR2A / B
2x linear 6 point
RAMP generator
Half Bridge 2
Half Bridge 2
Step &
Direction pulse
generation
programmable
sine table
4*256 entry
chopper
O2A2
Half Bridge 1
Half Bridge 1
S
N
O2A1
VS
F = 60ns spike filter
100n
+VM
2 phase
stepper
motor
Stepper
#2
DRV_ENN
GND
GNDA
REFR2
DIE PAD
F
REFL2
TST_MODE
F
O2B2
O2B1
x
otor
ep m
t
S
l
o
co
r
drive
reference switch
processing
100n
GNDP
coolStep™
CLK_IN
VCC_IO
2 x DAC
stallGuard2™
Motio
INT
SINGLEDRV
ref. / stop switches motor 2
opt. driver enable
Figure 1.1 Basic application and block diagram
The TMC5031 motion controller and driver chip is an intelligent power component interfacing between
the CPU and up to two stepper motors. All stepper motor logic is completely within the TMC5031. No
software is required to control the motor – just provide target positions. The TMC5031 offers a
number of unique enhancements which are enabled by the system-on-chip integration of driver and
controller. The sixPoint ramp generator of the TMC5031 uses coolStep and stallGuard2 automatically to
optimize every motor movement: TRINAMICs special features contribute toward lower system cost,
greater precision, greater energy efficiency, smoother motion, and cooler operation in stepper motor
applications. The clear concept and the comprehensive solution save design-in time.
1.1
Key Concepts
The TMC5031 implements several advanced features which are exclusive to TRINAMIC products. These
features contribute toward greater precision, greater energy efficiency, higher reliability, smoother
motion, and cooler operation in many stepper motor applications.
stallGuard2™
High-precision load measurement using the back EMF on the motor coils.
coolStep™
Load-adaptive current control which reduces energy consumption by as much as
75%.
spreadCycle™
High-precision chopper algorithm available as an alternative to the traditional
constant off-time algorithm.
sixPoint™
Fast and precise positioning using a hardware ramp generator with a set of four
acceleration / deceleration settings. Quickest response due to dedicated hardware.
In addition to these performance enhancements, TRINAMIC motor drivers also offer safeguards to
detect and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
1.2
5
SPI Control Interface
The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave, another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC5031 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.
The SPI command rate typically is a few commands per complete motor motion.
1.3
Software
From a software point of view the TMC5031 is a peripheral with a number of control and status
registers. Most of them can either be written only or read only, some of the registers allow both read
and write access. In case read-modify-write access is desired for a write only register, a shadow
register can be realized in master software.
1.4
1.4.1
Moving and Controlling the Motor
Integrated Motion Controller
The integrated 32 bit motion controller automatically drives the motors to target positions, or
accelerates to target velocities. All motion parameters can be changed on the fly. The motion
controller recalculates immediately. A minimum set of configuration data consists of acceleration and
deceleration values and the maximum motion velocity. A start and stop velocity is supported as well
as a second acceleration and deceleration setting. The integrated motion controller supports
immediate reaction to mechanical reference switches and to the sensorless stall detection stallGuard2.
Benefits are:
Flexible ramp programming
Efficient use of motor torque for acceleration and deceleration allows higher machine throughput
Immediate reaction to stop and stall conditions
1.5
Precision Driver with Programmable Microstepping
Wave
Current into the motor coils is controlled using a cycle-by-cycle chopper mode. Two chopper modes
are available: a traditional constant off-time mode and the new spreadCycle mode. Constant off-time
mode provides higher torque at the highest velocity, while spreadCycle mode offers smoother
operation and greater power efficiency over a wide range of speed and load. The spreadCycle chopper
scheme automatically integrates a fast decay cycle and guarantees smooth zero crossing performance.
Programmable microstep shapes allow optimizing the motor performance.
Benefits are:
- Significantly improved microstepping with low cost motors
- Motor runs smooth and quiet
- Reduced mechanical resonances yields improved torque
1.6
stallGuard2 – Mechanical Load Sensing
stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
1.7
6
coolStep – Load Adaptive Current Control
coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool, making the drive an efficient and precise solution.
Benefits are:
- Energy efficiency
- Motor generates less heat
- Less or no cooling
- Use of smaller motor
power consumption decreased up to 75%
improved mechanical precision
improved reliability
less torque reserve required → cheaper motor does the job
Figure 1.2 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.
0,9
Efficiency with coolStep
0,8
Efficiency with 50% torque reserve
0,7
0,6
0,5
Efficiency
0,4
0,3
0,2
0,1
0
0
50
100
150
200
250
300
350
Velocity [RPM]
Figure 1.2 Energy efficiency with coolStep (example)
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
Pin Assignments
TST_MODE
O1A1
BR1A
O1A2
VS
GNDP
VS
O1B1
BR1B
O1B2
-
VCP
47
46
45
44
43
42
41
40
39
38
37
Package Outline
48
2.1
INT
1
36
CPI
PP
2
35
CSN
3
34
CPO
GND
SCK
4
33
VCC
SDI
5
32
5VOUT
GND
6
31
GNDA
VCC_IO
7
30
VSA
SDO
8
29
DRV_ENN
GND
9
28
REFL1
GND
10
27
REFR1
CLK
11
26
REFL2
GND
12
25
REFR2
13
14
15
16
17
18
19
20
21
22
23
24
O2A1
BR2A
O2A2
VS
GNDP
VS
O2B1
BR2B
O2B2
-
GND
TMC 5031-LA
QFN48 7mm x 7mm
0.5 pitch
-
2
7
Figure 2.1 TMC5031 pin assignments.
2.2
Pin
GND
Signal Descriptions
VCC_IO
VSA
Number Type
6, 9, 10,
GND
12, 24, 34
7
30
GNDA
5VOUT
31
32
www.trinamic.com
GND
Function
Digital ground pin for IO pins and digital circuitry.
3.3V or 5V I/O supply voltage pin for all digital pins.
Analog supply voltage for 5V regulator – typically supplied with
driver supply voltage. An additional 100nF capacitor to GND (GND
plane) is recommended for best performance.
Analog GND
Output of internal 5V regulator. Attach 2.2μF or larger ceramic
capacitor to GNDA near to pin for best performance. May be used to
supply VCC of chip.
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
Pin
VCC
Number
33
Type
DIE_PAD
-
GND
8
Function
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). May be supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT.
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
CPO
Number
35
Type
O(VCC)
CPI
36
I(VCP)
VCP
37
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22 nF / 50 V capacitor
to CPO.
Output of charge pump. Provide external 100 nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
INT
Number
1
Type
O (Z)
PP
CSN
SCK
SDI
SDO
CLK
2
3
4
5
8
11
O (Z)
I
I
I
O (Z)
I
REFR2
REFL2
REFR1
REFL1
DRV_ENN
25
26
27
28
29
I
I
I
I
I
TST_MODE
48
I
-
13, 23, 38 N.C.
Function
Tristate interrupt output. Can be programmed to provide interrupt
output based on ramp generator flags RAMP_STAT bits 4, 5, 6 & 7
(poscmp_enable=1).
Tristate position compare output for motor 1 (poscmp_enable=1).
Chip select input of SPI interface
Serial clock input of SPI interface
Data input of SPI interface
Tristate data output of SPI interface (enabled with CSN=0)
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
Right reference switch input for motor 2
Left reference switch input for motor 2
Right reference switch input for motor 1
Left reference switch input for motor 1
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
Test mode input. Puts IC into test mode. Tie to GND for normal
operation.
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
Pin
O2A1
BR2A
Number
14
15
Type
O (VS)
O2A2
VS
16
17, 19
O (VS)
GNDP
O2B1
BR2B
18
20
21
GND
O (VS)
O2B2
O1B2
BR1B
22
39
40
O (VS)
O (VS)
O1B1
VS
41
42, 44
O (VS)
GNDP
O1A2
BR1A
43
45
46
GND
O (VS)
O1A1
47
O (VS)
Table 2.4 Power driver pins
www.trinamic.com
9
Function
Motor 2 coil A output 1
Sense resistor connection for motor 2 coil A. Place sense resistor to
GND near pin.
Motor 2 coil A output 2
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 2 coil B output 1
Sense resistor connection for motor 2 coil B. Place sense resistor to
GND near pin.
Motor 2 coil B output 2
Motor 1 coil B output 2
Sense resistor connection for motor 1 coil B. Place sense resistor to
GND near pin.
Motor 1 coil B output 1
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 1 coil A output 2
Sense resistor connection for motor 1 coil A. Place sense resistor to
GND near pin.
Motor 1 coil A output 1
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
3
10
Sample Circuits
The sample circuits show the connection of the external components in different operation and
supply modes. The connection of the bus interface and further digital signals is left out for clarity.
REFR1
CPI
22n
REFL1
Standard Application Circuit
CPO
+VM
+VM
VS
VSA
5VOUT
100n
reference switch
processing
100n
O1A1
Full Bridge A
5V Voltage
regulator
4.7µ
O1A2
Controller 1
Driver 1
Full Bridge B
N
stepper
motor #1
N
stepper
motor #2
O1B2
BR1A
BR1B
TMC5031
SPI interface
S
O1B1
VCC
CSN
SCK
SDI
SDO
100µF
RS1A
charge pump
DRV_ENN
VCP
100n
RS1B
3.1
VS
+VM
100n
O2A1
Full Bridge A
O2A2
PP
Controller 2
Driver 2
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
5V
BR2A
reference switch
processing
VCC_IO
BR2B
RS2A
INT
RS2B
optional
external
clock
12-16MHz
S
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2
REFL2
3.3V
TST_MODE
TS3480
CX33*)
*) For a reliable start-up it is essential that VCC_IO comes up to a minimum of 1.5V before the TMC5031 leaves the reset condition. Therefore,
TRINAMIC recommends using a fast-start-up voltage regulator (e.g. TS3480CX33) in a 3.3V environment.
Figure 3.1 Standard application circuit
The standard application circuit uses a minimum set of additional components in order to operate the
motor. Use low ESR capacitors for filtering the power supply capable to cope with the current ripple.
The current ripple often depends on the power supply and cable length. The VCC_IO voltage can be
supplied from 5VOUT, or from a fast startup 3.3V regulator. In order to minimize linear voltage
regulator power dissipation of the internal 5V voltage regulator in applications where VM is high, a
different (lower) supply voltage can be used for VSA, if available. For best motor chopper
performance, an optional R/C-filter de-couples 5VOUT from digital noise cause by power drawn from
VCC.
Basic layout hints
Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.
Attention
In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop upon power up or power down.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
3.1.1
11
VCC_IO Requirements
For a reliable start-up it is essential that VCC_IO comes up to a minimum of 1.5V before the TMC5031
leaves the reset condition. The reset condition ends earliest 50µs after the time when VSA exceeds its
undervoltage threshold of typically 4.2V, or when 5VOUT exceeds its undervoltage threshold of
typically 3.5V, whichever comes last.
THERE ARE THREE WAYS TO COME UP TO VCC_IO REQUIREMENTS
-
5VOUT can be used directly to supply VCC_IO. In this case there are no further requirements.
-
An external low drop regulator can be used in a 3.3V environment as shown in Figure 3.1.
Note, that most voltage regulators are not suitable for this application because they show a
delayed boot up. The following external regulators are proved by TRINAMIC:
This regulator can be used within the full supply voltage range when tied
to the motor supply voltage.
This regulator can be used to supply VCC_IO from 5VOUT, or from a supply
voltage of up to 15V.
TS3480CX33
LD1117-3.3
VCC_IO can be supplied externally as shown in Figure 3.2 . In this case it is mandatory to
connect the Schottky diode to the logic supply of the external circuitry. Please note, that the
2K resistor is not to be used with 5V I/O voltage.
CPI
22n
CPO
-
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
4.7µ
5V Voltage
regulator
2R2
VCC
+VCC_IO
1K
VCC_IO
MSS1P3
2K
22n
470n
3.3V, only
Figure 3.2 External supply of VCC_IO (showing optional filtering for VCC)
Refer to application note no. 028 Supply Voltage Considerations: VCC_IO in TMC50xx Designs
(www.trinamic.com). Here you will find complete information about connecting VCC_IO.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
REFR1
CPI
22n
REFL1
5 V Only Supply
CPO
+5V
VS
+5V
100n
VSA
5VOUT
reference switch
processing
100n
O1A1
Full Bridge A
5V Voltage
regulator
4.7µ
O1A2
Controller 1
Driver 1
Full Bridge B
N
stepper
motor #1
N
stepper
motor #2
O1B2
470n
BR1A
BR1B
TMC5031
SPI interface
S
O1B1
VCC
CSN
SCK
SDI
SDO
100µF
VS
RS1A
charge pump
DRV_ENN
VCP
RS1B
3.2
12
+5V
100n
O2A1
Full Bridge A
O2A2
PP
Controller 2
Driver 2
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
BR2A
reference switch
processing
VCC_IO
BR2B
RS2A
VCC_IO
5V
INT
RS2B
Optional
external
clock
12-16MHz
S
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2
REFL2
TST_MODE
VCC_IO 3.3V
see standard
application schematic
Figure 3.3 5V only operation
While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
3.3
13
External VCC Supply
Supplying VCC from an external supply is advised, when cooling of the chip is critical, e.g. at high
environment temperatures in combination with high supply voltages (16 V), as the linear regulator is a
major source of on-chip power dissipation. It must be made sure that the external VCC supply comes
up before or synchronously with the 5VOUT supply, because otherwise the power-up reset event may
be missed by the TMC5031. A diode from 5VOUT to VCC ensures this, in case the external voltage
regulator is not a low drop type linear regulator. In order to prevent overload of the internal 5V
regulator when using this diode, an additional series resistor has been added to VSA.
CPI
22n
CPO
An alternative for reduced power dissipation is using a lower supply voltage for VSA, e.g. 6V to 12V.
If power dissipation is critical, but no external supply is available, the clock frequency can be reduced
as a first step by supplying external 12 MHz clock.
The diode is mandatory to satisfy power-up
conditions!
+VM
VCP
charge pump
100n
220R
VSA
5VOUT
+5V
100n
5V Voltage
regulator
4.7µ
VCC
LL4148
470n
Figure 3.4 Using an external 5V supply to reduce linear regulator power dissipation
3.3.1
Internal Regulator Bridged
In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.5). The circuit will benefit from a well-regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.
Well-regulated, stable
supply, better than +-5%
+5V
VSA
5VOUT
4.7µ
5V Voltage
regulator
10R
VCC
470n
Figure 3.5 Using an external 5V supply to bypass internal regulator
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
3.4
14
Optimizing Analog Precision
CPI
22n
CPO
The 5VOUT pin is used as an analog reference for operation of the TMC5031. Performance will degrade
when there is voltage ripple on this pin. Most of the high frequency ripple in a TMC5031 design
results from the operation of the internal digital logic. The digital logic switches with each edge of
the clock signal. Further, ripple results from operation of the charge pump, which operates with
roughly 1 MHz and draws current from the VCC pin. In order to keep this ripple as low as possible, an
additional filtering capacitor can be put directly next to the VCC pin with vias to the GND plane giving
a short connection to the digital GND pins (pin 6 and pin 34). Analog performance is best, when this
ripple is kept away from the analog supply pin 5VOUT, using an additional series resistor of 2.2 Ω to
3.3 Ω. The voltage drop on this resistor will be roughly 100 mV (IVCC * R).
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
5V Voltage
regulator
GNDA
4.7µ
2R2
VCC
470n
Figure 3.6 Adding an RC-Filter on VCC for reduced ripple
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
3.5
15
Driver Protection and EME Circuitry
Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events. It is best practice to avoid ESD events by attaching all
conductive parts, especially the motors themselves to PCB ground, or to apply electrically conductive
plastic parts. In addition, the driver can be protected up to a certain degree against ESD events or live
plugging / pulling the motor, which also causes high voltages and high currents into the motor
connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the dV/dt caused
by ESD events. Larger capacitors will bring more benefit concerning ESD suppression, but cause
additional current flow in each chopper cycle, and thus increase driver power dissipation, especially at
high supply voltages. The values shown are example values – they might be varied between 100pF
and 1nF. The capacitors also dampen high frequency noise injected from digital parts of the circuit
and thus reduce electromagnetic emission. A more elaborate scheme uses LC filters to de-couple the
driver outputs from the motor connector. Varistors in between of the coil terminals eliminate coil
overvoltage caused by live plugging. Optionally protect all outputs by a varistor against ESD voltage.
470pF
100V
OA1
Full Bridge A
OA1
OA2
S
N
stepper
motor
Full Bridge A
50Ohm @
100MHz
V1A
V1
OA2
50Ohm @
100MHz
470pF
100V
BRA
Driver
RSA
470pF
100V
S
N
stepper
motor
V1B
470pF
100V
Driver
100nF
16V
470pF
100V
OB1
Full Bridge B
OB1
Full Bridge B
OB2
50Ohm @
100MHz
V2A
V2
OB2
50Ohm @
100MHz
470pF
100V
BRB
RSB
100nF
16V
470pF
100V
Fit varistors to supply voltage
rating. SMD inductivities
conduct full motor coil
current.
Figure 3.7 Simple ESD enhancement and more elaborate motor output protection
www.trinamic.com
V2B
470pF
100V
Varistors V1 and V2 protect
against inductive motor coil
overvoltage.
V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
4
16
SPI Interface
4.1
SPI Datagram Structure
The TMC5031 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the TMC5031 must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the TMC5031 is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set of the TMC5031. Each register is
accessed via 32 data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
TMC5031 SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
39 ...
8 bit address
8 bit SPI status
... 0
32 bit data
39 ... 32
to TMC5031:
RW + 7 bit address
from TMC5031:
8 bit SPI status
W
39 / 38 ... 32
38...32
LSB (transmitted last)
31 ... 0
8 bit data
8 bit data
31 ... 24
31...28
27...24
23 ... 16
23...20
19...16
8 bit data
8 bit data
15 ... 8
15...12
7 ... 0
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4.1.1
Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC5031, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
17
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to
be set to 0x21 in the access preceding the read access. For a write access to the register
(VMAX), the address byte has to be set to 0x80 + 0x27 = 0xA7. For read access, the data bit
might have any value (-). So, one can set them to 0.
action
read XACTUAL
read XACTUAL
write VMAX:= 0x00ABCDEF
write VMAX:= 0x00123456
data sent to TMC5031
0x2100000000
0x2100000000
0xA700ABCDEF
0xA700123456
data received from TMC5031
0xSS & unused data
0xSS & XACTUAL
0xSS & XACTUAL
0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2
SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32
Bit
7
6
5
4
3
2
1
0
Name
Comment
status_stop_l(2)
status_stop_l(1)
velocity_reached(2)
velocity_reached(1)
driver_error(2)
driver_error(1)
reset_flag
reserved (0)
RAMP_STAT2[0] – 1: Signals motor 2 stop left switch status
RAMP_STAT1[0] – 1: Signals motor 1 stop left switch status
RAMP_STAT2[8] – 1: Signals motor 2 has reached its target velocity
RAMP_STAT1[8] – 1: Signals motor 1 has reached its target velocity
GSTAT[2] – 1: Signals driver 2 driver error (clear by reading GSTAT)
GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)
GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3
Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2
SPI Signals
The SPI bus on the TMC5031 has four signals:
- SCK – bus clock input
- SDI – serial data input
- SDO – serial data output
- CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC5031.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
4.3
18
Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
tDU
SDI
bit39
tDH
bit38
bit0
tDO
SDO
tZC
bit39
bit38
bit0
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3 (CPOL=1 and CPHA=1).
SPI interface timing
Parameter
SCK valid before or after change
of CSN
AC-Characteristics
clock period: tCLK
Symbol
tCC
fSCK
fSCK
assumes
synchronous CLK
tCSH
SCK low time
tCL
SCK high time
tCH
www.trinamic.com
Min
Typ
Max
10
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
*) Min time is for
synchronous CLK
only
*) Min time is for
synchronous CLK
only
assumes minimum
OSC frequency
CSN high time
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
Data out valid time after falling
SCK clock edge
SDI, SCK and CSN filter delay
time
Conditions
Unit
ns
tCLK*)
>2tCLK+10
ns
tCLK*)
>tCLK+10
ns
tCLK*)
>tCLK+10
ns
4
MHz
8
MHz
tDU
10
ns
tDH
10
ns
tDO
no capacitive load
on SDO
tFILT
rising and falling
edge
12
20
tFILT+5
ns
30
ns
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
5
19
Register Mapping
This chapter gives an overview of the complete register set. Some of the registers bundling a number
of single bits are detailed in extra tables. The functional practical application of the settings is
detailed in dedicated chapters.
Note
- All registers become reset to 0 upon power up, unless otherwise noted.
- Add 0x80 to the address Addr for write accesses!
NOTATION OF HEXADECIMAL AND BINARY NUMBERS
0x
%
NOTATION OF R/W FIELD
R
W
R/W
R+C
precedes a hexadecimal number, e.g. 0x04
precedes a multi-bit binary number, e.g. %100
Read only
Write only
Read- and writable register
Clear upon read (i.e. status bit becomes reset after
readout)
OVERVIEW REGISTER MAPPING
REGISTER
DESCRIPTION
General Configuration Registers
These registers contain
global configuration
global status flags
This register set offers registers for
choosing a ramp mode
choosing velocities
homing
acceleration and deceleration
target positioning
This register set offers registers for
driver current control
setting thresholds for coolStep operation
setting thresholds for different chopper modes
a reference switch and stallGuard2 event
configuration
a ramp and reference switch status register
This register set offers registers for
setting / reading out microstep table and
counter
chopper and driver configuration
coolStep and stallGuard2 configuration
reading out stallGuard2 values and driver error
flags
Ramp Generator Motion Control Register Set
Ramp Generator Driver Feature Control Register Set
Motor Driver Register Set
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
5.1
20
General Configuration Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X1F)
R/W
Addr
n
Register
Description / bit names
Bit
GCONF – Global configuration flags
0..2 Reserved, set to 0
3 poscmp_enable
0:
Outputs INT and PP are tristated.
1:
Position compare pulse (PP) and interrupt output
(INT) are available
4..6
7
RW
0x00
11
GCONF
8
9
10
Bit
0
1
R+C
0x01
4
GSTAT
2
3
Bit
3..0
W
R
0x03
0x04
4
8
+
8
www.trinamic.com
TEST_SEL
INPUT
Bit
0..6
7
31..
24
Attention – do not leave the outputs floating in tristate
condition, provide an external pull-up or set this bit 1.
Reserved, set to 0
test_mode
0:
Normal operation
1:
Enable analog test output on pin REFR2
TEST_SEL selects the function of REFR2:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
shaft1
1:
Inverse motor 1 direction
shaft2
1:
Inverse motor 2 direction
lock_gconf
1:
GCONF is locked against further write access.
GSTAT – Global status flags
reset
1:
Indicates that the IC has been reset since the last
read access to GSTAT.
drv_err1
1:
Indicates, that driver 1 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS1 for
details. The flag can only be reset when all error
conditions are cleared.
drv_err2
1:
Indicates, that driver 2 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS2 for
details. The flag can only be reset when all error
conditions are cleared.
uv_cp
1:
Indicates an undervoltage on the charge pump.
The driver is disabled in this case.
SLAVECONF
TEST_SEL:
selects the function of REFR2 in test mode:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
INPUT
Unused, ignore these bits
Reads the state of the DRV_ENN pin
VERSION: 0x01=first version of the IC
Identical numbers mean full digital compatibility.
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
21
GENERAL CONFIGURATION REGISTERS (0X00…0X1F)
R/W
Addr
n
Register
W
0x05
32
X_COMPARE
Description / bit names
Position comparison register for motor 1 position strobe.
Activate poscmp_enable to get position pulse on output PP.
XACTUAL = X_COMPARE:
-
5.2
Output PP becomes high. It returns to a low state, if
the positions mismatch.
Ramp Generator Registers
Addresses Addr are specified for motor 1 (upper value) and motor 2 (second address).
5.2.1
Ramp Generator Motion Control Register Set
RAMP GENERATOR MOTION CONTROL REGISTER SET (MOTOR 1: 0X20…0X2D, MOTOR 2: 0X40…0X4D)
R/W
Addr
n
Register
RW
0x20
0x40
2
RAMPMODE
RW
0x21
0x41
32
XACTUAL
R
0x22
0x42
W
0x23
0x43
18
W
0x24
0x44
16
A1
W
0x25
0x45
20
V1
W
0x26
0x46
24
16
www.trinamic.com
VACTUAL
Description / bit names
RAMPMODE:
0:
Positioning mode (using all A, D and V
parameters)
1:
Velocity mode to positive VMAX (using
AMAX acceleration)
2:
Velocity mode to negative VMAX (using
AMAX acceleration)
3:
Hold mode (velocity remains unchanged,
unless stop event occurs)
Actual motor position (signed)
Hint: This value normally should only be
modified, when homing the drive. In
positioning mode, modifying the register
content will start a motion.
Actual motor velocity from ramp generator
(signed)
The sign matches the motion direction. A
negative sign means motion to lower
XACTUAL.
Motor start velocity (unsigned)
VSTART
Range [Unit]
0…3
-2^31…
+(2^31)-1
+-(2^23)-1
[µsteps / t]
0…(2^18)-1
[µsteps / t]
Set VSTOP ≥ VSTART!
First acceleration between VSTART and V1
(unsigned)
First acceleration / deceleration phase target
velocity (unsigned)
0…(2^16)-1
[µsteps / ta²]
0…(2^20)-1
[µsteps / t]
0: Disables A1 and D1 phase, use AMAX, DMAX
only
Second acceleration between V1 and VMAX
(unsigned)
0…(2^16)-1
[µsteps / ta²]
AMAX
This is the acceleration and deceleration value
for velocity mode.
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
22
RAMP GENERATOR MOTION CONTROL REGISTER SET (MOTOR 1: 0X20…0X2D, MOTOR 2: 0X40…0X4D)
R/W
Addr
n
Register
W
0x27
0x47
23
VMAX
0x28
0x48
16
W
W
W
W
0x2A
0x4A
0x2B
0x4B
0x2C
0x4C
DMAX
Description / bit names
Motion ramp target velocity (for positioning
ensure VMAX ≥ VSTART) (unsigned)
This is the target velocity in velocity mode. It
can be changed any time during a motion.
Deceleration between VMAX and V1 (unsigned)
Deceleration
(unsigned)
16
between
V1
and
VSTOP
16
VSTOP
TZEROWAIT
RW
32
XTARGET
Attention: Do not set 0 in positioning mode!
Waiting time after ramping down to zero
velocity before next movement or direction
inversion can start and before motor power
down starts. Time range is about 0 to 2
seconds.
Hint: The position is allowed to wrap around,
thus, XTARGET value optionally can be treated
as an unsigned number.
Hint: The maximum possible displacement is
+/-((2^31)-1).
Hint: When increasing V1, D1 or DMAX during
a motion, rewrite XTARGET afterwards in order
to trigger a second acceleration phase, if
desired.
www.trinamic.com
1…(2^18)-1
[µsteps / t]
Attention: Set VSTOP ≥ VSTART!
This setting avoids excess acceleration e.g.
from VSTOP to -VSTART.
Target position for ramp mode (signed). Write
a new target position to this register in order
to activate the ramp generator positioning in
RAMPMODE=0.
Initialize
all
velocity,
acceleration and deceleration parameters
before.
0x2D
0x4D
0…(2^16)-1
[µsteps / ta²]
1…(2^16)-1
[µsteps / ta²]
D1
Attention: Do not set 0 in positioning mode,
even if V1=0!
Motor stop velocity (unsigned)
18
Range [Unit]
0…(2^23)-512
[µsteps / t]
0…(2^16)-1 *
512 tCLK
-2^31…
+(2^31)-1
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
5.2.2
23
Ramp Generator Driver Feature Control Register Set
RAMP GENERATOR DRIVER FEATURE CONTROL REGISTER SET (MOTOR 1: 0X30…0X36, MOTOR 2: 0X50…0X56)
R/W
W
Addr
n
0x30
0x50
5
+
5
+
4
Register
IHOLD_IRUN
Description / bit names
Bit
IHOLD_IRUN – Driver current control
4..0 IHOLD
Standstill current (0=1/32…31=32/32)
12..8 IRUN
Motor run current (0=1/32…31=32/32)
19..16
Hint: Choose sense resistors in a way, that normal
IRUN is 16 to 31 for best microstep performance.
IHOLDDELAY
Controls the number of clock cycles for motor
power down after a motion as soon as TZEROWAIT
has expired. The smooth transition avoids a motor
jerk upon power down.
0:
1..15:
W
0x31
0x51
instant power down
Delay per current reduction step in multiple
of 2^18 clocks
This is the lower threshold velocity for switching on smart
energy coolStep. (unsigned)
Set this parameter to disable coolStep at low speeds, where it
cannot work reliably.
23
VCOOLTHRS
VHIGH ≥ |VACT| ≥ VCOOLTHRS:
- coolStep is enabled, if configured
(Only bits 22..8 are used for value and for comparison)
This velocity setting allows velocity dependent switching into
a different chopper mode and fullstepping to maximize torque.
(unsigned)
W
RW
R+C
R
0x32
0x52
0x34
0x54
0x35
0x55
0x36
0x56
23
11
14
32
VHIGH
SW_MODE
RAMP_STAT
XLATCH
|VACT| ≥ VHIGH:
- coolStep is disabled (motor runs with normal current
scale)
- If vhighchm is set, the chopper switches to chm=1
with TFD=0 (constant off time with slow decay, only).
- chopSync2 is switched off (SYNC=0)
- If vhighfs is set, the motor operates in fullstep mode.
(Only bits 22..8 are used for value and for comparison)
Switch mode configuration
See separate table!
Ramp status and switch event status
See separate table!
Ramp generator latch position, latches XACTUAL upon a
programmable switch event (see SW_MODE).
time reference t for velocities: t = 2^24 / fCLK
time reference ta² for accelerations: ta² = 2^41 / (fCLK)²
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
24
6.2.2.1 SW_MODE – Reference Switch and stallGuard2 Event Configuration
Register
0X34, 0X54: SW_MODE – REFERENCE SWITCH AND STALLGUARD2 EVENT CONFIGURATION REGISTER
Bit
11
Name
en_softstop
Comment
0: Hard stop
1: Soft stop
The soft stop mode always uses the deceleration ramp settings DMAX, V1,
D1, VSTOP and TZEROWAIT for stopping the motor. A stop occurs when
the velocity sign matches the reference switch position (REFL for negative
velocities, REFR for positive velocities) and the respective switch stop
function is enabled.
A hard stop also uses TZEROWAIT before the motor becomes released.
10
sg_stop
9
8
latch_r_inactive
7
latch_r_active
6
latch_l_inactive
5
latch_l_active
Attention: Do not use soft stop in combination with stallGuard2.
1: Enable stop by stallGuard2. Disable to release motor after stop event.
Attention: Do not enable during motor spin-up, wait until the motor
velocity exceeds a certain value, where stallGuard2 delivers a stable result.
Reserved, set to 0
1: Activates latching of the position to XLATCH upon an inactive going
edge on the right reference switch input REFR. The active level is defined
by pol_stop_r.
1: Activates latching of the position to XLATCH upon an active going edge
on the right reference switch input REFR.
Hint: Activate latch_r_active to detect any spurious stop event by reading
status_latch_r.
1: Activates latching of the position to XLATCH upon an inactive going
edge on the left reference switch input REFL. The active level is defined
by pol_stop_l.
1: Activates latching of the position to XLATCH upon an active going edge
on the left reference switch input REFL.
4
3
swap_lr
pol_stop_r
2
pol_stop_l
1
stop_r_enable
Hint: Activate latch_l_active to detect any spurious stop event by reading
status_latch_l.
1: Swap the left and the right reference switch input
Sets the active polarity of the right reference switch input
0=non-inverted, high active: a high level on REFR stops the motor
1=inverted, low active: a low level on REFR stops the motor
Sets the active polarity of the left reference switch input
0=non-inverted, high active: a high level on REFL stops the motor
1=inverted, low active: a low level on REFL stops the motor
1: Enables automatic motor stop during active right reference switch input
0
stop_l_enable
Hint: The motor restarts in case the stop switch becomes released.
1: Enables automatic motor stop during active left reference switch input
Hint: The motor restarts in case the stop switch becomes released.
www.trinamic.com
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
25
6.2.2.2 RAMP_STAT – Ramp and Reference Switch Status Register
0X35, 0X55: RAMP_STAT – RAMP AND REFERENCE SWITCH STATUS REGISTER
R/W
R
Bit
13
Name
status_sg
R+C
12
second_move
R
11
R
R
10
9
R
8
R+C
7
t_zerowait_
active
vzero
position_
reached
velocity_
reached
event_pos_
reached
R+C
6
event_stop_
sg
R
5
event_stop_r
4
event_stop_l
3
status_latch_r
2
status_latch_l
1
0
status_stop_r
status_stop_l
R+C
R
www.trinamic.com
Comment
1: Signals an active stallGuard2 input from the coolStep driver, if
enabled.
Hint: When polling this flag, stall events may be missed – activate
sg_stop to be sure not to miss the stall event.
1: Signals that the automatic ramp requires moving back in the
opposite direction, e.g. due to on-the-fly parameter change
(Flag is cleared upon reading)
1: Signals, that TZEROWAIT is active after a motor stop. During this
time, the motor is in standstill.
1: Signals, that the actual velocity is 0.
1: Signals, that the target position is reached.
This flag becomes set while XACTUAL and XTARGET match.
1: Signals, that the target velocity is reached.
This flag becomes set while VACTUAL and VMAX match.
1: Signals, that the target position has been reached
(position_reached becoming active).
(Flag and interrupt condition are cleared upon reading)
This bit is ORed to the interrupt output signal.
1: Signals an active StallGuard2 stop event.
Reading the register will clear the stall condition and the motor may
re-start motion, unless the motion controller has been stopped.
(Flag and interrupt condition are cleared upon reading)
This bit is ORed to the interrupt output signal.
1: Signals an active stop right condition due to stop switch.
The stop condition and the interrupt condition can be removed by
setting RAMP_MODE to hold mode or by commanding a move to the
opposite direction. In soft_stop mode, the condition will remain
active until the motor has stopped motion into the direction of the
stop switch. Disabling the stop switch or the stop function also
clears the flag, but the motor will continue motion.
This bit is ORed to the interrupt output signal.
1: Signals an active stop left condition due to stop switch.
The stop condition and the interrupt condition can be removed by
setting RAMP_MODE to hold mode or by commanding a move to the
opposite direction. In soft_stop mode, the condition will remain
active until the motor has stopped motion into the direction of the
stop switch. Disabling the stop switch or the stop function also
clears the flag, but the motor will continue motion.
This bit is ORed to the interrupt output signal.
1: Latch right ready
(enable position latching using SWITCH_MODE settings
latch_r_active or latch_r_inactive)
(Flag is cleared upon reading)
1: Latch left ready
(enable position latching using SWITCH_MODE settings
latch_l_active or latch_l_inactive)
(Flag is cleared upon reading)
Reference switch right status (1=active)
Reference switch left status (1=active)
TMC5031 DATASHEET (Rev. 1.11 / 2016-APR-28)
5.3
26
Motor Driver Registers
MOTOR DRIVER REGISTER SET (MOTOR 1: 0X60…0X6F, MOTOR 2: 0X70…0X7F)
R/W
Addr
n
W
0x60
0x70
32
W
W
W
0x61
…
0x67
0x71
…
0x77
0x68
0x78
0x69
0x79
7
x
32
32
8
+
8
Register
MSLUT1[0]
MSLUT2[0]
microstep
table entries
0…31
MSLUT1[1...7]
MSLUT2[1...7]
microstep
table entries
32…255
MSLUTSEL1
MSLUTSEL2
MSLUTSTART
Description / bit names
Each bit gives the difference between
microstep x and x+1 when combined with
the corresponding MSLUTSEL W bits:
0: W= %00: -1
%01: +0
%10: +1
%11: +2
1: W= %00: +0
%01: +1
%10: +2
%11: +3
This is the differential coding for the first
quarter of a wave. Start values for CUR_A and
CUR_B are stored for MSCNT position 0 in
START_SIN and START_SIN90_120.
ofs31, ofs30, …, ofs01, ofs00
…
ofs255, ofs254, …, ofs225, ofs224
This register defines four segments within
each quarter MSLUT wave. Four 2 bit entries
determine the meaning of a 0 and a 1 bit in
the corresponding segment of MSLUT.
See separate table!
bit 7… 0:
START_SIN
bit 23… 16: START_SIN90_120
START_SIN gives the absolute current at
microstep table entry 0.
START_SIN90_120 gives the absolute current
for microstep table entry at positions 256.
Start values are transferred to the microstep
registers CUR_A and CUR_B, whenever the
reference position MSCNT=0 is passed.
R
0x6A
0x7A
10
MSCNT
R
0x6B
0x7B
9
+
9
MSCURACT
RW
0x6C
0x7C
32
CHOPCONF
W
0x6D
0x7D
25
COOLCONF
www.trinamic.com
Microstep counter. Indicates actual position
in the microstep table for CUR_A. CUR_B uses
an offset of 256.
Hint: Move to a position where MSCNT is
zero before re-initializing MSLUTSTART or
MSLUT and MSLUTSEL.
bit 8… 0:
CUR_A (signed):
Actual microstep current for
motor phase A as read from
MSLUT (not scaled by current)
bit 24… 16: CUR_B (signed):
Actual microstep current for
motor phase B as read from
MSLUT (not scaled by current)
chopper and driver configuration
See separate table!
coolStep smart current control register
and stallGuard2 configuration
See separate table!
Range [Unit]
32x 0 or 1
reset default=
sine wave
table
7x
32x 0 or 1
reset default=
sine wave
table
0
工商网监
湘ICP备2023018690号
