POWER DRIVER FOR STEPPER MOTORS
INTEGRATED CIRCUITS
TMC5041 DATASHEET
Dual controller/driver for up to two 2-phase bipolar stepper motors. stealthChop™ no-noise stepper
operation. Integrated motion controller with SPI interface.
APPLICATIONS
CCTV, Security
Office Automation
Antenna Positioning
Battery powered applications
ATM, Cash recycler, POS
Lab Automation
Liquid Handling
Medical
Printer and Scanner
Pumps and Valves
FEATURES
AND
BENEFITS
DESCRIPTION
Two 2-phase stepper motors
Drive Capability up to 2x 1.1A coil current (2x 1.5A peak)
Motion Controller with sixPoint™ ramp
Voltage Range 4.75… 26V DC
SPI Interface
2x Ref.-Switch input per axis
Highest Resolution up to 256 microsteps per full step
stealthChop™ for extremely quiet operation and smooth motion
spreadCycle™ highly dynamic motor control chopper
stallGuard2™ high precision sensorless motor load detection
coolStep™ current control for energy savings up to 75%
Passive Breaking and freewheeling mode
Full Protection & Diagnostics
Compact Size 7x7mm2 QFN48 package
The TMC5041 is a cost-effective dual
stepper motor controller and driver IC
with serial communication interface. It
combines flexible ramp generators for
automatic
target
positioning
with
industries’ most advanced stepper motor
drivers.
Based
on
TRINAMICs
sophisticated stealthChop chopper, the
driver ensures absolutely noiseless
operation combined with maximum
efficiency and best motor torque. High
integration, high energy efficiency and a
small form factor enable miniaturized
and scalable systems for cost effective
solutions. The complete solution reduces
learning curve to a minimum while
giving best performance in class. This
ensures a highly competitive solution.
BLOCK DIAGRAM
2x Ref. Switches
Power
Supply
Charge
Pump
TMC5041
MOTION CONTROLLER
with Linear 6 Point
RAMP Generator
Programmable
256 µStep
Sequencer
Motor 1
DRIVER 1
Protection
& Diagnostics
SPI
Protection
& Diagnostics
MOTION CONTROLLER
with Linear 6 Point
RAMP Generator
Motor 2
Programmable
256 µStep
Sequencer
DRIVER 2
stallGuard2
2x Ref. Switches
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
coolStep
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
2
APPLICATION EXAMPLES: HIGH FLEXIBILITY – MULTIPURPOSE USE
The TMC5041 scores with power density, complete motion controlling features and integrated power
stages. It offers a versatility that covers a wide spectrum of applications from battery systems up to
embedded applications with 1.5A motor current per coil. The small form factor keeps costs down and
allows for miniaturized layouts. Extensive support at the chip, board, and software levels enables rapid
design cycles and fast time-to-market with competitive products. High energy efficiency and reliability
deliver cost savings in related systems such as power supplies and cooling.
MINIATURIZED DESIGN
FOR UP TO TWO
STEPPER MOTORS
Ref.
Switches
High-Level
Interface
CPU
SPI
M
TMC5041
Two reference switch inputs
can be used for each motor.
A single CPU controls the
whole system, which is
highly economical and space
saving, because the TMC5041
covers
all
functionality
required to drive the motor.
Ref.
Switches
High-Level
Interface
CPU
SPI
M
TMC5041
M
Ref.
Switches
TMC5041-EVAL EVALUATION BOARD
EVALUATION & DEVELOPMENT PLATFORM
The TMC5041-EVAL is part of TRINAMICs universal
Layout for Evaluation
evaluation board system which provides a
convenient handling of the hardware as well as a
user-friendly software tool for evaluation. The
TMC5041 evaluation board system consists of three
parts: STARTRAMPE (base board), ESELSBRÜCKE
(connector board including several test points), and
TMC5041-EVAL.
ORDER CODES
Order code
TMC5041-LA
TMC5041-EVAL
STARTRAMPE
ESELSBRÜCKE
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Description
Dual axis stealthChop controller/driver, QFN-48
Evaluation board for TMC5041
Baseboard for TMC5041-EVAL and further evaluation boards
Connector board for plug-in evaluation board system
Size [mm2]
7x7
85 x 55
85 x 55
61 x 38
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
3
TABLE OF CONTENTS
1
PRINCIPLES OF OPERATION
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2
KEY CONCEPTS
5
SPI CONTROL INTERFACE
6
SOFTWARE
6
MOVING AND CONTROLLING THE MOTOR
6
STEALTHCHOP DRIVER WITH PROGRAMMABLE
MICROSTEPPING WAVE
6
STALLGUARD2 – MECHANICAL LOAD SENSING 6
COOLSTEP – LOAD ADAPTIVE CURRENT CONTROL 7
PIN ASSIGNMENTS
2.1
2.2
3
PACKAGE OUTLINE
SIGNAL DESCRIPTIONS
SAMPLE CIRCUITS
3.1
3.2
3.3
3.4
3.5
4
STANDARD APPLICATION CIRCUIT
5 V ONLY SUPPLY
EXTERNAL 5V POWER SUPPLY
OPTIMIZING ANALOG PRECISION
DRIVER PROTECTION AND EME CIRCUITRY
SPI INTERFACE
4.1
4.2
4.3
5
SPI DATAGRAM STRUCTURE
SPI SIGNALS
TIMING
REGISTER MAPPING
5.1
5.2
5.3
5.4
5.5
6
6.1
7
GENERAL CONFIGURATION REGISTERS
RAMP GENERATOR REGISTERS
MICROSTEP TABLE REGISTERS
MOTOR DRIVER REGISTERS
VOLTAGE PWM MODE STEALTHCHOP
7.5
7.6
8
9
9.1
9.2
9.3
8
8
11
11
12
13
14
14
16
16
17
18
19
20
22
28
30
35
36
SENSE RESISTORS
37
38
TWO MODES FOR CURRENT REGULATION
38
AUTOMATIC SCALING
39
FIXED SCALING
41
COMBINING STEALTHCHOP WITH OTHER CHOPPER
MODES
43
FLAGS IN STEALTHCHOP
44
FREEWHEELING AND PASSIVE MOTOR BRAKING 45
SPREADCYCLE AND CLASSIC CHOPPER
8.1
8.2
8.3
8
CURRENT SETTING
STEALTHCHOP™
7.1
7.2
7.3
7.4
5
SPREADCYCLE
CHOPPER
CLASSIC CONSTANT OFF TIME CHOPPER
RANDOM OFF TIME
46
47
50
51
DRIVER DIAGNOSTIC FLAGS
52
TEMPERATURE MEASUREMENT
SHORT TO GND PROTECTION
OPEN LOAD DIAGNOSTICS
52
52
52
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10
RAMP GENERATOR
10.1
10.2
10.3
10.4
10.5
11
REAL WORLD UNIT CONVERSION
MOTION PROFILES
INTERRUPT HANDLING
VELOCITY THRESHOLDS
REFERENCE SWITCHES
53
54
56
56
57
STALLGUARD2 LOAD MEASUREMENT
59
11.1
11.2
11.3
11.4
11.5
12
TUNING STALLGUARD2 THRESHOLD SGT
STALLGUARD2 UPDATE RATE AND FILTER
DETECTING A MOTOR STALL
HOMING WITH STALLGUARD
LIMITS OF STALLGUARD2 OPERATION
COOLSTEP OPERATION
12.1
12.2
12.3
13
53
USER BENEFITS
SETTING UP FOR COOLSTEP
TUNING COOLSTEP
SINE-WAVE LOOK-UP TABLE
13.1
13.2
13.3
USER BENEFITS
MICROSTEP TABLE
CHANGING RESOLUTION
60
62
62
62
62
63
63
63
65
66
66
66
67
14
QUICK CONFIGURATION GUIDE
68
15
GETTING STARTED
72
15.1
INITIALIZATION EXAMPLES
72
16
EXTERNAL RESET
73
17
CLOCK OSCILLATOR AND CLOCK INPUT
73
17.1
17.2
17.3
USING THE INTERNAL CLOCK
USING AN EXTERNAL CLOCK
CONSIDERATIONS ON THE FREQUENCY
73
73
74
18
ABSOLUTE MAXIMUM RATINGS
75
19
ELECTRICAL CHARACTERISTICS
75
19.1
19.2
19.3
20
LAYOUT CONSIDERATIONS
20.1
20.2
20.3
20.4
21
OPERATIONAL RANGE
DC CHARACTERISTICS AND TIMING
CHARACTERISTICS
THERMAL CHARACTERISTICS
EXPOSED DIE PAD
WIRING GND
SUPPLY FILTERING
LAYOUT EXAMPLE
PACKAGE MECHANICAL DATA
21.1
21.2
DIMENSIONAL DRAWINGS
PACKAGE CODES
75
76
79
80
80
80
80
81
82
82
82
22
DESIGN PHILOSOPHY
83
23
DISCLAIMER
83
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
4
24
ESD SENSITIVE DEVICE
83
25
TABLE OF FIGURES
84
26
REVISION HISTORY
85
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27
REFERENCES
85
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
1
5
Principles of Operation
REFL1
REFR1
ref. / stop switches motor 1
+VM
F
tor
p mo
e
t
S
l
coo river
d
F
reference switch
processing
VCP
CPI
100n
charge pump
CPO
VSA
5VOUT
100n
5V Voltage
regulator
VCC
4.7µ
programmable
sine table
4*256 entry
Step &
Direction pulse
generation
2x linear 6 point
RAMP generator
22n
100n
DRV_ENN
TMC5041
Dual stepper motor
driver / controller
Half Bridge 1
Half Bridge 1
S
N
O1B1
Half Bridge 2
Half Bridge 2
trol
n co n
Motio
O1A1
O1A2
spreadCycle &
stealthChop
chopper
x
Stepper
#1
+VM
VS
2 phase
stepper
motor
O1B2
BR1A / B
coolStep™
RSENSE
RSENSE
GNDP
stallGuard2™
CSN
SCK
SDI
SDO
SPI™
Control register
set
interrupt out
opt. ext. clock
8-16MHz
+VIO
3.3V or 5V
I/O voltage
PP
2 x current
comparator
temperature
measurement
2 x DAC
RSENSE=0R25 allows for
maximum coil current
SPI interface
Inte
rface
CLK oscillator/
selector
Stepper driver
Protection
& diagnostics
2 x current
comparator
2 x DAC
GNDP
stallGuard2™
Motio
INT
SINGLEDRV
INT & position
pulse output
ol
contr
n
RSENSE
BR2A / B
2x linear 6 point
RAMP generator
Half Bridge 2
Half Bridge 2
Step &
Direction pulse
generation
programmable
sine table
4*256 entry
reference switch
processing
O2B2
O2B1
O2A2
Half Bridge 1
Half Bridge 1
S
N
O2A1
VS
F = 60ns spike filter
100n
+VM
2 phase
stepper
motor
Stepper
#2
DRV_ENN
GND
GNDA
DIE PAD
F
REFR2
TST_MODE
F
REFL2
100n
x
spreadCycle &
stealthChop
chopper
otor
ep m
t
S
l
o
co
r
drive
CLK_IN
VCC_IO
RSENSE
coolStep™
ref. / stop switches motor 2
opt. driver enable
Figure 1.1 Basic application and block diagram
The TMC5041 motion controller and driver chip is an intelligent power component interfacing between
the CPU and one or two stepper motors. All stepper motor logic is completely within the TMC5041. No
software is required to control the motor – just provide target positions. The TMC5041 offers a
number of unique enhancements which are enabled by the system-on-chip integration of driver and
controller. The sixPoint ramp generator of the TMC5041 uses stealthChop, coolStep, and stallGuard2
automatically to optimize every motor movement. The clear concept and the comprehensive solution
save design time.
1.1 Key Concepts
The TMC5041 implements several advanced features which are exclusive to TRINAMIC products. These
features contribute toward greater precision, greater energy efficiency, higher reliability, smoother
motion, and cooler operation in many stepper motor applications.
stealthChop™
No-noise, high-precision chopper algorithm for inaudible motion and inaudible
standstill of the motor.
stallGuard2™
High-precision load measurement using the back EMF on the motor coils.
coolStep™
Load-adaptive current control which reduces energy consumption by as much as
75%.
spreadCycle™
High-precision chopper algorithm available as an alternative to the traditional
constant off-time algorithm.
sixPoint™
Fast and precise positioning using a hardware ramp generator with a set of four
acceleration / deceleration settings. Quickest response due to dedicated hardware.
In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect
and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
6
1.2 SPI Control Interface
The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC5041 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.
The SPI command rate typically is a few commands per complete motor motion.
1.3 Software
From a software point of view the TMC5041 is a peripheral with a number of control and status
registers. Most of them can either be written only or read only. Some of the registers allow both read
and write access. In case read-modify-write access is desired for a write only register, a shadow
register can be realized in master software.
1.4 Moving and Controlling the Motor
1.4.1
Integrated Motion Controller
The integrated 32 bit motion controller automatically drives the motor to target positions, or
accelerates to target velocities. All motion parameters can be changed on the fly. The motion
controller recalculates immediately. A minimum set of configuration data consists of acceleration and
deceleration values and the maximum motion velocity. A start and stop velocity is supported as well
as a second acceleration and deceleration setting. The integrated motion controller supports
immediate reaction to mechanical reference switches and to the sensorless stall detection stallGuard2.
Benefits are:
Flexible ramp programming
Efficient use of motor torque for acceleration and deceleration allows higher machine throughput
Immediate reaction to stop and stall conditions
1.5 stealthChop Driver with Programmable Microstepping
Wave
Current into the motor coils is controlled using a cycle-by-cycle chopper mode. Up to three chopper
modes are available: a traditional constant off-time mode and the spreadCycle mode as well as the
unique stealthChop. The constant off-time mode provides higher torque at highest velocity, while
spreadCycle mode offers smoother operation and greater power efficiency over a wide range of speed
and load. The spreadCycle chopper scheme automatically integrates a fast decay cycle and guarantees
smooth zero crossing performance. In contrast to the other chopper modes, stealthChop is a voltage
chopper based principle. It guarantees that the motor is absolutely quiet in standstill and in slow
motion, except for noise generated by ball bearings. The extremely smooth motion is beneficial for
many applications.
Programmable microstep shapes allow optimizing the motor performance.
Benefits of using stealthChop:
- Significantly improved microstepping with low cost motors
- Motor runs smooth and quiet
- Absolutely no standby noise
- Reduced mechanical resonances yields improved torque
1.6 stallGuard2 – Mechanical Load Sensing
stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep loadadaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
7
1.7 coolStep – Load Adaptive Current Control
coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool.
Benefits are:
- Energy efficiency
- Motor generates less heat
- Less or no cooling
- Use of smaller motor
power consumption decreased up to 75%
improved mechanical precision
improved reliability
less torque reserve required → cheaper motor does the job
Figure 1.2 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.
0,9
Efficiency with coolStep
0,8
Efficiency with 50% torque reserve
0,7
0,6
0,5
Efficiency
0,4
0,3
0,2
0,1
0
0
50
100
150
200
250
300
350
Velocity [RPM]
Figure 1.2 Energy efficiency with coolStep (example)
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
2
8
Pin Assignments
TST_MODE
O1A1
BR1A
O1A2
VS
GNDP
VS
O1B1
BR1B
O1B2
-
VCP
48
47
46
45
44
43
42
41
40
39
38
37
2.1 Package Outline
INT
1
36
CPI
PP
2
35
CSN
3
34
CPO
GND
SCK
4
33
VCC
SDI
5
32
5VOUT
GND
6
31
GNDA
VCC_IO
7
30
VSA
SDO
8
29
DRV_ENN
GND
9
28
REFL1
GND
10
27
REFR1
CLK
11
26
REFL2
GND
12
25
REFR2
17
18
19
20
21
22
23
24
VS
GNDP
VS
O2B1
BR2B
O2B2
-
GND
15
BR2A
O2A2
14
O2A1
16
13
-
TMC 5041-LA
QFN48 7mm x 7mm
0.5 pitch
Figure 2.1 TMC5041 pin assignments.
2.2 Signal Descriptions
Pin
GND
VCC_IO
VSA
Number Type
6, 9, 10,
GND
12, 24, 34
7
30
GNDA
5VOUT
31
32
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GND
Function
Digital ground pin for IO pins and digital circuitry.
3.3V or 5V I/O supply voltage pin for all digital pins.
Analog supply voltage for 5V regulator – typically supplied with
driver supply voltage. An additional 100nF capacitor to GND (GND
plane) is recommended for best performance.
Analog GND. Tie to GND plane.
Output of internal 5V regulator. Attach 2.2µF or larger ceramic
capacitor to GNDA near to pin for best performance. May be used to
supply VCC of chip.
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
Pin
VCC
Number
33
Type
DIE_PAD
-
GND
9
Function
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). May be supplied by
5VOUT. A 2.2Ω resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT or VCC_IO, whichever comes up
later!
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
CPO
Number
35
Type
O(VCC)
CPI
36
I(VCP)
VCP
37
Function
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
Charge pump capacitor input: Provide external 22nF to 33nF / 50 V
capacitor to CPO.
Output of charge pump. Provide external 100nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
INT
Number
1
Type
O (Z)
PP
CSN
SCK
SDI
SDO
CLK
2
3
4
5
8
11
O (Z)
I
I
I
O (Z)
I
REFR2
REFL2
REFR1
REFL1
DRV_ENN
25
26
27
28
29
I
I
I
I
I
TST_MODE
-
48
I
13, 23, 38 N.C.
Function
Tristate interrupt output based on ramp generator flags RAMP_STAT
bits 4, 5, 6 & 7. Outputs positive active interrupt signal.
Tristate position compare output for motor 1 (poscmp_enable=1).
Chip select input of SPI interface
Serial clock input of SPI interface
Data input of SPI interface
Data output of SPI interface (Tristate, enabled with CSN=0)
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
Right reference switch input for motor 2
Left reference switch input for motor 2
Right reference switch input for motor 1
Left reference switch input for motor 1
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
Test mode input. Tie to GND using short wire.
Unused pins – no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
Pin
O2A1
BR2A
Number
14
15
Type
O (VS)
O2A2
VS
16
17, 19
O (VS)
GNDP
O2B1
BR2B
18
20
21
GND
O (VS)
O2B2
O1B2
BR1B
22
39
40
O (VS)
O (VS)
O1B1
VS
41
42, 44
O (VS)
GNDP
O1A2
BR1A
43
45
46
GND
O (VS)
O1A1
47
O (VS)
Table 2.4 Power driver pins
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10
Function
Motor 2 coil A output 1
Sense resistor connection for motor 2 coil A. Place sense resistor to
GND near pin.
Motor 2 coil A output 2
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 2 coil B output 1
Sense resistor connection for motor 2 coil B. Place sense resistor to
GND near pin.
Motor 2 coil B output 2
Motor 1 coil B output 2
Sense resistor connection for motor 1 coil B. Place sense resistor to
GND near pin.
Motor 1 coil B output 1
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
Power GND. Connect to GND plane near pin.
Motor 1 coil A output 2
Sense resistor connection for motor 1 coil A. Place sense resistor to
GND near pin.
Motor 1 coil A output 1
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
3
11
Sample Circuits
The sample circuits show the connection of the external components in different operation and
supply modes. The connection of the bus interface and further digital signals is left out for clarity.
VSA
5VOUT
4.7µ
REFR1
reference switch
processing
100n
O1A1
Full Bridge A
5V Voltage
regulator
O1A2
Controller 1
2R2
Driver 1
Full Bridge B
470n
N
stepper
motor #1
N
stepper
motor #2
O1B2
BR1A
BR1B
VS
+VM
TMC5041
SPI interface
S
O1B1
VCC
CSN
SCK
SDI
SDO
100µF
RS1A
charge pump
RS1B
VCP
100n
100n
+VM
VS
+VM
DRV_ENN
Optional use lower
voltage down to 6V
REFL1
CPI
22n
CPO
3.1 Standard Application Circuit
100n
O2A1
Full Bridge A
O2A2
opt. ext. clock
12-16MHz
+VIO
3.3V or 5V
I/O voltage
Controller 2
Driver 2
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
BR2A
reference switch
processing
VCC_IO
BR2B
RS2A
PP
RS2B
INT
S
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2
REFL2
TST_MODE
Figure 3.1 Standard application circuit
The standard application circuit uses a minimum set of additional components in order to operate the
motor. Use low ESR capacitors for filtering the power supply which are capable to cope with the
current ripple. The current ripple often depends on the power supply and cable length. The VCC_IO
voltage can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V regulator. In
order to minimize linear voltage regulator power dissipation of the internal 5V voltage regulator in
applications where VM is high, a different (lower) supply voltage can be used for VSA, if available. For
example, many applications provide a 12V supply in addition to a higher supply voltage like 24V.
Using the 12V supply for VSA will reduce the power dissipation of the internal 5V regulator to about
37% of the dissipation caused by supply with the full motor voltage. For best motor chopper
performance, an optional R/C-filter de-couples 5VOUT from digital noise cause by power drawn from
VCC.
Basic layout hints
Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.
Attention
In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop upon power up or power down.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
12
REFR1
REFL1
CPI
22n
CPO
3.2 5 V Only Supply
+5V
VS
+5V
5VOUT
100n
O1A1
Full Bridge A
5V Voltage
regulator
4.7µ
O1A2
Controller 1
Driver 1
Full Bridge B
N
stepper
motor #1
N
stepper
motor #2
O1B2
470n
BR1A
BR1B
VS
+5V
TMC5041
SPI interface
S
O1B1
VCC
CSN
SCK
SDI
SDO
100µF
RS1A
VSA
reference switch
processing
RS1B
charge pump
DRV_ENN
VCP
100n
100n
O2A1
Full Bridge A
O2A2
PP
O2B1
INT & position
pulse output
Full Bridge B
O2B2
CLK_IN
BR2A
reference switch
processing
VCC_IO
BR2B
RS2A
VCC_IO
5V
INT
Driver 2
RS2B
Optional
external
clock
12-16MHz
Controller 2
S
100n
GNDP
GND
GNDA
DIE PAD
DRV_ENN
REFR2
REFL2
TST_MODE
VCC_IO 3.3V
Figure 3.2 5V only operation
While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
13
3.3 External 5V Power Supply
When an external 5V power supply is available, the power dissipation caused by the internal linear
regulator can be eliminated. This especially is beneficial in high voltage applications, and when
thermal conditions are critical. There are two options for using this external 5V source: either the
external 5V source is used to support the digital supply of the driver by supplying the VCC pin, or the
complete internal voltage regulator becomes bridged and is replaced by the external supply voltage.
3.3.1
Support for the VCC Supply
This scheme uses an external supply for all digital circuitry within the driver (Figure 3.3). As the digital
circuitry makes up for most of the power dissipation, this way the internal 5V regulator sees only low
remaining load. The precisely regulated voltage of the internal regulator is still used as the reference
for the motor current regulation as well as for supplying internal analog circuitry.
When cutting pin VCC from 5VOUT, make sure that the VCC supply comes up before or synchronously
with the 5VOUT supply to ensure a correct power up reset of the internal logic. A simple schematic
uses two diodes forming an OR of the internal and the external power supplies for VCC. In order to
prevent the chip from drawing part of the power from its internal regulator, a low drop 1A Schottky
diode is used for the external 5V supply path, while a silicon diode is used for the 5VOUT path. An
enhanced solution uses a dual PNP transistor as an active switch. It minimizes voltage drop and thus
gives best performance.
In certain setups, switching of VCC voltage can be eliminated. A third variant uses the VCC_IO supply
to ensure power-on reset. This is possible, if VCC_IO comes up synchronously with or delayed to VCC.
Use a linear regulator to generate a 3.3V VCC_IO from the external 5V VCC source. This 3.3V regulator
will cause a certain voltage drop. A voltage drop in the regulator of 0.9V or more (e.g. LD1117-3.3)
ensures that the 5V supply already has exceeded the lower limit of about 3.0V once the reset
conditions ends. The reset condition ends earliest, when VCC_IO exceeds the undervoltage limit of
minimum 2.1V. Make sure that the power-down sequence also is safe. Undefined states can result
when VCC drops well below 4V without safely triggering a reset condition. Triggering a reset upon
power-down can be ensured when VSA goes down synchronously with or before VCC.
+VM
+VM
VSA
+5V
100n
4.7µ
VSA
5V Voltage
regulator
5VOUT
5VOUT
+5V
LL4448
100n
4.7µ
VCC
MSS1P3
5V Voltage
regulator
VCC
VCC_IO
3.3V
regulator
470n
470n
100n
3.3V
VCC supplied from external 5V. 5V or 3.3V IO voltage.
VCC supplied from external 5V. 3.3V IO voltage generated from same source.
+VM
VSA
5VOUT
100n
5V Voltage
regulator
4.7µ
+5V
BAT54
10k
VCC
2x BC857 or
1x BC857BS
470n
4k7
VCC supplied from external 5V using active switch. 5V or 3.3V IO voltage.
Figure 3.3 Using an external 5V supply for digital circuitry of driver (different options)
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
3.3.2
14
Internal Regulator Bridged
In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.4). The circuit will benefit from a well regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.
Well-regulated, stable
supply, better than +-5%
+5V
VSA
5V Voltage
regulator
5VOUT
4.7µ
10R
VCC
470n
Figure 3.4 Using an external 5V supply to bypass internal regulator
3.4 Optimizing Analog Precision
CPI
22n
CPO
The 5VOUT pin is used as an analog reference for operation of the TMC5041. Performance will degrade
when there is voltage ripple on this pin. Most of the high frequency ripple in a TMC5041 design
results from the operation of the internal digital logic. The digital logic switches with each edge of
the clock signal. Further, ripple results from operation of the charge pump, which operates with
roughly 1 MHz and draws current from the VCC pin. In order to keep this ripple as low as possible, an
additional filtering capacitor can be put directly next to the VCC pin with vias to the GND plane giving
a short connection to the digital GND pins (pin 6 and pin 34). Analog performance is best, when this
ripple is kept away from the analog supply pin 5VOUT, using an additional series resistor of 2.2 Ω. The
voltage drop on this resistor will be roughly 100 mV (IVCC * R).
+VM
VCP
charge pump
100n
VSA
5VOUT
100n
5V Voltage
regulator
GNDA
4.7µ
2R2
VCC
470n
Figure 3.5 RC-Filter on VCC for reduced ripple
3.5 Driver Protection and EME Circuitry
Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events. It is best practice to avoid ESD events by attaching all
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
15
conductive parts, especially the motors themselves to PCB ground, or to apply electrically conductive
plastic parts. In addition, the driver can be protected up to a certain degree against ESD events or live
plugging / pulling the motor, which also causes high voltages and high currents into the motor
connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the dV/dt caused
by ESD events. Larger capacitors will bring more benefit concerning ESD suppression, but cause
additional current flow in each chopper cycle, and thus increase driver power dissipation, especially at
high supply voltages. The values shown are example values – they might be varied between 100pF
and 1nF. The capacitors also dampen high frequency noise injected from digital parts of the circuit
and thus reduce electromagnetic emission. A more elaborate scheme uses LC filters to de-couple the
driver outputs from the motor connector. Varistors in between of the coil terminals eliminate coil
overvoltage caused by live plugging. Optionally protect all outputs by a varistor against ESD voltage.
470pF
100V
OA1
Full Bridge A
OA1
OA2
S
N
stepper
motor
Full Bridge A
50Ohm @
100MHz
V1A
V1
OA2
50Ohm @
100MHz
470pF
100V
BRA
Driver
RSA
470pF
100V
S
N
stepper
motor
V1B
470pF
100V
Driver
100nF
16V
470pF
100V
OB1
Full Bridge B
OB1
Full Bridge B
OB2
50Ohm @
100MHz
V2A
V2
OB2
50Ohm @
100MHz
470pF
100V
BRB
RSB
100nF
16V
470pF
100V
Fit varistors to supply voltage
rating. SMD inductivities
conduct full motor coil
current.
Figure 3.6 Simple ESD enhancement and more elaborate motor output protection
www.trinamic.com
V2B
470pF
100V
Varistors V1 and V2 protect
against inductive motor coil
overvoltage.
V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
4
16
SPI Interface
4.1 SPI Datagram Structure
The TMC5041 uses 40 bit SPI™ (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the TMC5072 must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the device is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set. Each register is accessed via 32
data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
39 ...
8 bit address
8 bit SPI status
... 0
32 bit data
39 ... 32
to TMC5041:
RW + 7 bit address
from TMC5041:
8 bit SPI status
W
39 / 38 ... 32
38...32
LSB (transmitted last)
31 ... 0
8 bit data
8 bit data
31 ... 24
31...28
27...24
23 ... 16
23...20
19...16
8 bit data
8 bit data
15 ... 8
15...12
7 ... 0
11...8
7...4
3...0
3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4.1.1
Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC5041, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
17
Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to
be set to 0x21 in the access preceding the read access. For a write access to the register
(VACTUAL), the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data
bit might have any value (-). So, one can set them to 0.
action
read XACTUAL
read XACTUAL
write VMAX:= 0x00ABCDEF
write VMAX:= 0x00123456
data sent to TMC5041
0x2100000000
0x2100000000
0xA700ABCDEF
0xA700123456
data received from TMC5041
0xSS & unused data
0xSS & XACTUAL
0xSS & XACTUAL
0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2
SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS – status flags transmitted with each SPI access in bits 39 to 32
Bit
7
6
5
4
3
2
1
0
Name
Comment
status_stop_l(2)
status_stop_l(1)
velocity_reached(2)
velocity_reached(1)
driver_error(2)
driver_error(1)
reset_flag
reserved (0)
RAMP_STAT2[0] – 1: Signals motor 2 stop left switch status
RAMP_STAT1[0] – 1: Signals motor 1 stop left switch status
RAMP_STAT2[8] – 1: Signals motor 2 has reached its target velocity
RAMP_STAT1[8] – 1: Signals motor 1 has reached its target velocity
GSTAT[2] – 1: Signals driver 2 driver error (clear by reading GSTAT)
GSTAT[1] – 1: Signals driver 1 driver error (clear by reading GSTAT)
GSTAT[0] – 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3
Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC5041 has four signals:
- SCK – bus clock input
- SDI – serial data input
- SDO – serial data output
- CSN – chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC5041.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
18
4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
tCC
tCL
tCH
tCH
tCC
SCK
tDU
SDI
bit39
tDH
bit38
bit0
tDO
SDO
tZC
bit39
bit38
bit0
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
Parameter
SCK valid before or after change
of CSN
AC-Characteristics
clock period: tCLK
Symbol
tCC
fSCK
fSCK
assumes
synchronous CLK
tCSH
SCK low time
tCL
SCK high time
tCH
www.trinamic.com
Min
Typ
Max
10
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
*) Min time is for
synchronous CLK
only
*) Min time is for
synchronous CLK
only
assumes minimum
OSC frequency
CSN high time
SCK frequency using internal
clock
SCK frequency using external
16MHz clock
SDI setup time before rising
edge of SCK
SDI hold time after rising edge
of SCK
Data out valid time after falling
SCK clock edge
SDI, SCK and CSN filter delay
time
Conditions
Unit
ns
tCLK*)
>2tCLK+10
ns
tCLK*)
>tCLK+10
ns
tCLK*)
>tCLK+10
ns
4
MHz
8
MHz
tDU
10
ns
tDH
10
ns
tDO
no capacitive load
on SDO
tFILT
rising and falling
edge
12
20
tFILT+5
ns
30
ns
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
5
19
Register Mapping
This chapter gives an overview of the complete register set. Some of the registers bundling a number
of single bits are detailed in extra tables. The functional practical application of the settings is
detailed in dedicated chapters.
Note
- All registers become reset to 0 upon power up, unless otherwise noted.
- Add 0x80 to the address Addr for write accesses!
NOTATION OF HEXADECIMAL AND BINARY NUMBERS
0x
%
precedes a hexadecimal number, e.g. 0x04
precedes a multi-bit binary number, e.g. %100
NOTATION OF R/W FIELD
R
W
R/W
R+C
Read only
Write only
Read- and writable register
Clear upon read
OVERVIEW REGISTER MAPPING
REGISTER
DESCRIPTION
General Configuration Registers
These registers contain
global configuration
global status flags
This register set offers registers for
choosing a ramp mode
choosing velocities
homing
acceleration and deceleration
target positioning
This register set offers registers for
driver current control
setting thresholds for coolStep operation
setting thresholds for different chopper modes
reference switch and stallGuard2 event
configuration
a ramp and reference switch status register
This register set offers registers for
setting / reading out microstep table and
counter
chopper and driver configuration
coolStep and stallGuard2 configuration
reading out stallGuard2 values and driver error
flags
Ramp Generator Motion Control Register Set
Ramp Generator Driver Feature Control Register Set
Motor Driver Register Set
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
20
5.1 General Configuration Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
RW
Addr
n
Register
0x00
11
GCONF
R+C
0x01
4
GSTAT
W
0x03
4
TEST_SEL
R
0x04
9
+
8
INPUT
www.trinamic.com
Description / bit names
Bit
GCONF – Global configuration flags
0..2 Reserved, set to 0
3 poscmp_enable
0:
Outputs INT and PP are tristated.
1:
Position compare pulse (PP) and interrupt output
(INT) are available
Attention – do not leave the outputs floating in tristate
condition, provide an external pull-up
4..6 Reserved, set to 0
7 test_mode
0:
Normal operation
1:
Enable analog test output on pin REFR2
TEST_SEL selects the function of REFR2:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
8 shaft1
1:
Inverse motor 1 direction
9 shaft2
1:
Inverse motor 2 direction
10 lock_gconf
1:
GCONF is locked against further write access.
11 Reserved, set to 0
Bit
GSTAT – Global status flags
0 reset
1:
Indicates that the IC has been reset since the last
read access to GSTAT. All registers have been
cleared to reset values.
1 drv_err1
1:
Indicates, that driver 1 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS1 for
details. The flag can only be reset when all error
conditions are cleared.
2 drv_err2
1:
Indicates, that driver 2 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS2 for
details. The flag can only be reset when all error
conditions are cleared.
3 uv_cp
1:
Indicates an undervoltage on the charge pump.
The driver is disabled in this case.
Select test mode output
Attention: Not for user, set to 0 for normal operation!
Bit
INPUT
0..6 Unused, ignore these bits
7 drv_enn_in: DRV_ENN pin polarity
8 Unused, ignore this bit
31.. VERSION: 0x10=version of the IC
24 Identical numbers mean full digital compatibility.
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
21
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
W
0x05
32
X_COMPARE
Description / bit names
Position comparison register for motor 1 position strobe.
Activate poscmp_enable to get position pulse on output PP.
XACTUAL = X_COMPARE:
-
www.trinamic.com
Output PP becomes high. It returns to a low state, if
the positions mismatch.
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
22
5.2 Ramp Generator Registers
Addresses Addr are specified for motor 1 (upper value) and motor 2 (second address).
5.2.1
Ramp Generator Motion Control Register Set
RAMP GENERATOR MOTION CONTROL REGISTER SET (MOTOR 1: 0X20…0X2D, MOTOR 2: 0X40…0X4D)
R/W
Addr
n
Register
RW
0x20
0x40
2
RAMPMODE
RW
0x21
0x41
32
XACTUAL
R
0x22
0x42
24
VACTUAL
W
0x23
0x43
18
VSTART
W
0x24
0x44
16
A1
W
0x25
0x45
20
V1
W
W
W
W
0x26
0x46
16
0x27
0x47
23
0x28
0x48
16
0x2A
0x4A
Description / bit names
RAMPMODE:
0:
Positioning mode (using all A, D and V
parameters)
1:
Velocity mode to positive VMAX (using
AMAX acceleration)
2:
Velocity mode to negative VMAX (using
AMAX acceleration)
3:
Hold mode (velocity remains unchanged,
unless stop event occurs)
Actual motor position (signed)
Hint: This value normally should only be
modified, when homing the drive. In
positioning mode, modifying the register
content will start a motion.
Actual motor velocity from ramp generator
(signed)
The sign matches the motion direction. A
negative sign means motion to lower
XACTUAL.
Motor start velocity (unsigned)
www.trinamic.com
-2^31…
+(2^31)-1
+-(2^23)-1
[µsteps / t]
0…(2^18)-1
[µsteps / t]
Set VSTOP ≥ VSTART!
First acceleration between VSTART and V1
(unsigned)
First acceleration / deceleration phase
threshold velocity (unsigned)
0…(2^16)-1
[µsteps / ta²]
0…(2^20)-1
[µsteps / t]
0: Disables A1 and D1 phase, use AMAX, DMAX
only
Second acceleration between V1 and VMAX
(unsigned)
0…(2^16)-1
[µsteps / ta²]
This is the acceleration and deceleration value
for velocity mode.
Motion ramp target velocity (for positioning
ensure VMAX ≥ VSTART) (unsigned)
0…(2^23)-512
[µsteps / t]
AMAX
VMAX
DMAX
This is the target velocity in velocity mode. It
can be changed any time during a motion.
Deceleration between VMAX and V1 (unsigned)
Deceleration
(unsigned)
16
Range [Unit]
0…3
between
V1
and
VSTOP
D1
Attention: Do not set 0 in positioning mode,
even if V1=0!
0…(2^16)-1
[µsteps / ta²]
1…(2^16)-1
[µsteps / ta²]
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
23
RAMP GENERATOR MOTION CONTROL REGISTER SET (MOTOR 1: 0X20…0X2D, MOTOR 2: 0X40…0X4D)
R/W
Addr
n
Register
W
0x2B
0x4B
18
VSTOP
W
0x2C
0x4C
16
TZEROWAIT
Description / bit names
Motor stop velocity (unsigned)
Attention: Set VSTOP ≥ VSTART!
Attention: Do not set 0 in positioning mode,
minimum 10 recommended!
Waiting time after ramping down to zero
velocity before next movement or direction
inversion can start and before motor power
down starts. Time range is about 0 to 2
seconds.
This setting avoids excess acceleration e.g.
from VSTOP to -VSTART.
Target position for ramp mode (signed). Write
a new target position to this register in order
to activate the ramp generator positioning in
RAMPMODE=0.
Initialize
all
velocity,
acceleration and deceleration parameters
before.
RW
0x2D
0x4D
32
XTARGET
Hint: The position is allowed to wrap around,
thus, XTARGET value optionally can be treated
as an unsigned number.
Hint: The maximum possible displacement is
+/-((2^31)-1).
Hint: When increasing V1, D1 or DMAX during
a motion, rewrite XTARGET afterwards in order
to trigger a second acceleration phase, if
desired.
www.trinamic.com
Range [Unit]
1…(2^18)-1
[µsteps / t]
0…(2^16)-1 *
512 tCLK
-2^31…
+(2^31)-1
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
5.2.2
24
Ramp Generator Driver Feature Control Register Set
RAMP GENERATOR DRIVER FEATURE CONTROL REGISTER SET (MOTOR 1: 0X30…0X36, MOTOR 2: 0X50…0X56)
R/W
W
Addr
n
Register
0x30
0x50
5
+
5
+
4
IHOLD_IRUN
Description / bit names
Bit
IHOLD_IRUN – Driver current control
4..0 IHOLD
Standstill current (0=1/32…31=32/32)
In combination with stealthChop mode, setting
IHOLD=0 allows to choose freewheeling or coil
short circuit for motor stand still.
12..8 IRUN
Motor run current (0=1/32…31=32/32)
19..16
Hint: Choose sense resistors in a way, that normal
IRUN is 16 to 31 for best microstep performance.
IHOLDDELAY
Controls the number of clock cycles for motor
power down after a motion as soon as TZEROWAIT
has expired. The smooth transition avoids a motor
jerk upon power down.
0:
1..15:
instant power down
Delay per current reduction step in multiple
of 2^18 clocks
This is the lower threshold velocity for switching on smart
energy coolStep and stallGuard feature. Further it is the upper
operation velocity for stealthChop. (unsigned)
W
0x31
0x51
23
VCOOLTHRS
Set this parameter to disable coolStep at low speeds, where it
cannot work reliably. The stop on stall function (enable with
sg_stop when using internal motion controller) becomes
enabled when exceeding this velocity. It becomes disabled
again once the velocity falls below this threshold. This allows
for homing procedures with stallGuard by blanking out the
stallGuard signal at low velocities (will not work in
combination with stealthChop).
VHIGH ≥ |VACT| ≥ VCOOLTHRS:
- coolStep and stop on stall are enabled, if configured
- Voltage PWM mode stealthChop is switched off, if
configured
(Only bits 22..8 are used for value and for comparison)
This velocity setting allows velocity dependent switching into
a different chopper mode and fullstepping to maximize torque.
(unsigned)
W
0x32
0x52
23
VHIGH
|VACT| ≥ VHIGH:
- coolStep is disabled (motor runs with normal current
scale)
- If vhighchm is set, the chopper switches to chm=1
with TFD=0 (constant off time with slow decay, only).
- If vhighfs is set, the motor operates in fullstep mode.
- Voltage PWM mode stealthChop is switched off, if
configured
(Only bits 22..8 are used for value and for comparison)
www.trinamic.com
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
25
RAMP GENERATOR DRIVER FEATURE CONTROL REGISTER SET (MOTOR 1: 0X30…0X36, MOTOR 2: 0X50…0X56)
R/W
RW
R+C
R
Addr
0x34
0x54
0x35
0x55
0x36
0x56
n
12
14
32
Register
SW_MODE
RAMP_STAT
XLATCH
Description / bit names
Switch mode configuration
See separate table!
Ramp status and switch event status
See separate table!
Ramp generator latch position, latches XACTUAL upon a
programmable switch event (see SW_MODE).
Time reference t for velocities: t = 2^24 / fCLK
Time reference ta² for accelerations: ta² = 2^41 / (fCLK)²
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
26
6.2.2.1 SW_MODE – Reference Switch & stallGuard2 Event Configuration Register
0X34, 0X54: SW_MODE – REFERENCE SWITCH AND STALLGUARD2 EVENT CONFIGURATION REGISTER
Bit
11
Name
en_softstop
Comment
0: Hard stop
1: Soft stop
The soft stop mode always uses the deceleration ramp settings DMAX, V1,
D1, VSTOP and TZEROWAIT for stopping the motor. A stop occurs when
the velocity sign matches the reference switch position (REFL for negative
velocities, REFR for positive velocities) and the respective switch stop
function is enabled.
A hard stop also uses TZEROWAIT before the motor becomes released.
10
sg_stop
9
8
latch_r_inactive
7
latch_r_active
6
latch_l_inactive
5
latch_l_active
Attention: Do not use soft stop in combination with stallGuard2.
1: Enable stop by stallGuard2. Disable to release motor after stop event.
Attention: Do not enable during motor spin-up, wait until the motor
velocity exceeds a certain value, where stallGuard2 delivers a stable result,
or set VCOOLTHRS to a suitable value.
Unused, set to 0
1: Activates latching of the position to XLATCH upon an inactive going
edge on the right reference switch input REFR. The active level is defined
by pol_stop_r.
1: Activates latching of the position to XLATCH upon an active going edge
on the right reference switch input REFR.
Hint: Activate latch_r_active to detect any spurious stop event by reading
status_latch_r.
1: Activates latching of the position to XLATCH upon an inactive going
edge on the left reference switch input REFL. The active level is defined
by pol_stop_l.
1: Activates latching of the position to XLATCH upon an active going edge
on the left reference switch input REFL.
4
3
swap_lr
pol_stop_r
2
pol_stop_l
1
stop_r_enable
Hint: Activate latch_l_active to detect any spurious stop event by reading
status_latch_l.
1: Swap the left and the right reference switch input REFL and REFR
Sets the active polarity of the right reference switch input
0=non-inverted, high active: a high level on REFR stops the motor
1=inverted, low active: a low level on REFR stops the motor
Sets the active polarity of the left reference switch input
0=non-inverted, high active: a high level on REFL stops the motor
1=inverted, low active: a low level on REFL stops the motor
1: Enables automatic motor stop during active right reference switch input
0
stop_l_enable
Hint: The motor restarts in case the stop switch becomes released.
1: Enables automatic motor stop during active left reference switch input
Hint: The motor restarts in case the stop switch becomes released.
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TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
27
6.2.2.2 RAMP_STAT – Ramp and Reference Switch Status Register
0X35, 0X55: RAMP_STAT – RAMP AND REFERENCE SWITCH STATUS REGISTER
R/W
R
Bit
13
Name
status_sg
R+C
12
second_move
R
11
R
R
10
9
R
8
R+C
7
t_zerowait_
active
vzero
position_
reached
velocity_
reached
event_pos_
reached
R+C
6
event_stop_
sg
R
5
event_stop_r
4
event_stop_l
3
status_latch_r
2
status_latch_l
1
0
status_stop_r
status_stop_l
R+C
R
www.trinamic.com
Comment
1: Signals an active stallGuard2 input from the coolStep driver, if
configured.
Hint: When polling this flag, stall events may be missed – activate
sg_stop to be sure not to miss the stall event.
1: Signals that the automatic ramp required moving back in the
opposite direction, e.g. due to on-the-fly parameter change
(Flag is cleared upon reading)
1: Signals, that TZEROWAIT is active after a motor stop. During this
time, the motor is in standstill.
1: Signals, that the actual velocity is 0.
1: Signals, that the target position is reached.
This flag becomes set while XACTUAL and XTARGET match.
1: Signals, that the target velocity is reached.
This flag becomes set while VACTUAL and VMAX match.
1: Signals, that the target position has been reached
(position_reached becoming active).
(Flag and interrupt condition are cleared upon reading)
This bit is ORed to the interrupt output signal.
1: Signals an active StallGuard2 stop event.
Reading the register will clear the stall condition and the motor may
re-start motion, unless the motion controller has been stopped.
(Flag and interrupt condition are cleared upon reading)
This bit is ORed to the interrupt output signal.
1: Signals an active stop right condition due to stop switch.
The stop condition and the interrupt condition can be removed by
setting RAMP_MODE to hold mode or by commanding a move to the
opposite direction. In soft_stop mode, the condition will remain
active until the motor has stopped motion into the direction of the
stop switch. Disabling the stop switch or the stop function also
clears the flag, but the motor will continue motion.
This bit is ORed to the interrupt output signal.
1: Signals an active stop left condition due to stop switch.
The stop condition and the interrupt condition can be removed by
setting RAMP_MODE to hold mode or by commanding a move to the
opposite direction. In soft_stop mode, the condition will remain
active until the motor has stopped motion into the direction of the
stop switch. Disabling the stop switch or the stop function also
clears the flag, but the motor will continue motion.
This bit is ORed to the interrupt output signal.
1: Latch right ready
(enable position latching using SWITCH_MODE settings
latch_r_active or latch_r_inactive)
(Flag is cleared upon reading)
1: Latch left ready
(enable position latching using SWITCH_MODE settings
latch_l_active or latch_l_inactive)
(Flag is cleared upon reading)
Reference switch right status (1=active)
Reference switch left status (1=active)
TMC5041 DATASHEET (Rev. 1.13 / 2017-MAY-16)
28
5.3 Microstep Table Registers
COMMON MICROSTEP TABLE REGISTERS (MOTOR 1/2: 0X60…0X69)
R/W
Addr
n
Register
MSLUT[0]
W
0x60
32
microstep
table entries
0…31
MSLUT[1...7]
0x61
…
0x67
W
W
0x68
W
0x69
7
x
32
32
8
+
8
microstep
table entries
32…255
MSLUTSEL
MSLUTSTART
Description / bit names
Each bit gives the difference between entry x
and entry x+1 when combined with the corresponding MSLUTSEL W bits:
0: W= %00: -1
%01: +0
%10: +1
%11: +2
1: W= %00: +0
%01: +1
%10: +2
%11: +3
This is the differential coding for the first
quarter of a wave. Start values for CUR_A and
CUR_B are stored for MSCNT position 0 in
START_SIN and START_SIN90.
ofs31, ofs30, …, ofs01, ofs00
…
ofs255, ofs254, …, ofs225, ofs224
This register defines four segments within
each quarter MSLUT wave. Four 2 bit entries
determine the meaning of a 0 and a 1 bit in
the corresponding segment of MSLUT.
See separate table!
bit 7… 0:
START_SIN
bit 23… 16: START_SIN90
START_SIN gives the absolute current at
microstep table entry 0.
START_SIN90 gives the absolute current for
microstep table entry at positions 256.
Start values are transferred to the microstep
registers CUR_A and CUR_B, whenever the
reference position MSCNT=0 is passed.
Range [Unit]
32x 0 or 1
reset default=
sine wave
table
7x
32x 0 or 1
reset default=
sine wave
table
0
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