TMC6130-EVAL

POWER DRIVER FOR STEPPER MOTORS INTEGRATED CIRCUITS TMC6130 DATASHEET Cost-effective high-current BLDC motor driver with state-of-the-art feature set. Fastest settling time and built-in EEPROM for extensive configuration. APPLICATIONS Battery operated equipment Handcraft gear Professional healthcare Fail-safe applications Low-torque control applications BLDC sine wave applications Positioning Actuators Factory Automation Pumps and Valves CNC Machines FEATURES AND BENEFITS DESCRIPTION Level Shifting: µC PWM outputs / 6 or 3 ext. N-FET half-bridges The TMC6130 is a high-current motor driver for compact and energy efficient BLDC solutions. It is designed to drive N-type FET 3-phase motor control applications and contains all power and analog circuitry required for a high performance system. The built-in EEPROM allows extensive configurability without the need for external resistors and SPI interface programming. This reduces the pin count to only 32. All output voltages are monitored and controlled. The device comprises a current shunt amplifier with a high gain bandwidth (GBW), offering a fast settling time with low noise. A combination of bootstrap and charge pump enables driving 6 (or 3) NFETs, with gate charges up to 400nC/NFET with a minimum of device self-heating. Further, the IC reset level below 4.5V allows also for low-voltage operation. 100% PWM Operation Low Offset, Low Drift, Fast Current Sense Amplifier with configurable input range Operating Range VM = [4.5, 28]V, 32V abs. max Fault Interrupt & Feedback to microcontroller Fastest settling time and minimum noise Diagnostics: overcurrent, overtemperature, undervoltage Configurable communication interface for diagnostics feedback Drain-Source Voltage / Gate-Source Voltage external FET monitoring for short circuit protection Sleep Mode with low quiescent current ( VREG+2*VF with VF = forward voltage of charge pump diodes. CHARGE PUMP MODE = 1 (has to be programmed and stored in EEPROM via SPI) Alternatively, the charge pump can regulate VBOOST compared to VM. In this case the CBOOST capacitor should be connected to VM to ensure any supply variations are coupled to the VBOOST level. The disadvantage is an additional amount of dissipation inside the pre-driver to regulate VREG. The default configuration is stored in the integrated EEPROM. In case CPMODE1 is desired, it is necessary to change EEPROM configuration bits (using the SPI interface or via bit banging). www.trinamic.com TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 11 3.2 100% PWM with Bootstrap A current is drawn from the VCP_SW pin to the phase pins. This current will discharge the gate voltage on top of any external pull down gate resistance. CALCULATION EXAMPLE 1 Parameter bootstrap VCP_reg Qbootstr QFET VGS_initial Rcp_leak Leakage On time Qleak VGS_end VGS_drop Value 330 12 3960 200 11.4 0.75 15 60 914 9.4 2.06 CALCULATION EXAMPLE 2 Unit nF V nC nC V MΩ µA ms nC V V Parameter bootstrap VCP_reg Qbootstr QFET VGS_initial Value 100 12 1200 120 10.9 Unit nF V nC nC V Leakage On time Qleak VGS_end VGS_drop 15 10 152 9.8 1.13 µA ms nC V V This gate leakage will limit the maximum state time during which 100% PWM can be applied. 3.3 Current Consumption in Sleep Mode Sleep mode is activated when the supply input VCC is pulled below VCC_SLEEP level. In sleep mode, the current consumption is reduced to ISSLEEP. Pin Current consumption in Sleep Mode Input/Output BHx BLx ENABLE VREF ERROR CURRENT VCP_REG VCP VCP_SW VCPx HSx BMx Input pins, supplied from VCC GND Supplied from VCC Supply regulator disabled Externally connected to supply. Charge pump disabled. Any charge that remains after VCP_REG is disabled will leak to ground. VM > 4.5V In sleep mode, gate-discharge-resistors (RSGD) between HSx and BMx are activated. VM > 4.5V In sleep mode, gate-discharge-resistors (RSGD) between LSx and DGND are activated. GND GND ~VBAT GND GND LSx GND GND ATTENTION! In case input pins are externally pulled high while VCC is low, current will flow into VCC via internal protection diodes. This condition is not allowed! When VCC is pulled low, also ERROR will go low. This should not be interpreted as a diagnostic interrupt. STATES IN SLEEP MODE www.trinamic.com TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) Name RS+ CUR BL1 BL2 BL3 ERROR ENABLE BM2 HS2 VCP2 BM1 HS1 VCP1 BM3 HS3 VCP3 VCP VCP_REG LS2 LS3 LS1 GNDP VCP_SW VM VMON GNDA BH2 BH1 BH3 VCC VREF RS- Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 www.trinamic.com Type Analog Analog Digital Digital Digital IO IO Phase Output Supply Phase Output Supply Phase Output Supply Analog Analog Output Output Output Ground Analog Supply Input Ground Digital Digital Digital Supply Analog Analog 12 State in Sleep Mode GND GND (tied to VCC) GND (tied to VCC) GND (tied to VCC) GND (tied to VCC) GND (tied to VCC) GND (tied to VCC) Connected via diode to GATE2 Internal pull down (RSGD) to GND Any present charge leaks to GND Connected via Diode to GATE1 Internal pull down (RSGD) to GND Any present charge leaks to GND Connected via Diode to GATE3 Internal pull down (RSGD) to GND Any present charge leaks to GND Connected via charge pump diodes to VBAT GND Internal pull down (RSGD) to GND Internal pull down (RSGD) to GND Internal pull down (RSGD) to GND Driver ground GND Power supply input Connected to supply Analog ground GND (tied to VCC) GND (tied to VCC) GND (tied to VCC) Externally pulled low GND GND TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 4 13 Diagnostics 4.1 ERROR Interface ERROR is a serial interface that feeds back detailed diagnostics information to the microcontroller. Two modes for supplying diagnostic feedback can be used (configured in EEPROM). The default configuration for the TMC6130 is PWM_SPEED = 1. PWM_SPEED = 0 Slow response diagnostic mode PWM period TERROR ≈ 64µs for frequency FERROR_S PWM_SPEED = 1 Fast response diagnostic mode PWM period TERROR ≈ 10µs for frequency FERROR_F In these modes detailed diagnostic information is provided in the form of a PWM duty cycle. Each error corresponds to one duty cycle. The duty cycle is transmitted until the microcontroller acknowledges the reception of the duty cycle. The microcontroller acknowledges by pulling the ERROR line low for a period tACK > tERROR. 2 1 ERROR 1 T MCU T 2 2 3 1 3 ERROR 2 T T T Tack 1 3 ERROR 3 T Tack T EOF T T Tack T T Tack 1 MCU pulls ERROR low. 2 TMC6130 detects acknowledge on falling edge. 3 MCU releases ERROR line. Figure 4.1 ERROR handshake protocol At each falling edge the TMC6130 checks the actual voltage on the ERROR line to detect an acknowledgement. When an acknowledgement is detected the duty cycle value is changed to the corresponding duty cycle value of the highest priority next error that has not yet been transmitted. This sequence of capturing duty cycle and acknowledging continues until the end of the frame (EOF) duty cycle has been received. By acknowledging the EOF duty cycle all error latches are reset and the ERROR line goes high again until a new error occurs. ATTENTION - It is possible that a lower priority error is transmitted before a higher priority error because the higher priority error occurred after the start of transmission of the lower priority error. When VCC is pulled low to put the TMC6130 into sleep mode, ERROR will go low as well. As soon as VCC goes high, ERROR will go high as well and remains high: no EOF is required in this case. As long as the regulated voltages on VCP and VCP_REG have not been achieved, ERROR may immediately start to go in diagnostic mode. This implies the microcontroller has to acknowledge these errors until the undervoltage conditions have been resolved. As soon as ERROR no longer enters diagnostic mode, the pre-driver is ready for operation. www.trinamic.com TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 14 ACKNOWLEDGE ON ERROR For the CPU to acknowledge ERROR it should be able to keep the line low while ERROR is pulling the line high. VCC Microcontroller VCC TMC6130 125C: the extended temperature range is only allowed for a limited period of time. The application mission profile has to be agreed by TRINAMIC. Some analogue parameters may drift out of limits, but chip function is guaranteed. www.trinamic.com TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 9 22 General Electrical Specifications 9.1 Operational Range (unless otherwise specified) Parameter Symbol Min Max Unit Application temperature Supply voltage TMC6130 VCC logic supply input voltage tA VM VCC -40 7 3 125 18 5.5 °C V V Max Units BATTERY SUPPLY Parameter Symbol Supply voltage Supply voltage extended range low Supply voltage extended range high Quiescent current drawn from VM Operating current drawn from VM VM VM_ERL Battery overvoltage threshold high Battery overvoltage threshold low Battery overvoltage threshold hyst Battery overvoltage debounce time Battery undervoltage threshold high Battery undervoltage threshold low Battery undervoltage threshold hyst Battery undervoltage debounce time Power on reset level VM_OVH Pre-driver operation without charge pump operation (EN_CP=0). Warning on ERROR. VM_OVL ERROR released. www.trinamic.com VM_ERH IMSLEEP IM_INT Test Conditions Functional with specification. Functional with specification. VCC = low Min Typ relaxed 7 4.5 18 7 V V relaxed 18 28 V 30 µA 1 mA 35 V VM_OV_HY 31 0.4 V 1 VM_OV_DEB VM_UVH Warning on ERROR. VM_UVL ERROR released. VM_UVHY 0.2 Reset released on rising edge of VM while VCC is high. 2 µS 6 V 5 VM_UV_DEB VPOR V 3 V 0.5 V 10 µS 4.5 V TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 23 POWER AND TEMPERATURE Parameter Overtemperature protection high Overtemperature protection low Symbol OTH Test Conditions Warning on ERROR. Min 153 Typ 166 Max 183 Units OTL ERROR released. 123 137 153 C Symbol ICC Test Conditions Maximum input current includes ERROR current sourcing. Min Typ Max 20 Units mA 230 3 300 370 5.5 KΩ V 2.7 2.8 V 2.6 2.7 V C VCC IO SUPPLY INPUT Parameter VCC operating current VCC pull down resistance VCC_RPD VCC input voltage VCC VCC input undervoltage high 1) VCC input undervoltage low VCC input undervoltage hyst VCC sleep voltage high VCC_UV_H VCC sleep voltage low VCC_SLEEP_L VCC sleep voltage hyst VCC_SLEEP_HY 1) VCC_UV_L VCC = 3.3V or 5V, logic supply. VCC increasing, NFET control is activated. VCC decreasing, disable NFET control. VCC_UV_HY VCC_SLEEP_H 0.07 VCC increasing, out of sleep. VCC decreasing, go to sleep. 0.1 V 2.45 2.6 V 1.9 2 V 0.45 0.58 Min 170 85 Typ V The info VCC_UV_X is used to disable the control of the external FETs. ON-CHIP OSCILLATOR Parameter Charge pump frequency ERROR PWM frequency fast ERROR PWM frequency slow SPI start up pulse duration www.trinamic.com Symbol FCP FERROR_F Test Conditions FERROR_S tSPI_SU EN = Low BH1/2/3 = low BL1/2/3 = high Max 230 115 Units KHz KHz 10.6 14.4 KHz 2048/F OSC 4096/F OSC Sec TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 24 The charge pump of the TMC6130 can be used with three modes of operation. CHARGE PUMP / CPMODE=X (Silicon diodes BAS16, Ccp=1µF,Cboost=1µF +Creg=4.7µF: to be confirmed) Parameter Resistive load from VCP to GND Symbol RCP_LEAK Test Conditions RTYP = room temperature RMIN = 150C (excl. RVCP_REG_LEAK) Min 6 Output slew rate Typ 8 Max Units MΩ 100 Charge pump frequency FCP 170 VCP undervoltage (VCP high) VCP undervoltage (VCP low) VCP_UVH ERROR released. VCP_UVL Warning on ERROR. 200 V/us 230 kHz 7.2 V 6.7 V 5.7 CHARGE PUMP / CPMODE=0 (Silicon diodes BAS16, Ccp=1µF,Cboost=1µF +Creg=4.7µF: to be confirmed) Parameter Symbol CP Load current on ICP_REG_MOD VCP_REG E0 Output voltage VCP_REG VREG Test Conditions VCP_REG > 11V EN_CP = 1 VM > 8V Ireg < 40mA Min Typ Max 40 Units mA 11 12 13 V Output voltage VCP_REG VCP_REG 10 13 V VCP_UVH VM = [7,8]V IVCP_REG < 40mA ERROR released. 7.2 V VCP_UVL Warning on ERROR. 5.7 6.7 V VCP Undervoltage, (VCP high) VCP Undervoltage, (VCP low) CHARGE PUMP / CPMODE=1 (Silicon diodes BAS16, Ccp=1µF,Cboost=1µF +Creg=4.7µF: to be confirmed) Parameter CP load current on VCP_REG Reverse polarity NFET gate voltage (VCP – VM) Output voltage VCP_REG VCP undervoltage, (VCP – VM) high VCP undervoltage, (VCP – VM) low Symbol Test Conditions ICP_REG_MOD VREG > 11V EN_CP = 1 E1 VGS_RPFET VM > 7 IVCP_REG < 20mA Typ Max 20 Units mA 5 12 13 V 12 13 7.2 V V 6.7 V VCP_REG VCP_UVH IREG < 20mA ERROR released. 11 VCP_UVL Warning on ERROR. 5.7 VREG Warnings / CPMODE=X www.trinamic.com Min TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) Parameter Internal resistive load from VCP_REG to GND VCP_REG overvoltage high VCP_REG overvoltage low VCP_REG overvoltage hyst VCP_REG undervoltage high VCP_REG undervoltage low 25 Symbol Test Conditions RVCP_REG_LEA RTYP = Room RMIN = 150C K VCP_REG_OVH Warning on ERROR. Min 0.3 14.2 VCP_REG_OVL ERROR released. 13.5 VCP_REG_OVH 0.7 Typ 0.4 Max Units MΩ 16.5 V V 1 V Y VCP_REG_UVH ERROR released. VCP_REG_UVL Warning on ERROR. VBATF Parameter Symbol Internal leakage from RVMON_LEAK VMON to GND 6.9 8.1 V 7.8 V Test Conditions Pre-driver is not in sleep mode. Min Typ Max 20 Units µA Test Conditions Min 6 4 2.4 Typ 4 7 7 Max 8 15 15 6.5 Units Ω ns ns Ω 5.7 Ω -1 -1.4 A 1 1.6 A 100 ns 20 ns 0.0002 µs 15 % V FET GATE DRIVERS Parameter Driver ON resistance2) Rise time Fall time Pull-up on resistance Symbol RDR_ON tR tF RON_UP Pull down on resistance RON_DN Turn on gate drive peak current Turn off gate drive peak current Propagation delay IG_ON Cload = 1nF, 20% to 80% Cload = 1nF, 80% to 20% -10mA tJ = -40 -10mA, tJ = 150 10mA tJ = -40 10mA, tJ = 150 VGS = 0V IG_OFF VGS = 12V tPD_DRV Propagation delay matching Programmable dead time : asynchronous internal delay between top and bottom FET tPD_DRVM Dead time tolerance Programmable VDS monitor voltage tDEAD_TOL VDS_MON From logic input threshold to 20 2V VGS drive output at no load. Transitions at the different -20 phases at no load condition. DEAD_TIME[2:0] = 000 0.0001 001 010 011 100 101 110 111 -15 VDSMON[2:0] = 000: disabled 0.4 001 0.6 010 0.85 011 1.05 100 1.25 101 1.5 110 1.70 111 www.trinamic.com tDEAD 1.5 0 0.5 0.75 1.0 1.5 2.0 3.0 6.0 0.5 0.75 1.00 1.25 1.50 1.75 2.00 0.6 0.9 1.15 1.45 1.75 2.00 2.3 TMC6130 DATASHEET (Rev. 1.01 / 2018-JAN-19) 26 FET GATE DRIVERS Parameter Programmable VDS monitor blanking time: internal delay between GATE signal high and enabling the corresponding VDS monitor Symbol tVDS_BL VDS blanking time tolerance Sleep gate discharge resistor tVDS_TOL VGS under voltage monitor PWM frequency Leakage from VCPx to BMx VGS_UV 2) RSGD FPWM RCP_LEAK Test Conditions VDS_BLANK_TIME[1:0] = 00 01 10 11 Min Typ 0.75 1.5 3 6 Max Units µs 15 % 1 KΩ 75 %VREG 20 1 100 KHz MΩ Typ Max 70 Units %VCC -15 Internal resistance between FET gate-source pins to switch-off FET. VCC = 0V (sleep mode) VGS = 0.5V See chapter FET driver during sleep mode. Warning on ERROR. Typ = Room Min = 150C TBD 5 0.75 The driver on resistance is