TQPED

Pre-Production Process 0.5 um E/D pHEMT Foundry Service Features Metal 2 Dielectric Metal 2 - 4um TQPED • • • • • Dielectric Metal 1 - 2um Metal 1 Metal 1 Dielectric MIM Metal NiCr Nitride N+ Pseudomorphic Channel Metal 0 Isolation Implant Isolation Isolation Implant MIM Capacitor NiCr Resistor E-Mode / D-Mode pHEMT Semi-Insulating GaAs Substrate • • • • • • 0.5 um pHEMT Device Cross-Section E-Mode, 0.35 V, Vth D-Mode, -0.8 V Vp InGaAs Active Layer pHEMT Process 0.5 um Optical Lithography Gates High Density Interconnects: • 2 Global • 1 Local High-Q Passives Thin Film Resistors High Value Capacitors Backside Vias Optional Based on Production TQPHT pHEMT and Interconnect Nominal TOM3 FET Models Available General Description TriQuint’s TQPED process is based on our production-released 0.5 µm TQPHT process. TQPED partners an E-Mode pHEMT device with our TQPHT D-Mode transistors to be the first foundry pHEMT process to integrate E-Mode and D-Mode transistors on the same wafer. This process is targeted for low noise amplifiers, linear, low loss and high isolation RF switch applications, converters and integrated RF Front Ends. The TQPED process offers a D-Mode pHEMT with a –0.8 V pinch off, and an E-Mode pHEMT with a +0.35 V threshold voltage. The three metal interconnecting layers are encapsulated in a high performance dielectric that allows wiring flexibility, optimized die size and plastic packaging simplicity. Precision NiCr resistors and high value MIM capacitors are included allowing higher levels of integration, while maintaining smaller, cost –effective die sizes. Applications • • • • • • • Highly Efficient, and Linear Power Amplifiers Low Loss, High Isolation, LowHarmonic Contnt Switches Integrated digital control logic for Switches and Transceivers Converters Integrated RF Front Ends– LNA, SW, PA Wireless Transceivers, Base stations, Direct Broadcast Satellite Radars, Digital Radios, RF / Mixed Signal ICs Power Detectors and Couplers Production Release: Q1’2005 Page 1 of 3; Rev 1.0 12/1/2004 Pre-Production Process Production 0.5 um E/D pHEMT Foundry Service TQPED Process Details Process Details @ Vds = 3.0V Element D-Mode pHEMT Parameter Vp (1uA/um) Idss Imax Breakdown, Vdg Ft @ 50% Idss Fmax @ 50% Idss Gm (50% Idss) Ron E-Mode pHEMT Vth (1uA/um) Idss Imax Breakdown, Vdg Ft @ 50% Idss Fmax @ 50% Idss Gm (50% Idss) Ron Value -0.8 225 550 15 min, 20 typ 25 90 350 1.5 +0.35 0.1 310 15 min, 18 typ 30 100 625 2.5 Units V mA/mm mA/mm V GHz GHz mS/mm Ohms * mm V uA/um mA/mm V GHz GHz mS/mm Ohms * mm TQPED Common Process Element Details Gate Length Interconnect MIM Caps Resistors Value NiCr Bulk 0.5 3 630 50 285 -65 to +150 -55 to +150 15 40 µm Metal Layers pF/mm2 Ohms/sq Ohms/sq Deg C Deg C V V Maximum Ratings Storage Temperature Range Operating Temperature Range EFET/DFET Transistor (Vs open; Idg = 1uA/um) Capacitor TriQuint Semiconductor 2300 NE Brookwood Pkwy Hillsboro, Oregon 97124 Semiconductors for Communications www.triquint.com Page 2 of of Rev 1.0 12/1/2004 Page 2 3; 5; Rev 2.0 7/22/03 Phone: 503-615-9000 Fax: 503-615-8905 Email: info@triquint.com Pre-Production Process 0.5 um E/D pHEMT Foundry Service Prototyping and Development Process Qualification Status TQPED • Prototype Development Quick Turn (PDQ): • Shared mask set • Run monthly • Hot Lot cycle time • Prototype Wafer Option (PWO): • Customer-specific masks; Customer schedule • 2 wafers delivered • Hot Lot cycle time • With thinning and sawing; optional backside vias • Mature process based on TQPHT 150-mm process • Process release to production scheduled for Q1 2005 • Full 150mm wafer Process Qualification in process. To be completed early Q1 2005 • For more information on Quality and Reliability, contact TriQuint or visit: www.triquint.com/manufacturing/QR/ • Complete Design Manual Now • Device Library of circuit elements: FETs, diodes, thin film resistors, capacitors, inductors • Design Kit for Agilent’s ADS design environment • Design Kit planned for AWR Microwave Office • Layout Library in GSD II format • Cadence Development Kit with PCells in Preliminary Release • Layout Rule Sets for Design Rule Check for ICED, Cadence • Qualified package models for supported package styles • Noise parameters on specific device sizes available Design Tool Status • • • • • • • • • Tiling of GDSII stream files including PCM Design Rule Check services Layout Versus Schematic check services Packaging Development Engineering Test Development Engineering: • On-wafer • Packaged parts Thermal Analysis Engineering Yield Enhancement Engineering Part Qualification Services Failure Analysis Applications Support Services • GaAs Design Classes: • Half-Day Introduction; Upon request • Four-Day Technical Training; Fall and Spring at TriQuint Oregon facility • For Training & PDQ Schedules, please visit: www.triquint.com/foundry/ Training • • • • • • • • • Mask making Production 150-mm wafer fab Wafer Thinning Wafer Sawing Substrate Vias DC Diesort Testing RF On-wafer testing Plastic Packaging RF Packaged Part Testing Manufacturing Services Please contact your local TriQuint Semiconductor Representative/ Distributor or Foundry Services Division for Additional information: E-mail: sales@triquint.com Phone: (503) 615-9000 Fax: (503) 615-8905 Semiconductors for Communications www.triquint.com Page 3 of 3; Rev 1.0 12/1/2004 TriQuint Semiconductor 2300 NE Brookwood Pkwy Hillsboro, Oregon 97124 Phone: 503-615-9000 Fax: 503-615-8905 Email: info@triquint.com