TS2026LCS

TS2026L Dual-Channel Power Distribution Switch Pin assignment: 1. EN A 2. FLGA 3. FLGB 4. EN B 5. OU TB 6. GND 7. IN 8. OU TA 140mΩ max. on-resistance per channel 2.7V to 5.5V operating range Under voltage lockout General Description The TS2026L is h igh-side MOSFET switches optimized for general-purpose power distribution requiring circuit protection. The TS2026L are internally current limited and have therm al shutdown that protects the device and load. When a thermal shutdown fault occurs, the output is latched off until the faulty load is removed. Removing that load or toggling the enable input w ill reset the device output. Both device employ soft-s tart circuitry that minim ized inrush current in application where h ighly capacitive loads are employed. A fa ult sta tus output flag is asserted during over current and thermal shutdown conditions. Transient faults are internally filtered. Features            140mΩ max. on-resistance per channel 2.7V to 5 .5V operating range 500mA min. continuous current pe r channel Short-circuit p rotection with therma l shutdown Thermal isolated channels. Fault status flag with 3ms filter elim inates fa lse assertions. Under voltage lockout Reverse current flow blocking (no “body diode”) Logic-compatible inputs Soft-sta rt circuit Low quiescent current Applications       USB peripherals General purpose power switching ACPI power d istribution Notebook PCs PDAs PC Card hot swap Ordering Information Part No. T S2 0 2 6 L CS Operat ing Temp. (Ambient) -40 ~ +85 C o Package SOP-8 Absolute Maximum Rating Supply Voltage Fault Flag Voltage Fault Flag Cu rrent Output Voltage Output Current Enable input Storage Temperatu re V IN VFLG IFLG VOUT IOUT IEN TSTG +6 +6 25 +6 Internal L imited -0.3 ~ +3 -65 ~ +150 V o V V mA o C C TS2026L 1 -7 2005/11 rev. A Typical Application Block Diagram TS2026L 2 -7 2005/11 rev. A Electrical Characteristics Vin=5V, TA = 25 C, unless noted o Parameter Symbol OU T = o p e n Condition VENA=VENB≥2.4V (switch off), Min. -- Typ. 0.75 Max. 5 Units uA Supply Current IDD VENA=VENB≤0.8V (switch on), OU T = o p e n --0.8 -- 100 1.7 1.455 250 0.01 1 90 100 -1.3 1.15 35 32 0.9 1.0 20 3 3 160 2.4 --1 -140 160 10 5 4.9 100 100 1.25 1.25 -7 -2.7 2.5 25 40 10 ----- uA V V mV uA pF mΩ mΩ uA mS mS uS uS A A uS mS mS V V Ω Ω uA o o o o Enable Input th reshold Enable Input Hysteresis Enable Input Current Enable Input Capacitance Switch Resistance Note 4 Output Leakage Current Output Turn -on Delay Output Turn -on Rise Time Output Turn -off Delay Output Turn -off Fall T ime Short-C ircuit Output Current Current –Limit Threshold Short-C ircuit Response Time Low-to-high transition VEN High-to-low transition IEN VENA= 0V to 5.5V -1 -- RDS(ON) VIN= 5V, IOUT= 500mA VIN= 3.3V, IOUT= 500mA VENX≤0.8V or VENX≥2 .4V ----- tON tR tOFF tF ILIMIT VOUT= 0V, enable into short-c ircuit Ramped load applied to ou tput VOUT= 0V to IOUT= ILIMIT (short applied to outpu t) VIN=5V, apply VOUT=0V , Until FLG low tD VIN=3.3V, apply VOUT=0V, Until FLG low VIN rising VIN falling IL =10mA, VIN =5V IL =10mA, VIN =3.3V VFLAG =5V TJ increasing, each switch RL=10Ω, CL=1F, see “Timing D iagrams” ---0.5 --1.5 Over current Flag Response Delay Under voltage Lockout Threshold Error Flag Ou tput Resistance Error Flag O ff Curren t 2.2 2.0 -------- 2.4 2.15 10 15 -140 120 160 150 C C C C Over tempera ture Th reshold Note 5 TJ decreasing, each switch TJ increasing, both switch TJ decreasing, both switch Note 1. Exceeding the absolute maximum rating may damag e the device. Note 2. The device is not guaranteed to function outside its o perating ra ting. Note 3. Devices are ESD sensitive . Handing precautions recommended. Note 4. Fo r main tenance RDS≤140mΩ assembly to make gold conductors in diamete r 50m . o Note 5. If there is a fault on one channel, that channel will s hut down when the die reaches approximately 140 C. If the o die reaches approximately 160 C, bo th channels will shut do wn, even if neither channel is in current limit. TS2026L 3 -7 2005/11 rev. A Pin Description Pin 1 2 Name ENA F L GA Description Switch A Enable (Input): Logic-compatible enable input. activ e low (L ) Fault Flag A (Outpu t): Active -low, open-drain outpu t. Indicate d over current or therma l shutdown conditions. Over current conditions mush last longer than tD in order to assert FLGA Fault Flag B (Outpu t): Active -low, open-drain outpu t. Indicate d over current or therma l shutdown conditions. Over current conditions mush last longer than tD in order to assert FLGB Switch B Enable (Input): Logic-compatible enable input. activ e-low (L) Switch B (Output) Ground Input: Sw itch and logic supply input Switch A (Output) 3 4 5 6 7 8 F L GB ENB OU T B GN D IN OU T A Test Circuit Timing Diagram Output R ise and Fall Time Active-Low Switch Times TS2026L 4 -7 2005/11 rev. A Function Description Input and Ou tput IN is the power supply connection to the logic circuitry and the drain of the output MOSFET. OUT is the source of the output M OSFET. In a typical circuit, current flows from IN to OUT towa rd the load. If V OUT is greate r than VIN, current will flow from OUT to IN, since the switch is bidirectional when enabled. The output MOSFET and drive r circuitry are also designed to allow the MOSFET source to be externally fo rced to a higher voltage than the dra in (VOUT > VIN ) when the switch is disabled. In th is situation, th e TS2026 prevents undesirable current flow from O UT to IN . Thermal Shu tdown Thermal shutdown is employed to protect the device from da mage should the die tempera ture exceed safe margins due mainly to short circuit faults. Each channel employs its own thermal sensor. Thermal shutdown shuts off the o output MOSFET and asserts the FLG output if the die temperature reaches 140 C and the overheated channel is in current lim it. The over channel w ill be shut off. Upon determining a thermal shutdown condition. The TS2026 w ill o automatically reset its output when the die tempe rature cools down to 120 C . The TS2026 output and FLG signal will continue to cycle on and off until the device is disabled o r the fault is removed. F igure 1. Depicts typical tim ing. Depending on PCB layout, package, ambient temperature , e tc., it may take several hundred milliseconds from the incidence of the fault to the output MOSFET being shut off. This time will be shortest in the case of dead short on the output. Power Diss ipation The device’s junction te mperature depends on several facto rs such as the load, P CB layout, ambien t temperature and package type. Equations that can be used to calculate power dissipation of each channel and junction temperature are found below. 2 PD = RDS(ON) x IOUT Total power dissipation of the device will be the summa tio n of PD for both channels. To relate this to junction temperature , the follow ing equation can be used: TJ = PD x θJA + TA Where: TJ = junction tempera ture TA = amb ient temperature θJA = is the thermal resistance of the package Current Sensing and Limiting The current-limit threshold is preset in ternally . The preset level prevents damage to the device and external load but still a llows a m inimum cu rrent o f 500mA to be delivered to th e load. The current-limit circuit senses a portion of the output MOSFET switch current. The current-sense resisto r s hown in the b lock diagram is virtual and has no voltage drop. The reaction to an over curren t condition varies with th ree scenarios. Switch Enable into Short-C ircuit If a switch is enabled into a heavy load or short-circuit, the switch immedia tely enters into a constant-current mode, reducing the output voltage. The FLG signal is asserted indic ating an over current condition. Switch Enable Applied to Enabled Output When a heavy load o r short-circuit is applied to an enabled switch, a la rge transient curren t may flow until the current limit c ircuitry responds. Once this occurs the device limits current to less than the short circuit current limit specification. Current-Limit Response-Ramped Load The TS2026 current-lim it p rofile exhibits a small fold back effect of about 200mA. Once this current-lim it threshold is exceeded the device switches into a constant current mode. It is important to note that the device will supply current up to the current-lim it threshold TS2026L 5 -7 2005/11 rev. A Function Description Fault Flag The FLG signal is an N-channel open-drain MOSFET output. FLG is asserted (active-low ) when either an over current or the rmal shutdown condition occurs. In the case of and ov er current condition, FLG w ill be asserted only a fter the flag response delay time, tD, has elapsed. This ensured that FLG is asserted only upon valid over current conditions and that erroneous error reporting is eliminated . For example, false over cu rrent condition can occur during hot plug event when a h ighly capacitive load is connected and causes a high transient inrush current that exceeds the current-limit threshold fo r up to 1ms. The FLG response delay time tD is typically 3ms. Undervoltage Lockout Undervoltage lockout (UVLO ) prevents the ou tput MOSFET from turn ing on until VIN exceeds approximately 2.5V. Undervoltage detection function only when the switch is enabled. Figure 1. TS2026L Fault Timing TS2026L 6 -7 2005/11 rev. A SOP-8 Mechanical Drawing SOP-8 DIMENSION DIM A B C D F G K M P R 0 MILLIMETERS MIN 4.80 3.80 1.35 0.35 0.40 0.10 o INCHES MIN 0.189 0.150 0.054 0.014 0.016 0.004 0 o MA X 5.00 4.00 1.75 0.49 1.25 0.25 7 o MA X 0.196 0.157 0.068 0.019 0.049 0.009 7 o 1.27 (typ) 0.05 (typ) 5.80 0.25 6.20 0.50 0.229 0.010 0.244 0.019 TS2026L 7 -7 2005/11 rev. A