TS824CX5ARF

TS823/824/825 Series Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset SOT-25 General Description The TS823/824/825 family allows the user to cus tomize the C PU monitoring func tion without any external components . The user has a large choice of reset voltage thresholds and output driver configurations, all of w hich ar e present ant the fac tory. Each wafer is trimmed to the customer ’s specifications . These circuits will ignore fast negative going tr ansients on Vdd. The state of the reset output is guaranteed to be correct dow n to 1V. After Vdd crosses above a fac tor y present threshold, the TS823/824/825 assert a reset signal. After a predeter mined time ( the “reset” interval) the res et is deasserted. If Vdd ever dr ops below the threshold voltage a reset is asserted immediately . In addition to a supply monitoring function the TS823/824/825 also monitor transitions at the watchdog (WD I) input. If a logic transition does not occur at the WD I pin within a certain time inter val (the “watchdog” interval) then a reset is asserted. The reset deasserts after the reset interval, as explained earlier. The TS823/824/825 can both assert a reset manually by pulling the MR input to ground, and the micro-power quiescent current make this family a natural for portable battery powered equipment. Features ● ● ● ● ● ● ● ● Precision monitoring of +3V, +3.3V and +5V power supply voltage Tight voltage threshold tolerance +/-1.5% Fully specified over temperature 210mS min. power-on reset pulse width 3uA( typ) supply current Guaranteed reset valid to Vdd = +1V Power supply trans ient immunity No external components Ordering Information Part No. Package Packi ng TS823C X5x RF SOT-25 3Kpcs / 7” Reel TS824C X5x RF SOT-25 3Kpcs / 7” Reel TS825C X5x RF SOT-25 3Kpcs / 7” Reel Note: x is the threshold voltage type, option as A : 4.63V B : 4.38V D : 3.08V E : 2.93V F : 2.63V G : 2.32V H : 2.19V Contac t factory for additional voltage option Pin Descriptions Function RESET ( Ac tive-Low) Gr o u n d Manual Reset (RESET) (Ac tive-High) Watchdog Input Supply Voltage ( Vdd) Applications ● ● ● ● ● ● Computers and Controllers Embedded Controllers Intelligent ins truments Critical uP monitor ing Portable / Battery powered equipment Automotive Systems TS823 1 2 3 4 5 TS824 1 2 3 4 5 TS825 1 2 4 3 5 Absolute Maximum Rating Parameter Supply Voltage Supply Voltage - R ecommended Operating Junction Temperature R ange Storage Temperature Range Thermal R esistance o Symbol Vdd Vdd TOP TSTG Θjc Maxi mum 6.0 0.9 ~ 5 - 4 0 ~ +1 2 5 - 6 5 ~ +1 5 0 256 Unit V V o C o C C/W S o Maximum Lead Temperature (260 C) TLEAD 10 Notes: Stress above the listed absolute rating may cause per manent damage to the device. 1/8 Version: B07 TS823/824/825 Series Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset Electrical Specifications (Ta = 25oC, unless otherwise noted) Parameter Input Supply Voltage Supply Current WDI and MR B unconnected TS823/824/825C X5A TS823/824/825C X5B TS823/824/825C X5D Reset Threshold TS823/824/825C X5E TS823/824/825C X5F TS823/824/825C X5G TS823/824/825C X5H RESET Output Voltage Low (RESET) Output Voltage High Vdd to Reset Delay Reset Ac tive Timeout Per iod Watchdog Timeout Period WDI Pulse Width WDI Input Threshold WDI Input Current MR Input Threshold MR Pulse Width MR N oise Immunity MR to Reset Delay MR Pull Up R esistance Input Supply Voltage Vdd = VTH x 1.2 WDI =0V WDI =Vdd = 5V Vdd=VTH x 1.2 VddVTH(MAX), ISOURCE=0.5mA Vdd =VTH - 100mV o o Ta=-40 C ~+85 C VOL VOH TD1 TD2 TWD TWDI WDIIL WDIIH IIL IIH MRIL MRIH TWMR Pulse width with no reset Vdd = VTH - 100mV Ta=-40 C ~+85 C o o Conditi ons Symbol Vdd Idd Mi n 1.0 -4.56 4.31 3.03 Ty p -3 4.63 4.38 3.08 2.93 2.63 2.32 2.19 --40 210 1760 ----8 8 ---100 500 --- Max 5.5 10 4.7 4.45 3.13 2.97 2.67 2.36 2.23 0.5 --280 2400 -0.7 -0.7 15 0.7 ----120 5.5 Unit V uA VTH 2.89 2.59 2.28 2.15 -0.8 Vdd -140 1120 50 -0.8 Vdd - 15 --0.8 Vdd 1 --80 1.0 V V V uS mS mS nS V V uA uA V V uS nS nS KΩ V TDMR VCC Detail Description Pin Function Pin N ame R es et GN D (Reset) MR Pin D escript ion Active Low Gr o u n d Active High This pin is ac tive low. Pulling this pin low to forces a r eset. After a low to high transition reset remains asserted for exac tly one reset timeout period. This pin is internally pulled high. If this function is unused then float this pin or tie it to Vdd. Watch Dog Input. Any transition on this pin will reset the Watch Dog timer. If this pin remains high or low for longer than the Watch Dog interval then a reset is asserted. Float or tri-s tate this pin to disable the Watch Dog feature. Positive power supply. A reset is asserted after this v oltage drops below a predeter mined level. After Vdd rises above that level reset remains asserted until the end of the reset timeout period. WD I Vdd 2/8 Version: B07 TS823/824/825 Series Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset Application Information The TS823/824/825 are designed to interface with the reset input of a microprocessor and to prevent C PU execution errors due to power up, power down, and other pow er supply errors. The TS823/824 also monitor the C PU health by checking for signal transitions form the CPU at the WD I input. Reset Output Active low reset outputs are denoted as R ESET, Active high reset output are denoted as (R ESET), A reset will be asserted if any of thr ee things happen: 1. Vdd drops below the thr eshold (Vth) 2. The MR pin is pulled low . 3. The WD I pin does not detect a trans ition w ithin the Watch Dog interval (TWD) The reset will remain asserted for the prescribed reset interval after : 1. Vdd rises above the threshold ( Vth) 2. MR goes high 3. The Watch D og timer have timed out causing the res et to assert. Manual Reset Input The TS823 and TS825 feature a manual reset featur e (MR). A logic low on the MR pin asser ts a reset. The reset remains asserted a long as the MR pin remains low . After the MR pin transitions to a high s tate the reset remains asserted for the prescribed reset interval ( TD2). The MR pin is internally pulled up to Vdd by a 100KΩ resistor. It is internally de-bounced to reject switching transients . The MR pin is ESD protected by diodes connected to Vdd and Gnd. So the MR pin should never be driven higher than Vdd or lower than Gnd. Watchdog Input The TS823 and TS824 are equipped with a watchdog input (WD I). If the microprocessor does not produce a v alid logic edge at the watchdog input (WD I) within the prescribed watchdog interval (TWD) then a reset asserts. The reset remains asserted for the required reset interval (TD2) . Ata the end of the reset interval the reset is deasser ted and the watchdog interval timer starts again fr om zero. If the watchdog input is left unconnected or is connected to a tri-stated buffer the watchdog function is disabled. As soon as the WD I input is driven either low or high the w atchdog function resumes with the watchdog timer set to zero. Watchdog Input C urrent The watchdog input pin ( WDI) typically sources/sinks 8uA when driven high or low. So from a power dissipation point of v iew the duty cycle of the wavefor m at WD I is unimpor tant. When the WD I pin is floating or tri-stated the pow er supply current fall to less than 3uA. Glitch Rejection The TS823/824/825 family w ill rejec t negative going tr ansients on the Vdd line to some extent. The s maller the duration of the transient the larger its amplitude may be without triggering a reset. The “Glitch Rejection” chart in the graphs section of this datasheet shows the relation between glitch amplitude and allowable glitch duration to avoid unintended resets . Accurate Output State at Low Vdd With Vdd voltage on the order of the MOS trans istor threshold (