TS8405P

PRELIMINARY DATA SHEET For information only TS8405P - Single P-Channel 1.8V Specified MicroSURF™ General Description Taiwan Semiconductor’s new low cost, state of the art MicroSURF™ lateral MOSFET process technology in chipscale bondwireless packaging minimizes PCB space and RDS(ON) plus provides an ultralow Qg X RDS(ON) figure of merit. Features • -4.9A, -12V RDS(ON) = 50mΩ at -4.5 Volts • -4.4A, -12V RDS(ON) = 70mΩ at -2.5 Volts • -4.0A, -12V RDS(ON) = 90mΩ at -1.8 Volts MicroSURF™ for Load Switching and PA Switch Patent Pending • Low profile package: less than 0.8mm height when mounted on PCB. • Occupies only 2.25 mm2 of PCB area. Less than 25% of the area of a SSOT-6. • Excellent thermal characteristics. • Lead free solder bumps available. D D S G Bump Side View Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID PD TJ, TSTG TA=25°C unless otherwise noted Ratings -12 +8 -4.9 -10 1.5 -55 to +150 Units V V A W ºC Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed Power Dissipation (Steady State) Operating and Storage Junction Temperature Range Thermal Characteristics RθJA RθJR Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Balls 1 85 12 °C/W 9/14/03 Rev5 PRELIMINARY DATA SHEET Electrical Characteristics TA=25°C unless otherwise specified TS8405P IDS S Zero Gate Voltage Drain Current Zero Gate Voltage Drain Current VDS =-12V, VGS =0V VDS =-12V, VGS =0V, T=70°C VGS =±8V, VDS =0V VDS =VGS , ID=-250µA VGS =-4.5V, ID=-1A VGS =-2.5V, ID=-1A VGS =-1.8V, ID=-1A VDS =-12V, VGS =0V, F=1MHZ VDS =-12V, VGS =0V, F=1MHZ VDS =-12V, VGS =0V, F=1MHZ VGS =-4.5V, ID=-1A, VDS =-6V IS =-1A, VGS =0V IS =-1A, VGS =0V, di/dt=100A/µs 800 250 100 9.0 -0.71 40 -0.7 -1 -5 ±100 µA µA nA V IGS S VGS (th) r Gate-Body Leakage Gate Threshold Voltage Drain-Source On-State Resistance 50 70 90 mΩ mΩ mΩ pF pF pF nC V ns DS (on ) Drain-Source On-State Resistance Drain-Source On-State Resistance Cis s Cos s Crs s Qg VS D trr Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Diode Forward Voltage Source-Drain Reverse Recovery Time 2 9/14/03 Rev5 TS8405P 3 9/14/03 Rev5 TS8405P 4 9/14/03 Rev5 TS8405P 5 9/14/03 Rev5 TS8405P 6 9/14/03 Rev5 TS8405P 7 9/14/03 Rev5 TS8405P 8 9/14/03 Rev5 TS8405P 9 9/14/03 Rev5 TS8405P 10 9/14/03 Rev5 TS8405P 11 9/14/03 Rev5 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout TS8405P Ø 0.30mm Solder Mask Ø ~ 0.40mm D G D 0.80mm S 0.27mm 0.80mm LAND PATTERN RECOMMENDATION D = Drain Pad S = Source Pad G = Gate Pad SILICON 0.80mm MAX 1.50mm 0.35mm 1.50mm 0.80mm EXXXX BACKSIDE VIEW (NO BUMP SIDE VIEW) Mark on backside of die E = 8405P Product Code XXXX = Lot Traceability Code Mark is located in lower right quadrant on top of Source pad. Gate pad is located in lower left quadrant. Bump Ø 0.37mm 0.80mm 0.35mm Bumps are Eutectic solder 63/37 Sn/Pb 11 9/14/03 Rev5