TSM2321

TSM2321 -20V P-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = - 20V RDS (on), Vgs @ -4.5V, Ids @ -3.2A = 65mΩ RDS (on), Vgs @ -2.5V, Ids @ -2.0A = 90mΩ Features Advanced trench process technology High density cell design for ultra low on-resistance Excellent thermal and electrical capabilities Compact and low profile SOT-23 package Block Diagram Ordering Information Part No. TSM2321CX Packing Tape & Reel Package SOT-23 Absolute Maximum Rating (Ta = 25 oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Maximum Power Dissipation Operating Junction Temperature Operating Junction and Storage Temperature Range Ta = 25 C Ta = 75 oC o Symbol VDS VGS ID IDM PD TJ TJ, TSTG Limit -20V ±10 -3.2 -11 1.25 0.8 +150 -55 to +150 Unit V V A A W o o C C Thermal Performance Parameter Lead Temperature (1/8” from case) Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t