TSM2N7002CX

TSM2N7002 60V N-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = 60V RDS (on), Vgs @ 10V, Ids @ 500mA = 7.5Ω RDS (on), Vgs @ 5V, Ids @ 50mA = 13.5Ω Features Advanced trench process technology High density cell design for low on-resistance High input impedance High speed switching No minority carrier storage time CMOS logic compatible input No secondary breakdown Compact and low profile SOT-23 package Block Diagram Ordering Information Part No. TSM2N7002CX Packing Tape & Reel Package SOT-23 Absolute Maximum Rating (Ta = 25oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Maximum Power Dissipation Ta = 25 C Ta > 25 C Operating Junction Temperature Operating Junction and Storage Temperature Range TJ TJ, TSTG o o Symbol VDS VGS ID IDM PD Limit 60 ± 20 115 800 225 1.8 +150 - 55 to +150 Unit V V mA mA mW MW/ C o o o C C Thermal Performance Parameter Lead Temperature (1/8” from case) Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t