TSM2N7002ED

TSM2N7002ED 50V Dual N-Channel Enhancement Mode MOSFET Pin assignment: 1. Source (2) 6. Drain (2) 2. Gate (2) 5. Gate (1) 3. Drain (1) 4. Source (1) VDS = 50V RDS (on), Vgs @ 10V, Ids @ 250mA = 3Ω RDS (on), Vgs @ 5V, Ids @ 50mA = 4Ω Features Dual N-channel in package. Advanced trench process technology High density cell design for ultra low on-resistance High input impedance High speed switching No minority carrier storage time CMOS logic compatible input No secondary breakdown Compact and low profile SOT-363 package Ordering Information Part No. TSM2N7002EDCU6 Packing Package T & R (3kpcs/Rell) SOT-363 Block Diagram Absolute Maximum Rating (Ta = 25oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Maximum Power Dissipation Ta = 25 oC Ta = 75 C Operating Junction Temperature Operating Junction and Storage Temperature Range TJ TJ, TSTG o Symbol VDS VGS ID IDM PD Limit 50 ± 20 250 1.0 200 150 +150 - 55 to +150 Unit V V mA A mW o o C C Thermal Performance Parameter Lead Temperature (1/8” from case) Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t