TSM5N50CZC0

T S M5 N 5 0 500V N-Channel Power MOSFET TO-220 Pin Definition: 1. Gate 2. Drain 3. Source PRODUCT SUMMARY VDS (V) 500 RDS(on)(Ω) 1.8 @ VGS =10V ID (A) 2.2 General Description The TSM5N50 N-Channel enhancement mode Power MOSFET is produced by planar s tripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resis tance, provide superior s witching perfor mance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supply, power factor correction, electronic lamp ballas t based on half bridge. Features ● ● ● ● ● Low gate charge typical @ 13nC Low Crss typical @ 8.5pF Fast Sw itching 100% avalanche tes ted Impr oved dv /dt capability Block Diagram Ordering Information Part No. TSM5N50CZ C0 Package TO-220 Packi ng 50pc s / T ube N-Channel MOSFET Absolute Maximum Rating (Ta = 25oC unless otherwise noted) Parameter Drain-Source Voltage Gate- Source Voltage Continuous Drain Current Pulsed Drain Current Continuous Source Current (D iode Conduc tion) Peak Diode Recovery (Note 2) Single Pulse Drain to Source Avalanche Energy (Note 3) Maximum Power Dissipation @ Ta = 25 C Operating Junction and Storage Temperature Range o Symbol VDS VGS ID IDM IS dv/dt EAS PD TJ, TSTG Limit 500 ± 30 4.5 18 4.5 4.5 300 85 - 55 t o + 150 Unit V V A A A V/ns mJ W o C Thermal Performance Parameter Thermal R esistance - Junction to Case Thermal R esistance - Junction to Ambient Notes: Surface mounted on FR4 board t ≤ 10sec 1/ 6 Symbol R ӨJ C R ӨJ A Limit 1.47 62.5 Unit o o C/W C/W Version: A07 T S M5 N 5 0 500V N-Channel Power MOSFET Electrical Specifications (Ta = 25oC unless otherwise noted) Parameter Conditi ons Symbol Mi n 500 -3.0 ----------------- Ty p -1.36 ---4 -13 3.4 6.4 470 75 8.5 13 55 25 35 215 1.26 Max -1.8 5.0 1 ± 100 -1.4 17 --610 95 11 35 120 60 80 --- Unit V Ω V uA nA S V Static Drain-Source Breakdown Voltage VGS = 0V, ID = 250uA BVDSS Drain-Source On-State R esistance VGS = 10V, ID = 2.2A RDS(ON) Gate Threshold Voltage VDS = VGS, ID = 250uA VGS(TH) Zero Gate Voltage Drain Current VDS = 500V, VGS = 0V IDSS Gate Body Leakage VGS = ±30V, VDS = 0V IGSS Forward Transconduc tance VDS = 50V, ID = 2.2A gf s Diode Forward Voltage IS = 4.5A, VGS = 0V VSD b Dynamic Total Gate Charge Qg VDS = 250V, ID = 4.5A, Gate- Source Charge Qgs VGS = 10V Gate-Drain C harge Qgd Input Capacitance Ciss VDS = 25V, VGS = 0V, Output Capacitance Coss f = 1.0MHz Reverse Trans fer C apacitance Crss c Switching Turn-On Delay Time td(on) Turn-On Rise Time VGS = 10V, ID = 4.5A, tr VDD = 250V, RG = 25Ω Turn-Off Delay Time td(off) Turn-Off Fall Time tf Reverse Recovery Time VGS = 0V, IS = 4.5A, tfr dIF/dt = 100A/us R ev er s e R ec ov er y C har ge Qf r Notes: 1. Pulse test: pulse w idth ≤300uS, duty cycle ≤2% 2. ISD