TSM7104DCS

TSM7104D 20V Dual P-Channel Enhancement Mode MOSFET Pin assignment: 1. Source 1 2. Gate 1 3. Source 2 4. Gate 2 5, 6. Drain 2 7, 8. Drain 1 VDS = - 20V RDS (on), Vgs @ - 4.5V, Ids @ - 2.3A =130mΩ RDS (on), Vgs @ - 2.5V, Ids @ - 2.0A =190mΩ Features Advanced trench process technology High density cell design for ultra low on-resistance Excellent thermal and electrical capabilities Surface mount Fast switching Block Diagram Ordering Information Part No. TSM7104DCS Packing Tape & Reel Package SOP-8 Absolute Maximum Rating (Ta = 25 oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @4.5V. Pulsed Drain Current, VGS @4.5V Maximum Power Dissipation Ta = 25 C Ta > 25 C Operating Junction Temperature Operating Junction and Storage Temperature Range TJ TJ, TSTG o o Symbol VDS VGS ID IDM PD Limit - 20V ±8 - 2.3 - 10 2 16 +150 - 55 to +150 Unit V V A A W mW/ C o o o C C Thermal Performance Parameter Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t