UM6552A

UM6522/A Versatile Interface Adap ter( VIA) Features . Two Shit b i-directional I/O ports n Two 16-bit programmable timer/counters m Serial data port n Single +5V power supply m TTL compatible except Port A n CMOS compatible peripheral Port A lines m E xpanded “handshake” capability allows positive control of data transfers between processor and peripheral devices n Latched input and output registers n 1 MHz and 2 MHz Operation General Description The UM6522/A Versatile Interface Adapter (VIA) is a very flexible l/O control device. In addition, this device contains a pair of very powerful 16.bit interval timers, a serlalto-parallel/parallel-to-serial shift register and input data latching on the peripheral ports. Expanded handshaking capability allows control of bi-directional data transfers between VIA’s in multiple processor Systems. Control of peripheral devices is handled primarily through two Shit b i-directional ports. Esch line tan be programmed as either an input or- an output. Several peripheral l/O lines tan be controlled directly from the interval timers for generating programmable frequency Square waves or for counting externally generated Pulses. To facilitate control of the many powerful features of this Chip, an interrupt flag register, an interrupt enable register and a pair of function control registers are provided. Pin Configuration Block Diagram “SS c PA0 c PA1 c 2 3 39 38 37 36 35 34 33 2 8 E $ ;: 30 29 28 27 26 25 24 23 22 21 PA2 r 4 PA3 c 5 PA4 c 6 PA5 c 7 PA6 c 8 PA7 [z PB0 c PB1 c 9 ‘O 11 13 14 15 16 17 16 19 20 ] CA1 ] CA2 -J RSO ] RSl ] RS2 ] RS3 ]RES 1 DO 1 D’ 1 D2 I] D3 2 D4 7 D5 7 PB2 [ ‘12 PB3 [ PB4 c PB5 [ D6 7 07 7 $2 7 CS1 Jcs2 PB6 c PB7 [I CB1 c CB2 c “cc c 5-18 GD UMC “Comments UM6522/A +8.0 VOLTS 1 +4v to +7v GND-2.0V to 0.5V GND-0.5V to Vcc +0.5V -65°c to +1 5o”c . . oOc to +70°c . . . . . ...AT!VE. A CTIVE EDGE 0 I 0 I i I INOEPENDENT INTERRUPT INPUT NcG EDGE 0 1 0 INPUT POSITIVE ACTIVE EDGE 011 INDEPENDENT INTERRUPT INPUT POS EDGE 1 0 0 HANDSHAKE OUTPUT 1 0 1 PULSE OUTPUT 1 1 0 LOW OUTPUT 1 1 1 HIGH OUTPUT CB1 INTERRUPT CONTROL- CA1 INTERRUPT CONTROL 0 = N EGATIVE ACTIVE EDGE 1 = POSITIVE ACTIVE EDGE CA2 CONTROL -~ 0 = NEGATIVE ACTIVE EDGE 1 = POSITIVE ACTIVE EDGE (SEE N OTE ACCOMPANYING FIGURE 251 Figure 14. CAI, CA2, CBI, CB2 Control Timer Operation Interval Timer, Tl, consists of two X-Bit latches and a 16-bit decrement at the $2 clock rate. Upon reaching “zero”, an interrupt flag will be set, and IRQ will go low if the interrupt decrements at the 42 c lock rate. Upon reaching “Zero” an interrupt flag will be set, and IRQ will go low if the interrupt is enabled. The timer will then disable any further interrupts, or (when programmed to) will automatically transfer the contents of the latches into the counter and begin to decrement again. In addition, the timer may be programmed to invert the output Signal on a peripheral 5-27 GD UMC UM6522/A Two bits are provided in the Auxiliary Control Register (bits 6 and 7) to allow selection of the Tl operating modes. The four possible modes are depicted in Figure 17. pin each t ime it “firnes-out.” Esch o f these modes is discussed separately below. The Tl counter is depicted in Figure 15 and the latches in Figure 16 Reg 4 - Timer 1 Low-Order Counter Reg 5 - Timer 1 High-Order Counter COUNT VALUE WRITE -8 BITS ARE LOA&l I N T O T l L O W - O R D E R L A T C H E S . CATCH C O N T E N T S A R E T R A N S F E R R E D I N T O L O W O R D E R C O U N T E R A T T H E TIME T H E H I G H O R D E R C O U N T E R IS LOADED (REG. 51. READ - 8 B I T S F R O M T l L O W - O R D E R C O U N T E R ARE T R A N S FERRED TO MPU. IN ADDITION. Tl INTERRUPT FLAG IS R ESET (BIT 6 IN INTERRUPT FLAG REGISTER). WRITE -6 BITS LOADED INTO ;, HIGt%ORDER LATCHES. ALSO, AT THIS T IME BOTH HIGH AND LOW-ORDER LATCHES ARE TRANSFERRED INTO THE Tl COUNTER. AND INITIATES COUNTDOWN Tl INTERRUPT FLAG IS A L S O RESET READ - 8 B ITS FROM Tl HIGH-ORDER COUNTER TRANSFERRED TO MPU. Figure 15. Tl Counter Registers Reg 6 - Timer 1 Low-Order Latches 1 2 4 Reg 7 - Timer 1 High-Order Latches 8 1 l- 16 COUNT VALUE COUNT VALLJE WRITE-6 B I T S A R E L O A D E D I N T O T l L O W - O R D E R L A T C H E S T H I S O P E R A T I O N IS N O D I F F E R E N T FOLLOWING A WRITE INTO REG 4 R E A D - 6 BITS FAOM Tl LOW-OADER L A T C H E S T R A N S F E R R E D T O MPU. UNLIKE AEG 4 OPERATION, THIS D O E S N C T CAUSE RESET OF Tl INTERRUPT F LAG. WRITE-6 B ITS LOADED INTO Tl HIGH-ORDER LATCHES. UNLIKE REG. 4 OPERATION. NO LATCH-TO-COUNTER TRANS FERS TAKE PLACE. READ- 6 BITS FROM Tl HIGH-ORDER LATCHES ARE TRANSFERRED TO MPU Figure 16. Tl Latch Registers Reg 11 - Auxiliary Control Register Figure 17. Auxiliary Control Register Note. The processor does not wfite directly to the Iow order counter (TlC-L). Instead. this half of the counter is loaded automatically from the low Order latch when the processor writes to the high Order counter In fact, it may not be necessary to write to the low Order counter in some applications since the timing Operation is triggered by writing to the high Order counter. 5-28 UM6522/A 42 JlJ-1 WRITE T I C - H OPERATION ” 00;;;;; (Tl, ONLY) Tl COUNT TZ COUNT I Figure 18. Timer 1 and Timer 2 One-Shot Mode Timing Timer 1 One-Shot Mode The interval timer one-shot mode allows generation of a Single interrupt for each Timer load Operation. In addition, Timer 1 tan be programmed to produce a Single negative pulse on PB7. To generate a Single interrupt ACR bits 6 and 7 must be “O”, then either TI L-L or TIC-L must be written with the low-Order count value. (A write to TIC-L is effectlvely a Write to TIL-L). Next, the high-order count value is written to TIC-H, (the value is simultaneously written into TIL-Hl, a nd TIL-L is transferred to TIC-L. Countdown begins on 42 following the write TIC-H and decrements at the 92 rate. Tl interrupt occurs when the counters resch “0”. Generation of a negative pulse on PB7 is done in the same manner, except ACR bit 7 must be a one. PB7 will go low after a Write TIC-H and go high again when the counters resch “0”. The Tl interrupt flag is res.% b y either writing TIC-H fstarting a new count) or b y reading TIC-L. Timing for the one-shot mode is illustrated in Figure 18. Timer 1 Free-Run Mode The most important advantage associated with the latches in Tl is the ability to produce a continuous series of evenly spaced interrupts and the ability to produce a Square wave on PB7 whose frequency is not affected by variations in the processor interrupt response time. This is a ccomplished in the “free-running” mode. In the free-running mode, the interrupt flag is set and the Signal o n PB7 is inverted each t ime the counter reaches Zero. However, instead of continuing to decrement from zero after a time-out, the timer automatically transfers the contents of the latch into the counter (16 bits) and continues to decrement from there. lt is not necessary to rewrite the timer to enable setting the interrupt flag on the next time-out. The interrupt flag tan be cleared by reading TIC-L, by writing directly into the flag as will be described later, or if a new count value is desired by a write to TIC-H. All interval timers in the UM6522/A are “re-triggerable”. Aewriting the counter will always re-initialize the time-out period. In fact, the time-out tan be prevented completely if the processor c ontinues to rewrite the timer before it reaches Zero. Timer 1 will operate in this manner if the processor w r i t e s i n t o t h e h i g h Order counter (TlC-Hl. However, by loading the latches only, the processor tan access the timer during each d own-counting Operation without affecting the time-out in process. I nstead, the data loaded into the latches will determine the length of’ the next time-out period. This capability is particularly valuable in the free-running mode with the output enabled. In this mode, the Signal on PB7 is inverted and the interrupt flag is set with each time-out. By responding to the interr u p t s w i t h new d ata for the latches, t he processor tan I determine the period of the next half cycle during each half cycle of the output Signal an PB7. In this manner, very complex waveforms tan be generated. Timing for the free-running mode is shown in Figure 19. PB7 OUTPUT Figure 19. Timer 1 Free-Run Mode Timing ’ Note. A precaution to take when using PB7 as the timer output concerns the data direction Register contents for PB7. 60th DDRB bit 7 and ACR bit 7 must be “1” for PB7 to function as the timer output. If either is a “0”. then PB7 functions as a normal output pin, controlled by ORB bit 7. 5-29 4!D UMC UM6522/A similar to Timer 1. In this mode, T2 provides a Single interrupt for each “write T2C- H” operatron. After timing out, (reading 0) the counters “roll-over” to all 1’s (FFFF,,) and continue decrementing, allowing the user to read them and determine how lang T2 interrupt has been set. However, setting of the interrupt flag will be disabled after initial time-out so that it will not be set by the counter continuing to decrement through Zero. The processor m ust rewrite T2C-H t o enable setting of the interrupt flag. T he interrupt flag is cleared by reading T2C-L or by writing T2CH. T iming for this Operation is shown in Figure 18. Reg 9 - Timer 2 High-Order Counter Timer 2 Operation Timer 2 operates as an interval timer (in the “oneshot” mode only), or as a counter for counting negative pulses on the PB6 peripheral pin. A Single control bit is provided in the Auxiliary Control Regkter to select between these two modes. This timer is comprised of a “write-only” low-Order latch (T2L- L), a “read-only” low-Order counter and a read/write high Order counter. The counter registers act as a 16-bit counter which decrements at the $2 rate. Figure 20 illustrates the T2 Counter Registers. Timer 2 One-Shot Mode As an interval timer, T2 operates in the “one-shot” mode Reg 8 - Timer 2 Low-Order Counter 1 2 4 8 16 32 64 128 COLJNT V ALUE - C O U N T VALUE 1 WRITE - 8 B ITS LOADED INTO T2 HIGH-ORDER COUNTER. ALSO, LOW-ORDER LATCHES TRANSFERRED TO LOW-ORDER COUNTER. IN ADDITION, T2 INTERRUPT FLAG IS RESET. R E A D - 8 B ITS FROM T2 HIGH-ORDER COUNTER TRANSFERAED T O MPU. WRITE - 8 B ITS LOADED INTO T2 LOW-ORDER LATCHES. READ -8 BITS FROM T2 LOW-ORDER COUNTER TRANSFERRED TO MPU. T2 INTERRUPT FLAG IS R ESET. Figure 20. T2 bunter Registers Timer 2 Pulse Counting Mode In the pulse counting mode, T2 serves primarily to count a predetermined number of negative-going pulses on PB6. This is accomplished by first loading a number into T2. Writing into T2CH clears the interrupt flag and allows the counter to decrement each time a pulse is applied to PB6. The interrupt flag will be set when T2 reaches Zero. At this time, the counter will continue to decrement with each pulse on PB6. However, it is necessary to rewrite T2C-H to allow the interrupt flag to be set on subsequent downcounting operations. Timing for this mode is shown in Figure 21. The pulse must be low on the leading edge of operating modes are located in the Auxiliary Control Register. Figure 22 illustrates the configuration of the SR data bitsand the SR control bits of the ACR. Figures and 24 illustrate the Operation of the various shift register modes. Interrupt Opetatlon Controlling interrupts within the UM6522/A involves three principal operations. These are flagging the interrupts, enabling interrupts and signaling to the processor that an active interrupt exists within the Chip. I nterrupt flags are set by interrupting conditions which exist within the chip or on inputs to the Chip. These flags normally remain set until the interrupt has been serviced. To determine the source of an interrupt, the microprocessor must examine these flags in Order from highest to lowest priority. This is accomplished by reading the flag register into the processor accumulator, shifting this register either right or left and then using conditional branch instructions to detect an active interrupt. 42. Shift Register Operation The Shift Register (SR) performs serial d ata transfer into and out of the CB2 pin under control of an internal modulo-8 counter. Shift pulses tan b e applied to the CB1 pin from an external Source or, with the proper mode selection, shift pulses g enerated internally will appear on the CB1 pin for controlling external devices. The control bits which select the various shift register 5-30 UMC Associated with each interrupt flag is an interrupt enable bit. This tan be set or cleared by the processor to enable interrupting the processor from the corresponding interrupt flag. If an interrupt flag is set to a logic “1” byan interrupting condition, and the corresponding interrupt enable bit is set to a “l”, the Interrupt Request Output (m) will go low. IRQ is an “open-collector” o u t p u t which tan b e wire-ORed to other devices in the System to interrupt the WRITE TZC-H OPERATION PE6 INPUT ~ IRQ OUTPUT N I N-l UMSSZZ/A processor. In the UM6522/A, all the interrupt flags are contained in one register. In addition, bit 7 of this register will be read as a logic “1” when an interrupt exists within the Chip. This allows very convenient polling of several devices within a System to locate the Source of an interrupt. I N-2 l{ IO Figure 21. Timer 2 Pulse Counting Mode Reg 10 - Shift Register Reg IO - H Reg 11 - Auxiliary Cuntrol Register SHIFT REGISTER MODE CONTROL SHIFT REGISTER BITS NOTES: 1. WHEN SHIFTING OUT. BIT 7 IS T HE FIRST BIT OUT AND SIMULTANEOUSLY IS R OTATED BACK BIT 0 AND SHIFTED TOWARDS BIT 7. 2. WHEN SHIFTING IN. BITS INITIALLY ENTER BIT 0 AND ARE SHIFTED TOWARDS BIT 7. SHIFT OUT UNOER C Figure 22. SR and ACR Control Bits . SR Disabled (000) The 000 mode is used to disable the Shift Register. In this mode the microprocessor tan wrlte or read the SR, but the shifting operating is disabled and Operation of CB1 and CB2 is controlled by the appropriate bits in the Peripheral Control Register (PCR). I n this mode the SR Interrupt Flag is disabled (held to a logic “0”). Shift in Under Cuntrol of T2 (001) In the 001 mode the shifting rate is controlled by the low Order 8 b its of “T2”. Shift Pulses are generated on the CB1 Pin to control shifting in external devices. The time between transitions of this output clock is a function of the System clock period and the contents of the low Order T2 latch (N). The shifting Operation is triggered by writing or reading the shift register. Data is shifted first into the low Order bit of SR and is then shifted into the next higher Order bit of the shift register on the negative-going edge of each clock pulse. The input data should Change b efore the positive-going edge of the CB1 clock pulse. This data is shifted into the shift register during the 42 clock cycle following the positive-going edge of the CB1 clock pulse. After 8 CB1 clock pulses, t he shift register interrupt flag will be set and IRQ will go low. WRITE OR READ SHIFT REG. CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA @ UMC UMSSZZ/A writing the Shift Register. Data is shifted first into bit 0 and is then shifted into the next higher Order bit of the shift register on the trailing edge of each 42 clock pulse. After 8 clock pulses, t he shift register interrupt flag will be set, and the output clock pulses o n CB1 will stop. Shift in Under Control of $2 (010) In mode 010 the shift rate is a direct function of the System clock frequency. CB1 becomes an output which generates shift pulses for controlling external devices. Timer 2 operates as an independent interval timer and has no effect on SR. The shifting Operation is trlggered by reading or REAO SR OPERATION CB1 O UTPUT SHIFT CLOCK CB2 INPUT DATA Figure 23-2 Shift Register Input Modes Shift in Under C o n t r o l o f E x t e r n a t CB1 Glock (Oll) In mode Oll CB1 becomes an input. This allows an external device to load the shift register at its own Pace. The shift register counter will interrupt the processor each time 8 bits have been shifted in. However, the shift register counter does not stop the shifting Operation; it acts simply as a pulse counter. Reading or writing the Shift Register resets the Interrupt flag and initializes the SR counter to count another 8 pulses. Note that the data is shifted durrng the first System clock cycle following the positive-going edge of the CB1 shift pulse. For this reason, data must be held stable during the first full cycle after CB1 goes high. CB1 OUTPUT SHIFT CLOCK Figure 23-3 Shift Register Input Modes Shift Out Free-Running at T2 Rate (1001 Mode 100 is very similar to mode 101 in which the shift rate is set by T2. However, in mode 100 the SR Counter does not stop the shift Operation. Since S hift Register bit 7 (SR7) is circulated back into bit 0, the 8 bits loaded into the shift register will be clocked onto CR2 repeatedly. In this mode the shift register counter is disabled, and IRQ is never Set. WRITE SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA Figure 24-1 Shift Register Output Modes 5-32 GD UMC .- UMSSZZ/A generated on CB1 to control shifting in external devices. After the 8 shift pulses, s hifting is disabled, the SR Interrupt Flag is set and CB2 remains at the last data level. Shift Out Under Control of T2 (1011 In mode 101 the shift rate is controlled by TZ (as in the However, with each r ead or write of previous model. the shift register the SR Counter is reset and 8 bits are shifted onto CB2. At the same time, 8 shift pulses are $2 CLOCK WRITE SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA IRQ Figure 24-2 Shift Register Output Modes Shift Out Under Control of 9 2 (1 IO) In mode 110, the shift rate is controlled by the $2 System clock. WRITE SR OPERATION CB1 OUTPUT SHIFT CLOCK CB2 INPUT DATA IRQ Figure 24-3 Shift Register Output Modes Shift Out Under Control of External CB1 Glock (111) In mode 111, shifting is controlled by pulses a pplied to the CB1 pin by an external device. The SR counter sets the SR Interrupt flag each t ime it counts 8 pulses b ut it does not disable the shrfting function. Esch t ime the microorocesor writes or reads the shift register, the SR Interrupt flag is reset and the SR counter is initialized to begin counting the next 8 shift pulses on pin GBl. After 8 shift pulses, t he interrupt flag is set. The microprocessor tan then load the shift register with the next byte of data. dJ2 WRITE SR OPERATION _ SHIFT CLOCK CB2 OUTPUT IRQ Figure 24-4 Shift Register Output Modes @ UMC UM6522/A tan Set or clear s elected bits in this register to facilitate controlling individual interrupts without affecting others. This is accomplished by writing to address 1110 (IER address). If bit 7 of the data placed on the System d ata bus during this write Operation is a “O”, each “1 ” in bits 6 through 0 clears the corresponding bit in the Interrupt Enable Register. For each “zero” in bits 6 through 0, the corresponding bit is unaffected. Setting selected bits in the Interrupt Enable Register is accomplished by writing to the same address with bit 7 in the data word set to a logic “1”. In this case, each “1” in bits 6 through 0 will set the corresponding bit. For each “Zero”, the corresponding bit will be unaffected. The individual control of the setting and Clearing o perations allows very convenient control of the interrupts during System Operation. In addition to setting and Clearing IER bits, the processor tan read the contents of this register by placing the proper address on the register select and chip select inputs with the Rmline high. Bit 7 will be read as a logic “1 ” The Interrupt Flag Register (IFR) and Interrupt Enable Register (IERI are depicted in Figures 25 and 26, respectively. The IFR may be read directly by the processor. In addition, individual flag bits may be cleared by writing a “1” into the appropriate bit of the IFR. When the proper chip select and register Signals are applied to the Chip, the contents of this register are placrxf on the data bus. Bit 7 indicates the Status of the IRQ output. This bit corresponds t o the logic function. IRQ = IFR6 x IER6 + IFR5 x IER5 + IFR4 x IER4 + IFR3 x IER3 + IFR2 x IER2 + IFRl x IERl + I FRO x IERO. N ote: X = l o g i c AND, += Logic OR. T h e IFR bit 7 is not a flag. Therefore, this bit is not directly cleared by writing a logic “1” into it, lt tan only be cleared by Clearing all the flags in the register or by disabling all the active interrupts as discussed in the next section. For each interrupt flag in IFR, there is a corresponding bit in the Interrupt Enable Register. The System processor Reg 13 - Interrupt Flag Register Reg 14 - Interrupt Enable Register SET BY CLEAAEO BY CA1 . IF THE CA2KB2 C ONTROL IN THE PCR IS S E L E C T E D A S “INDEPENDENT” I NTERRUPT INPUT, THEN READING OR W R I T I N G T H E O U T P U T R E G I S T E R ORA/ORB W I L L N O T C L E A A T H E F L A G B I T . INSTEAD. T H E B I T M U S T B E C L E A A E D B Y W R I T I N G I N T O T H E IFR. A S DESCRIBED PREVIOUSLY, Notes: 1 . I F B I T 7 ISA”O”,THEN EACH”1”INBlT.S0.6DISABLESTHE CORRESPONDING INTERRUPT. 2. IF BIT 7 IS A “l”,THEN EACH “1” IN BITSO-6 E N A B L E S T H E COARESPONDING INTERRUPT. 3. IF A READ OF THIS REGISTER IS D ONE, BIT 7 WILL BE “1” A N D A L L O T H E R B I T S W I L L R E F L E C T THEIR ENABLEI DISABLE STATE. Figure 25. Interrupt Flag Register (IFRI Figure 26. Interrupt Enable Register (IER) Ordering Information Part Number UM6522 UM6522A Frequency 1 MHz 2 MHz Package 40L DIP 40L DIP 5-34