CHR3694-QDG

CHR3694-QDG RoHS COMPLIANT 37-40GHz Integrated Down converter GaAs Monolithic Microwave IC in SMD package Description The CHR3694-QDG is a multifunction chip, which integrates a balanced cold FET mixer, a time two multiplier, and a RF LNA including gain control. It is designed for a wide range of applications, typically commercial communication systems. The circuit is manufactured with a pHEMT process, 0.25µm gate length, via holes through the substrate and air bridges. It is available in lead-free SMD package. A mirror version versus RF & LO access is available as CHR3794-QDG. Conversion gain (Sup. Mode) @ IF=2GHz 20 18 16 14 12 10 8 6 4 2 0 36 UMS R3694 YYWW Main Features ■ Broadband performance 37-40GHz ■ 12dB Gain ■ 15dBc Image Frequency Rejection ■ -5dBm IIP3 ■ 4dB Gain control ■ DC power consumption: 4V, 150mA ■ 24L-QFN4x4 ■ ESD protected ■ MSL Level 1 Conversion Gain (dB) Gain @ 0V Gain @ -2V 37 38 39 40 41 RF frequency (GHz) Main Characteristics Tamb = +25° VDL= VDX= 4V C, Symbol FRF FLO FIF G Parameter RF frequency range LO frequency range IF frequency range Conversion gain @ VGC=-2V Conversion gain @ VGC=0V Min 37 17.5 DC 8 11 10 14 Typ Max 40 21 3.5 Unit GHz GHz GHz dB dB ESD Protections: Electrostatic discharge sensitive device observe handling precautions! Electrical Characteristics Ref. : DSCHA3694-QDG9077 - 18 Mar 09 1/18 Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Route Départementale 128 - BP46 - 91401 Orsay Cedex France Tel.: +33 (0) 1 69 33 03 08 - Fax: +33 (0) 1 69 33 03 09 CHR3694-QDG Symbol FRF FLO FIF G Parameter RF frequency range LO frequency range IF frequency range Conversion gain @ VGC = -2V Conversion gain @ VGC = 0V PLO IFR NF LO Input power Image Frequency Rejection (1) Noise Figure @ VGC = -2V Noise Figure @ VGC = 0V IIP3 LO RL RF RL Gc Input IP3 Input LO Return Loss Input RF Return Loss Gain control range 37-40GHz Down Converter Tamb= +25° VDL= VDX= 4V, Typical VGX = -0.9V & VG M= -0.7V C, Min 37 17.5 DC 8 11 10 14 1 13 15 5 4.5 -5 -10 -4 4 4 -2 100 110 140 150 0 180 190 -8 -3 6.5 6 Typ Max 40 21 3.5 Unit GHz GHz GHz dB dB dBm dBc dB dB dBm dB dB dB V V mA mA VDL,VDX Drain bias voltage VGC Idl + Idx Gain control voltage (2) Bias current @ VGC = -2V (3) Bias current @ VGC = 0V (3) (1) With external I/Q 90° hybrid coupler (2) Idl=50mA@VGC=-2V, Idl= 60mA@VGC=0V (3) Typically, Idl=60mA@VGC=0V, Idx=90mA These values are representative of onboard measurements as defined on the drawing at page 16 for CHR3694-QDG and page 17 for CHR3794-QDG. Ref. : DSCHA3694-QDG9077 - 18 Mar 09 2/18 Specifications subject to change without notice Route Départementale 128, BP46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0) 1 69 33 03 08 - Fax: +33 (0) 1 69 33 03 09 37-40GHz Down Converter Absolute Maximum Ratings (1) Tamb = +25° C Symbol VDL,VDX Idl + Idx VGM,VGX VGC P_RF P_LO Tch Ta Tstg Parameter Maximum drain bias voltage Maximum drain bias current Gate bias voltage Control gain voltage Maximum RF input power Maximum LO input power Maximum channel temperature Operating temperature range Storage temperature range CHR3694-QDG Values 4.5 200 -2.0 to +0 -3.0 to +4 10 10 175 -40 to +85 -55 to +125 Unit V mA V V dBm dBm ° C ° C ° C (1) Operation of this device above anyone of these paramaters may cause permanent damage. Ref.: DSCHA3694-QDG9077 - 18 Mar 09 3/18 Specifications subject to change without notice Route Départementale 128, BP46 - 91401 ORSAY Cedex - FRANCE Tel.: +33 (0) 1 69 33 03 08 - Fax: +33 (0) 1 69 33 03 09 CHR3694-QDG Device thermal performances 37-40GHz Down Converter All the figures given in this section are obtained assuming that the QFN device is cooled down only by conduction through the package thermal pad (no convection mode considered). The temperature is monitored at the package back-side interface (Tcase) as shown below. The system maximum temperature must be adjusted in order to guarantee that Tcase remains below than the maximum value specified in the next table. So, the system PCB must be designed to comply with this requirement. A derating must be applied on the dissipated power if the Tcase temperature can not be maintained below than the maximum temperature specified (see the curve Pdiss. Max) in order to guarantee the nominal device life time (MTTF). DEVICE THERMAL SPECIFICATION : CHR3694-QDG Max. junction temperature (Tj max) : 144 ° C Max. continuous dissipated power @ Tcase= 85 °C : 0,6 W (1) => Pdiss derating above Tcase = 85 °C : 10 mW/° C (2) Junction-Case thermal resistance (Rth J-C) :